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P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/write_data_fifo/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/simulation/fg_tb_rng.vhd | 54 | 3878 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_3/complete/issueque.vhd | 1 | 52631 | -------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre,Prasanjeet Das
-- Company : University of Southern California
-- Updated : 03/15/2010, 07/13/2010
-- TASK : Complete the seven TODO sections
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-- This is the code for the integer issue queue, the codes for
-- Multiplier queue and divider queue are provided separately
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque is
port (
-- Global Clk and dispatch Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Output of LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
Iss_Lsb : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit (ALU)
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque;
-- Architecture
architecture behav of issueque is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --TAG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --REG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_32 is array(0 to 7) of std_logic_vector(31 downto 0) ; --BRANCHADDR
type array_8_16 is array(0 to 7) of std_logic_vector(15 downto 0) ; --IMMEDIATEADDR
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelectEmpty : std_logic_vector(7 downto 0);
signal OutSelectJRrstemp : std_logic_vector(7 downto 0);
signal OutSelectJRrs : std_logic_vector(2 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
signal IssuedRdPhyAddr : std_logic_vector(5 downto 0);
SIGNAL IssuequeBranchPredict : array_8_1;
SIGNAL IssuequeJR : array_8_1;
SIGNAL IssuequeJRrs : array_8_1;
SIGNAL IssuequeJAL : array_8_1;
SIGNAL IssuequeBranch : array_8_1;
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeBranchAddr : array_8_32;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeBranchPCBits : array_8_3;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
SIGNAL IssuequeImmediate : array_8_16;
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL EnJRrstemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL IssuedRegWrite : std_logic;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
--###############################################################################################
-- TODO 1: Generate the IssuequeReadyTemp signal which is asserted when
--################################################################################################
-- For anyone of the 8 entries in the issue queue
-- NOTE: where [i] is from 0 to 7
-- The instruction [i] is valid and
-- instruction [i] is JAL or (JR with Rs register ready) or (JRrs with Rs register ready) or other int type instructions with both Rs register and Rt register ready
IssuequeReadyTemp <= OutSelecttemp(0) or OutSelecttemp(1) or OutSelecttemp (2) or OutSelecttemp(3) or
OutSelecttemp(4) or OutSelecttemp(5) or OutSelecttemp (6) or OutSelecttemp(7);
IssInt_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--##################################################################################################
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issuing an instruction then the issueque is not full otherwise
-- issueque is full if all the eight entries are valid
--***********************************************************************************
--###############################################################################################
-- TODO 2: Generate the Full control signal
--################################################################################################
process ( IssuequeInstrValReg ,Iss_Int ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Int = '1' ) then
IssuequefullTemp_Upper <= '0' ; --Fill in the initial values of these two signals.
IssuequefullTemp_Lower <= IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_IntQueueFull <= IssuequefullTemp_Upper and IssuequefullTemp_Lower; --Complete the right hand side of the expression
--##################################################################################################
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
--###############################################################################################
-- TODO 3: Generate the Nearly Full control signal
--################################################################################################
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_IntQueueTwoOrMoreVacant <= UpperHalf_Has_Two_or_More_vacant or LowerHalf_Has_Two_or_More_vacant or
(not (IssuequefullTemp_Upper) and not (IssuequefullTemp_Lower)) ;
-- NOTE : Two or more vacant only if
-- (a) UpperHalf Has Two or More vacant
-- (b) LowerHalf Has Two or More vacant
-- (c) Identify the third case when you need to deal with both the halfs simultaneoulsy
-- i.e) atleast one slot vacant in lower half and atleast one slot vacant in upper half
------------------ Done Generating Full and Nearly Full Condition -------------------------------
--##################################################################################################
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and (IssuequeJAL(I) or(IssuequeRsReadyReg(I) and (IssuequeRtReadyReg(I) or IssuequeJR(I) or IssuequeJRrs(I))))) ; -- this has the priority in being issued
OutSelectJRrstemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeJRrs(I)) ;
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
--***************************************************************************************
-- This process generates to give priority to JRrs instruction in the issue queue.
-- the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelectJRrstemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelectJRrstemp(0) = '1' ) then
OutSelectJRrs <= "000";
else
if ( OutSelectJRrstemp(1) = '1' ) then
OutSelectJRrs <= "001";
else
if ( OutSelectJRrstemp(2) = '1') then
OutSelectJRrs <= "010";
else
if ( OutSelectJRrstemp(3) = '1') then
OutSelectJRrs <= "011";
else
if ( OutSelectJRrstemp(4) = '1') then
OutSelectJRrs <= "100";
else
if ( OutSelectJRrstemp(5) = '1') then
OutSelectJRrs <= "101";
else
if ( OutSelectJRrstemp(6) = '1') then
OutSelectJRrs <= "110";
else
OutSelectJRrs <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
process ( OutSelectJRrs , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelectJRrs) is
when "000" => EnJRrstemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => EnJRrstemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => EnJRrstemp <= "11111100" ;
when "011" => EnJRrstemp <= "11111000" ;
when "100" => EnJRrstemp <= "11110000" ;
when "101" => EnJRrstemp <= "11100000" ;
when "110" => EnJRrstemp <= "11000000" ;
when others => EnJRrstemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
EnJRrstemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
EnJRrstemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
EnJRrstemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
EnJRrstemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
EnJRrstemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= EnJRrstemp when (OutSelectJRrstemp /= "00000000") else Entemp; -- To given JRrs priority
OutSelect_result <= OutSelectJRrs when (OutSelectJRrstemp /= "00000000") else OutSelect; -- To given JRrs priority
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 4: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= unsigned(IssuequeRobTag(0)) - unsigned(Rob_TopPtr);
Buffer1Depth <= unsigned(IssuequeRobTag(1)) - unsigned(Rob_TopPtr);
Buffer2Depth <= unsigned(IssuequeRobTag(2)) - unsigned(Rob_TopPtr);
Buffer3Depth <= unsigned(IssuequeRobTag(3)) - unsigned(Rob_TopPtr);
Buffer4Depth <= unsigned(IssuequeRobTag(4)) - unsigned(Rob_TopPtr);
Buffer5Depth <= unsigned(IssuequeRobTag(5)) - unsigned(Rob_TopPtr);
Buffer6Depth <= unsigned(IssuequeRobTag(6)) - unsigned(Rob_TopPtr);
Buffer7Depth <= unsigned(IssuequeRobTag(7)) - unsigned(Rob_TopPtr);
--################################################################################################
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
--###############################################################################################
-- TODO 5: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= Flush(1); --Hint: Take into account the shift mechanism so is it i or i+1 or i - 1?
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= Flush(2);
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= Flush(3);
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= Flush(4);
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= Flush(5);
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= Flush(6);
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= Flush(7);
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--###############################################################################################
-- TODO 6: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction being issued for ALU Queue, load - store queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit and do the forwarding if necessary.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Lsbuf_RdWrite, Iss_Lsb, IssuequeRegWrite , IssuequeInstrValReg, IssuequeRtReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
--###############################################################################################
-- TODO 7: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for load - store queue, ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Iss_Lsb, Lsbuf_RdWrite,IssuequeInstrValReg, IssuequeRsReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or(IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
IssuequeRsReadyReg <= (others => '0');
IssuequeRtReadyReg <= (others => '0');
IssuequeJR <= (others => '0');
IssuequeJRrs <= (others => '0');
IssuequeJAL <= (others => '0');
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
-- end if;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
IssuequeBranchPredict(I) <= IssuequeBranchPredict(I + 1);
IssuequeBranch(I) <= IssuequeBranch(I + 1);
IssuequeBranchAddr(I) <= IssuequeBranchAddr(I + 1);
IssuequeBranchPCBits(I) <= IssuequeBranchPCBits(I + 1);
IssuequeJR(I) <= IssuequeJR(I + 1);
IssuequeJRrs(I) <= IssuequeJRrs(I + 1);
IssuequeJAL(I) <= IssuequeJAL(I + 1);
IssuequeImmediate(I) <= IssuequeImmediate(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
---If can be removed ---
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeBranchPredict(7) <= Dis_BranchPredict;
IssuequeBranch(7) <= Dis_Branch;
IssuequeBranchAddr(7) <= Dis_BranchOtherAddr;
IssuequeBranchPCBits(7) <= Dis_BranchPCBits;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
IssuequeJR(7) <= Dis_Jr31Inst;
IssuequeJRrs(7) <= Dis_JrRsInst;
IssuequeJAL(7) <= Dis_JalInst;
IssuequeImmediate(7) <= Dis_Immediate;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrAlu <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrAlu <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRdPhyAddr <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRegWrite <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RdPhyAddrAlu <= IssuedRdPhyAddr;
Iss_OpcodeAlu <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagAlu <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RegWriteAlu <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchPredictAlu <= IssuequeBranchPredict(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAlu <= IssuequeBranch(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAddrAlu <= IssuequeBranchAddr(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchUptAddrAlu <= IssuequeBranchPCBits(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrInstAlu <= IssuequeJR(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JalInstAlu <= IssuequeJAL(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrRsInstAlu <= IssuequeJrRs(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_ImmediateAlu <= IssuequeImmediate(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_off
Iss_instructionAlu <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO/simulation/fg_tb_pctrl.vhd | 6 | 18528 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/spy_tb/top_tb_withBPBComp_r1.vhd | 1 | 6813 | -------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Branch Prediction Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_off
--use reverseAssemblyFunctionPkg.all; --modified by sabya - not needed in top!
-- synopsys translate_on
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_ROB of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden BPB)
signal Bpb_BranchPrediction_gold :std_logic;
-- Signals for the student's DUT (BPB)
signal Resetb :std_logic;
signal Dis_CdbUpdBranch :std_logic;
signal Dis_CdbUpdBranchAddr :std_logic_vector(2 downto 0);
signal Dis_CdbBranchOutcome :std_logic;
signal Bpb_BranchPrediction :std_logic;
signal Dis_BpbBranchPCBits :std_logic_vector(2 downto 0) ;
signal Dis_BpbBranch :std_logic;
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component bpb
port (
Clk : in std_logic;
Resetb : in std_logic;
Dis_CdbUpdBranch : in std_logic;
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);
Dis_CdbBranchOutcome : in std_logic;
Bpb_BranchPrediction : out std_logic;
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;
Dis_BpbBranch : in std_logic
);
end component bpb;
for BPB_UUT: bpb use entity work.bpb(behv);
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
BPB_UUT: bpb
port map (
Clk => Clk,
Resetb => Resetb,
Dis_CdbUpdBranch=>Dis_CdbUpdBranch,
Dis_CdbUpdBranchAddr=>Dis_CdbUpdBranchAddr,
Dis_CdbBranchOutcome=>Dis_CdbBranchOutcome,
Bpb_BranchPrediction=>Bpb_BranchPrediction,
Dis_BpbBranchPCBits=>Dis_BpbBranchPCBits,
Dis_BpbBranch=>Dis_BpbBranch
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of Branch Prediction Buffer only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Bpb_BranchPrediction_gold /= Bpb_BranchPrediction) then
write (my_outline, string'("ERROR! Bpb_BranchPrediction of TEST does not match Bpb_BranchPrediction_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/Dis_CdbUpdBranch","Dis_CdbUpdBranch",1,1);
enable_signal_spy("/UUT/Dis_CdbUpdBranch","Dis_CdbUpdBranch",0);
init_signal_spy("/UUT/Dis_CdbUpdBranchAddr","Dis_CdbUpdBranchAddr",1,1);
enable_signal_spy("/UUT/Dis_CdbUpdBranchAddr","Dis_CdbUpdBranchAddr",0);
init_signal_spy("/UUT/Dis_CdbBranchOutcome","Dis_CdbBranchOutcome",1,1);
enable_signal_spy("/UUT/Dis_CdbBranchOutcome","Dis_CdbBranchOutcome",0);
init_signal_spy("/UUT/Dis_BpbBranchPCBits","Dis_BpbBranchPCBits",1,1);
enable_signal_spy("/UUT/Dis_BpbBranchPCBits","Dis_BpbBranchPCBits",0);
init_signal_spy("/UUT/Dis_BpbBranch","Dis_BpbBranch",1,1);
enable_signal_spy("/UUT/Dis_BpbBranch","Dis_BpbBranch",0);
--outputs--
init_signal_spy("/UUT/Bpb_BranchPrediction","Bpb_BranchPrediction_gold",1,1);
enable_signal_spy("/UUT/Bpb_BranchPrediction","Bpb_BranchPrediction_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_ROB;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/controller_command_fifo/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/GC_fifo/simulation/fg_tb_pctrl.vhd | 20 | 15357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_data_rec_fifo/simulation/fg_tb_top.vhd | 6 | 6307 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RECV_REQ_QUEUE/simulation/fg_tb_synth.vhd | 1 | 10490 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RECV_REQ_QUEUE_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/Cfc_withBRAM.vhd | 1 | 21112 | -------------------------------------------------------------------------------
--
-- Design : CFC Unit
-- Project : Tomasulo Processor
-- Entity : CFC
-- Author : Rajat Shah
-- Company : University of Southern California
-- Last Updated : April 15th, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end cfc;
architecture cfc_arch of cfc is
--Signal declaration for 8 copies of checkpoints - Each 32 deep and 6 bit wide
type cfc_checkpoint_type is array(0 to 255) of std_logic_vector(5 downto 0);
signal Cfc_RsList, Cfc_RtList, Cfc_RdList : cfc_checkpoint_type; --3 BRAM, each containing flattened 8 tables
--Signal declaration for committed checkpoint (Retirement RAT) - 32 deep and 6 bit wide
type committed_type is array(0 to 31) of std_logic_vector(5 downto 0);
signal Committed_RsList, Committed_RtList, Committed_RdList : committed_type :=(
"000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111"); -- 3 copies of committed list initialize to 0 to 31
--Signal declaration for 8 copies of Dirty Flag Array(DFA) validating each checkpoints - Each 32 deep and 1 bit wide
type dfa_checkpoint_type is array(0 to 31) of std_logic;
type dfa_array_type is array (0 to 7) of dfa_checkpoint_type;
signal Dfa_List : dfa_array_type;
type checkpoint_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Checkpoint_TagArray: checkpoint_tag_type; --8 deep and 5 bit wide array for storing ROB tag of checkpointed branch instructions
type Frl_HeadPtrArray_type is array (0 to 7) of std_logic_vector (4 downto 0);
signal Frl_HeadPtrArray: Frl_HeadPtrArray_type;
type depth_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Depth_Array: depth_tag_type;
type Cfc_Valid_Array_type is array (0 to 7) of std_logic;
signal Cfc_ValidArray: Cfc_Valid_Array_type;
signal Full, Empty : std_logic; --flag indicating if all 8 checkpoints are used or empty
signal Head_Pointer, Tail_Pointer: std_logic_vector(2 downto 0); --Head Pointer indicates active checkpoint while tail pointer indicates oldest uncommitted branch
signal Checkpoint_MatchArray: std_logic_vector (7 downto 0); --Array indicating if the instruction on CDB matches any checkpointed branch
signal DFA_RsValid, DFA_RtValid, DFA_RdValid: std_logic;
signal Cfc_RsList_temp, Cfc_RtList_temp, Cfc_RdList_temp: std_logic_vector (5 downto 0);
signal Committed_RsList_temp, Committed_RtList_temp, Committed_RdList_temp: std_logic_vector (5 downto 0);
signal Next_Head_Pointer: std_logic_vector (2 downto 0); --Temporary Head_pointer generated during CDB Flush
begin
Depth_Array(0) <= Checkpoint_TagArray(0) - Rob_TopPtr; -- std_logic_vector is treated as unsigned because of library declaration IEEE_STD_LOGIC_UNSIGNED
Depth_Array(1) <= Checkpoint_TagArray(1) - Rob_TopPtr;
Depth_Array(2) <= Checkpoint_TagArray(2) - Rob_TopPtr;
Depth_Array(3) <= Checkpoint_TagArray(3) - Rob_TopPtr;
Depth_Array(4) <= Checkpoint_TagArray(4) - Rob_TopPtr;
Depth_Array(5) <= Checkpoint_TagArray(5) - Rob_TopPtr;
Depth_Array(6) <= Checkpoint_TagArray(6) - Rob_TopPtr;
Depth_Array(7) <= Checkpoint_TagArray(7) - Rob_TopPtr;
--Combinational assignment determining if the instruction on CDB is a frozen branch or not
Checkpoint_MatchArray(0) <= '1' when ((Checkpoint_TagArray(0) = Cdb_RobTag) and (Cfc_ValidArray(0) = '1')) else
'0';
Checkpoint_MatchArray(1) <= '1' when ((Checkpoint_TagArray(1) = Cdb_RobTag) and (Cfc_ValidArray(1) = '1')) else
'0';
Checkpoint_MatchArray(2) <= '1' when ((Checkpoint_TagArray(2) = Cdb_RobTag) and (Cfc_ValidArray(2) = '1')) else
'0';
Checkpoint_MatchArray(3) <= '1' when ((Checkpoint_TagArray(3) = Cdb_RobTag) and (Cfc_ValidArray(3) = '1')) else
'0';
Checkpoint_MatchArray(4) <= '1' when ((Checkpoint_TagArray(4) = Cdb_RobTag) and (Cfc_ValidArray(4) = '1')) else
'0';
Checkpoint_MatchArray(5) <= '1' when ((Checkpoint_TagArray(5) = Cdb_RobTag) and (Cfc_ValidArray(5) = '1')) else
'0';
Checkpoint_MatchArray(6) <= '1' when ((Checkpoint_TagArray(6) = Cdb_RobTag) and (Cfc_ValidArray(6) = '1')) else
'0';
Checkpoint_MatchArray(7) <= '1' when ((Checkpoint_TagArray(7) = Cdb_RobTag) and (Cfc_ValidArray(7) = '1')) else
'0';
Cfc_Full <= Full;
--Task 0: Complete the Full and empty conditions depending on the Head_Pointer and Tail_pointer values
Full <= '1' when (unsigned(Tail_Pointer-Head_Pointer)=1) else '0';
Empty <= '1' when (Head_Pointer = Tail_Pointer) else '0'; --Flag indicating that there is no frozen checkpoint
Cfc_FrlHeadPtr <= Frl_HeadPtrArray(conv_integer(Next_Head_Pointer));
Cfc_RobTag <= Checkpoint_Tagarray(conv_integer(Next_Head_Pointer));
CfcUpdate: process (Clk, Resetb)
begin
if(Resetb = '0') then
Head_Pointer <= "000"; --Here the Head_Pointer points to the active checkpoint and not to the empty location
Tail_Pointer <= "000";
for I in 0 to 7 loop
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
Cfc_ValidArray(I) <= '0';
end loop;
elsif (Clk'event and Clk = '1') then
--Releasing the oldest checkpoint if the branch reaches top of ROB
if ((Rob_Commit = '1') and (Rob_TopPtr = Checkpoint_TagArray(conv_integer(Tail_Pointer))) and ((Tail_Pointer - Next_Head_Pointer) /= "00")) then
Tail_Pointer <= Tail_Pointer + '1';
Cfc_ValidArray(conv_integer(Tail_Pointer)) <= '0';
for I in 0 to 31 loop
Dfa_List(conv_integer(Tail_Pointer))(I) <= '0';
end loop;
end if;
if (Cdb_Flush = '1') then
---- ADDED BY MANPREET--- need to invalidate the active rat dfa bits
for J in 0 to 31 loop
Dfa_List(conv_integer(Head_Pointer))(J) <= '0';
end loop;
-----------------------------
for I in 0 to 7 loop
-- changed by Manpreet.. shouldnt invalidate the rat corresponding to branch_tag = cdb_robtag as
-- it contains instructions before the flushed branch and will become the active rat
if (Cdb_RobDepth < Depth_Array(I)) then --Invalidating all the younger checkpoints and clearing the Dfa_List
Cfc_ValidArray(I)<='0';
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
end if;
if (Cdb_RobDepth = Depth_Array(I)) then
Cfc_ValidArray(I)<='0';
end if ;
end loop;
Head_Pointer <= Next_Head_Pointer;
else
-- Task 1: Update the DFA bit of the Active Checkpoint on dispatch of Register Writing Instruction
if (Dis_InstValid='1' and Dis_CfcRegWrite='1') then
Dfa_List(conv_integer(Head_Pointer)) (conv_integer(Dis_CfcRdAddr)) <= '1';
end if;
-- Task 2: Create a new checkpoint for dispatched branch (i.e. freeze the active checkpoint)
if ((Dis_CfcBranch = '1' or Dis_Jr31Inst = '1')and Dis_InstValid = '1' and ((Full /= '1') or ((Rob_Commit = '1') and (Full = '1') ))) then -- Task 2.1 - some conditions missing - think structural hazard - can't dispatch branch if all checkpoints are in use. But what if a branch is committing as well?
Checkpoint_TagArray (conv_integer(Head_Pointer)) <= Dis_CfcBranchTag;
Cfc_ValidArray (conv_integer(Head_Pointer)) <= '1';
Frl_HeadPtrArray(conv_integer(Head_Pointer)) <= Frl_HeadPtr;
Head_Pointer <= Head_Pointer + 1;
-- Task 2.2 - what things need to be done for a new checkpoint? Tagarray, validarray, FRL headpointer and the headpointer should be updated.
end if;
end if;
end if;
end process;
--Combinational Process to determine new head pointer during branch misprediction
CDB_Flush_Process: process (Cdb_Flush, Checkpoint_MatchArray, Frl_HeadPtrArray, Checkpoint_TagArray, Head_Pointer)
begin
Next_Head_Pointer <= Head_Pointer;
if (Cdb_Flush = '1') then
Case Checkpoint_MatchArray is --Case statement to move the head pointer on branch misprediction to corresponding frozen checkpoint
when "00000001" =>
Next_Head_Pointer <= "000";
when "00000010" =>
Next_Head_Pointer <= "001";
when "00000100" =>
Next_Head_Pointer <= "010";
when "00001000" =>
Next_Head_Pointer <= "011";
when "00010000" =>
Next_Head_Pointer <= "100";
when "00100000" =>
Next_Head_Pointer <= "101";
when "01000000" =>
Next_Head_Pointer <= "110";
when "10000000" =>
Next_Head_Pointer <= "111";
when others =>
Next_Head_Pointer <= "XXX";
end case;
end if;
end process;
--Process to find the latest value of Rs to be given to Dispatch
Dispatch_RsRead_Process: process (Clk,Resetb)
variable found_Rs1, found_Rs2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RsPointer: std_logic_vector(2 downto 0);
begin
if (Resetb = '0') then
Committed_RsList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rs1 := '1';
exit;
else
found_Rs1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rs2 := '1';
exit;
else
found_Rs2 := '0';
end if;
end if;
end loop;
-- Task 3: Use found_Rs1, found_Rs2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rspointer and Dfa_RsValid
-- Dfa_RsValid tells if the Rs register is present in any of the 8 checkpoints or not
-- BRAM_Rspointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RsValid <= found_Rs1 or found_Rs2;
if (found_Rs1 = '1') then
BRAM_Rspointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rs2 = '1') then
BRAM_Rspointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rspointer := (others => '0');
end if;
-- Task 4: Update Committed_Rslist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rslist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RsList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RsList_temp <= Cfc_RsList(conv_integer(BRAM_RsPointer & Dis_CfcRsAddr)); --concatenating the pointer & logical Rs address value to read BRAM
Committed_RsList_temp <= Committed_RsList(conv_integer(Dis_CfcRsAddr));
end if;
end if;
end process;
process (Dfa_RsValid, Cfc_RsList_temp, Committed_RsList_temp)--mux to select between the checkpoint value or committed value
begin
if (Dfa_RsValid = '1') then
Cfc_RsPhyAddr <= Cfc_RsList_temp;
else
Cfc_RsPhyAddr <= Committed_RsList_temp;
end if;
end process;
-- Task 5: same process as above for finding the latest value of Rt
Dispatch_RtRead_Process: process(Clk,Resetb)
variable found_Rt1, found_Rt2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RtPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RtList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRtAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rt1 := '1';
exit;
else
found_Rt1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRtAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rt2 := '1';
exit;
else
found_Rt2 := '0';
end if;
end if;
end loop;
-- Use found_Rt1, found_Rt2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rtpointer and Dfa_RtValid
-- Dfa_RtValid tells if the Rt register is present in any of the 8 checkpoints or not
-- BRAM_Rtpointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RtValid <= found_Rt1 or found_Rt2;
if (found_Rt1 = '1') then
BRAM_Rtpointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rt2 = '1') then
BRAM_Rtpointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rtpointer := (others => '0');
end if;
-- Task 4: Update Committed_Rtlist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rtlist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RtList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RtList_temp <= Cfc_RtList(conv_integer(BRAM_RtPointer & Dis_CfcRtAddr)); --concatenating the pointer & logical Rt address value to read BRAM
Committed_RtList_temp <= Committed_RtList(conv_integer(Dis_CfcRtAddr));
end if;
end if;
end process;
process (Dfa_RtValid, Cfc_RtList_temp, Committed_RtList_temp)
begin
if (Dfa_RtValid = '1') then
Cfc_RtPhyAddr <= Cfc_RtList_temp;
else
Cfc_RtPhyAddr <= Committed_RtList_temp;
end if;
end process;
-- Task 6: same process as above for finding the latest value of Rd
Dispatch_RdRead_Process: process(Clk,Resetb)
variable found_Rd1, found_Rd2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RdPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RdList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRdAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rd1 := '1';
exit;
else
found_Rd1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRdAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rd2 := '1';
exit;
else
found_Rd2 := '0';
end if;
end if;
end loop;
-- Use found_Rd1, found_Rd2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rdpointer and Dfa_RdValid
-- Dfa_RdValid tells if the Rd register is present in any of the 8 checkpoints or not
-- BRAM_Rdpointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RdValid <= found_Rd1 or found_Rd2;
if (found_Rd1 = '1') then
BRAM_Rdpointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rd2 = '1') then
BRAM_Rdpointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rdpointer := (others => '0');
end if;
-- Task 4: Update Committed_Rdlist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rdlist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RdList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RdList_temp <= Cfc_RdList(conv_integer(BRAM_RdPointer & Dis_CfcRdAddr)); --concatenating the pointer & logical Rd address value to read BRAM
Committed_RdList_temp <= Committed_RdList(conv_integer(Dis_CfcRdAddr));
end if;
end if;
end process;
process (Dfa_RdValid, Cfc_RdList_temp, Committed_RdList_temp)
begin
if (Dfa_RdValid = '1') then
Cfc_RdPhyAddr <= Cfc_RdList_temp;
else
Cfc_RdPhyAddr <= Committed_RdList_temp;
end if;
end process;
end cfc_arch;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_command_rec_fifo/simulation/fg_tb_synth.vhd | 1 | 11716 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/FIFO_DDR_DATA_IN/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_POST_FIFO/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/rx_data_fifo/simulation/fg_tb_dverif.vhd | 35 | 5486 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RX_RECV_FIFO/example_design/RX_RECV_FIFO_top.vhd | 1 | 4786 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RX_RECV_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RX_RECV_FIFO_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RX_RECV_FIFO_top;
architecture xilinx of RX_RECV_FIFO_top is
SIGNAL clk_i : std_logic;
component RX_RECV_FIFO is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : RX_RECV_FIFO PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_jal_jr_factorial_simple.vhd | 3 | 8759 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $6 : F0
-- $29: contains fixed bottom of stack for $31 values
-- The program calculates factorial of the number n
-- addi $4, $0, n ---put factorial candidate in $4
-- addi $3, $0, n ---put factorial candidate in $3
-- slt $5, $4, $2 ---check if no. is zero or one
-- bne $5, $1, skiptwo ---go ahead if no. is not 0 or 1
-- add $5, $1, $0 ---no. is 0 or 1, ans is 1
-- jump exit1 --- exit the code. $5 has final ans.
-- skiptwo: jal subroutine ---calculate factorial. goto function.
-- add $5, $3, $0 ---store final ans. in $5
-- exit1: jr $6 ---jump to exit
-- subroutine:
-- addi $29, $29, -4 --decrement address
-- sw $31,0($29) --put contents of $31 into location pointed by $29
-- sub $4, $4, $1 ---$4=$4 - 1
-- mul $3, $3, $4 ---$3=$3 * $4
-- beq $1, $4, outofloop ---check if $4 has reached 1
-- jal subroutine; --- if $4 /= 1, do 1 more iteration
-- outofloop: lw $31,0($29)
-- addi $29, $29, 4
-- jr $31 ---start exiting the loop
--($6):
-- sw $5, 0($29) -- this sw stores final ans to mem
-- add $4,$2,$2 -- load 4 into $4
-- lw $4, 0($4) -- add large latency in order to stop completion
-- add $4, $4, $4
-- add $4, $4, $4
-- add $4, $4, $4
-- add $4, $4, $4
-- jr $4
--($4):
-- exit
--- EXPECTED RESULT----
-- the stream calculates factorial 8 and puts it in $5
-- $5 is mapped to physical reg 37
-- Physical register 37 should be 40320 (d) = 9D80 (H)
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
( X"14A10002_0082282A_20030008_20040008", -- Loc 0C, 08, 04, 00 bne_slt_addi_addi
X"00602820_0C000009_08000008_00202820", -- Loc 1C, 18, 14, 10 add_jal_jump_add
X"00812022_AFBF0000_23BDFFFC_08000020", -- Loc 2C, 28, 24, 20 sub_sw_addi_jump
X"00000020_00000020_10240005_00641819", -- Loc 3C, 38, 34, 30 nop_nop_beq_mul
X"00000020_0C000009_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_jal_nop_nop
X"8FBF0000_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50 lw_nop_nop_nop
X"00000020_AC0C0020_03E00008_23BD0004", -- Loc 6C, 68, 64, 60 jr_addi
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/megatb/i_fetch_test_stream_min_finder.vhd | 3 | 8076 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
-- DATE OF LAST RIVISON: 07/28/08 BY PRASHESH
-- THE GIVEN PROGRAM FINDS MINIMUM NUMBER FROM THE FIRST 10 LOCATION OF DATA MEM
-- ADD $31, $0, $0 --$31 is set to X?00000000?.
-- ADD $11, $10, $0 --
-- ADD $30, $14, $30--
-- ADD $10, $0, $0 --
-- LW $2, 0($31) --Content of memory location 0 goes to $2
-- BEQ $A, $B, GOTO2-- $A is counter to track 10 numbers. -- INSTRUCTION WITH LABEL LOOP
-- ADD $31, $31, $4 --$31 is incremented by 4 so it can point to the next memory location
-- LW $3, 0($31) --Content of Memory location 2 goes to $3
-- SLT $5, $3, $2 --Check if ($3) < ($2)
-- ADD $10, $10, $1 --Increment counter $10
-- BEQ $5, $1, GOTO1-- If ($3) < ($2) then
-- JMP LOOP --If ($3) ? ($2) then
-- ADD $2, $3, $0 --Move ($3)-->($2) IF $3< $2 --INSTRUCTION WITH LABEL GOTO1
-- JMP LOOP --Jump to loop
-- SW $2,0($30) --Store ($2) at memory location 11. ($30)-->4 --INSTRUCTION WITH LABEL GOTO2
-- LW $6, 0($16) --Content of memory location 12 goes to $6 --> THIS BRANCH IS NEVER TAKEN
-- BEQ $2, $6, -4 --If ($2) = ($6) then ? this branch is always taken
-- JMP HERE -- LOCATION WITH LABEL HERE
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"00005020_01DEF020_01405820_0000F820", -- Loc 0C, 08, 04, 00
X"8FE30000_03E4F820_114B0008_8FE20000", -- Loc 1C, 18, 14, 10
X"08000005_10A10001_01415020_0062282A", -- Loc 2C, 28, 24, 20
X"8E060000_AFC20000_08000005_00601020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_08000011_1046FFF4", -- Loc 4C, 48, 44, 40
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/RX_RECV_FIFO/example_design/RX_RECV_FIFO_top_wrapper.vhd | 1 | 18998 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RX_RECV_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RX_RECV_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RX_RECV_FIFO_top_wrapper;
architecture xilinx of RX_RECV_FIFO_top_wrapper is
SIGNAL clk_i : std_logic;
component RX_RECV_FIFO_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : RX_RECV_FIFO_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_div.vhd | 3 | 7087 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are div $2 $3 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"0062101B_0062101B_0062101B_0062101B", -- Loc 0C, 08, 04, 00
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1C, 18, 14, 10
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2C, 28, 24, 20
X"0062101B_0062101B_0062101B_0062101B", -- Loc 3C, 38, 34, 30
X"0062101B_0062101B_0062101B_0062101B", -- Loc 4C, 48, 44, 40
X"0062101B_0062101B_0062101B_0062101B", -- Loc 5C, 58, 54, 50
X"0062101B_0062101B_0062101B_0062101B", -- Loc 6C, 68, 64, 60
X"0062101B_0062101B_0062101B_0062101B", -- Loc 7C, 78, 74, 70
X"0062101B_0062101B_0062101B_0062101B", -- Loc 8C, 88, 84, 80
X"0062101B_0062101B_0062101B_0062101B", -- Loc 9C, 98, 94, 90
X"0062101B_0062101B_0062101B_0062101B", -- Loc AC, A8, A4, A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc BC, B8, B4, B0
X"0062101B_0062101B_0062101B_0062101B", -- Loc CC, C8, C4, C0
X"0062101B_0062101B_0062101B_0062101B", -- Loc DC, D8, D4, D0
X"0062101B_0062101B_0062101B_0062101B", -- Loc EC, E8, E4, E0
X"0062101B_0062101B_0062101B_0062101B", -- Loc FC, F8, F4, F0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 10C, 108, 104, 100
X"0062101B_0062101B_0062101B_0062101B", -- Loc 11C, 118, 114, 110
X"0062101B_0062101B_0062101B_0062101B", -- Loc 12C, 128, 124, 120
X"0062101B_0062101B_0062101B_0062101B", -- Loc 13C, 138, 134, 130
X"0062101B_0062101B_0062101B_0062101B", -- Loc 14C, 148, 144, 140
X"0062101B_0062101B_0062101B_0062101B", -- Loc 15C, 158, 154, 150
X"0062101B_0062101B_0062101B_0062101B", -- Loc 16C, 168, 164, 160
X"0062101B_0062101B_0062101B_0062101B", -- Loc 17C, 178, 174, 170
X"0062101B_0062101B_0062101B_0062101B", -- Loc 18C, 188, 184, 180
X"0062101B_0062101B_0062101B_0062101B", -- Loc 19C, 198, 194, 190
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1AC, 1A8, 1A4, 1A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1BC, 1B8, 1B4, 1B0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1CC, 1C8, 1C4, 1C0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1DC, 1D8, 1D4, 1D0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1EC, 1E8, 1E4, 1E0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1FC, 1F8, 1F4, 1F0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 20C, 208, 204, 200
X"0062101B_0062101B_0062101B_0062101B", -- Loc 21C, 218, 214, 221
X"0062101B_0062101B_0062101B_0062101B", -- Loc 22C, 228, 224, 220
X"0062101B_0062101B_0062101B_0062101B", -- Loc 23C, 238, 234, 230
X"0062101B_0062101B_0062101B_0062101B", -- Loc 24C, 248, 244, 240
X"0062101B_0062101B_0062101B_0062101B", -- Loc 25C, 258, 254, 250
X"0062101B_0062101B_0062101B_0062101B", -- Loc 26C, 268, 264, 260
X"0062101B_0062101B_0062101B_0062101B", -- Loc 27C, 278, 274, 270
X"0062101B_0062101B_0062101B_0062101B", -- Loc 28C, 288, 284, 280
X"0062101B_0062101B_0062101B_0062101B", -- Loc 29C, 298, 294, 290
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2AC, 2A8, 2A4, 2A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2BC, 2B8, 2B4, 2B0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2CC, 2C8, 2C4, 2C0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2DC, 2D8, 2D4, 2D0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2EC, 2E8, 2E4, 2E0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2FC, 2F8, 2F4, 2F0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 30C, 308, 304, 300
X"0062101B_0062101B_0062101B_0062101B", -- Loc 31C, 318, 314, 331
X"0062101B_0062101B_0062101B_0062101B", -- Loc 32C, 328, 324, 320
X"0062101B_0062101B_0062101B_0062101B", -- Loc 33C, 338, 334, 330
X"0062101B_0062101B_0062101B_0062101B", -- Loc 34C, 348, 344, 340
X"0062101B_0062101B_0062101B_0062101B", -- Loc 35C, 358, 354, 350
X"0062101B_0062101B_0062101B_0062101B", -- Loc 36C, 368, 364, 360
X"0062101B_0062101B_0062101B_0062101B", -- Loc 37C, 378, 374, 370
X"0062101B_0062101B_0062101B_0062101B", -- Loc 38C, 388, 384, 380
X"0062101B_0062101B_0062101B_0062101B", -- Loc 39C, 398, 394, 390
X"0062101B_0062101B_0062101B_0062101B", -- Loc 3AC, 3A8, 3A4, 3A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_3/top_tb_withlsqComp_r1.vhd | 1 | 21571 | -------------------------------------------------------------------------------
-- Design : Signal Spy testbench for load store queue
-- Project : Tomasulo Processor
-- Author : Prasanjeet Das
-- Data : July 15,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_off
--use work.reverseAssemblyFunctionPkg.all;
-- synopsys translate_on
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_lsq of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden lsq)
-- Global Clk and Resetb Signals
signal Resetb : std_logic;
-- Information to be captured from the CDB (Common Data Bus)
signal Cdb_RdPhyAddr_gold : std_logic_vector(5 downto 0);
signal Cdb_PhyRegWrite_gold : std_logic;
signal Cdb_Valid_gold : std_logic;
-- Information from the Dispatch Unit
signal Dis_Opcode_gold : std_logic;
signal Dis_Immediate_gold : std_logic_vector(15 downto 0 );
signal Dis_RsDataRdy_gold : std_logic;
signal Dis_RsPhyAddr_gold : std_logic_vector(5 downto 0 );
signal Dis_RobTag_gold : std_logic_vector(4 downto 0);
signal Dis_NewRdPhyAddr_gold : std_logic_vector(5 downto 0);
signal Dis_LdIssquenable_gold : std_logic;
signal Issque_LdStQueueFull_gold : std_logic;
signal Issque_LdStQueueTwoOrMoreVacant_gold: std_logic;
signal Dis_instruction_gold : std_logic_vector(31 downto 0);
signal Iss_instructionLsq_gold : std_logic_vector(31 downto 0);
signal Iss_RsPhyAddrLsq_gold : std_logic_vector(5 downto 0);
signal PhyReg_LsqRsData_gold : std_logic_vector(31 downto 0);
signal Iss_LdStReady_gold : std_logic ;
signal Iss_LdStOpcode_gold : std_logic ;
signal Iss_LdStRobTag_gold : std_logic_vector(4 downto 0);
signal Iss_LdStAddr_gold : std_logic_vector(31 downto 0);
signal Iss_LdStIssued_gold : std_logic;
signal Iss_LdStPhyAddr_gold : std_logic_vector(5 downto 0);
signal DCE_ReadBusy_gold : std_logic;
signal Lsbuf_Done_gold : std_logic;
signal Cdb_Flush_gold : std_logic;
signal Rob_TopPtr_gold : std_logic_vector (4 downto 0);
signal Cdb_RobDepth_gold : std_logic_vector (4 downto 0);
signal SB_FlushSw_gold : std_logic;
signal SB_FlushSwTag_gold : std_logic_vector (1 downto 0);
signal SBTag_counter_gold : std_logic_vector (1 downto 0); --Added by Waleed 06/04/10
signal Rob_CommitMemWrite_gold : std_logic;
-- Signals for the student's DUT (Issue_Queue)
-- Information to be captured from the CDB (Common Data Bus)
signal Cdb_RdPhyAddr : std_logic_vector(5 downto 0);
signal Cdb_PhyRegWrite : std_logic;
signal Cdb_Valid : std_logic;
-- Information from the Dispatch Unit
signal Dis_Opcode : std_logic;
signal Dis_Immediate : std_logic_vector(15 downto 0 );
signal Dis_RsDataRdy : std_logic;
signal Dis_RsPhyAddr : std_logic_vector(5 downto 0 );
signal Dis_RobTag : std_logic_vector(4 downto 0);
signal Dis_NewRdPhyAddr : std_logic_vector(5 downto 0);
signal Dis_LdIssquenable : std_logic;
signal Issque_LdStQueueFull : std_logic;
signal Issque_LdStQueueTwoOrMoreVacant: std_logic;
signal Dis_instruction : std_logic_vector(31 downto 0);
signal Iss_instructionLsq : std_logic_vector(31 downto 0);
signal Iss_RsPhyAddrLsq : std_logic_vector(5 downto 0);
signal PhyReg_LsqRsData : std_logic_vector(31 downto 0);
signal Iss_LdStReady : std_logic ;
signal Iss_LdStOpcode : std_logic ;
signal Iss_LdStRobTag : std_logic_vector(4 downto 0);
signal Iss_LdStAddr : std_logic_vector(31 downto 0);
signal Iss_LdStIssued : std_logic;
signal Iss_LdStPhyAddr : std_logic_vector(5 downto 0);
signal DCE_ReadBusy : std_logic;
signal Lsbuf_Done : std_logic;
signal Cdb_Flush : std_logic;
signal Rob_TopPtr : std_logic_vector (4 downto 0);
signal Cdb_RobDepth : std_logic_vector (4 downto 0);
signal SB_FlushSw : std_logic;
signal SB_FlushSwTag : std_logic_vector (1 downto 0);
signal SBTag_counter : std_logic_vector (1 downto 0); --Added by Waleed 06/04/10
signal Rob_CommitMemWrite : std_logic;
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
-- signals corresponding to Instruction memory
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component lsq
port (
-- Global Clk and Resetb Signals
Clk : in std_logic;
Resetb : in std_logic;
-- Information to be captured from the CDB (Common Data Bus)
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0);
Cdb_PhyRegWrite : in std_logic;
Cdb_Valid : in std_logic ;
-- Information from the Dispatch Unit
Dis_Opcode : in std_logic;
Dis_Immediate : in std_logic_vector(15 downto 0 );
Dis_RsDataRdy : in std_logic;
Dis_RsPhyAddr : in std_logic_vector(5 downto 0 );
Dis_RobTag : in std_logic_vector(4 downto 0);
Dis_NewRdPhyAddr : in std_logic_vector(5 downto 0);
Dis_LdIssquenable : in std_logic;
Issque_LdStQueueFull : out std_logic;
Issque_LdStQueueTwoOrMoreVacant: out std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Iss_instructionLsq : out std_logic_vector(31 downto 0);
-- translate_on
-- interface with PRF
Iss_RsPhyAddrLsq : out std_logic_vector(5 downto 0);
PhyReg_LsqRsData : in std_logic_vector(31 downto 0);
-- Interface with the Issue Unit
Iss_LdStReady : out std_logic ;
Iss_LdStOpcode : out std_logic ;
Iss_LdStRobTag : out std_logic_vector(4 downto 0);
Iss_LdStAddr : out std_logic_vector(31 downto 0);
Iss_LdStIssued : in std_logic;
Iss_LdStPhyAddr : out std_logic_vector(5 downto 0);
DCE_ReadBusy : in std_logic;
Lsbuf_Done : in std_logic;
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector (4 downto 0);
Cdb_RobDepth : in std_logic_vector (4 downto 0);
SB_FlushSw : in std_logic;
--SB_FlushSwTag : in std_logic_vector (4 downto 0) --Modified by Waleed 06/04/10
SB_FlushSwTag : in std_logic_vector (1 downto 0);
SBTag_counter : in std_logic_vector (1 downto 0); --Added by Waleed 06/04/10
--Interface with ROB , Added by Waleed 06/04/10
Rob_CommitMemWrite : in std_logic
);
end component lsq;
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
lsq_UUT: lsq
port map (
Clk => Clk,
Resetb => Resetb,
Cdb_RdPhyAddr => Cdb_RdPhyAddr,
Cdb_PhyRegWrite => Cdb_PhyRegWrite,
Cdb_Valid => Cdb_Valid,
Dis_Opcode => Dis_Opcode,
Dis_Immediate => Dis_Immediate,
Dis_RsDataRdy => Dis_RsDataRdy,
Dis_RsPhyAddr => Dis_RsPhyAddr,
Dis_RobTag => Dis_RobTag,
Dis_NewRdPhyAddr => Dis_NewRdPhyAddr,
Dis_LdIssquenable => Dis_LdIssquenable,
Issque_LdStQueueFull => Issque_LdStQueueFull,
Issque_LdStQueueTwoOrMoreVacant => Issque_LdStQueueTwoOrMoreVacant,
Dis_instruction => Dis_instruction,
Iss_instructionLsq => Iss_instructionLsq,
Iss_RsPhyAddrLsq => Iss_RsPhyAddrLsq,
PhyReg_LsqRsData => PhyReg_LsqRsData,
Iss_LdStReady => Iss_LdStReady,
Iss_LdStOpcode => Iss_LdStOpcode,
Iss_LdStRobTag => Iss_LdStRobTag,
Iss_LdStAddr => Iss_LdStAddr,
Iss_LdStIssued => Iss_LdStIssued,
Iss_LdStPhyAddr => Iss_LdStPhyAddr,
DCE_ReadBusy => DCE_ReadBusy,
Lsbuf_Done => Lsbuf_Done,
Cdb_Flush => Cdb_Flush,
Rob_TopPtr => Rob_TopPtr,
Cdb_RobDepth => Cdb_RobDepth,
SB_FlushSw => SB_FlushSw,
SB_FlushSwTag => SB_FlushSwTag,
SBTag_counter => SBTag_counter,
Rob_CommitMemWrite => Rob_CommitMemWrite
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of lsq only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Issque_LdStQueueFull_gold /=Issque_LdStQueueFull) then
write (my_outline, string'("ERROR! Issque_LdStQueueFull of TEST does not match Issque_LdStQueueFull_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Issque_LdStQueueTwoOrMoreVacant_gold /= Issque_LdStQueueTwoOrMoreVacant) then
write (my_outline, string'("ERROR! Issque_LdStQueueTwoOrMoreVacant of TEST does not match Issque_LdStQueueTwoOrMoreVacant_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_instructionLsq_gold /= Iss_instructionLsq) then
write (my_outline, string'("ERROR! Iss_instructionLsq of TEST does not match Iss_instructionLsq_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_RsPhyAddrLsq_gold /= Iss_RsPhyAddrLsq ) then
write (my_outline, string'("ERROR! Iss_RsPhyAddrLsq of TEST does not match Iss_RsPhyAddrLsq_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_LdStReady_gold /=Iss_LdStReady) then
write (my_outline, string'("ERROR! Iss_LdStReady of TEST does not match Iss_LdStReady_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Iss_LdStOpcode_gold /= Iss_LdStOpcode) then
write (my_outline, string'("ERROR! Iss_LdStOpcode of TEST does not match Iss_LdStOpcode_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_LdStRobTag_gold /= Iss_LdStRobTag) then
write (my_outline, string'("ERROR! Iss_LdStRobTag of TEST does not match Iss_LdStRobTag_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_LdStAddr_gold /= Iss_LdStAddr ) then
write (my_outline, string'("ERROR! Iss_LdStAddr of TEST does not match Iss_LdStAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Iss_LdStPhyAddr_gold /= Iss_LdStPhyAddr) then
write (my_outline, string'("ERROR! Iss_LdStPhyAddr of TEST does not match Iss_LdStPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/integer_queue_inst/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/integer_queue_inst/Resetb","Resetb",0);
init_signal_spy("/UUT/loadstoreque_inst/Cdb_RdPhyAddr","Cdb_RdPhyAddr",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Cdb_RdPhyAddr","Cdb_RdPhyAddr",0);
init_signal_spy("/UUT/loadstoreque_inst/Cdb_PhyRegWrite","Cdb_PhyRegWrite",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Cdb_PhyRegWrite","Cdb_PhyRegWrite",0);
init_signal_spy("/UUT/loadstoreque_inst/Cdb_Valid","Cdb_Valid",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Cdb_Valid","Cdb_Valid",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_Opcode","Dis_Opcode",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_Opcode","Dis_Opcode",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_Immediate","Dis_Immediate",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_Immediate","Dis_Immediate",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_RsDataRdy","Dis_RsDataRdy",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_RsDataRdy","Dis_RsDataRdy",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_RsPhyAddr","Dis_RsPhyAddr",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_RsPhyAddr","Dis_RsPhyAddr",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_NewRdPhyAddr","Dis_NewRdPhyAddr",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_NewRdPhyAddr","Dis_NewRdPhyAddr",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_RobTag","Dis_RobTag",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_RobTag","Dis_RobTag",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_LdIssquenable","Dis_LdIssquenable",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_LdIssquenable","Dis_LdIssquenable",0);
init_signal_spy("/UUT/loadstoreque_inst/Dis_instruction","Dis_instruction",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Dis_instruction","Dis_instruction",0);
init_signal_spy("/UUT/loadstoreque_inst/Cdb_Flush","Cdb_Flush",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Cdb_Flush","Cdb_Flush",0);
init_signal_spy("/UUT/loadstoreque_inst/Rob_TopPtr","Rob_TopPtr",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Rob_TopPtr","Rob_TopPtr",0);
init_signal_spy("/UUT/loadstoreque_inst/Cdb_RobDepth","Cdb_RobDepth",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Cdb_RobDepth","Cdb_RobDepth",0);
init_signal_spy("/UUT/loadstoreque_inst/PhyReg_LsqRsData","PhyReg_LsqRsData",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/PhyReg_LsqRsData","PhyReg_LsqRsData",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_LdStIssued","Iss_LdStIssued",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_LdStIssued","Iss_LdStIssued",0);
init_signal_spy("/UUT/loadstoreque_inst/DCE_ReadBusy","DCE_ReadBusy",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/DCE_ReadBusy","DCE_ReadBusy",0);
init_signal_spy("/UUT/loadstoreque_inst/Lsbuf_Done","Lsbuf_Done",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Lsbuf_Done","Lsbuf_Done",0);
init_signal_spy("/UUT/loadstoreque_inst/SB_FlushSw","SB_FlushSw",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/SB_FlushSw","SB_FlushSw",0);
init_signal_spy("/UUT/loadstoreque_inst/SB_FlushSwTag","SB_FlushSwTag",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/SB_FlushSwTag","SB_FlushSwTag",0);
init_signal_spy("/UUT/loadstoreque_inst/SBTag_counter","SBTag_counter",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/SBTag_counter","SBTag_counter",0);
init_signal_spy("/UUT/loadstoreque_inst/Rob_CommitMemWrite","Rob_CommitMemWrite",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Rob_CommitMemWrite","Rob_CommitMemWrite",0);
--outputs--
init_signal_spy("/UUT/loadstoreque_inst/Issque_LdStQueueFull","Issque_LdStQueueFull_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Issque_LdStQueueFull","Issque_LdStQueueFull_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_instructionLsq","Iss_instructionLsq_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_instructionLsq","Iss_instructionLsq_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_RsPhyAddrLsq","Iss_RsPhyAddrLsq_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_RsPhyAddrLsq","Iss_RsPhyAddrLsq_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Issque_LdStQueueTwoOrMoreVacant","Issque_LdStQueueTwoOrMoreVacant_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Issque_LdStQueueTwoOrMoreVacant","Issque_LdStQueueTwoOrMoreVacant_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_LdStReady ","Iss_LdStReady_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_LdStReady "," Iss_LdStReady_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_LdStOpcode","Iss_LdStOpcode_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_LdStOpcode","Iss_LdStOpcode_gold",0);
-------
init_signal_spy("/UUT/loadstoreque_inst/Iss_LdStRobTag","Iss_LdStRobTag_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_LdStRobTag","Iss_LdStRobTag_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_LdStAddr","Iss_LdStAddr_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_LdStAddr","Iss_LdStAddr_gold",0);
init_signal_spy("/UUT/loadstoreque_inst/Iss_LdStPhyAddr","Iss_LdStPhyAddr_gold",1,1);
enable_signal_spy("/UUT/loadstoreque_inst/Iss_LdStPhyAddr","Iss_LdStPhyAddr_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_lsq;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/simulation/fg_tb_synth.vhd | 1 | 10001 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : Command_FIFO_top
PORT MAP (
CLK => clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_selective_flushing_memory_diambiguation.vhd | 3 | 8800 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"008C6819_0202601B_00000020_00000020", -- Loc 0C, 08, 04, 00
X"11C40006_AC0C0000_8C890000_0182701B", -- Loc 1C, 18, 14, 10 -- corrected
X"8C840000_00030820_00020820_00232819", -- Loc 2C, 28, 24, 20
X"AC050014_AC0E0010_AC0C0010_0242601B", -- Loc 3C, 38, 34, 30
X"00000020_AC0C0020_AC04001C_AC010018", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"0180C01B_0182681B_0202601B_00000020", -- Loc 6C, 68, 64, 60
X"AC130004_AC120004_8DA90000_AC180004", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_AC09000C", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Sukhun Kang
-- Date : 07/27/09
--0202601B DIV $12, $16, $2 $12 = 16/2 = 8
--006C6819 MUL $13, $4, $12 $13 = 8*4 = 32
--0182701B DIV $14, $12, $2 $14 = 8/2 = 4
--8C890000 LW $9, 0($4) $9 = dmem(1) = 16
--AC0C0000 SD $12, 0($0) dmem(0) = 8
--11C40006 BEQ $14, $4, 6 IF $4 = $14, jump to the instruction after SD $12, 4($0) skips 6 instructions
--00232819 MUL $5, $1, $3 $5 = 1*3 = 3 * should be flushed*
--00020820 ADD $1, $0, $2 $1 = 0+2 = 2 *should be flushed*
--00030820 ADD $1, $0, $3 $1 = 0+3 = 3* should be flushed*
--8C840000 LD $4, 0($4) $4 = dmem(1) = 8 *should be flushed*
--0242601B DIV $12, $18, $2 $12 = 18/2 = 9 *should flushed*
--AC0C0010 SD $12, 16($0) dmem(4) = 9 *should flushed*
--AC0E0010 SD $14, 16($0) dmem(4) = 4 BRANCH TARGET
--AC050014 SD $5, 20($0) dmem(5) = $5 = 5 not 3
--AC010018 SD $1, 24($0) dmem(6) = $1 = 1 not 3
--AC04001C SD $4, 28($0) dmem(7) = $4 = 4 not 8
--AC0C0020 SD $12, 32($0) dmem(8) = $12 = 8 not 9
--************************************************
--************************************************
-- tag opcode mnemonics result
--************************************************
-- 0 0202601B div $12, $16, $2 $12 = (16/2 = 8)
-- 1 0182681B div $13, $12, $2 $13 = (8/2 = 4)
-- 2 0180C01B div $24, $12, $0 $24 = (8/0 = FFFFFFFF)
-- 3 AC180004 sw $24, 4($0) dmem(1) = FFFFFFFF
-- 4 8DA90000 lw $9, 0($13) $9 = dmem(1) = FFFFFFFF
-- 5 AC120004 sw $18, 4($0) dmem(1)= 18
-- 6 AC130004 sw $19, 4($0) dmem(1)= 19
-- 7 AC09000C sw $9, 12($0) dmem(3)= FFFFFFFFF
--*************************************************
-- "lw" will be waiting for $13 for about 16 clocks
-- for address calculation.
-- 1st "sw" will be waiting for $24 for about 24 clocks
-- the last two "sw"'s will wait until the "lw" has its address
-- then the last two "sw"'s will bypass "lw", count = 2, addbuffmatch = 2
-- then the first "sw" will leave and addbuffmatch = 3
-- then the first "sw" commits and addbuffmatch = 2
-- Now that the "lw" has no "sw" older in the queue and addbuffmatch = count
-- It gets issued.
-- We can see the CDB tag and CDB valid to recognize the order of appearance on CDB
-- ==================================================================================
-- *******************************************************
-- The expected order of appearance on CDB leaving NOP's
-- ******************************************************
-- first 0 0050601B div $12, $2, $16
-- second 1 004C681B div $13, $2, $12
-- third 5 AC120004 sw $18, 4($0)
-- fourth 6 AC130004 sw $19, 4($0)
-- fifth 2 000CC01B div $24, $0, $12
-- sixth 3 AC180004 sw $24, 4($0)
-- seventh 4 8DA90000 lw $9, 0($13)
-- *****************************************************
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_2/dispatch_xtend_BRAM.vhd | 2 | 38983 | -------------------------------------------------------------------------------
--
-- Design : Dispatch Unit
-- Project : Tomasulo Processor
-- Entity : dispatch_unit
-- Author : Manpreet Billing
-- Company : University of Southern California
-- Last Updated : March 2, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity dispatch_unit is
port(
Clk : in std_logic ;
Resetb : in std_logic ;
-- Interface with Intsruction Fetch Queue
Ifetch_Instruction : in std_logic_vector(31 downto 0); -- instruction from IFQ
Ifetch_PcPlusFour : in std_logic_vector(31 downto 0); -- the PC+4 value carried forward for jumping and branching
Ifetch_EmptyFlag : in std_logic; -- signal showing that the ifq is empty,hence stopping any decoding and dispatch of the current if_inst
Dis_Ren : out std_logic; -- stalling caused due to issue queue being full
Dis_JmpBrAddr : out std_logic_vector(31 downto 0); -- the jump or branch address
Dis_JmpBr : out std_logic; -- validating that address to cause a jump or branch
Dis_JmpBrAddrValid : out std_logic; -- to tell if the jump or branch address is valid or not.. will be invalid for "jr $rs" inst
-------------------------------------------------------------------------
-- Interface with branch prediction buffer
Dis_CdbUpdBranch : out std_logic; -- indicates that a branch is processed by the cdb and gives the pred(wen to bpb)
Dis_CdbUpdBranchAddr : out std_logic_vector(2 downto 0);-- indiactes the least significant 3 bit PC[4:2] of the branch beign processed by cdb
Dis_CdbBranchOutcome : out std_logic; -- indiacates the outocome of the branch to the bpb
Bpb_BranchPrediction : in std_logic; -- this bit tells the dispatch what is the prediction based on bpb state-mc
Dis_BpbBranchPCBits : out std_logic_vector(2 downto 0);-- indiaces the 3 least sig bits of the PC value of the current instr being dis (PC[4:2])
Dis_BpbBranch : out std_logic; -- indiactes a branch instr (ren to the bpb)
--------------------------------------------------------------------------------
-- interface with the cdb
Cdb_Branch : in std_logic;
Cdb_BranchOutcome : in std_logic;
Cdb_BranchAddr : in std_logic_vector(31 downto 0);
Cdb_BrUpdtAddr : in std_logic_vector(2 downto 0);
Cdb_Flush : in std_logic;
Cdb_RobTag : in std_logic_vector(4 downto 0);
------------------------------------------------------------------------------
-- interface with checkpoint module (CFC)
Dis_CfcRsAddr : out std_logic_vector(4 downto 0); -- indicates the Rs Address to be read from Reg file
Dis_CfcRtAddr : out std_logic_vector(4 downto 0); -- indicates the Rt Address to be read from Reg file
Dis_CfcRdAddr : out std_logic_vector(4 downto 0); -- indicates the Rd Address to be written by instruction
-- goes to Dis_CfcRdAddr of ROB too
Cfc_RsPhyAddr : in std_logic_vector(5 downto 0); -- Rs Physical register Tag corresponding to Rs Addr
Cfc_RtPhyAddr : in std_logic_vector(5 downto 0); -- Rt Physical register Tag corresponding to Rt Addr
Cfc_RdPhyAddr : in std_logic_vector(5 downto 0); -- Rd Old Physical register Tag corresponding to Rd Addr
Cfc_Full : in std_logic ; -- indicates that all RATs are used and hence we stall in case of branch or Jr $31
Dis_CfcBranchTag : out std_logic_vector(4 downto 0) ; -- indicats the rob tag of the branch for which checkpoint is to be done
Dis_CfcRegWrite : out std_logic; -- indicates that the instruction in the dispatch is a register writing instruction and hence should update the active RAT with destination register tag.
Dis_CfcNewRdPhyAddr : out std_logic_vector(5 downto 0); -- indicates the new physical register to be assigned to Rd for the instruciton in first stage
Dis_CfcBranch : out std_logic; -- indicates if branch is there in first stage of dispatch... tells cfc to checkpoint
Dis_CfcInstValid : out std_logic;
--------------------------------------------------------------------------------
-- physical register interface
PhyReg_RsDataRdy : in std_logic ; -- indicating if the value of Rs is ready at the physical tag location
PhyReg_RtDataRdy : in std_logic ; -- indicating if the value of Rt is ready at the physical tag location
-- translate_off
Dis_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
--------------------------------------------------------------------------------
-- interface with issue queues
Dis_RegWrite : out std_logic;
Dis_RsDataRdy : out std_logic; -- tells the queues that Rs value is ready in PRF and no need to snoop on CDB for that.
Dis_RtDataRdy : out std_logic; -- tells the queues that Rt value is ready in PRF and no need to snoop on CDB for that.
Dis_RsPhyAddr : out std_logic_vector(5 downto 0); -- tells the physical register mapped to Rs (as given by Cfc)
Dis_RtPhyAddr : out std_logic_vector(5 downto 0); -- tells the physical register mapped to Rt (as given by Cfc)
Dis_RobTag : out std_logic_vector(4 downto 0);
Dis_Opcode : out std_logic_vector(2 downto 0); -- gives the Opcode of the given instruction for ALU operation
Dis_IntIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_LdIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_DivIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_MulIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_Immediate : out std_logic_vector(15 downto 0); -- 15 bit immediate value for lw/sw address calculation and addi instruction
Issque_IntQueueFull : in std_logic;
Issque_LdStQueueFull : in std_logic;
Issque_DivQueueFull : in std_logic;
Issque_MulQueueFull : in std_logic;
Issque_IntQueTwoOrMoreVacant : in std_logic; -- indicates that 2 or more slots are available in integer queue
Issque_LdStQueTwoOrMoreVacant : in std_logic;
Issque_DivQueTwoOrMoreVacant : in std_logic;
Issque_MulQueTwoOrMoreVacant : in std_logic;
Dis_BranchOtherAddr : out std_logic_vector(31 downto 0); -- indicates 32 pins for carrying branch other address to be used incase of misprediction.
Dis_BranchPredict : out std_logic; -- indicates the prediction given by BPB for branch instruction
Dis_Branch : out std_logic;
Dis_BranchPCBits : out std_logic_vector(2 downto 0);
Dis_JrRsInst : out std_logic;
Dis_JalInst : out std_logic ; -- Indicating whether there is a call instruction
Dis_Jr31Inst : out std_logic;
----------------------------------------------------------------------------------
---- interface with the FRL---- accessed in first sage only so dont need NaerlyEmpty signal from Frl
Frl_RdPhyAddr : in std_logic_vector(5 downto 0); -- Physical tag for the next available free register
Dis_FrlRead : out std_logic ; -- indicating if free register given by FRL is used or not
Frl_Empty : in std_logic; -- indicates that there are no more free physical registers
----------------------------------------------------------------------------------
---- interface with the RAS
Dis_RasJalInst : out std_logic ; -- indicating whether there is a call instruction
Dis_RasJr31Inst : out std_logic;
Dis_PcPlusFour : out std_logic_vector(31 downto 0); -- represents the return address of Jal call instruction
Ras_Addr : in std_logic_vector(31 downto 0); -- popped RAS address from RAS
----------------------------------------------------------------------------------
---- interface with the rob
Dis_PrevPhyAddr : out std_logic_vector(5 downto 0); -- indicates old physical register mapped to Rd of the instruction
Dis_NewRdPhyAddr : out std_logic_vector(5 downto 0); -- indicates new physical register to be assigned to Rd (given by FRL)
Dis_RobRdAddr : out std_logic_vector(4 downto 0); -- indicates the Rd Address to be written by instruction -- send to Physical register file too.. so that he can make data ready bit "0"
Dis_InstValid : out std_logic ;
Dis_InstSw : out std_logic ;
Dis_SwRtPhyAddr : out std_logic_vector(5 downto 0); -- indicates physical register mapped to Rt of the Sw instruction
Rob_BottomPtr : in std_logic_vector(4 downto 0);
Rob_Full : in std_logic;
Rob_TwoOrMoreVacant : in std_logic
);
end dispatch_unit;
architecture behv of dispatch_unit is
signal Ifetch_Instruction_small :std_logic_vector(5 downto 0);
signal dispatch_rsaddr,dispatch_rtaddr,dispatch_rdaddr:std_logic_vector(4 downto 0);
signal sel_que_full ,sel_que_nearly_full: std_logic;
signal DisJal ,DisJr31 ,DisJrRs,RegWrite , jr_stall :std_logic ;
signal jr_rob_tag : std_logic_vector(4 downto 0);
signal StageReg_RdAddr ,Dis_CfcRdAddrTemp : std_logic_vector(4 downto 0);
signal IntIssquenable ,DivIssquenable,LdIssquenable,MulIssquenable , ren_var : std_logic ;
signal InstValid , InstSw ,Branch ,BranchPredict: std_logic ;
signal Opcode , BranchPCBits : std_logic_vector (2 downto 0);
signal ImmLdSt : std_logic_vector(15 downto 0);
signal StageReg_IntIssquenable ,StageReg_DivIssquenable,StageReg_LdIssquenable,StageReg_MulIssquenable : std_logic ;
signal StageReg_InstValid, StageReg_InstSw ,StageReg_Branch ,StageReg_RegWrite ,StageReg_BranchPredict: std_logic ;
signal StageReg_Opcode , StageReg_BranchPCBits : std_logic_vector (2 downto 0);
signal StageReg_ImmLdSt : std_logic_vector(15 downto 0);
signal StageReg_BranchOtherAddr , BranchOtherAddr: std_logic_vector(31 downto 0);
signal StageReg_JrRsInst ,StageReg_Jr31Inst,StageReg_JalInst : std_logic ;
signal StageReg_NewRdPhyAddr : std_logic_vector(5 downto 0);
signal StageReg_Instruction : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
--variable assignments---------------
Ifetch_Instruction_small <= Ifetch_Instruction(31 downto 26);
dispatch_rsaddr <=Ifetch_Instruction(25 downto 21);
dispatch_rtaddr <=Ifetch_Instruction(20 downto 16);
dispatch_rdaddr <=Ifetch_Instruction(15 downto 11);
---- process for interactions with IFETCH
ifetch_comm : process(Ifetch_Instruction,sel_que_full,Rob_Full,Ifetch_Instruction_small,
Cdb_Flush,Ifetch_PcPlusFour,Ifetch_EmptyFlag,Bpb_BranchPrediction,
Cdb_BranchAddr,DisJal,DisJr31,DisJrRs,RegWrite, sel_que_nearly_full,Rob_TwoOrMoreVacant,
StageReg_InstValid,StageReg_RegWrite, Cfc_Full , Branch,InstValid,
jr_stall, Frl_Empty, Cdb_RobTag, jr_rob_tag, Ras_Addr
)
variable branch_addr_sign_extended_var ,branch_target_addr:std_logic_vector(31 downto 0);
variable branch_addr_sign_extended_shifted_var :std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
-- Task1:
-- 1. Correct the sign-extension operation implemented in the if statement below
if (Ifetch_Instruction(15) = '1') then
branch_addr_sign_extended_var := X"FFFF" & Ifetch_Instruction(15 downto 0) ; -- This line is incorrect and you need to modify it
else
branch_addr_sign_extended_var := X"0000" & Ifetch_Instruction(15 downto 0) ; -- This line is incorrect and you need to modify it
end if ;
-- 2. Complete the branch target address calculation
branch_addr_sign_extended_shifted_var := branch_addr_sign_extended_var(29 downto 0)& "00";
branch_target_addr := branch_addr_sign_extended_shifted_var + Ifetch_PcPlusFour ; -- Complete this statement
-- End of Task1
----------------------------------------------------------
----------------------------------------------------------
-- Dis_Ren: In this process we generate the read enable signal of IFQ. When the 1st stage dispatch is stalled for one reason
-- or IFQ is empty then read enable should be 0 otherwise it going to be 1.
-- Dis_JmpBr: At the same time we generate the Dis_JmpBr signal. This signal is used to flush the IFQ and start fetching instruction
-- from other direction in any of the following cases: branch instr in dispatch predicted taken, jump instruction in dispatch,
-- Flush signal active due to misprediction, or Jr $rs instruction coming out of stall.
-- Dis_JmpBr has higher priority over Dis_Ren
-- NOTE : The two or more vacant slot condition of rob is checked with StageReg_InstValid to make sure that instruction in 2nd stage dispatch is a valid instruction
-- The same apply for Frl_empty which is checked with RegWrite signal to make sure that instruction in 1st stage dispatch is a register writing instruction
if ((sel_que_full= '1')or (sel_que_nearly_full = '1') or (Rob_Full= '1') or
(Rob_TwoOrMoreVacant = '0' and StageReg_InstValid = '1')or (Ifetch_EmptyFlag = '1') or
(jr_stall = '1') or (Frl_Empty = '1' and RegWrite = '1') or (Cfc_Full = '1' and (Branch = '1' or DisJr31 = '1'))) then
ren_var <= '0' ;
Dis_Ren<= '0';
else
ren_var <= '1' ;
Dis_Ren<= '1';
end if ;
-- Note : Bpb_BranchPrediction is "0" by default . It is "1" only if there is a branch instruction and the prediction is true in the prediction bit table
-- CONDITIONAL INSTRUCTIONS AND CDBFLUSH IS CHECKED HERE...
if ( (((Ifetch_Instruction_small= "000010") or (((DisJal = '1') or (DisJr31 = '1' or DisJrRs = '1')) and InstValid = '1')
or (Bpb_BranchPrediction = '1') )and Ifetch_EmptyFlag = '0') or (Cdb_Flush='1') or (jr_stall = '1' and Cdb_RobTag = jr_rob_tag))then -- confirm
Dis_JmpBr<= '1';
else
Dis_JmpBr<= '0';
end if ;
-- Dis_JmpBrAddrValid: Pin from dispatch to IFetch telling if JR addr is valid...
Dis_JmpBrAddrValid <= not (DisJrRs and InstValid) ; -- in ifetch this pin is checked along with disaptch_jm_br pin..
-- Thus keeping it "1" as default is harmless..But it should be "0" for "jr $rs" inst
----------------------------------------------------------
-- Task2: Complete the following piece of code to generate the next address from which you need to start fetching
-- incase Dis_JmpBr is set to 1.
-- Dis_JmpBrAddrValid
-- Note : Cdb has the responsibility of generating Cdb_Flush at mispredicted branches and mispredicted "jr $31" instructions
-- Have to jump when dispatch is waiting for jr $RS once it comes on Cdb
if (Cdb_Flush= '1' or (jr_stall = '1' and Cdb_RobTag = jr_rob_tag))then -- Cdb_Flush -- can't avoid as have to give priority to CDB flush over any conditional instruction in dispatch
Dis_JmpBrAddr<=Cdb_BranchAddr ;
else
-- have to give the default value to avoid latch
Dis_JmpBrAddr<=Cdb_BranchAddr ;
if ((Ifetch_Instruction_small = "000010") or (DisJal = '1')) then -- jump
Dis_JmpBrAddr <= Ifetch_PcPlusFour(31 downto 28) & branch_addr_sign_extended_shifted_var(27 downto 0); -- Complete this line
elsif (DisJr31 = '1') then -- JR $31 .. use address popped from RAS
Dis_JmpBrAddr <= Ras_Addr; -- Complete this line
elsif (Bpb_BranchPrediction = '1' ) then -- Branch predicted taken
Dis_JmpBrAddr <= branch_target_addr; -- Complete this line
end if ;
end if ;
-- End of Task2
----------------------------------------------------------
end process;
----------------------------------------------------------
-- selective_que_full Process:
-- This process is used to generate the sel_que_full signal which indicates if the desired instruction
-- issue queue is full or not. Basically, what we need to do is to investigate the opcode of the instruction
-- in the dispatch stage and then we check the full bit of the corresponding instr issue queue. If the
-- corresponding issue queue is full then we set the sel_que_full bit to '1' otherwise it is set to '0'.
selective_que_full:process(Ifetch_Instruction_small,Ifetch_Instruction,Issque_IntQueueFull,
Issque_DivQueueFull,Issque_MulQueueFull,Issque_LdStQueueFull )
begin
if ((( (Ifetch_Instruction_small="000000") and((Ifetch_Instruction(5 downto 0) = "100000") -- add
or (Ifetch_Instruction(5 downto 0) = "100010") or -- sub
(Ifetch_Instruction(5 downto 0) = "100100") or -- and
(Ifetch_Instruction(5 downto 0) = "100101") or --or
(Ifetch_Instruction(5 downto 0) = "101010"))) -- slt
or ( Ifetch_Instruction_small="001000" ) -- addi
or ( Ifetch_Instruction_small="000101" ) -- bne
or ( Ifetch_Instruction_small="000100" ) -- beq
or ( Ifetch_Instruction_small="000011" ) -- jal
or ( Ifetch_Instruction_small="000000" and (Ifetch_Instruction(5 downto 0) = "001000"))) -- jr
and Issque_IntQueueFull='1' -- jr
) then
sel_que_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011011") -- div
and (Issque_DivQueueFull='1')) then
sel_que_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011001") -- mul
and (Issque_MulQueueFull = '1' )) then
sel_que_full<='1';
elsif (((Ifetch_Instruction_small="100011") or (Ifetch_Instruction_small="101011")) -- load / store
and (Issque_LdStQueueFull = '1')) then
sel_que_full<='1';
else
sel_que_full<='0';
end if ;
end process;
----------------------------------------------------------
-- Task3: Complete the selective_que_nearly_full Process
-- This process is used to generate the sel_que_nearly_full signal which indicates if the desired instruction
-- issue queue has less than 2 vacancies ( 1 or 0) and the instruction in the 2nd dispatch stage is of the same
-- type.
-- Hint: This process is very similar to the selective_que_full process.
selective_que_nearly_full:process(Ifetch_Instruction_small,Ifetch_Instruction,Issque_IntQueTwoOrMoreVacant,
Issque_DivQueTwoOrMoreVacant,Issque_MulQueTwoOrMoreVacant,Issque_LdStQueTwoOrMoreVacant,
StageReg_IntIssquenable, StageReg_DivIssquenable, StageReg_MulIssquenable, StageReg_LdIssquenable -- Added by Vaibhav
)
begin
if ((( (Ifetch_Instruction_small="000000") and((Ifetch_Instruction(5 downto 0) = "100000") -- add
or (Ifetch_Instruction(5 downto 0) = "100010") or -- sub
(Ifetch_Instruction(5 downto 0) = "100100") or -- and
(Ifetch_Instruction(5 downto 0) = "100101") or --or
(Ifetch_Instruction(5 downto 0) = "101010"))) -- slt
or ( Ifetch_Instruction_small="001000" ) -- addi
or ( Ifetch_Instruction_small="000101" ) -- bne
or ( Ifetch_Instruction_small="000100" ) -- beq
or ( Ifetch_Instruction_small="000011" ) -- jal
or ( Ifetch_Instruction_small="000000" and (Ifetch_Instruction(5 downto 0) = "001000"))) -- jr
and Issque_IntQueTwoOrMoreVacant='0'
and Issque_IntQueueFull='0'
) then
sel_que_nearly_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011011") -- div
and (Issque_DivQueTwoOrMoreVacant='0')
and Issque_DivQueueFull='0') then
sel_que_nearly_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011001") -- mul
and (Issque_MulQueTwoOrMoreVacant = '0' )
and Issque_MulQueueFull='0') then
sel_que_nearly_full<='1';
elsif (((Ifetch_Instruction_small="100011") or (Ifetch_Instruction_small="101011")) -- load / store
and (Issque_LdStQueTwoOrMoreVacant = '0')
and Issque_LdStQueueFull='0') then
sel_que_nearly_full<='1';
else
sel_que_nearly_full<='0';
end if ;
end process;
-- End of Task3
----------------------------------------------------------
----------------------------------------------------------
-- make_rob_entry Process:
-- The name of the process may cause some confusion. In this process we generate 3 signals:
-- 1. InstValid signal: This signal indicates if the instruction in the 1st stage dispatch is valid or not. Invalid instructions
-- include the following:
-- if the flush signal is active then the instruction in dispatch is flushed
-- if the instruction is a jump instruction which executes in dispatch and then vanishes.
-- JR $rs: This is a special case, since we stall the pipeline until JR $rs completes and it appears on Cdb. In
-- we need an RobTag to identify when the instruction comes on Cdb but no Rob entry is needed as the instr
-- vanishes after the Cdb and does not enter ROB.
-- For Invalid instructions we don't need to assign an ROB entry for that instruction.
make_rob_entry: process(Cdb_Flush, ren_var,dispatch_rsaddr, dispatch_rtaddr , dispatch_rdaddr , Ifetch_Instruction_Small,Ifetch_Instruction)
begin
if ( (ren_var = '0') or (Cdb_Flush ='1') or (Ifetch_Instruction_small="000010")or
((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "001000") and (dispatch_rsaddr /= "11111")) )then
InstValid<='0';
else
InstValid<='1';
end if;
-- 2. InstSw signal: This signal indicates if the instruction in the 1st stage dispatch is a SW instruction.
if (Ifetch_Instruction_small="101011") then -- store word
InstSw <='1';
else
InstSw <='0';
end if ;
-- 3. Dis_CfcRdAddrTemp: This signal holds the Rd address of the instruction in dispatch
----------------------------------------------------------
-- Task4: Write an if-statement to generate Dis_CfcRdAddrTemp
-- Hint: R-type instructions use $rd field, lw and addi use $rt as destination, jal uses $31 as destination.
if (Ifetch_Instruction_small="000000") then --R-type
Dis_CfcRdAddrTemp <= dispatch_rdaddr;
elsif (Ifetch_Instruction_small="001000") then --addi
Dis_CfcRdAddrTemp <= dispatch_rtaddr;
elsif (Ifetch_Instruction_small="100011") then --lw
Dis_CfcRdAddrTemp <= dispatch_rtaddr;
elsif (Ifetch_Instruction_small="000011") then --jal
Dis_CfcRdAddrTemp <= ("11111");
else
Dis_CfcRdAddrTemp <= dispatch_rdaddr;
end if;
-- End of Task4
----------------------------------------------------------
end process ;
----------- Interface with issue queue-------------
-- This process is used to generate the enable signal for the desired issue queue. This signal acts
-- as a wen signal to update the desired issue queue. In addition, we generate the 3-bit ALUOpcode used
-- with r-type, addi, branch and ld/sw instructions.
process (Ifetch_Instruction_small,Ifetch_Instruction , ren_var,Cdb_Flush)
begin
DivIssquenable <= '0';
MulIssquenable <= '0';
IntIssquenable <= '0';
LdIssquenable <= '0' ;
Opcode <= "000";
if ((ren_var = '0') or (Cdb_Flush ='1') or (Ifetch_Instruction_small="000010")) then -- "000010" jump instruction
ImmLdSt <= Ifetch_Instruction(15 downto 0);
-- No entry in any queue is to be made. Queue enables has default value of "0"
else
ImmLdSt <= Ifetch_Instruction(15 downto 0);
case Ifetch_Instruction_small is
when "000000" =>
case Ifetch_Instruction(5 downto 0 ) is
when "011011" => ----div
DivIssquenable <= '1';
when "011001" => ---mul
MulIssquenable <= '1';
when "100000" => ---- add
IntIssquenable <= '1';
when "100010" => ---sub
IntIssquenable <= '1';
Opcode <= "001";
when "100100" => ---and
IntIssquenable <= '1';
Opcode <= "010";
when "100101" => ---or
IntIssquenable <= '1';
Opcode <= "011";
when "101010" => ---slt
IntIssquenable <= '1';
Opcode <= "101";
when "001000" => ---jr
IntIssquenable <= '1';
when others =>
Opcode <= "000";
end case;
when "001000" => -- addi
IntIssquenable <= '1';
Opcode <= "100";
when "000011" => -----jal
IntIssquenable <= '1';
when "000100" => -----beq
IntIssquenable <= '1';
Opcode <= "110";
when "000101" => -- bne
IntIssquenable <= '1';
Opcode <= "111";
when "100011" => -- Load
LdIssquenable <= '1';
Opcode(0)<= '1';
Opcode(2 downto 1)<= "00";
when "101011" => -- store
LdIssquenable <= '1';
Opcode(0)<= '0';
Opcode(2 downto 1)<= "00";
when others =>
Opcode <= "000";
end case ;
end if;
end process;
--- GENERATING RegWrite signal ------------------------------
-- Task5: Your task is to generate the RegWrite signal.
-- Hint1: Why do we need to include the Dis_CfcRdAddrTemp in the sensitivity list !!!
-- Hint2: For R-type instructions you need to check both opcode and the function field. Jr $rs and
-- Jr $31 have the same opcode as R-Type but are not register writing instruction.
process (Ifetch_Instruction_small, Ifetch_Instruction , Dis_CfcRdAddrTemp)
begin
--if (clk'event and clk='1') then
if (Ifetch_Instruction = X"00000020") then --NOP
RegWrite <= '0';
elsif (Ifetch_Instruction_small="000000" and Ifetch_Instruction(5 downto 0)/="001000") then --R-type except jr $31
RegWrite <= '1';
elsif (Dis_CfcRdAddrTemp ="00000") then --can't write reg$0
RegWrite <= '0';
elsif (Ifetch_Instruction_small="000100" --beq
or Ifetch_Instruction_small="000010" --jump
or Ifetch_Instruction_small="000101" --bne
or Ifetch_Instruction_small="101011") then --sw
RegWrite <= '0';
else
RegWrite <= '1';
-- end if;
end if;
-- End of Task5
----------------------------------------------------------
end process ;
-- Generating Jal , JrRs and Jr31 signals
process (Ifetch_Instruction_small, Ifetch_Instruction , dispatch_rsaddr)
begin
DisJr31 <= '0';
DisJrRs <= '0';
DisJal<= '0';
if ((Ifetch_Instruction_small = "000000") and (Ifetch_Instruction(5 downto 0 ) = "001000")) then-- jr
if (dispatch_rsaddr = "11111") then
DisJr31 <= '1';
else
DisJrRs <= '1';
end if;
elsif ( Ifetch_Instruction_small = "000011") then
DisJal<= '1';
end if;
end process ;
-- Generating Branch PC bits and Branch signal
bpb_comm_read:process(Ifetch_PcPlusFour,Ifetch_Instruction_small)
begin
BranchPCBits <= (Ifetch_PcPlusFour(4 downto 2) - 1); -- to get PC for instruction
if ((Ifetch_Instruction_small="000100") OR (Ifetch_Instruction_small="000101" )) then -- beq or bne
Branch <= '1'; -- queues and bpb
else
Branch <= '0';
end if ;
end process;
-- CLOCK PROCESS FOR GENERATING STALL SIGNAL ON JR $RS INSTRUCTION
-- This is a very important process which takes care of generating the stall signal required in case of Jr $rs
-- instruction. When there is a JR $rs instruction in dispatch, first we set the jr_stall flag which is used to stall
-- the dispatch stage. At the same time we record the Rob Tag mapped to the JR $rs instruction in a special register.
-- We snoop on the Cdb waiting for that Rob Tag in order to get the value of $rs which represents the jump address. At
-- that moment we can come out from the stall.
-- Note that the Jr $rs disappears after coming out on the Cdb and does not enter the ROB and hence no ROB entry is needed.
-- However, we still need to assign an Rob Tag for the Jr $rs instruction in order to use it for snooping on the Cdb.
-- Task6: The process is almost complete you just need to update the condition of two if statements
jr_process: process(Clk,Resetb)
begin
if (Resetb = '0') then
jr_stall <= '0';
jr_rob_tag <= "00000"; -- can be don't care also
elsif (Clk'event and Clk = '1') then
if (Cdb_Flush = '1') then
jr_stall <= '0' ;
else
if (Ifetch_Instruction(5 downto 0 )="001000" and Ifetch_Instruction_small = "000000")then -- if jr
-- Add the condition for the following if statement.
-- Hint: Single Condition
if (jr_stall = '0') then
jr_stall <= '1' ;
if (StageReg_InstValid = '0') then
jr_rob_tag <= Rob_BottomPtr ;
else
jr_rob_tag <= Rob_BottomPtr + 1 ;
end if;
end if ;
end if ; -- end of if jr
-- Complete the condition for the following if statement.
-- Hint: How do you know when to come out of the JR $rs stall!!
if (jr_stall = '1' and (Cdb_RobTag = jr_rob_tag-1)) then
jr_stall <= '0';
end if ;
end if ;-- if Cdb_Flush
end if ; -- if Resetb
-- End of Task6
----------------------------------------------------------
end process ;
----------------------------------------------------------
-- issue_queue_entry Process:
-- In this process we generate the BranchOtherAddr signal which is used in case of misprediction of branch instruction.
issue_queue_entry :process(Ifetch_Instruction,Ifetch_PcPlusFour,Bpb_BranchPrediction,DisJal, DisJr31,Ras_Addr)
variable branch_addr_sign_extended_var ,branch_target_addr:std_logic_vector(31 downto 0);
variable branch_addr_sign_extended_shifted_var :std_logic_vector(31 downto 0);
begin
if (Ifetch_Instruction(15) = '1') then
branch_addr_sign_extended_var := X"FFFF" & Ifetch_Instruction(15 downto 0) ;
else
branch_addr_sign_extended_var := X"0000" & Ifetch_Instruction(15 downto 0) ;
end if ;
branch_addr_sign_extended_shifted_var := branch_addr_sign_extended_var(29 downto 0)& "00";
branch_target_addr := branch_addr_sign_extended_shifted_var + Ifetch_PcPlusFour;
--------------------------- NOTE--------------------------------------------------
-- Dis_BranchOtherAddr pins carry the following :
-- a) In case of a branch , we sent the "other address" with branch. By "other address " we mean , the address to be taken in case the branch is mis-predicted
-- If the branch was predicted to be "not taken" , then we keep on executing the instructions from PC + 4 location only. In case of mis-prediction,
-- we need to jump to target address calculated , thus we send branch_target_Addr on these pins
-- If the branch was predicted to be "taken" , then we started executing instructions from "target address". In case of mis-prediction,
-- we actually need to execute instructions from PC+4 , thus we send PC+4 on the pins
-- b) In case of jr , the pins carry the address given by RAS (valid or invalid). Sending the invlaid address will be harmless. That address is compared with
-- the correct address from software stack and a flush signal is initiated in case of mis-match.
-- c) In case of jal, the pins carry PC+4 which is stored in register $31.
-----------------------------------------------------------------------------------------
if(Bpb_BranchPrediction = '1' or DisJal = '1') then
BranchOtherAddr <= Ifetch_PcPlusFour;
elsif (DisJr31 = '1') then
BranchOtherAddr <= Ras_Addr;
else
BranchOtherAddr <= branch_target_addr; -- put jr addr from RAS in case of jr
end if ;
end process;
-- PHYSICAL FILE SIGNALS (From second stage)
Dis_RsPhyAddr <= Cfc_RsPhyAddr;
Dis_RtPhyAddr <= Cfc_RtPhyAddr;
-- BPB SIGNALS... INTERFACE WITH BPB IS FROM FIRST STAGE
Dis_CdbUpdBranch <= Cdb_Branch;
Dis_CdbUpdBranchAddr<=Cdb_BrUpdtAddr;
Dis_CdbBranchOutcome<=Cdb_BranchOutcome; ---outcome bit from rob;
Dis_BpbBranchPCBits <= BranchPCBits ;
Dis_BpbBranch <= Branch ;
-- CFC SIGNALS.. INTERFACE WITH CFC IS FROM FIRST STAGE
Dis_CfcBranchTag <= Rob_BottomPtr when (StageReg_InstValid = '0') else Rob_BottomPtr + 1;
Dis_CfcRegWrite <= RegWrite and InstValid ;
Dis_CfcRsAddr <= dispatch_rsaddr ;
Dis_CfcRtAddr <= dispatch_rtaddr ;
Dis_CfcRdAddr <= Dis_CfcRdAddrTemp ;
Dis_CfcBranch <= Branch ;
Dis_CfcNewRdPhyAddr <= Frl_RdPhyAddr ;
Dis_CfcInstValid <= InstValid;
-- FRL SIGNALS.. INTERFACE WITH FRL IS FROM FIRST STAGE
Dis_FrlRead <= RegWrite and InstValid;
-- RAS SIGNALS.. INTERFACE WITH RAS IS FROM FIRST STAGE
Dis_PcPlusFour <= Ifetch_PcPlusFour ;
Dis_RasJalInst <= DisJal and InstValid;
Dis_RasJr31Inst <= DisJr31 and InstValid;
-- ISSUEQUE SIGNALS.. INTERFACE WITH ISSUEQUE IS FROM SECOND STAGE
-- translate_off
Dis_Instruction <= StageReg_Instruction ;
-- translate_on
Dis_RsDataRdy <= PhyReg_RsDataRdy ;
Dis_RtDataRdy <= PhyReg_RtDataRdy ;
Dis_RobTag <= Rob_BottomPtr ;
Dis_Opcode <= StageReg_Opcode;
Dis_IntIssquenable <= StageReg_IntIssquenable when (Cdb_Flush = '0') else '0';
Dis_LdIssquenable <= StageReg_LdIssquenable when (Cdb_Flush = '0') else '0';
Dis_DivIssquenable <= StageReg_DivIssquenable when (Cdb_Flush = '0') else '0';
Dis_MulIssquenable <= StageReg_MulIssquenable when (Cdb_Flush = '0') else '0';
Dis_Immediate <= StageReg_ImmLdSt ;
Dis_BranchOtherAddr <= StageReg_BranchOtherAddr ;
Dis_BranchPredict <= StageReg_BranchPredict;
Dis_Branch <= StageReg_Branch ;
Dis_BranchPCBits <= StageReg_BranchPCBits ;
Dis_JrRsInst <= StageReg_JrRsInst ;
Dis_Jr31Inst <= StageReg_Jr31Inst ;
Dis_JalInst <= StageReg_JalInst ;
-- ROB SIGNALS.. INTERFACE WITH ROB IS FROM SECOND STAGE
Dis_PrevPhyAddr <= Cfc_RdPhyAddr ;
Dis_NewRdPhyAddr <= StageReg_NewRdPhyAddr ;
Dis_RobRdAddr <= StageReg_RdAddr ;
Dis_InstValid <= StageReg_InstValid when (Cdb_Flush = '0') else '0';
Dis_InstSw <= StageReg_InstSw when (Cdb_Flush = '0') else '0';
Dis_RegWrite <= StageReg_RegWrite when (Cdb_Flush = '0') else '0'; -- signal for Queues too
Dis_SwRtPhyAddr <= Cfc_RtPhyAddr;
-- PROCESS FOR STAGE REGISTER of dispatch
process(Clk, Resetb)
begin
if (Resetb = '0') then
StageReg_InstValid <= '0';
StageReg_InstSw <= '0';
StageReg_RegWrite <= '0';
StageReg_IntIssquenable <= '0';
StageReg_LdIssquenable <= '0';
StageReg_DivIssquenable <= '0';
StageReg_MulIssquenable <= '0';
StageReg_Branch <= '0';
StageReg_JrRsInst <= '0';
StageReg_Jr31Inst <= '0';
StageReg_JalInst <= '0';
elsif (Clk'event and Clk = '1' ) then
StageReg_RdAddr <= Dis_CfcRdAddrTemp ;
StageReg_InstValid <= InstValid ;
StageReg_InstSw <= InstSw ;
StageReg_RegWrite <= RegWrite and InstValid; -- RegWrite , DisJrRs, DisJal and DisJr31 are generated in the process without checking the validity of instruciton . Thus needs to be validated with InstValid signal
StageReg_Instruction <= Ifetch_Instruction ;
StageReg_NewRdPhyAddr <= Frl_RdPhyAddr;
StageReg_Opcode <= Opcode;
StageReg_IntIssquenable <= IntIssquenable ;
StageReg_LdIssquenable <= LdIssquenable;
StageReg_DivIssquenable <= DivIssquenable;
StageReg_MulIssquenable <= MulIssquenable;
StageReg_ImmLdSt <= ImmLdSt ;
StageReg_BranchOtherAddr <= BranchOtherAddr ;
StageReg_BranchPredict <= Bpb_BranchPrediction ;
StageReg_Branch <= Branch ;
StageReg_BranchPCBits <= BranchPCBits ;
StageReg_JrRsInst <= DisJrRs and InstValid;
StageReg_Jr31Inst <= DisJr31 and InstValid;
StageReg_JalInst <= DisJal and InstValid;
end if ;
end process;
end behv ;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_PRE_FIFO/simulation/fg_tb_pkg.vhd | 1 | 11390 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT WR_FLASH_PRE_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_command_rec_fifo/simulation/fg_tb_pctrl.vhd | 4 | 20403 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_sim/megatb/i_fetch_test_stream_lws.vhd | 3 | 7214 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h)
-- 35 => 00000040(h)
-- 36 => 00000050(h)
-- 37 => 00000060(h)
-- 38 => 00000070(h)
-- 39 => 00000080(h)
-- 40 => 00000001(h)
-- 41 => 00000002(h)
-- 42 => 000000B0(h)
-- 43 => 000000C0(h)
-- 44 => 000000D0(h)
-- 45 => 000000E0(h)
-- 46 => 000000F0(h)
-- 47 => 00000100(h)
------------------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"8C9E000C_8C9E0008_8C9E0004_8C9E0000", -- Loc 0C, 08, 04, 00
X"8C9E001C_8C9E0018_8C9E0014_8C9E0010", -- Loc 1C, 18, 14, 10
X"8C9E002C_8C9E0028_8C9E0024_8C9E0020", -- Loc 2C, 28, 24, 20
X"8C9E003C_8C9E0038_8C9E0034_8C9E0030", -- Loc 3C, 38, 34, 30
-- 16 sw instructions changing 16 locations with the content of $30 which is decimal 30 (1D hex)
-- "00000000000000000000000000011110", -- $30
-- Location:() | LW $30 ,0( $4) -- 8C9E0000
-- Location:() | LW $30 ,4( $4) -- 8C9E0004
X"00000020_00000020_00000020_00000020", --- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_memory_disambiguation_RAW.vhd | 3 | 6218 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"8D0C0000_8D020004_ACE20000_0102381B", -- Loc 0C, 08, 04, 00
X"00000020_00000020_00000020_00000020", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Sukhun Kang
-- Modified: 07-25-2009
--
--
-- 0102381B -- div $7, $8, $2 -- $7 gets q=4, r=0
-- ACE20000 -- SW $2, 0($7) -- mem(1) gets 2
-- 8D020004 -- lw $2, 4($8) -- $2 gets mem(3) = 30H
-- 8D0C0000 -- lw $12, 0($8) -- $12 gets mem(2) = 20H
--
----------------------------------------------
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/ssd_command_fifo/example_design/ssd_command_fifo_top_wrapper.vhd | 1 | 19150 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ssd_command_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ssd_command_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end ssd_command_fifo_top_wrapper;
architecture xilinx of ssd_command_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component ssd_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : ssd_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/read_data_fifo/example_design/read_data_fifo_top.vhd | 2 | 5646 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: read_data_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity read_data_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end read_data_fifo_top;
architecture xilinx of read_data_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component read_data_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : read_data_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_syn/code/data_cache_r4.vhd | 1 | 20641 | ------------------------------------------------------------------------------
-- Create/rivision Date: 03/25/10,
-- Minor revision: rev 4 on 7/14/2011 by Gandhi Puvvada
-- Design Name: DATA Cache Emulator Unit
-- Module Name: data_cache
-- Authors: Manpreet Billing , Mohan SK
-- File : data_cache_r4.vhd
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--synopsys translate_off
use work.instr_stream_pkg.all; -- instruction stream defining package
--synopsys translate_on
------------------------------------------------------------------------------
entity data_cache is
generic (
DATA_WIDTH : integer := 32; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
Clk : in std_logic;
Resetb : in std_logic;
DCE_ReadCache : in std_logic;
-- July 14, 2011 -- I have comment it out the following line as it is left unconnected in the top_synth.vhd -- Gandhi Puvvada
-- Abort_PrevRead : in std_logic; -- will be used under jump or successful branch --
-- June 27, 2010 The above pin is not properly connected in the top. So I am ignoring the pin and producing it here as Abort_PrevRead_int
-- Moreover, it does not make sense for other top modules to remember what data item the data cache emulator is reading,
-- and figuring out and telling this module to abort.
--addr : in std_logic_vector (5 downto 0);
Iss_LdStOpcode : in std_logic ;
Iss_LdStRobTag : in std_logic_vector(4 downto 0);
Iss_LdStAddr : in std_logic_vector(31 downto 0);
--- added --------
Iss_LdStPhyAddr : in std_logic_vector(5 downto 0);
------------------
Lsbuf_DCETaken : in std_logic;
Cdb_Flush : in std_logic ; -- Cdb_Flush signal
Rob_TopPtr : in std_logic_vector(4 downto 0);
Cdb_RobDepth : in std_logic_vector(4 downto 0);
SB_WriteCache : in std_logic ;
SB_AddrDmem : in std_logic_vector (31 downto 0);
SB_DataDmem : in std_logic_vector (31 downto 0);
-- translate_off
DCE_instruction : out std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Iss_instructionLsq : in std_logic_vector(31 downto 0);
-- translate_on
--data_out : out std_logic_vector (31 downto 0);
DCE_Opcode : out std_logic ;
DCE_RobTag : out std_logic_vector(4 downto 0);
DCE_Addr : out std_logic_vector(31 downto 0);
DCE_MemData : out std_logic_vector (31 downto 0 ) ; -- data from data memory in the case of lw
------------------new pin added for CDB-----------
DCE_PhyAddr : out std_logic_vector(5 downto 0);
------------------------------------------------------------
-- synopsys translate_off
registered_addr : out std_logic_vector(5 downto 0);
registered_SB_AddrDmem : out std_logic_vector(5 downto 0);
-- synopsys translate_on
DCE_ReadDone : out std_logic;
DCE_WriteDone : out std_logic;
DCE_ReadBusy : out std_logic;
DCE_WriteBusy : out std_logic
-- fio_icache_addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- fio_icache_data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- fio_icache_wea : in std_logic;
-- fio_icache_data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- fio_icache_ena : in std_logic
);
end data_cache;
------------------------------------------------------------------------------
architecture behv of data_cache is
--constant DATA_WIDTH : integer := 32;
--constant ADDR_WIDTH : integer := 6;
signal count_rd : std_logic_vector( 3 downto 0); -- count for latency
-- signal indx_rd : std_logic_vector ( 3 downto 0); -- index to the register array contaning latencies
signal latency_rd : std_logic_vector ( 3 downto 0); -- latency read from the latency register array
signal data_out_mem , reg_instruction: std_logic_vector(31 downto 0);
signal count_wr : std_logic_vector( 3 downto 0); -- count for latency
-- signal indx_wr : std_logic_vector ( 3 downto 0); -- index to the register array contaning latencies
signal latency_wr : std_logic_vector ( 3 downto 0); -- latency read from the latency register array
signal pending_rd_req : std_logic; -- basically a new DCE_ReadCache request is recorded as a pending request
signal DCE_ReadDone_int : std_logic; -- internal signal for the output port DCE_ReadDone
signal pending_wr_req : std_logic; -- basically a new DCE_ReadCache request is recorded as a pending request
signal DCE_WriteDone_int : std_logic; -- internal signal for the output port DCE_WriteDone
signal WriteDone , ReadDone , mem_exc : std_logic ;
signal read_addr , reg_addr : std_logic_vector(31 downto 0);
signal reg_opcode , Abort_PrevRead_int, Abort_incoming_RD_int , read_hit_flag , DCE_ReadBusy_int: std_logic;
-- The line below is commented out as the signal "abort-all is causing combinational feedback
-- signal reg_opcode , abort_all , read_hit_flag , DCE_ReadBusy_int: std_logic;
signal reg_RdTag , lw_Cdb_RobDepth ,incoming_lw_depth:std_logic_vector(4 downto 0);
signal reg_PhyAddr : std_logic_vector(5 downto 0);
signal WriteEnable , DCE_WriteBusy_int : std_logic;
signal SBreg_addr , SBreg_data , DataDmem: std_logic_vector(31 downto 0);
signal AddrDmem : std_logic_vector(5 downto 0);
-- Type definition for latencies
-- Type definition for a 4-bit individual register for the register array.
subtype reg is std_logic_vector (3 downto 0);
-- Type definition of 16-latencies register array
type reg_array is array (0 to 15) of reg;
--type test is array (0 to 31) of reg_array ;
constant latency_array_rd : reg_array := -- minimum latency = 0 after registering the request
( X"6", --0 -- which guarantees the 1 clock delay due to BRAM
X"1", --1
X"2", --2
X"7", --3 -- however, the BRAM works like a pipeline
X"4", --4 -- if the latency is continuously 0 and if
X"6", --5 -- DCE_ReadCache request is true continuously.
X"4", --6
X"4", --7
X"7", --8
x"6", --9
x"5", --10
X"4", --11
X"3", --12
X"3", --13
X"6", --14
X"2" --15
);
constant latency_array_wr : reg_array := -- minimum latency = 0 after registering the request
( X"7", --0 -- which guarantees the 1 clock delay due to BRAM
X"6", --1
X"5", --2
X"3", --3 -- however, the BRAM works like a pipeline
X"3", --4 -- if the latency is continuously 0 and if
X"2", --5 -- DCE_WriteCache request is true continuously.
X"1", --6
X"0", --7
X"0", --8
x"1", --9
x"2", --10
X"3", --11
X"4", --12
X"5", --13
X"6", --14
X"7" --15
);
------
-- component declarations [ data memory]
component ls_buffer_ram_reg_array is
generic (ADDR_WIDTH: integer := 6; DATA_WIDTH: integer := 32);
port (
Clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dia : in std_logic_vector (DATA_WIDTH-1 downto 0);
addrb : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dob : out std_logic_vector (DATA_WIDTH-1 downto 0);
rea : in std_logic ;
mem_wri : out std_logic ;
mem_exc : out std_logic ;
mem_read : out std_logic
);
end component ls_buffer_ram_reg_array;
begin -- begin of architecture
-- component port map
memory: ls_buffer_ram_reg_array
generic map (ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH)
port map (
Clka => Clk ,
wea => WriteEnable, --changed by PRASANJEET to support memory mapped I/O
addra => AddrDmem, --mem_addr( 7 downto 2 ) changed by PRASANJEET ,
dia => DataDmem , --changed by PRASANJEET
addrb => read_addr(7 downto 2), --ReadAddr ( 7 downto 2 ) , --changed by PRASANJEET
dob => data_out_mem,
rea => DCE_ReadCache,
mem_wri => WriteDone ,
mem_exc => mem_exc ,
mem_read => ReadDone
);
lw_Cdb_RobDepth <= unsigned(reg_RdTag) - unsigned(Rob_TopPtr);
incoming_lw_depth <= unsigned(Iss_LdStRobTag) - unsigned(Rob_TopPtr);
DCE_Opcode <= reg_opcode ;
DCE_RobTag <= reg_RdTag ;
DCE_Addr <= reg_addr ;
DCE_PhyAddr <= reg_PhyAddr;
-- translate_off
DCE_instruction <= reg_instruction ;
-- translate_on
read_addr <= Iss_LdStAddr when DCE_ReadCache = '1' else reg_addr ;
DCE_ReadDone <= DCE_ReadDone_int ; -- DCE_ReadDone port is assigned with internal DCE_ReadDone_int
-- Fix 6/27/2010 -- abort_all <= '1' when ((Cdb_Flush = '1' and lw_Cdb_RobDepth > Cdb_RobDepth and DCE_ReadBusy_int = '1') or
-- Fix 6/27/2010 -- (Cdb_Flush = '1' and incoming_lw_depth > Cdb_RobDepth and DCE_ReadBusy_int = '0'))
-- Fix 6/27/2010 -- else '0' ;
Abort_PrevRead_int <= '1' when (Cdb_Flush = '1' and lw_Cdb_RobDepth > Cdb_RobDepth) else '0';
Abort_incoming_RD_int <= '1' when (Cdb_Flush = '1' and incoming_lw_depth > Cdb_RobDepth and DCE_ReadBusy_int = '0') else '0';
-------------------------------------------------------
lw_info_tranfer: process ( Clk, Resetb )
begin
if (Resetb = '0') then
reg_opcode <= '0';
--reg_addr <= X"0";
elsif Clk'event and Clk = '1' then
if (DCE_ReadCache = '1') then
reg_opcode <= Iss_LdStOpcode ;
reg_RdTag <= Iss_LdStRobTag ;
reg_addr <= Iss_LdStAddr ;
reg_PhyAddr <= Iss_LdStPhyAddr;
-- translate_off
reg_instruction <= Iss_instructionLsq;
-- translate_on
end if ;
end if;
end process lw_info_tranfer;
-------------------------------------------------------------------------------
pending_rd_req_two_state_state_machine: process ( Clk, Resetb )
begin
if (Resetb = '0') then
pending_rd_req <= '0';
elsif Clk'event and Clk = '1' then
case pending_rd_req is
when '0' => --- busy signal from data emulator
if ((DCE_ReadCache = '1') and (Abort_incoming_RD_int = '0')) then -- and (abort_all = '0')) then
pending_rd_req <= '1';
end if;
when others => -- i.e. when '1' =>
if ( ((DCE_ReadDone_int = '1') and (DCE_ReadCache = '0')) or (Abort_incoming_RD_int = '1') or (Abort_PrevRead_int = '1')) then -- (abort_all = '1') ) then
-- July 14, 2011 Gandhi: I commented out the following line and replaced it with the above line as now we do not have Abort_PrevRead input any more.
-- if ( (((DCE_ReadDone_int = '1') or (Abort_PrevRead = '1')) and (DCE_ReadCache = '0')) or (Abort_incoming_RD_int = '1') or (Abort_PrevRead_int = '1')) then -- (abort_all = '1') ) then
-- July 27, 2010 fix -- if ( ( ((DCE_ReadDone_int = '1') or (Abort_PrevRead = '1')) and (DCE_ReadCache = '0')) or (abort_all = '1') ) then
--if (DCE_ReadCache = '0' ) then
pending_rd_req <= '0';
end if;
end case;
end if;
end process pending_rd_req_two_state_state_machine;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
register_addr_and_latecy: process ( Clk, Resetb )
variable indx_rd : std_logic_vector ( 3 downto 0);
begin
if (Resetb = '0') then
-- synopsys translate_off
-- registered_addr <= x"08080808"; -- actually does not need any initialization
-- synopsys translate_on
latency_rd <= X"0"; -- actually does not need any initialization
count_rd <= X"0";
indx_rd := X"0"; -- actually does not need any initialization
elsif ( Clk'event and Clk='1') then
if ( ((DCE_ReadCache = '1') and (Abort_incoming_RD_int = '0')) and -- valid incoming read request
( (pending_rd_req = '0') or (DCE_ReadDone_int = '1') ) -- or (abort_all = '1') ) -- and no pending (= on going) request
-- July 14, 2011 Gandhi: commented out the bottom line and added the line above
--( (pending_rd_req = '0') or (DCE_ReadDone_int = '1') or (Abort_PrevRead = '1')) -- or (abort_all = '1') ) -- and no pending (= on going) request
) then -- i.e. a new request has been initiated;
-- we need to record the address of memory location to be read,
-- the latency pointed to by the index,
-- initiate count to zero, and
-- increment the index
-- synopsys translate_off
registered_addr <= read_addr(5 downto 0); -- need to change according to the width
-- synopsys translate_on
indx_rd := read_addr(5 downto 2); -- mod 16 of read addr
latency_rd <= latency_array_rd (CONV_INTEGER(unsigned(indx_rd)));
count_rd <= X"0";
elsif (pending_rd_req = '1') then
count_rd <= unsigned(count_rd) + 1;
else
count_rd <= X"0";
end if;
end if;
end process register_addr_and_latecy;
-------------------------------------------------------------------------------
DCE_ReadFlag_process :
process(Clk,Resetb)
begin
if (Resetb = '0') then
read_hit_flag <= '0';
elsif Clk'event and Clk = '1' then
if (DCE_ReadDone_int = '1' and Lsbuf_DCETaken = '0') then
read_hit_flag <= '1' ;
end if ;
if ((read_hit_flag = '1') and (Lsbuf_DCETaken = '1'))then
read_hit_flag <= '0';
end if;
end if ; -- end of clock if
end process;
-------------------------------------------------------------------------------
DCE_MemData <= data_out_mem;
DCE_ReadDone_comb_process:
process (pending_rd_req, latency_rd, count_rd, data_out_mem , read_hit_flag)
begin
if (((pending_rd_req = '1') and (latency_rd = count_rd)) or (read_hit_flag = '1')) then
DCE_ReadDone_int <= '1';
else
DCE_ReadDone_int <= '0';
end if;
end process DCE_ReadDone_comb_process;
-------------------------------------------------------------------------------
DCE_ReadBusy <= DCE_ReadBusy_int ;
DCE_ReadBusy_comb_process:
process (pending_rd_req, latency_rd, count_rd,
-- abort_all,
Abort_PrevRead_int , read_hit_flag , Lsbuf_DCETaken) -- July 14, 2011 Gandhi: changed Abort_PrevRead to Abort_PrevRead_int
begin
-- if ((abort_all = '1') or (Abort_PrevRead = '1')) then
-- if (Abort_PrevRead = '1') or (Abort_PrevRead_int = '1') then -- removed (Abort_PrevRead = '1')
if (Abort_PrevRead_int = '1') then
DCE_ReadBusy_int <= '0' ;
elsif ((pending_rd_req = '1') and (latency_rd /= count_rd)) then
DCE_ReadBusy_int <= '1';
elsif ((pending_rd_req = '1') and (latency_rd = count_rd) and (Lsbuf_DCETaken = '0')) then
DCE_ReadBusy_int <= '1';
elsif ((read_hit_flag = '1') and (Lsbuf_DCETaken = '0')) then
DCE_ReadBusy_int <= '1' ;
else
DCE_ReadBusy_int <= '0' ;
end if;
end process DCE_ReadBusy_comb_process;
-------------------------------------------------------------------------------
-------------------------------------------------------
SB_info_tranfer: process ( Clk, Resetb )
begin
if (Resetb = '0') then
-- Cache_Write <= '0';
SBreg_data <= (others => '0');
SBreg_addr <= (others => '0');
elsif Clk'event and Clk = '1' then
if (SB_WriteCache = '1' and DCE_WriteBusy_int = '0') then
SBreg_data <= SB_DataDmem ;
SBreg_addr <= SB_AddrDmem ;
end if ;
end if;
end process SB_info_tranfer;
WriteEnable <= SB_WriteCache when (DCE_WriteBusy_int = '0') else '1' ;
AddrDmem <= SB_AddrDmem(7 downto 2) when (DCE_WriteBusy_int = '0') else SBreg_addr(7 downto 2) ;
DataDmem <= SB_DataDmem when (DCE_WriteBusy_int = '0') else SBreg_data;
-------------------------------------------------------------------------------
DCE_WriteDone <= DCE_WriteDone_int ; -- DCE_WriteDone port is assigned with internal DCE_WriteDone_int
DCE_WriteBusy <= DCE_WriteBusy_int ;
-------------------------------------------------------------------------------
pending_wr_req_two_state_state_machine: process ( Clk, Resetb )
begin
if (Resetb = '0') then
pending_wr_req <= '0';
elsif Clk'event and Clk = '1' then
case pending_wr_req is
when '0' =>
if SB_WriteCache = '1' then
pending_wr_req <= '1';
end if;
when others => -- i.e. when '1' =>
if ( ( (DCE_WriteDone_int = '1')) and (SB_WriteCache = '0') ) then
--if (DCE_ReadCache = '0' ) then
pending_wr_req <= '0';
end if;
end case;
end if;
end process pending_wr_req_two_state_state_machine;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
register_addr_and_wr_latecy: process ( Clk, Resetb )
variable indx_wr : std_logic_vector ( 3 downto 0);
begin
if (Resetb = '0') then
-- synopsys translate_off
-- registered_SB_AddrDmem <= b"001000"; -- actually does not need any initalization
-- synopsys translate_on
latency_wr <= X"0"; -- actually does not need any initialization
count_wr <= X"0";
indx_wr := X"0"; -- actually does not need any initialization
elsif ( Clk'event and Clk='1') then
if ( ( SB_WriteCache = '1') and
( (pending_wr_req = '0') or (DCE_WriteDone_int = '1'))
) then -- i.e. a new request has been initiated;
-- we need to record the address of memory location to be read,
-- the latency pointed to by the index,
-- initiate count to zero, and
-- increment the index
-- synopsys translate_off
registered_SB_AddrDmem <= SB_AddrDmem(5 downto 0); -- need to change according to the width
-- synopsys translate_on
indx_wr := SB_AddrDmem(5 downto 2); -- mod 16 of SB_AddrDmem
latency_wr <= latency_array_wr (CONV_INTEGER(unsigned(indx_wr)));
count_wr <= X"0";
elsif (pending_wr_req = '1') then
count_wr <= unsigned(count_wr) + 1;
else
count_wr <= X"0";
end if;
end if;
end process register_addr_and_wr_latecy;
-------------------------------------------------------------------------------
DCE_WriteDone_comb_process:
process (pending_wr_req, latency_wr, count_wr, SB_DataDmem)
begin
if ((pending_wr_req = '1') and (latency_wr = count_wr)) then
DCE_WriteDone_int <= '1';
-- data_out <= data_out_mem;
else
DCE_WriteDone_int <= '0';
-- data_out <= (others => 'X'); -- don't care
end if;
end process DCE_WriteDone_comb_process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
write_busy_comb_process:
process (pending_wr_req, latency_wr, count_wr)
begin
if ((pending_wr_req = '1') and (latency_wr /= count_wr)) then
DCE_WriteBusy_int <= '1';
else
DCE_WriteBusy_int <= '0';
end if;
end process write_busy_comb_process;
-------------------------------------------------------------------------------
end behv;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/FIFO_DDR_DATA_IN/simulation/fg_tb_pkg.vhd | 1 | 11334 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT FIFO_DDR_DATA_IN_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| gpl-2.0 |
cheehieu/tomasulo-processor | sw/tomasulo_1/Instruction_streams_packages/i_fetch_test_stream_summation.vhd | 3 | 6986 | -- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"00002020_00001820_01401020_0080F820", -- Loc 0C, 08, 04, 00
X"00000020_00003820_00003020_00002820", -- Loc 1C, 18, 14, 10
X"00C53020_8C850000_007F2019_005F3819", -- Loc 2C, 28, 24, 20
X"1000FFF9_10620001_00611820_ACE60000", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- 0080F820 -- ADD $31, $4, $0 -- $31 = 4
-- 01401020 -- ADD $2, $10, $0 -- num_of_items = 10
-- 00001820 -- ADD $3, $0, $0 -- read_index = 0
-- 00002020 -- ADD $4, $0, $0 -- read_addr = 0
-- 00002820 -- ADD $5, $0, $0 -- read_val = 0
-- 00003020 -- ADD $6, $0, $0 -- sum = 0
-- 00003820 -- ADD $7, $0, $0 -- write_addr = 0
-- 00000020 -- noop
-- 005F3819 -- MUL $7, $2, $31 -- write_addr = num_of_items * 4
-- 007F2019 -- MUL $4, $3, $31 -- read_addr = index * 4
-- 8C850000 -- LW $5 ,0( $4) -- read_val = M(read_addr)
-- 00C53020 -- Add $6, $6, $5 -- sum = sum + value
-- ACE60000 -- SW $6 ,0( $7) -- M(write_addr) = sum
-- 00611820 -- Add $3, $3, $1 -- index++
-- 10620001 -- BEQ $3 ,$2 ,1 -- (index = num_of_items)?
-- 1000FFF9 -- BEQ $0 ,$0 ,-7 -- jmp
-- 00000020 -- noop
--
-- REGISTERS
-- $0 --> 0
-- $1 --> 1
-- $2 --> 10 num_of_items
-- $3 --> 0 read index
-- $4 --> 0 read addr
-- $5 --> 0 mem_value
-- $6 --> 0 sum
-- $7 --> 0 write addr (0 for version 1, 40 for version 2)
-- $31 --> 4 for address calculation
--
-- MEM
-- Put first n numbers starting from the beginning of the memory.
-- You will get the sum of them at n+1
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/GC_fifo/simulation/fg_tb_top.vhd | 2 | 5679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 37
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_data_send_fifo/example_design/pcie_data_send_fifo_top.vhd | 1 | 6001 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_data_send_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_data_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_data_send_fifo_top;
architecture xilinx of pcie_data_send_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_data_send_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_data_send_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_data_rec_fifo/simulation/fg_tb_pctrl.vhd | 2 | 20672 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/read_data_fifo_0/simulation/fg_tb_synth.vhd | 1 | 11500 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 14,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : read_data_fifo_0_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/read_data_fifo_0/simulation/fg_tb_pctrl.vhd | 5 | 18527 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 |
Daverball/reconos | demos/reconf_led/hw/hwt_led_off_v1_00_a/hdl/vhdl/hwt_led_off.vhd | 2 | 3398 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_off is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_off;
architecture imp of hwt_led_off is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '0';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
| gpl-2.0 |
apimanagement/drupalportal | ibm_apim/swaggereditor/app/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| gpl-2.0 |
Daverball/reconos | demos/sort_demo/hw/hwt_sort_demo_v1_00_c/hdl/vhdl/bubble_sorter.vhd | 4 | 6023 | --
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
| gpl-2.0 |
phil91stud/protocol_hdl | SPI_master/hdl/spi_master.vhd | 1 | 3774 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
clk_freq : natural := 50000000; -- 50 MHz
spi_freq : natural := 1000000; -- 1 MHz
pre_delay : natural := 10; -- us
post_delay : natural := 10;
wordlength : natural := 16
);
port (
clk : in std_logic;
start_tx : in std_logic;
tx_done : out std_logic;
rx_data : out std_logic_vector(wordlength-1 downto 0);
tx_data : in std_logic_vector(wordlength-1 downto 0);
-- spi mode configuration
cpol : in std_logic;
cpha : in std_logic;
-- spi pins
mosi : out std_logic;
miso : in std_logic;
sclk : out std_logic;
ss : out std_logic -- more cs via demux
);
end entity spi_master;
architecture behavorial of spi_master is
constant clk_delay : natural := (clk_freq/(2*spi_freq))-1;
signal delay : natural range 0 to clk_delay + 1;
signal delay_pre : natural range 0 to (pre_delay*(clk_freq/1000))/1000;
signal delay_post : natural range 0 to (post_delay*(clk_freq/1000))/1000;
type tx_state_t is (spi_stx, del_pre, spi_active, del_post, spi_etx);
signal spistate : tx_state_t := spi_stx;
type clockstate_t is (propagate, capture);
signal clockstate : clockstate_t;
signal bits_to_transmit : natural range 0 to wordlength;
signal tx_reg : std_logic_vector(wordlength-1 downto 0) := (others => '0');
signal rx_reg : std_logic_vector(wordlength-1 downto 0) := (others => '0');
begin
main_proc:
process(clk,start_tx,tx_data,cpol,cpha)
begin
if rising_edge(clk) then
MOSI <= tx_reg(tx_reg'left); -- msb in register
if(delay > 0) then
delay <= delay - 1; -- counter for sclk generation
else
delay <= clk_delay;
end if;
case spistate is
when spi_stx =>
delay_post <= (post_delay*(clk_freq/1000))/1000;
delay_pre <= (pre_delay*(clk_freq/1000))/1000;
ss <= '1';
tx_done <= '0';
sclk <= cpol;
bits_to_transmit <= wordlength;
if start_tx = '1' then
spistate <= del_pre;
end if;
when del_pre =>
ss <= '0';
sclk <= cpol;
delay <= 0;
if delay_pre > 0 then
delay_pre <= delay_pre - 1;
else
spistate <= spi_active;
end if;
case cpha is
when '1' => clockstate <= propagate;
when '0' => clockstate <= capture;
when others => clockstate <= capture;
end case;
when spi_active =>
-- TODO
case clockstate is
when capture =>
sclk <= (cpol xor cpha);
if delay = 0 then
clockstate <= propagate;
if cpha = '1' then
bits_to_transmit <= bits_to_transmit - 1;
end if;
end if;
when propagate =>
sclk <= not (cpol xor cpha);
if delay = 0 then
clockstate <= capture;
if cpha = '0' then
bits_to_transmit <= bits_to_transmit - 1;
end if;
end if;
end case;
if delay = 0 and bits_to_transmit = 0 then
spistate <= del_post;
sclk <= cpol;
end if;
when del_post =>
sclk <= cpol;
if (delay_post > 0) then
delay_post <= delay_post - 1;
else
spistate <= spi_etx;
ss <= '1';
end if;
when spi_etx =>
tx_done <= '1';
rx_data <= rx_reg;
if start_tx = '0' then
spistate <= spi_stx;
end if;
end case;
end if;
end process main_proc;
shift_proc:
process(clk,spistate,rx_reg,tx_reg,miso)
begin
if rising_edge(clk) then
if spistate = spi_active and clockstate = capture and delay = 0 and bits_to_transmit /= 0 then
rx_reg <= rx_reg(rx_reg'left-1 downto 0) & miso;
end if;
if spistate = spi_active and clockstate = propagate and delay = 0 and bits_to_transmit /= 0 then
tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '1';
end if;
if spistate = spi_stx then
tx_reg <= tx_data;
end if;
end if;
end process shift_proc;
end architecture behavorial;
| gpl-2.0 |
meriororen/i2s-interface-vhdl | i2s_tb.vhd | 1 | 4026 | library ieee;
use ieee.std_logic_1164.all;
entity i2s_tb is
generic ( DATA_WIDTH : integer := 24;
BITPERFRAME : integer := 64);
end i2s_tb;
architecture behavioral of i2s_tb is
signal clk_50 : std_logic;
signal dac_d : std_logic;
signal adc_d : std_logic;
signal bclk : std_logic;
signal lrclk : std_logic;
signal dstim : std_logic_vector(63 downto 0) := x"aaaaeeeebbbb5555";
signal sample : std_logic_vector(DATA_WIDTH - 1 downto 0) := x"fafafa";
constant period : time := 20 ns;
constant bclk_period : time := 32552 ns / BITPERFRAME;
signal zbclk, zzbclk, zzzbclk : std_logic;
signal neg_edge, pos_edge : std_logic;
signal wdth : integer := DATA_WIDTH;
signal cnt : integer := 0;
signal toggle : std_logic := '1';
signal new_sample : std_logic := '0';
signal sample_out : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal valid : std_logic;
signal ready : std_logic := '1';
signal rst : std_logic := '0';
component i2s_interface is
generic ( DATA_WIDTH : integer range 16 to 32;
BITPERFRAME: integer );
port (
clk : in std_logic;
reset : in std_logic;
bclk : in std_logic;
lrclk : in std_logic;
sample_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
sample_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
dac_data : out std_logic;
adc_data : in std_logic;
valid : out std_logic;
ready : out std_logic
);
end component;
begin
-- Instantiate
DUT : i2s_interface
generic map ( DATA_WIDTH => DATA_WIDTH,
BITPERFRAME => BITPERFRAME )
port map (
clk => clk_50,
reset => rst,
bclk => bclk,
lrclk => lrclk,
sample_out => sample_out,
sample_in => sample,
dac_data => dac_d,
adc_data => adc_d,
valid => valid,
ready => ready
);
clk_proc : process
begin
clk_50 <= '0';
wait for period/2;
clk_50 <= '1';
wait for period/2;
end process;
-- lrclk <= lrstim(lrstim'high);
i2s_bclk : process
begin
bclk <= '0';
-- lrstim <= lrstim(lrstim'high - 1 downto 0) & lrstim(lrstim'high);
wait for bclk_period/2;
-- lrstim <= lrstim(lrstim'high - 1 downto 0) & lrstim(lrstim'high);
bclk <= '1';
wait for bclk_period/2;
end process;
detect : process(clk_50)
begin
if rising_edge(clk_50) then
zbclk <= bclk;
zzbclk <= zbclk;
zzzbclk <= zzbclk;
if zzbclk = '1' and zzzbclk = '0' then
neg_edge <= '1';
elsif zzbclk = '0' and zzzbclk = '1' then
pos_edge <= '1';
else
neg_edge <= '0';
pos_edge <= '0';
end if;
end if;
end process;
lrclk <= toggle;
i2s_lrclk : process(bclk)
begin
if rising_edge(bclk) then
if cnt < BITPERFRAME/2 - 1 then
cnt <= cnt + 1;
elsif cnt = BITPERFRAME/2 - 1 then
cnt <= 0;
end if;
end if;
if falling_edge(bclk) then
if cnt >= BITPERFRAME/2 - 1 then
toggle <= not toggle;
else
if cnt = 0 then
new_sample <= '1';
elsif cnt >= wdth then
new_sample <= '0';
end if;
end if;
end if;
end process;
adc_d <= dstim(dstim'high);
i2s_data : process(bclk)
begin
if falling_edge(bclk) then
if new_sample = '1' then
dstim <= dstim(dstim'high - 1 downto 0) & dstim(dstim'high);
end if;
end if;
if rising_edge(clk_50) then
if ready = '1' then
sample <= dstim(dstim'high downto dstim'high - DATA_WIDTH + 1);
else
sample <= (others => '0');
end if;
end if;
end process;
end behavioral;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/enumsystem.vhd | 4 | 2181 | ------------------------------------------------------------------------------
-- Author: Oswaldo Cadenas
-- Date: September 27 2011
--
-- Summary: This system runs an internal counter 0,1,2, ..., 7, 0, 1,
-- and also accepts an enable signal
-- it generates an output y (4 bits) as:
-- if (e = 0) y = 0000
-- if (e = 1) then
-- y = 1000 when counter is 0
-- y = 0100 when counter is 1
-- y = 0010 when counter is 2
-- y = 0001 when counter is 3
-- y = 1111 other count
-- internaly the design uses some enumartion arguments for decoding and encoding
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity enumsystem is
port (clk, reset: in std_logic;
en: in std_logic; -- enable
y: out std_logic_vector (0 to 3) ); -- decoded output
end enumsystem;
architecture enumsystem_rtl of enumsystem is
type States is (zero, one, two, three, other);
signal mystate: States;
signal Counter: std_logic_vector (2 downto 0);
begin
SmallCounter : process (clk, reset)
begin
if ( clk'event and clk = '1') then
if (reset = '1') then
Counter <= (others => '0');
else
Counter <= Counter + 1;
end if;
end if;
end process;
encoding_process: process (Counter)
begin
case Counter is
when "000" => mystate <= zero;
when "001" => mystate <= one;
when "010" => mystate <= two;
when "011" => mystate <= three;
when others => mystate <= other;
end case;
end process;
decoding_process: process (mystate, en)
begin
if (en = '1') then
case mystate is
when zero => y <= "1000";
when one => y <= "0100";
when two => y <= "0010";
when three => y <= "0001";
when others => y <= "1111";
end case;
else
y <= "0000";
end if;
end process;
end enumsystem_rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_test7.vhd | 2 | 662 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity dummy is
port (
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(input)
variable tmp : std_logic_vector(7 downto 0);
begin
tmp := input; -- use multiple assignments to the same variable
tmp := (7 => input(7), others => '1'); -- inluding slices in a process
output <= tmp;
end process;
end;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_test1.vhd | 2 | 607 | --
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mask is
port (input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0)
);
end;
architecture behaviour of mask is
begin
L: process(input)
variable tmp : std_logic_vector(15 downto 0);
begin
output <= tmp; --this shouln't really change anything
tmp := input;
tmp := tmp and "1010101010101010";
output <= tmp;
end process;
end;
| gpl-2.0 |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/tbd_rr_base_tb.vhd | 1 | 9426 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_rr_base is
end tb_rr_base;
architecture bhv of tb_rr_base is
----------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------
-- System
constant c_spi_rate : natural := 99E5; -- Should be something weird => Detect more errors
constant c_bit_with_half_t : time := 1E9 ns / c_spi_rate;
constant c_byte_pad_t : time := 5 * c_bit_with_half_t;
constant SPI_USER_CS_IDX : natural := 1;
-- User
constant c_clk_frequency : natural := 50E6;
constant c_use_issi_sdram : std_ulogic := '1';
constant c_use_sdram_pll : std_ulogic := '1';
-- Derived
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal keys : std_ulogic_vector(1 downto 0);
signal switches : std_ulogic_vector(3 downto 0);
signal leds : std_ulogic_vector(7 downto 0);
signal gdb_tx : std_ulogic := '1';
signal gdb_rx : std_ulogic;
signal spi_cs : std_ulogic_vector(1 downto 0) := (others => '1');
signal spi_clk : std_ulogic := '0';
signal spi_mosi : std_ulogic := '0';
signal spi_miso : std_ulogic := '0';
signal spi_epcs_cs : std_ulogic;
signal spi_epcs_clk : std_ulogic;
signal spi_epcs_mosi : std_ulogic;
signal spi_epcs_miso : std_ulogic;
signal arReconf : std_ulogic;
signal sdram_addr : std_logic_vector(12 downto 0);
signal sdram_ba : std_logic_vector(1 downto 0);
signal sdram_cke : std_logic;
signal sdram_clk : std_logic;
signal sdram_cs_n : std_logic;
signal sdram_dq : std_logic_vector(15 downto 0);
signal sdram_dqm : std_logic_vector(1 downto 0);
signal sdram_cas_n : std_logic;
signal sdram_ras_n : std_logic;
signal sdram_we_n : std_logic;
signal sdram_ctrl_str : string(1 to 5);
begin
clk <= not clk after 1E9 ns / (2 * c_clk_frequency);
keys <= (others => '1');
switches <= (others => '0');
testbed: entity work.tbd_rr_base(rtl)
generic map
(
use_sdram_pll => c_use_sdram_pll
)
port map
(
clock_50mhz => clk,
keys => keys,
switches => switches,
leds => leds,
uart_rx => gdb_tx,
uart_tx => gdb_rx,
spi_cs => spi_cs,
spi_clk => spi_clk,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
spi_epcs_cs => spi_epcs_cs,
spi_epcs_clk => spi_epcs_clk,
spi_epcs_mosi => spi_epcs_mosi,
spi_epcs_miso => spi_epcs_miso,
arReconf => arReconf,
sdram_addr => sdram_addr,
sdram_ba => sdram_ba,
sdram_cke => sdram_cke,
sdram_clk => sdram_clk,
sdram_cs_n => sdram_cs_n,
sdram_dq => sdram_dq,
sdram_dqm => sdram_dqm,
sdram_cas_n => sdram_cas_n,
sdram_ras_n => sdram_ras_n,
sdram_we_n => sdram_we_n
);
altera_sdram : if (c_use_issi_sdram = '0') generate
eSDRAM : entity work.sdram_0_test_component(europa)
port map
(
-- inputs:
clk => sdram_clk,
ZS_ADDR => sdram_addr,
zs_ba => sdram_ba,
zs_cas_n => sdram_cas_n,
zs_cke => sdram_cke,
zs_cs_n => sdram_cs_n,
zs_dqm => sdram_dqm,
zs_ras_n => sdram_ras_n,
zs_we_n => sdram_we_n,
-- outputs:
zs_dq => sdram_dq
);
end generate;
issi_sdram : if (c_use_issi_sdram = '1') generate
eSDRAM_issi : entity work.IS42S16160
port map
(
Dq => sdram_dq,
Addr => sdram_addr,
Ba => sdram_ba,
Clk => sdram_clk,
Cke => sdram_cke,
Cs_n => sdram_cs_n,
Ras_n => sdram_ras_n,
Cas_n => sdram_cas_n,
We_n => sdram_we_n,
Dqm => sdram_dqm
);
end generate;
sdram_ctrl_debug: process(sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n)
variable ctrl_vect : std_logic_vector(2 downto 0);
begin
ctrl_vect := sdram_ras_n & sdram_cas_n & sdram_we_n;
if(sdram_cs_n = '1')then
sdram_ctrl_str <= "DESL ";
else
case ctrl_vect is
when "111" =>
sdram_ctrl_str <= "NOP ";
when "101" =>
sdram_ctrl_str <= "READ ";
when "100" =>
sdram_ctrl_str <= "WRITE";
when "011" =>
sdram_ctrl_str <= "ACT ";
when "010" =>
sdram_ctrl_str <= "PALL ";
when "001" =>
sdram_ctrl_str <= "REF ";
when "000" =>
sdram_ctrl_str <= "MRS ";
when others =>
sdram_ctrl_str <= "??? ";
end case;
end if;
end process;
----------------------------------------------------------------------------------------------------------------------------
-- Testing process
Stimu : process
procedure spi_send_byte(dat : in std_ulogic_vector(7 downto 0)) is
begin
for i in 7 downto 0 loop
spi_mosi <= dat(i);
wait for c_bit_with_half_t;
spi_clk <= '1';
wait for c_bit_with_half_t;
spi_clk <= '0';
end loop;
spi_mosi <= '0';
end procedure;
procedure spi_send_rgb(red : in std_ulogic_vector(7 downto 0); green : in std_ulogic_vector(7 downto 0); blue : in std_ulogic_vector(7 downto 0)) is
begin
wait for c_byte_pad_t;
wait for c_byte_pad_t;
spi_cs(SPI_USER_CS_IDX) <= '0';
wait for c_byte_pad_t;
spi_send_byte(X"00"); -- Dummy address
wait for c_byte_pad_t;
spi_send_byte(X"00");
wait for c_byte_pad_t;
spi_send_byte(red);
wait for c_byte_pad_t;
spi_send_byte(green);
wait for c_byte_pad_t;
spi_send_byte(blue);
wait for c_byte_pad_t;
-- spi_send_byte(X"11"); -- Test byte
spi_cs(SPI_USER_CS_IDX) <= '1';
wait for c_byte_pad_t;
wait for c_byte_pad_t;
end procedure;
begin
-- ########################################################################################################
-----------------------------------------------------------------------------------------------------------
-- Testing Code
wait for 200 ns;
spi_send_rgb(X"AB", X"CD", X"EF");
spi_send_rgb(X"00", X"01", X"FE");
spi_send_rgb(X"00", X"FF", X"FE");
wait for 20 us;
spi_send_rgb(X"01", X"FE", X"FF");
-----------------------------------------------------------------------------------------------------------
-- ########################################################################################################
assert false report "SIMULATION ENDED SUCCESSFULLY" severity note;
wait;
end process;
----------------------------------------------------------------------------------------------------------------------------
end bhv;
| gpl-2.0 |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/altremote_pulsed.vhd | 3 | 7770 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0_Nano_Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.global.all;
entity altremotePulsed is
port
(
clock : in std_ulogic;
nResetAsync : in std_ulogic;
reconf : in std_ulogic -- One clock cycle high => Reconf
);
end entity altremotePulsed;
architecture rtl of altremotePulsed is
component altremote is
port (
read_param : in std_logic := 'X'; -- read_param
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
write_param : in std_logic := 'X'; -- write_param
data_in : in std_logic_vector(23 downto 0) := (others => 'X') -- data_in
);
end component altremote;
type STATEMACHINE_STEP_TYPE is
(
SM_INIT, SM_SET_RESET, SM_WRITE_BOOT_ADDRESS, SM_TURN_OFF_WDT, SM_SET_EARLY_CONF_DONE_CHECK, SM_WRITE_PARAM, SM_WAIT_BUSY, SM_IDLE, SM_RECONF_READY
);
type REG_TYPE is record
sm_step : STATEMACHINE_STEP_TYPE;
sm_step_ret : STATEMACHINE_STEP_TYPE;
param : std_logic_vector(2 downto 0);
data_in : std_logic_vector(23 downto 0);
ar_reset_cnt : natural;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
sm_step => SM_INIT,
sm_step_ret => SM_INIT,
param => "000",
data_in => (others => '0'),
ar_reset_cnt => 0
);
signal R, NxR : REG_TYPE;
signal clk_3 : std_ulogic;
signal ar_data_in : std_logic_vector(23 downto 0);
signal ar_param : std_logic_vector(2 downto 0);
signal ar_reconfig : std_logic;
signal ar_reset : std_logic;
signal ar_write_param : std_logic;
signal ar_busy : std_logic;
begin
altremote_inst : altremote
port map
(
clock => clk_3,
data_in => ar_data_in,
param => ar_param,
read_param => '0',
read_source => "00",
reconfig => ar_reconfig,
reset => ar_reset,
reset_timer => '0',
write_param => ar_write_param,
busy => ar_busy,
data_out => open
);
eALTREMOTE_CLK: entity work.frequencyDivider(rtl)
generic map
(
divideBy => 16
)
port map
(
clock => clock,
nResetAsync => nResetAsync,
output => clk_3
);
proc_comb: process(R, reconf, ar_busy)
begin
NxR <= R;
-- standard values
ar_data_in <= (others => '0');
ar_param <= "000";
ar_write_param <= '0';
ar_reconfig <= '0';
ar_reset <= '0';
-- fsm
case R.sm_step is
when SM_IDLE =>
if(reconf = '0')then
NxR.sm_step <= SM_RECONF_READY;
end if;
when SM_RECONF_READY =>
if(reconf = '1')then
ar_reconfig <= '1';
end if;
when SM_INIT =>
NxR.sm_step <= SM_SET_RESET;
when SM_SET_RESET =>
ar_reset <= '1';
if(R.ar_reset_cnt = 15)then
NxR.sm_step <= SM_WRITE_BOOT_ADDRESS;
else
NxR.ar_reset_cnt <= R.ar_reset_cnt + 1;
end if;
when SM_WRITE_BOOT_ADDRESS =>
NxR.param <= "100";
NxR.data_in <= (others => '0');
NxR.sm_step <= SM_WRITE_PARAM;
NxR.sm_step_ret <= SM_TURN_OFF_WDT;
when SM_TURN_OFF_WDT =>
NxR.param <= "011";
NxR.data_in <= (others => '0');
NxR.sm_step <= SM_WRITE_PARAM;
NxR.sm_step_ret <= SM_SET_EARLY_CONF_DONE_CHECK;
when SM_SET_EARLY_CONF_DONE_CHECK =>
NxR.param <= "001";
NxR.data_in <= (others => '1');
NxR.sm_step <= SM_WRITE_PARAM;
NxR.sm_step_ret <= SM_IDLE;
when SM_WRITE_PARAM =>
ar_param <= R.param;
ar_data_in <= R.data_in;
ar_write_param <= '1';
if(ar_busy = '1')then
NxR.sm_step <= SM_WAIT_BUSY;
end if;
when SM_WAIT_BUSY =>
ar_data_in <= R.data_in;
if(ar_busy = '0')then
NxR.sm_step <= R.sm_step_ret;
end if;
when others =>
null;
end case;
end process;
proc_reg: process(nResetAsync, clock)
begin
if(nResetAsync = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_and_gate.vhd | 8 | 295 | library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity and_gate;
architecture rtl of and_gate is
begin
c_o <= a_i and b_i;
end architecture rtl;
| gpl-2.0 |
orsonmmz/ivtest | ivltests/vhdl_notg_bit.vhd | 4 | 249 | library IEEE;
use IEEE.numeric_bit.all;
entity not_gate is
port (
a_i : in bit; -- inputs
c_o : out bit -- output
);
end entity not_gate;
architecture rtl of not_gate is
begin
c_o <= not a_i;
end architecture rtl;
| gpl-2.0 |
DSP-Crowd/software | apps/rpi-gpio-ext/de0_nano/src/gpio-ext.vhd | 1 | 6472 | -----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DSP-Crowd project --
-- https://www.dsp-crowd.com --
-- --
-- Author(s): --
-- - Johannes Natter, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2017 Authors and www.dsp-crowd.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpio_ext is
generic
(
my_id : natural := 0
);
port
(
clock : in std_ulogic;
n_reset_async : in std_ulogic;
spi_cs : in std_ulogic;
data : in std_ulogic_vector(7 downto 0);
data_is_id : in std_ulogic;
data_valid : in std_ulogic;
input_state : out std_ulogic;
input_state_valid : out std_ulogic;
cmd_done : out std_ulogic;
gpio_in : in std_ulogic;
gpio_out : out std_ulogic;
gpio_en : out std_ulogic
);
begin
assert (my_id >= 0)
report "gpio_ext: id must be at least 1"
severity error;
end gpio_ext;
architecture rtl of gpio_ext is
type STATEMACHINE_MAIN_STEP_TYPE is
(
SM_WAIT_SELECTED, SM_GET_CMD, SM_CHECK_CMD, SM_GET_INPUT, SM_GET_DUMMY, SM_SET_OUTPUT, SM_GET_COUNTER_MAX, SM_GET_COUNTER_MID
);
type GPIO_TYPE is
(
GPIO_INPUT, GPIO_OUTPUT, GPIO_PWM
);
subtype BYTE_IDX_TYPE is integer range 0 to 3;
type REG_TYPE is record
sm_step : STATEMACHINE_MAIN_STEP_TYPE;
data : std_ulogic_vector(7 downto 0);
counter : natural;
counter_max : natural;
counter_mid : natural;
byte_idx : BYTE_IDX_TYPE;
tmp : std_ulogic_vector(23 downto 0);
gpio_type : GPIO_TYPE;
gpio : std_ulogic;
end record;
constant RSET_INIT_VAL : REG_TYPE :=
(
sm_step => SM_WAIT_SELECTED,
data => (others => '0'),
counter => 0,
counter_max => 0,
counter_mid => 0,
byte_idx => 0,
tmp => (others => '0'),
gpio_type => GPIO_INPUT,
gpio => '0'
);
signal R, NxR : REG_TYPE;
begin
proc_comb: process(R, spi_cs, data, data_is_id, data_valid, gpio_in)
begin
NxR <= R;
input_state <= '0';
input_state_valid <= '0';
cmd_done <= '0';
gpio_out <= R.gpio;
if(R.gpio_type = GPIO_OUTPUT or R.gpio_type = GPIO_PWM)then
gpio_en <= '1';
else
gpio_en <= '0';
end if;
if(R.gpio_type = GPIO_PWM)then
if(R.counter < R.counter_max - 1)then
NxR.counter <= R.counter + 1;
else
NxR.counter <= 0;
end if;
if(R.counter < R.counter_mid)then
NxR.gpio <= '1';
else
NxR.gpio <= '0';
end if;
end if;
case R.sm_step is
when SM_WAIT_SELECTED =>
if(data_is_id = '1' and to_integer(unsigned(data)) = my_id)then
NxR.sm_step <= SM_GET_CMD;
end if;
when SM_GET_CMD =>
if(data_valid = '1')then
NxR.data <= data;
NxR.sm_step <= SM_CHECK_CMD;
end if;
when SM_CHECK_CMD =>
if(R.data(1 downto 0) = "00")then -- read
NxR.gpio_type <= GPIO_INPUT;
NxR.sm_step <= SM_GET_INPUT;
elsif(R.data(1 downto 0) = "01")then -- write
NxR.gpio_type <= GPIO_OUTPUT;
NxR.sm_step <= SM_SET_OUTPUT;
else -- pwm
NxR.byte_idx <= 3;
NxR.sm_step <= SM_GET_COUNTER_MAX;
end if;
when SM_GET_INPUT =>
input_state <= gpio_in;
input_state_valid <= '1';
NxR.sm_step <= SM_GET_DUMMY;
when SM_GET_DUMMY =>
if(data_valid = '1')then
cmd_done <= '1';
NxR.sm_step <= SM_WAIT_SELECTED;
end if;
when SM_SET_OUTPUT =>
if(data_valid = '1')then
cmd_done <= '1';
NxR.gpio <= data(0);
NxR.sm_step <= SM_WAIT_SELECTED;
end if;
when SM_GET_COUNTER_MAX =>
if(data_valid = '1')then
if(R.byte_idx = 0)then
NxR.counter_max <= to_integer(unsigned(R.tmp & data));
NxR.byte_idx <= 3;
NxR.sm_step <= SM_GET_COUNTER_MID;
else
NxR.tmp(8 * R.byte_idx - 1 downto 8 * (R.byte_idx - 1)) <= data;
NxR.byte_idx <= R.byte_idx - 1;
end if;
end if;
when SM_GET_COUNTER_MID =>
if(data_valid = '1')then
if(R.byte_idx = 0)then
NxR.counter_mid <= to_integer(unsigned(R.tmp & data));
NxR.gpio_type <= GPIO_PWM;
cmd_done <= '1';
NxR.sm_step <= SM_WAIT_SELECTED;
else
NxR.tmp(8 * R.byte_idx - 1 downto 8 * (R.byte_idx - 1)) <= data;
NxR.byte_idx <= R.byte_idx - 1;
end if;
end if;
when others =>
NxR.sm_step <= SM_WAIT_SELECTED;
end case;
if(spi_cs = '1')then
NxR.sm_step <= SM_WAIT_SELECTED;
end if;
end process;
proc_reg: process(n_reset_async, clock)
begin
if(n_reset_async = '0')then
R <= RSET_INIT_VAL;
elsif(clock'event and clock = '1')then
R <= NxR;
end if;
end process;
end architecture rtl;
| gpl-2.0 |
bjandre/ctags-fortran | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
diecaptain/unscented_kalman_mppt | k_ukf_Uofk.vhd | 1 | 2294 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Uofk is
port (
I : in std_logic_vector(31 downto 0);
Isc : in std_logic_vector(31 downto 0);
Vactofk : in std_logic_vector(31 downto 0);
D : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
clock : in std_logic;
Uofk : out std_logic_vector(31 downto 0)
);
end k_ukf_Uofk;
architecture struct of k_ukf_Uofk is
component k_ukf_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_exp IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2,Z3,Z4,Z5,Z6 : std_logic_vector(31 downto 0);
signal Z : std_logic_vector(31 downto 0) := "00111111100000000000000000000000";
begin
M1 : k_ukf_sub port map
( clock => clock,
dataa => D,
datab => Z,
result => Z1);
M2 : k_ukf_mult port map
( clock => clock,
dataa => B,
datab => Z1,
result => Z2);
M3 : k_ukf_exp port map
( clock => clock,
data => Z2,
result => Z3);
M4 : k_ukf_mult port map
( clock => clock,
dataa => D,
datab => Z3,
result => Z4);
M5 : k_ukf_mult port map
( clock => clock,
dataa => Isc,
datab => Vactofk,
result => Z5);
M6 : k_ukf_mult port map
( clock => clock,
dataa => Z5,
datab => Z4,
result => Z6);
M7 : k_ukf_add port map
( clock => clock,
dataa => I,
datab => Z6,
result => Uofk);
end struct; | gpl-2.0 |
tmeissner/cryptocores | cbctdes/sim/vhdl/tb_cbctdes.vhd | 1 | 6148 | -- ======================================================================
-- CBC-DES encryption/decryption testbench
-- tests according to NIST 800-17 special publication
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_cbctdes is
end entity tb_cbctdes;
architecture rtl of tb_cbctdes is
type t_array is array (natural range <>) of std_logic_vector(0 to 63);
constant c_table_test_plain : t_array(0 to 18) :=
(x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
x"305532286D6F295A");
signal s_tdes_answers : t_array(0 to 19);
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_mode : std_logic := '0';
signal s_start : std_logic := '0';
signal s_iv : std_logic_vector(0 to 63) := (others => '0');
signal s_key1 : std_logic_vector(0 to 63) := (others => '0');
signal s_key2 : std_logic_vector(0 to 63) := (others => '0');
signal s_key3 : std_logic_vector(0 to 63) := (others => '0');
signal s_datain : std_logic_vector(0 to 63) := (others => '0');
signal s_validin : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic := '0';
component cbctdes is
port (
reset_i : in std_logic;
clk_i : in std_logic;
mode_i : in std_logic;
start_i : in std_logic;
iv_i : in std_logic_vector(0 to 63);
key1_i : in std_logic_vector(0 to 63);
key2_i : in std_logic_vector(0 TO 63);
key3_i : in std_logic_vector(0 TO 63);
data_i : in std_logic_vector(0 TO 63);
valid_i : in std_logic;
data_o : out std_logic_vector(0 TO 63);
valid_o : out std_logic;
ready_o : out std_logic
);
end component cbctdes;
begin
s_reset <= '1' after 100 ns;
s_clk <= not(s_clk) after 10 ns;
teststimuliP : process is
begin
s_start <= '0';
s_mode <= '0';
s_validin <= '0';
s_iv <= (others => '0');
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_datain <= (others => '0');
wait until s_reset = '1';
-- ENCRYPTION TESTS
-- cbc known answers test
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_ready = '1';
s_key1 <= x"1111111111111111";
s_key2 <= x"5555555555555555";
s_key3 <= x"9999999999999999";
s_validin <= '1';
s_datain <= c_table_test_plain(index);
if(index = 0) then
s_start <= '1';
end if;
wait until rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
end loop;
wait until rising_edge(s_clk);
s_mode <= '0';
s_start <= '0';
s_validin <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_datain <= (others => '0');
wait for 1 us;
-- DECRYPTION TESTS
-- cbc known answer test
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_ready = '1';
s_key1 <= x"1111111111111111";
s_key2 <= x"5555555555555555";
s_key3 <= x"9999999999999999";
s_mode <= '1';
s_validin <= '1';
s_datain <= s_tdes_answers(index);
if(index = 0) then
s_start <= '1';
end if;
wait until rising_edge(s_clk);
s_start <= '0';
s_validin <= '0';
s_mode <= '0';
end loop;
wait until rising_edge(s_clk);
s_mode <= '0';
s_start <= '0';
s_validin <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_datain <= (others => '0');
wait;
end process teststimuliP;
testcheckerP : process is
begin
report "# ENCRYPTION TESTS";
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_validout = '1';
s_tdes_answers(index) <= s_dataout;
end loop;
report "# DECRYPTION TESTS";
report "# tdes known answer test";
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_validout = '1';
assert (s_dataout = c_table_test_plain(index))
report "decryption error"
severity error;
end loop;
report "# Successfully passed all tests";
wait;
end process testcheckerP;
i_cbctdes : cbctdes
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
mode_i => s_mode,
iv_i => s_iv,
key1_i => s_key1,
key2_i => s_key2,
key3_i => s_key3,
data_i => s_datain,
valid_i => s_validin,
data_o => s_dataout,
valid_o => s_validout,
ready_o => s_ready
);
end architecture rtl;
| gpl-2.0 |
tmeissner/cryptocores | cbctdes/rtl/vhdl/tdes.vhd | 1 | 5085 | -- ======================================================================
-- TDES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity tdes is
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 TO 63); -- key input
key2_i : in std_logic_vector(0 TO 63); -- key input
key3_i : in std_logic_vector(0 TO 63); -- key input
data_i : in std_logic_vector(0 TO 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
data_o : out std_logic_vector(0 TO 63); -- data output
valid_o : out std_logic; -- output data valid flag
ready_o : out std_logic
);
end entity tdes;
architecture rtl of tdes is
component des is
port (
reset_i : in std_logic;
clk_i : IN std_logic; -- clock
mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : IN std_logic_vector(0 TO 63); -- key input
data_i : IN std_logic_vector(0 TO 63); -- data input
valid_i : IN std_logic; -- input key/data valid flag
data_o : OUT std_logic_vector(0 TO 63); -- data output
valid_o : OUT std_logic -- output data valid flag
);
end component des;
signal s_ready : std_logic;
signal s_mode : std_logic;
signal s_des2_mode : std_logic;
signal s_des1_validin : std_logic := '0';
signal s_des1_validout : std_logic;
signal s_des2_validout : std_logic;
signal s_des3_validout : std_logic;
signal s_key1 : std_logic_vector(0 to 63);
signal s_key2 : std_logic_vector(0 to 63);
signal s_key3 : std_logic_vector(0 to 63);
signal s_des1_key : std_logic_vector(0 to 63);
signal s_des3_key : std_logic_vector(0 to 63);
signal s_des1_dataout : std_logic_vector(0 to 63);
signal s_des2_dataout : std_logic_vector(0 to 63);
begin
ready_o <= s_ready;
valid_o <= s_des3_validout;
s_des2_mode <= not(s_mode);
s_des1_validin <= valid_i and s_ready;
s_des1_key <= key1_i when mode_i = '0' else key3_i;
s_des3_key <= s_key3 when s_mode = '0' else s_key1;
inputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_mode <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1') then
s_mode <= mode_i;
s_key1 <= key1_i;
s_key2 <= key2_i;
s_key3 <= key3_i;
end if;
end if;
end process inputregister;
outputregister : process(clk_i, reset_i) is
begin
if(reset_i = '0') then
s_ready <= '1';
elsif(rising_edge(clk_i)) then
if(valid_i = '1' and s_ready = '1') then
s_ready <= '0';
end if;
if(s_des3_validout = '1') then
s_ready <= '1';
end if;
end if;
end process outputregister;
i1_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => mode_i,
key_i => s_des1_key,
data_i => data_i,
valid_i => s_des1_validin,
data_o => s_des1_dataout,
valid_o => s_des1_validout
);
i2_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_des2_mode,
key_i => s_key2,
data_i => s_des1_dataout,
valid_i => s_des1_validout,
data_o => s_des2_dataout,
valid_o => s_des2_validout
);
i3_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_mode,
key_i => s_des3_key,
data_i => s_des2_dataout,
valid_i => s_des2_validout,
data_o => data_o,
valid_o => s_des3_validout
);
end architecture rtl;
| gpl-2.0 |
tmeissner/cryptocores | des/rtl/vhdl/des_pkg.vhd | 1 | 12677 | -- ======================================================================
-- DES encryption/decryption
-- package file with functions
-- Copyright (C) 2007 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package des_pkg is
component des is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
key_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid
accept_o : out std_logic; -- input accept
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic -- output accept
);
end component des;
type ip_matrix is array (0 to 63) of natural range 0 to 63;
constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17, 9, 1,
59, 51, 43, 35, 27, 19, 11, 3,
61, 53, 45, 37, 29, 21, 13, 5,
63, 55, 47, 39, 31, 23, 15, 7,
56, 48, 40, 32, 24, 16, 8, 0,
58, 50, 42, 34, 26, 18, 10, 2,
60, 52, 44, 36, 28, 20, 12, 4,
62, 54, 46, 38, 30, 22, 14, 6);
constant ipn_table : ip_matrix := (39, 7, 47, 15, 55, 23, 63, 31,
38, 6, 46, 14, 54, 22, 62, 30,
37, 5, 45, 13, 53, 21, 61, 29,
36, 4, 44, 12, 52, 20, 60, 28,
35, 3, 43, 11, 51, 19, 59, 27,
34, 2, 42, 10, 50, 18, 58, 26,
33, 1, 41, 9, 49, 17, 57, 25,
32, 0, 40, 8, 48, 16, 56, 24);
type e_matrix is array (0 to 47) of natural range 0 to 31;
constant e_table : e_matrix := (31, 0, 1, 2, 3, 4,
3, 4, 5, 6, 7, 8,
7, 8, 9, 10, 11, 12,
11, 12, 13, 14, 15, 16,
15, 16, 17, 18, 19, 20,
19, 20, 21, 22, 23, 24,
23, 24, 25, 26, 27, 28,
27, 28, 29, 30, 31, 0);
type s_matrix is array (0 to 3, 0 to 15) of integer range 0 to 15;
constant s1_table : s_matrix := (0 => (14, 4, 13, 1, 2, 15, 11, 8, 3, 10, 6, 12, 5, 9, 0, 7),
1 => ( 0, 15, 7, 4, 14, 2, 13, 1, 10, 6, 12, 11, 9, 5, 3, 8),
2 => ( 4, 1, 14, 8, 13, 6, 2, 11, 15, 12, 9, 7, 3, 10, 5, 0),
3 => (15, 12, 8, 2, 4, 9, 1, 7, 5, 11, 3, 14, 10, 0, 6, 13));
constant s2_table : s_matrix := (0 => (15, 1, 8, 14, 6, 11, 3, 4, 9, 7, 2, 13, 12, 0, 5, 10),
1 => ( 3, 13, 4, 7, 15, 2, 8, 14, 12, 0, 1, 10, 6, 9, 11, 5),
2 => ( 0, 14, 7, 11, 10, 4, 13, 1, 5, 8, 12, 6, 9, 3, 2, 15),
3 => (13, 8, 10, 1, 3, 15, 4, 2, 11, 6, 7, 12, 0, 5, 14, 9));
constant s3_table : s_matrix := (0 => (10, 0, 9, 14, 6, 3, 15, 5, 1, 13, 12, 7, 11, 4, 2, 8),
1 => (13, 7, 0, 9, 3, 4, 6, 10, 2, 8, 5, 14, 12, 11, 15, 1),
2 => (13, 6, 4, 9, 8, 15, 3, 0, 11, 1, 2, 12, 5, 10, 14, 7),
3 => ( 1, 10, 13, 0, 6, 9, 8, 7, 4, 15, 14, 3, 11, 5, 2, 12));
constant s4_table : s_matrix := (0 => ( 7, 13, 14, 3, 0, 6, 9, 10, 1, 2, 8, 5, 11, 12, 4, 15),
1 => (13, 8, 11, 5, 6, 15, 0, 3, 4, 7, 2, 12, 1, 10, 14, 9),
2 => (10, 6, 9, 0, 12, 11, 7, 13, 15, 1, 3, 14, 5, 2, 8, 4),
3 => ( 3, 15, 0, 6, 10, 1, 13, 8, 9, 4, 5, 11, 12, 7, 2, 14));
constant s5_table : s_matrix := (0 => ( 2, 12, 4, 1, 7, 10, 11, 6, 8, 5, 3, 15, 13, 0, 14, 9),
1 => (14, 11, 2, 12, 4, 7, 13, 1, 5, 0, 15, 10, 3, 9, 8, 6),
2 => ( 4, 2, 1, 11, 10, 13, 7, 8, 15, 9, 12, 5, 6, 3, 0, 14),
3 => (11, 8, 12, 7, 1, 14, 2, 13, 6, 15, 0, 9, 10, 4, 5, 3));
constant s6_table : s_matrix := (0 => (12, 1, 10, 15, 9, 2, 6, 8, 0, 13, 3, 4, 14, 7, 5, 11),
1 => (10, 15, 4, 2, 7, 12, 9, 5, 6, 1, 13, 14, 0, 11, 3, 8),
2 => ( 9, 14, 15, 5, 2, 8, 12, 3, 7, 0, 4, 10, 1, 13, 11, 6),
3 => ( 4, 3, 2, 12, 9, 5, 15, 10, 11, 14, 1, 7, 6, 0, 8, 13));
constant s7_table : s_matrix := (0 => ( 4, 11, 2, 14, 15, 0, 8, 13, 3, 12, 9, 7, 5, 10, 6, 1),
1 => (13, 0, 11, 7, 4, 9, 1, 10, 14, 3, 5, 12, 2, 15, 8, 6),
2 => ( 1, 4, 11, 13, 12, 3, 7, 14, 10, 15, 6, 8, 0, 5, 9, 2),
3 => ( 6, 11, 13, 8, 1, 4, 10, 7, 9, 5, 0, 15, 14, 2, 3, 12));
constant s8_table : s_matrix := (0 => (13, 2, 8, 4, 6, 15, 11, 1, 10, 9, 3, 14, 5, 0, 12, 7),
1 => ( 1, 15, 13, 8, 10, 3, 7, 4, 12, 5, 6, 11, 0, 14, 9, 2),
2 => ( 7, 11, 4, 1, 9, 12, 14, 2, 0, 6, 10, 13, 15, 3, 5, 8),
3 => ( 2, 1, 14, 7, 4, 10, 8, 13, 15, 12, 9, 0, 3, 5, 6, 11));
type pc_matrix is array (0 to 27) of natural range 0 to 63;
constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16, 8,
0, 57, 49, 41, 33, 25, 17,
9, 1, 58, 50, 42, 34, 26,
18, 10, 2, 59, 51, 43, 35);
constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
6, 61, 53, 45, 37, 29, 21,
13, 5, 60, 52, 44, 36, 28,
20, 12, 4, 27, 19, 11, 3);
type p_matrix is array (0 to 31) of natural range 0 to 31;
constant p_table : p_matrix := (15, 6, 19, 20,
28, 11, 27, 16,
0, 14, 22, 25,
4, 17, 30, 9,
1, 7, 23, 13,
31, 26, 2, 8,
18, 12, 29, 5,
21, 10, 3, 24);
type pc2_matrix is array (0 to 47) of natural range 0 to 63;
constant pc2_table : pc2_matrix := (13, 16, 10, 23, 0, 4,
2, 27, 14, 5, 20, 9,
22, 18, 11, 3, 25, 7,
15, 6, 26, 19, 12, 1,
40, 51, 30, 36, 46, 54,
29, 39, 50, 44, 32, 47,
43, 48, 38, 55, 33, 52,
45, 41, 49, 35, 28, 31);
function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
function s (input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector;
function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector;
function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector;
end package des_pkg;
package body des_pkg is
function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 63);
begin
for index IN 0 to 63 loop
result( index ) := input_vector( ip_table( index ) );
end loop;
return result;
end function ip;
function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 63);
begin
for index IN 0 to 63 loop
result( index ) := input_vector( ipn_table( index ) );
end loop;
return result;
end function ipn;
function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
variable result : std_logic_vector(0 to 47);
begin
for index IN 0 to 47 loop
result( index ) := input_vector( e_table( index ) );
end loop;
return result;
end function e;
function s ( input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector is
variable int : std_logic_vector(0 to 1);
variable i : integer range 0 to 3;
variable j : integer range 0 to 15;
variable result : std_logic_vector(0 to 3);
begin
int := input_vector( 0 ) & input_vector( 5 );
i := to_integer( unsigned( int ) );
j := to_integer( unsigned( input_vector( 1 to 4) ) );
result := std_logic_vector( to_unsigned( s_table( i, j ), 4 ) );
return result;
end function s;
function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
variable result : std_logic_vector(0 to 31);
begin
for index IN 0 to 31 loop
result( index ) := input_vector( p_table( index ) );
end loop;
return result;
end function p;
function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector is
variable intern : std_logic_vector(0 to 47);
variable result : std_logic_vector(0 to 31);
begin
intern := e( input_r ) xor input_key;
result := p( s( intern(0 to 5), s1_table ) & s( intern(6 to 11), s2_table ) & s( intern(12 to 17), s3_table ) &
s( intern(18 to 23), s4_table ) & s( intern(24 to 29), s5_table ) & s( intern(30 to 35), s6_table ) &
s( intern(36 to 41), s7_table ) & s( intern(42 to 47), s8_table ) );
return result;
end function f;
function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 27);
begin
for index IN 0 to 27 loop
result( index ) := input_vector( pc1c_table( index ) );
end loop;
return result;
end function pc1_c;
function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
variable result : std_logic_vector(0 to 27);
begin
for index IN 0 to 27 loop
result( index ) := input_vector( pc1d_table( index ) );
end loop;
return result;
end function pc1_d;
function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector is
variable result : std_logic_vector(0 to 47);
begin
for index IN 0 to 47 loop
result( index ) := input_vector( pc2_table( index ) );
end loop;
return result;
end function pc2;
end package body des_pkg;
| gpl-2.0 |
siam28/neppielight | dvid_out/dvid_out_clocking.vhd | 2 | 4094 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Description: Generate clocking for sending TMDS data use the OSERDES2
--
-- REMEMBER TO CHECK CLKIN_PERIOD ON PLL_BASE
-- For pixel rates between 25Mhz and 50MHz use the following PLL settings:
-- CLKFBOUT_MULT => 20,
-- CLKOUT0_DIVIDE => 2, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
-- CLKOUT1_DIVIDE => 10, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
-- CLKOUT2_DIVIDE => 20, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
-- CLKIN_PERIOD => 20.0,
--
-- For pixel rates between 40Mhz and 100MHz use the following PLL settings:
-- CLKFBOUT_MULT => 10,
-- CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
-- CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
-- CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
-- CLKIN_PERIOD => 10.0,
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity dvid_out_clocking is
Port ( clk_pixel : in STD_LOGIC;
clk_x1 : out STD_LOGIC;
clk_x2 : out STD_LOGIC;
clk_x10 : out STD_LOGIC;
serdes_strobe : out STD_LOGIC);
end dvid_out_clocking;
architecture Behavioral of dvid_out_clocking is
signal clock_local_x1 : std_logic;
signal clock_local_x2 : std_logic;
signal clock_local_x10 : std_logic;
signal clock_x10_unbuffered : std_logic;
signal clock_x2_unbuffered : std_logic;
signal clock_x1_unbuffered : std_logic;
signal clk_feedback : std_logic;
signal clk50_buffered : std_logic;
signal pll_locked : std_logic;
begin
clk_x1 <= clock_local_x1;
clk_x2 <= clock_local_x2;
clk_x10 <= clock_local_x10;
-- Multiply clk50m by 10, then :
-- * divide by 1 for the bit clock (pixel clock x10)
-- * divide by 5 for the pixel clock x2
-- * divide by 10 for the pixel clock
-- Because the all come from the same PLL the will all be in phase
PLL_BASE_inst : PLL_BASE
generic map (
CLKFBOUT_MULT => 10,
CLKOUT0_DIVIDE => 1, CLKOUT0_PHASE => 0.0, -- Output 10x original frequency
CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.0, -- Output 2x original frequency
CLKOUT2_DIVIDE => 10, CLKOUT2_PHASE => 0.0, -- Output 1x original frequency
CLK_FEEDBACK => "CLKFBOUT",
CLKIN_PERIOD => 10.0,
DIVCLK_DIVIDE => 1
)
port map (
CLKFBOUT => clk_feedback,
CLKOUT0 => clock_x10_unbuffered,
CLKOUT1 => clock_x2_unbuffered,
CLKOUT2 => clock_x1_unbuffered,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pll_locked,
CLKFBIN => clk_feedback,
CLKIN => clk_pixel,
RST => '0'
);
BUFG_pclockx2 : BUFG port map ( I => clock_x2_unbuffered, O => clock_local_x2);
BUFG_pclock : BUFG port map ( I => clock_x1_unbuffered, O => clock_local_x1);
BUFPLL_inst : BUFPLL
generic map (
DIVIDE => 5, -- DIVCLK divider (1-8) !!!! IMPORTANT TO CHANGE THIS AS NEEDED !!!!
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) -- should be true
)
port map (
IOCLK => clock_local_x10, -- Clock used to send bits
LOCK => open,
SERDESSTROBE => serdes_strobe, -- Clock use to load data into SERDES
GCLK => clock_local_x2, -- Global clock use as a reference for serdes_strobe
LOCKED => pll_locked, -- When the upstream PLL is locked
PLLIN => clock_x10_unbuffered -- What clock to use - this must be unbuffered
);
end Behavioral; | gpl-2.0 |
siam28/neppielight | dvid_out/tmds_encoder.vhd | 2 | 4194 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: TMDS Encoder
-- 8 bits colour, 2 control bits and one blanking bits in
-- 10 bits of TMDS encoded data out
-- Clocked at the pixel clock
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TMDS_encoder is
Port ( clk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (7 downto 0);
c : in STD_LOGIC_VECTOR (1 downto 0);
blank : in STD_LOGIC;
encoded : out STD_LOGIC_VECTOR (9 downto 0));
end TMDS_encoder;
architecture Behavioral of TMDS_encoder is
signal xored : STD_LOGIC_VECTOR (8 downto 0);
signal xnored : STD_LOGIC_VECTOR (8 downto 0);
signal ones : STD_LOGIC_VECTOR (3 downto 0);
signal data_word : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_inv : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_disparity : STD_LOGIC_VECTOR (3 downto 0);
signal dc_bias : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
-- Work our the two different encodings for the byte
xored(0) <= data(0);
xored(1) <= data(1) xor xored(0);
xored(2) <= data(2) xor xored(1);
xored(3) <= data(3) xor xored(2);
xored(4) <= data(4) xor xored(3);
xored(5) <= data(5) xor xored(4);
xored(6) <= data(6) xor xored(5);
xored(7) <= data(7) xor xored(6);
xored(8) <= '1';
xnored(0) <= data(0);
xnored(1) <= data(1) xnor xnored(0);
xnored(2) <= data(2) xnor xnored(1);
xnored(3) <= data(3) xnor xnored(2);
xnored(4) <= data(4) xnor xnored(3);
xnored(5) <= data(5) xnor xnored(4);
xnored(6) <= data(6) xnor xnored(5);
xnored(7) <= data(7) xnor xnored(6);
xnored(8) <= '0';
-- Count how many ones are set in data
ones <= "0000" + data(0) + data(1) + data(2) + data(3)
+ data(4) + data(5) + data(6) + data(7);
-- Decide which encoding to use
process(ones, data(0), xnored, xored)
begin
if ones > 4 or (ones = 4 and data(0) = '0') then
data_word <= xnored;
data_word_inv <= NOT(xnored);
else
data_word <= xored;
data_word_inv <= NOT(xored);
end if;
end process;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + data_word(0) + data_word(1) + data_word(2) + data_word(3)
+ data_word(4) + data_word(5) + data_word(6) + data_word(7);
-- Now work out what the output should be
process(clk)
begin
if rising_edge(clk) then
if blank = '1' then
-- In the control periods, all values have and have balanced bit count
case c is
when "00" => encoded <= "1101010100";
when "01" => encoded <= "0010101011";
when "10" => encoded <= "0101010100";
when others => encoded <= "1010101011";
end case;
dc_bias <= (others => '0');
else
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if data_word(8) = '1' then
encoded <= "01" & data_word(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
else
encoded <= "10" & data_word_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
encoded <= '1' & data_word(8) & data_word_inv(7 downto 0);
dc_bias <= dc_bias + data_word(8) - data_word_disparity;
else
encoded <= '0' & data_word;
dc_bias <= dc_bias - data_word_inv(8) + data_word_disparity;
end if;
end if;
end if;
end process;
end Behavioral; | gpl-2.0 |
siam28/neppielight | neppielight.vhd | 2 | 4220 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity neppielight is
Port ( clk50 : in STD_LOGIC;
hdmi_in_p : in STD_LOGIC_VECTOR(3 downto 0);
hdmi_in_n : in STD_LOGIC_VECTOR(3 downto 0);
hdmi_in_sclk : inout STD_LOGIC;
hdmi_in_sdat : inout STD_LOGIC;
hdmi_out_p : out STD_LOGIC_VECTOR(3 downto 0);
hdmi_out_n : out STD_LOGIC_VECTOR(3 downto 0);
leds : out std_logic_vector(7 downto 0);
spiout_mosi: out std_logic;
spiout_sck: out std_logic);
end neppielight;
architecture Behavioral of neppielight is
COMPONENT dvid_out
PORT(
clk_pixel : IN std_logic;
red_p : IN std_logic_vector(7 downto 0);
green_p : IN std_logic_vector(7 downto 0);
blue_p : IN std_logic_vector(7 downto 0);
blank : IN std_logic;
hsync : IN std_logic;
vsync : IN std_logic;
tmds_out_p : OUT std_logic_vector(3 downto 0);
tmds_out_n : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT averager
PORT(
clk_pixel : IN std_logic;
--
i_red : IN std_logic_vector(7 downto 0);
i_green : IN std_logic_vector(7 downto 0);
i_blue : IN std_logic_vector(7 downto 0);
i_blank : IN std_logic;
i_hsync : IN std_logic;
i_vsync : IN std_logic;
--
framebuffer: OUT std_logic_vector(0 to 24*25-1 );
o_red : OUT std_logic_vector(7 downto 0);
o_green : OUT std_logic_vector(7 downto 0);
o_blue : OUT std_logic_vector(7 downto 0);
o_blank : OUT std_logic;
o_hsync : OUT std_logic;
o_vsync : OUT std_logic
);
END COMPONENT;
COMPONENT dvid_in
PORT(
clk_pixel : out std_logic;
leds : out std_logic_vector(7 downto 0) := (others => '0');
red_p : out std_logic_vector(7 downto 0);
green_p : out std_logic_vector(7 downto 0);
blue_p : out std_logic_vector(7 downto 0);
blank : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
tmds_in_p : in std_logic_vector(3 downto 0);
tmds_in_n : in std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT spiout
PORT(
clk50 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (25*24-1 downto 0);
MOSI : out STD_LOGIC;
SCK : out STD_LOGIC
);
END COMPONENT;
signal clk_pixel : std_logic;
signal i_red : std_logic_vector(7 downto 0);
signal i_green : std_logic_vector(7 downto 0);
signal i_blue : std_logic_vector(7 downto 0);
signal i_blank : std_logic;
signal i_hsync : std_logic;
signal i_vsync : std_logic;
signal o_red : std_logic_vector(7 downto 0);
signal o_green : std_logic_vector(7 downto 0);
signal o_blue : std_logic_vector(7 downto 0);
signal o_blank : std_logic;
signal o_hsync : std_logic;
signal o_vsync : std_logic;
signal framebuffer : std_logic_vector(0 to 25*24-1) := (others => '0');
begin
hdmi_in_sclk <= 'Z';
hdmi_in_sdat <= 'Z';
Inst_dvid_in: dvid_in PORT MAP(
tmds_in_p => hdmi_in_p,
tmds_in_n => hdmi_in_n,
leds => leds,
clk_pixel => clk_pixel,
red_p => i_red,
green_p => i_green,
blue_p => i_blue,
blank => i_blank,
hsync => i_hsync,
vsync => i_vsync
);
Inst_averager: averager PORT MAP(
clk_pixel => clk_pixel,
i_red => i_red,
i_green => i_green,
i_blue => i_blue,
i_blank => i_blank,
i_hsync => i_hsync,
i_vsync => i_vsync,
--
framebuffer => framebuffer,
o_red => o_red,
o_green => o_green,
o_blue => o_blue,
o_blank => o_blank,
o_hsync => o_hsync,
o_vsync => o_vsync
);
Inst_dvid_out: dvid_out PORT MAP(
clk_pixel => clk_pixel,
red_p => o_red,
green_p => o_green,
blue_p => o_blue,
blank => o_blank,
hsync => o_hsync,
vsync => o_vsync,
tmds_out_p => hdmi_out_p,
tmds_out_n => hdmi_out_n
);
Inst_spout: spiout PORT MAP(
clk50 => clk50,
data => framebuffer,
MOSI => SPIOUT_MOSI,
SCK => SPIOUT_SCK
);
end Behavioral;
| gpl-2.0 |
siam28/neppielight | averager.vhd | 2 | 6662 | ----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 22:35:50 01/09/2015
-- Design Name: HDMI block averager
-- Module Name: - Behavioral
-- Project Name: Neppielight
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity averager is
Port (
clk_pixel : IN std_logic;
--
i_red : IN std_logic_vector(7 downto 0);
i_green : IN std_logic_vector(7 downto 0);
i_blue : IN std_logic_vector(7 downto 0);
i_blank : IN std_logic;
i_hsync : IN std_logic;
i_vsync : IN std_logic;
--
framebuffer : OUT std_logic_vector(0 to 25*24-1);
o_red : OUT std_logic_vector(7 downto 0);
o_green : OUT std_logic_vector(7 downto 0);
o_blue : OUT std_logic_vector(7 downto 0);
o_blank : OUT std_logic;
o_hsync : OUT std_logic;
o_vsync : OUT std_logic);
end averager;
architecture Behavioral of averager is
-------------------------
-- Part of the pipeline
-------------------------
signal a_red : std_logic_vector(7 downto 0);
signal a_green : std_logic_vector(7 downto 0);
signal a_blue : std_logic_vector(7 downto 0);
signal a_blank : std_logic;
signal a_hsync : std_logic;
signal a_vsync : std_logic;
-------------------------------
-- Counters for screen position
-------------------------------
signal x : STD_LOGIC_VECTOR (10 downto 0);
signal y : STD_LOGIC_VECTOR (10 downto 0);
constant nblocks : integer := 25;
-- signal pixel : std_logic_vector(23 downto 0) := (others => '0');
type accumulator_type is array (0 to nblocks-1,0 to 3) of std_logic_vector(21 downto 0);
signal accumulator : accumulator_type;
--signal blocknr : integer range 0 to 10;
type blockcoords_type is array (0 to nblocks-1) of integer;
-- Due to the details of the construction, we start in the lower left corner
-- and work our way clockwise.
-- Laterally, we've got more leds than pixels, so we'll have partially verlapping boxes.
constant startx : blockcoords_type := ( 0, 0, 0, 0, 0,0,144,288,432,576,720,864,1008,1152,1152,1152,1152,1152,1152,987,823,658,494,329,164);
constant starty : blockcoords_type := (592,472,356,238,118,0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 238, 356, 472, 592,592,592,592,592,592,592);
type gamma_lut_type is array ( 0 to 255) of std_logic_vector(7 downto 0);
constant gamma_lut : gamma_lut_type := (
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"02", X"02", X"02", X"02", X"02", X"02",
X"02", X"02", X"02", X"02", X"02", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"04",
X"04", X"04", X"04", X"04", X"05", X"05", X"05", X"05", X"05", X"06", X"06", X"06", X"06", X"06",
X"07", X"07", X"07", X"08", X"08", X"08", X"08", X"09", X"09", X"09", X"0A", X"0A", X"0A", X"0B",
X"0B", X"0B", X"0C", X"0C", X"0D", X"0D", X"0D", X"0E", X"0E", X"0F", X"0F", X"0F", X"10", X"10",
X"11", X"11", X"12", X"12", X"13", X"13", X"14", X"14", X"15", X"15", X"16", X"17", X"17", X"18",
X"18", X"19", X"19", X"1A", X"1B", X"1B", X"1C", X"1D", X"1D", X"1E", X"1F", X"1F", X"20", X"21",
X"21", X"22", X"23", X"24", X"24", X"25", X"26", X"27", X"28", X"28", X"29", X"2A", X"2B", X"2C",
X"2D", X"2D", X"2E", X"2F", X"30", X"31", X"32", X"33", X"34", X"35", X"36", X"37", X"38", X"39",
X"3A", X"3B", X"3C", X"3D", X"3E", X"3F", X"40", X"41", X"42", X"43", X"44", X"46", X"47", X"48",
X"49", X"4A", X"4B", X"4D", X"4E", X"4F", X"50", X"51", X"53", X"54", X"55", X"57", X"58", X"59",
X"5A", X"5C", X"5D", X"5F", X"60", X"61", X"63", X"64", X"66", X"67", X"68", X"6A", X"6B", X"6D",
X"6E", X"70", X"71", X"73", X"74", X"76", X"78", X"79", X"7B", X"7C", X"7E", X"80", X"81", X"83",
X"85", X"86", X"88", X"8A", X"8B", X"8D", X"8F", X"91", X"92", X"94", X"96", X"98", X"9A", X"9B",
X"9D", X"9F", X"A1", X"A3", X"A5", X"A7", X"A9", X"AB", X"AD", X"AF", X"B1", X"B3", X"B5", X"B7",
X"B9", X"BB", X"BD", X"BF", X"C1", X"C3", X"C5", X"C7", X"CA", X"CC", X"CE", X"D0", X"D2", X"D5",
X"D7", X"D9", X"DB", X"DE", X"E0", X"E2", X"E4", X"E7", X"E9", X"EC", X"EE", X"F0", X"F3", X"F5",
X"F8", X"FA", X"FD", X"FF");
begin
process(clk_pixel)
variable blockedge : std_logic := '0';
begin
if rising_edge(clk_pixel) then
for bn in 0 to nblocks-1 loop
if unsigned(x) >= startx(bn) and unsigned(x) < startx(bn)+128 and
unsigned(y) >= starty(bn) and unsigned(y) < starty(bn)+128 then
-- We are a part of block bn. Accumulate the color info.
accumulator(bn,0) <= std_logic_vector(unsigned(accumulator(bn,0)) + unsigned(a_red));
accumulator(bn,1) <= std_logic_vector(unsigned(accumulator(bn,1)) + unsigned(a_green));
accumulator(bn,2) <= std_logic_vector(unsigned(accumulator(bn,2)) + unsigned(a_blue));
end if;
end loop;
-- debug, mark the block corners in red
-- blockedge := '0';
-- for bn in 0 to nblocks-1 loop
-- if (unsigned(x) = startx(bn) or unsigned(x) = startx(bn)+128) and
-- (unsigned(y) = starty(bn) or unsigned(y) = starty(bn)+128) then
-- blockedge := '1';
-- end if;
-- end loop;
--
-- if blockedge = '0' then
o_red <= a_red;
o_green <= a_green;
o_blue <= a_blue;
-- else
-- o_red <= X"FF";
-- o_green <= X"00";
-- o_blue <= X"00";
-- end if;
o_blank <= a_blank;
o_hsync <= a_hsync;
o_vsync <= a_vsync;
a_red <= i_red;
a_green <= i_green;
a_blue <= i_blue;
a_blank <= i_blank;
a_hsync <= i_hsync;
a_vsync <= i_vsync;
-- Working out where we are in the screen..
if i_vsync /= a_vsync then
y <= (others => '0');
if i_vsync = '1' then
for i in 0 to nblocks-1 loop
for c in 0 to 2 loop
framebuffer(c * 8 + i * 24 to i * 24 + c * 8 + 7) <= gamma_lut(to_integer(unsigned(accumulator(i,c)(21 downto 14))));
accumulator(i,c) <= (others => '0');
end loop;
end loop;
end if;
end if;
if i_blank = '0' then
x <= std_logic_vector(unsigned(x) + 1);
end if;
-- Start of the blanking interval?
if a_blank = '0' and i_blank = '1' then
y <= std_logic_vector(unsigned(y) + 1);
x <= (others => '0');
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
Liorkoren/Verilog-IDE | AntlrGrammer/grammar/com/koltem/antlr/grammer/vhdl/examples/signed.vhd | 5 | 10990 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R;
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R);
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L);
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L);
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R);
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R);
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) < R;
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L < SIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) <= SIGNED(R);
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) <= R;
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L <= SIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) > SIGNED(R);
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) > R;
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L > SIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) >= SIGNED(R);
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) >= R;
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L >= SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
end STD_LOGIC_SIGNED;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_shift.vhd | 1 | 1326 | -- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for shift operators (logical and arithmetic)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity shifter is
port(input : in signed(7 downto 0);
out_srl, out_sll, out_sra, out_sla : out signed(7 downto 0));
end entity shifter;
architecture test of shifter is
begin
process(input)
begin
out_srl <= input srl 1;
out_sll <= input sll 1;
out_sra <= input sra 1;
out_sla <= input sla 1;
end process;
end architecture test;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/dma_handler.vhd | 5 | 8221 | -------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_new_len : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
dma_rd_len_out <= dma_rd_len; --register in openMAC.vhd!
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
dma_new_len <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/work7/work7-pkg.vhd | 8 | 579 | library ieee;
use ieee.std_logic_1164.all;
package work7 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end component;
end package work7;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/altera/hostinterface/src/alteraHostInterfaceRtl.vhd | 2 | 14774 | -------------------------------------------------------------------------------
--! @file alteraHostInterface.vhd
--
--! @brief toplevel of host interface for Altera FPGA
--
--! @details This toplevel interfaces to Altera specific implementation.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
entity alteraHostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBaseTpdo : natural := 16#0B000#;
--! Base address Rpdo
gBaseRpdo : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Rpdo)
gBaseRes : natural := 16#14000#;
--! Select Host Interface Type (0 = Avalon, 1 = Parallel)
gHostIfType : natural := 0;
--! Data width of parallel interface (16/32)
gParallelDataWidth : natural := 16;
--! Address and Data bus are multiplexed (0 = FALSE, otherwise = TRUE)
gParallelMultiplex : natural := 0
);
port (
--! Clock Source input
csi_c0_clock : in std_logic;
--! Reset Source input
rsi_r0_reset : in std_logic;
-- Avalon Memory Mapped Slave for Host
--! Avalon-MM slave host address
avs_host_address : in std_logic_vector(16 downto 2);
--! Avalon-MM slave host byteenable
avs_host_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave host read
avs_host_read : in std_logic;
--! Avalon-MM slave host readdata
avs_host_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave host write
avs_host_write : in std_logic;
--! Avalon-MM slave host writedata
avs_host_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave host waitrequest
avs_host_waitrequest : out std_logic;
-- Avalon Memory Mapped Slave for PCP
--! Avalon-MM slave pcp address
avs_pcp_address : in std_logic_vector(10 downto 2);
--! Avalon-MM slave pcp byteenable
avs_pcp_byteenable : in std_logic_vector(3 downto 0);
--! Avalon-MM slave pcp read
avs_pcp_read : in std_logic;
--! Avalon-MM slave pcp readdata
avs_pcp_readdata : out std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp write
avs_pcp_write : in std_logic;
--! Avalon-MM slave pcp writedata
avs_pcp_writedata : in std_logic_vector(31 downto 0);
--! Avalon-MM slave pcp waitrequest
avs_pcp_waitrequest : out std_logic;
-- Avalon Memory Mapped Master for Host via Magic Bridge
--! Avalon-MM master hostBridge address
avm_hostBridge_address : out std_logic_vector(29 downto 0);
--! Avalon-MM master hostBridge byteenable
avm_hostBridge_byteenable : out std_logic_vector(3 downto 0);
--! Avalon-MM master hostBridge read
avm_hostBridge_read : out std_logic;
--! Avalon-MM master hostBridge readdata
avm_hostBridge_readdata : in std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge write
avm_hostBridge_write : out std_logic;
--! Avalon-MM master hostBridge writedata
avm_hostBridge_writedata : out std_logic_vector(31 downto 0);
--! Avalon-MM master hostBridge waitrequest
avm_hostBridge_waitrequest : in std_logic;
--! Interrupt receiver
inr_irqSync_irq : in std_logic;
--! Interrupt sender
ins_irqOut_irq : out std_logic;
--! External Sync Source
coe_ExtSync_exsync : in std_logic;
--! Node Id
coe_NodeId_nodeid : in std_logic_vector(7 downto 0);
--! POWERLINK Error LED
coe_PlkLed_lederr : out std_logic;
--! POWERLINK Status LED
coe_PlkLed_ledst : out std_logic;
-- Parallel Host Interface
--! Chipselect
coe_parHost_chipselect : in std_logic;
--! Read strobe
coe_parHost_read : in std_logic;
--! Write strobe
coe_parHost_write : in std_logic;
--! Address Latch enable (Multiplexed only)
coe_parHost_addressLatchEnable : in std_logic;
--! High active Acknowledge
coe_parHost_acknowledge : out std_logic;
--! Byteenables
coe_parHost_byteenable : in std_logic_vector(gParallelDataWidth/8-1 downto 0);
--! Address bus (Demultiplexed, word-address)
coe_parHost_address : in std_logic_vector(15 downto 0);
--! Data bus (Demultiplexed)
coe_parHost_data : inout std_logic_vector(gParallelDataWidth-1 downto 0);
--! Address/Data bus (Multiplexed, word-address))
coe_parHost_addressData : inout std_logic_vector(gParallelDataWidth-1 downto 0)
);
end alteraHostInterface;
architecture rtl of alteraHostInterface is
--! The bridge translation lut is implemented in memory blocks to save logic resources.
--! If no M9K shall be used, set this constant to 0.
constant cBridgeUseMemBlock : natural := 1;
signal host_address : std_logic_vector(16 downto 2);
signal host_byteenable : std_logic_vector(3 downto 0);
signal host_read : std_logic;
signal host_readdata : std_logic_vector(31 downto 0);
signal host_write : std_logic;
signal host_writedata : std_logic_vector(31 downto 0);
signal host_waitrequest : std_logic;
begin
--! Assign the host side to Avalon
genAvalon : if gHostIfType = 0 generate
begin
host_address <= avs_host_address;
host_byteenable <= avs_host_byteenable;
host_read <= avs_host_read;
avs_host_readdata <= host_readdata;
host_write <= avs_host_write;
host_writedata <= avs_host_writedata;
avs_host_waitrequest <= host_waitrequest;
end generate;
--! Assign the host side to Parallel
genParallel : if gHostIfType = 1 generate
signal hostData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostData_en : std_logic;
signal hostAddressData_i : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostAddressData_o : std_logic_vector(gParallelDataWidth-1 downto 0);
signal hostAddressData_en : std_logic;
begin
-- not used signals are set to inactive
avs_host_readdata <= (others => cInactivated);
avs_host_waitrequest <= cInactivated;
theParallelInterface : entity work.parallelInterface
generic map (
gDataWidth => gParallelDataWidth,
gMultiplex => gParallelMultiplex
)
port map (
iParHostChipselect => coe_parHost_chipselect,
iParHostRead => coe_parHost_read,
iParHostWrite => coe_parHost_write,
iParHostAddressLatchEnable => coe_parHost_addressLatchEnable,
oParHostAcknowledge => coe_parHost_acknowledge,
iParHostByteenable => coe_parHost_byteenable,
iParHostAddress => coe_parHost_address,
oParHostData => hostData_o,
iParHostData => hostData_i,
oParHostDataEnable => hostData_en,
oParHostAddressData => hostAddressData_o,
iParHostAddressData => hostAddressData_i,
oParHostAddressDataEnable => hostAddressData_en,
iClk => csi_c0_clock,
iRst => rsi_r0_reset,
oHostAddress => host_address,
oHostByteenable => host_byteenable,
oHostRead => host_read,
iHostReaddata => host_readdata,
oHostWrite => host_write,
oHostWritedata => host_writedata,
iHostWaitrequest => host_waitrequest
);
-- tri-state buffers
coe_parHost_data <= hostData_o when hostData_en = cActivated else
(others => 'Z');
hostData_i <= coe_parHost_data;
coe_parHost_addressData <= hostAddressData_o when hostAddressData_en = cActivated else
(others => 'Z');
hostAddressData_i <= coe_parHost_addressData;
end generate;
--! The host interface
theHostInterface: entity work.hostInterface
generic map (
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gBridgeUseMemBlock => cBridgeUseMemBlock,
gBaseDynBuf0 => gBaseDynBuf0,
gBaseDynBuf1 => gBaseDynBuf1,
gBaseErrCntr => gBaseErrCntr,
gBaseTxNmtQ => gBaseTxNmtQ,
gBaseTxGenQ => gBaseTxGenQ,
gBaseTxSynQ => gBaseTxSynQ,
gBaseTxVetQ => gBaseTxVetQ,
gBaseRxVetQ => gBaseRxVetQ,
gBaseK2UQ => gBaseK2UQ,
gBaseU2KQ => gBaseU2KQ,
gBaseTpdo => gBaseTpdo,
gBaseRpdo => gBaseRpdo,
gBaseRes => gBaseRes
)
port map (
iClk => csi_c0_clock,
iRst => rsi_r0_reset,
iHostAddress => host_address,
iHostByteenable => host_byteenable,
iHostRead => host_read,
oHostReaddata => host_readdata,
iHostWrite => host_write,
iHostWritedata => host_writedata,
oHostWaitrequest => host_waitrequest,
iPcpAddress => avs_pcp_address,
iPcpByteenable => avs_pcp_byteenable,
iPcpRead => avs_pcp_read,
oPcpReaddata => avs_pcp_readdata,
iPcpWrite => avs_pcp_write,
iPcpWritedata => avs_pcp_writedata,
oPcpWaitrequest => avs_pcp_waitrequest,
oHostBridgeAddress => avm_hostBridge_address,
oHostBridgeByteenable => avm_hostBridge_byteenable,
oHostBridgeRead => avm_hostBridge_read,
iHostBridgeReaddata => avm_hostBridge_readdata,
oHostBridgeWrite => avm_hostBridge_write,
oHostBridgeWritedata => avm_hostBridge_writedata,
iHostBridgeWaitrequest => avm_hostBridge_waitrequest,
iIrqIntSync => inr_irqSync_irq,
iIrqExtSync => coe_ExtSync_exsync,
oIrq => ins_irqOut_irq,
iNodeId => coe_NodeId_nodeid,
oPlkLedError => coe_PlkLed_lederr,
oPlkLedStatus => coe_PlkLed_ledst
);
end rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/forgen.vhd | 4 | 1259 | library ieee;
use ieee.std_logic_1164.all;
-- This is a simple test of the initialization assignment for
-- signals. We also let a generic into the test.
entity test is
generic (width : integer := 4);
port (clk : in std_logic;
src0, src1 : in std_logic_vector (width-1 downto 0);
dst : out std_logic_vector (width-1 downto 0));
end test;
library ieee;
use ieee.std_logic_1164.all;
entity reg_xor is
port (clk : in std_logic;
src0, src1 : in std_logic;
dst : out std_logic);
end reg_xor;
architecture operation of test is
component reg_xor
port (clk : in std_logic;
src0, src1 : in std_logic;
dst : out std_logic);
end component;
begin
vec: for idx in width-1 downto 0 generate
slice: reg_xor port map (clk => clk,
src0 => src0(idx),
src1 => src1(idx),
dst => dst(idx));
end generate vec;
end operation;
architecture operation of reg_xor is
signal tmp : std_logic;
begin
tmp <= src0 xor src1;
step: process (clk)
begin -- process step
if clk'event and clk = '1' then -- rising clock edge
dst <= tmp;
end if;
end process step;
end operation;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/hostinterface/src/hostInterfaceRtl.vhd | 2 | 20653 | -------------------------------------------------------------------------------
--! @file hostInterface.vhd
--
--! @brief toplevel of host interface
--
--! @details The toplevel instantiates the necessary components for the
--! host interface like the Dynamic Bridge and the Status-/Control Registers.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity hostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
gBridgeUseMemBlock : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBaseTpdo : natural := 16#0B000#;
--! Base address Rpdo
gBaseRpdo : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Rpdo)
gBaseRes : natural := 16#14000#
);
port (
--! Clock Source input
iClk : in std_logic;
--! Reset Source input
iRst : in std_logic;
-- Memory Mapped Slave for Host
--! MM slave host address
iHostAddress : in std_logic_vector(16 downto 2);
--! MM slave host byteenable
iHostByteenable : in std_logic_vector(3 downto 0);
--! MM slave host read
iHostRead : in std_logic;
--! MM slave host readdata
oHostReaddata : out std_logic_vector(31 downto 0);
--! MM slave host write
iHostWrite : in std_logic;
--! MM slave host writedata
iHostWritedata : in std_logic_vector(31 downto 0);
--! MM slave host waitrequest
oHostWaitrequest : out std_logic;
-- Memory Mapped Slave for PCP
--! MM slave pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! MM slave pcp byteenable
iPcpByteenable : in std_logic_vector(3 downto 0);
--! MM slave pcp read
iPcpRead : in std_logic;
--! MM slave pcp readdata
oPcpReaddata : out std_logic_vector(31 downto 0);
--! MM slave pcp write
iPcpWrite : in std_logic;
--! MM slave pcp writedata
iPcpWritedata : in std_logic_vector(31 downto 0);
--! MM slave pcp waitrequest
oPcpWaitrequest : out std_logic;
-- Memory Mapped Master for Host via Dynamic Bridge
--! MM master hostBridge address
oHostBridgeAddress : out std_logic_vector(29 downto 0);
--! MM master hostBridge byteenable
oHostBridgeByteenable : out std_logic_vector(3 downto 0);
--! MM master hostBridge read
oHostBridgeRead : out std_logic;
--! MM master hostBridge readdata
iHostBridgeReaddata : in std_logic_vector(31 downto 0);
--! MM master hostBridge write
oHostBridgeWrite : out std_logic;
--! MM master hostBridge writedata
oHostBridgeWritedata : out std_logic_vector(31 downto 0);
--! MM master hostBridge waitrequest
iHostBridgeWaitrequest : in std_logic;
--! Interrupt internal sync signal (from openMAC)
iIrqIntSync : in std_logic;
--! External sync source
iIrqExtSync : in std_logic;
--! Interrupt output signal
oIrq : out std_logic;
--! Node Id
iNodeId : in std_logic_vector(7 downto 0);
--! POWERLINK Error LED
oPlkLedError : out std_logic;
--! POWERLINK Status LED
oPlkLedStatus : out std_logic
);
end hostInterface;
architecture Rtl of hostInterface is
--! Magic
constant cMagic : natural := 16#504C4B00#;
--! Base address array
constant cBaseAddressArray : tArrayStd32 := (
std_logic_vector(to_unsigned(gBaseDynBuf0, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseDynBuf1, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseErrCntr, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxNmtQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxGenQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxSynQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseK2UQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseU2KQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTpdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRpdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRes, cArrayStd32ElementSize))
);
--! Base address array count
constant cBaseAddressArrayCount : natural := cBaseAddressArray'length;
--! Base address set by host
constant cBaseAddressHostCount : natural := 2;
--! Base address set by pcp
constant cBaseAddressPcpCount : natural := cBaseAddressArrayCount-cBaseAddressHostCount;
--! Number of interrupt sources (sync not included)
constant cIrqSourceCount : natural := 3;
--! Bridge fsm type
type tFsm is (
sIdle,
sReqAddr,
sAccess,
sDone
);
--! select the bridge logic
signal bridgeSel : std_logic;
--! invalid address range selected
signal invalidSel : std_logic;
--! select status control registers
signal statCtrlSel : std_logic;
--! write status control register
signal statCtrlWrite : std_logic;
--! read status control register
signal statCtrlRead : std_logic;
--! waitrequest from status/control
signal statCtrlWaitrequest : std_logic;
--! readdata from status/control
signal statCtrlReaddata : std_logic_vector(oHostReaddata'range);
--! Bridge request signal
signal bridgeRequest : std_logic;
--! Bridge enable control
signal bridgeEnable : std_logic;
--! Bridge address is valid
signal bridgeAddrValid : std_logic;
--! LED from status/control registers
signal statCtrlLed : std_logic_vector(1 downto 0);
--! The magic bridge outputs the dword address
signal hostBridgeAddress_dword : std_logic_vector(oHostBridgeAddress'length-1 downto 2);
--! Bridge transfer done strobe
signal bridgeTfDone : std_logic;
--! Bridge read data
signal bridgeReaddata : std_logic_vector(iHostBridgeReaddata'range);
--! Bridge state machine
signal fsm : tFsm;
--! Bridge state machine, next state
signal fsm_next : tFsm;
-- base set signals
--! BaseSet Write
signal baseSetWrite : std_logic;
--! BaseSet Read
signal baseSetRead : std_logic;
--! BaseSet byteenable
signal baseSetByteenable : std_logic_vector(3 downto 0);
--! BaseSet Writedata
signal baseSetWritedata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Readdata
signal baseSetReaddata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Address
signal baseSetAddress : std_logic_vector(logDualis(cBaseAddressArrayCount)-1 downto 0);
--! BaseSet acknowledge
signal baseSetAck : std_logic;
-- interrupt signals
--! Irq master enable
signal irqMasterEnable : std_logic;
--! Irq source enable
signal irqSourceEnable : std_logic_vector(cIrqSourceCount downto 0);
--! Irq acknowledge
signal irqAcknowledge : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source pending
signal irqSourcePending : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source set (no sync!)
signal irqSourceSet : std_logic_vector(cIrqSourceCount downto 1);
--! sync signal
signal syncSig : std_logic;
--! synchronized ext sync
signal extSync_sync : std_logic;
--! external sync signal
signal extSyncEnable : std_logic;
--! external sync config
signal extSyncConfig : std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
--! external sync signal detected rising edge
signal extSync_rising : std_logic;
--! external sync signal detected falling edge
signal extSync_falling : std_logic;
--! external sync signal detected any edge
signal extSync_any : std_logic;
begin
-- select status/control registers if host address is below 2 kB
statCtrlSel <= cActivated when iHostAddress < cBaseAddressArray(0)(iHostAddress'range) else
cInactivated;
-- select invalid address
invalidSel <= cActivated when iHostAddress >= cBaseAddressArray(cBaseAddressArrayCount-1)(iHostAddress'range) else
cInactivated;
-- bridge is selected if status/control registers are not accessed
bridgeSel <= cInactivated when bridgeEnable = cInactivated else
cInactivated when invalidSel = cActivated else
cInactivated when statCtrlSel = cActivated else
cActivated;
-- create write and read strobe for status/control registers
statCtrlWrite <= iHostWrite and statCtrlSel;
statCtrlRead <= iHostRead and statCtrlSel;
-- host waitrequest from status/control, bridge or invalid
oHostWaitrequest <= statCtrlWaitrequest when statCtrlSel = cActivated else
cInactivated when bridgeEnable = cInactivated else
not bridgeTfDone when bridgeSel = cActivated else
not invalidSel;
-- host readdata from status/control or bridge
oHostReaddata <= bridgeReaddata when bridgeSel = cActivated else
statCtrlReaddata when statCtrlSel = cActivated else
(others => cInactivated);
-- select external sync if enabled, otherwise rx irq signal
syncSig <= iIrqIntSync when extSyncEnable /= cActivated else
extSync_rising when extSyncConfig = cExtSyncEdgeRis else
extSync_falling when extSyncConfig = cExtSyncEdgeFal else
extSync_any when extSyncConfig = cExtSyncEdgeAny else
cInactivated;
--! The bridge state machine handles the address translation of
--! dynamicBridge and finalizes the access to the host bridge master.
theFsmCom : process (
fsm,
bridgeSel,
bridgeAddrValid,
iHostRead,
iHostWrite,
iHostBridgeWaitrequest
)
begin
--default
fsm_next <= fsm;
case fsm is
when sIdle =>
if ( (iHostRead = cActivated or iHostWrite = cActivated) and
bridgeSel = cActivated) then
fsm_next <= sReqAddr;
end if;
when sReqAddr =>
if bridgeAddrValid = cActivated then
fsm_next <= sAccess;
end if;
when sAccess =>
if iHostBridgeWaitrequest = cInactivated then
fsm_next <= sDone;
end if;
when sDone =>
fsm_next <= sIdle;
end case;
end process;
bridgeRequest <= cActivated when fsm = sReqAddr else cInactivated;
bridgeTfDone <= cActivated when fsm = sDone else cInactivated;
--! Clock process to assign registers.
theClkPro : process(iRst, iClk)
begin
if iRst = cActivated then
fsm <= sIdle;
oHostBridgeAddress <= (others => cInactivated);
oHostBridgeByteenable <= (others => cInactivated);
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
oHostBridgeWritedata <= (others => cInactivated);
elsif rising_edge(iClk) then
fsm <= fsm_next;
if iHostBridgeWaitrequest = cInactivated then
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
bridgeReaddata <= iHostBridgeReaddata;
end if;
if bridgeAddrValid = cActivated then
oHostBridgeAddress <= hostBridgeAddress_dword & "00";
oHostBridgeByteenable <= iHostByteenable;
oHostBridgeRead <= iHostRead;
oHostBridgeWrite <= iHostWrite;
oHostBridgeWritedata <= iHostWritedata;
end if;
end if;
end process;
--! The synchronizer which protects us from crazy effects!
theSynchronizer : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iIrqExtSync,
oSync => extSync_sync
);
--! The Edge Detector for external sync
theExtSyncEdgeDet : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => extSync_sync,
oRising => extSync_rising,
oFalling => extSync_falling,
oAny => extSync_any
);
--! The Dynamic Bridge
theDynamicBridge : entity work.dynamicBridge
generic map (
gAddressSpaceCount => cBaseAddressArrayCount-1,
gUseMemBlock => gBridgeUseMemBlock,
gBaseAddressArray => cBaseAddressArray
)
port map (
iClk => iClk,
iRst => iRst,
iBridgeAddress => iHostAddress,
iBridgeRequest => bridgeRequest,
oBridgeAddress => hostBridgeAddress_dword,
oBridgeSelectAny => open,
oBridgeSelect => open,
oBridgeValid => bridgeAddrValid,
iBaseSetWrite => baseSetWrite,
iBaseSetRead => baseSetRead,
iBaseSetByteenable => baseSetByteenable,
iBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetWritedata,
oBaseSetData => baseSetReaddata,
oBaseSetAck => basesetAck
);
--! The Irq Generator
theIrqGen : entity work.irqGen
generic map (
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iSync => syncSig,
iIrqSource => irqSourceSet,
oIrq => oIrq,
iIrqMasterEnable => irqMasterEnable,
iIrqSourceEnable => irqSourceEnable,
iIrqAcknowledge => irqAcknowledge,
oIrgPending => irqSourcePending
);
--! The Status-/Control Registers
theStCtrlReg : entity work.statusControlReg
generic map (
gMagic => cMagic,
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gHostBaseSet => cBaseAddressHostCount,
gPcpBaseSet => cBaseAddressPcpCount,
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iHostRead => statCtrlRead,
iHostWrite => statCtrlWrite,
iHostByteenable => iHostByteenable,
iHostAddress => iHostAddress(10 downto 2),
oHostReaddata => statCtrlReaddata,
iHostWritedata => iHostWritedata,
oHostWaitrequest => statCtrlWaitrequest,
iPcpRead => iPcpRead,
iPcpWrite => iPcpWrite,
iPcpByteenable => iPcpByteenable,
iPcpAddress => iPcpAddress,
oPcpReaddata => oPcpReaddata,
iPcpWritedata => iPcpWritedata,
oPcpWaitrequest => oPcpWaitrequest,
oBaseSetWrite => baseSetWrite,
oBaseSetRead => baseSetRead,
oBaseSetByteenable => baseSetByteenable,
oBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetReaddata,
oBaseSetData => baseSetWritedata,
iBaseSetAck => basesetAck,
oIrqMasterEnable => irqMasterEnable,
oIrqSourceEnable => irqSourceEnable,
oIrqAcknowledge => irqAcknowledge,
oIrqSet => irqSourceSet,
iIrqPending => irqSourcePending,
oExtSyncEnable => extSyncEnable,
oExtSyncConfig => extSyncConfig,
iNodeId => iNodeId,
oPLed => statCtrlLed,
oBridgeEnable => bridgeEnable
);
oPlkLedStatus <= statCtrlLed(0);
oPlkLedError <= statCtrlLed(1);
end Rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_xorg_stdlogic.vhd | 4 | 295 | library IEEE;
use IEEE.std_logic_1164.all;
entity xor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity xor_gate;
architecture rtl of xor_gate is
begin
c_o <= a_i xor b_i;
end architecture rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/fifo/src/asyncFifo-e.vhd | 2 | 3669 | -------------------------------------------------------------------------------
--! @file asyncFifo-e.vhd
--
--! @brief The asynchronous FIFO entity.
--!
--! @details This is the asynchronous FIFO interface description, for a dual
--! clocked FIFO component.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity asyncFifo is
generic (
--! Data width of write and read port
gDataWidth : natural := 8;
--! Number of words stored in fifo
gWordSize : natural := 64;
--! Number of synchronizer stages
gSyncStages : natural := 2;
--! Select memory resource ("ON" = memory / "OFF" = registers)
gMemRes : string := "ON"
);
port (
--! Asynchronous clear (FIXME: Convert this to reset, and add wr-/rd-clear inputs)
iAclr : in std_logic;
--! Write Clk
iWrClk : in std_logic;
--! Write Request
iWrReq : in std_logic;
--! Write Data
iWrData : in std_logic_vector(gDataWidth-1 downto 0);
--! Write Empty Flag
oWrEmpty : out std_logic;
--! Write Full Flag
oWrFull : out std_logic;
--! Write used words
oWrUsedw : out std_logic_vector(logDualis(gWordSize)-1 downto 0);
--! Read clk
iRdClk : in std_logic;
--! Read Request
iRdReq : in std_logic;
--! Read Data
oRdData : out std_logic_vector(gDataWidth-1 downto 0);
--! Read Empty Flag
oRdEmpty : out std_logic;
--! Read Full Flag
oRdFull : out std_logic;
--! Read used words
oRdUsedw : out std_logic_vector(logDualis(gWordSize)-1 downto 0)
);
end entity asyncFifo;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/fifo/src/asyncFifo-rtl-a.vhd | 2 | 9706 | -------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
architecture rtl of asyncFifo is
--! Address width
constant cAddrWidth : natural := logDualis(gWordSize);
--! Type for DPRAM port commons
type tDpramPortCommon is record
clk : std_logic;
enable : std_logic;
address : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for DPRAM port assignment
type tDpramPort is record
wrPort : tDpramPortCommon;
rdPort : tDpramPortCommon;
write : std_logic;
writedata : std_logic_vector(gDataWidth-1 downto 0);
readdata : std_logic_vector(gDataWidth-1 downto 0);
end record;
--! Type for control port
type tControlPort is record
clk : std_logic;
rst : std_logic;
request : std_logic;
otherPointer : std_logic_vector(cAddrWidth downto 0);
empty : std_logic;
full : std_logic;
pointer : std_logic_vector(cAddrWidth downto 0);
address : std_logic_vector(cAddrWidth-1 downto 0);
usedWord : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for pointer synchronizers
type tPointerSyncPort is record
clk : std_logic;
rst : std_logic;
din : std_logic_vector(cAddrWidth downto 0);
dout : std_logic_vector(cAddrWidth downto 0);
end record;
--! DPRAM instance
signal inst_dpram : tDpramPort;
--! Write controller instance
signal inst_writeCtrl : tControlPort;
--! Read controller instance
signal inst_readCtrl : tControlPort;
--! Write pointer synchronizer instance
signal inst_writeSync : tPointerSyncPort;
--! Read pointer synchronizer instance
signal inst_readSync : tPointerSyncPort;
begin
assert (gMemRes = "ON")
report "This FIFO implementation only supports memory resources!"
severity warning;
---------------------------------------------------------------------------
-- Assign Outputs
---------------------------------------------------------------------------
-- Write port
oWrEmpty <= inst_writeCtrl.empty;
oWrFull <= inst_writeCtrl.full;
oWrUsedw <= inst_writeCtrl.usedWord;
-- Read port
oRdEmpty <= inst_readCtrl.empty;
oRdFull <= inst_readCtrl.full;
oRdUsedw <= inst_readCtrl.usedWord;
oRdData <= inst_dpram.readdata;
---------------------------------------------------------------------------
-- Map DPRAM instance
---------------------------------------------------------------------------
-- Write port
inst_dpram.wrPort.clk <= iWrClk;
inst_dpram.wrPort.enable <= inst_writeCtrl.request;
inst_dpram.write <= inst_writeCtrl.request;
inst_dpram.wrPort.address <= inst_writeCtrl.address;
inst_dpram.writedata <= iWrData;
-- Read port
inst_dpram.rdPort.clk <= iRdClk;
inst_dpram.rdPort.enable <= iRdReq;
inst_dpram.rdPort.address <= inst_readCtrl.address;
---------------------------------------------------------------------------
-- Map Write and Read controller instance
---------------------------------------------------------------------------
inst_readCtrl.clk <= iRdClk;
inst_readCtrl.rst <= iAclr;
inst_readCtrl.request <= iRdReq;
inst_readCtrl.otherPointer <= inst_writeSync.dout;
inst_writeCtrl.clk <= iWrClk;
inst_writeCtrl.rst <= iAclr;
inst_writeCtrl.request <= iWrReq and not inst_writeCtrl.full;
inst_writeCtrl.otherPointer <= inst_readSync.dout;
---------------------------------------------------------------------------
-- Map pointer synchronizers
---------------------------------------------------------------------------
inst_readSync.rst <= iAclr;
inst_readSync.clk <= iWrClk; -- synchronize read pointer to write clock
inst_readSync.din <= inst_readCtrl.pointer;
inst_writeSync.rst <= iAclr;
inst_writeSync.clk <= iRdClk; -- synchronize write pointer to read clock
inst_writeSync.din <= inst_writeCtrl.pointer;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! This is the FIFO read controller.
FIFO_READ_CONTROL : entity work.fifoRead
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_readCtrl.clk,
iRst => inst_readCtrl.rst,
iRead => inst_readCtrl.request,
iWrPointer => inst_readCtrl.otherPointer,
oEmpty => inst_readCtrl.empty,
oFull => inst_readCtrl.full,
oPointer => inst_readCtrl.pointer,
oAddress => inst_readCtrl.address,
oUsedWord => inst_readCtrl.usedWord
);
--! This is the FIFO write controller.
FIFO_WRITE_CONTROL : entity work.fifoWrite
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_writeCtrl.clk,
iRst => inst_writeCtrl.rst,
iWrite => inst_writeCtrl.request,
iRdPointer => inst_writeCtrl.otherPointer,
oEmpty => inst_writeCtrl.empty,
oFull => inst_writeCtrl.full,
oPointer => inst_writeCtrl.pointer,
oAddress => inst_writeCtrl.address,
oUsedWord => inst_writeCtrl.usedWord
);
--! This is the FIFO buffer.
FIFO_BUFFER : entity work.dpRamSplxNbe
generic map (
gWordWidth => gDataWidth,
gNumberOfWords => gWordSize,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_dpram.wrPort.clk,
iEnable_A => inst_dpram.wrPort.enable,
iWriteEnable_A => inst_dpram.write,
iAddress_A => inst_dpram.wrPort.address,
iWritedata_A => inst_dpram.writedata,
iClk_B => inst_dpram.rdPort.clk,
iEnable_B => inst_dpram.rdPort.enable,
iAddress_B => inst_dpram.rdPort.address,
oReaddata_B => inst_dpram.readdata
);
--! This generate block instantiates multiple synchrinizers to transfer
--! the write and read pointers to the opposite clock domains.
GEN_POINTERSYNC : for i in cAddrWidth downto 0 generate
WRITESYNC : entity work.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_writeSync.rst,
iClk => inst_writeSync.clk,
iAsync => inst_writeSync.din(i),
oSync => inst_writeSync.dout(i)
);
READSYNC : entity work.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_readSync.rst,
iClk => inst_readSync.clk,
iAsync => inst_readSync.din(i),
oSync => inst_readSync.dout(i)
);
end generate GEN_POINTERSYNC;
end rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/system.vhd | 4 | 3790 | -- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Const_system is
generic (C: in integer := 500);
port (clk, reset: in std_logic;
x: in std_logic_vector (7 downto 0);
y: out std_logic_vector (10 downto 0) );
end Const_system;
library ieee;
use ieee.std_logic_1164.all;
entity Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end Add;
library ieee;
use ieee.std_logic_1164.all;
entity Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc;
library ieee;
use ieee.std_logic_1164.all;
entity Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end Reg_N;
architecture System_rtl of Const_system is
-- Register component
component Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end component;
-- incrementer component
component Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end component;
-- adder component
component Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end component;
signal x_int: std_logic_vector (7 downto 0);
signal x_inc: std_logic_vector (7 downto 0);
signal x_sum: std_logic_vector (10 downto 0);
signal x_ext: std_logic_vector (10 downto 0);
signal x_inv: std_logic_vector (10 downto 0);
signal x_dif: std_logic_vector (10 downto 0);
signal zero, one: std_logic;
signal const: std_logic_vector (10 downto 0);
begin
const <= conv_std_logic_vector (C, 11);
-- connstant bit 0, 1
zero <= '0';
one <= '1';
-- registering input X
RegX: Reg_N generic map (n => 8)
port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
-- Incrementing input x_int
incrementer: Inc generic map (n => 8)
port map (a => x_int, sum => x_inc); -- x + 1
-- forming 1's complement of x+1
x_inv <= "111" & not x_inc;
x_ext <= "000" & x_int;
-- adding constant to x_int
addition: Add generic map (n => 11)
port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
-- this should get x+1000-(x+1) = 1000-1 = 999
subtraction: Add generic map (n => 11)
port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
-- registering output X
RegY: Reg_N generic map (n => 11)
port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
end System_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Add_rtl of Add is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
end Add_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Inc_rtl of Inc is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end Inc_rtl;
library ieee;
use ieee.std_logic_1164.all;
architecture Reg_rtl of Reg_N is
begin
My_register: process (clk, reset)
begin
if (reset = '1') then
a_reg <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg <= a;
end if;
end process;
end Reg_rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_smul23_bit.vhd | 4 | 275 | library ieee;
use ieee.numeric_bit.all;
entity smul23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (45 downto 0)
);
end entity smul23;
architecture rtl of smul23 is
begin
c_o <= a_i * b_i;
end architecture rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/phyActGen-rtl-ea.vhd | 2 | 5098 | -------------------------------------------------------------------------------
--! @file phyActGen-rtl-ea.vhd
--
--! @brief Phy activity generator
--
--! @details The phy activity generator generates a free-running clock-synchronous
--! packet activity signal. This signal can be used to drive an LED.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity phyActGen is
generic (
--! Generated activity frequency of oActivity [Hz]
gActivityFreq : natural := 6;
--! Clock frequency of iClk [Hz]
gClkFreq : natural := 50e6
);
port (
--! Reset
iRst : in std_logic;
--! Clock
iClk : in std_logic;
--! MAC Tx enable signal
iTxEnable : in std_logic;
--! MAC Rx data valid signal
iRxValid : in std_logic;
--! Generated activity signal
oActivity : out std_logic
);
end phyActGen;
architecture rtl of phyActGen is
--! Obtain maximum counter value to achieve activity frequency
constant cCntMaxValue : natural := gClkFreq / gActivityFreq;
--! Obtain counter width
constant cCntWidth : natural := logDualis(cCntMaxValue);
--! Constant for counter value zero
constant cCntIsZero : std_logic_vector(cCntWidth downto 0) := (others => cInactivated);
--! The counter
signal counter : std_logic_vector(cCntWidth-1 downto 0);
--! Terminal counter
signal counterTc : std_logic;
--! Trigger activity in next cycle due to packet activity
signal triggerActivity : std_logic;
--! Enable activity
signal enableActivity : std_logic;
begin
oActivity <= counter(counter'high) when enableActivity = cActivated else
cInactivated;
ledCntr : process(iRst, iClk)
begin
if iRst = cActivated then
triggerActivity <= cInactivated;
enableActivity <= cInactivated;
elsif rising_edge(iClk) then
--monoflop, of course no default value!
if triggerActivity = cActivated and counterTc = cActivated then
--counter overflow and activity within last cycle
enableActivity <= cActivated;
elsif counterTc = cActivated then
--counter overflow but no activity
enableActivity <= cInactivated;
end if;
--monoflop, of course no default value!
if counterTc = cActivated then
--count cycle over, reset trigger
triggerActivity <= cInactivated;
elsif iTxEnable = cActivated or iRxValid = cActivated then
--activity within cycle
triggerActivity <= cActivated;
end if;
end if;
end process;
theFreeRunCnt : process(iClk, iRst)
begin
if iRst = cActivated then
counter <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
counter <= std_logic_vector(unsigned(counter) - 1);
end if;
end process;
counterTc <= cActivated when counter = cCntIsZero else
cInactivated;
end rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/vhdl_and104_stdlogic.vhd | 4 | 313 | library ieee;
use ieee.std_logic_1164.all;
entity and104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity and104;
architecture rtl of and104 is
begin
c_o <= a_i and b_i;
end architecture rtl;
| gpl-2.0 |
Kalycito-open-automation/openPOWERLINK_V2_old_25-06-2014 | hardware/ipcore/common/openmac/src/openhub-rtl-ea.vhd | 2 | 7431 | -------------------------------------------------------------------------------
--! @file openhub-rtl-ea.vhd
--
--! @brief OpenHUB
--
--! @details This is the openHUB using RMII Rx and Tx lines.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
--! use openmac package
use work.openmacPkg.all;
entity openhub is
generic (
--! Number of ports
gPortCount : integer := 3
);
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive paths
iRx : in tRmiiPathArray(gPortCount downto 1);
--! RMII transmit paths
oTx : out tRmiiPathArray(gPortCount downto 1);
--! Determine number of internal port (to MAC)
iIntPort : in integer range 1 to gPortCount := 1;
--! Transmit mask to enable ports
iTxMask : in std_logic_vector(gPortCount downto 1) := (others => cActivated);
--! Gives the number of the currectly receiving port
oRxPort : out integer range 0 to gPortCount
);
end entity openhub;
architecture rtl of openhub is
--! All ports inactive constant
constant cPortsAreInactive : std_logic_vector(gPortCount downto 0) := (others => cInactivated);
--! Receive path array
signal rxPath : tRmiiPathArray(gPortCount downto 0);
--! Receive path array delayed by one cycle
signal rxPath_l : tRmiiPathArray(gPortCount downto 0);
--! Transmit path array
signal txPath : tRmiiPathArray(gPortCount downto 0);
--! Stored transmit mask (is taken from iTxMask when to packet transfer is in progress)
signal txMask_reg : std_logic_vector(gPortCount downto 1);
begin
rxPath <= iRx & cRmiiPathInit;
oTx <= txPath(oTx'range);
do: process (iRst, iClk)
variable vActive : boolean;
variable vMaster : integer range 0 to gPortCount;
variable vMasterAtCollision : integer range 0 to gPortCount;
variable vCollision : boolean;
variable vRxDvm : std_logic_vector(gPortCount downto 0);
begin
if iRst = cActivated then
rxPath_l <= (others => cRmiiPathInit);
txPath <= (others => cRmiiPathInit);
vActive := false;
vMaster := 0;
vMasterAtCollision := 0;
vCollision := false;
txMask_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
rxPath_l <= rxPath;
if vActive = false then
if rmiiGetEnable(rxPath_l) /= cPortsAreInactive then
for i in 1 to gPortCount loop
if (rxPath_l(i).enable = cActivated and
(rxPath_l(i).data(0) = cActivated or rxPath_l(i).data(1) = cActivated)) then
vMaster := i;
vActive := true;
exit;
end if;
end loop;
end if;
else
if rxPath_l(vMaster).enable = cInactivated and rxPath(vMaster).enable = cInactivated then
vMaster := 0;
end if;
if rmiiGetEnable(rxPath_l) = cPortsAreInactive and rmiiGetEnable(rxPath) = cPortsAreInactive then
vActive := false;
end if;
end if;
if vMaster = 0 then
txPath <= (others => cRmiiPathInit);
-- overtake new iTxMask only, when there is no active frame.
txMask_reg <= iTxMask;
else
for i in 1 to gPortCount loop -- output received frame to every port
if i /= vMaster then -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> iTxMask is set to cActivated) or the internal port (mac)
if txMask_reg(i) = cActivated or vMaster = iIntPort then
txPath(i).enable <= cActivated;
txPath(i).data <= rxPath_l(vMaster).data;
end if;
-- if there is a frame received and another is sent => collision!
if rxPath_l(i).enable = cActivated then
vCollision := true;
vMasterAtCollision := vMaster;
end if;
end if;
end loop;
end if;
if vCollision = true then
txPath(vMasterAtCollision).enable <= cActivated;
txPath(vMasterAtCollision).data <= "01";
vRxDvm := rmiiGetEnable(rxPath_l);
vRxDvm(vMasterAtCollision) := cInactivated;
if vRxDvm = cPortsAreInactive then
txPath(vMasterAtCollision) <= cRmiiPathInit;
vCollision := false;
vMasterAtCollision := 0;
end if;
end if;
-- output the master port - identifies the port (1...n) which has received the packet.
-- if master is 0, the hub is inactive.
oRxPort <= vMaster;
end if;
end process do;
end rtl;
| gpl-2.0 |
riverever/verilogTestSuit | ivltests/br943_944.vhd | 3 | 532 | library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
type t is (one, zero);
signal r : t;
begin
q <= '1' when r = one else '0';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= zero;
else
case r is
when zero => r <= one;
when others => r <= zero;
end case;
end if;
end if;
end process;
end a;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/rgb_grayscale_v1_00_a/hdl/vhdl/rgb_grayscale.vhd | 1 | 3672 | -- rgb_grayscale.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils_v1_00_a;
use utils_v1_00_a.multiply18;
---
-- Performs RGB to grayscale conversion.
-- The result is that all color channels
-- have the same value.
---
entity rgb_grayscale is
port (
CLK : in std_logic;
CE : in std_logic;
IN_R : in std_logic_vector(7 downto 0);
IN_B : in std_logic_vector(7 downto 0);
IN_G : in std_logic_vector(7 downto 0);
IN_DE : in std_logic;
IN_HS : in std_logic;
IN_VS : in std_logic;
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
---
-- Uses theorem
-- G := r * 0.30 + g * 0.59 + b * 0.11
--
-- Multiplication is performed in fixed point arithmetic
-- using Xilinx DSP blocks. Extends each 8b channel to
-- 18 bits for enough precision.
-- After mutliplication and sum it is divided by 1024.
---
architecture dsp of rgb_grayscale is
constant RAW_RED_FACTOR : real := 0.30;
constant RAW_GREEN_FACTOR : real := 0.59;
constant RAW_BLUE_FACTOR : real := 0.11;
constant INT_RED_FACTOR : integer := integer(RAW_RED_FACTOR * 1024.0);
constant INT_GREEN_FACTOR : integer := integer(RAW_GREEN_FACTOR * 1024.0);
constant INT_BLUE_FACTOR : integer := integer(RAW_BLUE_FACTOR * 1024.0);
constant RED_FACTOR : std_logic_vector(17 downto 0) := conv_std_logic_vector(INT_RED_FACTOR, 18);
constant GREEN_FACTOR : std_logic_vector(17 downto 0) := conv_std_logic_vector(INT_GREEN_FACTOR, 18);
constant BLUE_FACTOR : std_logic_vector(17 downto 0) := conv_std_logic_vector(INT_BLUE_FACTOR, 18);
signal arg_r : std_logic_vector(17 downto 0);
signal arg_g : std_logic_vector(17 downto 0);
signal arg_b : std_logic_vector(17 downto 0);
signal prod_r : std_logic_vector(35 downto 0);
signal prod_g : std_logic_vector(35 downto 0);
signal prod_b : std_logic_vector(35 downto 0);
signal prod_de : std_logic;
signal prod_hs : std_logic;
signal prod_vs : std_logic;
signal gray_c : std_logic_vector(35 downto 0);
signal gray_de : std_logic;
signal gray_hs : std_logic;
signal gray_vs : std_logic;
begin
arg_r <= "0000000000" & IN_R;
arg_g <= "0000000000" & IN_G;
arg_b <= "0000000000" & IN_B;
mult_r : entity utils_v1_00_a.multiply18
generic map (
CTL_WIDTH => 1
)
port map (
CLK => CLK,
CE => CE,
A => arg_r,
B => RED_FACTOR,
P => prod_r,
CTLI(0) => IN_DE,
CTLO(0) => prod_de
);
mult_g : entity utils_v1_00_a.multiply18
generic map (
CTL_WIDTH => 1
)
port map (
CLK => CLK,
CE => CE,
A => arg_g,
B => GREEN_FACTOR,
P => prod_g,
CTLI(0) => IN_HS,
CTLO(0) => prod_hs
);
mult_b : entity utils_v1_00_a.multiply18
generic map (
CTL_WIDTH => 1
)
port map (
CLK => CLK,
CE => CE,
A => arg_b,
B => BLUE_FACTOR,
P => prod_b,
CTLI(0) => IN_VS,
CTLO(0) => prod_VS
);
----------------------------------
sum_outp : process(CLK, CE, prod_r, prod_g, prod_b, prod_de, prod_hs, prod_vs)
begin
if rising_edge(CLK) then
if CE = '1' then
gray_c <= prod_r + prod_g + prod_b;
gray_de <= prod_de;
gray_hs <= prod_hs;
gray_vs <= prod_vs;
end if;
end if;
end process;
OUT_R <= gray_c(17 downto 10);
OUT_G <= gray_c(17 downto 10);
OUT_B <= gray_c(17 downto 10);
OUT_DE <= gray_de;
OUT_HS <= gray_hs;
OUT_VS <= gray_vs;
end architecture;
| gpl-2.0 |
spesialstyrker/boula | gen/FIFO/simulation/FIFO_tb.vhd | 1 | 6020 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FIFO_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.FIFO_pkg.ALL;
ENTITY FIFO_tb IS
END ENTITY;
ARCHITECTURE FIFO_arch OF FIFO_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from FIFO_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of FIFO_synth
FIFO_synth_inst:FIFO_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
S_ACLK => wr_clk,
M_ACLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 |
sandeshghimire/model-based-fpga-desing | matlab_model/hdlsrc/hdlcodercpu_eml/SinglePortRAM_Inst0.vhd | 1 | 2284 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\SinglePortRAM_Inst0.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: SinglePortRAM_Inst0
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/SinglePortRAM_Inst0
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SinglePortRAM_Inst0 IS
PORT( clk : IN std_logic;
enb : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0); -- int8
addr : IN std_logic_vector(7 DOWNTO 0); -- uint8
we : IN std_logic; -- ufix1
dout : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END SinglePortRAM_Inst0;
ARCHITECTURE rtl OF SinglePortRAM_Inst0 IS
-- Component Declarations
COMPONENT SinglePortRAM_256x8b
PORT( clk : IN std_logic;
enb : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0); -- int8
addr : IN std_logic_vector(7 DOWNTO 0); -- uint8
we : IN std_logic; -- ufix1
dout : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : SinglePortRAM_256x8b
USE ENTITY work.SinglePortRAM_256x8b(rtl);
-- Signals
SIGNAL dout_tmp : std_logic_vector(7 DOWNTO 0); -- ufix8
BEGIN
u_SinglePortRAM_256x8b : SinglePortRAM_256x8b
PORT MAP( clk => clk,
enb => enb,
din => din, -- int8
addr => addr, -- uint8
we => we, -- ufix1
dout => dout_tmp -- int8
);
dout <= dout_tmp;
END rtl;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/rgb_async_v1_00_a/hdl/vhdl/rgb_async.vhd | 1 | 2194 | -- rgb_async.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library utils_v1_00_a;
use utils_v1_00_a.afifo;
---
-- Every IN_CLK data are written unless
-- the FULL flag is asserted.
-- Every OUT_CLK data are read unless
-- the EMPTY flag is asserted.
--
-- Not tested, never used...
---
entity rgb_async is
port (
IN_CLK : in std_logic;
IN_RST : in std_logic;
FULL : out std_logic;
IN_R : in std_logic_vector(7 downto 0);
IN_B : in std_logic_vector(7 downto 0);
IN_G : in std_logic_vector(7 downto 0);
IN_DE : in std_logic;
IN_HS : in std_logic;
IN_VS : in std_logic;
OUT_CLK : in std_logic;
OUT_RST : in std_logic;
EMPTY : out std_logic;
OUT_R : out std_logic_vector(7 downto 0);
OUT_G : out std_logic_vector(7 downto 0);
OUT_B : out std_logic_vector(7 downto 0);
OUT_DE : out std_logic;
OUT_HS : out std_logic;
OUT_VS : out std_logic
);
end entity;
architecture afifo of rgb_async is
signal rgb_in : std_logic_vector(26 downto 0);
signal rgb_we : std_logic;
signal rgb_out : std_logic_vector(26 downto 0);
signal rgb_re : std_logic;
signal rgb_full : std_logic;
signal rgb_empty : std_logic;
signal or_reset : std_logic;
begin
or_reset <= IN_RST or OUT_RST;
---------------------
rgb_in( 7 downto 0) <= IN_R;
rgb_in(15 downto 8) <= IN_G;
rgb_in(23 downto 16) <= IN_B;
rgb_in(24) <= IN_DE;
rgb_in(25) <= IN_HS;
rgb_in(26) <= IN_VS;
OUT_R <= rgb_out( 7 downto 0);
OUT_G <= rgb_out(15 downto 8);
OUT_B <= rgb_out(23 downto 16);
OUT_DE <= rgb_out(24);
OUT_HS <= rgb_out(25);
OUT_VS <= rgb_out(26);
rgb_we <= not rgb_full;
rgb_re <= not rgb_empty;
FULL <= rgb_full;
EMPTY <= rgb_empty;
---------------------
afifo_i : entity utils_v1_00_a.afifo
generic map (
DWIDTH => 27,
DEPTH => 16
)
port map (
WCLK => IN_CLK,
RCLK => OUT_CLK,
RESET => or_reset,
WE => rgb_we,
FULL => rgb_full,
DI => rgb_in,
RE => rgb_re,
EMPTY => rgb_empty.
DO => rgb_out
);
end architecture;
| gpl-2.0 |
sandeshghimire/model-based-fpga-desing | matlab_model/hdlsrc/Control_Unit.vhd | 1 | 30490 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc\Control_Unit.vhd
-- Created: 2014-03-05 16:19:14
--
-- Generated by MATLAB 7.12 and Simulink HDL Coder 2.1
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Control_Unit
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Control Unit
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Control_Unit IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0); -- int8
in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
master_rst : IN std_logic;
IR_in : IN std_logic_vector(11 DOWNTO 0); -- ufix12
shifter_sel : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
out_flags : OUT std_logic_vector(3 DOWNTO 0); -- ufix4
ALU_func : OUT std_logic_vector(2 DOWNTO 0); -- ufix3
print_data : OUT std_logic;
DM_addr : OUT std_logic_vector(7 DOWNTO 0); -- uint8
DM_r_w : OUT std_logic; -- ufix1
AC_func : OUT std_logic_vector(2 DOWNTO 0); -- ufix3
AC_data : OUT std_logic_vector(7 DOWNTO 0); -- int8
IR_func : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
PC_func : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
addr_inc : OUT std_logic_vector(7 DOWNTO 0); -- int8
IM_read : OUT std_logic; -- ufix1
hlt : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END Control_Unit;
ARCHITECTURE rtl OF Control_Unit IS
-- Signals
SIGNAL data_in_signed : signed(7 DOWNTO 0); -- int8
SIGNAL in_flags_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL IR_in_unsigned : unsigned(11 DOWNTO 0); -- ufix12
SIGNAL shifter_sel_tmp : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL out_flags_tmp : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL ALU_func_tmp : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL DM_addr_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL AC_func_tmp : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL AC_data_tmp : signed(7 DOWNTO 0); -- int8
SIGNAL IR_func_tmp : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL PC_func_tmp : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL addr_inc_tmp : signed(7 DOWNTO 0); -- int8
SIGNAL hlt_tmp : unsigned(7 DOWNTO 0); -- uint8
SIGNAL CPU_state : unsigned(7 DOWNTO 0); -- uint8
SIGNAL previous_CPU_state : unsigned(7 DOWNTO 0); -- uint8
SIGNAL major_opcode : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL minor_opcode : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL address_data : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL indirect_address : unsigned(7 DOWNTO 0); -- uint8
SIGNAL CPU_state_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL previous_CPU_state_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL major_opcode_next : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL minor_opcode_next : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL address_data_next : unsigned(7 DOWNTO 0); -- ufix8
SIGNAL indirect_address_next : unsigned(7 DOWNTO 0); -- uint8
BEGIN
data_in_signed <= signed(data_in);
in_flags_unsigned <= unsigned(in_flags);
IR_in_unsigned <= unsigned(IR_in);
Control_Unit_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
CPU_state <= to_unsigned(0, 8);
previous_CPU_state <= to_unsigned(0, 8);
major_opcode <= to_unsigned(0, 8);
minor_opcode <= to_unsigned(0, 8);
address_data <= to_unsigned(0, 8);
indirect_address <= to_unsigned(0, 8);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
CPU_state <= CPU_state_next;
previous_CPU_state <= previous_CPU_state_next;
major_opcode <= major_opcode_next;
minor_opcode <= minor_opcode_next;
address_data <= address_data_next;
indirect_address <= indirect_address_next;
END IF;
END IF;
END PROCESS Control_Unit_1_process;
Control_Unit_1_output : PROCESS (data_in_signed, in_flags_unsigned, master_rst, IR_in_unsigned, CPU_state, previous_CPU_state,
major_opcode, minor_opcode, address_data, indirect_address)
VARIABLE minor_opcode_bit6 : std_logic;
VARIABLE temp_address_data : signed(6 DOWNTO 0);
VARIABLE indirect_bit : std_logic;
VARIABLE c : std_logic;
VARIABLE n : std_logic;
VARIABLE minor_opcode_bit4 : std_logic;
VARIABLE v : std_logic;
VARIABLE z : std_logic;
VARIABLE c_0 : unsigned(11 DOWNTO 0);
VARIABLE c_1 : unsigned(11 DOWNTO 0);
VARIABLE c_uint : unsigned(11 DOWNTO 0);
VARIABLE c_uint_0 : unsigned(11 DOWNTO 0);
VARIABLE CPU_state_temp : unsigned(7 DOWNTO 0);
VARIABLE minor_opcode_bit6_0 : std_logic;
VARIABLE temp_address_data_0 : signed(6 DOWNTO 0);
VARIABLE temp_address_data_1 : signed(6 DOWNTO 0);
VARIABLE minor_opcode_bit6_1 : std_logic;
VARIABLE temp_address_data_2 : signed(6 DOWNTO 0);
VARIABLE temp_address_data_3 : signed(6 DOWNTO 0);
VARIABLE indirect_bit_0 : std_logic;
VARIABLE indirect_bit_1 : std_logic;
VARIABLE indirect_bit_2 : std_logic;
VARIABLE indirect_bit_3 : std_logic;
VARIABLE sub_cast : signed(12 DOWNTO 0);
VARIABLE sub_temp : signed(12 DOWNTO 0);
VARIABLE sub_cast_0 : signed(12 DOWNTO 0);
VARIABLE sub_temp_0 : signed(12 DOWNTO 0);
VARIABLE sub_cast_1 : signed(12 DOWNTO 0);
VARIABLE sub_temp_1 : signed(12 DOWNTO 0);
VARIABLE sub_cast_2 : signed(12 DOWNTO 0);
VARIABLE sub_temp_2 : signed(12 DOWNTO 0);
VARIABLE sub_cast_3 : signed(12 DOWNTO 0);
VARIABLE sub_temp_3 : signed(12 DOWNTO 0);
BEGIN
CPU_state_temp := CPU_state;
previous_CPU_state_next <= previous_CPU_state;
major_opcode_next <= major_opcode;
minor_opcode_next <= minor_opcode;
address_data_next <= address_data;
indirect_address_next <= indirect_address;
--MATLAB Function 'CPU_Subsystem_8_bit/Control Unit': '<S5>:1'
-- CPU Controller
--
-- The CPU Instruction Set:
-- ------------------------
--
-- LDA <loc>: AC = content(<loc>)
-- LDAI <loc>: AC = content(content(<loc>))
-- AND <loc>: AC = AC & content(<loc>)
-- ANDI <loc>: AC = AC & content(content(<loc>))
-- ADD <loc>: AC = AC + content(<loc>) + C(flag)
-- ADDI <loc>: AC = AC + content(content(<loc>)) + C(flag)
-- SUB <loc>: AC = AC - content(<loc>) - C(flag)
-- SUBI <loc>: AC = AC - content(content(<loc>)) - C(flag)
-- JMP <loc>: Jump to <PC + <loc>>
-- LI <const>: AC = <const>
-- STA <loc>: content(<loc>) = AC
-- STAI <loc>: content(content(<loc>)) = AC
-- BRA_C <loc>: Jump to <PC + <loc>> if (C(flag) == 1)
-- BRA_N <loc>: Jump to <PC + <loc>> if (N(flag) == 1)
-- BRA_V <loc>: Jump to <PC + <loc>> if (V(flag) == 1)
-- BRA_Z <loc>: Jump to <PC + <loc>> if (Z(flag) == 1)
-- NOP: Do nothing
-- CLA: AC = 0
-- CMA: Complement AC
-- CMC: Complement C(flag)
-- ASL: AC = AC << 1
-- ASR: AC = AC >> 1
-- PRINT: Display value from the memory-mapped location 255
-- CLC: C(flag) = 0
--
-- 12-bit Instruction Encoding:
-- ---------------------------
--
-- LDA: 000 0 <8-bit loc>
-- LDAI: 000 1 <8-bit loc>
-- AND: 001 0 <8-bit loc>
-- ANDI: 001 1 <8-bit loc>
-- ADD: 010 0 <8-bit loc>
-- ADDI: 010 1 <8-bit loc>
-- SUB: 011 0 <8-bit loc>
-- SUBI: 011 1 <8-bit loc>
-- JMP: 1000 <8-bit loc>
-- LI: 1001 <8-bit const>
-- STA: 101 0 <8-bit loc>
-- STAI: 101 1 <8-bit loc>
-- BRA_C: 1100 <8-bit loc>
-- BRA_N: 1101 <8-bit loc>
-- BRA_C: 1110 <8-bit loc>
-- BRA_C: 1111 <8-bit loc>
-- HLT: 111 0 0100 0 000
-- CLA: 111 0 0100 1 000
-- CMA: 111 0 0101 0 000
-- CMC: 111 0 0101 1 000
-- ASL: 111 0 0110 0 000
-- ASR: 111 0 0110 1 000
-- PRINT: 111 0 0111 0 000
-- CLC: 111 0 0111 1 000
-- HDL specific fimath
IF master_rst = '1' THEN
--'<S5>:1:81'
--'<S5>:1:82'
CPU_state_temp := to_unsigned(0, 8);
END IF;
--'<S5>:1:85'
shifter_sel_tmp <= to_unsigned(0, 2);
--'<S5>:1:86'
ALU_func_tmp <= to_unsigned(0, 3);
--'<S5>:1:87'
out_flags_tmp <= in_flags_unsigned;
--'<S5>:1:88'
AC_func_tmp <= to_unsigned(4, 3);
-- NOP
--'<S5>:1:89'
AC_data_tmp <= to_signed(0, 8);
--'<S5>:1:90'
IR_func_tmp <= to_unsigned(3, 2);
-- NOP
--'<S5>:1:91'
PC_func_tmp <= to_unsigned(3, 2);
-- NOP
--'<S5>:1:92'
IM_read <= '0';
--'<S5>:1:93'
DM_addr_tmp <= to_unsigned(0, 8);
--'<S5>:1:94'
DM_r_w <= '0';
--'<S5>:1:95'
addr_inc_tmp <= to_signed(0, 8);
--'<S5>:1:96'
print_data <= '0';
--'<S5>:1:97'
hlt_tmp <= to_unsigned(0, 8);
-- Instruction: <12..1>
-- major_opcode: <12..10>
-- indirect_addressing: <9>
-- minor_opcode: <9..4>
-- address bits: <8..1>
--'<S5>:1:117'
CASE CPU_state_temp IS
WHEN "00000000" =>
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- RESETTING OUTPUTS
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--'<S5>:1:122'
PC_func_tmp <= to_unsigned(0, 2);
--'<S5>:1:123'
AC_func_tmp <= to_unsigned(0, 3);
--'<S5>:1:124'
IR_func_tmp <= to_unsigned(0, 2);
--'<S5>:1:125'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:126'
CPU_state_temp := to_unsigned(1, 8);
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- FETCH
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
WHEN "00000001" =>
-- Read from IM
--'<S5>:1:133'
IM_read <= '1';
-- Increment PC
--'<S5>:1:135'
PC_func_tmp <= to_unsigned(2, 2);
-- store into IR
--'<S5>:1:137'
IR_func_tmp <= to_unsigned(1, 2);
--'<S5>:1:139'
CPU_state_temp := to_unsigned(2, 8);
WHEN "00000010" =>
-- Read from IR
--'<S5>:1:143'
IR_func_tmp <= to_unsigned(2, 2);
-- Accommodating for the 'unit delay' from IR_out to IR_in
--'<S5>:1:146'
CPU_state_temp := to_unsigned(3, 8);
WHEN "00000011" =>
-- IR_in <12..10>
--'<S5>:1:150'
c_0 := IR_in_unsigned srl 9;
major_opcode_next <= c_0(7 DOWNTO 0);
-- IR_in <9..4>
--'<S5>:1:153'
c_1 := IR_in_unsigned srl 3;
c_uint := c_1 AND to_unsigned(63, 12);
minor_opcode_next <= c_uint(7 DOWNTO 0);
-- IR_in <8..1>
--'<S5>:1:156'
c_uint_0 := IR_in_unsigned AND to_unsigned(255, 12);
address_data_next <= c_uint_0(7 DOWNTO 0);
-- Go to the decode stage
--'<S5>:1:159'
CPU_state_temp := to_unsigned(4, 8);
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-- DECODE AND EXECUTE
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
WHEN "00000100" =>
--'<S5>:1:165'
previous_CPU_state_next <= CPU_state_temp;
CASE major_opcode IS
WHEN "00000000" =>
-- LDA
-- minor_opcode contains the address (assuming direct addressing)
--'<S5>:1:170'
DM_addr_tmp <= address_data;
-- Read the data memory
--'<S5>:1:172'
DM_r_w <= '0';
-- Simply pass the value read from memory
--'<S5>:1:174'
CPU_state_temp := to_unsigned(13, 8);
WHEN "00000001" =>
-- AND
--'<S5>:1:178'
DM_addr_tmp <= address_data;
-- Reading the data memory for address or data
--'<S5>:1:180'
DM_r_w <= '0';
--'<S5>:1:182'
CPU_state_temp := to_unsigned(15, 8);
WHEN "00000010" =>
-- ADD
--'<S5>:1:186'
DM_addr_tmp <= address_data;
-- Reading the data memory for address or data
--'<S5>:1:188'
DM_r_w <= '0';
--'<S5>:1:190'
CPU_state_temp := to_unsigned(17, 8);
WHEN "00000011" =>
-- SUB
--'<S5>:1:194'
DM_addr_tmp <= address_data;
-- Reading the data memory for address or data
--'<S5>:1:196'
DM_r_w <= '0';
--'<S5>:1:198'
CPU_state_temp := to_unsigned(19, 8);
WHEN "00000100" =>
--'<S5>:1:201'
minor_opcode_bit6 := minor_opcode(5);
CASE minor_opcode_bit6 IS
WHEN '0' =>
-- JMP
--'<S5>:1:205'
temp_address_data := signed(address_data(6 DOWNTO 0));
--'<S5>:1:206'
sub_cast := resize(temp_address_data & '0' & '0' & '0' & '0' & '0', 13);
sub_temp := sub_cast - 32;
addr_inc_tmp <= sub_temp(12 DOWNTO 5);
--'<S5>:1:207'
PC_func_tmp <= to_unsigned(1, 2);
WHEN '1' =>
-- LI
--'<S5>:1:211'
AC_data_tmp <= signed(address_data);
--'<S5>:1:212'
AC_func_tmp <= to_unsigned(1, 3);
WHEN OTHERS =>
NULL;
END CASE;
-- Go back to the fetch stage again
--'<S5>:1:215'
CPU_state_temp := to_unsigned(1, 8);
WHEN "00000101" =>
-- STA
-- minor_opcode contains the address (assuming direct addressing)
--'<S5>:1:220'
DM_addr_tmp <= address_data;
--'<S5>:1:221'
indirect_bit := minor_opcode(5);
IF indirect_bit /= '0' THEN
-- indirect addressing
-- Read the address from the data memory
--'<S5>:1:225'
DM_r_w <= '0';
--'<S5>:1:226'
CPU_state_temp := to_unsigned(21, 8);
ELSE
-- Write into the data memory
--'<S5>:1:229'
DM_r_w <= '1';
-- Go back to the fetch stage again
--'<S5>:1:231'
CPU_state_temp := to_unsigned(25, 8);
-- going to 'otherwise'
END IF;
WHEN "00000110" =>
--'<S5>:1:235'
minor_opcode_bit6_0 := minor_opcode(5);
CASE minor_opcode_bit6_0 IS
WHEN '0' =>
-- special branches:
-- BRA_C
--'<S5>:1:240'
c := in_flags_unsigned(3);
IF c /= '0' THEN
--'<S5>:1:242'
temp_address_data_0 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:243'
sub_cast_1 := resize(temp_address_data_0 & '0' & '0' & '0' & '0' & '0', 13);
sub_temp_1 := sub_cast_1 - 32;
addr_inc_tmp <= sub_temp_1(12 DOWNTO 5);
--'<S5>:1:244'
PC_func_tmp <= to_unsigned(1, 2);
END IF;
WHEN '1' =>
-- BRA_N
--'<S5>:1:249'
n := in_flags_unsigned(2);
IF n /= '0' THEN
--'<S5>:1:251'
temp_address_data_1 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:252'
sub_cast_0 := resize(temp_address_data_1 & '0' & '0' & '0' & '0' & '0', 13);
sub_temp_0 := sub_cast_0 - 32;
addr_inc_tmp <= sub_temp_0(12 DOWNTO 5);
--'<S5>:1:253'
PC_func_tmp <= to_unsigned(1, 2);
END IF;
WHEN OTHERS =>
NULL;
END CASE;
-- Go back to the fetch stage again
--'<S5>:1:257'
CPU_state_temp := to_unsigned(15, 8);
WHEN "00000111" =>
-- by default, go back to the fetch stage again
--'<S5>:1:261'
CPU_state_temp := to_unsigned(1, 8);
--'<S5>:1:262'
minor_opcode_bit4 := minor_opcode(3);
IF (minor_opcode_bit4 /= '0') = FALSE THEN
--'<S5>:1:263'
-- Further cases of special branches:
--'<S5>:1:265'
minor_opcode_bit6_1 := minor_opcode(5);
CASE minor_opcode_bit6_1 IS
WHEN '0' =>
-- BRA_V
--'<S5>:1:269'
v := in_flags_unsigned(1);
IF v /= '0' THEN
--'<S5>:1:271'
temp_address_data_2 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:272'
sub_cast_2 := resize(temp_address_data_2 & '0' & '0' & '0' & '0' & '0', 13);
sub_temp_2 := sub_cast_2 - 32;
addr_inc_tmp <= sub_temp_2(12 DOWNTO 5);
--'<S5>:1:273'
PC_func_tmp <= to_unsigned(1, 2);
END IF;
WHEN '1' =>
-- BRA_Z
--'<S5>:1:278'
z := in_flags_unsigned(0);
IF z /= '0' THEN
--'<S5>:1:280'
temp_address_data_3 := signed(address_data(6 DOWNTO 0));
--'<S5>:1:281'
sub_cast_3 := resize(temp_address_data_3 & '0' & '0' & '0' & '0' & '0', 13);
sub_temp_3 := sub_cast_3 - 32;
addr_inc_tmp <= sub_temp_3(12 DOWNTO 5);
--'<S5>:1:282'
PC_func_tmp <= to_unsigned(1, 2);
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
-- Instructions having no operands
CASE minor_opcode IS
WHEN "00001000" =>
-- HLT
-- Stop the simulation
--'<S5>:1:291'
hlt_tmp <= to_unsigned(1, 8);
--'<S5>:1:292'
CPU_state_temp := to_unsigned(22, 8);
WHEN "00001001" =>
-- CLA
--'<S5>:1:295'
AC_func_tmp <= to_unsigned(0, 3);
WHEN "00001010" =>
-- CMA
--'<S5>:1:299'
ALU_func_tmp <= to_unsigned(4, 3);
--'<S5>:1:300'
shifter_sel_tmp <= to_unsigned(3, 2);
--'<S5>:1:301'
CPU_state_temp := to_unsigned(6, 8);
WHEN "00001011" =>
-- CMC
--'<S5>:1:305'
ALU_func_tmp <= to_unsigned(5, 3);
--'<S5>:1:306'
shifter_sel_tmp <= to_unsigned(3, 2);
WHEN "00001100" =>
-- ASL
--'<S5>:1:310'
shifter_sel_tmp <= to_unsigned(1, 2);
--'<S5>:1:311'
CPU_state_temp := to_unsigned(6, 8);
WHEN "00001101" =>
-- ASR
--'<S5>:1:315'
shifter_sel_tmp <= to_unsigned(2, 2);
--'<S5>:1:316'
CPU_state_temp := to_unsigned(6, 8);
WHEN "00001110" =>
-- PRINT
--'<S5>:1:320'
DM_addr_tmp <= to_unsigned(255, 8);
-- Read the data memory
--'<S5>:1:322'
DM_r_w <= '0';
--'<S5>:1:324'
CPU_state_temp := to_unsigned(12, 8);
WHEN "00001111" =>
-- CLC
--'<S5>:1:328'
ALU_func_tmp <= to_unsigned(7, 3);
--'<S5>:1:329'
shifter_sel_tmp <= to_unsigned(3, 2);
WHEN OTHERS =>
-- by default, go back to the fetch stage again
--'<S5>:1:333'
CPU_state_temp := to_unsigned(1, 8);
-- Minor Opcode cases end here
END CASE;
-- Major Opcode cases end here
WHEN OTHERS =>
NULL;
END CASE;
-- introducing delay
WHEN "00000110" =>
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:343'
AC_func_tmp <= to_unsigned(2, 3);
--'<S5>:1:344'
previous_CPU_state_next <= CPU_state_temp;
-- Go back to the fetch stage again
--'<S5>:1:346'
CPU_state_temp := to_unsigned(1, 8);
-- Operations with indirect addressing
WHEN "00000111" =>
-- LDA Indirect
-- data_in is the address read from the data memory
--'<S5>:1:352'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:354'
DM_r_w <= '0';
--'<S5>:1:356'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:357'
CPU_state_temp := to_unsigned(13, 8);
WHEN "00001000" =>
-- AND Indirect
-- data_in is the address read from the data memory
--'<S5>:1:362'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:364'
DM_r_w <= '0';
--'<S5>:1:366'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:367'
CPU_state_temp := to_unsigned(15, 8);
WHEN "00001001" =>
-- ADD Indirect
-- data_in is the address read from the data memory
--'<S5>:1:372'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:374'
DM_r_w <= '0';
--'<S5>:1:376'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:377'
CPU_state_temp := to_unsigned(17, 8);
WHEN "00001010" =>
-- SUB Indirect
-- data_in is the address read from the data memory
--'<S5>:1:382'
DM_addr_tmp <= indirect_address;
-- Read the data memory
--'<S5>:1:384'
DM_r_w <= '0';
--'<S5>:1:386'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:387'
CPU_state_temp := to_unsigned(19, 8);
WHEN "00001011" =>
-- STA Indirect
-- data_in is the address read from the data memory
--'<S5>:1:392'
IF data_in_signed(7) = '1' THEN
DM_addr_tmp <= "00000000";
ELSE
DM_addr_tmp <= unsigned(data_in_signed);
END IF;
-- Write the data memory
--'<S5>:1:394'
DM_r_w <= '1';
--'<S5>:1:395'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:396'
CPU_state_temp := to_unsigned(1, 8);
WHEN "00001100" =>
-- PRINT
--'<S5>:1:400'
print_data <= '1';
--'<S5>:1:401'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:402'
CPU_state_temp := to_unsigned(1, 8);
WHEN "00001101" =>
-- LDA (contd.)
-- Simply pass the value read from memory
--'<S5>:1:407'
ALU_func_tmp <= to_unsigned(6, 3);
--'<S5>:1:408'
shifter_sel_tmp <= to_unsigned(3, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:410'
--'<S5>:1:411'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:412'
CPU_state_temp := to_unsigned(14, 8);
ELSE
--'<S5>:1:414'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:415'
CPU_state_temp := to_unsigned(6, 8);
END IF;
WHEN "00001110" =>
--'<S5>:1:419'
indirect_bit_0 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:421'
AC_func_tmp <= to_unsigned(2, 3);
--'<S5>:1:423'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_0 /= '0' THEN
-- indirect addressing
--'<S5>:1:426'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:427'
CPU_state_temp := to_unsigned(7, 8);
ELSE
--'<S5>:1:429'
CPU_state_temp := to_unsigned(25, 8);
END IF;
WHEN "00001111" =>
-- AND (contd.)
--'<S5>:1:435'
ALU_func_tmp <= to_unsigned(1, 3);
--'<S5>:1:436'
shifter_sel_tmp <= to_unsigned(3, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:438'
--'<S5>:1:439'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:440'
CPU_state_temp := to_unsigned(16, 8);
ELSE
--'<S5>:1:442'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:443'
CPU_state_temp := to_unsigned(6, 8);
END IF;
WHEN "00010000" =>
--'<S5>:1:447'
indirect_bit_1 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:449'
AC_func_tmp <= to_unsigned(2, 3);
--'<S5>:1:451'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_1 /= '0' THEN
-- indirect addressing
--'<S5>:1:454'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:455'
CPU_state_temp := to_unsigned(8, 8);
ELSE
--'<S5>:1:457'
CPU_state_temp := to_unsigned(25, 8);
END IF;
WHEN "00010001" =>
-- ADD (contd.)
--'<S5>:1:462'
ALU_func_tmp <= to_unsigned(2, 3);
--'<S5>:1:463'
shifter_sel_tmp <= to_unsigned(3, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:465'
--'<S5>:1:466'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:467'
CPU_state_temp := to_unsigned(18, 8);
ELSE
--'<S5>:1:469'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:470'
CPU_state_temp := to_unsigned(6, 8);
END IF;
WHEN "00010010" =>
--'<S5>:1:474'
indirect_bit_2 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:476'
AC_func_tmp <= to_unsigned(2, 3);
--'<S5>:1:478'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_2 /= '0' THEN
-- indirect addressing
--'<S5>:1:481'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:482'
CPU_state_temp := to_unsigned(9, 8);
ELSE
--'<S5>:1:484'
CPU_state_temp := to_unsigned(25, 8);
END IF;
WHEN "00010011" =>
-- SUB (contd.)
--'<S5>:1:489'
ALU_func_tmp <= to_unsigned(3, 3);
--'<S5>:1:490'
shifter_sel_tmp <= to_unsigned(3, 2);
IF previous_CPU_state = 4 THEN
--'<S5>:1:492'
--'<S5>:1:493'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:494'
CPU_state_temp := to_unsigned(20, 8);
ELSE
--'<S5>:1:496'
previous_CPU_state_next <= CPU_state_temp;
--'<S5>:1:497'
CPU_state_temp := to_unsigned(6, 8);
END IF;
WHEN "00010100" =>
--'<S5>:1:501'
indirect_bit_3 := minor_opcode(5);
-- accounting for the delay from shift_out to AC_in2
--'<S5>:1:503'
AC_func_tmp <= to_unsigned(2, 3);
--'<S5>:1:505'
previous_CPU_state_next <= CPU_state_temp;
IF indirect_bit_3 /= '0' THEN
-- indirect addressing
--'<S5>:1:508'
IF data_in_signed(7) = '1' THEN
indirect_address_next <= "00000000";
ELSE
indirect_address_next <= unsigned(data_in_signed);
END IF;
--'<S5>:1:509'
CPU_state_temp := to_unsigned(10, 8);
ELSE
--'<S5>:1:512'
CPU_state_temp := to_unsigned(25, 8);
END IF;
WHEN "00010101" =>
-- STA indirect
--'<S5>:1:517'
CPU_state_temp := to_unsigned(11, 8);
WHEN "00010110" =>
-- lock state
--'<S5>:1:521'
hlt_tmp <= to_unsigned(1, 8);
--'<S5>:1:522'
CPU_state_temp := to_unsigned(22, 8);
WHEN OTHERS =>
--'<S5>:1:525'
previous_CPU_state_next <= CPU_state_temp;
-- by default, go back to the fetch stage again
--'<S5>:1:527'
CPU_state_temp := to_unsigned(1, 8);
-- switch(CPU_state) end here
END CASE;
CPU_state_next <= CPU_state_temp;
END PROCESS Control_Unit_1_output;
shifter_sel <= std_logic_vector(shifter_sel_tmp);
out_flags <= std_logic_vector(out_flags_tmp);
ALU_func <= std_logic_vector(ALU_func_tmp);
DM_addr <= std_logic_vector(DM_addr_tmp);
AC_func <= std_logic_vector(AC_func_tmp);
AC_data <= std_logic_vector(AC_data_tmp);
IR_func <= std_logic_vector(IR_func_tmp);
PC_func <= std_logic_vector(PC_func_tmp);
addr_inc <= std_logic_vector(addr_inc_tmp);
hlt <= std_logic_vector(hlt_tmp);
END rtl;
| gpl-2.0 |
sandeshghimire/model-based-fpga-desing | matlab_model/hdlsrc/hdlcodercpu_eml/Shifter_8_bit.vhd | 1 | 3733 | -- -------------------------------------------------------------
--
-- File Name: hdlsrc\hdlcodercpu_eml\Shifter_8_bit.vhd
-- Created: 2014-08-26 11:41:14
--
-- Generated by MATLAB 8.3 and HDL Coder 3.4
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Shifter_8_bit
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/Shifter (8-bit)
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Shifter_8_bit IS
PORT( select_rsvd : IN std_logic_vector(1 DOWNTO 0); -- ufix2
input : IN std_logic_vector(7 DOWNTO 0); -- int8
in_flags : IN std_logic_vector(3 DOWNTO 0); -- ufix4
out_flags : OUT std_logic_vector(3 DOWNTO 0); -- ufix4
shift_out : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END Shifter_8_bit;
ARCHITECTURE rtl OF Shifter_8_bit IS
-- Functions
-- HDLCODER_TO_STDLOGIC
FUNCTION hdlcoder_to_stdlogic(arg: boolean) RETURN std_logic IS
BEGIN
IF arg THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END FUNCTION;
-- Signals
SIGNAL select_unsigned : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL input_signed : signed(7 DOWNTO 0); -- int8
SIGNAL in_flags_unsigned : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL out_flags_tmp : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL shift_out_tmp : signed(7 DOWNTO 0); -- int8
BEGIN
select_unsigned <= unsigned(select_rsvd);
input_signed <= signed(input);
in_flags_unsigned <= unsigned(in_flags);
Shifter_8_bit_1_output : PROCESS (select_unsigned, input_signed, in_flags_unsigned)
VARIABLE c_out : std_logic;
VARIABLE sign_bit : std_logic;
VARIABLE is_zero : unsigned(7 DOWNTO 0);
VARIABLE zero_ufix1 : std_logic;
VARIABLE c_uint : std_logic;
VARIABLE c : signed(7 DOWNTO 0);
VARIABLE c_0 : BOOLEAN;
BEGIN
--MATLAB Function 'CPU_Subsystem_8_bit/Shifter (8-bit)': '<S11>:1'
-- An 8-bit shifter:
-- select = 1 => shift left by 1 bit
-- select = 2 => shift right by 1 bit
-- otherwise, pass the input
-- HDL specific fimath
-- Overflow (V)
--'<S11>:1:16'
c_uint := in_flags_unsigned(1);
-- Carry (C)
--'<S11>:1:19'
c_out := in_flags_unsigned(3);
CASE select_unsigned IS
WHEN "01" =>
-- shift left
-- affects C and V as well
--'<S11>:1:25'
c := input_signed sll 1;
-- Carry (C)
--'<S11>:1:27'
c_out := input_signed(7);
-- Overflow (V)
--'<S11>:1:29'
c_uint := input_signed(7) XOR input_signed(6);
WHEN "10" =>
-- shift right
--'<S11>:1:32'
c := SHIFT_RIGHT(input_signed , 1);
WHEN OTHERS =>
-- pass the input
--'<S11>:1:35'
c := input_signed;
END CASE;
-- Negativity (N)
--'<S11>:1:39'
sign_bit := c(7);
-- Is Zero? (Z)
--'<S11>:1:42'
c_0 := NOT (c /= 0);
is_zero := '0' & '0' & '0' & '0' & '0' & '0' & '0' & hdlcoder_to_stdlogic(c_0);
--'<S11>:1:43'
zero_ufix1 := is_zero(0);
-- Set [C, N, V, Z] in the flag register
--'<S11>:1:46'
out_flags_tmp <= unsigned'(c_out & sign_bit & c_uint & zero_ufix1);
shift_out_tmp <= c;
END PROCESS Shifter_8_bit_1_output;
out_flags <= std_logic_vector(out_flags_tmp);
shift_out <= std_logic_vector(shift_out_tmp);
END rtl;
| gpl-2.0 |
jviki/rgbproc-repository | rgbproc/pcores/utils_v1_00_a/sim/ipif_generator.vhd | 1 | 6224 | -- ipif_generator.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity ipif_generator is
generic (
DWIDTH : integer := 32;
AWIDTH : integer := 32;
ADDR_MIN : integer := 0;
ADDR_MAX : integer := 128
);
port (
CLK : in std_logic;
RST : in std_logic;
Bus2IP_Addr : out std_logic_vector(AWIDTH - 1 downto 0);
Bus2IP_Data : out std_logic_vector(DWIDTH - 1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector(DWIDTH / 8 - 1 downto 0);
Bus2IP_CS : out std_logic;
IPIF_BUSY : out std_logic;
IPIF_READ : out std_logic;
IPIF_DONE : in std_logic
);
end entity;
architecture full of ipif_generator is
-- should be greater then CLK_FACTOR * AFIFO_DEPTH (eg. 4 * 16)
-- when using asynchronous IPIF otherwise can be set to any value...
constant DELAY_MIN : integer := 70;
constant DELAY_WIDTH : integer := 8;
---
-- Creates a random address conforming to the constraints
-- ADDR_MIN and ADDR_MAX and based on random number 'rnd'.
---
procedure gen_addr(rnd : in integer; addr : out std_logic_vector(Bus2IP_Addr'range)) is
variable rnd_addr : integer;
begin
assert ADDR_MIN < ADDR_MAX
report "Invalid ADDR_{MIN,MAX}, constructs a negative range"
severity failure;
if rnd >= ADDR_MIN and rnd <= ADDR_MAX then
rnd_addr := rnd;
else
rnd_addr := rnd mod (ADDR_MAX - ADDR_MIN + 1) + ADDR_MIN;
end if;
-- be multiple of 4 as PLB used to be...
rnd_addr := rnd_addr - (rnd_addr mod 4);
assert rnd_addr >= ADDR_MIN and rnd_addr <= ADDR_MAX
report "BUG: invalid address generated: " & integer'image(rnd_addr)
severity failure;
-- report "Generated address: " & integer'image(rnd_addr);
addr := conv_std_logic_vector(rnd_addr, addr'length);
end procedure;
---
-- Random generators
---
shared variable aseed0 : integer := 844396720;
shared variable aseed1 : integer := 821616997;
impure function getrand return real is
variable r : real;
begin
uniform(aseed0, aseed1, r);
return r;
end function;
impure function getbool return boolean is
begin
return getrand < 0.5;
end function;
impure function getbit return std_logic is
begin
if getbool then
return '1';
else
return '0';
end if;
end function;
impure function getint return integer is
begin
return integer(getrand * real(integer'high));
end function;
impure function getdelay return integer is
variable delay : integer;
begin
delay := getint;
if delay < DELAY_MIN then
delay := DELAY_MIN + delay;
end if;
if delay mod DELAY_WIDTH < DELAY_MIN then
return DELAY_MIN;
end if;
return delay;
end function;
---
-- Signals
---
type state_t is (s_idle, s_generate, s_busy, s_delay);
signal state : state_t;
signal nstate : state_t;
signal cnt_timer : std_logic_vector(DELAY_WIDTH - 1 downto 0);
signal cnt_timer_in : std_logic_vector(DELAY_WIDTH - 1 downto 0);
signal cnt_timer_ce : std_logic;
signal cnt_timer_le : std_logic;
signal cnt_timer_of : std_logic;
signal wait_enough : std_logic;
signal ipif_addr : std_logic_vector(AWIDTH - 1 downto 0);
signal ipif_data : std_logic_vector(DWIDTH - 1 downto 0);
signal ipif_rnw : std_logic;
signal ipif_be : std_logic_vector(DWIDTH / 8 - 1 downto 0);
signal ipif_cs : std_logic;
begin
wait_enough <= cnt_timer_of;
cnt_timerp : process(CLK, RST, cnt_timer_ce, cnt_timer_le, cnt_timer_in)
begin
if rising_edge(CLK) then
if RST = '1' then
cnt_timer <= (others => '0');
elsif cnt_timer_le = '1' then
cnt_timer <= cnt_timer_in;
elsif cnt_timer_ce = '1' then
if cnt_timer = (cnt_timer'range => '1') then
cnt_timer_of <= '1';
else
cnt_timer_of <= '0';
end if;
cnt_timer <= cnt_timer + 1;
end if;
end if;
end process;
fsm_state : process(CLK, RST, nstate)
begin
if rising_edge(CLK) then
if RST = '1' then
state <= s_idle;
else
state <= nstate;
end if;
end if;
end process;
fsm_next : process(CLK, state, wait_enough, IPIF_DONE)
begin
nstate <= state;
case state is
when s_idle =>
nstate <= s_delay;
when s_delay =>
if wait_enough = '1' then
nstate <= s_generate;
end if;
when s_generate =>
if IPIF_DONE = '1' then
nstate <= s_idle;
else
nstate <= s_busy;
end if;
when s_busy =>
if IPIF_DONE = '1' then
nstate <= s_idle;
end if;
end case;
end process;
fsm_output : process(CLK, state, IPIF_DONE)
variable address : std_logic_vector(Bus2IP_Addr'range);
variable data : integer;
variable be : integer;
variable rnw : std_logic;
variable generated : boolean;
begin
cnt_timer_ce <= '0';
cnt_timer_le <= '0';
case state is
when s_idle =>
cnt_timer_le <= '1';
cnt_timer_in <= conv_std_logic_vector(getdelay, cnt_timer_in'length);
IPIF_BUSY <= '0';
ipif_cs <= '0';
ipif_addr <= (others => 'X');
ipif_data <= (others => 'X');
ipif_be <= (others => 'X');
ipif_rnw <= 'X';
generated := false;
when s_delay =>
cnt_timer_ce <= '1';
IPIF_BUSY <= '0';
ipif_cs <= '0';
ipif_addr <= (others => 'X');
ipif_data <= (others => 'X');
ipif_be <= (others => 'X');
ipif_rnw <= 'X';
when s_generate =>
IPIF_BUSY <= '1';
if not generated then
gen_addr(getint, address);
data := getint;
be := getint;
rnw := getbit;
end if;
ipif_addr <= address;
ipif_data <= conv_std_logic_vector(data, Bus2IP_Data'length);
ipif_rnw <= rnw;
ipif_be <= conv_std_logic_vector(be, Bus2IP_BE'length);
ipif_cs <= '1';
generated := true;
when s_busy =>
IPIF_BUSY <= '1';
ipif_addr <= address;
ipif_data <= conv_std_logic_vector(data, Bus2IP_Data'length);
ipif_rnw <= rnw;
ipif_be <= conv_std_logic_vector(be, Bus2IP_BE'length);
ipif_cs <= not IPIF_DONE;
end case;
end process;
Bus2IP_Addr <= ipif_addr;
Bus2IP_Data <= ipif_data;
Bus2IP_RNW <= ipif_rnw;
Bus2IP_CS <= ipif_cs;
Bus2IP_BE <= ipif_be;
IPIF_READ <= ipif_rnw;
end architecture;
| gpl-2.0 |
6769/VHDL | Lab_2_part1/simulation/qsim/work/@nbit@counter/_primary.vhd | 1 | 290 | library verilog;
use verilog.vl_types.all;
entity NbitCounter is
port(
clear : in vl_logic;
clk : in vl_logic;
enable : in vl_logic;
Q : out vl_logic_vector(15 downto 0)
);
end NbitCounter;
| gpl-2.0 |
zzhou007/161lab | lab02/bin_alu.vhd | 1 | 2436 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
entity bin_alu is
generic(NUMBITS : natural := 32);
Port ( Atemp : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
Btemp : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
A : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
B : in STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
opcode : in STD_LOGIC_VECTOR(3 downto 0);
result : out STD_LOGIC_VECTOR(NUMBITS - 1 downto 0);
carryout : out STD_LOGIC;
overflow : out STD_LOGIC;
zero : out STD_LOGIC);
end bin_alu;
architecture Behavioral of bin_alu is
--temp signal for alu
signal stuff: std_logic_vector(NUMBITS downto 0);
begin
process (A, B, opcode, stuff, Atemp, Btemp)
begin
--UNSIGNED ADD
if opcode = "1000" then
stuff <= std_logic_vector( unsigned('0' & A ) + unsigned( '0' & B));
result <= stuff(NUMBITS-1 downto 0);
--carryout <= '1';
carryout <= stuff(NUMBITS);
overflow <= '0';
if stuff(NUMBITS downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED ADD
elsif opcode = "1100" then
stuff <= std_logic_vector( signed('0' & A) + signed('0' & B) );
result <= stuff(NUMBITS-1 downto 0);
overflow <= '0';
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--UNSIGNED SUB
elsif opcode = "1001" then
stuff <= std_logic_vector( ('0' & unsigned(A) ) + ( '0' & ((not unsigned(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (Atemp < Btemp) then
overflow <= '1';
end if;
if stuff(NUMBITS - 1) = '0' then
carryout <= '1';
else
carryout <= '0';
end if;
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
--SIGNED SUB
elsif opcode = "1101" then
stuff <= std_logic_vector( ('0' & signed(A) ) + ( '0' & ((not signed(B)) + 1)));
result <= stuff(NUMBITS-1 downto 0);
if (A(NUMBITS-1) = '0') and (B(NUMBITS-1) = '1') and (stuff(NUMBITS-2) = '1') then
overflow <= '1';
elsif (A(NUMBITS-1) = '1') and (B(NUMBITS-1) = '0') and (stuff(NUMBITS-2) = '0') then
overflow <= '1';
else
overflow <= '0';
end if;
carryout <= stuff(NUMBITS);
if stuff(NUMBITS - 1 downto 0) = 0 then
zero <= '1';
else
zero <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
6769/VHDL | Lab_2_part1/Segment7Decoder.vhd | 1 | 1397 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; --'A'
when "1011"=> segment7 <="0000011"; --'b'
when "1100"=> segment7 <="0100111"; --'c'
when "1101"=> segment7 <="0100001"; --'d'
when "1110"=> segment7 <="0000110"; --'E'
when "1111"=> segment7 <="0001110"; --'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral; | gpl-2.0 |
6769/VHDL | Lab_1_partB/Bcd2digitAdder.vhd | 1 | 1434 | --------------------------------------------------------
---------------------partB------------------------------
--------------------------------------------------------
entity Bcd2digitAdder is
port (adder1,adder2:in bit_vector(7 downto 0);
result:out bit_vector(7 downto 0);
finalCarry:out bit);
end entity Bcd2digitAdder;
architecture structure of Bcd2digitAdder is
signal mid_carry_adjust:bit;
signal midResult:bit_vector(7 downto 0);
signal mid_carry:bit_vector(1 downto 0);
--include FullAdderl;
component Adder4
port(A,B:in bit_vector (3 downto 0);
cin:in bit ;
S:out bit_vector(3 downto 0);
cout:buffer bit);
end component;
--include adjust part
component adjustAdder4
port(origin:in bit_vector(3 downto 0);
adjusted:out bit_vector(3 downto 0);
carryIn:in bit;
carryAdjusted:out bit);
end component;
begin
-- 4bits FullAdder
FA4_low :Adder4 port map(adder1(3 downto 0),adder2(3 downto 0),'0',
midResult(3 downto 0),mid_carry(0));
FA4_high:Adder4 port map(adder1(7 downto 4),adder2(7 downto 4),mid_carry_adjust,
midResult(7 downto 4),mid_carry(1));
--adjust 4bits
ADJust4_low: adjustAdder4 port map(midResult(3 downto 0),result(3 downto 0),mid_carry(0),mid_carry_adjust);
ADjust4_high:adjustAdder4 port map(midResult(7 downto 4),result(7 downto 4),mid_carry(1),finalCarry);
--output in result(7 downto 0),finalcarry,
end architecture structure; | gpl-2.0 |
6769/VHDL | Lab_5/SingluarUnit/controller/simulation/qsim/work/@controller_vlg_check_tst/_primary.vhd | 1 | 444 | library verilog;
use verilog.vl_types.all;
entity Controller_vlg_check_tst is
port(
Clear : in vl_logic;
Lose : in vl_logic;
Roll : in vl_logic;
Sp : in vl_logic;
State_debug : in vl_logic_vector(1 downto 0);
Win : in vl_logic;
sampler_rx : in vl_logic
);
end Controller_vlg_check_tst;
| gpl-2.0 |
sorgelig/SAMCoupe_MIST | sid/sid_ctrl.vhd | 6 | 1641 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_ctrl is
generic (
g_num_voices : natural := 8 );
port (
clock : in std_logic;
reset : in std_logic;
start_iter : in std_logic;
voice_osc : out unsigned(3 downto 0);
enable_osc : out std_logic );
end sid_ctrl;
architecture gideon of sid_ctrl is
signal voice_cnt : unsigned(3 downto 0);
signal enable : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
voice_cnt <= X"0";
enable <= '0';
elsif start_iter='1' then
voice_cnt <= X"0";
enable <= '1';
elsif voice_cnt = g_num_voices-1 then
voice_cnt <= X"0";
enable <= '0';
elsif enable='1' then
voice_cnt <= voice_cnt + 1;
enable <= '1';
end if;
end if;
end process;
voice_osc <= voice_cnt;
enable_osc <= enable;
end gideon;
| gpl-2.0 |
6769/VHDL | Lab_2_part1/Counter16anDisplay.vhd | 1 | 1184 | entity Counter16anDisplay is
port(clk,enable,clear:in bit;
hex0,hex1,hex2,hex3:out bit_vector(7 downto 0)
);
end entity Counter16anDisplay;
architecture combination of Counter16anDisplay is
component NbitCounter
port(
clear:in bit:='1';
clk,enable:in bit ;
Q:buffer bit_vector(15 downto 0):=( others=>'0') );
--Q:buffer bit_vector(15 downto 0):="1111111111111100");
end component;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
signal midQ:bit_vector(15 downto 0);
begin
hex0(0)<='1';
hex1(0)<='1';
hex2(0)<='1';
hex3(0)<='1';
counter_part:NbitCounter port map(clear,clk,enable,midQ);
displayLED0:segment7Decoder port map(midQ(3 downto 0),hex0 (7 downto 1));
displayLED1:segment7Decoder port map(midQ(7 downto 4),hex1 (7 downto 1));
displayLED2:segment7Decoder port map(midQ(11 downto 8),hex2 (7 downto 1));
displayLED3:segment7Decoder port map(midQ(15 downto 12),hex3(7 downto 1));
end architecture combination; | gpl-2.0 |
sorgelig/SAMCoupe_MIST | sid/my_math_pkg.vhd | 6 | 4097 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_math_pkg is
function sum_limit(i1, i2 : signed) return signed;
function sub_limit(i1, i2 : signed) return signed;
function sum_limit(i1, i2 : unsigned) return unsigned;
function extend(x : signed; len : natural) return signed;
function extend(x : unsigned; len : natural) return unsigned;
function left_align(x : signed; len : natural) return signed;
function left_scale(x : signed; sh : natural) return signed;
-- function shift_right(x : signed; positions: natural) return signed;
end;
package body my_math_pkg is
function sum_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 + i2;
if (i1(i1'left) = i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sub_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 - i2;
if (i1(i1'left) /= i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sum_limit(i1, i2 : unsigned) return unsigned is
variable o : unsigned(i1'length downto 0);
begin
o := ('0' & i1) + i2;
if o(o'left)='1' then
o := (others => '1');
end if;
return o(i1'length-1 downto 0);
end function;
function extend(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
alias a : signed(x'length-1 downto 0) is x;
begin
ret := (others => x(x'left));
ret(a'range) := a;
return ret;
end function extend;
function extend(x : unsigned; len : natural) return unsigned is
variable ret : unsigned(len-1 downto 0);
alias a : unsigned(x'length-1 downto 0) is x;
begin
ret := (others => '0');
ret(a'range) := a;
return ret;
end function extend;
function left_align(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
begin
ret := (others => '0');
ret(len-1 downto len-x'length) := x;
return ret;
end function left_align;
function left_scale(x : signed; sh : natural) return signed is
alias a : signed(x'length-1 downto 0) is x;
variable ret : signed(x'length-(1+sh) downto 0);
variable top : signed(sh downto 0);
begin
if sh=0 then
return x;
end if;
top := a(a'high downto a'high-sh);
if (top = -1) or (top = 0) then -- can shift without getting punished!
ret := a(ret'range);
elsif a(a'high)='1' then -- negative and can't shift, so max neg:
ret := (others => '0');
ret(ret'high) := '1';
else -- positive and can't shift, so max pos
ret := (others => '1');
ret(ret'high) := '0';
end if;
return ret;
end function left_scale;
-- function shift_right(x : signed; positions: natural) return signed is
-- alias a : signed(x'length-1 downto 0) is x;
-- variable ret : signed(x'length-1 downto 0);
-- begin
-- ret := (others => x(x'left));
-- ret(a'left-positions downto 0) := a(a'left downto positions);
-- return ret;
-- end function shift_right;
end;
| gpl-2.0 |
6769/VHDL | Lab_2_part2/cyclic_reg_with_clock.vhd | 1 | 1136 | entity cyclic_reg_with_clock is
port(clk,reset:in bit;
hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7:out bit_vector(7 downto 0)
);
end entity cyclic_reg_with_clock;
architecture combine of cyclic_reg_with_clock is
component clock_second is
port(clk:in bit ;
second:buffer bit);
end component;
component rotate_shift_register
port(clk,reset: in bit;
--problem is that the predefined value seems didn't assigned
hex0:buffer bit_vector(7 downto 0):="10000001"; --O
hex1:buffer bit_vector(7 downto 0):="10001111"; --L
hex2:buffer bit_vector(7 downto 0):="10001111"; --L
hex3:buffer bit_vector(7 downto 0):="00001101"; --E
hex4:buffer bit_vector(7 downto 0):="00010011"; --H
hex5:buffer bit_vector(7 downto 0):="11111111"; --nothing
hex6:buffer bit_vector(7 downto 0):="11111111"; --
hex7:buffer bit_vector(7 downto 0):="11111111" --nothing
);
end component;
signal midline:bit;
begin
clock0:clock_second port map(clk,midline);
reg0:rotate_shift_register port map(midline,reset,hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7);
end architecture combine; | gpl-2.0 |
6769/VHDL | Lab_6/TheFinalCodeVersion/__report_formats.vhd | 1 | 14126 | --------------------------------------------------------------
------------------------------------------------------------
-- Addsub.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Addsub_Unit is
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end entity Addsub_Unit;
architecture Behavior of Addsub_Unit is
begin
process(select_add_sub,a,b)
begin
case select_add_sub is
when '0'=>
result<=a+b;
when '1'=>
result<=a-b;
when others=>
result<=(others=>'Z');
end case;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- Control_unit.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end entity Control_unit;
architecture behavior of Control_unit is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
--InstructionSet
signal IR:std_logic_vector(1 to 9);
signal I,X,Y:std_LOGIC_vector(1 to 3);
signal Xreg,Yreg:std_logic_vector(0 to 7);
begin
Clear<= (not Resetn) or Done;
--InstructionFormat I..X..Y..
process(IRset,Run)
begin
if(Run='1' )then
IR<=IRset;
end if;
end process;
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
--InstructionDecoder to MUX
decX : dec3to8 port map(X, '1', Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, '1', Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)--,Run)
begin
--specify initial values
Done<='0';
--to multiplexer
DINout<='0';
Gout<='0';
Riout<=(others =>'0');
--to register
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub<='Z';
--if(Run='1')then
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Riout<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
DINout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
--end if;
end process;
end architecture behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- dec3to8.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dec3to8 is
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end dec3to8;
architecture Behavior of dec3to8 is
begin
process (W, En)
begin
if En = '1' then
case W is
when "000" => Y <= "10000000";
when "001" => Y <= "01000000";
when "010" => Y <= "00100000";
when "011" => Y <= "00010000";
when "100" => Y <= "00001000";
when "101" => Y <= "00000100";
when "110" => Y <= "00000010";
when "111" => Y <= "00000001";
when others=> null;
end case;
else
Y <= "00000000";
end if;
end process;
end Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- multiplexers.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity multiplexers is
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end entity multiplexers;
architecture choice of multiplexers is
signal mid_choice:std_logic_vector(N+2-1 downto 0);
begin
mid_choice<=control_reg&control_GDi;--0~7|G|Din--
-- out_to_bus<= DataIn when control_GDi(0)='1'
-- else reg_G when control_GDi(1)='1'
-- else reg0 when control_reg(0)='1'
-- else reg1 when control_reg(1)='1'
-- ;--else (others=>'Z');
process(mid_choice,reg0,reg1,reg_G,DataIn)
begin
case mid_choice is
when "1000"=>
out_to_bus<=reg0;
when "0100"=>
out_to_bus<=reg1;
when "0010"=>
out_to_bus<=reg_G;
when others=>
--when "0001"=>
out_to_bus<=DataIn;
--when others=>
end case;
end process;
end architecture choice;
--------------------------------------------------------------
------------------------------------------------------------
-- regn.vhd
------------------------------------------------------------
--------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.All;
Entity regn Is
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
End regn;
Architecture Behavior Of regn Is
Begin
Process (Clock)
Begin
If Clock'EVENT And Clock = '1' Then
If Rin = '1' Then
Q <= R;
End If;
End If;
End Process;
End Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- upcount.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity upcount is
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end upcount;
architecture Behavior of upcount is
signal Count : STD_LOGIC_VECTOR(1 downto 0);
begin
process (Clock)
begin
if (Clock'EVENT and Clock = '1') then
if Clear = '1' then
Count <= "00";
else
Count <= Count + 1;
end if;
end if;
end process;
Q <= Count;
end Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity View is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : out STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end View;
architecture Behavior of View is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
component regn --usual register
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
end component;
component upcount
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component Addsub_Unit
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end component;
component multiplexers
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end component;
component Control_unit
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
signal R0,R1,A,G:regwidth;
---------------------------------
--Control_unit output
---------------------------------
--IR control_unit
signal IRset: std_logic_vector(0 to 8);--instruction length =9 bits
signal IRin: std_logic;
--multiplexer
signal Riout: std_logic_vector(0 to 7);
signal Gout,DINout: std_logic;
--Register Data in
signal Rin: std_logic_vector(0 to 7);
signal Ain,Gin: std_logic;
--ALU control_unit
signal AddSub: std_logic;
--Counter state
signal Tstep_Q: std_logic_vector(1 downto 0);
signal Clear: std_logic;
--singular control signal
--signal Run,Resetn: std_logic;
--signal Done: std_logic;
-------------------------------------
signal ALU_result:std_logic_vector(15 downto 0);
begin
Tstep : upcount port map(Clear, Clock , Tstep_Q);
-- Din, RinControl,Clk,ROut
reg_0 : regn port map(BusWires, Rin(0), Clock, R0);
reg_1 : regn port map(BusWires, Rin(1), Clock, R1);
reg_A : regn port map(BusWires, Ain, Clock, A );
reg_G : regn port map(ALU_result, Gin, Clock, G );
reg_IR: regn generic map(9) port map(DIN(15 downto 7),IRin,Clock,IRset);
ALU_Unit:
Addsub_Unit port map(A, BusWires,AddSub, ALU_result);
--instantiate other registers and the adder/subtracter unit
Multiplexer_Unit:
multiplexers generic map(N=>2,n_multi=>16) port map(DIN,G,R0,R1,Riout(0 to 1) ,Gout&DINout,BusWires);
--define the bus
--Control_unit
--------------------
Control_unit_label:Control_unit port map(
IRset,--instruction length =9 bits
IRin,
--multiplexer
Riout,
Gout,DINout,
--Register Data in
Rin,
Ain,Gin,
--ALU control_unit
AddSub,
--Counter state
Tstep_Q,
Clear,
--singular control signal
Run,Resetn,
Done
);
--------------------
end architecture Behavior;
| gpl-2.0 |
6769/VHDL | Lab_6/TheFinalCodeVersion/regn.vhd | 2 | 411 |
Library ieee;
Use ieee.std_logic_1164.All;
Entity regn Is
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
End regn;
Architecture Behavior Of regn Is
Begin
Process (Clock)
Begin
If Clock'EVENT And Clock = '1' Then
If Rin = '1' Then
Q <= R;
End If;
End If;
End Process;
End Behavior; | gpl-2.0 |
6769/VHDL | Lab_2_part2/simulation/qsim/work/cyclic_reg_with_clock_vlg_vec_tst/_primary.vhd | 1 | 126 | library verilog;
use verilog.vl_types.all;
entity cyclic_reg_with_clock_vlg_vec_tst is
end cyclic_reg_with_clock_vlg_vec_tst;
| gpl-2.0 |
6769/VHDL | Lab_6/TheFinalCodeVersion/View.vhd | 2 | 4554 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity View is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : out STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end View;
architecture Behavior of View is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
component regn --usual register
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
end component;
component upcount
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component Addsub_Unit
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end component;
component multiplexers
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end component;
component Control_unit
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
signal R0,R1,A,G:regwidth;
---------------------------------
--Control_unit output
---------------------------------
--IR control_unit
signal IRset: std_logic_vector(0 to 8);--instruction length =9 bits
signal IRin: std_logic;
--multiplexer
signal Riout: std_logic_vector(0 to 7);
signal Gout,DINout: std_logic;
--Register Data in
signal Rin: std_logic_vector(0 to 7);
signal Ain,Gin: std_logic;
--ALU control_unit
signal AddSub: std_logic;
--Counter state
signal Tstep_Q: std_logic_vector(1 downto 0);
signal Clear: std_logic;
--singular control signal
--signal Run,Resetn: std_logic;
--signal Done: std_logic;
-------------------------------------
signal ALU_result:std_logic_vector(15 downto 0);
begin
Tstep : upcount port map(Clear, Clock , Tstep_Q);
-- Din, RinControl,Clk,ROut
reg_0 : regn port map(BusWires, Rin(0), Clock, R0);
reg_1 : regn port map(BusWires, Rin(1), Clock, R1);
reg_A : regn port map(BusWires, Ain, Clock, A );
reg_G : regn port map(ALU_result, Gin, Clock, G );
reg_IR: regn generic map(9) port map(DIN(15 downto 7),IRin,Clock,IRset);
ALU_Unit:
Addsub_Unit port map(A, BusWires,AddSub, ALU_result);
--instantiate other registers and the adder/subtracter unit
Multiplexer_Unit:
multiplexers generic map(N=>2,n_multi=>16) port map(DIN,G,R0,R1,Riout(0 to 1) ,Gout&DINout,BusWires);
--define the bus
--Control_unit
--------------------
Control_unit_label:Control_unit port map(
IRset,--instruction length =9 bits
IRin,
--multiplexer
Riout,
Gout,DINout,
--Register Data in
Rin,
Ain,Gin,
--ALU control_unit
AddSub,
--Counter state
Tstep_Q,
Clear,
--singular control signal
Run,Resetn,
Done
);
--------------------
end architecture Behavior; | gpl-2.0 |
6769/VHDL | Lab_1/allofcode.vhd | 1 | 9794 | --partA
--file for first VHDL Documents.!!!
entity NumberAnDisplay is
port(
-- Input ports
V : in bit_vector(3 downto 0);
-- Output ports
z : buffer bit;
M : buffer bit_vector(3 downto 0);
-- 7 Segment Display
segment7:out bit_vector(6 downto 0);
--segment7:out bit_vector();
segment7_point:out bit :='1';
segment7_1:out bit_vector(6 downto 0);
segment7_1_point:out bit :='1'
);
end NumberAnDisplay;
architecture CircuitA_Mux of NumberAnDisplay is
signal midM : bit_vector(2 downto 0);
--assignment about <:='0000'> correspond?
begin
z<= V(3)and (V(2)or V(1));
--circuitA part
midM(0)<=V(0);
midM(1)<=not V(1);
midM(2)<=V(2)and V(1);
--Multiplexer part
M(3)<=(not z) and V(3) ;
M(2)<=((not z) and V(2)) or (z and midM(2));
M(1)<=((not z) and V(1)) or (z and midM(1));
M(0)<=((not z) and V(0)) or (z and midM(0));
--7 Segment Display
process (M)
BEGIN
case M is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
process (z)
BEGIN
case z is
when '0'=> segment7_1 <="1000000"; -- '0'
when '1'=> segment7_1 <="1111001"; -- '1'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end CircuitA_Mux;
--------------------------------------------------------
-- partB --
--------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--finally synthesis all component;
entity Input_Display is
port(adder1,adder2:in bit_vector(7 downto 0);
adder1_hex_display,adder2_hex_display:out bit_vector(15 downto 0);
sum:out bit_vector(23 downto 0)
);
end entity Input_Display;
architecture combination of Input_Display is
--bcd4-adder;
component Bcd2digitAdder
port (adder1,adder2:in bit_vector(7 downto 0);
result:out bit_vector(7 downto 0);
finalCarry:out bit);
end component;
--7segment decoder;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
signal result_in_bcd:bit_vector(7 downto 0);
signal HighBit:bit;
signal tower:bit_vector(3 downto 0):="0000";
signal point_value:bit:='1';
begin
tower(0)<= HighBit;
Bcdadder:Bcd2digitAdder port map(adder1,adder2,result_in_bcd,HighBit);
--display Adder1;
--lower 4
Dis7Segment_adder1_lower:Segment7Decoder port map(adder1(3 downto 0),adder1_hex_display(7 downto 1));
--higher 4
Dis7Segment_adder1_higer:Segment7Decoder port map(adder1(7 downto 4),adder1_hex_display(15 downto 9));
--point in bit 8,0
--display Adder2 ;
--lower 4
Dis7Segment_adder2_lower:Segment7Decoder port map(adder2(3 downto 0),adder2_hex_display(7 downto 1));
--higher 4
Dis7Segment_adder2_higer:Segment7Decoder port map(adder2(7 downto 4),adder2_hex_display(15 downto 9));
--display result_in_bcd
Dis7Segment_result_lower:Segment7Decoder port map(result_in_bcd(3 downto 0),sum( 7 downto 1));
Dis7Segment_result_higer:Segment7Decoder port map(result_in_bcd(7 downto 4),sum(15 downto 9));
Dis7Segment_result_tower:Segment7Decoder port map(tower ,sum(23 downto 17));
--point in bit 16,8,0;
--reset All of Point in segment ;
adder1_hex_display(0)<=point_value;
adder1_hex_display(8)<=point_value;
adder2_hex_display(0)<=point_value;
adder2_hex_display(8)<=point_value;
sum(0)<=point_value;
sum(8)<=point_value;
sum(16)<=point_value;
end architecture combination;
entity Bcd2digitAdder is
port (adder1,adder2:in bit_vector(7 downto 0);
result:out bit_vector(7 downto 0);
finalCarry:out bit);
end entity Bcd2digitAdder;
architecture structure of Bcd2digitAdder is
signal mid_carry_adjust:bit;
signal midResult:bit_vector(7 downto 0);
signal mid_carry:bit_vector(1 downto 0);
--include FullAdderl;
component Adder4
port(A,B:in bit_vector (3 downto 0);
cin:in bit ;
S:out bit_vector(3 downto 0);
cout:buffer bit);
end component;
--include adjust part
component adjustAdder4
port(origin:in bit_vector(3 downto 0);
adjusted:out bit_vector(3 downto 0);
carryIn:in bit;
carryAdjusted:out bit);
end component;
begin
-- 4bits FullAdder
FA4_low :Adder4 port map(adder1(3 downto 0),adder2(3 downto 0),'0',
midResult(3 downto 0),mid_carry(0));
FA4_high:Adder4 port map(adder1(7 downto 4),adder2(7 downto 4),mid_carry_adjust,
midResult(7 downto 4),mid_carry(1));
--adjust 4bits
ADJust4_low: adjustAdder4 port map(midResult(3 downto 0),result(3 downto 0),mid_carry(0),mid_carry_adjust);
ADjust4_high:adjustAdder4 port map(midResult(7 downto 4),result(7 downto 4),mid_carry(1),finalCarry);
--output in result(7 downto 0),finalcarry,
end architecture structure;
entity adjustAdder4 is
port(origin:in bit_vector(3 downto 0);
adjusted:out bit_vector(3 downto 0);
carryIn:in bit;
carryAdjusted:out bit);
end adjustAdder4;
architecture conversion of adjustAdder4 is
component Adder4
port(A,B:in bit_vector (3 downto 0);
cin:in bit ;
S:out bit_vector(3 downto 0);
cout:buffer bit);
end component;
signal z:bit:='0';
signal never_use:bit;
signal S_mid:bit_vector(3 downto 0);
begin
z<=carryIn or (origin(3)and (origin(2) or origin(1)) );
carryAdjusted<=z;
FA4:Adder4 port map (origin,"0110",'0',S_mid,never_use);
adjusted<=origin when z='0'
else s_mid ;
end conversion;
--another function is adjust BCD ,like the instruct DA in 8051;
--A pure 4bits fullAdder;
entity Adder4 is
port(A,B:in bit_vector (3 downto 0);
cin:in bit ;
S:out bit_vector(3 downto 0);
cout:buffer bit);
end Adder4;
architecture bit4FullAdder of Adder4 is
component FullAdder
port(a,b,cin:in bit ;
s,cout:out bit );
end component;
signal C:bit_vector(3 downto 1);--internal carry bit ;
begin
FA0:FullAdder port map(A(0),B(0),cin ,S(0),C(1));
FA1:FullAdder port map(A(1),B(1),C(1),S(1),C(2));
FA2:FullAdder port map(A(2),B(2),C(2),S(2),C(3));
FA3:FullAdder port map(A(3),B(3),C(3),S(3),cout);
end bit4FullAdder;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral;
--------------------------------------------------------
--- partC ---
--------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--finally synthesis all component;
entity Input_Display is
port(adder1,adder2:in std_logic_vector(7 downto 0);
adder1_hex_display,adder2_hex_display:out std_logic_vector(15 downto 0);
sum: out std_logic_vector(23 downto 0)
);
end entity Input_Display;
architecture combination of Input_Display is
--signal A0,B0,T0,Z0,A1,B1,T1,Z1,S0,S1,S2:std_logic_vector(3 downto 0):="0000";
signal A0,B0,T0,Z0,A1,B1,T1,Z1,S0,S1,S2:std_logic_vector(3 downto 0);
signal c1,c2:std_logic;
component Segment7Decoder
port (bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
begin
A0<=adder1(3 downto 0);B0<=adder2(3 downto 0);
A1<=adder1(7 downto 4);B1<=adder2(7 downto 4);
process(adder1,adder2)
begin
T0<=A0+B0;
if T0>9 then Z0<="1010";c1<='1';
else Z0<="0000";c1<='0';
end if;
S0<=T0-Z0;
T1<=A1+B1+c1;
if(T1>9) then Z1<="1010";c2<='1';
else Z1<="0000";c2<='0';
end if;
S1<=T1-Z1;
S2<="000"&c2;
end process;
--adder1
Display_adder1_lower:Segment7Decoder port map(A0,adder1_hex_display(7 downto 1));
Display_adder1_higer:Segment7Decoder port map(A1,adder1_hex_display(15 downto 9));
--adder2
Display_adder2_lower:Segment7Decoder port map(B0,adder2_hex_display(7 downto 1));
Display_adder2_higer:Segment7Decoder port map(B1,adder2_hex_display(15 downto 9));
--result
Res_lower:Segment7Decoder port map(S0,sum(7 downto 1));
Res_higer:Segment7Decoder port map(S1,sum(15 downto 9));
Res_tower:Segment7Decoder port map(S2,sum(23 downto 17));
--point
sum(0)<='1';
sum(8)<='1';
sum(16)<='1';
adder1_hex_display(0)<='1';
adder1_hex_display(8)<='1';
adder2_hex_display(0)<='1';
adder2_hex_display(8)<='1';
end architecture combination;
| gpl-2.0 |
6769/VHDL | Lab_3/Part2/simulation/qsim/work/@view_input_vlg_check_tst/_primary.vhd | 1 | 272 | library verilog;
use verilog.vl_types.all;
entity View_input_vlg_check_tst is
port(
state8_0 : in vl_logic_vector(8 downto 0);
z : in vl_logic;
sampler_rx : in vl_logic
);
end View_input_vlg_check_tst;
| gpl-2.0 |
b4n/ctags | Test/test.vhd | 91 | 192381 | package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end paramterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
| gpl-2.0 |
hwstar/PCIRADIO | io.vhd | 1 | 13201 | --
-- io.vhd: VHDL module for Zapata Telephony PCI Radio Card, Rev. A
-- Author: Stephen A. Rodgers
--
-- Copyright (c) 2004,2005 Stephen A. Rodgers
--
-- Steve Rodgers <[email protected]>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which it runs is free, and all are
-- distributed under the terms of the GNU General Public License.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity io is
port
(
arn : in std_logic;
clk : in std_logic;
wrn : in std_logic;
rd : in std_logic;
sel_uio : in std_logic;
sel_testptt : in std_logic;
sel_ctrl1 : in std_logic;
sel_ctrl2 : in std_logic;
sel_leds : in std_logic;
sel_irqmask : in std_logic;
sel_uarttx : in std_logic;
rbsclk : in std_logic;
rbsdata : in std_logic;
irq_mx828 : in std_logic;
ledpwm : in std_logic;
rbs_busy : in std_logic;
busy_mx828 : in std_logic;
mxaccess : in std_logic;
uioinlsb : in std_logic_vector(3 downto 0);
cor : in std_logic_vector(3 downto 0);
wdb : in std_logic_vector(7 downto 0);
tjirq : out std_logic;
led0 : out std_logic_vector(1 downto 0);
led1 : out std_logic_vector(1 downto 0);
led2 : out std_logic_vector(1 downto 0);
led3 : out std_logic_vector(1 downto 0);
uioout : out std_logic_vector(7 downto 0);
testpttout : out std_logic_vector(7 downto 0);
ctrlout1 : out std_logic_vector(7 downto 0);
ctrlout2 : out std_logic_vector(7 downto 0);
statusreg : out std_logic_vector(7 downto 0);
corbits : out std_logic_vector(7 downto 0);
irqmaskbits : out std_logic_vector(7 downto 0);
uart_rxdata : out std_logic_vector(7 downto 0)
);
end io;
architecture rtl of io is
signal irqsum : std_logic;
signal rxd : std_logic;
signal txd : std_logic;
signal ovrrun : std_logic;
signal dirty : std_logic;
signal dav : std_logic;
signal txgo : std_logic;
signal txdone : std_logic;
signal txbusy : std_logic;
signal bce9600 : std_logic;
signal txwdtrip: std_logic;
signal rxba : std_logic;
signal leds2 : std_logic_vector(1 downto 0);
signal txgosync: std_logic_vector(2 downto 0);
signal rdsuart : std_logic_vector(2 downto 0);
signal wdptts : std_logic_vector(3 downto 0);
signal irqmbits: std_logic_vector(3 downto 0);
signal plsdone : std_logic_vector(3 downto 0);
signal rbsdone : std_logic_vector(3 downto 0);
signal leds4 : std_logic_vector(3 downto 0);
signal davshift: std_logic_vector(4 downto 0);
signal leds6 : std_logic_vector(5 downto 0);
signal uarttx : std_logic_vector(7 downto 0);
signal ledport : std_logic_vector(7 downto 0);
signal ledctrl : std_logic_vector(7 downto 0);
signal ledsync : std_logic_vector(7 downto 0);
signal uiobits : std_logic_vector(7 downto 0);
signal ctrl2 : std_logic_vector(7 downto 0);
component tinyuart
port
(
arn : in std_logic;
clk : in std_logic;
txgo : in std_logic;
rxrd : in std_logic;
rxd : in std_logic;
txdata : in std_logic_vector(7 downto 0);
ovrrun : out std_logic;
dirty : out std_logic;
dav : out std_logic;
txdone : out std_logic;
txd : out std_logic;
bce9600 : out std_logic;
rxdata : out std_logic_vector(7 downto 0)
);
end component;
component txwdog
port
(
arn : in std_logic;
clk : in std_logic;
mxaccess : in std_logic;
bce9600 : in std_logic;
pttin : in std_logic_vector(3 downto 0);
txwdtrip : out std_logic;
pttout : out std_logic_vector(3 downto 0)
);
end component;
begin
mtinyuart : tinyuart
port map
(
arn => arn,
clk => clk,
txgo => txgo,
rxrd => rdsuart(2),
rxd => rxd,
txdata => uarttx,
ovrrun => ovrrun,
dirty => dirty,
dav => dav,
txdone => txdone,
txd => txd,
bce9600 => bce9600,
rxdata => uart_rxdata
);
mtxwdog : txwdog
port map
(
arn => arn,
clk => clk,
mxaccess => mxaccess,
bce9600 => bce9600,
txwdtrip => txwdtrip,
pttin => wdptts,
pttout => testpttout(3 downto 0)
);
uiop : process(arn, wrn)
begin
if(arn = '0') then
uiobits <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_uio = '1') then
uiobits <= wdb;
end if;
end if;
end process uiop;
testpttp : process(arn, wrn)
begin
if(arn = '0') then
testpttout(7 downto 4) <= "0000";
wdptts <= "0000";
elsif(wrn'event) and (wrn = '1') then
if(sel_testptt = '1') then
testpttout(7 downto 4) <= wdb(7 downto 4);
wdptts <= wdb(3 downto 0);
end if;
end if;
end process testpttp;
ledp : process(arn, wrn)
begin
if(arn = '0') then
ledport <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_leds = '1') then
ledport <= wdb;
end if;
end if;
end process ledp;
ctrlp1 : process(arn, wrn)
begin
if(arn = '0') then
ctrlout1 <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_ctrl1 = '1') then
ctrlout1 <= wdb;
end if;
end if;
end process ctrlp1;
ctrlp2 : process(arn, wrn)
begin
if(arn = '0') then
ctrl2 <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_ctrl2 = '1') then
ctrl2 <= wdb;
end if;
end if;
end process ctrlp2;
irqmrp : process(arn, wrn)
begin
if(arn = '0') then
irqmbits <= "0000";
elsif(wrn'event) and (wrn = '1') then
if(sel_irqmask = '1') then
irqmbits(2 downto 0) <= not wdb(2 downto 0);
irqmbits(3) <= not wdb(7);
end if;
end if;
end process irqmrp;
-- prevent glitches on tjirq
irqsync : process(arn, clk)
begin
if(arn = '0') then
tjirq <= '0';
elsif(clk'event) and (clk = '1') then
tjirq <= irqsum;
end if;
end process irqsync;
-- Generate UART unload strobe
rdsynca : process(arn, rdsuart, rd)
begin
if(arn = '0') or (rdsuart(2) = '1') then
rdsuart(0) <= '0';
elsif(rd'event) and (rd = '0') then
if(sel_uarttx = '1') then -- receive register read
rdsuart(0) <= '1';
end if;
end if;
end process rdsynca;
rdsyncb : process(arn, clk, rdsuart)
begin
if(arn = '0') then
rdsuart(2 downto 1) <= "00";
elsif(clk'event) and (clk = '1') then
rdsuart(2) <= rdsuart(1);
rdsuart(1) <= rdsuart(0);
end if;
end process rdsyncb;
-- delay dav by 5 clocks
davshftp : process(arn, clk)
begin
if(arn = '0') then
davshift <= "00000";
elsif(clk'event) and (clk = '1') then
davshift <= davshift(3 downto 0) & dav;
end if;
end process davshftp;
-- rxba latch
rxbafm : process(arn, rd, davshift(4))
begin
if(arn = '0') then
rxba <= '0';
elsif(davshift(4) = '1') then
rxba <= '1'; -- byte available asynchronously sets
elsif(rd'event) and (rd = '0') then
if(sel_uarttx = '1') then -- receive register read
rxba <= '0'; -- byte available clears on rising edge of rd.
end if;
end if;
end process rxbafm;
-- start to generate a load pulse from a tx write
puarttx1 : process(arn, txgosync(2), wrn)
begin
if(arn = '0') then
txgosync(0) <= '0';
elsif(txgosync(2) = '1') then
txgosync(0) <= '0';
elsif(wrn'event) and (wrn = '1') then
if(sel_uarttx = '1') then
txgosync(0) <= '1';
end if;
end if;
end process puarttx1;
-- set or clear txbusy
puarttx2 : process(arn, wrn, txdone)
begin
if(arn = '0') or (txdone = '1') then
txbusy <= '0';
elsif(wrn'event) and (wrn = '1') then
if(sel_uarttx = '1') then
txbusy <= '1';
end if;
end if;
end process puarttx2;
-- save byte to be transmitted
puarttx3 : process(arn, wrn)
begin
if(arn = '0') then
uarttx <= "00000000";
elsif(wrn'event) and (wrn = '1') then
if(sel_uarttx = '1') then
uarttx <= wdb;
end if;
end if;
end process puarttx3;
-- sequence the load pulse for the tx write
puarttx4 : process(arn, clk)
begin
if(arn = '0') then
txgosync(2 downto 1) <= "00";
elsif(clk'event) and (clk = '1') then
txgosync(1) <= txgosync(0);
txgosync(2) <= txgosync(1);
end if;
end process puarttx4;
-- latch the transition of pl serializer busy from high to low
mxdnp : process(arn, clk)
begin
if(arn = '0') then
plsdone(2 downto 0) <= "000";
elsif(clk'event) and (clk = '1') then
plsdone(1) <= plsdone(0);
plsdone(0) <= busy_mx828;
if( irqmbits(0) = '0') then
plsdone(2) <= '0';
elsif(plsdone(3) = '1') then
plsdone(2) <= '1';
end if;
end if;
end process mxdnp;
-- latch the transition of remote serializer busy from high to low
rbdnp : process(arn, clk)
begin
if(arn = '0') then
rbsdone(2 downto 0) <= "000";
elsif(clk'event) and (clk = '1') then
rbsdone(1) <= rbsdone(0);
rbsdone(0) <= rbs_busy;
if(irqmbits(1) = '0') then
rbsdone(2) <= '0';
elsif(rbsdone(3) = '1') then
rbsdone(2) <= '1';
end if;
end if;
end process rbdnp;
-- handle status led modulation
ledmod : process(ledpwm, ledport)
begin
case ledport(1 downto 0) is
when "00" =>
ledctrl(1 downto 0) <= "00";
when "01" =>
ledctrl(1 downto 0) <= "01";
when "10" =>
ledctrl(1 downto 0) <= "10";
when "11" =>
ledctrl(0) <= ledpwm;
ledctrl(1) <= not ledpwm;
when others =>
ledctrl(1 downto 0) <= "00";
end case;
case ledport(3 downto 2) is
when "00" =>
ledctrl(3 downto 2) <= "00";
when "01" =>
ledctrl(3 downto 2) <= "01";
when "10" =>
ledctrl(3 downto 2) <= "10";
when "11" =>
ledctrl(2) <= ledpwm;
ledctrl(3) <= not ledpwm;
when others =>
ledctrl(3 downto 2) <= "00";
end case;
case ledport(5 downto 4) is
when "00" =>
ledctrl(5 downto 4) <= "00";
when "01" =>
ledctrl(5 downto 4) <= "01";
when "10" =>
ledctrl(5 downto 4) <= "10";
when "11" =>
ledctrl(4) <= ledpwm;
ledctrl(5) <= not ledpwm;
when others =>
ledctrl(5 downto 4) <= "00";
end case;
case ledport(7 downto 6) is
when "00" =>
ledctrl(7 downto 6) <= "00";
when "01" =>
ledctrl(7 downto 6) <= "01";
when "10" =>
ledctrl(7 downto 6) <= "10";
when "11" =>
ledctrl(6) <= ledpwm;
ledctrl(7) <= not ledpwm;
when others =>
ledctrl(7 downto 6) <= "00";
end case;
end process ledmod;
-- skew LED control signals to meet simultaneous switching limitations.
ledskew : process(arn, clk)
begin
if(arn = '0') then
ledsync <= "00000000";
leds6 <= "000000";
leds4 <= "0000";
leds2 <= "00";
elsif(clk'event) and (clk = '1') then
ledsync <= ledctrl;
leds6 <= ledsync(5 downto 0);
leds4 <= leds6(3 downto 0);
leds2 <= leds4(1 downto 0);
end if;
end process ledskew;
-- map outbut modes to correct uioa/b bit pairs
--
outselp : process(ctrl2, uiobits, rbsdata, rbsclk, txd, uioinlsb)
begin
if(ctrl2(7 downto 6) = "01") then -- select RBS on a port.
rxd <= '1';
case ctrl2(5 downto 4) is
when "00" =>
uioout <= uiobits(7 downto 5) & rbsdata & uiobits(3 downto 1) & rbsclk;
when "01" =>
uioout <= uiobits(7 downto 6) & rbsdata & uiobits(4 downto 2) & rbsclk & uiobits(0);
when "10" =>
uioout <= uiobits(7) & rbsdata & uiobits(5 downto 3) & rbsclk & uiobits(1 downto 0);
when "11" =>
uioout <= rbsdata & uiobits(6 downto 4) & rbsclk & uiobits(2 downto 0);
when others =>
uioout <= "00000000";
end case;
elsif(ctrl2(7 downto 6) = "10") then -- select UART on a port
case ctrl2(5 downto 4) is
when "00" =>
rxd <= uioinlsb(0);
uioout <= uiobits(7 downto 5) & txd & uiobits(3 downto 1) & '1';
when "01" =>
rxd <= uioinlsb(1);
uioout <= uiobits(7 downto 6) & txd & uiobits(4 downto 2) & '1' & uiobits(0);
when "10" =>
rxd <= uioinlsb(2);
uioout <= uiobits(7) & txd & uiobits(5 downto 3) & '1' & uiobits(1 downto 0);
when "11" =>
rxd <= uioinlsb(3);
uioout <= txd & uiobits(6 downto 4) & '1' & uiobits(2 downto 0);
when others =>
rxd <= '1';
uioout <= "00000000";
end case;
else
rxd <= '1';
uioout <= uiobits;
end if;
end process outselp;
--
-- Concurrent statements
--
led0 <= leds2;
led1 <= leds4(3 downto 2);
led2 <= leds6(5 downto 4);
led3 <= ledsync(7 downto 6);
ctrlout2 <= ctrl2;
plsdone(3) <= '1' when plsdone(0) = '0' and plsdone(1) = '1' else '0';
rbsdone(3) <= '1' when rbsdone(0) = '0' and rbsdone(1) = '1' else '0';
irqsum <= '1' when irqmbits(3) = '1' and ((irqmbits(2) = '1' and irq_mx828 = '1') or
(irqmbits(1) = '1' and rbsdone(2) = '1') or
(irqmbits(0) = '1' and plsdone(2) = '1')) else '0';
-- assemble general status register bits
statusreg <= irqsum & irq_mx828 & rbsdone(2) & plsdone(2) & '0' & txwdtrip & rbs_busy & busy_mx828;
-- assemble cbits for uart status/cor register
corbits <= txbusy & ovrrun & dirty & rxba & cor(3 downto 0);
-- assemble irqmaskbits
irqmaskbits <= not irqmbits(3) & "0000" & not irqmbits(2 downto 0);
txgo <= txgosync(1) and not txgosync(2);
end rtl;
| gpl-2.0 |
brandonpollack23/VHDL_pong | turnin/col_addr_logic.vhd | 2 | 1445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vga_lib.all;
entity col_addr_logic is
port
(
Hcount : in std_logic_vector(COUNT_WIDTH-1 downto 0);
position_select : in std_logic_vector(2 downto 0);
col : out std_logic_vector(5 downto 0);
image_enable : out std_logic
);
end col_addr_logic;
architecture bhv of col_addr_logic is
signal X_start,X_end : integer;
signal col_u : unsigned(COUNT_WIDTH-1 downto 0);
begin
process(position_select) --process to get Y_start and Y_end
begin
if(position_select = "000") then
X_start <= CENTERED_X_START;
X_end <= CENTERED_X_END;
elsif(position_select = "001") then
X_start <= TOP_LEFT_X_START;
X_end <= TOP_LEFT_X_END;
elsif(position_select = "010") then
X_start <= TOP_RIGHT_X_START;
X_end <= TOP_RIGHT_X_END;
elsif(position_select = "011") then
X_start <= BOTTOM_LEFT_X_START;
X_end <= BOTTOM_LEFT_X_END;
elsif(position_select = "100") then
X_start <= BOTTOM_RIGHT_X_START;
X_end <= BOTTOM_RIGHT_X_END;
else
X_start <= CENTERED_X_START;
X_end <= CenTERED_X_END;
end if;
end process;
process(Hcount,X_start,position_select) --process to output image_enable
begin
if(unsigned(Hcount) > X_start and unsigned(Hcount) <= X_end) then
image_enable <= '1';
else
image_enable <= '0';
end if;
end process;
col_u <= (unsigned(Hcount) - X_start)/2;
col <= std_logic_vector(col_u(5 downto 0));
end bhv; | gpl-2.0 |
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