repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1036.vhd
|
4
|
1665
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1036.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p02n01i01036ent IS
END c06s04b00x00p02n01i01036ent;
ARCHITECTURE c06s04b00x00p02n01i01036arch OF c06s04b00x00p02n01i01036ent IS
BEGIN
TESTING: PROCESS
type T2 is array (0 to 31) of BIT;
variable V1 : T2 ;
BEGIN
V1(2 := '1' ; -- Failure_here
assert FALSE
report "***FAILED TEST: c06s04b00x00p02n01i01036 - Missing parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01036arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2826.vhd
|
4
|
1617
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2826.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity PROCEDURE is
end PROCEDURE;
ENTITY c13s09b00x00p99n01i02826ent IS
END c13s09b00x00p99n01i02826ent;
ARCHITECTURE c13s09b00x00p99n01i02826arch OF c13s09b00x00p99n01i02826ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02826 - Reserved word PROCEDURE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02826arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd
|
4
|
3153
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc663.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:56 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:25 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:35 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00663ent IS
END c03s04b01x00p01n01i00663ent;
ARCHITECTURE c03s04b01x00p01n01i00663arch OF c03s04b01x00p01n01i00663ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_range is positive_vector(hi_to_low_range);
constant C1 : positive_vector_range := (others => 3);
type positive_vector_range_file is file of positive_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : positive_vector_range_file open read_mode is "iofile.03";
variable v : positive_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00663"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00663 - File reading of positive_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00663arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc132.vhd
|
4
|
1979
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc132.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p04n01i00132ent IS
port (
A1 : in Bit;
A2 : inout Bit;
A3 : linkage Bit;
A4 : out Bit;
A5 : Buffer Bit
) ;
END c04s03b02x02p04n01i00132ent;
ARCHITECTURE c04s03b02x02p04n01i00132arch OF c04s03b02x02p04n01i00132ent IS
component Local
port (
C1 : in Bit;
C2 : inout Bit;
C3 : linkage Bit;
C4 : out Bit;
C5 : Buffer Bit
);
end component;
BEGIN
CLSI : Local port map
(open => A1, open => A2, open => A3, open => A4, open => A5);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x02p04n01i00132 - Open is not a valid formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p04n01i00132arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc389.vhd
|
4
|
1642
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc389.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p04n03i00389ent IS
END c03s02b01x01p04n03i00389ent;
ARCHITECTURE c03s02b01x01p04n03i00389arch OF c03s02b01x01p04n03i00389ent IS
type M1 is array (0 to 1, 0 to 2) of bit;
BEGIN
TESTING: PROCESS
variable M2 : M1 := (('1','0'),('1','0','1'));
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p04n03i00389 - Different index ranges"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p04n03i00389arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/perf02-long/quant26bt_neg.vhd
|
3
|
2202
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity quant26bt_neg is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0)
);
end quant26bt_neg;
architecture augh of quant26bt_neg is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := ("00000000000000000000000000111111", "00000000000000000000000000111110", "00000000000000000000000000011111", "00000000000000000000000000011110", "00000000000000000000000000011101", "00000000000000000000000000011100", "00000000000000000000000000011011", "00000000000000000000000000011010", "00000000000000000000000000011001", "00000000000000000000000000011000", "00000000000000000000000000010111", "00000000000000000000000000010110", "00000000000000000000000000010101", "00000000000000000000000000010100", "00000000000000000000000000010011", "00000000000000000000000000010010", "00000000000000000000000000010001", "00000000000000000000000000010000", "00000000000000000000000000001111", "00000000000000000000000000001110", "00000000000000000000000000001101", "00000000000000000000000000001100", "00000000000000000000000000001011", "00000000000000000000000000001010", "00000000000000000000000000001001", "00000000000000000000000000001000", "00000000000000000000000000000111", "00000000000000000000000000000110", "00000000000000000000000000000101", "00000000000000000000000000000100", "00000000000000000000000000000100", "00000000000000000000000000000000");
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- The component is a ROM.
-- There is no Write side.
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd
|
4
|
1840
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_07_02 is
end entity ch_07_02;
----------------------------------------------------------------
architecture test of ch_07_02 is
constant val1 : integer := 1;
procedure p ( signal s1, s2 : in bit; val1 : in integer ) is
begin
null;
end procedure p;
begin
block_07_3_a : block is
signal s1, s2 : bit;
begin
-- code from book:
call_proc : p ( s1, s2, val1 );
-- end of code from book
end block block_07_3_a;
----------------
block_07_3_b : block is
signal s1, s2 : bit;
begin
-- code from book:
call_proc : process is
begin
p ( s1, s2, val1 );
wait on s1, s2;
end process call_proc;
-- end of code from book
end block block_07_3_b;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd
|
4
|
1789
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process is
type natural_ptr is access natural;
-- code from book:
variable count1, count2 : natural_ptr;
-- end of code from book
begin
-- code from book:
count1 := new natural'(5);
count2 := new natural'(10);
count2 := count1;
count1.all := 20;
-- end of code from book
assert
-- code from book:
count1 = count2
-- end of code from book
;
-- code from book:
count1 := new natural'(30);
count2 := new natural'(30);
-- end of code from book
assert count1 = count2;
assert
-- code from book:
count1.all = count2.all
-- end of code from book
;
-- code from book:
if count1 /= null then
count1.all := count1.all + 1;
end if;
-- end of code from book
wait;
end process;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug017/call2.vhdl
|
2
|
278
|
entity call2 is
end;
architecture behav of call2 is
procedure p (n : natural) is
begin
for i in 1 to n loop
report "hello";
wait for 1 ns;
end loop;
end p;
begin
process
begin
p (5);
report "SUCCESS";
wait;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug23165/mwe_working/counter.vhd
|
6
|
598
|
-- counter
-- clk: clock input
-- en: enable input
-- rst: reset input
-- dir: direction pin (1 = up, 0 = down)
-- q: output
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic (
width : positive := 16
);
port (
clk : in std_logic;
q : out std_logic_vector(width-1 downto 0)
);
end counter;
architecture behav of counter is
signal cnt : unsigned(width-1 downto 0) := to_unsigned(0, width);
begin
process
begin
wait until rising_edge(clk);
cnt <= cnt + to_unsigned(1, cnt'length);
end process;
q <= std_logic_vector(cnt);
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2809.vhd
|
4
|
1611
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2809.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity LIBRARY is
end LIBRARY;
ENTITY c13s09b00x00p99n01i02809ent IS
END c13s09b00x00p99n01i02809ent;
ARCHITECTURE c13s09b00x00p99n01i02809arch OF c13s09b00x00p99n01i02809ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02809 - Reserved word LIBRARY can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02809arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/forgen01/forgen01.vhdl
|
1
|
292
|
library ieee;
use ieee.std_logic_1164.all;
entity forgen01 is
port (a : out std_logic_vector (7 downto 0));
end;
architecture behav of forgen01 is
constant c : std_logic_vector (7 downto 0) := x"a1";
begin
gen: for i in a'range generate
a (i) <= c (i);
end generate;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue50/vector.d/cmp_156.vhd
|
2
|
376
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_156 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_156;
architecture augh of cmp_156 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd
|
4
|
1739
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book
entity reg is
generic ( width : positive );
port ( d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1);
-- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity reg;
-- end code from book
architecture test of reg is
begin
q <= d;
end architecture test;
entity inline_07 is
end entity inline_07;
----------------------------------------------------------------
architecture test of inline_07 is
constant bus_size : positive := 16;
-- code from book
signal in_data, out_data : bit_vector(0 to bus_size - 1);
-- . . .
-- end code from book
begin
-- code from book
ok_reg : entity work.reg
generic map ( width => bus_size )
port map ( d => in_data, q => out_data, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- end code from book
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/resolved-integer-type.vhdl
|
4
|
830
|
entity test is
end test;
architecture only of test is
type integer_array is array ( natural range <> ) of integer;
function return_biggest ( inputs : integer_array )
return integer is
variable retval : integer := integer'left;
begin
for i in inputs'range loop
if inputs(i) > retval then
retval := inputs(i);
end if;
end loop; -- i
return retval;
end return_biggest;
subtype biggest_wins is return_biggest integer;
signal common : biggest_wins;
begin -- only
p1 : process
begin
common <= 1 after 1 ns;
wait;
end process;
p2 : process
begin
common <= 1 after 1 ns;
wait;
end process;
test: process
begin
wait for 2 ns;
assert common = 1 report "TEST FAILED" severity failure;
wait;
end process;
end only;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/iassoc01/tb_iassoc03.vhdl
|
1
|
472
|
entity tb_iassoc03 is
end tb_iassoc03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc03 is
signal a : natural;
signal b : natural;
signal res : natural;
begin
dut: entity work.iassoc03
port map (a, b, res);
process
begin
a <= 1;
b <= 5;
wait for 1 ns;
assert res = 6 severity failure;
a <= 197;
b <= 203;
wait for 1 ns;
assert res = 400 severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
libraries/ieee/math_complex-body.vhdl
|
3
|
52648
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_COMPLEX package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common COMPLEX
-- : constants and common COMPLEX mathematical functions and
-- : operators.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end function "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end function "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end function CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end function GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end function COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end function POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end function "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end function "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end function ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end function ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end function "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end function "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end function CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end function CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end function SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end function SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end function EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end function EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end function LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end function LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end function LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end function LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end function SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end function COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end function SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end function COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end function "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end function "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end function "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end function "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end function "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end function "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end function "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end function "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end function "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end function "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
constant TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end function "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end function "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end function "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end function "/";
end package body MATH_COMPLEX;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug18659/crash.vhd
|
3
|
557
|
entity crash is
end entity crash;
library ieee;
use ieee.std_logic_1164.all;
architecture test of crash is
type t_mem2D is array
(natural range <>, -- Address, specifies one word
natural range <> -- Bit positions within a word
)
of std_logic;
begin -- architecture test
process is
variable var_array : t_mem2D(0 to 5, 7 downto 0);
begin -- process
assert var_array = t_mem2D'(X"DEAD", X"BEEF") report "var array error" severity error;
wait;
end process;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd
|
4
|
2000
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc16.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p06n03i00016ent IS
END c04s02b00x00p06n03i00016ent;
ARCHITECTURE c04s02b00x00p06n03i00016arch OF c04s02b00x00p06n03i00016ent IS
BEGIN
TESTING: PROCESS
-- Define a subtype of a subtype.
subtype ZERO is NATURAL;
-- Define variables of these subtypes.
variable ZEROV : ZERO := 0;
variable NATURALV : NATURAL := 0;
BEGIN
-- Verify that these two variables have the same base type.
assert NOT( Naturalv = zerov and zerov = zero'low )
report "***PASSED TEST: c04s02b00x00p06n03i00016"
severity NOTE;
assert ( Naturalv = zerov and zerov = zero'low )
report "***FAILED TEST: c04s02b00x00p06n03i00016 - The base type of a subtype is the base type of the type mark."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p06n03i00016arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd
|
4
|
8163
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc762.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00762pkg is
--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
--Index type is natural
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
end c01s01b01x01p05n02i00762pkg;
use work.c01s01b01x01p05n02i00762pkg.ALL;
ENTITY c01s01b01x01p05n02i00762ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three : integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven : integer := 7;
eight : integer := 8;
nine : integer := 9;
fifteen :integer:= 15;
Cgen1 : boolean := true;
Cgen2 : bit := '1';
Cgen3 : character := 's';
Cgen4 : severity_level := note;
Cgen5 : integer := 3;
Cgen6 : real := 3.0;
Cgen7 : time := 3 ns;
Cgen8 : natural := 1;
Cgen9 : positive := 1;
Cgen70 : boolean_vector_st :=(others => true);
Cgen71 : severity_level_vector_st :=(others => note);
Cgen72 : integer_vector_st :=(others => 3);
Cgen73 : real_vector_st :=(others => 3.0);
Cgen74 : time_vector_st :=(others => 3 ns);
Cgen75 : natural_vector_st :=(others => 1);
Cgen76 : positive_vector_st :=(others => 1)
);
END c01s01b01x01p05n02i00762ent;
ARCHITECTURE c01s01b01x01p05n02i00762arch OF c01s01b01x01p05n02i00762ent IS
constant Vgen1 : boolean := true;
constant Vgen2 : bit := '1';
constant Vgen3 : character := 's';
constant Vgen4 : severity_level := note;
constant Vgen5 : integer := 3;
constant Vgen6 : real := 3.0;
constant Vgen7 : time := 3 ns;
constant Vgen8 : natural := 1;
constant Vgen9 : positive := 1;
constant Vgen70 : boolean_vector_st :=(others => Cgen1);
constant Vgen71 : severity_level_vector_st :=(others => Cgen4);
constant Vgen72 : integer_vector_st :=(others => Cgen5);
constant Vgen73 : real_vector_st :=(others => Cgen6);
constant Vgen74 : time_vector_st :=(others => Cgen7);
constant Vgen75 : natural_vector_st :=(others => Cgen8);
constant Vgen76 : positive_vector_st :=(others => Cgen9);
BEGIN
assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
TESTING: PROCESS
BEGIN
assert NOT( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***PASSED TEST: c01s01b01x01p05n02i00762"
severity NOTE;
assert( Vgen1 = C1 and
Vgen2 = C2 and
Vgen3 = C3 and
Vgen4 = C4 and
Vgen5 = C5 and
Vgen6 = C6 and
Vgen7 = C7 and
Vgen8 = C8 and
Vgen9 = C9 and
Vgen70 = C70 and
Vgen71 = C71 and
Vgen72 = C72 and
Vgen73 = C73 and
Vgen74 = C74 and
Vgen75 = C75 and
Vgen76 = C76 )
report "***FAILED TEST: c01s01b01x01p05n02i00762 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00762arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd
|
3
|
1855
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1176.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01176ent IS
END c08s00b00x00p01n02i01176ent;
ARCHITECTURE c08s00b00x00p01n02i01176arch OF c08s00b00x00p01n02i01176ent IS
signal k : integer := 0;
BEGIN
L1 : process
begin
k <= 5;
wait for 1 ns;
-- Avoid infinite simulation
wait;
end process L1;
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert NOT(k = 5)
report "***PASSED TEST: c08s00b00x00p01n02i01176"
severity NOTE;
assert (k = 5)
report "***FAILED TEST: c08s00b00x00p01n02i01176 - Sequential statement are executed in the order in which they appear."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01176arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2993.vhd
|
4
|
1814
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2993.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s05b00x00p02n01i02993pkg is
package P2 is -- Failure_here
-- ERROR: PACKAGE DECLARATIONS ARE NOT ALLOWED IN PACKAGES
type INIT_1 is RANGE 1 to 10;
end P2;
end c02s05b00x00p02n01i02993pkg;
ENTITY c02s05b00x00p02n01i02993ent IS
END c02s05b00x00p02n01i02993ent;
ARCHITECTURE c02s05b00x00p02n01i02993arch OF c02s05b00x00p02n01i02993ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s05b00x00p02n01i02993 - Package declarations are not allowed within packages."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s05b00x00p02n01i02993arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2526.vhd
|
4
|
1877
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2526.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n03i02526ent IS
END c07s03b05x00p06n03i02526ent;
ARCHITECTURE c07s03b05x00p06n03i02526arch OF c07s03b05x00p06n03i02526ent IS
BEGIN
TESTING: PROCESS
type Apples is range 0 to 75;
type Oranges is range 0 to 75;
type MVL is ('0','1','Z') ;
variable Macintosh : Apples;
variable Seville, valencia : Oranges;
variable V1 : MVL;
BEGIN
Macintosh := Apples (Seville) ;
V1 := Oranges (76) ; -- Failure_here
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c07s03b05x00p06n03i02526 - Target type is not an Integer or floating point type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n03i02526arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/case01/case02.vhdl
|
1
|
366
|
library ieee;
use ieee.std_logic_1164.all;
entity case02 is
port (a : std_logic_vector (4 downto 0);
o : out std_logic);
end case02;
architecture behav of case02 is
begin
with a select o <=
'1' when "00011",
'1' when "00110" | "00111" | "10001",
'0' when "00100",
'1' when "01100",
'1' when "10000",
'0' when others;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd
|
4
|
1964
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1390.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n03i01390ent IS
END c08s05b00x00p04n03i01390ent;
ARCHITECTURE c08s05b00x00p04n03i01390arch OF c08s05b00x00p04n03i01390ent IS
BEGIN
TESTING: PROCESS
variable A : integer := 0;
variable B : integer := 0;
variable C : integer := 1;
variable D : integer := 2;
type array_of_ints is array (Positive range <>) of integer;
BEGIN
(A,B) := array_of_ints'(C,D);
assert NOT( (A=1) and (B=2) )
report "***PASSED TEST: c08s05b00x00p04n03i01390"
severity NOTE;
assert ( (A=1) and (B=2) )
report "***FAILED TEST: c08s05b00x00p04n03i01390 - Each element association of the aggregate must be a locally static name that denotes a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n03i01390arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd
|
4
|
1766
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc297.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n04i00297ent IS
END c03s01b03x01p01n04i00297ent;
ARCHITECTURE c03s01b03x01p01n04i00297arch OF c03s01b03x01p01n04i00297ent IS
constant T1 : TIME := 10 ns;
signal S : BIT ;
BEGIN
TESTING: PROCESS
BEGIN
S <= '1' after T1;
wait for 20 ns;
assert NOT(S='1')
report "***PASSED TEST: c03s01b03x01p01n04i00297"
severity NOTE;
assert (S='1')
report "***FAILED TEST: c03s01b03x01p01n04i00297 - The delay specification is not of type TIME."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n04i00297arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2277.vhd
|
4
|
2391
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2277.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02277ent IS
END c07s02b06x00p14n01i02277ent;
ARCHITECTURE c07s02b06x00p14n01i02277arch OF c07s02b06x00p14n01i02277ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- m = 100 cm; -- meter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
-- ft = 12 inch; -- foot
-- yd = 3 ft; -- yard
end units;
-- Local declarations.
variable INTV : INTEGER;
variable DISTV : DISTANCE;
BEGIN
INTV := INTV / DISTV; -- ERROR:
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02277 - Incompatible operands: May not be multiplied or divided."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02277arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc5.vhd
|
4
|
1798
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc5.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p08n01i00005ent IS
END c04s01b00x00p08n01i00005ent;
ARCHITECTURE c04s01b00x00p08n01i00005arch OFc04s01b00x00p08n01i00005ent IS
BEGIN
TESTING: PROCESS
type I1 is range 1 to 1;
type I2 is range 1 to 1;
variable V1: I1;
variable V2: I2;
BEGIN
if V1 = V2 then -- Failure_here
-- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
null ;
end if;
assert FALSE
report "***FAILED TEST: c04s01b00x00p08n01i00005 - Types are different and hence incompatible."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p08n01i00005arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd
|
4
|
2012
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_19.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book (in text)
entity nand3 is
port ( a, b, c : in bit; y : out bit );
end entity nand3;
-- end code from book
architecture behavioral of nand3 is
begin
y <= not (a and b and c);
end architecture behavioral;
entity logic_block is
end entity logic_block;
-- code from book
library gate_lib;
architecture ideal of logic_block is
component nand2 is
port ( in1, in2 : in bit; result : out bit );
end component nand2;
for all : nand2
use entity gate_lib.nand3(behavioral)
port map ( a => in1, b => in2, c => '1', y => result );
-- . . . -- other declarations
-- not in book
signal s1, s2, s3 : bit := '0';
begin
gate1 : component nand2
port map ( in1 => s1, in2 => s2, result => s3 );
-- . . . -- other concurrent statements
-- not in book
s1 <= '1' after 20 ns;
s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
-- end not in book
end architecture ideal;
-- end code from book
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd
|
4
|
2166
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity fg_05_04 is
end entity fg_05_04;
architecture test of fg_05_04 is
constant prop_delay : time := 5 ns;
signal a, b, sel, z : bit;
begin
-- code from book
mux : process (a, b, sel) is
begin
case sel is
when '0' =>
z <= a after prop_delay;
when '1' =>
z <= b after prop_delay;
end case;
end process mux;
-- end code from book
stimulus : process is
subtype stim_vector_type is bit_vector(0 to 3);
type stim_vector_array is array ( natural range <> ) of stim_vector_type;
constant stim_vector : stim_vector_array
:= ( "0000",
"0010",
"0100",
"0111",
"1001",
"1010",
"1101",
"1111" );
begin
for i in stim_vector'range loop
(a, b, sel) <= stim_vector(i)(0 to 2);
wait for 10 ns;
assert z = stim_vector(i)(3);
end loop;
wait;
end process stimulus;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd
|
4
|
2086
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1424.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s06b00x00p05n01i01424ent IS
END c08s06b00x00p05n01i01424ent;
ARCHITECTURE c08s06b00x00p05n01i01424arch OF c08s06b00x00p05n01i01424ent IS
procedure copy_into ( variable dest : out integer;
variable src : in integer := 0 ) is
--
-- This procedure copies the value of the second argument
-- into the first argument.
--
begin
dest := src;
end copy_into;
BEGIN
TESTING : PROCESS
variable v1 : integer := 0;
BEGIN
--
-- Try it with only one parameter
--
copy_into(v1); -- v1 <- (0)
assert NOT(v1 = 0)
report "***PASSED TEST: c08s06b00x00p05n01i01424"
severity NOTE;
assert (v1 = 0)
report "***FAILED TEST: c08s06b00x00p05n01i01424 - Procedure call without an actual parameter part is permitted."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s06b00x00p05n01i01424arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue476/pixel_matrix_pkg.vhd
|
1
|
3095
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pixel_column_pkg;
package pixel_matrix_pkg is
generic(
NBITS_IN : natural;
NBR_OF_CHROMA_IN : natural;
NBR_OF_ROW_IN : natural;
NBR_OF_COL_IN : natural;
NBITS_OUT : natural;
NBR_OF_CHROMA_OUT : natural;
NBR_OF_ROW_OUT : natural;
NBR_OF_COL_OUT : natural;
package local_pixel_column_pkg is new pixel_column_pkg generic map (<>)
);
use local_pixel_column_pkg.all;
type TYPE_PIXEL_MATRIX_IN is array (NBR_OF_COL_IN-1 downto 0) of TYPE_PIXEL_COLUMN_IN;
type TYPE_PIXEL_MATRIX_OUT is array (NBR_OF_COL_OUT-1 downto 0) of TYPE_PIXEL_COLUMN_OUT;
-- Note: this pkgs is used to propagate the functions that where defined for a (N x 1) array of pixel
-- to a (N x M) array of pixel
function std_logic_vector_to_pixel_matrix_in( in_vector : in std_logic_vector(NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0))
return TYPE_PIXEL_MATRIX_IN;
function pixel_matrix_out_to_std_logic_vector( out_pixel_matrix : in TYPE_PIXEL_MATRIX_OUT)
return std_logic_vector;
function "not" ( pixel_matrix_in : in TYPE_PIXEL_MATRIX_IN)
return TYPE_PIXEL_MATRIX_OUT;
end package pixel_matrix_pkg;
package body pixel_matrix_pkg is
function std_logic_vector_to_pixel_matrix_in( in_vector : in std_logic_vector(NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0))
return TYPE_PIXEL_MATRIX_IN is
variable pixel_matrix_in : TYPE_PIXEL_MATRIX_IN;
begin
for col in 0 to NBR_OF_COL_IN-1 loop
pixel_matrix_in(col) := std_logic_vector_to_pixel_column_in(in_vector((col+1)*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto col*NBR_OF_ROW_OUT*NBR_OF_CHROMA_IN*NBITS_IN));
end loop;
return pixel_matrix_in;
end function std_logic_vector_to_pixel_matrix_in;
function pixel_matrix_out_to_std_logic_vector( out_pixel_matrix : in TYPE_PIXEL_MATRIX_OUT)
return std_logic_vector is
variable out_vector : std_logic_vector(NBR_OF_COL_OUT*NBR_OF_ROW_OUT*NBR_OF_CHROMA_OUT*NBITS_OUT-1 downto 0);
begin
for col in 0 to NBR_OF_COL_OUT-1 loop
out_vector(((col+1)*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN)*NBITS_IN-1 downto col*NBR_OF_ROW_OUT*NBR_OF_CHROMA_IN*NBITS_IN) := pixel_column_out_to_std_logic_vector(out_pixel_matrix(col));
end loop;
return out_vector;
end function pixel_matrix_out_to_std_logic_vector;
function "not" ( pixel_matrix_in : in TYPE_PIXEL_MATRIX_IN)
return TYPE_PIXEL_MATRIX_OUT is
variable pixel_matrix_out : TYPE_PIXEL_MATRIX_OUT;
begin
for index in 0 to NBR_OF_COL_IN-1 loop
pixel_matrix_out(index) := not pixel_matrix_in(index);
end loop;
return pixel_matrix_out;
end function "not";
end package body pixel_matrix_pkg;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/issue1239/repro2.vhdl
|
1
|
448
|
library ieee;
use ieee.std_logic_1164.all;
entity repro2 is
generic (
constant DIN_WIDTH : positive := 8;
constant F_SIZE : positive := 2
);
end repro2;
architecture Behav of repro2 is
type SLIDING_WINDOW is array (0 to F_SIZE-1, 0 to F_SIZE-1)
of STD_LOGIC_VECTOR(DIN_WIDTH- 1 downto 0);
signal WINDOW: SLIDING_WINDOW;
begin
WINDOW <=(WINDOW 'range=> (WINDOW 'range=> (WINDOW 'range=>'0')));
end Behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue167/pkg1.vhdl
|
2
|
442
|
package p is
component c is
generic (
-- None of these work in GHDL 1a1d378dcafeca5a18dfa8862ebe412efa1e9718
-- together with the ports defined below.
g : bit_vector
-- g : bit_vector := x"0"
-- g : bit_vector(3 downto 0) := x"0"
-- g : bit_vector(3 downto 0)
);
port (
-- fails if generic 'g' is referenced
x : bit_vector(g'length-1 downto 0)
);
end component;
end package;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/issue1163/bug.vhdl
|
1
|
698
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
W : positive := 4;
N : positive := 4
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic
);
end bug;
architecture behav of bug is
type queue_info_t is record
dummy : integer range 0 to W-1;
strb : std_ulogic_vector(W-1 downto 0);
end record;
type queues_t is array (0 to N-1) of queue_info_t;
signal queues : queues_t;
begin
process(clk, reset_n)
variable index : integer range 0 to N-1;
begin
if reset_n = '0' then
elsif rising_edge(clk) then
for i in 0 to W-1 loop
queues(index).strb(i) <= '0';
end loop;
end if;
end process;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/bug17309/polyamplib.vhdl
|
3
|
58980
|
-----------------------------------------------------------------------------
-- Polyamp vhdl function library
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package polyamplib is
component interface_ads1271
port (
fastclk : in std_logic; -- Fast clock
adclk : in std_logic; -- A/D converter clock
resync : in std_logic; -- Clock change; resync
ser_data : in std_logic; -- Serial data in
n_drdy : in std_logic; -- Data is ready, active low
data_out : out std_logic_vector(23 downto 0); -- Parallell data out
nsync : out std_logic; -- Synchronize (restart) A/D conv.
busy : out std_logic; -- Busy reading serial data
g_sclk : out std_logic); -- Gated SPI clock, FOR SIMULATION ONLY
end component;
component priority_resolver2 is
port (
inp : in std_logic_vector(11 downto 0);
prio : out unsigned(3 downto 0); -- Output highest signal
active : out std_logic); -- High when any input is active
end component;
component one_of_n_encoder is
port (
number : in unsigned(3 downto 0);
enable : in std_logic;
single_out : out std_logic_vector(11 downto 0)); -- Only a single wire is active at a time
end component;
component active_input is
port (
fastclk : in std_logic; -- Main clock
enable : in std_logic; -- Enable signal
busy_n : in std_logic; -- Busy input signal, active low
clear : in std_logic; -- Clear the corresponding flip-flop
active_out : out std_logic); -- Active output
end component;
component master_state_machine is
port (
fastclk : in std_logic := '0'; -- Main clock
enable_lo8 : in std_logic; -- Enable the 8 low inputs
busy_n_vec : in std_logic_vector(11 downto 0); -- Busy inputs
id_code : inout unsigned(3 downto 0); -- Id code output
fifo_write : out std_logic); -- Save to fifo
end component;
component fifo_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end component;
component fifo_ft_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end component;
component ads1271_model is
port (
analog_in : in signed(23 downto 0); -- Analog input signal
clk : in std_logic; -- Conversion clock
sclk : in std_logic; -- SPI clock
n_sync : in std_logic; -- Input sync signal, active low
din : in std_logic; -- Serial data in
dout : out std_logic; -- Serial data out
n_drdy : out std_logic); -- Data ready, active low
end component;
component sr_sipo is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
ser_in : in std_logic; --! Serial input data
par_out : out std_logic_vector(1 to LENGTH)); --! Parallel output data
end component;
component sr_piso is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
load : in std_logic; --! Load on next clock
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end component;
component sr_piso_s is
generic (
LENGTH : positive := 8; --! Shift register length
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
fastclk : in std_logic; --! Synchronous clock
clk_en : in std_logic; --! Clock enable input
load_en : in std_logic; --! Load enable input
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end component;
component spi_slave is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
spi_op : out std_logic; -- Read/Write status/data/command
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end component;
component command_decoder is
port (
addr_data : in std_logic_vector(31 downto 0); -- Input address/data
decode : in std_logic; -- Single cycle decode pulse
fastclk : in std_logic; -- Master clock (not used for now)
sel_nulcmd : out std_logic; -- NULL command (no operation)
sel_adclk0 : out std_logic; -- Select sampling clock, ad0.
sel_adclk1 : out std_logic; -- Select sampling clock, ad1.
sel_adclk2 : out std_logic; -- Select sampling clock, ad2.
sel_adclk3 : out std_logic; -- Select sampling clock, ad3.
sel_adclk4 : out std_logic; -- Select sampling clock, ad4.
sel_adclk5 : out std_logic; -- Select sampling clock, ad5.
sel_adclk6 : out std_logic; -- Select sampling clock, ad6.
sel_adclk7 : out std_logic; -- Select sampling clock, ad7.
resync_adc : out std_logic; -- Resynchronize all ADC's
write_ctrl : out std_logic; -- Write to control-signal register
start_adcs : out std_logic; -- Start AD-conversion
stop_adcs : out std_logic); -- Stop AD-conversion
end component;
component clockmux is
port (
clk24M : in std_logic; -- Input clocks, 24 576 000
clk4M : in std_logic; -- 4 096 000
clk2M : in std_logic; -- 2 048 000
clk1M : in std_logic; -- 1 024 000
clk512k : in std_logic; -- 512 000
clk256k : in std_logic; -- 256 000
clk128k : in std_logic; -- 128 000
sel : in unsigned(2 downto 0); -- Mux select input
clkout : out std_logic); -- Output clock
end component;
component spi_master is
port (
-- Hardware ports
miso : in std_logic;
mosi : out std_logic;
sck : inout std_logic;
en_adval : out std_logic := '1';
en_incl : out std_logic := '1';
-- Simulation ports
data_to_spi : in std_logic_vector(31 downto 0);
data_from_spi : out std_logic_vector(31 downto 0);
start : in std_logic;
busy : out std_logic := '0';
running : in std_logic);
end component;
component spi_slave_burst is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
exec_cmd : out std_logic; -- Write command/data
fifo_read : out std_logic; -- Read status/data
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end component;
component sync_logic_2 is
port (
start_adcs : in std_logic; -- Start command
stop_adcs : in std_logic; -- Stop command
reset : in std_logic; -- Active high
hwsync : in std_logic; -- Hardware sync
fastclk : in std_logic; -- Master clock
enable_adcvalues : out std_logic); -- Enable reception of values
end component;
end polyamplib;
-----------------------------------------------------------------------------
-- Shift register for adc_interface, spi_interface etc.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! General serial input, parallell output shift register
--! The shift register length is generic, from 2 and up. It can trigger on
--! positive or negative edges, and the shift direction can be choosen as well.
entity sr_sipo is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
ser_in : in std_logic; --! Serial input data
par_out : out std_logic_vector(1 to LENGTH)); --! Parallel output data
end sr_sipo;
architecture sr_arch of sr_sipo is
signal my_sr : std_logic_vector(1 to LENGTH);
begin -- sr_arch
posedge_right : if (EDGE = 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
my_sr(1 to LENGTH) <= (my_sr(2 to LENGTH) & ser_in);
end if;
end process shift;
end generate posedge_right;
posedge_left : if (EDGE = 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
my_sr(1 to LENGTH) <= (ser_in & my_sr(1 to LENGTH-1));
end if;
end process shift;
end generate posedge_left;
negedge_right : if (EDGE /= 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
my_sr(1 to LENGTH) <= (my_sr(2 to LENGTH) & ser_in);
end if;
end process shift;
end generate negedge_right;
negedge_left : if (EDGE /= 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
my_sr(1 to LENGTH) <= (ser_in & my_sr(1 to LENGTH-1));
end if;
end process shift;
end generate negedge_left;
par_out <= my_sr(1 to LENGTH) after 2 ns;
end sr_arch;
-----------------------------------------------------------------------------
-- Shift register for spi_interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! General parallell input, serial output shift register
--! The shift register length is generic, from 2 and up. It can trigger on
--! positive or negative edges, and the shift direction can be choosen as well.
entity sr_piso is
generic (
LENGTH : positive := 8; --! Shift register length
EDGE : natural := 1; --! Active edge; 1=positive, 0=negative
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
load : in std_logic; --! Load on next clock
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end sr_piso;
architecture sr_arch of sr_piso is
signal my_sr : std_logic_vector(1 to LENGTH);
begin -- sr_arch
shift_left : if DIR = 1 generate
ser_out <= my_sr(1) after 2 ns;
end generate shift_left;
shift_right : if DIR /= 1 generate
ser_out <= my_sr(LENGTH) after 2 ns;
end generate shift_right;
posedge_left : if (EDGE = 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(1 to (LENGTH-1)) <= my_sr(2 to LENGTH);
my_sr(LENGTH) <= ser_in;
end if;
end if;
end process shift;
end generate posedge_left;
posedge_right : if (EDGE = 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '1' then -- Positive clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(2 to LENGTH) <= my_sr(1 to LENGTH-1);
my_sr(1) <= ser_in;
end if;
end if;
end process shift;
end generate posedge_right;
negedge_left : if (EDGE /= 1) and (DIR = 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(1 to (LENGTH-1)) <= my_sr(2 to LENGTH);
my_sr(LENGTH) <= ser_in;
end if;
end if;
end process shift;
end generate negedge_left;
negedge_right : if (EDGE /= 1) and (DIR /= 1) generate
shift : process(clk)
begin
if clk'event and clk = '0' then -- Negative clock edge
if load = '1' then
my_sr <= par_in;
else
my_sr(2 to LENGTH) <= my_sr(1 to LENGTH-1);
my_sr(1) <= ser_in;
end if;
end if;
end process shift;
end generate negedge_right;
end sr_arch;
-----------------------------------------------------------------------------
-- Synchronously clocked shift register for spi_interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Synchronously clocked parallell input, serial output shift register
--! The shift register length is generic, from 2 and up.
--! The shift direction can be choosen.
entity sr_piso_s is
generic (
LENGTH : positive := 8; --! Shift register length
DIR : natural := 1); --! Direction; 1=left, 0=right
port (
fastclk : in std_logic; --! Synchronous clock
clk_en : in std_logic; --! Clock enable input
load_en : in std_logic; --! Load enable input
par_in : in std_logic_vector(1 to LENGTH); --! Parallel input data
ser_in : in std_logic; --! Serial input data
ser_out : out std_logic); --! Serial output data
end sr_piso_s;
architecture ar_piso_s_arch of sr_piso_s is
signal my_sr : std_logic_vector(1 to LENGTH);
begin -- ar_piso_s_arch
shift_left_out : if DIR = 1 generate
ser_out <= my_sr(1) after 2 ns;
end generate shift_left_out;
shift_right_out : if DIR /= 1 generate
ser_out <= my_sr(LENGTH) after 2 ns;
end generate shift_right_out;
shift_left : if (DIR = 1) generate
shift : process(fastclk)
begin
if rising_edge(fastclk) then -- Positive clock edge
if load_en = '1' then
my_sr <= par_in;
elsif clk_en = '1' then
my_sr(1 to (LENGTH-1)) <= my_sr(2 to LENGTH);
my_sr(LENGTH) <= ser_in;
end if;
end if;
end process shift;
end generate shift_left;
shift_right : if (DIR /= 1) generate
shift : process(fastclk)
begin
if rising_edge(fastclk) then -- Positive clock edge
if load_en = '1' then
my_sr <= par_in;
elsif clk_en = '1' then
my_sr(2 to LENGTH) <= my_sr(1 to LENGTH-1);
my_sr(1) <= ser_in;
end if;
end if;
end process shift;
end generate shift_right;
end ar_piso_s_arch;
-----------------------------------------------------------------------------
-- The adc_interface
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interface_ads1271 is
port (
fastclk : in std_logic; -- Fast clock
adclk : in std_logic; -- A/D converter clock
resync : in std_logic; -- Clock change; resync
ser_data : in std_logic; -- Serial data in
n_drdy : in std_logic; -- Data is ready, active low
data_out : out std_logic_vector(23 downto 0); -- Parallell data out
nsync : out std_logic := '1'; -- Synchronize (restart) A/D conv.
busy : out std_logic; -- Busy reading serial data
g_sclk : out std_logic); -- Gated SPI clock, FOR SIMULATION ONLY
end interface_ads1271;
architecture interface_ads1271_arch of interface_ads1271 is
type state_type is (idle, counting, freeze);
signal state : state_type := idle; -- Controlling state machine
signal unlatch_data : std_logic_vector(23 downto 0) := (others => '0'); -- From shift register
signal bitcounter : unsigned(4 downto 0) := to_unsigned(0, 5); -- Range 0..31
signal g_sclk_enable : std_logic := '0';
type rsync_sm_type is (rs_idle, rs_clo1, rs_chi, rs_clo2);
signal rsync_sm : rsync_sm_type := rs_idle;
component sr_sipo is
generic (
LENGTH : positive; --! Shift register length
EDGE : natural; --! Active edge; 1=positive, 0=negative
DIR : natural); --! Direction; 1=left, 0=right
port (
clk : in std_logic; --! Clock input
ser_in : in std_logic; --! Serial input data
par_out : out std_logic_vector(1 to LENGTH)); --! Parallel output data
end component;
begin -- interface_ads1271_arch
sr1 : sr_sipo generic map (
LENGTH => 24,
EDGE => 1,
DIR => 1)
port map (
clk => adclk,
ser_in => ser_data,
par_out => unlatch_data);
-- Static interconnects
g_sclk <= g_sclk_enable and adclk;
-- purpose: Freeze output data
-- type : sequential
-- inputs : adclk, n_drdy
freeze_proc : process (adclk)
begin -- process freeze_proc
if rising_edge(adclk) then -- rising clock edge
case state is
when idle => if n_drdy = '0' then
busy <= '1';
state <= counting;
bitcounter <= to_unsigned(23, 5);
g_sclk_enable <= '1';
else
busy <= '0';
end if;
when counting => busy <= '1';
if bitcounter > 0 then
bitcounter <= bitcounter - 1;
else
state <= freeze;
data_out <= unlatch_data;
g_sclk_enable <= '0';
end if;
when freeze => busy <= '0';
if n_drdy = '1' then
state <= idle;
end if;
when others => state <= idle; busy <= '0';
end case;
end if;
end process freeze_proc;
-- purpose: Handle resyncronization of A/D converters
-- Keep nsync low for at least one adclk cycle
-- type : sequential
-- inputs : fastclk, adclk, resync
-- outputs: nsync
resync_proc : process (fastclk)
begin -- process resync_proc
if rising_edge(fastclk) then -- rising clock edge
nsync <= '0';
case rsync_sm is
when rs_idle => if resync = '1' then
rsync_sm <= rs_clo1;
else
nsync <= '1';
end if;
when rs_clo1 => if adclk = '0' then
rsync_sm <= rs_chi;
end if;
when rs_chi => if adclk = '1' then
rsync_sm <= rs_clo2;
end if;
when rs_clo2 => if adclk = '0' then
rsync_sm <= rs_idle;
end if;
when others => rsync_sm <= rs_idle;
nsync <= '1';
end case;
end if;
end process resync_proc;
end interface_ads1271_arch;
-----------------------------------------------------------------------------
-- The priority_resolver2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_resolver2 is
port (
inp : in std_logic_vector(11 downto 0); -- Active low inputs
prio : out unsigned(3 downto 0); -- Output highest signal
active : out std_logic); -- High when any input is active
end priority_resolver2;
architecture priority_resolver2_arch of priority_resolver2 is
begin -- priority_resolver2_arch
-- Any input active ???
active <= inp(0) or inp(1) or inp(2) or inp(3) or inp(4) or inp(5) or
inp(6) or inp(7) or inp(8) or inp(9) or inp(10) or inp(11) after 1 ns;
-- purpose: Priority resolver
-- type : combinational
-- inputs : inp
-- outputs: prio, active
mainloop : process (inp)
begin -- process mainloop
if inp(11) = '1' then
prio <= to_unsigned(11, 4) after 1 ns;
elsif inp(10) = '1' then
prio <= to_unsigned(10, 4) after 1 ns;
elsif inp(9) = '1' then
prio <= to_unsigned(9, 4) after 1 ns;
elsif inp(8) = '1' then
prio <= to_unsigned(8, 4) after 1 ns;
elsif inp(7) = '1' then
prio <= to_unsigned(7, 4) after 1 ns;
elsif inp(6) = '1' then
prio <= to_unsigned(6, 4) after 1 ns;
elsif inp(5) = '1' then
prio <= to_unsigned(5, 4) after 1 ns;
elsif inp(4) = '1' then
prio <= to_unsigned(4, 4) after 1 ns;
elsif inp(3) = '1' then
prio <= to_unsigned(3, 4) after 1 ns;
elsif inp(2) = '1' then
prio <= to_unsigned(2, 4) after 1 ns;
elsif inp(1) = '1' then
prio <= to_unsigned(1, 4) after 1 ns;
else
prio <= to_unsigned(0, 4) after 1 ns;
end if;
end process mainloop;
end priority_resolver2_arch;
-----------------------------------------------------------------------------
-- The active_input state machine
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity active_input is
port (
fastclk : in std_logic; -- Main clock
enable : in std_logic; -- Enable signal
busy_n : in std_logic; -- Busy input signal, active low
clear : in std_logic; -- Clear the corresponding flip-flop
active_out : out std_logic); -- Active output
end active_input;
architecture active_input_arch of active_input is
type input_state_type is (i_idle, i_active, i_decay);
signal i_state : input_state_type := i_idle;
signal temp_active_out : std_logic := '0'; -- Temporary signal'
begin -- active_input_arch
-- Static delayed connex
active_out <= temp_active_out after 1 ns;
-- purpose: Input state machine
-- type : sequential
-- inputs : fastclk, fastclk, busy_n, clear
-- outputs: temp_active_out
input_active : process (fastclk)
begin -- process input_active
if rising_edge(fastclk) then -- rising clock edge
temp_active_out <= '0';
case i_state is
when i_idle => if (busy_n = '0') and (enable = '1') then
temp_active_out <= '1';
i_state <= i_active;
end if;
when i_active => if clear = '0' then
temp_active_out <= '1';
else
i_state <= i_decay;
end if;
when i_decay => if busy_n = '1' then
i_state <= i_idle;
end if;
when others => i_state <= i_idle;
end case;
end if;
end process input_active;
end active_input_arch;
-----------------------------------------------------------------------------
-- The one_of_n_encoder
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_of_n_encoder is
port (
number : in unsigned(3 downto 0);
enable : in std_logic;
single_out : out std_logic_vector(11 downto 0)); -- Only a single wire is active at a time
end one_of_n_encoder;
architecture one_of_n_encoder_arch of one_of_n_encoder is
type out_table_type is array (0 to 15) of std_logic_vector(11 downto 0);
constant out_table : out_table_type :=
("000000000001",
"000000000010",
"000000000100",
"000000001000",
"000000010000",
"000000100000",
"000001000000",
"000010000000",
"000100000000",
"001000000000",
"010000000000",
"100000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000");
begin -- one_of_n_encoder_arch
-- purpose: Translate unsigned number into a signle output
-- type : sequential
-- inputs : number, number, enable
-- outputs: single_out
xlate : process (number, enable)
begin -- process xlate
if enable = '1' then
single_out <= out_table(to_integer(number)) after 1 ns;
else
single_out <= "000000000000" after 1 ns;
end if;
end process xlate;
end one_of_n_encoder_arch;
-----------------------------------------------------------------------------
-- The master_state_machine
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.polyamplib.all;
entity master_state_machine is
port (
fastclk : in std_logic := '0'; -- Main clock
enable_lo8 : in std_logic; -- Enable the 8 low inputs
busy_n_vec : in std_logic_vector(11 downto 0); -- Busy inputs
id_code : inout unsigned(3 downto 0); -- Id code output
fifo_write : out std_logic); -- Save to fifo
end master_state_machine;
architecture master_state_machine_arch of master_state_machine is
signal active_data : std_logic_vector(11 downto 0);
signal clear_vec : std_logic_vector(11 downto 0);
signal any_active : std_logic := '0'; -- Is any input active ???
signal clear_enable : std_logic := '0'; -- Clear the current active input flip-flop
signal temp_clear_en : std_logic := '0';
signal priority : unsigned(3 downto 0);
type master_state_type is (m_idle, m_latch, m_clear, m_decay);
signal m_state : master_state_type := m_idle;
begin -- master_state_machine_arch
-- The first 8 are controlled by the enable_lo8 signal
gen1 : for i in 0 to 7 generate
inp_sm : active_input port map (
fastclk => fastclk,
enable => enable_lo8,
busy_n => busy_n_vec(i),
clear => clear_vec(i),
active_out => active_data(i));
end generate gen1;
-- The other inputs are always enabled
gen2 : for i in 8 to 11 generate
inp_sm : active_input port map (
fastclk => fastclk,
enable => '1',
busy_n => busy_n_vec(i),
clear => clear_vec(i),
active_out => active_data(i));
end generate gen2;
resolve : priority_resolver2 port map (
inp => active_data,
prio => priority,
active => any_active);
encode : one_of_n_encoder port map (
number => id_code,
enable => clear_enable,
single_out => clear_vec);
clear_enable <= temp_clear_en after 1 ns; -- After some delay
fifo_write <= clear_enable; -- Same-same
-- purpose: Master state machine
-- type : sequential
-- inputs : fastclk, s0..s11,c0..c11
-- outputs: fifo_write, data_id
master_loop : process (fastclk)
begin -- process master_loop
if rising_edge(fastclk) then -- rising clock edge
temp_clear_en <= '0';
case m_state is
when m_idle => if any_active = '1' then
id_code <= priority after 1 ns;
m_state <= m_latch;
end if;
when m_latch =>
temp_clear_en <= '1';
m_state <= m_clear;
when m_clear =>
m_state <= m_decay;
when m_decay =>
if any_active = '1' then
id_code <= priority after 1 ns;
m_state <= m_latch;
else
m_state <= m_idle;
end if;
when others => m_state <= m_idle;
end case;
end if;
end process master_loop;
end master_state_machine_arch;
-----------------------------------------------------------------------------
-- The fifo_memory
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.polyamplib.all;
entity fifo_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end fifo_memory;
architecture fifo_memory_arch of fifo_memory is
begin -- fifo_memory_arch
-- purpose: Fifo memory simulator
-- type : sequential
-- inputs : clock, datain, wrreq, rdreq, clock
-- outputs: dataout, full, empty
fifo_mem : process (clock)
subtype word is std_logic_vector(31 downto 0);
type memory_area is array(0 to fifo_size) of word;
variable fifo : memory_area; -- The fifo memory area
variable head_ix : natural := 0; -- Write data to this address
variable tail_ix : natural := 0; -- Read data from this address
variable test_ix : natural := 0; -- Used for test of overflow/underflow
begin -- process fifo
if rising_edge(clock) then -- rising clock edge
-- Synchronous clear
if sclr = '1' then
head_ix := 0;
tail_ix := 0;
elsif wrreq = '1' then -- Fifo write op's
test_ix := head_ix + 1;
if test_ix > fifo_size then
test_ix := 0;
end if;
-- Writing to full fifo discards the last value
if test_ix /= tail_ix then -- NOT full
fifo(head_ix) := datain; -- Write data
head_ix := test_ix; -- And adjust the pointer
end if;
end if;
-- Reading empty fifo returns the last value
if (rdreq = '1') and (head_ix /= tail_ix) then
dataout <= fifo(tail_ix) after 1 ns;
tail_ix := tail_ix + 1;
if tail_ix > fifo_size then
tail_ix := 0;
end if;
end if;
-- Fifo empty signal
if head_ix = tail_ix then
empty <= '1' after 1 ns;
else
empty <= '0' after 1 ns;
end if;
-- Fifo full signal
if (tail_ix = (head_ix+1)) or ((tail_ix = 0) and (head_ix = fifo_size)) then
full <= '1' after 1 ns;
else
full <= '0' after 1 ns;
end if;
-- Fifo fill meter operations
if head_ix >= tail_ix then
meter <= to_unsigned(head_ix - tail_ix, 8);
else
meter <= to_unsigned(fifo_size + 1 + head_ix - tail_ix, 8);
end if;
end if;
end process fifo_mem;
end fifo_memory_arch;
-----------------------------------------------------------------------------
-- The fifo_ft_memory
-----------------------------------------------------------------------------
-- Fallthrough fifo memory model
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.polyamplib.all;
entity fifo_ft_memory is
generic (
fifo_size : natural := 100);
port (
clock : in std_logic;
sclr : in std_logic;
datain : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
dataout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
meter : out unsigned(7 downto 0));
end fifo_ft_memory;
architecture fifo_ft_memory_arch of fifo_ft_memory is
begin -- fifo_ft_memory_arch
-- purpose: Fifo memory simulator
-- type : sequential
-- inputs : clock, datain, wrreq, rdreq, clock
-- outputs: dataout, full, empty
fifo_mem : process (clock)
subtype word is std_logic_vector(31 downto 0);
type memory_area is array(0 to fifo_size) of word;
variable fifo : memory_area; -- The fifo memory area
variable head_ix : natural := 0; -- Write data to this address
variable tail_ix : natural := 0; -- Read data from this address
variable test_ix : natural := 0; -- Used for test of overflow/underflow
begin -- process fifo
if rising_edge(clock) then -- rising clock edge
-- Synchronous clear
if sclr = '1' then
head_ix := 0;
tail_ix := 0;
else
-- Write to fifo
if wrreq = '1' then -- Fifo write op's
test_ix := head_ix + 1;
if test_ix > fifo_size then
test_ix := 0;
end if;
-- Fifo is empty
if head_ix = tail_ix then
dataout <= datain; -- Let data fall-through
fifo(head_ix) := datain; -- Write data
head_ix := test_ix; -- And adjust the pointer
elsif test_ix /= tail_ix then -- NOT full
fifo(head_ix) := datain; -- Write data
head_ix := test_ix; -- And adjust the pointer
end if;
end if;
-- Reading empty fifo returns the last value
if (rdreq = '1') and (head_ix /= tail_ix) then
tail_ix := tail_ix + 1;
if tail_ix > fifo_size then
tail_ix := 0;
end if;
if tail_ix /= head_ix then
dataout <= fifo(tail_ix) after 1 ns;
end if;
end if;
end if;
-- Fifo empty signal
if head_ix = tail_ix then
empty <= '1' after 1 ns;
else
empty <= '0' after 1 ns;
end if;
-- Fifo full signal
if (tail_ix = (head_ix+1)) or ((tail_ix = 0) and (head_ix = fifo_size)) then
full <= '1' after 1 ns;
else
full <= '0' after 1 ns;
end if;
-- Fifo fill meter operations
if head_ix >= tail_ix then
meter <= to_unsigned(head_ix - tail_ix, 8);
else
meter <= to_unsigned(fifo_size + 1 + head_ix - tail_ix, 8);
end if;
end if;
end process fifo_mem;
end fifo_ft_memory_arch;
-----------------------------------------------------------------------------
-- VHDL model of A/D-converter Texas ADS1271
-----------------------------------------------------------------------------
-- NOTE! This is a model for simulation only. It is not
-- coded to be synthezised.
-- SPI interface format, 512 clock cycles/conversion
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1271_model is
port (
analog_in : in signed(23 downto 0); -- Analog input signal
clk : in std_logic; -- Conversion clock
sclk : in std_logic; -- SPI clock
n_sync : in std_logic; -- Input sync signal, active low
din : in std_logic; -- Serial data in
dout : out std_logic; -- Serial data out
n_drdy : out std_logic := '1'); -- Data ready, active low
end ads1271_model;
architecture ads1271_model_arch of ads1271_model is
signal analog_data : signed(23 downto 0) := to_signed(0, 24);
shared variable conv_timer : integer := 2; -- Data conversion rate
shared variable sdata_counter : integer := -1; -- Controls dout bits
signal din_mem : std_logic := '0'; -- 'din' memory
signal drdy_ff : std_logic;
signal clk_del : std_logic := '0'; -- Delayed clk signal
signal sclk_del : std_logic := '0'; -- Delayed sclk signal
signal ct_is_one : std_logic; -- Locally generated sync
signal ct_is_zero : std_logic; -- Locally generated sync
begin -- ads1271_model_arch
n_drdy <= drdy_ff or ct_is_one after 8 ns;
sclk_del <= sclk after 2 ns;
clk_del <= clk after 1 ns;
-- purpose: Data conversion circuitry
-- type : sequential
-- inputs : clk_del
-- outputs: dout, ct_is_one
convert : process (clk_del)
begin -- process convert
if falling_edge(clk_del) then -- falling clock edge
ct_is_one <= '0';
ct_is_zero <= '0';
if n_sync = '0' then
conv_timer := (128*512); -- Reloading the FIR takes a while
ct_is_one <= '1';
else
conv_timer := conv_timer - 1;
if conv_timer <= 0 then -- Conversion rate number
conv_timer := 512;
sdata_counter := 23; -- MSBit comes first
ct_is_zero <= '1';
end if; -- conv_timer <= 0
if conv_timer = 1 then
ct_is_one <= '1';
end if; -- conv_timer = 1
if conv_timer = 512 then
analog_data <= analog_in; -- Data sampling, data av. after 512 clock's
end if; -- conv_timer = 512
end if; -- n_sync = '0'
end if; -- falling_edge(clk_del)
end process convert;
-- purpose: Serial data interface control
-- type : sequential
-- inputs : sclk_del
-- outputs: dout
dataout : process (sclk_del)
begin -- process dataout
if sclk_del'event then
if sclk_del = '0' then -- falling clock edge
if sdata_counter >= 0 then
dout <= 'X' after 5 ns;
dout <= analog_data(sdata_counter) after 12 ns;
sdata_counter := sdata_counter - 1;
else
dout <= 'X' after 5 ns;
dout <= din_mem after 12 ns;
end if;
else
-- rising clock edge samples din
din_mem <= din;
end if;
end if;
end process dataout;
-- purpose: Controls the drdy_ff signal
-- type : sequential
-- inputs : sclk_del, ct_is_zero
-- outputs: drdy_ff
readyctl : process (sclk_del, ct_is_zero)
begin -- process readyctl
if ct_is_zero = '1' then -- asynchronous reset (active high)
drdy_ff <= '0';
elsif falling_edge(sclk_del) then -- falling clock edge
drdy_ff <= '1';
end if;
end process readyctl;
end ads1271_model_arch;
-----------------------------------------------------------------------------
-- SPI slave with secondary spi master port
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.polyamplib.all;
entity spi_slave is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
spi_op : out std_logic; -- Read/Write status/data/command
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end spi_slave;
architecture spi_slave_arch of spi_slave is
type state_type is (idle, load, shift, relax);
signal state : state_type := idle; -- Controlling state machine
signal enable_inclinometer : std_logic := '0';
signal enable_adc : std_logic := '0';
signal adc_miso : std_logic;
signal adc_load : std_logic := '0';
-- signal g_miso : std_logic register := '0'; -- guarded miso signal
signal adc_sck : std_logic;
signal tx_sck : std_logic;
signal delayed_adc_sck : std_logic; -- Delayed, for edge detection
begin -- spi_slave_arch
-- Transmit shift register
tx_sr : sr_piso_s generic map (
LENGTH => 32,
DIR => 1) -- Shift left => MSB first
port map (
fastclk => fastclk,
clk_en => tx_sck,
load_en => adc_load,
par_in => spi_tx,
ser_in => '0',
ser_out => adc_miso);
-- Receive shift register
rx_sr : sr_sipo generic map (
LENGTH => 32,
EDGE => 1, -- Positive edge
DIR => 1) -- Shift left => MSB first
port map (
clk => adc_sck,
ser_in => mosi,
par_out => spi_rx);
-- Passthru signals
incl_sck <= sck after 1 ns;
incl_mosi <= mosi after 1 ns;
incl_ena <= not enable_inclinometer after 1 ns; -- Active low output
-- Enable and clock
enable_inclinometer <= not en_incl and en_adc after 1 ns;
enable_adc <= not en_adc after 1 ns;
adc_sck <= sck or en_adc after 1 ns; -- Clock is driven high at inactive state
tx_sck <= (not adc_sck) and delayed_adc_sck after 1 ns; -- sck negative edge trigger
-- Output data
-- miso <= g_miso;
-- purpose: ADC controls miso
-- talkto_adc : block (enable_adc = '1')
-- begin -- block talkto_adc
-- g_miso <= guarded adc_miso;
-- end block talkto_adc;
-- purpose: Inclinometer controls miso
-- talkto_incl : block (enable_inclinometer = '1')
-- begin -- block talkto_incl
-- g_miso <= guarded incl_miso;
-- end block talkto_incl;
-- Instead of the guarded assignments above
miso <= adc_miso when enable_inclinometer = '0' else incl_miso;
-- purpose: SPI slave controller state machine
-- type : sequential
-- inputs : fastclk, enable_adc
-- outputs: adc_load
input_active : process (fastclk)
begin -- process input_active
if rising_edge(fastclk) then -- rising clock edge
delayed_adc_sck <= adc_sck;
adc_load <= '1' after 1 ns;
spi_op <= '0' after 1 ns;
case state is
when idle => if enable_adc = '1' then
state <= load;
end if;
when load => state <= shift;
when shift => adc_load <= '0' after 1 ns;
if enable_adc = '0' then
state <= relax;
spi_op <= '1' after 1 ns;
end if;
when relax => state <= idle;
when others => state <= idle;
end case;
end if;
end process input_active;
end spi_slave_arch;
-----------------------------------------------------------------------------
-- SPI slave with burst capabilities and with secondary spi master port
-- NOTE! Spi mode 2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.polyamplib.all;
entity spi_slave_burst is
port (
-- Main controls
fastclk : in std_logic;
spi_tx : in std_logic_vector(31 downto 0); -- Data to be sent
spi_rx : out std_logic_vector(31 downto 0); -- Data to be received
exec_cmd : out std_logic; -- Write command/data
fifo_read : out std_logic; -- Read status/data
-- Slave port, connected to CPU
mosi : in std_logic;
miso : out std_logic;
sck : in std_logic; -- SPI clock
en_adc : in std_logic; -- Active low, enable ADC
en_incl : in std_logic; -- Active low, enable inclinometer
-- Master port, connected to inclinometer
incl_miso : in std_logic;
incl_mosi : out std_logic;
incl_sck : out std_logic;
incl_ena : out std_logic); -- Active low, enable inclinometer
end spi_slave_burst;
architecture spi_slave_burst_arch of spi_slave_burst is
-- type state_type is (idle, load, shift, relax);
-- signal state : state_type := idle; -- Controlling state machine
signal bitcounter : unsigned(4 downto 0) := to_unsigned(0, 5); -- Range 0..31
signal enable_inclinometer : std_logic := '0';
signal enable_adc : std_logic := '0';
signal adc_miso : std_logic;
signal clk_tx_sr : std_logic := '0';
signal load_tx_sr : std_logic := '0';
signal sck_r1 : std_logic; -- Delayed, for edge detection
signal sck_r2 : std_logic; -- Delayed, for edge detection
signal sck_negedge : std_logic; -- Negative edge
signal sck_posedge : std_logic; -- Positive edge
signal enable_adc_r1 : std_logic; -- Delayed, for edge detection
signal enable_adc_r2 : std_logic; -- Delayed, for edge detection
signal enable_adc_negedge : std_logic; -- Negative edge
signal bitcounter_zero : std_logic;
signal bitcounter_one : std_logic;
signal exec_ff : std_logic := '0'; -- Enable the execute signal
signal load_ff : std_logic := '0'; -- Enable the load signal
begin -- spi_slave_burst_arch
-- Transmit shift register
tx_sr : sr_piso_s generic map (
LENGTH => 32,
DIR => 1) -- Shift left => MSB first
port map (
fastclk => fastclk,
clk_en => clk_tx_sr,
load_en => load_tx_sr,
par_in => spi_tx,
ser_in => '0',
ser_out => adc_miso);
-- Receive shift register
rx_sr : sr_sipo generic map (
LENGTH => 32,
EDGE => 1, -- Positive edge
DIR => 1) -- Shift left => MSB first
port map (
clk => sck_negedge,
ser_in => mosi,
par_out => spi_rx);
-- Passthru signals
incl_sck <= sck after 1 ns;
incl_mosi <= mosi after 1 ns;
incl_ena <= not enable_inclinometer after 1 ns; -- Active low output
-- Enable and clock
enable_inclinometer <= not en_incl and en_adc after 1 ns;
enable_adc <= not en_adc after 1 ns;
sck_posedge <= sck_r1 and (not sck_r2) after 1 ns; -- sck Positive edge
sck_negedge <= sck_r2 and (not sck_r1) after 1 ns; -- sck Negative edge
enable_adc_negedge <= enable_adc_r1 and (not enable_adc_r2) after 1 ns;
fifo_read <= sck_posedge and bitcounter_one after 1 ns;
load_tx_sr <= enable_adc_negedge or
(sck_negedge and bitcounter_zero and (not load_ff)) after 1 ns;
exec_cmd <= bitcounter_zero and exec_ff and sck_posedge after 1 ns;
clk_tx_sr <= sck_posedge or enable_adc_negedge after 1 ns;
-- Instead of the guarded assignments above
miso <= adc_miso when enable_inclinometer = '0' else incl_miso after 1 ns;
-- purpose: SPI slave controller state machine
-- type : sequential
-- inputs : fastclk, sck, enable_adc, bitcounter, load_tx_sr
-- outputs: sck_r1, sck_r2, enable_adc_r1, enable_adc_r2, bitcounter
input_active : process (fastclk)
begin -- process input_active
if rising_edge(fastclk) then -- rising clock edge
sck_r2 <= sck_r1 after 1 ns;
sck_r1 <= sck after 1 ns;
enable_adc_r2 <= enable_adc_r1 after 1 ns;
enable_adc_r1 <= enable_adc after 1 ns;
if enable_adc_negedge = '1' then
bitcounter <= to_unsigned(0, 5) after 1 ns;
else if sck_negedge = '1' then
bitcounter <= bitcounter + 1 after 1 ns;
end if;
end if;
if bitcounter = 0 then
bitcounter_zero <= '1' after 1 ns;
else
bitcounter_zero <= '0' after 1 ns;
end if;
if bitcounter = 1 then
bitcounter_one <= '1' after 1 ns;
else
bitcounter_one <= '0' after 1 ns;
end if;
if enable_adc = '0' then
exec_ff <= '0' after 1 ns;
elsif bitcounter = 2 then
exec_ff <= '1' after 1 ns;
end if;
if load_tx_sr = '1' then
load_ff <= '1' after 1 ns;
elsif bitcounter = 2 then
load_ff <= '0' after 1 ns;
end if;
end if;
end process input_active;
end spi_slave_burst_arch;
----------------------------------------------------------------------
-- Command decoder function
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity command_decoder is
port (
addr_data : in std_logic_vector(31 downto 0); -- Input address/data
decode : in std_logic; -- Single cycle decode pulse
fastclk : in std_logic; -- Master clock (not used for now)
sel_nulcmd : out std_logic; -- NULL command (no operation)
sel_adclk0 : out std_logic; -- Select sampling clock, ad0.
sel_adclk1 : out std_logic; -- Select sampling clock, ad1.
sel_adclk2 : out std_logic; -- Select sampling clock, ad2.
sel_adclk3 : out std_logic; -- Select sampling clock, ad3.
sel_adclk4 : out std_logic; -- Select sampling clock, ad4.
sel_adclk5 : out std_logic; -- Select sampling clock, ad5.
sel_adclk6 : out std_logic; -- Select sampling clock, ad6.
sel_adclk7 : out std_logic; -- Select sampling clock, ad7.
resync_adc : out std_logic; -- Resynchronize all ADC's
write_ctrl : out std_logic; -- Write to control-signal register
start_adcs : out std_logic; -- Start AD-conversion
stop_adcs : out std_logic); -- Stop AD-conversion
end command_decoder;
architecture command_decoder_arch of command_decoder is
begin -- command_decoder_arch
sel_nulcmd <= '1' when (addr_data(27 downto 24) = "0000") and decode = '1' else '0';
sel_adclk0 <= '1' when (addr_data(27 downto 24) = "0001") and decode = '1' else '0';
sel_adclk1 <= '1' when (addr_data(27 downto 24) = "0010") and decode = '1' else '0';
sel_adclk2 <= '1' when (addr_data(27 downto 24) = "0011") and decode = '1' else '0';
sel_adclk3 <= '1' when (addr_data(27 downto 24) = "0100") and decode = '1' else '0';
sel_adclk4 <= '1' when (addr_data(27 downto 24) = "0101") and decode = '1' else '0';
sel_adclk5 <= '1' when (addr_data(27 downto 24) = "0110") and decode = '1' else '0';
sel_adclk6 <= '1' when (addr_data(27 downto 24) = "0111") and decode = '1' else '0';
sel_adclk7 <= '1' when (addr_data(27 downto 24) = "1000") and decode = '1' else '0';
resync_adc <= '1' when (addr_data(27 downto 24) = "1001") and decode = '1' else '0';
write_ctrl <= '1' when (addr_data(27 downto 24) = "1010") and decode = '1' else '0';
start_adcs <= '1' when (addr_data(27 downto 24) = "1011") and decode = '1' else '0';
stop_adcs <= '1' when (addr_data(27 downto 24) = "1100") and decode = '1' else '0';
end command_decoder_arch;
----------------------------------------------------------------------
-- ADC clock multiplexer function
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clockmux is
port (
clk24M : in std_logic; -- Input clocks, 24 576 000
clk4M : in std_logic; -- 4 096 000
clk2M : in std_logic; -- 2 048 000
clk1M : in std_logic; -- 1 024 000
clk512k : in std_logic; -- 512 000
clk256k : in std_logic; -- 256 000
clk128k : in std_logic; -- 128 000
sel : in unsigned(2 downto 0); -- Mux select input
clkout : out std_logic); -- Output clock
end clockmux;
architecture clockmux_arch of clockmux is
begin -- clockmux_arch
with sel select
clkout <=
clk128k when "000",
clk256k when "001",
clk512k when "010",
clk1M when "011",
clk2M when "100",
clk4M when "101",
clk24M when "110",
clk24M when others;
end clockmux_arch;
-------------------------------------------------------------------------------
-- SPI master for simulation and test (no synth.)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
port (
-- Hardware ports
miso : in std_logic;
mosi : out std_logic;
sck : inout std_logic := '0';
en_adval : out std_logic := '1';
en_incl : out std_logic := '1';
-- Simulation ports
data_to_spi : in std_logic_vector(31 downto 0);
data_from_spi : out std_logic_vector(31 downto 0);
start : in std_logic;
busy : out std_logic := '0';
running : in std_logic);
end spi_master;
architecture spi_master_arch of spi_master is
type state_type is (idle, load, shift);
signal state : state_type := idle;
signal start_mem : std_logic := '0';
begin -- spi_master_arch
-----------------------------------------------------------------------------
-- Assume that data_to_spi is defined before this process is triggered
spi_rxtx : process (sck)
variable bit_index : integer := 0;
begin -- process spi_rxtx
if sck'event then
if sck = '1' then -- rising clock edge
start_mem <= start;
case state is
when idle => if start = '1' and start_mem = '0' then -- Start rising
-- edge
en_adval <= '0' after 15 ns;
busy <= '1' after 2 ns;
state <= load;
bit_index := 31;
end if;
when load => data_from_spi(bit_index) <= miso;
state <= shift;
when shift => bit_index := bit_index - 1;
if bit_index < 0 then
state <= idle;
en_adval <= '1' after 15 ns;
busy <= '0' after 2 ns;
else
data_from_spi(bit_index) <= miso;
end if;
when others => state <= idle;
end case;
end if; -- sck = '1' else ...
if sck = '0' and (state = load or state = shift) then
mosi <= data_to_spi(bit_index) after 1 ns;
end if;
end if; -- sck'event
end process spi_rxtx;
-----------------------------------------------------------------------------
spi_clk : process
begin -- process spi_clk
while running = '1' loop
sck <= not sck;
wait for 50 ns;
end loop;
sck <= not sck;
wait for 50 ns;
sck <= not sck;
wait for 50 ns;
sck <= not sck;
wait for 50 ns;
sck <= not sck;
wait for 50 ns;
wait;
end process spi_clk;
end spi_master_arch;
----------------------------------------------------------------------
-- Synchronization logic
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_logic_2 is
port (
start_adcs : in std_logic; -- Start command
stop_adcs : in std_logic; -- Stop command
reset : in std_logic; -- Active high
hwsync : in std_logic; -- Hardware sync
fastclk : in std_logic; -- Master clock
enable_adcvalues : out std_logic); -- Enable reception of values
end sync_logic_2;
architecture sync_logic_2_arch of sync_logic_2 is
signal del_sync_1 : std_logic; -- 1'st delay
signal del_sync_2 : std_logic; -- 2'nd delay
signal sr_set : std_logic; -- Set input to SR-latch
signal sr : std_logic := '0'; -- sr Q output, entity output
begin -- sync_logic_2_arch
enable_adcvalues <= sr;
sr_set <= (del_sync_1 and (not del_sync_2)) xor start_adcs;
-- purpose: Two D-latches and one SR-latch is controlled
-- type : sequential
-- inputs : fastclk, reset, start_adcs, stop_adcs, hwsync
-- outputs: sr
registered_logic : process (fastclk, reset)
begin -- process registered_logic
if reset = '1' then -- asynchronous reset
del_sync_1 <= '0' after 2 ns;
del_sync_2 <= '0' after 2 ns;
sr <= '0' after 2 ns;
elsif rising_edge(fastclk) then -- rising clock edge
del_sync_1 <= hwsync after 2 ns;
del_sync_2 <= del_sync_1 after 2 ns;
if stop_adcs = '1' then
sr <= '0' after 2 ns;
elsif sr_set = '1' then
sr <= '1' after 2 ns;
end if;
end if;
end process registered_logic;
end sync_logic_2_arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd
|
4
|
1478
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_source.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use qsim.qsim_types.all, random.random.all;
entity source is
generic ( name : string;
distribution : distribution_type;
mean_inter_arrival_time : delay_length;
seed : seed_type;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( out_arc : out arc_type;
info_detail : in info_detail_type );
end entity source;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1621.vhd
|
4
|
1663
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1621.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p03n01i01621ent IS
begin
return true; -- illegal in entity statement region.
END c08s12b00x00p03n01i01621ent;
ARCHITECTURE c08s12b00x00p03n01i01621arch OF c08s12b00x00p03n01i01621ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01621 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01621arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2933.vhd
|
4
|
1895
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2933.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n04i02933pkg is
procedure proc1 (x, y : integer);
end c02s02b00x00p07n04i02933pkg;
package body c02s02b00x00p07n04i02933pkg is
procedure proc1 (x, y :in integer) is -- Failure_here
begin
end proc1;
end c02s02b00x00p07n04i02933pkg;
ENTITY c02s02b00x00p07n04i02933ent IS
END c02s02b00x00p07n04i02933ent;
ARCHITECTURE c02s02b00x00p07n04i02933arch OF c02s02b00x00p07n04i02933ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n04i02933 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n04i02933arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/sanity/001hello87/hello.vhdl
|
4
|
132
|
entity hello is
end hello;
architecture behav of hello is
begin
assert false report "Hello VHDL world" severity note;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
|
4
|
35957
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2002/05/21
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- C:\Rehan\Cs5\design_definition\hdl\vhdl\switch_dig_log.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity switch_dig_log is
generic
(
trans_time : real := 1.0e-9;
r_closed : resistance := 1.0e-3;
r_open : resistance := 1.0e6
);
port
(
terminal p1 : electrical ;
sw_state : in std_logic ;
terminal p2 : electrical
);
begin
end switch_dig_log ;
-----------------------------------------------------------------------------------------
architecture linear of switch_dig_log is
signal r_sig : resistance := r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
r_sig <= r_open;
elsif (sw_state'event and sw_state = '1') then
r_sig <= r_closed;
end if;
end process DetectState;
-- Characteristic equations
r == r_sig'ramp(trans_time, trans_time);
v == r*i;
end architecture linear;
-------------------------------------------------------------------------------------------
architecture log of switch_dig_log is
constant log10_r_open : real := log10(r_open);
constant log10_r_closed : real := log10(r_closed);
signal log10_r_sig : resistance := log10_r_open; -- create internal signal for CreateState process
quantity v across i through p1 to p2;
quantity r : resistance;
quantity log10_r : real;
begin
-- purpose: Detect Switch state and assign resistance value to r_sig
-- type : combinational
-- inputs : sw_state
-- outputs: r_sig
DetectState: process (sw_state)
begin -- process DetectState
if (sw_state'event and sw_state = '0') then
log10_r_sig <= log10_r_open;
elsif (sw_state'event and sw_state = '1') then
log10_r_sig <= log10_r_closed;
end if;
end process DetectState;
-- Characteristic equations
log10_r == log10_r_sig'ramp(trans_time, trans_time);
r == 10**log10_r;
v == r*i;
end architecture log;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : opamp.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: 3-pin OpAmp model with behavioral architecture
-- Uses Q'LTF function to define open-loop response
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity opamp is
-- Initialize parameters
generic (rin : resistance := 1.0e6; -- Input resistance [Ohms]
rout : resistance := 100.0; -- Output resistance (Ohms]
avol : real := 100.0e3; -- Open loop gain
f_0dB : real := 1.0e6 -- Unity Gain Frequency [Hz]
);
-- Define ports as electrical terminals
port (
terminal in_pos, in_neg, output : electrical);
end entity opamp;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Characteristics modeled:
-- 1. Open loop gain
-- 2. Frequency characteristics (single pole response)
-- 3. Input and output resistance
-- Uses Q'Ltf function to create open loop gain and roll off
-------------------------------------------------------------------------------
architecture basic of opamp is
-- Declare constants
constant f_3db : real := f_0db / avol; -- -3dB frequency
constant w_3dB : real := math_2_pi*f_3dB; -- -3dB freq in radians
-- Numerator and denominator for Q'LTF function
constant num : real_vector := (0 => avol);
constant den : real_vector := (1.0, 1.0/w_3dB);
-- Declare input and output quantities
quantity v_in across i_in through in_pos to in_neg;
quantity v_out across i_out through output;
begin -- ARCHITECTURE basic
i_in == v_in / rin; -- input current
v_out == v_in'ltf(num, den) + i_out*rout; -- output voltage
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : comparator_d.vhd
-- Author : Mentor Graphics
-- Created : 2001/08/03
-- Last update: 2001/08/03
-------------------------------------------------------------------------------
-- Description: Voltage comparator with digital output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/08/03 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use IEEE natures and packages
library IEEE;
use ieee.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
use IEEE_proposed.ENERGY_SYSTEMS.all;
entity comparator_d is
port (
terminal in_pos : electrical;
terminal in_neg : electrical;
signal output : out std_logic := '1' -- Digital output
);
end comparator_d;
-------------------------------------------------------------------------------
-- Behavioral architecture
-------------------------------------------------------------------------------
architecture behavioral of comparator_d is
quantity Vin across in_pos;
quantity Vref across in_neg;
begin -- behavioral
-- purpose: Detect threshold crossing and assign event on output
-- type : combinational
-- inputs : vin'above(thres)
-- outputs: pulse_signal
process (Vin'above(Vref)) is
begin -- PROCESS
if Vin'above(Vref) then
output <= '1' after 1us;
else
output <= '0' after 1us;
end if;
end process;
end behavioral;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pwm_mac is
port(
terminal inp : electrical;
terminal inm : electrical;
dig_out : out std_logic
);
end pwm_mac;
architecture pwm_mac of pwm_mac is
-- Component declarations
-- Signal declarations
terminal cmp_in : electrical;
terminal plse_in : electrical;
terminal XSIG010002 : electrical;
terminal XSIG010003 : electrical;
begin
-- Signal assignments
-- Component instances
U1 : entity work.opamp(basic)
port map(
in_neg => XSIG010002,
in_pos => inm,
output => cmp_in
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => XSIG010002,
p2 => cmp_in
);
v2 : entity work.v_constant(ideal)
generic map(
level => 0.0
)
port map(
pos => XSIG010003,
neg => ELECTRICAL_REF
);
R2 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => plse_in,
p2 => XSIG010002
);
R3 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => inp,
p2 => XSIG010002
);
XCMP4 : entity work.comparator_d(behavioral)
port map(
output => dig_out,
in_pos => XSIG010003,
in_neg => cmp_in
);
v9 : entity work.v_pulse(ideal)
generic map(
initial => -4.7,
pulse => 4.7,
ti2p => 200 us,
tp2i => 200 us,
delay => 1 us,
width => 1 us,
period => 405 us
)
port map(
pos => plse_in,
neg => ELECTRICAL_REF
);
end pwm_mac;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : prop_pwl.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Propeller Load (Rotational_V domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
package pwl_functions is
function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
return real;
function interpolate (x,y2,y1,x2,x1 : in real)
return real;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real;
end package pwl_functions;
package body pwl_functions is
function interpolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "interpolate: x1 cannot be equal to x2"
severity error;
assert (x >= x1) and (x <= x2)
report "interpolate: x must be between x1 and x2, inclusively "
severity error;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function interpolate;
function extrapolate (x,y2,y1,x2,x1 : in real)
return real is
variable m, yvalue : real;
begin
assert (x1 /= x2)
report "extrapolate: x1 cannot be equal to x2"
severity error;
assert (x <= x1) or (x >= x2)
report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
severity warning;
m := (y2 - y1)/(x2 - x1);
yvalue := y1 + m*(x - x1);
return yvalue;
end function extrapolate;
-- Created a new pwl_dim1_extrap function that returns extrapolated yvalue for "out-of-range" x value.
function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector )
return real is
variable xvalue, yvalue, m : real;
variable start, fin, mid: integer;
begin
if x <= xdata(0) then
yvalue := extrapolate(x,ydata(1),ydata(0),xdata(1),xdata(0));
return yvalue;
end if;
if x >= xdata(xdata'right) then
yvalue := extrapolate(x,ydata(ydata'right),ydata(ydata'right-1),xdata(xdata'right),xdata(xdata'right-1));
return yvalue;
end if;
start:=0;
fin:=xdata'right;
-- I assume that the valid elements are from xdata(0) to xdata(fin), inclusive.
-- so fin==n-1 in C terms (where n is the size of the array).
while start <=fin loop
mid:=(start+fin)/2;
if xdata(mid) < x
then start:=mid+1;
else fin:=mid-1;
end if;
end loop;
if xdata(mid) > x
then mid:=mid-1;
end if;
yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));
return yvalue;
end function pwl_dim1_extrap;
end package body pwl_functions;
library IEEE_proposed; use IEEE_proposed.mechanical_systems.all;
library ieee; use ieee.math_real.all;
use work.pwl_functions.all;
entity prop_pwl is
generic (
ydata : real_vector; -- torque data
xdata : real_vector -- velocity data
);
port (terminal shaft1 : rotational_v);
end entity prop_pwl;
architecture ideal of prop_pwl is
quantity w across torq through shaft1 to rotational_v_ref;
begin
torq == pwl_dim1_extrap(w, xdata, ydata);
end architecture ideal;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : diode_pwl.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Diode model with ideal architecture
-- Currently no Generics due to bug in DV
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
use IEEE_proposed.energy_systems.all;
ENTITY diode_pwl IS
GENERIC (
ron : real; -- equivalent series resistance
roff : real); -- leakage resistance
PORT (
TERMINAL p, -- positive pin
m : electrical); -- minus pin
END ENTITY diode_pwl;
ARCHITECTURE simple OF diode_pwl IS
QUANTITY v across i through p TO m;
BEGIN -- simple ARCHITECTURE
if v'Above(0.0) use
i == v/ron;
elsif not v'Above(0.0) use
i == v/roff;
else
i == 0.0;
end use;
break on v'Above(0.0);
END ARCHITECTURE simple;
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (v_sine.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_sine IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_sine;
-- Ideal Architecture
ARCHITECTURE ideal OF v_sine IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_Prop is
end tb_CS5_Prop;
architecture TB_CS5_Prop of tb_CS5_Prop is
-- Component declarations
-- Signal declarations
terminal prop : rotational_v;
terminal prop_amp_in : electrical;
terminal prop_mtr_in : electrical;
terminal prop_pwr : electrical;
signal pwm_out : std_logic;
begin
-- Signal assignments
-- Component instances
motor2 : entity work.DC_Motor(basic)
generic map(
kt => 30.1e-3,
l => 40.0e-6,
d => 5.63e-12,
j => 315.0e-6,
r_wind => 0.16
)
port map(
p1 => prop_mtr_in,
p2 => ELECTRICAL_REF,
shaft_rotv => prop
);
v4 : entity work.v_constant(ideal)
generic map(
level => 42.0
)
port map(
pos => prop_pwr,
neg => ELECTRICAL_REF
);
sw2 : entity work.switch_dig_log
port map(
sw_state => pwm_out,
p2 => prop_mtr_in,
p1 => prop_pwr
);
pwm1 : entity work.pwm_mac
port map(
inp => prop_amp_in,
dig_out => pwm_out,
inm => ELECTRICAL_REF
);
XCMP37 : entity work.prop_pwl(ideal)
generic map(
ydata => (0.233, 0.2865, 0.347, 0.4138, 0.485, 0.563, 0.645, 0.735, 0.830, 0.93, 1.08),
xdata => (471.2, 523.6, 576.0, 628.3, 680.7, 733.0, 785.4, 837.7, 890.0, 942.5, 994.8)
)
port map(
shaft1 => prop
);
D4 : entity work.diode_pwl(simple)
generic map(
ron => 0.001,
roff => 100.0e3
)
port map(
p => ELECTRICAL_REF,
m => prop_mtr_in
);
v8 : entity work.v_sine(ideal)
generic map(
freq => 1.0,
amplitude => 2.3,
phase => 0.0,
offset => 2.3
)
port map(
pos => prop_amp_in,
neg => ELECTRICAL_REF
);
end TB_CS5_Prop;
--
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue45/test2.vhdl
|
2
|
632
|
library ieee;
use ieee.std_logic_1164.all;
entity psl_test2_endpoint is
end entity psl_test2_endpoint;
architecture test of psl_test2_endpoint is
signal s_clk : std_logic := '0';
signal req, grant : std_logic;
begin
grant <= '0';
process
begin
for i in 1 to 10 loop
s_clk <= not s_clk;
if i = 5 then
req <= '1';
end if;
wait for 10 ns;
end loop;
wait;
end process;
-- psl endpoint e_test is {req; not(grant)} @rising_edge (s_clk);
process
begin
wait until e_test;
report "e_test hit" severity error;
wait;
end process;
end architecture test;
|
gpl-2.0
|
tgingold/ghdl
|
libraries/ieee2008/numeric_bit-body.vhdl
|
1
|
93982
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body NUMERIC_BIT is
-- null range array constants
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNSIGNED; C : BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNSIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : SIGNED; C : BIT) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(L_LEFT downto 0) is R;
variable RESULT : SIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNSIGNED; XQUOT, XREMAIN : out UNSIGNED) is
variable TEMP : UNSIGNED(NUM'length downto 0);
variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0);
alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_BIT.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_BIT.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
---------------- Local Subprograms - Relational Operators --------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- ====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT : SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : SIGNED(ARG_LEFT downto 0);
variable CBIT : BIT := '1';
begin
if ARG'length < 1 then return NAS;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.3R
function "+" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.4R
function "+" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.9R
function "-" (L : UNSIGNED; R : BIT) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : BIT; R : UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.10R
function "-" (L : SIGNED; R : BIT) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : BIT; R : SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) := (others => '0');
variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
QNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
RNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
RNEG := true;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNSIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : SIGNED; Y : BIT) return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function ">";
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function ">";
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function "<";
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function "<";
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function "<=";
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "<=";
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function ">=";
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function ">=";
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'length), R);
end function "=";
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "=";
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'length), R));
end function "/=";
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length)));
end function "/=";
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(L, SIZE);
else
return RESIZE(R, SIZE);
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
if UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE)) then
return RESIZE(R, SIZE);
else
return RESIZE(L, SIZE);
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED) return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER) return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : SIGNED) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.53
function "?>" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- Id: C.54
function "?>" (L : SIGNED; R : INTEGER) return BIT is
begin
if L > R then
return '1';
else
return '0';
end if;
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : SIGNED) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.59
function "?<" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- Id: C.60
function "?<" (L : SIGNED; R : INTEGER) return BIT is
begin
if L < R then
return '1';
else
return '0';
end if;
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- Id: C.66
function "?<=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L <= R then
return '1';
else
return '0';
end if;
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- Id: C.72
function "?>=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L >= R then
return '1';
else
return '0';
end if;
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.77
function "?=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- Id: C.78
function "?=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L = R then
return '1';
else
return '0';
end if;
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNSIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : SIGNED) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNSIGNED; R : NATURAL) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- Id: C.84
function "?/=" (L : SIGNED; R : INTEGER) return BIT is
begin
if L /= R then
return '1';
else
return '0';
end if;
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER is
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
if ARG(ARG'left) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is
variable RESULT : UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER;
SIZE : NATURAL) return SIGNED is
variable RESULT : SIGNED(SIZE-1 downto 0);
variable B_VAL : BIT := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED is
alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : BIT; R : UNSIGNED) return UNSIGNED is
begin
return UNSIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNSIGNED; R : BIT) return UNSIGNED is
begin
return UNSIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L and BIT_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L or BIT_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nand BIT_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L nor BIT_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xor BIT_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : BIT; R : SIGNED) return SIGNED is
begin
return SIGNED (L xnor BIT_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : SIGNED; R : BIT) return SIGNED is
begin
return SIGNED (BIT_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : SIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNSIGNED) return BIT is
begin
return and (BIT_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : SIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNSIGNED) return BIT is
begin
return nand (BIT_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : SIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNSIGNED) return BIT is
begin
return or (BIT_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : SIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNSIGNED) return BIT is
begin
return nor (BIT_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : SIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNSIGNED) return BIT is
begin
return xor (BIT_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : SIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNSIGNED) return BIT is
begin
return xnor (BIT_VECTOR (L));
end function "xnor";
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function TO_OSTRING (value : UNSIGNED) return STRING is
begin
return TO_OSTRING(BIT_VECTOR (value));
end function TO_OSTRING;
function TO_OSTRING (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : BIT_VECTOR(1 to (result_length*3 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return TO_OSTRING(pad & BIT_VECTOR (value));
end function TO_OSTRING;
function to_hstring (value : UNSIGNED) return STRING is
begin
return to_hstring(BIT_VECTOR (value));
end function to_hstring;
function to_hstring (value : SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : BIT_VECTOR(1 to (result_length*4 - value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & BIT_VECTOR (value));
end function to_hstring;
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ(L : inout LINE; VALUE : out SIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
GOOD := true;
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
GOOD := true;
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*3-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.OREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
good => ok);
if not ok then
GOOD := false;
return;
end if;
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
GOOD := true;
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
GOOD := false;
end if;
end if;
else
GOOD := true;
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : BIT_VECTOR(0 to ne*4-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
if (pad > 0) then
if (ivalue(0) = '0') then -- positive
if ivalue(0) = or (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
else -- negative
if ivalue(0) = and (ivalue(0 to pad)) then
VALUE := SIGNED (ivalue (pad to ivalue'high));
else
assert false
report "NUMERIC_BIT.HREAD Error: Signed vector truncated"
severity error;
end if;
end if;
else
VALUE := SIGNED (ivalue);
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : BIT_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : BIT_VECTOR(VALUE'range);
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : BIT_VECTOR(0 to (ne*4 - VALUE'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := BIT_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_BIT;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue1226/adder.vhdl
|
2
|
464
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
port
(
nibble1, nibble2 : in unsigned(3 downto 0);
sum : out unsigned(3 downto 0);
carry_out : out std_logic
);
end entity adder;
architecture behavioral of adder is
signal temp : unsigned(4 downto 0);
begin
temp <= ("0" & nibble1) + nibble2;
sum <= temp(3 downto 0);
carry_out <= temp(4);
end architecture behavioral;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/issue1058/tb_ent.vhdl
|
1
|
412
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal v : std_logic_vector (31 downto 0);
begin
dut: entity work.ent
port map (clk => clk, o => v);
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert v = x"8000_0000" severity failure;
wait;
end process;
end behav;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue50/idct.d/muxb_162.vhd
|
2
|
355
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_162 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_162;
architecture augh of muxb_162 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1064.vhd
|
4
|
1969
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1064.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01064ent IS
END c06s04b00x00p03n02i01064ent;
ARCHITECTURE c06s04b00x00p03n02i01064arch OF c06s04b00x00p03n02i01064ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN3)(EN2, 1); -- ONE LESS AND ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01064 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01064arch;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/synth/issue962/ent2.vhdl
|
1
|
122
|
entity ent2 is
end;
architecture a of ent2 is
signal x : integer;
signal y : integer;
begin
y <= x / 2;
end;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd
|
4
|
1902
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
package alu_types is
constant data_width : positive := 32;
end package alu_types;
package io_types is
constant data_width : positive := 32;
end package io_types;
entity controller_system is
end entity controller_system;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
use work.alu_types.all, work.io_types.all;
architecture structural of controller_system is
alias alu_data_width is work.alu_types.data_width;
alias io_data_width is work.io_types.data_width;
signal alu_in1, alu_in2,
alu_result : std_logic_vector(0 to alu_data_width - 1);
signal io_data : std_logic_vector(0 to io_data_width - 1);
-- . . .
-- not in book
-- following should not analyze: data_width not directly visible
-- constant test : positive := data_width;
-- end not in book
begin
-- . . .
end architecture structural;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/gna/issue379/e.vhdl
|
1
|
595
|
entity e is end entity;
architecture a of e is
begin
process
constant z :integer := 0;
type t is array(0 to 0) of bit;
procedure x(
z :out bit_vector(0 to 0);
f :out bit_vector(0 to 0)
) is
begin
end procedure;
procedure x(
z :out t;
f :out bit_vector(0 to 0)
) is
begin
end procedure;
function f(arg:t) return bit is
begin
end function;
variable actual_for_f :bit;
variable actual_for_z :t; -- bit
begin
x(
f(z) => actual_for_f,
f(z) => actual_for_z
);
end process;
end architecture;
|
gpl-2.0
|
tgingold/ghdl
|
testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd
|
4
|
1841
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library util; use util.stimulus_generators.all;
architecture test of inline_08 is
constant T_pd : delay_length := 5 ns;
signal a, b : bit := '0';
signal test_inputs : bit_vector(1 to 2);
begin
block_3_f : block is
signal sum, carry : bit;
begin
-- code from book:
half_add : process is
begin
sum <= a xor b after T_pd;
carry <= a and b after T_pd;
wait on a, b;
end process half_add;
-- end of code from book
end block block_3_f;
----------------
block_3_g : block is
signal sum, carry : bit;
begin
-- code from book:
half_add : process (a, b) is
begin
sum <= a xor b after T_pd;
carry <= a and b after T_pd;
end process half_add;
-- end of code from book
end block block_3_g;
----------------
stimulus_3_f_g :
all_possible_values(test_inputs, 20 ns);
(a, b) <= test_inputs;
end architecture test;
|
gpl-2.0
|
ReconOS/reconos
|
lib/pcores/reconos_memif_memory_controller_v1_00_a/hdl/vhdl/reconos_memif_memory_controller_user_logic.vhd
|
1
|
7350
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - Memory Controller
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A memory controller connecting the memory fifos with
-- the axi bus of the system.
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity reconos_memif_memory_controller_user_logic is
--
-- Port definitions
--
-- MEMIF_Hwt2Mem_In_/MEMIF_Mem2Hwt_In_ - fifo signal inputs
--
-- BUS2IP_/IP2BUS_ - axi ipif signals
--
port (
MEMIF_Hwt2Mem_In_Data : in std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
MEMIF_Hwt2Mem_In_Empty : in std_logic;
MEMIF_Hwt2Mem_In_RE : out std_logic;
MEMIF_Mem2Hwt_In_Data : out std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0);
MEMIF_Mem2Hwt_In_Full : in std_logic;
MEMIF_Mem2Hwt_In_WE : out std_logic;
BUS2IP_Clk : in std_logic;
BUS2IP_Resetn : in std_logic;
IP2BUS_Mst_Addr : out std_logic_vector(31 downto 0);
IP2BUS_Mst_BE : out std_logic_vector(3 downto 0);
IP2BUS_Mst_Length : out std_logic_vector(11 downto 0);
IP2BUS_Mst_Type : out std_logic;
IP2BUS_Mst_Lock : out std_logic;
IP2BUS_Mst_Reset : out std_logic;
BUS2IP_Mst_CmdAck : in std_logic;
BUS2IP_Mst_Cmplt : in std_logic;
BUS2IP_Mst_Error : in std_logic;
IP2BUS_MstRd_Req : out std_logic;
BUS2IP_MstRd_D : in std_logic_vector(31 downto 0);
BUS2IP_MstRd_Rem : in std_logic_vector(3 downto 0);
BUS2IP_MstRd_Sof_N : in std_logic;
BUS2IP_MstRd_Eof_N : in std_logic;
BUS2IP_MstRd_Src_Rdy_N : in std_logic;
BUS2IP_MstRd_Src_Dsc_N : in std_logic;
IP2BUS_MstRd_Dst_Rdy_N : out std_logic;
IP2BUS_MstRd_Dst_Dsc_N : out std_logic;
IP2BUS_MstWr_Req : out std_logic;
IP2BUS_MstWr_D : out std_logic_vector(31 downto 0);
IP2BUS_MstWr_Rem : out std_logic_vector(3 downto 0);
IP2BUS_MstWr_Sof_N : out std_logic;
IP2BUS_MstWr_Eof_N : out std_logic;
IP2BUS_MstWr_Src_Rdy_N : out std_logic;
IP2BUS_MstWr_Src_Dsc_N : out std_logic;
BUS2IP_MstWr_Dst_Rdy_N : in std_logic;
BUS2IP_MstWr_Dst_Dsc_N : in std_logic
);
end entity reconos_memif_memory_controller_user_logic;
architecture imp of reconos_memif_memory_controller_user_logic is
--
-- Internal state machine
--
--
-- state_type - vhdl type of the states
-- state - instantiation of the state
--
type state_type is (STATE_READ_CMD,STATE_READ_ADDR,
STATE_PROCESS_WRITE_0,STATE_PROCESS_WRITE_1,
STATE_PROCESS_READ_0,STATE_PROCESS_READ_1,
STATE_CMPLT);
signal state : state_type := STATE_READ_CMD;
--
-- Internal signals
--
-- mem_addr - received address from hwt
--
-- mem_op - operation to perform
-- mem_length - number of bytes to transfer
-- mem_count - counter of transferred bytes
--
signal mem_addr : std_logic_vector(C_MEMIF_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_op : std_logic_vector(C_MEMIF_OP_WIDTH - 1 downto 0) := (others => '0');
signal mem_length : unsigned(C_MEMIF_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mem_count : unsigned(C_MEMIF_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal rd_req, wr_req : std_logic;
begin
-- == Static assignments of signals ===================================
IP2BUS_Mst_BE <= (others => '1');
IP2BUS_Mst_Type <= '1';
IP2BUS_Mst_Lock <= '0';
IP2BUS_Mst_Reset <= '0';
IP2BUS_MstRd_Dst_Dsc_N <= '0';
IP2BUS_MstWr_Src_Dsc_N <= '1';
IP2BUS_MstWr_Rem <= (others => '0');
-- == Process definitions =============================================
--
-- Process handling reading from and writing to the memory.
--
-- Reads data from the memory and writes it into the memif fifos or
-- writes data form the memif fifo the the memory.
--
rdwr : process(BUS2IP_Clk,BUS2IP_Resetn) is
begin
if BUS2IP_Resetn = '0' then
state <= STATE_READ_CMD;
elsif rising_edge(BUS2IP_Clk) then
case state is
when STATE_READ_CMD =>
if MEMIF_Hwt2Mem_In_Empty = '0' then
mem_op <= MEMIF_Hwt2Mem_In_Data(C_MEMIF_OP_RANGE);
mem_length <= unsigned(MEMIF_Hwt2Mem_In_Data(C_MEMIF_LENGTH_RANGE));
mem_count <= unsigned(MEMIF_Hwt2Mem_In_Data(C_MEMIF_LENGTH_RANGE));
state <= STATE_READ_ADDR;
end if;
when STATE_READ_ADDR =>
if MEMIF_Hwt2Mem_In_Empty = '0' then
mem_addr <= MEMIF_Hwt2Mem_In_Data;
case mem_op is
when MEMIF_CMD_READ =>
state <= STATE_PROCESS_READ_0;
when MEMIF_CMD_WRITE =>
state <= STATE_PROCESS_WRITE_0;
when others =>
end case;
end if;
when STATE_PROCESS_WRITE_0 =>
if BUS2IP_Mst_CmdAck = '1' then
state <= STATE_PROCESS_WRITE_1;
end if;
when STATE_PROCESS_WRITE_1 =>
if BUS2IP_MstWr_Dst_Rdy_N = '0' and MEMIF_Hwt2Mem_In_Empty = '0' then
mem_count <= mem_count - 4;
if mem_count - 4 = 0 then
state <= STATE_CMPLT;
end if;
end if;
when STATE_PROCESS_READ_0 =>
if BUS2IP_Mst_CmdAck = '1' then
state <= STATE_PROCESS_READ_1;
end if;
when STATE_PROCESS_READ_1 =>
if BUS2IP_MstRd_Src_Rdy_N = '0' and MEMIF_Mem2Hwt_In_Full = '0' then
mem_count <= mem_count - 4;
if mem_count - 4 = 0 then
state <= STATE_CMPLT;
end if;
end if;
when STATE_CMPLT =>
if BUS2IP_Mst_Cmplt = '1' then
state <= STATE_READ_CMD;
end if;
when others =>
end case;
end if;
end process rdwr;
-- == Multiplexing signals ============================================
IP2Bus_Mst_Addr <= mem_addr;
IP2BUS_Mst_Length <= std_logic_vector(mem_length(11 downto 0));
IP2BUS_MstRd_Req <= '1' when state = STATE_PROCESS_READ_0 else '0';
IP2BUS_MstRd_Dst_Rdy_N <= MEMIF_Mem2Hwt_In_Full when state = STATE_PROCESS_READ_1 else '1';
IP2BUS_MstWr_D <= MEMIF_Hwt2Mem_In_Data;
IP2BUS_MstWr_Req <= '1' when state = STATE_PROCESS_WRITE_0 else '0';
IP2BUS_MstWr_Src_Rdy_N <= MEMIF_Hwt2Mem_In_Empty when state = STATE_PROCESS_WRITE_1 else '1';
IP2BUS_MstWr_Sof_N <= '0' when mem_count = mem_length else '1';
IP2BUS_MstWr_Eof_N <= '0' when mem_count - 4 = 0 else '1';
MEMIF_Hwt2Mem_In_RE <= not BUS2IP_MstWr_Dst_Rdy_N when state = STATE_PROCESS_WRITE_1 else
'1' when state = STATE_READ_CMD else
'1' when state = STATE_READ_ADDR else
'0';
MEMIF_Mem2Hwt_In_Data <= BUS2IP_MstRd_D;
MEMIF_Mem2Hwt_In_WE <= not BUS2IP_MstRd_Src_Rdy_N when state = STATE_PROCESS_READ_1 else '0';
end architecture imp;
|
gpl-2.0
|
ReconOS/reconos
|
lib/pcores/reconos_osif_intc_v1_00_a/hdl/vhdl/reconos_osif_intc.vhd
|
1
|
9069
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - INTC - Top level entity
--
-- project: ReconOS
-- author: Christoph R??thing, University of Paderborn
-- description: A simple interrupt controller with variable number of
-- inputs to connect the RECONOS_AXI_FIFO-interrupts to
-- the processor.
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
entity reconos_osif_intc is
generic (
-- INTC paramters
C_NUM_INTERRUPTS : integer := 1;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
-- INTC ports
<<generate for SLOTS>>
OSIF_INTC_In_<<Id>> : in std_logic;
<<end generate>>
OSIF_INTC_Out : out std_logic;
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end entity reconos_osif_intc;
architecture implementation of reconos_osif_intc is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
<<generate for SLOTS>>
ATTRIBUTE X_INTERFACE_INFO of OSIF_INTC_In_<<Id>>: SIGNAL is "xilinx.com:signal:interrupt:1.0 OSIF_INTC_In_<<Id>> INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER of OSIF_INTC_In_<<Id>>: SIGNAL is "SENSITIVITY LEVEL_HIGH";
<<end generate>>
ATTRIBUTE X_INTERFACE_INFO of OSIF_INTC_Out: SIGNAL is "xilinx.com:signal:interrupt:1.0 OSIF_INTC_Out INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER of OSIF_INTC_Out: SIGNAL is "SENSITIVITY LEVEL_HIGH";
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := C_NUM_INTERRUPTS / C_SLV_DWIDTH + 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- Index for CS/CE
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal intc_in : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity work.reconos_osif_intc_user_logic
generic map (
-- INTC ports
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS,
-- Bus protocol parameters
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- INTC ports
OSIF_INTC_In => intc_in,
OSIF_INTC_Out => OSIF_INTC_Out,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
<<generate for SLOTS>>
intc_in(<<_i>>) <= OSIF_INTC_In_<<Id>>;
<<end generate>>
end implementation;
|
gpl-2.0
|
fablab-lannion/IllustraBot2
|
android/www/lib/ngCordova/demo/www/lib/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
gpl-2.0
|
vvk/sysrek
|
skin_color_segm/ipcore_dir/delayLineBRAM/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-2.0
|
vvk/sysrek
|
skin_color_segm/ipcore_dir/delayLineBRAM/simulation/delayLineBRAM_tb.vhd
|
2
|
4352
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: delayLineBRAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY delayLineBRAM_tb IS
END ENTITY;
ARCHITECTURE delayLineBRAM_tb_ARCH OF delayLineBRAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
delayLineBRAM_synth_inst:ENTITY work.delayLineBRAM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-2.0
|
vvk/sysrek
|
skin_color_segm/ipcore_dir/delayLineBRAM/example_design/delayLineBRAM_exdes.vhd
|
2
|
4641
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY delayLineBRAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END delayLineBRAM_exdes;
ARCHITECTURE xilinx OF delayLineBRAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT delayLineBRAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : delayLineBRAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-2.0
|
freecores/lq057q3dc02
|
design/image_gen_bram.vhd
|
1
|
8627
|
------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
------------------------------------------------------------------------------
--
-- $Id: image_gen_bram.vhd,v 1.2 2008-11-07 04:54:32 jwdonal Exp $
--
-- Description: This file controls the BRAM components for each color.
--
-- Structure:
-- - xupv2p.ucf
-- - components.vhd
-- - lq057q3dc02_tb.vhd
-- - lq057q3dc02.vhd
-- - dcm_sys_to_lcd.xaw
-- - video_controller.vhd
-- - enab_control.vhd
-- - hsyncx_control.vhd
-- - vsyncx_control.vhd
-- - clk_lcd_cyc_cntr.vhd
-- - image_gen_bram.vhd
-- - image_gen_bram_red.xco
-- - image_gen_bram_green.xco
-- - image_gen_bram_blue.xco
--
------------------------------------------------------------------------------
--
-- Naming Conventions:
-- active low signals "*x"
-- clock signal "CLK_*"
-- reset signal "RST"
-- generic/constant "C_*"
-- user defined type "TYPE_*"
-- state machine next state "*_ns"
-- state machine current state "*_cs""
-- pipelined signals "*_d#"
-- register delay signals "*_p#"
-- signal "*_sig"
-- variable "*_var"
-- storage register "*_reg"
-- clock enable signals "*_ce"
-- internal version of output port used as connecting wire "*_wire"
-- input/output port "ALL_CAPS"
-- process "*_PROC"
--
------------------------------------------------------------------------------
--////////////////////--
-- LIBRARY INCLUSIONS --
--////////////////////--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.components.ALL;
--////////////////////--
-- ENTITY DECLARATION --
--////////////////////--
ENTITY image_gen_bram IS
generic (
C_BIT_DEPTH,
C_VSYNC_TVS,
C_LINE_NUM_WIDTH,
C_CLK_LCD_CYC_NUM_WIDTH,
C_ENAB_TEP,
C_ENAB_THE,
C_BRAM_ADDR_WIDTH,
C_IMAGE_WIDTH,
C_IMAGE_HEIGHT : POSITIVE
);
port(
RSTx,
CLK_LCD : IN std_logic;
LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);
CLK_LCD_CYC_NUM : IN std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);
R,
G,
B : OUT std_logic_vector(C_BIT_DEPTH/3-1 downto 0)
);
END ENTITY image_gen_bram;
--////////////////////////--
-- ARCHITECTURE OF ENTITY --
--////////////////////////--
ARCHITECTURE image_gen_bram_arch OF image_gen_bram IS
constant C_NUM_LCD_PIXELS : positive := 320; -- number of drawable pixels per line in the LCD
--Connecting signal wires between components
signal SINIT_wire : std_logic := '0';
signal ADDR_wire : std_logic_vector(C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0');
begin
--//////////////////////////--
-- COMPONENT INSTANTIATIONS --
--//////////////////////////--
--You can't simply instantiate one XCO BRAM component 3 times because all
--three components are initialized with 3 different COE files!
image_RED_data : image_gen_bram_red
port map (
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
douta => R
);
image_GREEN_data : image_gen_bram_green
port map (
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
douta => G
);
image_BLUE_data : image_gen_bram_blue
port map (
clka => CLK_LCD,
addra => ADDR_wire,
-- OUTPUTS --
douta => B
);
------------------------------------------------------------------
-- Process Description:
-- This process controls the BRAM's SINIT signal which sets the
-- DOUT pins of the BRAM to the value defined at the time of
-- the Xilinx core customization. The SINIT signal is enabled
-- b/w every line and b/w every new frame. This value is recommended
-- to be zero to conserver power but it doesn't really matter what
-- it is. In this design it is not connected but feel free to connect
-- it up yourself - everything should work exactly the same.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- SINIT_wire
--
-- Notes:
-- N/A
------------------------------------------------------------------
image_gen_bram_sinit_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
SINIT_wire <= '0';
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
if( CLK_LCD_CYC_NUM >= (C_ENAB_THE - 2) -- start of image... Change from -1 to -2 to enable one clock earlier
and
CLK_LCD_CYC_NUM < (C_IMAGE_WIDTH - 1 + C_ENAB_THE - 1)
and
LINE_NUM < (C_IMAGE_HEIGHT + C_VSYNC_TVS + 1) ) then
SINIT_wire <= '1'; --allow output to change based on ADDR
else
SINIT_wire <= '0';--reset output pins back to user-defined initial value (should be 0h to conserve power)
end if;
end if;
end process image_gen_bram_sinit_cntrl_PROC;
------------------------------------------------------------------
-- Process Description:
-- This process controls the address value input to the BRAMs.
--
-- Inputs:
-- RSTx
-- CLK_LCD
--
-- Outputs:
-- ADDR_wire
--
-- Notes:
-- This process causes the Xilinx BRAM IP cores (instantiated
-- above for each color) to generate warnings saying "Memory
-- address is out of range" during simulation. This is only
-- because ADDR_wire is 76800 for a few clocks after it finishes
-- drawing the last pixel on the screen. The allowable range
-- is only 0 - 76799, but driving 76800 doesn't cause any issues.
-- I could fix it, but I'm too lazy. :-)
------------------------------------------------------------------
image_gen_bram_addr_cntrl_PROC : process( RSTx, CLK_LCD )
begin
if( RSTx = '0' ) then
ADDR_wire <= (others => '0');
elsif( CLK_LCD'event and CLK_LCD = '1' ) then
--this condition signifies the start and end of each line
if( CLK_LCD_CYC_NUM >= (C_ENAB_THE - 1)
and
CLK_LCD_CYC_NUM < (C_IMAGE_WIDTH + C_ENAB_THE - 1)
and
LINE_NUM < (C_IMAGE_HEIGHT + C_VSYNC_TVS + 1) ) then
ADDR_wire <= ADDR_wire + 1;
--reset address back to zero once a complete image has been drawn
--(+ TVS timespec of course). We only have to do this in case the
--number of addressable image data bytes is less than
--2^#BRAM_ADDR_bits (i.e. the number of addressable BRAM bytes).
--This is almost always likely to be the case since the chances of
--Xilinx automatically generating a BRAM block the _exact_ same size
--as your image is highly unlikey. This conditional statement will work
--in either case. :-)
elsif( LINE_NUM >= (C_IMAGE_HEIGHT + C_VSYNC_TVS + 1) ) then
ADDR_wire <= (others => '0');
--if data should not be sent then just wait for the next line before
--incrementing the address again
else
ADDR_wire <= ADDR_wire;
end if; --end data OK TO SEND check
end if; --end CLK'event and CLK = '1'
end process image_gen_bram_addr_cntrl_PROC;
END ARCHITECTURE image_gen_bram_arch;
|
gpl-2.0
|
vira-lytvyn/labsAndOthersNiceThings
|
HardwareAndSoftwareOfNeuralNetworks/Lab_13/Lab_13_3_1/mult.vhd
|
1
|
494
|
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity mult is
generic (k : integer := 4);
port( carryin : in std_logic ;
A, B : in std_logic_vector (k-1 downto 0);
S : out std_logic_vector (k-1 downto 0);
carryout : out std_logic);
end entity mult;
architecture Behave of mult is
signal Sum : std_logic_vector (k downto 0);
begin
Sum <= ( '0' & A) - ( '0' & B) - carryin ;
S <= Sum (k-1 downto 0);
carryout <= Sum(k) ;
end Behave;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_dgen.vhd
|
1
|
4560
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
ENTITY rd_fifo_256to64_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF rd_fifo_256to64_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/bram_DDRs_Control_Loopback.vhd
|
1
|
44671
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bram_DDRs_Control_loopback is
Generic (
C_ASYNFIFO_WIDTH : integer := 72 ;
P_SIMULATION : boolean := TRUE
);
Port (
-- -- Pins
-- DDR_CLKn : OUT std_logic;
-- DDR_CLK : OUT std_logic;
-- DDR_CKE : OUT std_logic;
-- DDR_CSn : OUT std_logic;
-- DDR_RASn : OUT std_logic;
-- DDR_CASn : OUT std_logic;
-- DDR_WEn : OUT std_logic;
-- DDR_BankAddr : OUT std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
-- DDR_Addr : OUT std_logic_vector(C_DDR_AWIDTH-1 downto 0);
-- DDR_DM : OUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DDR_DQ : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
-- DDR_DQS : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DMA interface
DDR_wr_sof : IN std_logic;
DDR_wr_eof : IN std_logic;
DDR_wr_v : IN std_logic;
DDR_wr_FA : IN std_logic;
DDR_wr_Shift : IN std_logic;
DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : OUT std_logic;
DDR_rdc_sof : IN std_logic;
DDR_rdc_eof : IN std_logic;
DDR_rdc_v : IN std_logic;
DDR_rdc_FA : IN std_logic;
DDR_rdc_Shift : IN std_logic;
DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : OUT std_logic;
-- DDR_rdD_sof : OUT std_logic;
-- DDR_rdD_eof : OUT std_logic;
-- DDR_rdDout_V : OUT std_logic;
-- DDR_rdDout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : IN std_logic;
DDR_FIFO_Empty : OUT std_logic;
DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : OUT std_logic;
DDR_blinker : OUT std_logic;
Sim_Zeichen : OUT std_logic;
mem_clk : IN std_logic;
trn_clk : IN std_logic;
trn_reset_n : IN std_logic
);
end entity bram_DDRs_Control_loopback;
architecture Behavioral of bram_DDRs_Control_loopback is
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
COMPONENT DDR_ClkGen
PORT(
ddr_Clock : OUT std_logic;
ddr_Clock_n : OUT std_logic;
ddr_Clock90 : OUT std_logic;
ddr_Clock90_n : OUT std_logic;
Clk_ddr_rddata : OUT std_logic;
Clk_ddr_rddata_n : OUT std_logic;
ddr_DCM_locked : OUT std_logic;
clk_in : IN std_logic;
trn_reset_n : IN std_logic
);
END COMPONENT;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
COMPONENT asyn_rw_FIFO72
-- GENERIC (
-- OUTPUT_REGISTERED : BOOLEAN
-- );
PORT(
wClk : IN std_logic;
wEn : IN std_logic;
Din : IN std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aFull : OUT std_logic;
Full : OUT std_logic;
rClk : IN std_logic;
rEn : IN std_logic;
Qout : OUT std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aEmpty : OUT std_logic;
Empty : OUT std_logic;
Rst : IN std_logic
);
END COMPONENT;
component k7_prime_FIFO_plain
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
full : OUT std_logic;
prog_full: OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
empty : OUT std_logic;
rst : IN std_logic
);
end component;
-- component fifo_512x36_v4_2
-- port (
-- wr_clk : IN std_logic;
-- wr_en : IN std_logic;
-- din : IN std_logic_VECTOR(35 downto 0);
-- prog_full : OUT std_logic;
-- full : OUT std_logic;
--
-- rd_clk : IN std_logic;
-- rd_en : IN std_logic;
-- dout : OUT std_logic_VECTOR(35 downto 0);
-- prog_empty : OUT std_logic;
-- empty : OUT std_logic;
--
-- rst : IN std_logic
-- );
-- end component;
component fifo_512x72_v4_4
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
-- prog_empty : OUT std_logic;
empty : OUT std_logic;
rst : IN std_logic
);
end component;
---- Dual-port block RAM for packets
--- Core output registered
--
-- component v5bram4096x32
-- port (
-- clka : IN std_logic;
-- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- wea : IN std_logic_vector(0 downto 0);
-- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
-- clkb : IN std_logic;
-- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- web : IN std_logic_vector(0 downto 0);
-- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- );
-- end component;
component k7_bram4096x64
port (
clka : IN std_logic;
addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
wea : IN std_logic_vector(7 downto 0);
dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
clkb : IN std_logic;
addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
web : IN std_logic_vector(7 downto 0);
dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- Blinking -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
COMPONENT DDR_Blink
PORT(
DDR_Blinker : OUT std_logic;
DDR_Write : IN std_logic;
DDR_Read : IN std_logic;
DDR_Both : IN std_logic;
ddr_Clock : IN std_logic;
DDr_Rst_n : IN std_logic
);
END COMPONENT;
-- ---------------------------------------------------------------------
signal ddr_DCM_locked : std_logic;
-- -- ---------------------------------------------------------------------
signal Rst_i : std_logic;
-- -- ---------------------------------------------------------------------
signal DDR_Ready_i : std_logic;
-- -- ---------------------------------------------------------------------
signal ddr_Clock : std_logic;
signal ddr_Clock_n : std_logic;
signal ddr_Clock90 : std_logic;
signal ddr_Clock90_n : std_logic;
signal Clk_ddr_rddata : std_logic;
signal Clk_ddr_rddata_n : std_logic;
-- -- -- Write Pipe Channel
signal wpipe_wEn : std_logic;
signal wpipe_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal wpipe_aFull : std_logic;
signal wpipe_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_wr_Cross_Row : std_logic;
signal DDR_wr_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_write_ALC : std_logic_vector(11-1 downto 0);
signal wpipe_rEn : std_logic;
signal wpipe_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal wpipe_aEmpty : std_logic;
signal wpipe_Empty : std_logic;
signal wpipe_Qout_latch : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- -- -- Read Pipe Command Channel
signal rpipec_wEn : std_logic;
signal rpipec_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpipec_aFull : std_logic;
signal rpipec_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_rd_Cross_Row : std_logic;
signal DDR_rdc_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_read_ALC : std_logic_vector(11-1 downto 0);
signal rpipec_rEn : std_logic;
signal rpipec_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpipec_aEmpty : std_logic;
signal rpipec_Empty : std_logic;
-- -- -- Read Pipe Data Channel
signal rpiped_wEn : std_logic;
signal rpiped_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpiped_aFull : std_logic;
signal rpiped_Full : std_logic;
-- signal rpiped_rEn : std_logic;
signal rpiped_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpiped_aEmpty : std_logic;
-- signal rpiped_Empty : std_logic;
-- write State machine
type bram_wrStates is ( wrST_bram_RESET
, wrST_bram_IDLE
-- , wrST_bram_Address
, wrST_bram_1st_Data
, wrST_bram_1st_Data_b2b
, wrST_bram_more_Data
, wrST_bram_last_DW
);
-- State variables
signal pseudo_DDR_wr_State : bram_wrStates;
-- Block RAM
signal pRAM_weA : std_logic_vector(7 downto 0);
signal pRAM_addrA : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_weB : std_logic_vector(7 downto 0);
signal pRAM_addrB : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_shifted : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wpipe_qout_lo32b : std_logic_vector(33-1 downto 0);
signal wpipe_QW_Aligned : std_logic;
signal pRAM_AddrA_Inc : std_logic;
signal wpipe_read_valid : std_logic;
-- read State machine
type bram_rdStates is ( rdST_bram_RESET
, rdST_bram_IDLE
, rdST_bram_b4_LA
, rdST_bram_LA
-- , rdST_bram_b4_Length
-- , rdST_bram_Length
-- , rdST_bram_b4_Address
-- , rdST_bram_Address
, rdST_bram_Data
-- , rdST_bram_Data_shift
);
-- State variables
signal pseudo_DDR_rd_State : bram_rdStates;
signal rpiped_rd_counter : std_logic_vector(10-1 downto 0);
signal rpiped_wEn_b3 : std_logic;
signal rpiped_wEn_b2 : std_logic;
signal rpiped_wEn_b1 : std_logic;
signal rpiped_wr_EOF : std_logic;
signal rpipec_read_valid : std_logic;
signal rpiped_wr_skew : std_logic;
signal rpiped_wr_postpone : std_logic;
signal simone_debug : std_logic;
begin
Rst_i <= not trn_reset_n;
DDR_Ready <= DDR_Ready_i;
pRAM_doutB_shifted <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
-- Delay
Syn_Shifting_pRAM_doutB:
process ( trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
pRAM_doutB_r1 <= pRAM_doutB;
end if;
end process;
-- -----------------------------------------------
--
Syn_DDR_CKE:
process (trn_clk, Rst_i)
begin
if Rst_i = '1' then
DDR_Ready_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
DDR_Ready_i <= '1'; -- ddr_DCM_locked;
end if;
end process;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_Clock_Generator:
-- DDR_ClkGen
-- PORT MAP(
-- ddr_Clock => ddr_Clock , -- OUT std_logic;
-- ddr_Clock_n => ddr_Clock_n , -- OUT std_logic;
-- ddr_Clock90 => ddr_Clock90 , -- OUT std_logic;
-- ddr_Clock90_n => ddr_Clock90_n , -- OUT std_logic;
-- Clk_ddr_rddata => Clk_ddr_rddata , -- OUT std_logic;
-- Clk_ddr_rddata_n => Clk_ddr_rddata_n , -- OUT std_logic;
-- ddr_DCM_locked => ddr_DCM_locked , -- OUT std_logic;
--
-- clk_in => mem_clk , -- IN std_logic;
-- trn_reset_n => trn_reset_n -- IN std_logic
-- );
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => wpipe_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => wpipe_aEmpty ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => open ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_write_fifo:
k7_prime_fifo_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => wpipe_wEn , -- IN std_logic;
din => wpipe_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => wpipe_aFull , -- OUT std_logic;
full => wpipe_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => wpipe_rEn , -- IN std_logic;
dout => wpipe_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => wpipe_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
wpipe_wEn <= DDR_wr_v;
wpipe_Din <= DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
DDR_wr_full <= wpipe_aFull;
Sim_Zeichen <= simone_debug; --S wpipe_Empty;
Syn_DDR_wrD_Cross_Row:
process (trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
DDR_wr_din_r1(64-1 downto 10) <= (OTHERS=>'0');
DDR_wr_din_r1( 9 downto 0) <= DDR_wr_din(9 downto 0) - "100";
end if;
end process;
DDR_write_ALC <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
DDR_wr_Cross_Row <= '0'; -- DDR_write_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => rpipec_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => rpipec_aEmpty ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
--
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => open ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_C_fifo:
k7_prime_fifo_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => rpipec_wEn , -- IN std_logic;
din => rpipec_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpipec_aFull , -- OUT std_logic;
full => open, --rpipec_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => rpipec_rEn , -- IN std_logic;
dout => rpipec_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => rpipec_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
rpipec_wEn <= DDR_rdc_v;
rpipec_Din <= "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
DDR_rdc_full <= rpipec_aFull;
Syn_DDR_rdC_Cross_Row:
process (trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
DDR_rdc_din_r1(64-1 downto 10) <= (OTHERS=>'0');
DDR_rdc_din_r1( 9 downto 0) <= DDR_rdc_din(9 downto 0) - "100";
end if;
end process;
DDR_read_ALC <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
DDR_rd_Cross_Row <= '0'; -- DDR_read_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => ddr_Clock, -- Clk_ddr_rddata , -- ddr_Clock , -- ddr_Clock_n ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => rpiped_Full ,
--
-- rClk => trn_clk ,
-- rEn => DDR_FIFO_RdEn , -- rpiped_rEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open , -- rpiped_aEmpty ,
-- Empty => DDR_FIFO_Empty , -- rpiped_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => ddr_Clock ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => open ,
--
-- rClk => trn_clk ,
-- rEn => DDR_FIFO_RdEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open ,
-- Empty => DDR_FIFO_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_D_fifo:
k7_prime_fifo_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => rpiped_wEn , -- IN std_logic;
din => rpiped_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpiped_aFull , -- OUT std_logic;
full => open, -- rpiped_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => DDR_FIFO_RdEn , -- IN std_logic;
dout => rpiped_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => DDR_FIFO_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
DDR_FIFO_RdQout <= rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
-- -------------------------------------------------
-- pkt_RAM instantiate
--
pkt_RAM:
k7_bram4096x64
port map (
clka => trn_clk ,
addra => pRAM_addrA ,
wea => pRAM_weA ,
dina => pRAM_dinA ,
douta => pRAM_doutA ,
clkb => trn_clk ,
addrb => pRAM_addrB ,
web => pRAM_weB ,
dinb => pRAM_dinB ,
doutb => pRAM_doutB
);
pRAM_weB <= X"00";
pRAM_dinB <= (Others =>'0');
-- ------------------------------------------------
-- write States synchronous
--
Syn_Pseudo_DDR_wr_States:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (OTHERS=>'1');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
wpipe_qout_lo32b <= (OTHERS=>'0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
elsif trn_clk'event and trn_clk = '1' then
case pseudo_DDR_wr_State is
when wrST_bram_RESET =>
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_addrA <= (OTHERS=>'1');
wpipe_QW_Aligned <= '1';
wpipe_qout_lo32b <= (OTHERS=>'0');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
pRAM_AddrA_Inc <= '1';
when wrST_bram_IDLE =>
pRAM_addrA <= wpipe_Qout(14 downto 3);
pRAM_AddrA_Inc <= wpipe_Qout(2);
wpipe_QW_Aligned <= not wpipe_Qout(69);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= pRAM_dinA;
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data; -- wrST_bram_Address;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
end if;
when wrST_bram_1st_Data =>
pRAM_addrA <= pRAM_addrA;
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
elsif wpipe_Qout(71)='1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif pRAM_AddrA_Inc='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_more_Data =>
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_more_Data; -- wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_addrA <= pRAM_addrA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_last_DW =>
-- pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data_b2b; -- wrST_bram_Address;
wpipe_Qout_latch <= wpipe_Qout;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
wpipe_Qout_latch <= wpipe_Qout;
end if;
when wrST_bram_1st_Data_b2b =>
pRAM_addrA <= wpipe_Qout_latch(14 downto 3);
wpipe_QW_Aligned <= not wpipe_Qout_latch(69);
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(71)='1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout_latch(2)='1' then -- pRAM_AddrA_Inc
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when OTHERS =>
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (OTHERS=>'1');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
wpipe_qout_lo32b <= (OTHERS=>'0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
end case;
end if;
end process;
--
Syn_wPipe_read:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
wpipe_rEn <= '0';
wpipe_read_valid <= '0';
elsif trn_clk'event and trn_clk = '1' then
wpipe_rEn <= '1';
wpipe_read_valid <= wpipe_rEn and not wpipe_Empty;
end if;
end process;
--
Syn_rPipeC_read:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpipec_read_valid <= '0';
rpiped_wr_postpone <= '0';
rpiped_wr_skew <= '0';
elsif trn_clk'event and trn_clk = '1' then
rpipec_read_valid <= rpipec_rEn and not rpipec_Empty;
if rpipec_read_valid='1' then
rpiped_wr_postpone <= rpipec_Qout(2) and not rpipec_Qout(69);
rpiped_wr_skew <= rpipec_Qout(69) xor rpipec_Qout(2);
else
rpiped_wr_postpone <= rpiped_wr_postpone;
rpiped_wr_skew <= rpiped_wr_skew;
end if;
end if;
end process;
-- ------------------------------------------------
-- Read States synchronous
--
Syn_Pseudo_DDR_rd_States:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
pseudo_DDR_rd_State <= rdST_bram_RESET;
rpipec_rEn <= '0';
pRAM_addrB <= (OTHERS=>'1');
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
elsif trn_clk'event and trn_clk = '1' then
case pseudo_DDR_rd_State is
when rdST_bram_RESET =>
pseudo_DDR_rd_State <= rdST_bram_IDLE;
rpipec_rEn <= '0';
pRAM_addrB <= (OTHERS=>'1');
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
when rdST_bram_IDLE =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
if rpipec_Empty = '0' then
rpipec_rEn <= '1';
pseudo_DDR_rd_State <= rdST_bram_b4_LA; --rdST_bram_b4_Length;
else
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
end if;
when rdST_bram_b4_LA =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_LA;
when rdST_bram_LA =>
rpipec_rEn <= '0';
pRAM_addrB <= rpipec_Qout(14 downto 3);
rpiped_wr_EOF <= '0';
rpiped_wEn_b3 <= '0';
if rpipec_Qout(2+32)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + '1';
elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
else
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
end if;
-- elsif rpipec_Qout(2)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- elsif rpipec_Qout(69)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- else
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
-- end if;
pseudo_DDR_rd_State <= rdST_bram_Data;
when rdST_bram_Data =>
rpipec_rEn <= '0';
if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '1';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
elsif rpiped_aFull = '1' then
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
else
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter - "10";
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
end if;
when OTHERS =>
rpipec_rEn <= '0';
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_RESET;
end case;
end if;
end process;
Syn_Pseudo_DDR_rdd_write:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpiped_wEn_b1 <= '0';
rpiped_wEn_b2 <= '0';
rpiped_wEn <= '0';
rpiped_Din <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
rpiped_wEn_b2 <= rpiped_wEn_b3;
rpiped_wEn_b1 <= rpiped_wEn_b2;
if rpiped_wr_skew='1' then
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
else
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
end if;
end if;
end process;
--
DDR_Blinker_Module:
DDR_Blink
PORT MAP(
DDR_Blinker => DDR_Blinker ,
DDR_Write => wpipe_rEn ,
DDR_Read => rpiped_wEn ,
DDR_Both => '0' ,
ddr_Clock => trn_clk ,
DDr_Rst_n => DDR_Ready_i -- DDR_CKE_i
);
end architecture Behavioral;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_tb.vhd
|
1
|
6155
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_tb IS
END ENTITY;
ARCHITECTURE k7_prime_fifo_plain_arch OF k7_prime_fifo_plain_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from k7_prime_fifo_plain_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of k7_prime_fifo_plain_synth
k7_prime_fifo_plain_synth_inst:k7_prime_fifo_plain_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 77
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_rng.vhd
|
1
|
3941
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY k7_eb_fifo_counted_resized_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF k7_eb_fifo_counted_resized_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/simulation/random.vhd
|
101
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/simulation/k7_bram4096x64_synth.vhd
|
1
|
10410
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_bram4096x64_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY k7_bram4096x64_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE k7_bram4096x64_synth_ARCH OF k7_bram4096x64_synth IS
COMPONENT k7_bram4096x64_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: k7_bram4096x64_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
gpl-2.0
|
esar/hdmilight-v1
|
fpga/avr/opc_deco.vhd
|
2
|
29554
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: opc_deco - Behavioral
-- Create Date: 16:05:16 10/29/2009
-- Description: the opcode decoder of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.common.ALL;
entity opc_deco is
port ( I_CLK : in std_logic;
I_OPC : in std_logic_vector(31 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_T0 : in std_logic;
Q_ALU_OP : out std_logic_vector( 4 downto 0);
Q_AMOD : out std_logic_vector( 5 downto 0);
Q_BIT : out std_logic_vector( 3 downto 0);
Q_DDDDD : out std_logic_vector( 4 downto 0);
Q_IMM : out std_logic_vector(15 downto 0);
Q_JADR : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PC_OP : out std_logic_vector( 2 downto 0);
Q_PMS : out std_logic; -- program memory select
Q_RD_M : out std_logic;
Q_RRRRR : out std_logic_vector( 4 downto 0);
Q_RSEL : out std_logic_vector( 1 downto 0);
Q_WE_01 : out std_logic;
Q_WE_D : out std_logic_vector( 1 downto 0);
Q_WE_F : out std_logic;
Q_WE_M : out std_logic_vector( 1 downto 0);
Q_WE_XYZS : out std_logic);
end opc_deco;
architecture Behavioral of opc_deco is
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
--
-- set the most common settings as default.
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_AMOD <= AMOD_ABS;
Q_BIT <= I_OPC(10) & I_OPC(2 downto 0);
Q_DDDDD <= I_OPC(8 downto 4);
Q_IMM <= X"0000";
Q_JADR <= I_OPC(31 downto 16);
Q_OPC <= I_OPC(15 downto 0);
Q_PC <= I_PC;
Q_PC_OP <= PC_NEXT;
Q_PMS <= '0';
Q_RD_M <= '0';
Q_RRRRR <= I_OPC(9) & I_OPC(3 downto 0);
Q_RSEL <= RS_REG;
Q_WE_D <= "00";
Q_WE_01 <= '0';
Q_WE_F <= '0';
Q_WE_M <= "00";
Q_WE_XYZS <= '0';
case I_OPC(15 downto 10) is
when "000000" => -- 0000 00xx xxxx xxxx
case I_OPC(9 downto 8) is
when "00" =>
--
-- 0000 0000 0000 0000 - NOP
-- 0000 0000 001v vvvv - INTERRUPT
--
if (I_OPC(5)) = '1' then -- interrupt
Q_ALU_OP <= ALU_INTR;
Q_AMOD <= AMOD_SPdd;
Q_JADR <= "0000000000" & I_OPC(4 downto 0) & "0";
Q_PC_OP <= PC_LD_I;
Q_WE_F <= '1'; -- clear I-flag
Q_WE_M <= "11"; -- write return address
Q_WE_XYZS <= '1'; -- write new SP
end if;
when "01" =>
--
-- 0000 0001 dddd rrrr - MOVW
--
Q_DDDDD <= I_OPC(7 downto 4) & "0";
Q_RRRRR <= I_OPC(3 downto 0) & "0";
Q_ALU_OP <= ALU_MV_16;
Q_WE_D <= "11";
when "10" =>
--
-- 0000 0010 dddd rrrr - MULS
--
Q_DDDDD <= "1" & I_OPC(7 downto 4);
Q_RRRRR <= "1" & I_OPC(3 downto 0);
Q_ALU_OP <= ALU_MULT;
Q_IMM(7 downto 5) <= MULT_SS;
Q_WE_01 <= '1';
Q_WE_F <= '1';
when others =>
--
-- 0000 0011 0ddd 0rrr - _MULSU SU "010"
-- 0000 0011 0ddd 1rrr - FMUL UU "100"
-- 0000 0011 1ddd 0rrr - FMULS SS "111"
-- 0000 0011 1ddd 1rrr - FMULSU SU "110"
--
Q_DDDDD(4 downto 3) <= "10"; -- regs 16 to 23
Q_RRRRR(4 downto 3) <= "10"; -- regs 16 to 23
Q_ALU_OP <= ALU_MULT;
if I_OPC(7) = '0' then
if I_OPC(3) = '0' then
Q_IMM(7 downto 5) <= MULT_SU;
else
Q_IMM(7 downto 5) <= MULT_FUU;
end if;
else
if I_OPC(3) = '0' then
Q_IMM(7 downto 5) <= MULT_FSS;
else
Q_IMM(7 downto 5) <= MULT_FSU;
end if;
end if;
Q_WE_01 <= '1';
Q_WE_F <= '1';
end case;
when "000001" | "000010" =>
--
-- 0000 01rd dddd rrrr - CPC = SBC without Q_WE_D
-- 0000 10rd dddd rrrr - SBC
--
Q_ALU_OP <= ALU_SBC;
Q_WE_D <= '0' & I_OPC(11); -- write Rd if SBC.
Q_WE_F <= '1';
when "000011" => -- 0000 11xx xxxx xxxx
--
-- 0000 11rd dddd rrrr - ADD
--
Q_ALU_OP <= ALU_ADD;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "000100" => -- 0001 00xx xxxx xxxx
--
-- 0001 00rd dddd rrrr - CPSE
--
Q_ALU_OP <= ALU_SUB;
if (I_T0 = '0') then -- second cycle.
Q_PC_OP <= PC_SKIP_Z;
end if;
when "000101" | "000110" =>
--
-- 0001 01rd dddd rrrr - CP = SUB without Q_WE_D
-- 0000 10rd dddd rrrr - SUB
--
Q_ALU_OP <= ALU_SUB;
Q_WE_D <= '0' & I_OPC(11); -- write Rd if SUB.
Q_WE_F <= '1';
when "000111" => -- 0001 11xx xxxx xxxx
--
-- 0001 11rd dddd rrrr - ADC
--
Q_ALU_OP <= ALU_ADC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001000" => -- 0010 00xx xxxx xxxx
--
-- 0010 00rd dddd rrrr - AND
--
Q_ALU_OP <= ALU_AND;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001001" => -- 0010 01xx xxxx xxxx
--
-- 0010 01rd dddd rrrr - EOR
--
Q_ALU_OP <= ALU_EOR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001010" => -- 0010 10xx xxxx xxxx
--
-- 0010 10rd dddd rrrr - OR
--
Q_ALU_OP <= ALU_OR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001011" => -- 0010 11xx xxxx xxxx
--
-- 0010 11rd dddd rrrr - MOV
--
Q_ALU_OP <= ALU_R_MV_Q;
Q_WE_D <= "01";
when "001100" | "001101" | "001110" | "001111"
| "010100" | "010101" | "010110" | "010111" =>
--
-- 0011 KKKK dddd KKKK - CPI
-- 0101 KKKK dddd KKKK - SUBI
--
Q_ALU_OP <= ALU_SUB;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= '0' & I_OPC(14);
Q_WE_F <= '1';
when "010000" | "010001" | "010010" | "010011" =>
--
-- 0100 KKKK dddd KKKK - SBCI
--
Q_ALU_OP <= ALU_SBC;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "011000" | "011001" | "011010" | "011011" =>
--
-- 0110 KKKK dddd KKKK - ORI
--
Q_ALU_OP <= ALU_OR;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "011100" | "011101" | "011110" | "011111" =>
--
-- 0111 KKKK dddd KKKK - ANDI
--
Q_ALU_OP <= ALU_AND;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "100000" | "100001" | "100010" | "100011"
| "101000" | "101001" | "101010" | "101011" =>
--
-- LDD (Y + q) == LD (y) if q == 0
--
-- 10q0 qq0d dddd 1qqq LDD (Y + q)
-- 10q0 qq0d dddd 0qqq LDD (Z + q)
-- 10q0 qq1d dddd 1qqq SDD (Y + q)
-- 10q0 qq1d dddd 0qqq SDD (Z + q)
-- L/ Z/
-- S Y
--
Q_IMM(5) <= I_OPC(13);
Q_IMM(4 downto 3) <= I_OPC(11 downto 10);
Q_IMM(2 downto 0) <= I_OPC( 2 downto 0);
if (I_OPC(3) = '0') then Q_AMOD <= AMOD_Zq;
else Q_AMOD <= AMOD_Yq;
end if;
if (I_OPC(9) = '0') then -- LDD
Q_RSEL <= RS_DIN;
Q_RD_M <= I_T0;
Q_WE_D <= '0' & not I_T0;
else -- STD
Q_WE_M <= '0' & I_OPC(9);
end if;
when "100100" => -- 1001 00xx xxxx xxxx
Q_IMM <= I_OPC(31 downto 16); -- absolute address for LDS/STS
if (I_OPC(9) = '0') then -- LDD / POP
--
-- 1001 00-0d dddd 0000 - LDS
-- 1001 00-0d dddd 0001 - LD Rd, Z+
-- 1001 00-0d dddd 0010 - LD Rd, -Z
-- 1001 00-0d dddd 0100 - LPM Rd, (Z) (ii)
-- 1001 00-0d dddd 0101 - LPM Rd, (Z+) (iii)
-- 1001 00-0d dddd 0110 - ELPM Z --- not mega8
-- 1001 00-0d dddd 0111 - ELPM Z+ --- not mega8
-- 1001 00-0d dddd 1001 - LD Rd, Y+
-- 1001 00-0d dddd 1010 - LD Rd, -Y
-- 1001 00-0d dddd 1100 - LD Rd, X
-- 1001 00-0d dddd 1101 - LD Rd, X+
-- 1001 00-0d dddd 1110 - LD Rd, -X
-- 1001 00-0d dddd 1111 - POP Rd
--
Q_RSEL <= RS_DIN;
Q_RD_M <= I_T0;
Q_WE_D <= '0' & not I_T0;
Q_WE_XYZS <= not I_T0;
Q_PMS <= (not I_OPC(3)) and I_OPC(2) and (not I_OPC(1));
case I_OPC(3 downto 0) is
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
when "0001" => Q_AMOD <= AMOD_Zi;
when "0100" => Q_AMOD <= AMOD_Z; Q_WE_XYZS <= '0';
when "0101" => Q_AMOD <= AMOD_Zi;
when "1001" => Q_AMOD <= AMOD_Yi;
when "1010" => Q_AMOD <= AMOD_dY;
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_iSP;
when others => Q_WE_XYZS <= '0';
end case;
else -- STD / PUSH
--
-- 1001 00-1r rrrr 0000 - STS
-- 1001 00-1r rrrr 0001 - ST Z+. Rr
-- 1001 00-1r rrrr 0010 - ST -Z. Rr
-- 1001 00-1r rrrr 1000 - ST Y. Rr
-- 1001 00-1r rrrr 1001 - ST Y+. Rr
-- 1001 00-1r rrrr 1010 - ST -Y. Rr
-- 1001 00-1r rrrr 1100 - ST X. Rr
-- 1001 00-1r rrrr 1101 - ST X+. Rr
-- 1001 00-1r rrrr 1110 - ST -X. Rr
-- 1001 00-1r rrrr 1111 - PUSH Rr
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_WE_M <= "01";
Q_WE_XYZS <= '1';
case I_OPC(3 downto 0) is
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
when "0001" => Q_AMOD <= AMOD_Zi;
when "0010" => Q_AMOD <= AMOD_dZ;
when "1001" => Q_AMOD <= AMOD_Yi;
when "1010" => Q_AMOD <= AMOD_dY;
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_SPd;
when others =>
end case;
end if;
when "100101" => -- 1001 01xx xxxx xxxx
if (I_OPC(9) = '0') then -- 1001 010
case I_OPC(3 downto 0) is
when "0000" =>
--
-- 1001 010d dddd 0000 - COM Rd
--
Q_ALU_OP <= ALU_COM;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0001" =>
--
-- 1001 010d dddd 0001 - NEG Rd
--
Q_ALU_OP <= ALU_NEG;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0010" =>
--
-- 1001 010d dddd 0010 - SWAP Rd
--
Q_ALU_OP <= ALU_SWAP;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0011" =>
--
-- 1001 010d dddd 0011 - INC Rd
--
Q_ALU_OP <= ALU_INC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0101" =>
--
-- 1001 010d dddd 0101 - ASR Rd
--
Q_ALU_OP <= ALU_ASR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0110" =>
--
-- 1001 010d dddd 0110 - LSR Rd
--
Q_ALU_OP <= ALU_LSR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0111" =>
--
-- 1001 010d dddd 0111 - ROR Rd
--
Q_ALU_OP <= ALU_ROR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "1000" => -- 1001 010x xxxx 1000
if I_OPC(8) = '0' then -- 1001 0100 xxxx 1000
--
-- 1001 0100 0sss 1000 - BSET
-- 1001 0100 1sss 1000 - BCLR
--
Q_BIT(3 downto 0) <= I_OPC(7 downto 4);
Q_ALU_OP <= ALU_SREG;
Q_WE_F <= '1';
else -- 1001 0101 xxxx 1000
--
-- 1001 0101 0000 1000 - RET
-- 1001 0101 0001 1000 - RETI
-- 1001 0101 1000 1000 - SLEEP
-- 1001 0101 1001 1000 - BREAK
-- 1001 0101 1100 1000 - LPM [ R0,(Z) ]
-- 1001 0101 1101 1000 - ELPM not mega8
-- 1001 0101 1110 1000 - SPM
-- 1001 0101 1111 1000 - SPM #2
-- 1001 0101 1010 1000 - WDR
--
case I_OPC(7 downto 4) is
when "0000" => -- RET
Q_AMOD <= AMOD_iiSP;
Q_RD_M <= I_T0;
Q_WE_XYZS <= not I_T0;
if (I_T0 = '0') then
Q_PC_OP <= PC_LD_S;
end if;
when "0001" => -- RETI
Q_ALU_OP <= ALU_INTR;
Q_IMM(6) <= '1';
Q_AMOD <= AMOD_iiSP;
Q_RD_M <= I_T0;
Q_WE_F <= not I_T0; -- I flag
Q_WE_XYZS <= not I_T0;
if (I_T0 = '0') then
Q_PC_OP <= PC_LD_S;
end if;
when "1100" => -- (i) LPM R0, (Z)
Q_DDDDD <= "00000";
Q_AMOD <= AMOD_Z;
Q_PMS <= '1';
Q_WE_D <= '0' & not I_T0;
when "1110" => -- SPM
Q_ALU_OP <= ALU_D_MV_Q;
Q_DDDDD <= "00000";
Q_AMOD <= AMOD_Z;
Q_PMS <= '1';
Q_WE_M <= "01";
when "1111" => -- SPM #2
-- page write: not supported
when others =>
end case;
end if;
when "1001" => -- 1001 010x xxxx 1001
--
-- 1001 0100 0000 1001 IJMP
-- 1001 0100 0001 1001 EIJMP -- not mega8
-- 1001 0101 0000 1001 ICALL
-- 1001 0101 0001 1001 EICALL -- not mega8
--
Q_PC_OP <= PC_LD_Z;
if (I_OPC(8) = '1') then -- ICALL
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_SPdd;
Q_WE_M <= "11";
Q_WE_XYZS <= '1';
end if;
when "1010" => -- 1001 010x xxxx 1010
--
-- 1001 010d dddd 1010 - DEC Rd
--
Q_ALU_OP <= ALU_DEC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "1011" => -- 1001 010x xxxx 1011
--
-- 1001 0100 KKKK 1011 - DES -- not mega8
--
when "1100" | "1101" =>
--
-- 1001 010k kkkk 110k - JMP (k = 0 for 16 bit)
-- kkkk kkkk kkkk kkkk
--
Q_PC_OP <= PC_LD_I;
when "1110" | "1111" => -- 1001 010x xxxx 111x
--
-- 1001 010k kkkk 111k - CALL (k = 0)
-- kkkk kkkk kkkk kkkk
--
Q_ALU_OP <= ALU_PC_2;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
when others =>
end case;
else -- 1001 011
--
-- 1001 0110 KKdd KKKK - ADIW
-- 1001 0111 KKdd KKKK - SBIW
--
if (I_OPC(8) = '0') then Q_ALU_OP <= ALU_ADIW;
else Q_ALU_OP <= ALU_SBIW;
end if;
Q_IMM(5 downto 4) <= I_OPC(7 downto 6);
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD <= "11" & I_OPC(5 downto 4) & "0";
Q_WE_D <= "11";
Q_WE_F <= '1';
end if; -- I_OPC(9) = 0/1
when "100110" => -- 1001 10xx xxxx xxxx
--
-- 1001 1000 AAAA Abbb - CBI
-- 1001 1001 AAAA Abbb - SBIC
-- 1001 1010 AAAA Abbb - SBI
-- 1001 1011 AAAA Abbb - SBIS
--
Q_ALU_OP <= ALU_BIT_CS;
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(9); -- set/clear
-- IMM = AAAAAA + 0x20
--
Q_IMM(4 downto 0) <= I_OPC(7 downto 3);
Q_IMM(6 downto 5) <= "01";
Q_RD_M <= I_T0;
if ((I_OPC(8) = '0') ) then -- CBI or SBI
Q_WE_M(0) <= '1';
else -- SBIC or SBIS
if (I_T0 = '0') then -- second cycle.
Q_PC_OP <= PC_SKIP_T;
end if;
end if;
when "100111" => -- 1001 11xx xxxx xxxx
--
-- 1001 11rd dddd rrrr - MUL
--
Q_ALU_OP <= ALU_MULT;
Q_IMM(7 downto 5) <= "000"; -- -MUL UU;
Q_WE_01 <= '1';
Q_WE_F <= '1';
when "101100" | "101101" => -- 1011 0xxx xxxx xxxx
--
-- 1011 0AAd dddd AAAA - IN
--
Q_RSEL <= RS_DIN;
Q_AMOD <= AMOD_ABS;
-- IMM = AAAAAA
-- + 010000 (0x20)
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_IMM(4) <= I_OPC(9);
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
Q_RD_M <= '1';
Q_WE_D <= "01";
when "101110" | "101111" => -- 1011 1xxx xxxx xxxx
--
-- 1011 1AAr rrrr AAAA - OUT
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_AMOD <= AMOD_ABS;
-- IMM = AAAAAA
-- + 010000 (0x20)
--
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_IMM(4) <= I_OPC(9);
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
Q_WE_M <= "01";
when "110000" | "110001" | "110010" | "110011" =>
--
-- 1100 kkkk kkkk kkkk - RJMP
--
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_PC_OP <= PC_LD_I;
when "110100" | "110101" | "110110" | "110111" =>
--
-- 1101 kkkk kkkk kkkk - RCALL
--
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
when "111000" | "111001" | "111010" | "111011" => -- LDI
--
-- 1110 KKKK dddd KKKK - LDI Rd, K
--
Q_ALU_OP <= ALU_R_MV_Q;
Q_RSEL <= RS_IMM;
Q_DDDDD <= '1' & I_OPC(7 downto 4); -- 16..31
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_WE_D <= "01";
when "111100" | "111101" => -- 1111 0xxx xxxx xxxx
--
-- 1111 00kk kkkk kbbb - BRBS
-- 1111 01kk kkkk kbbb - BRBC
-- v
-- bbb: status register bit
-- v: value (set/cleared) of status register bit
--
Q_JADR <= I_PC + (I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
& I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
& I_OPC(9) & I_OPC(9 downto 3)) + X"0001";
Q_PC_OP <= PC_BCC;
when "111110" => -- 1111 10xx xxxx xxxx
--
-- 1111 100d dddd 0bbb - BLD
-- 1111 101d dddd 0bbb - BST
--
if I_OPC(9) = '0' then -- BLD: T flag to register
Q_ALU_OP <= ALU_BLD;
Q_WE_D <= "01";
else -- BST: register to T flag
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(10);
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
Q_ALU_OP <= ALU_BIT_CS;
Q_WE_F <= '1';
end if;
when "111111" => -- 1111 11xx xxxx xxxx
--
-- 1111 110r rrrr 0bbb - SBRC
-- 1111 111r rrrr 0bbb - SBRS
--
-- like SBIC, but and general purpose regs instead of I/O regs.
--
Q_ALU_OP <= ALU_BIT_CS;
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(9); -- set/clear bit
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
if (I_T0 = '0') then
Q_PC_OP <= PC_SKIP_T;
end if;
when others =>
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
v3best/R7Lite
|
R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain.vhd
|
1
|
10367
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_prime_fifo_plain.vhd when simulating
-- the core, k7_prime_fifo_plain. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_prime_fifo_plain IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END k7_prime_fifo_plain;
ARCHITECTURE k7_prime_fifo_plain_a OF k7_prime_fifo_plain IS
-- synthesis translate_off
COMPONENT wrapped_k7_prime_fifo_plain
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_prime_fifo_plain USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 6,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 4,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 5,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 6,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 496,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 495,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 9,
c_rd_depth => 512,
c_rd_freq => 125,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 9,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 125,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_prime_fifo_plain
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
END k7_prime_fifo_plain_a;
|
gpl-2.0
|
titto-thomas/Pipeline_RISC
|
testbench.vhdl
|
2
|
1746
|
----------------------------------------
-- Main Processor - Testbench : IITB-RISC
-- Author : Titto Thomas, Sainath, Anakha
-- Date : 9/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end testbench;
architecture behave of testbench is
component pipeline_RISC is
port (
clock, reset : in std_logic; -- clock and reset signals
InstrData, InstrAddress, DataData, DataAddress : in std_logic_vector(15 downto 0); -- External data and address for programing
mode, InstrWrite, DataWrite : in std_logic -- Program / Execution mode
);
end component;
signal clock, reset, mode, InstrWrite, DataWrite : std_logic := '0';
signal InstrData, InstrAddress, DataData, DataAddress : std_logic_vector(15 downto 0);
begin --behave
DUT : pipeline_RISC port map (clock, reset, InstrData, InstrAddress, DataData, DataAddress, mode, InstrWrite, DataWrite);
clock <= not clock after 5 ns;
Main : process
begin
reset <= '1';
InstrData <= x"42B0";
InstrAddress <= x"0000";
DataData <= x"0000";
DataAddress <= x"0000";
mode <= '1';
DataWrite <= '0';
InstrWrite <= '1';
wait for 10 ns;
InstrData <= x"6200";
InstrAddress <= x"0001";
wait for 10 ns;
InstrData <= x"6254";
InstrAddress <= x"0002";
wait for 10 ns;
InstrWrite <= '0';
DataWrite <= '1';
DataData <= x"0001";
DataAddress <= x"FFF0";
wait for 10 ns;
DataData <= x"ABCD";
DataAddress <= x"0001";
wait for 10 ns;
DataData <= x"EF10";
DataAddress <= x"0002";
wait for 10 ns;
DataData <= x"FFFF";
DataAddress <= x"0003";
wait for 10 ns;
DataWrite <= '0';
reset <= '0';
mode <= '0';
wait ;
end process;
end behave;
|
gpl-2.0
|
Caian/Minesweeper
|
Projeto/bcd7seg.vhd
|
1
|
905
|
---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity bcd7seg is
port( entrada : in std_logic_vector(3 downto 0);
saida : out std_logic_vector(6 downto 0) );
end entity;
architecture logic of bcd7seg is
begin
with entrada select
saida <= not "0111111" when "0000", -- 0
not "0000110" when "0001", -- 1
not "1011011" when "0010", -- 2
not "1001111" when "0011", -- 3
not "1100110" when "0100", -- 4
not "1101101" when "0101", -- 5
not "1111101" when "0110", -- 6
not "0000111" when "0111", -- 7
not "1111111" when "1000", -- 8
not "1100111" when "1001", -- 9
not "0000000" when others; -- apagado
end architecture;
|
gpl-2.0
|
Caian/Minesweeper
|
Projeto/gfx.vhd
|
1
|
6370
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: gfx.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY gfx IS
PORT
(
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gfx;
ARCHITECTURE SYN OF gfx IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./gfx.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 16384,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 14,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../Gfx/gfx.hex"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../Gfx/gfx.hex"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL address[13..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_wave*.jpg FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gfx_syn.v TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
Caian/Minesweeper
|
Projeto/decoder.vhd
|
1
|
986
|
---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity decoder is
port( entrada : in std_logic_vector(10 downto 0);
digito1 : out std_logic_vector(3 downto 0);
digito2 : out std_logic_vector(3 downto 0);
digito3 : out std_logic_vector(3 downto 0)
);
end;
architecture logica of decoder is
signal temp : std_logic_vector(10 downto 0);
begin
temp <= (others => '0') when (to_integer(signed(entrada)) < 0) else entrada;
digito1 <= std_logic_vector(to_unsigned(to_integer(unsigned(temp))/100,4));
digito2 <= std_logic_vector(to_unsigned(((to_integer(unsigned(temp)) rem 100)-(to_integer(unsigned(temp)) rem 10))/10,4));
digito3 <= std_logic_vector(to_unsigned(to_integer(unsigned(temp)) rem 10,4));
end architecture;
|
gpl-2.0
|
diecaptain/kalman_mppt
|
kn_kalman_Vactcapofkplusone.vhd
|
1
|
1674
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kn_kalman_Vactcapofkplusone is
port
( clock : in std_logic;
Vactcapdashofkplusone : in std_logic_vector(31 downto 0);
Vrefofkplusone : in std_logic_vector(31 downto 0);
Kofkplusone : in std_logic_vector(31 downto 0);
Vactcapofkplusone : out std_logic_vector(31 downto 0)
);
end kn_kalman_Vactcapofkplusone;
architecture struct of kn_kalman_Vactcapofkplusone is
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1 : std_logic_vector(31 downto 0);
signal Z2 : std_logic_vector(31 downto 0);
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => Vrefofkplusone, datab => Vactcapdashofkplusone, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => Z1, datab => Kofkplusone, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Vactcapdashofkplusone, datab => Z2, result => Vactcapofkplusone);
end struct;
|
gpl-2.0
|
Caian/Minesweeper
|
Projeto/ram.vhd
|
1
|
11186
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(7 DOWNTO 0);
q_b <= sub_wire1(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "./ram.mif",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 2048,
numwords_b => 2048,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 11,
widthad_b => 11,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../Ram/ram.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../Ram/ram.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL address_a[10..0]
-- Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL address_b[10..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
-- Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
freecores/w11
|
rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd
|
2
|
1721
|
-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
freecores/w11
|
rtl/ibus/ib_sres_or_mon.vhd
|
2
|
3467
|
-- $Id: ib_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_mon - sim
-- Description: ibus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end ib_sres_or_mon;
architecture sim of ib_sres_or_mon is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable ndout : integer := 0;
begin
nack := 0;
nbusy := 0;
ndout := 0;
if IB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_4.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, ib_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
|
gpl-2.0
|
freecores/w11
|
rtl/sys_gen/tst_rlink_cuff/tst_rlink_cuff.vhd
|
1
|
8649
|
-- $Id: tst_rlink_cuff.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_rlink_cuff - syn
-- Description: tester for rlink over cuff
--
-- Dependencies: vlib/rlink/rlink_core8
-- vlib/rlink/rlink_rlbmux
-- vlib/serport/serport_1clock
-- ../tst_rlink/rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/genlib/led_pulse_stretch
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity tst_rlink_cuff is -- tester for rlink over cuff
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
SWI : in slv8; -- hio: switches
BTN : in slv4; -- hio: buttons
LED : out slv8; -- hio: leds
DSP_DAT : out slv16; -- hio: display data
DSP_DP : out slv4; -- hio: display decimal points
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RTS_N : out slbit; -- receive rts (uart view, act.low)
CTS_N : in slbit; -- transmit cts (uart view, act.low)
FX2_RXDATA : in slv8; -- fx2: receiver data out
FX2_RXVAL : in slbit; -- fx2: receiver data valid
FX2_RXHOLD : out slbit; -- fx2: receiver data hold
FX2_TXDATA : out slv8; -- fx2: transmit data in
FX2_TXENA : out slbit; -- fx2: transmit data enable
FX2_TXBUSY : in slbit; -- fx2: transmit busy
FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
);
end tst_rlink_cuff;
architecture syn of tst_rlink_cuff is
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_TX2ENA_L : slbit := '0';
signal FX2_TXENA_L : slbit := '0';
signal FX2_TX2ENA_LED : slbit := '0';
signal FX2_TXENA_LED : slbit := '0';
signal FX2_RXVAL_LED : slbit := '0';
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
begin
RLCORE : rlink_core8
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon)
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLBMUX : rlink_rlbmux
port map (
SEL => SWI(2),
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA_L,
P1_TXBUSY => FX2_TXBUSY
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXSD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_TOP,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
TX2ENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TX2ENA_L,
POUT => FX2_TX2ENA_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TXENA_L,
POUT => FX2_TXENA_LED
);
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_RXVAL,
POUT => FX2_RXVAL_LED
);
proc_clkdiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_clkdiv;
proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED)
begin
DSP_DAT <= SER_MONI.abclkdiv;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
if SWI(2) = '0' then
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
else
DSP_DP(3) <= FX2_TX2BUSY;
DSP_DP(2) <= FX2_TX2ENA_LED;
DSP_DP(1) <= FX2_TXENA_LED;
DSP_DP(0) <= FX2_RXVAL_LED;
end if;
end process proc_hiomux;
RB_MREQ_TOP <= RB_MREQ;
FX2_TX2ENA <= FX2_TX2ENA_L;
FX2_TXENA <= FX2_TXENA_L;
end syn;
|
gpl-2.0
|
freecores/w11
|
rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
|
1
|
4146
|
-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop_s3 - sim
-- Description: Test bench for sys_tst_serloop_s3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop_s3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop_s3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop_s3 is
end tb_tst_serloop_s3;
architecture sim of tb_tst_serloop_s3 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKS : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop_s3
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKS,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-2.0
|
freecores/w11
|
rtl/sys_gen/w11a/nexys3/sys_conf.vhd
|
1
|
4274
|
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2013-10-05 537 1.1.1 use 72 MHz, no closure w/ ISE 14.x for 80 anymore
-- 2013-04-21 509 1.1 add fx2 settings
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432)
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd):
-- div mul clksys read0 read1 write
-- 2 1 50.0 2 2 3
-- 4 3 75.0 4 4 5 (also 70 MHz)
-- 5 4 80.0 5 5 5
-- 20 17 85.0 5 5 6
-- 10 9 90.0 6 6 6 (also 95 MHz)
-- 1 1 100.0 6 6 7
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 25;
constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_memctl_read0delay : positive := 4;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
freecores/w11
|
rtl/bplib/issi/is61lv25616al.vhd
|
2
|
6378
|
-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: is61lv25616al - sim
-- Description: ISSI 61LV25612AL SRAM model
-- Currently a truely minimalistic functional model, without
-- any timing checks. It assumes, that addr/data is stable at
-- the trailing edge of we.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Mode WE_N CE_N OE_N LB_N UB_N D(7:0) D(15:8)
-- Not selected X H X X X high-Z high-Z
-- Output disabled H L H X X high-Z high-Z
-- X L X H H high-Z high-Z
-- Read H L L L H D_out high-Z
-- H L L H L high-Z D_out
-- H L L L L D_out D_out
-- Write L L X L H D_in high-Z
-- L L X H L high-Z D_in
-- L L X L L D_in D_in
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61lv25616al is -- ISSI 61LV25612AL SRAM model
port (
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADDR : in slv18; -- address lines
DATA : inout slv16 -- data lines
);
end is61lv25616al;
architecture sim of is61lv25616al is
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
component is61lv25616al_bank is -- ISSI 61LV25612AL bank
port (
CE : in slbit; -- chip enable (act.high)
OE : in slbit; -- output enable (act.high)
WE : in slbit; -- write enable (act.high)
BE : in slbit; -- byte enable (act.high)
ADDR : in slv18; -- address lines
DATA : inout slv8 -- data lines
);
end component;
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
BANK_L : is61lv25616al_bank port map (
CE => CE,
OE => OE,
WE => WE,
BE => BE_L,
ADDR => ADDR,
DATA => DATA(7 downto 0));
BANK_U : is61lv25616al_bank port map (
CE => CE,
OE => OE,
WE => WE,
BE => BE_U,
ADDR => ADDR,
DATA => DATA(15 downto 8));
end sim;
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61lv25616al_bank is -- ISSI 61LV25612AL bank
port (
CE : in slbit; -- chip enable (act.high)
OE : in slbit; -- output enable (act.high)
WE : in slbit; -- write enable (act.high)
BE : in slbit; -- byte enable (act.high)
ADDR : in slv18; -- address lines
DATA : inout slv8 -- data lines
);
end is61lv25616al_bank;
architecture sim of is61lv25616al_bank is
constant T_rc : time := 10 ns; -- read cycle time (min)
constant T_aa : time := 10 ns; -- address access time (max)
constant T_oha : time := 2 ns; -- output hold time (min)
constant T_ace : time := 10 ns; -- ce access time (max)
constant T_doe : time := 4 ns; -- oe access time (max)
constant T_hzoe : time := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : time := 0 ns; -- oe to low-Z output (min)
constant T_hzce : time := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : time := 3 ns; -- ce to low-Z output (min)
constant T_ba : time := 4 ns; -- lb,ub access time (max)
constant T_hzb : time := 3 ns; -- lb,ub to high-Z output (min=0,max=3)
constant T_lzb : time := 0 ns; -- lb,ub low-Z output (min)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
signal WE_EFF : slbit := '0';
begin
WE_EFF <= CE and WE and BE;
proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;
end process proc_sram;
end sim;
|
gpl-2.0
|
db-electronics/MDFlashCart
|
VHDL/MDHomebrew.vhd
|
1
|
4988
|
--*************************************************************
--
-- $Rev:: 305 $: Revision of last commit
-- $Author:: reneleonrichard $: Author of last commit
-- $Date:: 2014-10-09 20:11:27 -0400 (Thu, 09 Oct 2014) $: Date of last commit
-- $HeadURL: https://subversion.assembla.com/svn/db_repository/trunk/FPGAProjects/SMSCart/src/SMSCart.vhd $
--
--*************************************************************
-- db MD Mapper
-- Copyright 2014 Rene Richard
-- DEVICE : EPM3064ATC100-10
--*************************************************************
-- db MD Mapper supports a face-melting 256 MEGA POWER
--*************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library altera;
use altera.altera_primitives_components.all;
entity MDHomebrew is
generic (
MAPPER_SIZE_g : integer := 6
);
port (
--input from Genesis
ADDRLO_p : in std_logic_vector(2 downto 0); --Address 3,2,1
ADDRHI_p : in std_logic_vector(2 downto 0); --Address 21,20,19
DATA_p : in std_logic_vector(MAPPER_SIZE_g-1 downto 0);
nRST_p : in std_logic;
nTIME_p : in std_logic;
nCE_p : in std_logic;
nLWR_p : in std_logic;
nUWR_p : in std_logic;
nOE_p : in std_logic;
--output to ROM
DIR_p : out std_logic;
nROMCE_p : out std_logic;
--ROM A19 and up
ROMADDR_p : out std_logic_vector(MAPPER_SIZE_g-1 downto 0);
--output to SRAM
nSRAMCE_p : out std_logic;
SRAMWE_p : out std_logic;
nLBS_p : out std_logic;
nUBS_p : out std_logic
);
end entity;
architecture MDHomebrew_a of MDHomebrew is
--Mapper slot registers, fitter will optimize any unused bits
signal romSlot1_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot2_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot3_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot4_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot5_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot6_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal romSlot7_s : std_logic_vector(MAPPER_SIZE_g-1 downto 0);
signal ramEn_s : std_logic;
begin
--what little level conversion I can do is handled here
SRAMWE_p <= '1' when (nLWR_p = '0' or nUWR_p = '0') else '0';
nLBS_p <= '0' when (nLWR_p = '0' or nOE_p = '0') else '1';
nUBS_p <= '0' when (nUWR_p = '0' or nOE_p = '0') else '1';
DIR_p <= '1' when (nOE_p = '0' and nCE_p = '0') else '0';
--drive CE depending on ramEn_s
--RAM, when enabled, appears at 0x200000
chipselects: process ( ADDRHI_p, nCE_p, ramEn_s)
begin
case ADDRHI_p(2) is --Address 21
when '0' =>
nSRAMCE_p <= '1';
nROMCE_p <= nCE_p;
when '1' =>
if ramEn_s = '1' then
nSRAMCE_p <= nCE_p;
nROMCE_p <= '1';
else
nSRAMCE_p <= '1';
nROMCE_p <= nCE_p;
end if;
end case;
end process;
--mapper registers
mappers: process( nRST_p, nTIME_p, ADDRLO_p)
begin
if nRST_p = '0' then
ramEn_s <= '0';
romSlot1_s <= std_logic_vector(to_unsigned(1, romSlot1_s'length));
romSlot2_s <= std_logic_vector(to_unsigned(2, romSlot2_s'length));
romSlot3_s <= std_logic_vector(to_unsigned(3, romSlot3_s'length));
romSlot4_s <= std_logic_vector(to_unsigned(4, romSlot4_s'length));
romSlot5_s <= std_logic_vector(to_unsigned(5, romSlot5_s'length));
romSlot6_s <= std_logic_vector(to_unsigned(6, romSlot6_s'length));
romSlot3_s <= std_logic_vector(to_unsigned(7, romSlot7_s'length));
elsif rising_edge(nTIME_p) then
--no address(0) from genesis, but I append it here for clarity
case (ADDRLO_p & '1') is
when x"1" =>
ramEn_s <= DATA_p(0);
when x"3" =>
romSlot1_s <= DATA_p;
when x"5" =>
romSlot2_s <= DATA_p;
when x"7" =>
romSlot3_s <= DATA_p;
when x"9" =>
romSlot4_s <= DATA_p;
when x"B" =>
romSlot5_s <= DATA_p;
when x"D" =>
romSlot6_s <= DATA_p;
when x"F" =>
romSlot7_s <= DATA_p;
when others =>
null;
end case;
end if;
end process;
--banking select
--only looks at address, this way the address setup and hold times can be respected
banking: process( ADDRHI_p )
begin
ROMADDR_p <= (others=>'0');
if ramEn_s = '0' then
case ADDRHI_p is --address 21,20 and 19
when "000" =>
-- first bank is always from lowest 512K of ROM
ROMADDR_p <= (others=>'0');
when "001" =>
ROMADDR_p <= romSlot1_s;
when "010" =>
ROMADDR_p <= romSlot2_s;
when "011" =>
ROMADDR_p <= romSlot3_s;
when "100" =>
ROMADDR_p <= romSlot4_s;
when "101" =>
ROMADDR_p <= romSlot5_s;
when "110" =>
ROMADDR_p <= romSlot6_s;
when "111" =>
ROMADDR_p <= romSlot7_s;
when others =>
ROMADDR_p <= (others=>'0');
end case;
end if;
end process;
end MDHomebrew_a;
|
gpl-2.0
|
tec499-20142/t02-warmup
|
rtl/HEADER.vhd
|
2
|
995
|
-- +UEFSHDR----------------------------------------------------------------------
-- 2014 UEFS Universidade Estadual de Feira de Santana
-- TEC499-Sistemas Digitais
-- ------------------------------------------------------------------------------
-- TEAM: <Team identification>
-- ------------------------------------------------------------------------------
-- PROJECT: <Project Title>
-- ------------------------------------------------------------------------------
-- FILE NAME : {module_name}
-- KEYWORDS : {keywords}
-- -----------------------------------------------------------------------------
-- PURPOSE: {description}
-- -----------------------------------------------------------------------------
-- REUSE ISSUES
-- Reset Strategy : <asychronous, active in low level reset>
-- Clock Domains : <clock_driver>
-- Instantiations : <modules_id>
-- Synthesizable (y/n) : <y/n>
-- -UEFSHDR----------------------------------------------------------------------
|
gpl-2.0
|
RowdyRajan/GestureGloveCapstone
|
DE2Component.vhd
|
1
|
8616
|
-- This is the top level file for Gesture Control Interface project for Group 2
-- Eric Smith, Chris Chmilar, Rajan Jassal
-- This file is a modified version of the top level file provided in lab 1
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (0 downto 0);
CLOCK_50 : in std_logic;
-- Green leds on board
LEDG : out DE2_LED_GREEN;
-- LCD on board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic
);
end DE2Component;
architecture structure of DE2Component is
-- Declarations (optional)
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic -- WE_N
--character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
--character_lcd_0_external_interface_ON : out std_logic; -- ON
--character_lcd_0_external_interface_BLON : out std_logic; -- BLON
--character_lcd_0_external_interface_EN : out std_logic; -- EN
--character_lcd_0_external_interface_RS : out std_logic; -- RS
--character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N
--character_lcd_0_external_interface_DATA => LCD_DATA,
--character_lcd_0_external_interface_ON => LCD_ON,
--character_lcd_0_external_interface_BLON => LCD_BLON,
--character_lcd_0_external_interface_EN => LCD_EN,
--character_lcd_0_external_interface_RS => LCD_RS,
--character_lcd_0_external_interface_RW => LCD_RW
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
|
gpl-2.0
|
freecores/t400
|
rtl/tech/spartan/t400_por-c.vhd
|
1
|
534
|
-------------------------------------------------------------------------------
-- $Id: t400_por-c.vhd,v 1.1 2006-05-07 01:47:51 arniml Exp $
-------------------------------------------------------------------------------
configuration t400_por_rtl_c0 of t400_por is
for spartan
end for;
end t400_por_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
gpl-2.0
|
freecores/t400
|
syn/t421/ep1c12/rom_t42x.vhd
|
2
|
25960
|
-- This file was generated with hex2rom written by Daniel Wallner
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rom_t42x is
port(
Clk : in std_logic;
A : in std_logic_vector(9 downto 0);
D : out std_logic_vector(7 downto 0)
);
end rom_t42x;
architecture rtl of rom_t42x is
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
case to_integer(unsigned(A)) is
when 000000 => D <= "01000100"; -- 0x0000
when 000001 => D <= "00110011"; -- 0x0001
when 000002 => D <= "01011001"; -- 0x0002
when 000003 => D <= "00110011"; -- 0x0003
when 000004 => D <= "01010110"; -- 0x0004
when 000005 => D <= "01111000"; -- 0x0005
when 000006 => D <= "00111100"; -- 0x0006
when 000007 => D <= "00110011"; -- 0x0007
when 000008 => D <= "00111110"; -- 0x0008
when 000009 => D <= "00000000"; -- 0x0009
when 000010 => D <= "00010010"; -- 0x000A
when 000011 => D <= "01010000"; -- 0x000B
when 000012 => D <= "00110011"; -- 0x000C
when 000013 => D <= "00111110"; -- 0x000D
when 000014 => D <= "00000000"; -- 0x000E
when 000015 => D <= "01010010"; -- 0x000F
when 000016 => D <= "01010000"; -- 0x0010
when 000017 => D <= "00110011"; -- 0x0011
when 000018 => D <= "00111110"; -- 0x0012
when 000019 => D <= "01110111"; -- 0x0013
when 000020 => D <= "00110011"; -- 0x0014
when 000021 => D <= "00111110"; -- 0x0015
when 000022 => D <= "01010000"; -- 0x0016
when 000023 => D <= "00110011"; -- 0x0017
when 000024 => D <= "00111010"; -- 0x0018
when 000025 => D <= "00000000"; -- 0x0019
when 000026 => D <= "01010000"; -- 0x001A
when 000027 => D <= "00110011"; -- 0x001B
when 000028 => D <= "00111010"; -- 0x001C
when 000029 => D <= "01001101"; -- 0x001D
when 000030 => D <= "00110011"; -- 0x001E
when 000031 => D <= "00111010"; -- 0x001F
when 000032 => D <= "01000111"; -- 0x0020
when 000033 => D <= "00110011"; -- 0x0021
when 000034 => D <= "00111010"; -- 0x0022
when 000035 => D <= "01001100"; -- 0x0023
when 000036 => D <= "01000011"; -- 0x0024
when 000037 => D <= "00000101"; -- 0x0025
when 000038 => D <= "01010000"; -- 0x0026
when 000039 => D <= "00110011"; -- 0x0027
when 000040 => D <= "00111010"; -- 0x0028
when 000041 => D <= "00010101"; -- 0x0029
when 000042 => D <= "00100011"; -- 0x002A
when 000043 => D <= "10000000"; -- 0x002B
when 000044 => D <= "01011111"; -- 0x002C
when 000045 => D <= "00100011"; -- 0x002D
when 000046 => D <= "00000000"; -- 0x002E
when 000047 => D <= "00000110"; -- 0x002F
when 000048 => D <= "00110011"; -- 0x0030
when 000049 => D <= "00111010"; -- 0x0031
when 000050 => D <= "00000101"; -- 0x0032
when 000051 => D <= "01001010"; -- 0x0033
when 000052 => D <= "00000111"; -- 0x0034
when 000053 => D <= "00000111"; -- 0x0035
when 000054 => D <= "00110011"; -- 0x0036
when 000055 => D <= "00111110"; -- 0x0037
when 000056 => D <= "01110101"; -- 0x0038
when 000057 => D <= "01001110"; -- 0x0039
when 000058 => D <= "01010011"; -- 0x003A
when 000059 => D <= "00000111"; -- 0x003B
when 000060 => D <= "00110011"; -- 0x003C
when 000061 => D <= "00111010"; -- 0x003D
when 000062 => D <= "00000111"; -- 0x003E
when 000063 => D <= "00100011"; -- 0x003F
when 000064 => D <= "00000000"; -- 0x0040
when 000065 => D <= "00110011"; -- 0x0041
when 000066 => D <= "00111110"; -- 0x0042
when 000067 => D <= "01010100"; -- 0x0043
when 000068 => D <= "00000110"; -- 0x0044
when 000069 => D <= "00110011"; -- 0x0045
when 000070 => D <= "00111010"; -- 0x0046
when 000071 => D <= "00000000"; -- 0x0047
when 000072 => D <= "01000000"; -- 0x0048
when 000073 => D <= "00000010"; -- 0x0049
when 000074 => D <= "00000100"; -- 0x004A
when 000075 => D <= "00100011"; -- 0x004B
when 000076 => D <= "00000000"; -- 0x004C
when 000077 => D <= "01011000"; -- 0x004D
when 000078 => D <= "00100011"; -- 0x004E
when 000079 => D <= "00000000"; -- 0x004F
when 000080 => D <= "00100001"; -- 0x0050
when 000081 => D <= "00110011"; -- 0x0051
when 000082 => D <= "10010010"; -- 0x0052
when 000083 => D <= "00110011"; -- 0x0053
when 000084 => D <= "00111110"; -- 0x0054
when 000085 => D <= "00100001"; -- 0x0055
when 000086 => D <= "00011111"; -- 0x0056
when 000087 => D <= "01000110"; -- 0x0057
when 000088 => D <= "00100001"; -- 0x0058
when 000089 => D <= "01000010"; -- 0x0059
when 000090 => D <= "00100001"; -- 0x005A
when 000091 => D <= "01001011"; -- 0x005B
when 000092 => D <= "00100001"; -- 0x005C
when 000093 => D <= "00100011"; -- 0x005D
when 000094 => D <= "00000000"; -- 0x005E
when 000095 => D <= "00110110"; -- 0x005F
when 000096 => D <= "00100011"; -- 0x0060
when 000097 => D <= "10010001"; -- 0x0061
when 000098 => D <= "00010100"; -- 0x0062
when 000099 => D <= "00110011"; -- 0x0063
when 000100 => D <= "00101010"; -- 0x0064
when 000101 => D <= "00000110"; -- 0x0065
when 000102 => D <= "00000000"; -- 0x0066
when 000103 => D <= "00110000"; -- 0x0067
when 000104 => D <= "00100010"; -- 0x0068
when 000105 => D <= "00100000"; -- 0x0069
when 000106 => D <= "00100011"; -- 0x006A
when 000107 => D <= "00000000"; -- 0x006B
when 000108 => D <= "00000110"; -- 0x006C
when 000109 => D <= "00110011"; -- 0x006D
when 000110 => D <= "00111010"; -- 0x006E
when 000111 => D <= "00000000"; -- 0x006F
when 000112 => D <= "00110000"; -- 0x0070
when 000113 => D <= "00000110"; -- 0x0071
when 000114 => D <= "00110011"; -- 0x0072
when 000115 => D <= "00111010"; -- 0x0073
when 000116 => D <= "00110011"; -- 0x0074
when 000117 => D <= "00111100"; -- 0x0075
when 000118 => D <= "00000111"; -- 0x0076
when 000119 => D <= "00110011"; -- 0x0077
when 000120 => D <= "00101100"; -- 0x0078
when 000121 => D <= "00110011"; -- 0x0079
when 000122 => D <= "00111010"; -- 0x007A
when 000123 => D <= "00100101"; -- 0x007B
when 000124 => D <= "00110011"; -- 0x007C
when 000125 => D <= "00111010"; -- 0x007D
when 000126 => D <= "00110101"; -- 0x007E
when 000127 => D <= "00110011"; -- 0x007F
when 000128 => D <= "00111010"; -- 0x0080
when 000129 => D <= "00110001"; -- 0x0081
when 000130 => D <= "00000110"; -- 0x0082
when 000131 => D <= "00100010"; -- 0x0083
when 000132 => D <= "00100011"; -- 0x0084
when 000133 => D <= "00000000"; -- 0x0085
when 000134 => D <= "00010000"; -- 0x0086
when 000135 => D <= "00100000"; -- 0x0087
when 000136 => D <= "00000110"; -- 0x0088
when 000137 => D <= "00110011"; -- 0x0089
when 000138 => D <= "00111010"; -- 0x008A
when 000139 => D <= "00000000"; -- 0x008B
when 000140 => D <= "01010011"; -- 0x008C
when 000141 => D <= "00000110"; -- 0x008D
when 000142 => D <= "00100010"; -- 0x008E
when 000143 => D <= "00100000"; -- 0x008F
when 000144 => D <= "00000110"; -- 0x0090
when 000145 => D <= "00110011"; -- 0x0091
when 000146 => D <= "00111010"; -- 0x0092
when 000147 => D <= "00110010"; -- 0x0093
when 000148 => D <= "00100000"; -- 0x0094
when 000149 => D <= "00000110"; -- 0x0095
when 000150 => D <= "00110011"; -- 0x0096
when 000151 => D <= "00111010"; -- 0x0097
when 000152 => D <= "00001111"; -- 0x0098
when 000153 => D <= "00011110"; -- 0x0099
when 000154 => D <= "00110011"; -- 0x009A
when 000155 => D <= "10100111"; -- 0x009B
when 000156 => D <= "00110011"; -- 0x009C
when 000157 => D <= "00111010"; -- 0x009D
when 000158 => D <= "00110011"; -- 0x009E
when 000159 => D <= "00101100"; -- 0x009F
when 000160 => D <= "00110011"; -- 0x00A0
when 000161 => D <= "00111010"; -- 0x00A1
when 000162 => D <= "00000110"; -- 0x00A2
when 000163 => D <= "00110011"; -- 0x00A3
when 000164 => D <= "00111010"; -- 0x00A4
when 000165 => D <= "00110011"; -- 0x00A5
when 000166 => D <= "01100001"; -- 0x00A6
when 000167 => D <= "01001111"; -- 0x00A7
when 000168 => D <= "00000000"; -- 0x00A8
when 000169 => D <= "01010111"; -- 0x00A9
when 000170 => D <= "00110011"; -- 0x00AA
when 000171 => D <= "00000001"; -- 0x00AB
when 000172 => D <= "00000110"; -- 0x00AC
when 000173 => D <= "00110011"; -- 0x00AD
when 000174 => D <= "00111010"; -- 0x00AE
when 000175 => D <= "00110011"; -- 0x00AF
when 000176 => D <= "00010001"; -- 0x00B0
when 000177 => D <= "00000110"; -- 0x00B1
when 000178 => D <= "00110011"; -- 0x00B2
when 000179 => D <= "00111010"; -- 0x00B3
when 000180 => D <= "00110011"; -- 0x00B4
when 000181 => D <= "00000011"; -- 0x00B5
when 000182 => D <= "00000110"; -- 0x00B6
when 000183 => D <= "00110011"; -- 0x00B7
when 000184 => D <= "00111010"; -- 0x00B8
when 000185 => D <= "00110011"; -- 0x00B9
when 000186 => D <= "00010011"; -- 0x00BA
when 000187 => D <= "00000110"; -- 0x00BB
when 000188 => D <= "00110011"; -- 0x00BC
when 000189 => D <= "00111010"; -- 0x00BD
when 000190 => D <= "00110011"; -- 0x00BE
when 000191 => D <= "00100001"; -- 0x00BF
when 000192 => D <= "00000110"; -- 0x00C0
when 000193 => D <= "00110011"; -- 0x00C1
when 000194 => D <= "00111010"; -- 0x00C2
when 000195 => D <= "00110011"; -- 0x00C3
when 000196 => D <= "01010000"; -- 0x00C4
when 000197 => D <= "00110011"; -- 0x00C5
when 000198 => D <= "00100001"; -- 0x00C6
when 000199 => D <= "00000110"; -- 0x00C7
when 000200 => D <= "00110011"; -- 0x00C8
when 000201 => D <= "00111010"; -- 0x00C9
when 000202 => D <= "00000001"; -- 0x00CA
when 000203 => D <= "00000110"; -- 0x00CB
when 000204 => D <= "00110011"; -- 0x00CC
when 000205 => D <= "00111010"; -- 0x00CD
when 000206 => D <= "00010001"; -- 0x00CE
when 000207 => D <= "00000110"; -- 0x00CF
when 000208 => D <= "00110011"; -- 0x00D0
when 000209 => D <= "00111010"; -- 0x00D1
when 000210 => D <= "00000011"; -- 0x00D2
when 000211 => D <= "00000110"; -- 0x00D3
when 000212 => D <= "00110011"; -- 0x00D4
when 000213 => D <= "00111010"; -- 0x00D5
when 000214 => D <= "00110011"; -- 0x00D6
when 000215 => D <= "00101001"; -- 0x00D7
when 000216 => D <= "00110011"; -- 0x00D8
when 000217 => D <= "00101000"; -- 0x00D9
when 000218 => D <= "00100001"; -- 0x00DA
when 000219 => D <= "00010110"; -- 0x00DB
when 000220 => D <= "00110011"; -- 0x00DC
when 000221 => D <= "00111010"; -- 0x00DD
when 000222 => D <= "00110011"; -- 0x00DE
when 000223 => D <= "00101001"; -- 0x00DF
when 000224 => D <= "00000110"; -- 0x00E0
when 000225 => D <= "00010011"; -- 0x00E1
when 000226 => D <= "00110011"; -- 0x00E2
when 000227 => D <= "00111110"; -- 0x00E3
when 000228 => D <= "00110011"; -- 0x00E4
when 000229 => D <= "01010001"; -- 0x00E5
when 000230 => D <= "00111010"; -- 0x00E6
when 000231 => D <= "00110011"; -- 0x00E7
when 000232 => D <= "01010000"; -- 0x00E8
when 000233 => D <= "01000100"; -- 0x00E9
when 000234 => D <= "00110011"; -- 0x00EA
when 000235 => D <= "00101001"; -- 0x00EB
when 000236 => D <= "00000110"; -- 0x00EC
when 000237 => D <= "00000001"; -- 0x00ED
when 000238 => D <= "00110011"; -- 0x00EE
when 000239 => D <= "00111110"; -- 0x00EF
when 000240 => D <= "01000100"; -- 0x00F0
when 000241 => D <= "01001111"; -- 0x00F1
when 000242 => D <= "00000110"; -- 0x00F2
when 000243 => D <= "00110011"; -- 0x00F3
when 000244 => D <= "00111010"; -- 0x00F4
when 000245 => D <= "00001111"; -- 0x00F5
when 000246 => D <= "01110111"; -- 0x00F6
when 000247 => D <= "01111110"; -- 0x00F7
when 000248 => D <= "01110101"; -- 0x00F8
when 000249 => D <= "01111100"; -- 0x00F9
when 000250 => D <= "01110011"; -- 0x00FA
when 000251 => D <= "01111010"; -- 0x00FB
when 000252 => D <= "01110001"; -- 0x00FC
when 000253 => D <= "01111000"; -- 0x00FD
when 000254 => D <= "01111111"; -- 0x00FE
when 000255 => D <= "01110110"; -- 0x00FF
when 000256 => D <= "01111101"; -- 0x0100
when 000257 => D <= "01110100"; -- 0x0101
when 000258 => D <= "01111011"; -- 0x0102
when 000259 => D <= "01110010"; -- 0x0103
when 000260 => D <= "01111001"; -- 0x0104
when 000261 => D <= "01110000"; -- 0x0105
when 000262 => D <= "00011111"; -- 0x0106
when 000263 => D <= "01110111"; -- 0x0107
when 000264 => D <= "01111110"; -- 0x0108
when 000265 => D <= "01110101"; -- 0x0109
when 000266 => D <= "01111100"; -- 0x010A
when 000267 => D <= "01110011"; -- 0x010B
when 000268 => D <= "01111010"; -- 0x010C
when 000269 => D <= "01110001"; -- 0x010D
when 000270 => D <= "01111000"; -- 0x010E
when 000271 => D <= "01111111"; -- 0x010F
when 000272 => D <= "01110110"; -- 0x0110
when 000273 => D <= "01111101"; -- 0x0111
when 000274 => D <= "01110100"; -- 0x0112
when 000275 => D <= "01111011"; -- 0x0113
when 000276 => D <= "01110010"; -- 0x0114
when 000277 => D <= "01111001"; -- 0x0115
when 000278 => D <= "01110000"; -- 0x0116
when 000279 => D <= "00101111"; -- 0x0117
when 000280 => D <= "01110111"; -- 0x0118
when 000281 => D <= "01111110"; -- 0x0119
when 000282 => D <= "01110101"; -- 0x011A
when 000283 => D <= "01111100"; -- 0x011B
when 000284 => D <= "01110011"; -- 0x011C
when 000285 => D <= "01111010"; -- 0x011D
when 000286 => D <= "01110001"; -- 0x011E
when 000287 => D <= "01111000"; -- 0x011F
when 000288 => D <= "01111111"; -- 0x0120
when 000289 => D <= "01110110"; -- 0x0121
when 000290 => D <= "01111101"; -- 0x0122
when 000291 => D <= "01110100"; -- 0x0123
when 000292 => D <= "01111011"; -- 0x0124
when 000293 => D <= "01110010"; -- 0x0125
when 000294 => D <= "01111001"; -- 0x0126
when 000295 => D <= "01110000"; -- 0x0127
when 000296 => D <= "00111111"; -- 0x0128
when 000297 => D <= "01110111"; -- 0x0129
when 000298 => D <= "01111110"; -- 0x012A
when 000299 => D <= "01110101"; -- 0x012B
when 000300 => D <= "01111100"; -- 0x012C
when 000301 => D <= "01110011"; -- 0x012D
when 000302 => D <= "01111010"; -- 0x012E
when 000303 => D <= "01110001"; -- 0x012F
when 000304 => D <= "01111000"; -- 0x0130
when 000305 => D <= "01111111"; -- 0x0131
when 000306 => D <= "01110110"; -- 0x0132
when 000307 => D <= "01111101"; -- 0x0133
when 000308 => D <= "01110100"; -- 0x0134
when 000309 => D <= "01111011"; -- 0x0135
when 000310 => D <= "01110010"; -- 0x0136
when 000311 => D <= "01111001"; -- 0x0137
when 000312 => D <= "01110000"; -- 0x0138
when 000313 => D <= "00001111"; -- 0x0139
when 000314 => D <= "00110011"; -- 0x013A
when 000315 => D <= "00111010"; -- 0x013B
when 000316 => D <= "00000101"; -- 0x013C
when 000317 => D <= "00000100"; -- 0x013D
when 000318 => D <= "00110011"; -- 0x013E
when 000319 => D <= "00111010"; -- 0x013F
when 000320 => D <= "00000101"; -- 0x0140
when 000321 => D <= "00000100"; -- 0x0141
when 000322 => D <= "00110011"; -- 0x0142
when 000323 => D <= "00111010"; -- 0x0143
when 000324 => D <= "00000101"; -- 0x0144
when 000325 => D <= "00000100"; -- 0x0145
when 000326 => D <= "00110011"; -- 0x0146
when 000327 => D <= "00111010"; -- 0x0147
when 000328 => D <= "00000101"; -- 0x0148
when 000329 => D <= "00000100"; -- 0x0149
when 000330 => D <= "00110011"; -- 0x014A
when 000331 => D <= "00111010"; -- 0x014B
when 000332 => D <= "00000101"; -- 0x014C
when 000333 => D <= "00000100"; -- 0x014D
when 000334 => D <= "00110011"; -- 0x014E
when 000335 => D <= "00111010"; -- 0x014F
when 000336 => D <= "00000101"; -- 0x0150
when 000337 => D <= "00000100"; -- 0x0151
when 000338 => D <= "00110011"; -- 0x0152
when 000339 => D <= "00111010"; -- 0x0153
when 000340 => D <= "00000101"; -- 0x0154
when 000341 => D <= "00000100"; -- 0x0155
when 000342 => D <= "00110011"; -- 0x0156
when 000343 => D <= "00111010"; -- 0x0157
when 000344 => D <= "00000101"; -- 0x0158
when 000345 => D <= "00000100"; -- 0x0159
when 000346 => D <= "00110011"; -- 0x015A
when 000347 => D <= "00111010"; -- 0x015B
when 000348 => D <= "00000101"; -- 0x015C
when 000349 => D <= "00000100"; -- 0x015D
when 000350 => D <= "00110011"; -- 0x015E
when 000351 => D <= "00111010"; -- 0x015F
when 000352 => D <= "00000101"; -- 0x0160
when 000353 => D <= "00000100"; -- 0x0161
when 000354 => D <= "00110011"; -- 0x0162
when 000355 => D <= "00111010"; -- 0x0163
when 000356 => D <= "00000101"; -- 0x0164
when 000357 => D <= "00000100"; -- 0x0165
when 000358 => D <= "00110011"; -- 0x0166
when 000359 => D <= "00111010"; -- 0x0167
when 000360 => D <= "00000101"; -- 0x0168
when 000361 => D <= "00000100"; -- 0x0169
when 000362 => D <= "00110011"; -- 0x016A
when 000363 => D <= "00111010"; -- 0x016B
when 000364 => D <= "00000101"; -- 0x016C
when 000365 => D <= "00000100"; -- 0x016D
when 000366 => D <= "00110011"; -- 0x016E
when 000367 => D <= "00111010"; -- 0x016F
when 000368 => D <= "00000101"; -- 0x0170
when 000369 => D <= "00000100"; -- 0x0171
when 000370 => D <= "00110011"; -- 0x0172
when 000371 => D <= "00111010"; -- 0x0173
when 000372 => D <= "00000101"; -- 0x0174
when 000373 => D <= "00000100"; -- 0x0175
when 000374 => D <= "00110011"; -- 0x0176
when 000375 => D <= "00111010"; -- 0x0177
when 000376 => D <= "00000101"; -- 0x0178
when 000377 => D <= "00000100"; -- 0x0179
when 000378 => D <= "01000100"; -- 0x017A
when 000379 => D <= "00011111"; -- 0x017B
when 000380 => D <= "00110011"; -- 0x017C
when 000381 => D <= "00111010"; -- 0x017D
when 000382 => D <= "00000101"; -- 0x017E
when 000383 => D <= "00000100"; -- 0x017F
when 000384 => D <= "00110011"; -- 0x0180
when 000385 => D <= "00111010"; -- 0x0181
when 000386 => D <= "00000101"; -- 0x0182
when 000387 => D <= "00000100"; -- 0x0183
when 000388 => D <= "00110011"; -- 0x0184
when 000389 => D <= "00111010"; -- 0x0185
when 000390 => D <= "00000101"; -- 0x0186
when 000391 => D <= "00000100"; -- 0x0187
when 000392 => D <= "00110011"; -- 0x0188
when 000393 => D <= "00111010"; -- 0x0189
when 000394 => D <= "00000101"; -- 0x018A
when 000395 => D <= "00000100"; -- 0x018B
when 000396 => D <= "00110011"; -- 0x018C
when 000397 => D <= "00111010"; -- 0x018D
when 000398 => D <= "00000101"; -- 0x018E
when 000399 => D <= "00000100"; -- 0x018F
when 000400 => D <= "00110011"; -- 0x0190
when 000401 => D <= "00111010"; -- 0x0191
when 000402 => D <= "00000101"; -- 0x0192
when 000403 => D <= "00000100"; -- 0x0193
when 000404 => D <= "00110011"; -- 0x0194
when 000405 => D <= "00111010"; -- 0x0195
when 000406 => D <= "00000101"; -- 0x0196
when 000407 => D <= "00000100"; -- 0x0197
when 000408 => D <= "00110011"; -- 0x0198
when 000409 => D <= "00111010"; -- 0x0199
when 000410 => D <= "00000101"; -- 0x019A
when 000411 => D <= "00000100"; -- 0x019B
when 000412 => D <= "00110011"; -- 0x019C
when 000413 => D <= "00111010"; -- 0x019D
when 000414 => D <= "00000101"; -- 0x019E
when 000415 => D <= "00000100"; -- 0x019F
when 000416 => D <= "00110011"; -- 0x01A0
when 000417 => D <= "00111010"; -- 0x01A1
when 000418 => D <= "00000101"; -- 0x01A2
when 000419 => D <= "00000100"; -- 0x01A3
when 000420 => D <= "00110011"; -- 0x01A4
when 000421 => D <= "00111010"; -- 0x01A5
when 000422 => D <= "00000101"; -- 0x01A6
when 000423 => D <= "00000100"; -- 0x01A7
when 000424 => D <= "00110011"; -- 0x01A8
when 000425 => D <= "00111010"; -- 0x01A9
when 000426 => D <= "00000101"; -- 0x01AA
when 000427 => D <= "00000100"; -- 0x01AB
when 000428 => D <= "00110011"; -- 0x01AC
when 000429 => D <= "00111010"; -- 0x01AD
when 000430 => D <= "00000101"; -- 0x01AE
when 000431 => D <= "00000100"; -- 0x01AF
when 000432 => D <= "00110011"; -- 0x01B0
when 000433 => D <= "00111010"; -- 0x01B1
when 000434 => D <= "00000101"; -- 0x01B2
when 000435 => D <= "00000100"; -- 0x01B3
when 000436 => D <= "00110011"; -- 0x01B4
when 000437 => D <= "00111010"; -- 0x01B5
when 000438 => D <= "00000101"; -- 0x01B6
when 000439 => D <= "00000100"; -- 0x01B7
when 000440 => D <= "00110011"; -- 0x01B8
when 000441 => D <= "00111010"; -- 0x01B9
when 000442 => D <= "00000101"; -- 0x01BA
when 000443 => D <= "00000100"; -- 0x01BB
when 000444 => D <= "01000100"; -- 0x01BC
when 000445 => D <= "00101111"; -- 0x01BD
when 000446 => D <= "00110011"; -- 0x01BE
when 000447 => D <= "00111010"; -- 0x01BF
when 000448 => D <= "00000101"; -- 0x01C0
when 000449 => D <= "00000100"; -- 0x01C1
when 000450 => D <= "00110011"; -- 0x01C2
when 000451 => D <= "00111010"; -- 0x01C3
when 000452 => D <= "00000101"; -- 0x01C4
when 000453 => D <= "00000100"; -- 0x01C5
when 000454 => D <= "00110011"; -- 0x01C6
when 000455 => D <= "00111010"; -- 0x01C7
when 000456 => D <= "00000101"; -- 0x01C8
when 000457 => D <= "00000100"; -- 0x01C9
when 000458 => D <= "00110011"; -- 0x01CA
when 000459 => D <= "00111010"; -- 0x01CB
when 000460 => D <= "00000101"; -- 0x01CC
when 000461 => D <= "00000100"; -- 0x01CD
when 000462 => D <= "00110011"; -- 0x01CE
when 000463 => D <= "00111010"; -- 0x01CF
when 000464 => D <= "00000101"; -- 0x01D0
when 000465 => D <= "00000100"; -- 0x01D1
when 000466 => D <= "00110011"; -- 0x01D2
when 000467 => D <= "00111010"; -- 0x01D3
when 000468 => D <= "00000101"; -- 0x01D4
when 000469 => D <= "00000100"; -- 0x01D5
when 000470 => D <= "00110011"; -- 0x01D6
when 000471 => D <= "00111010"; -- 0x01D7
when 000472 => D <= "00000101"; -- 0x01D8
when 000473 => D <= "00000100"; -- 0x01D9
when 000474 => D <= "00110011"; -- 0x01DA
when 000475 => D <= "00111010"; -- 0x01DB
when 000476 => D <= "00000101"; -- 0x01DC
when 000477 => D <= "00000100"; -- 0x01DD
when 000478 => D <= "00110011"; -- 0x01DE
when 000479 => D <= "00111010"; -- 0x01DF
when 000480 => D <= "00000101"; -- 0x01E0
when 000481 => D <= "00000100"; -- 0x01E1
when 000482 => D <= "00110011"; -- 0x01E2
when 000483 => D <= "00111010"; -- 0x01E3
when 000484 => D <= "00000101"; -- 0x01E4
when 000485 => D <= "00000100"; -- 0x01E5
when 000486 => D <= "00110011"; -- 0x01E6
when 000487 => D <= "00111010"; -- 0x01E7
when 000488 => D <= "00000101"; -- 0x01E8
when 000489 => D <= "00000100"; -- 0x01E9
when 000490 => D <= "00110011"; -- 0x01EA
when 000491 => D <= "00111010"; -- 0x01EB
when 000492 => D <= "00000101"; -- 0x01EC
when 000493 => D <= "00000100"; -- 0x01ED
when 000494 => D <= "00110011"; -- 0x01EE
when 000495 => D <= "00111010"; -- 0x01EF
when 000496 => D <= "00000101"; -- 0x01F0
when 000497 => D <= "00000100"; -- 0x01F1
when 000498 => D <= "00110011"; -- 0x01F2
when 000499 => D <= "00111010"; -- 0x01F3
when 000500 => D <= "00000101"; -- 0x01F4
when 000501 => D <= "00000100"; -- 0x01F5
when 000502 => D <= "00110011"; -- 0x01F6
when 000503 => D <= "00111010"; -- 0x01F7
when 000504 => D <= "00000101"; -- 0x01F8
when 000505 => D <= "00000100"; -- 0x01F9
when 000506 => D <= "00110011"; -- 0x01FA
when 000507 => D <= "00111010"; -- 0x01FB
when 000508 => D <= "00000101"; -- 0x01FC
when 000509 => D <= "00000100"; -- 0x01FD
when 000510 => D <= "01000100"; -- 0x01FE
when 000511 => D <= "00111111"; -- 0x01FF
when 000512 => D <= "00110011"; -- 0x0200
when 000513 => D <= "00111010"; -- 0x0201
when 000514 => D <= "00000101"; -- 0x0202
when 000515 => D <= "00000100"; -- 0x0203
when 000516 => D <= "00110011"; -- 0x0204
when 000517 => D <= "00111010"; -- 0x0205
when 000518 => D <= "00000101"; -- 0x0206
when 000519 => D <= "00000100"; -- 0x0207
when 000520 => D <= "00110011"; -- 0x0208
when 000521 => D <= "00111010"; -- 0x0209
when 000522 => D <= "00000101"; -- 0x020A
when 000523 => D <= "00000100"; -- 0x020B
when 000524 => D <= "00110011"; -- 0x020C
when 000525 => D <= "00111010"; -- 0x020D
when 000526 => D <= "00000101"; -- 0x020E
when 000527 => D <= "00000100"; -- 0x020F
when 000528 => D <= "00110011"; -- 0x0210
when 000529 => D <= "00111010"; -- 0x0211
when 000530 => D <= "00000101"; -- 0x0212
when 000531 => D <= "00000100"; -- 0x0213
when 000532 => D <= "00110011"; -- 0x0214
when 000533 => D <= "00111010"; -- 0x0215
when 000534 => D <= "00000101"; -- 0x0216
when 000535 => D <= "00000100"; -- 0x0217
when 000536 => D <= "00110011"; -- 0x0218
when 000537 => D <= "00111010"; -- 0x0219
when 000538 => D <= "00000101"; -- 0x021A
when 000539 => D <= "00000100"; -- 0x021B
when 000540 => D <= "00110011"; -- 0x021C
when 000541 => D <= "00111010"; -- 0x021D
when 000542 => D <= "00000101"; -- 0x021E
when 000543 => D <= "00000100"; -- 0x021F
when 000544 => D <= "00110011"; -- 0x0220
when 000545 => D <= "00111010"; -- 0x0221
when 000546 => D <= "00000101"; -- 0x0222
when 000547 => D <= "00000100"; -- 0x0223
when 000548 => D <= "00110011"; -- 0x0224
when 000549 => D <= "00111010"; -- 0x0225
when 000550 => D <= "00000101"; -- 0x0226
when 000551 => D <= "00000100"; -- 0x0227
when 000552 => D <= "00110011"; -- 0x0228
when 000553 => D <= "00111010"; -- 0x0229
when 000554 => D <= "00000101"; -- 0x022A
when 000555 => D <= "00000100"; -- 0x022B
when 000556 => D <= "00110011"; -- 0x022C
when 000557 => D <= "00111010"; -- 0x022D
when 000558 => D <= "00000101"; -- 0x022E
when 000559 => D <= "00000100"; -- 0x022F
when 000560 => D <= "00110011"; -- 0x0230
when 000561 => D <= "00111010"; -- 0x0231
when 000562 => D <= "00000101"; -- 0x0232
when 000563 => D <= "00000100"; -- 0x0233
when 000564 => D <= "00110011"; -- 0x0234
when 000565 => D <= "00111010"; -- 0x0235
when 000566 => D <= "00000101"; -- 0x0236
when 000567 => D <= "00000100"; -- 0x0237
when 000568 => D <= "00110011"; -- 0x0238
when 000569 => D <= "00111010"; -- 0x0239
when 000570 => D <= "00000101"; -- 0x023A
when 000571 => D <= "00000100"; -- 0x023B
when 000572 => D <= "00110011"; -- 0x023C
when 000573 => D <= "00111010"; -- 0x023D
when 000574 => D <= "00000101"; -- 0x023E
when 000575 => D <= "00000100"; -- 0x023F
when 000576 => D <= "01000100"; -- 0x0240
when 000577 => D <= "01100010"; -- 0x0241
when 000578 => D <= "01000001"; -- 0x0242
when others => D <= "--------";
end case;
end if;
end process;
end;
|
gpl-2.0
|
freecores/t400
|
rtl/tech/generic/generic_ram_ena-c.vhd
|
1
|
482
|
-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM with enable.
--
-- $Id: generic_ram_ena-c.vhd,v 1.1 2006-06-05 20:01:05 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration generic_ram_ena_rtl_c0 of generic_ram_ena is
for rtl
end for;
end generic_ram_ena_rtl_c0;
|
gpl-2.0
|
freecores/t400
|
rtl/tech/generic/generic_ram-c.vhd
|
1
|
458
|
-------------------------------------------------------------------------------
--
-- Parametrizable, generic RAM.
--
-- $Id: generic_ram-c.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration generic_ram_rtl_c0 of generic_ram is
for rtl
end for;
end generic_ram_rtl_c0;
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201010_abus3/sniff_fifo.vhd
|
2
|
7063
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sniff_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END sniff_fifo;
ARCHITECTURE SYN OF sniff_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (47 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (47 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (47 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(47 DOWNTO 0);
usedw <= sub_wire3(9 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "MAX 10",
lpm_numwords => 1024,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 48,
lpm_widthu => 10,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "48"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "48"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0
-- Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/abus_demux.vhd
|
2
|
40009
|
-- abus_demux.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_demux is
port (
-- -- External signals used for simulation vvv
-- sim_test1 : out std_logic_vector( 7 downto 0) := (others => '0');
-- sim_test2 : out std_logic_vector( 7 downto 0) := (others => '0');
-- abus_cspulse_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_read_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_writeneg0_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_writeneg1_trail_dbg : out std_logic_vector(11 downto 0) := (others => '0');
-- abus_addresslatched_dbg : out std_logic_vector(23 downto 0) := (others => '0');
-- sim_noise : in std_logic := '0';
-- -- External signals used for simulation ^^^
clock : in std_logic := '0'; -- clock.clk
-- A-Bus interface
abus_address : in std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector( 1 downto 0) := (others => '0'); -- .write
abus_waitrequest : out std_logic := '1'; -- .waitrequest
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector( 1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
saturn_reset : in std_logic := '0'; -- .saturn_reset
-- Demuxed signals
-- Note : naming is Saturn-centered, ie readdata = read from Saturn = output from A-Bus side = input from demux side
demux_writeaddress : out std_logic_vector(27 downto 0) := (others => '0');
demux_writedata : out std_logic_vector(15 downto 0) := (others => '0');
demux_writepulse : out std_logic := '0';
demux_write_byteenable : out std_logic_vector( 1 downto 0) := (others => '0');
demux_readaddress : out std_logic_vector(27 downto 0) := (others => '0');
demux_readdata : in std_logic_vector(15 downto 0) := (others => '0');
demux_readpulse : out std_logic := '0';
demux_readdatavalid : in std_logic := '0';
-- Avalon
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector( 7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
reset : in std_logic := '0' -- reset.reset
);
end entity abus_demux;
architecture rtl of abus_demux is
-- Trail size, same for all internal signals.
-- As Quartus won't synthetize unused signals, large enough size is defined
-- so that source readability shall be a bit improved.
constant ABUS_TRAILS_SIZE : integer := 12;
signal abus_address_ms : std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector( 8 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_p1 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_p2 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf2 : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writeneg_ms : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writedata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_read_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- RD
signal abus_write_buf2 : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_writeneg0_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- WR0
signal abus_writeneg1_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- WR1
signal abus_trcntr : std_logic_vector( 3 downto 0) := (others => '0'); -- Transaction state counter
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_reading : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic := '0'; -- .write
signal abus_writing : std_logic := '0'; -- .write
-- Trails to properly delay write pipeline
signal abus_write_pulse_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- write
signal abus_writing_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0'); -- write
-- Buffers to hold avalon parameters during transaction
signal avalon_writedata_buff : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_byteenable_buff : std_logic_vector( 1 downto 0) := (others => '0');
signal avalon_write_buff : std_logic := '0';
signal abus_read_pulse_dmy : std_logic := '0'; -- .read
signal abus_write_pulse_dmy : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector( 2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse_trail : std_logic_vector((ABUS_TRAILS_SIZE-1) downto 0) := (others => '0');
signal abus_cspulse_off : std_logic := '0';
signal abus_chipselect_latched : std_logic_vector( 2 downto 0) := (others => '1'); -- abus.chipselect
signal abus_read_latched : std_logic := '0'; -- .read
signal abus_write_latched : std_logic_vector( 1 downto 0) := (others => '0'); -- .write
signal abus_address_latched : std_logic_vector(23 downto 0) := (others => '0'); -- .address
signal abus_direction_internal : std_logic := '0'; --high-z
signal abus_muxing_internal : std_logic_vector( 1 downto 0) := "01"; -- sample address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read1 : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write1 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- Access test stuff, added 2019/11/04 vvv
signal rdwr_access_buff : std_logic_vector(127 downto 0) := x"CAFE0304050607080910111213141516";
-- Access test stuff, added 2019/11/04 ^^^
-- External signals used for simulation vvv
signal sim_test1_internal : std_logic_vector( 7 downto 0) := x"CA";
signal sim_test2_internal : std_logic_vector( 7 downto 0) := x"FE";
-- External signals used for simulation ^^^
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_p1 <= abus_chipselect;
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
abus_writeneg_ms <= not abus_write;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_p2 <= abus_chipselect_p1;
abus_read_trail(0) <= abus_read_ms;
abus_write_buf <= abus_write_ms;
abus_writeneg0_trail(0) <= abus_writeneg_ms(0);
abus_writeneg1_trail(0) <= abus_writeneg_ms(1);
end if;
end process;
--excluding metastability protection is a bad behavior
--but it looks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_chipselect_buf2 <= abus_chipselect_p2;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
for i in 0 to (ABUS_TRAILS_SIZE-2) loop
abus_cspulse_trail (i+1) <= abus_cspulse_trail (i);
abus_read_trail (i+1) <= abus_read_trail (i);
abus_writeneg0_trail(i+1) <= abus_writeneg0_trail(i);
abus_writeneg1_trail(i+1) <= abus_writeneg1_trail(i);
end loop;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse_dmy <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse_dmy <= abus_read_trail(1) and not abus_read_trail(0);
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_p2;
abus_chipselect_pulse <= abus_chipselect_p2 and not abus_chipselect_p1;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_trail(0) and not abus_read_trail(1);
abus_chipselect_pulse_off <= abus_chipselect_p2 and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse_dmy(0)
or abus_write_pulse_dmy(1)
or abus_read_pulse_dmy
or abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)
or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0)
or abus_write_pulse_off(1)
or abus_read_pulse_off
or abus_chipselect_pulse_off(0)
or abus_chipselect_pulse_off(1)
or abus_chipselect_pulse_off(2);
abus_cspulse_trail(0) <= abus_chipselect_pulse(0)
or abus_chipselect_pulse(1)
or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0)
or abus_chipselect_pulse_off(1)
or abus_chipselect_pulse_off(2);
-- Transaction counter update
--
-- Concept
-- | - It is assumed that CS0~1 lines become active last and that RD/WR/ADDR/DATA lines are setup before that moment.
-- | -> should need to measure that for real with OLS !
-- | -> Timeline is as follow :
-- | abus_chipselect_p2 (two clocks before)
-- | abus_chipselect_p1 (one clock before)
-- | abus_chipselect (latest)
-- | - Let's wait for one MAX 10 internal (116 MHz) clock after CS is active and start sampling other signals.
-- | - During write transaction (write from Saturn to cartridge), data is demuxed during two clocks : this may not be needed but seems safer in a first try.
--
--
-- COMMON
-- | - Retrieve read/write type and latch full address
--
-- CARTRIDGE READ FROM SATURN
-- | - If register, process it immediately
-- | - If SDRAM or OCRAM, start transaction and wait until read is valid
--
-- CARTRIDGE WRITE FROM SATURN
-- | - Multiplex data/address to retrieve write data
-- | - If register, process it immediately
-- | - If SDRAM or OCRAM, start transaction and hold it until write is terminated
--
-- Rules about mutiplexer control :
-- 1. Control with transaction counter, because in incremented during CS activity.
-- 2. Keep enough clocks at the beginning of CS activity to retrieve full address, and data if needed.
-- 3. After that, select and hold (until transaction counter becomes zero) appropriate bus direction.
process (clock)
begin
if rising_edge(clock) then
if saturn_reset = '0' then
abus_trcntr <= x"0"; -- Return to idle state during Saturn reset
else
if abus_trcntr = x"0" then
if ((abus_chipselect_p2(0) = '1') and (abus_chipselect_p2(1) = '1')
and ((abus_chipselect_p1(0) = '0') or (abus_chipselect_p1(1) = '0'))) then
abus_trcntr <= x"1"; -- Transaction startup
else
abus_trcntr <= x"0";
end if;
else
if (abus_chipselect(0) = '1') and (abus_chipselect(1) = '1') then
abus_trcntr <= x"0"; -- Return to idle state when CS returns to idle
else
if abus_trcntr = x"F" then
abus_trcntr <= x"F"; -- Hold counter to max until CS returns to idle
else
abus_trcntr <= abus_trcntr + x"1"; -- Go to next state
end if;
end if;
end if;
end if;
end if;
end process;
sim_test2_internal(3 downto 0) <= abus_trcntr(3 downto 0);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_trcntr = x"0" then
demux_readpulse <= '0';
demux_writepulse <= '0';
elsif abus_trcntr = x"1" then
-- Latch access base signals
abus_chipselect_latched <= abus_chipselect;
abus_read_latched <= abus_read;
abus_write_latched <= abus_write;
-- Generate read pulse (1/2)
if abus_read = '0' then
demux_readpulse <= '1';
end if;
elsif abus_trcntr = x"2" then
-- Generate read pulse (2/2)
if my_little_transaction_dir = DIR_READ then
demux_readpulse <= '0';
end if;
elsif abus_trcntr = x"4" then
-- Retrieve multiplexed data for write transaction, and generate write pulse
if my_little_transaction_dir = DIR_WRITE then
demux_writedata <= abus_data_in;
demux_writepulse <= '1';
end if;
elsif abus_trcntr = x"5" then
-- Terminate write pulse
if my_little_transaction_dir = DIR_WRITE then
demux_writepulse <= '0';
end if;
end if;
end if;
end process;
-- De-shuffle address
process(abus_address_latched, abus_address, abus_addressdata)
begin
if(abus_muxing_internal = "01") then
--if(abus_read = '1') then
-- 2019/07/20 : this is now adapted for "SIM to MAX 10 Board",
-- which allows multiplexing simpler than on cartridge
-- abus_address_latched <=
-- abus_address(7) -- abus_address(8) ignored ?!
-- & abus_address(6)
-- & abus_address(5)
-- & abus_address(4)
-- & abus_address(3)
-- & abus_address(2)
-- & abus_address(1)
-- & abus_address(0) -- TOP ADDRESS ^^^
-- & abus_addressdata(15) -- MUX vvv
-- & abus_addressdata(14)
-- & abus_addressdata(13)
-- & abus_addressdata(12)
-- & abus_addressdata(11)
-- & abus_addressdata(10)
-- & abus_addressdata( 9)
-- & abus_addressdata( 8)
-- & abus_addressdata( 7)
-- & abus_addressdata( 6)
-- & abus_addressdata( 5)
-- & abus_addressdata( 4)
-- & abus_addressdata( 3)
-- & abus_addressdata( 2)
-- & abus_addressdata( 1)
-- & abus_addressdata( 0);
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3) abus_address_latched <= abus_address
-- A13 -> MUX12 A0 -> MUX0 & abus_addressdata(11) -- A14
-- A6 -> MUX13 A9 -> MUX1 & abus_addressdata(12) -- A13
-- A5 -> MUX14 A10 -> MUX2 & abus_addressdata( 9) -- A12
-- A4 -> MUX15 A8 -> MUX3 & abus_addressdata(10) -- A11
-- A3 -> MUX4 A7 -> MUX8 & abus_addressdata( 2) -- A10
-- A2 -> MUX5 A12 -> MUX9 & abus_addressdata( 1) -- A9
-- A1 -> MUX6 A11 -> MUX10 & abus_addressdata( 3) -- A8
-- DMY -> MUX7 A14 -> MUX11 & abus_addressdata( 8) -- A7
--Which gives the following order for de-shuffling address : & abus_addressdata(13) -- A6
-- A14 -> MUX11 & abus_addressdata(14) -- A5
-- A13 -> MUX12 & abus_addressdata(15) -- A4
-- A12 -> MUX9 & abus_addressdata( 4) -- A3
-- A11 -> MUX10 & abus_addressdata( 5) -- A2
-- A10 -> MUX2 & abus_addressdata( 6) -- A1
-- A9 -> MUX1 & abus_addressdata( 0); -- A0
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
abus_address_latched <= abus_address
& abus_addressdata(11) -- A14
& abus_addressdata(12) -- A13
& abus_addressdata( 9) -- A12
& abus_addressdata(10) -- A11
& abus_addressdata( 2) -- A10
& abus_addressdata( 1) -- A9
& abus_addressdata( 3) -- A8
& abus_addressdata( 8) -- A7
& abus_addressdata(13) -- A6
& abus_addressdata(14) -- A5
& abus_addressdata(15) -- A4
& abus_addressdata( 4) -- A3
& abus_addressdata( 5) -- A2
& abus_addressdata( 6) -- A1
& abus_addressdata( 0); -- A0
end if;
end process;
-- Update the following "static" informations while idle :
-- - Demuxed address, including CS0~1
-- - Write byte enable
process (clock)
begin
if rising_edge(clock) then
-- Address and CS0~1
if abus_trcntr = x"1" then
--if((clock = '1') and ((abus_trcntr = x"0") or (abus_trcntr = x"1")))then
-- Put both address itself and chipselect on the same demuxed address
-- Upper bits of demuxed address are currently unused and reserved for eventual future purpose.
--
-- And, separate address for both write and read access, so that write operation
-- have more chances to terminate even when read operation starts just after.
if(abus_read = '0') then
demux_readaddress(27) <= '0';
demux_readaddress(26) <= '0';
if abus_chipselect(0) = '0' then
demux_readaddress(25 downto 24) <= "00";
elsif abus_chipselect(1) = '0' then
demux_readaddress(25 downto 24) <= "01";
elsif abus_chipselect(2) = '0' then
demux_readaddress(25 downto 24) <= "10";
else
demux_readaddress(25 downto 24) <= "11"; -- Shouldn't happen since transaction is initiated when activity on CS is detected.
end if;
demux_readaddress(23 downto 0) <= abus_address_latched(23 downto 0);
else
demux_writeaddress(27) <= '0';
demux_writeaddress(26) <= '0';
if abus_chipselect(0) = '0' then
demux_writeaddress(25 downto 24) <= "00";
elsif abus_chipselect(1) = '0' then
demux_writeaddress(25 downto 24) <= "01";
elsif abus_chipselect(2) = '0' then
demux_writeaddress(25 downto 24) <= "10";
else
demux_writeaddress(25 downto 24) <= "11"; -- Shouldn't happen since transaction is initiated when activity on CS is detected.
end if;
demux_writeaddress(23 downto 0) <= abus_address_latched(23 downto 0);
end if;
end if;
end if;
end process;
process (clock)
begin
if saturn_reset = '0' then
demux_write_byteenable(0) <= '0';
demux_write_byteenable(1) <= '0';
else
-- Write byte enable
-- Keep holding it even while read operation started,
-- so that eventual ongoing write operation have more
-- chances to terminate correctly.
if((abus_trcntr = x"1") and (abus_read = '1'))then
demux_write_byteenable(0) <= not abus_write(0);
demux_write_byteenable(1) <= not abus_write(1);
end if;
end if;
end process;
-- If valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if((abus_trcntr = x"0") or ((abus_chipselect(0) = '1') and (abus_chipselect(1) = '1')))then
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "01"; --address
elsif abus_trcntr = x"1" then
if abus_read = '0' then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "10"; --data
end if;
elsif abus_trcntr = x"2" then
if abus_read = '0' then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "10"; --data
end if;
-- Long multiplexer TEST vvv
-- Note 2019/12/13 : multiplexing during 1~2 is necessary for Wasca on real Hardware.
-- And so far it wasn't verified if multiplexing during 3 is necessary for MAX 10 Board r0.7 (b).
-- elsif abus_trcntr = x"3" then
-- if abus_read = '0' then
-- abus_direction_internal <= '1' ; --active
-- abus_muxing_internal <= "10"; --data
-- else
-- abus_direction_internal <= '0' ; --high-z
-- abus_muxing_internal <= "10"; --data
-- end if;
-- Long multiplexer TEST ^^^
else
if my_little_transaction_dir = DIR_READ then
abus_direction_internal <= '1' ; --active
abus_muxing_internal <= "10"; --data
else --if my_little_transaction_dir = DIR_READ then
abus_direction_internal <= '0' ; --high-z
abus_muxing_internal <= "01"; --address
end if;
end if;
end if;
end process;
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
-- Update access direction
process (clock)
begin
if rising_edge(clock) then
if((abus_chipselect(0) = '1') and (abus_chipselect(1) = '1'))then
my_little_transaction_dir <= DIR_NONE;
abus_writing <= '0';
abus_reading <= '0';
elsif abus_trcntr = x"1" then
-- Decide access direction, and hold it until end of transaction
if abus_read = '0' then
my_little_transaction_dir <= DIR_READ;
abus_writing <= '0';
abus_reading <= '1';
else --if abus_read_ms = '0' then
my_little_transaction_dir <= DIR_WRITE;
abus_writing <= '1';
abus_reading <= '0';
end if;
end if;
end if;
end process;
-- Generate a reading/writing pulse during access
process (clock)
begin
if rising_edge(clock) then
if abus_trcntr = x"0" then
abus_write_pulse <= '0'; -- No access during idle state
abus_read_pulse <= '0'; -- No access during idle state
elsif abus_trcntr = x"1" then
if abus_write(0) = '0' or abus_write(1) = '0' then
abus_write_pulse <= '0'; -- Wait to receive data during a write transaction
abus_read_pulse <= '0';
else --if abus_read_ms = '0' then
abus_write_pulse <= '0';
abus_read_pulse <= '1'; -- Generate a read pulse when full address is received
end if;
elsif abus_trcntr = x"2" then
if my_little_transaction_dir = DIR_WRITE then
abus_write_pulse <= '1'; -- Generate a write pulse when both full address and data are received
abus_read_pulse <= '0';
else --if my_little_transaction_dir = DIR_READ then
abus_write_pulse <= '0';
abus_read_pulse <= '0'; -- Read transaction falling edge
end if;
elsif abus_trcntr = x"3" then
abus_read_pulse <= '0'; -- Write transaction falling edge
abus_write_pulse <= '0';
if my_little_transaction_dir = DIR_WRITE then
else --if my_little_transaction_dir = DIR_READ then
end if;
else
abus_read_pulse <= '0'; -- Write transaction falling edge
abus_write_pulse <= '0';
if my_little_transaction_dir = DIR_WRITE then
else --if my_little_transaction_dir = DIR_READ then
end if;
end if;
-- Delay write related signals
abus_writing_trail (0) <= abus_writing;
abus_write_pulse_trail(0) <= abus_write_pulse;
for i in 0 to (ABUS_TRAILS_SIZE-2) loop
abus_writing_trail (i+1) <= abus_writing_trail (i);
abus_write_pulse_trail(i+1) <= abus_write_pulse_trail(i);
end loop;
end if;
end process;
sim_test2_internal(7) <= abus_write_pulse_trail(3);
sim_test2_internal(6) <= abus_write_pulse_trail(2);
sim_test2_internal(5) <= abus_write_pulse_trail(1);
sim_test2_internal(4) <= abus_write_pulse_trail(0);
---------------------------------------------------------------------------------------
-- Update buffer data when read data valid pulse if detected
-- Read data valid pulse may not be super necessary, but this is provided by Avalon,
-- and may be helpful when counting clocks elapsed during read access.
--
process (abus_reading) begin
abus_data_out <= demux_readdata; -- Faster than below
if rising_edge(clock) then
if(demux_readdatavalid = '1') then
--abus_data_out <= demux_readdata;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- In/Out process
--
-- Access from each CS0-2 is handled from this chip.
-- In the future, it may be required to manage access to external FTDI chip ?
--
process (abus_reading) begin
--if rising_edge(clock) then
--if(abus_reading = '1') then
if(abus_read = '0') then
-- Output to data bus
abus_addressdata <= abus_data_out;
--abus_addressdata <= x"ABCD";
--sim_test2_internal <= x"CA";
abus_data_in <= abus_addressdata;
else
-- Disable output to data bus
abus_addressdata <= "ZZZZZZZZZZZZZZZZ";
abus_data_in <= abus_addressdata;
--sim_test2_internal <= x"FF";
end if;
--end if;
end process;
sim_test1_internal(7) <= abus_writing;
sim_test1_internal(6) <= abus_reading;
sim_test1_internal(5) <= abus_write_pulse;
sim_test1_internal(4) <= abus_read_pulse;
sim_test1_internal(3) <= abus_writing_trail(0);
sim_test1_internal(2) <= abus_writing_trail(1);
sim_test1_internal(1) <= abus_writing_trail(2);
sim_test1_internal(0) <= '1';
-- "disable_out" controls refresh timing of wait and IRQ signals
-- 0:output, 1:hold previous
--abus_disable_out <= '1' when abus_chipselect_number(1) = '1' else '0';
abus_disable_out <= '0';
-- Let's completely neglect usage of wait request signal for now, and ... hope that
-- SDRAM controller is smarter enough to do things timely.
-- (Spoiler : SDRAM controller is completely dumb)
abus_waitrequest <= '1';
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read2 <= abus_waitrequest_read1;
-- abus_waitrequest_write2 <= abus_waitrequest_write1;
-- end if;
-- end process;
--
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- abus_waitrequest_read_off <= '0';
-- abus_waitrequest_write_off <= '0';
-- if abus_waitrequest_read1 = '0' and abus_waitrequest_read2 = '1' then
-- abus_waitrequest_read_off <= '1';
-- end if;
-- if abus_waitrequest_write1 = '0' and abus_waitrequest_write2 = '1' then
-- abus_waitrequest_write_off <= '1';
-- end if;
-- end if;
-- end process;
--
-- --process (clock)
-- --begin
-- -- if rising_edge(clock) then
-- -- --if abus_read_pulse_dmy='1' or abus_write_pulse_dmy(0)='1' or abus_write_pulse_dmy(1)='1' then
-- -- --if abus_anypulse = '1' then
-- -- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- -- abus_waitrequest <= '0';
-- -- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- -- abus_waitrequest <= '1';
-- -- end if;
-- -- end if;
-- --end process;
--
-- abus_waitrequest <= not (abus_waitrequest_read1 or abus_waitrequest_write1);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"00" =>
avalon_nios_readdata <= x"CA0000" & rd_access_cntr;
when X"01" =>
avalon_nios_readdata <= x"FE0000" & wr_access_cntr;
when X"10" =>
avalon_nios_readdata <= x"0000" & REG_PCNTR;
when X"11" =>
avalon_nios_readdata <= x"0000" & REG_STATUS;
when X"12" =>
avalon_nios_readdata <= x"0000" & REG_MODE;
when X"13" =>
avalon_nios_readdata <= x"0000" & REG_HWVER;
when X"14" =>
avalon_nios_readdata <= x"0000" & REG_SWVER;
when X"15" =>
avalon_nios_readdata <= X"0000ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= x"00000000";
end case;
else
avalon_nios_readdatavalid <= '0';
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"10" =>
REG_PCNTR <= avalon_nios_writedata(15 downto 0);
when X"11" =>
REG_STATUS <= avalon_nios_writedata(15 downto 0);
when X"12" =>
null;
when X"13" =>
null;
when X"14" =>
REG_SWVER <= avalon_nios_writedata(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
-- -- External signals used for simulation vvv
-- sim_test1 <= sim_test1_internal;
-- sim_test2 <= sim_test2_internal;
-- abus_cspulse_trail_dbg <= abus_cspulse_trail;
-- abus_read_trail_dbg <= abus_read_trail;
-- abus_writeneg0_trail_dbg <= abus_writeneg0_trail;
-- abus_writeneg1_trail_dbg <= abus_writeneg1_trail;
-- abus_addresslatched_dbg <= abus_address_latched;
-- -- External signals used for simulation ^^^
end architecture rtl; -- of abus_demux
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/sega_saturn_abus_slave.vhd
|
3
|
26193
|
-- sega_saturn_abus_slave.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sega_saturn_abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity sega_saturn_abus_slave;
architecture rtl of sega_saturn_abus_slave is
signal abus_address_ms : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(9 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
--abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
-- & abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
abus_address_latched <= abus_address & abus_addressdata_buf(11) & abus_addressdata_buf(12) & abus_addressdata_buf(9) & abus_addressdata_buf(10)
& abus_addressdata_buf(2) & abus_addressdata_buf(1) & abus_addressdata_buf(3) & abus_addressdata_buf(8)
& abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
& abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(0) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(24 downto 0) = "1"&X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF0" then
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF2" then
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF4" then
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF6" then
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFF8" then
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFA" then
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFC" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(24 downto 0) = "1"&X"FFFFFE" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFE" or abus_address_latched(23 downto 0) = X"FFFFFC" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFF4" then
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
avalon_address <= "010" & abus_address_latched(24 downto 0);
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of sega_saturn_abus_slave
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/abus_slave.vhd
|
2
|
30506
|
-- abus_slave.vhd
library IEEE;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity abus_slave is
port (
clock : in std_logic := '0'; -- clock.clk
abus_address : in std_logic_vector(8 downto 0) := (others => '0'); -- abus.address
abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
--abus_functioncode : in std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--abus_timing : in std_logic_vector(2 downto 0) := (others => '0'); -- .timing
abus_waitrequest : out std_logic := '1'; -- .waitrequest
--abus_addressstrobe : in std_logic := '0'; -- .addressstrobe
abus_interrupt : out std_logic := '0'; -- .interrupt
abus_direction : out std_logic := '0'; -- .direction
abus_muxing : out std_logic_vector(1 downto 0) := "01"; -- .muxing
abus_disable_out : out std_logic := '0'; -- .disableout
avalon_read : out std_logic; -- avalon_master.read
avalon_write : out std_logic; -- .write
avalon_waitrequest : in std_logic := '0'; -- .waitrequest
avalon_address : out std_logic_vector(27 downto 0); -- .address
avalon_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_writedata : out std_logic_vector(15 downto 0); -- .writedata
avalon_byteenable : out std_logic_vector( 1 downto 0); -- .byteenable
avalon_burstcount : out std_logic; -- .burstcount
avalon_readdatavalid : in std_logic := '0'; -- .readdatavalid
avalon_nios_read : in std_logic := '0'; -- avalon_master.read
avalon_nios_write : in std_logic := '0'; -- .write
avalon_nios_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_nios_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_nios_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_nios_burstcount : in std_logic; -- .burstcount
avalon_nios_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_nios_readdatavalid : out std_logic := '0'; -- .readdatavalid
saturn_reset : in std_logic := '0'; -- .saturn_reset
reset : in std_logic := '0' -- reset.reset
);
end entity abus_slave;
architecture rtl of abus_slave is
signal abus_address_ms : std_logic_vector(8 downto 0) := (others => '0'); -- abus.address
signal abus_address_buf : std_logic_vector(8 downto 0) := (others => '0'); -- abus.address
signal abus_addressdata_ms : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_addressdata_buf : std_logic_vector(15 downto 0) := (others => '0'); -- .data
signal abus_chipselect_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_chipselect_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_ms : std_logic := '0'; -- .read
signal abus_read_buf : std_logic := '0'; -- .read
signal abus_write_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_write_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .write
--signal abus_functioncode_ms : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_functioncode_buf : std_logic_vector(1 downto 0) := (others => '0'); -- .functioncode
--signal abus_timing_ms : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_timing_buf : std_logic_vector(2 downto 0) := (others => '0'); -- .timing
--signal abus_addressstrobe_ms : std_logic := '0'; -- .addressstrobe
--signal abus_addressstrobe_buf : std_logic := '0'; -- .addressstrobe
signal abus_read_buf2 : std_logic := '0'; -- .read
signal abus_read_buf3 : std_logic := '0'; -- .read
signal abus_read_buf4 : std_logic := '0'; -- .read
signal abus_read_buf5 : std_logic := '0'; -- .read
signal abus_read_buf6 : std_logic := '0'; -- .read
signal abus_read_buf7 : std_logic := '0'; -- .read
signal abus_write_buf2 : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_buf2 : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse : std_logic := '0'; -- .read
signal abus_write_pulse : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_read_pulse_off : std_logic := '0'; -- .read
signal abus_write_pulse_off : std_logic_vector(1 downto 0) := (others => '0'); -- .write
signal abus_chipselect_pulse_off : std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
signal abus_anypulse : std_logic := '0';
signal abus_anypulse2 : std_logic := '0';
signal abus_anypulse3 : std_logic := '0';
signal abus_anypulse_off : std_logic := '0';
signal abus_cspulse : std_logic := '0';
signal abus_cspulse2 : std_logic := '0';
signal abus_cspulse3 : std_logic := '0';
signal abus_cspulse4 : std_logic := '0';
signal abus_cspulse5 : std_logic := '0';
signal abus_cspulse6 : std_logic := '0';
signal abus_cspulse7 : std_logic := '0';
signal abus_cspulse_off : std_logic := '0';
signal abus_address_latched : std_logic_vector(23 downto 0) := (others => '0'); -- abus.address
signal abus_chipselect_latched : std_logic_vector(1 downto 0) := (others => '1'); -- abus.address
signal abus_direction_internal : std_logic := '0';
signal abus_muxing_internal : std_logic_vector(1 downto 0) := (others => '0'); -- abus.address
signal abus_data_out : std_logic_vector(15 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_waitrequest_read : std_logic := '0';
signal abus_waitrequest_write : std_logic := '0';
signal abus_waitrequest_read2 : std_logic := '0';
signal abus_waitrequest_write2 : std_logic := '0';
--signal abus_waitrequest_read3 : std_logic := '0';
--signal abus_waitrequest_write3 : std_logic := '0';
--signal abus_waitrequest_read4 : std_logic := '0';
--signal abus_waitrequest_write4 : std_logic := '0';
signal abus_waitrequest_read_off : std_logic := '0';
signal abus_waitrequest_write_off : std_logic := '0';
-- For Rd/Wr access debug
signal rd_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal wr_access_cntr : std_logic_vector( 7 downto 0) := x"01";
signal last_rd_addr : std_logic_vector(15 downto 0) := x"1230"; -- lower 16 bits only
signal last_wr_addr : std_logic_vector(15 downto 0) := x"1231"; -- lower 16 bits only
signal last_wr_data : std_logic_vector(15 downto 0) := x"5678";
signal REG_PCNTR : std_logic_vector(15 downto 0) := (others => '0');
signal REG_STATUS : std_logic_vector(15 downto 0) := (others => '0');
signal REG_MODE : std_logic_vector(15 downto 0) := (others => '0');
signal REG_HWVER : std_logic_vector(15 downto 0) := X"0002";
signal REG_SWVER : std_logic_vector(15 downto 0) := (others => '0');
TYPE transaction_dir IS (DIR_NONE,DIR_WRITE,DIR_READ);
SIGNAL my_little_transaction_dir : transaction_dir := DIR_NONE;
TYPE wasca_mode_type IS (MODE_INIT,
MODE_POWER_MEMORY_05M, MODE_POWER_MEMORY_1M, MODE_POWER_MEMORY_2M, MODE_POWER_MEMORY_4M,
MODE_RAM_1M, MODE_RAM_4M,
MODE_ROM_KOF95,
MODE_ROM_ULTRAMAN,
MODE_BOOT);
SIGNAL wasca_mode : wasca_mode_type := MODE_INIT;
begin
abus_direction <= abus_direction_internal;
abus_muxing <= not abus_muxing_internal;
--ignoring functioncode, timing and addressstrobe for now
--abus transactions are async, so first we must latch incoming signals
--to get rid of metastability
process (clock)
begin
if rising_edge(clock) then
--1st stage
abus_address_ms <= abus_address;
abus_addressdata_ms <= abus_addressdata;
abus_chipselect_ms <= abus_chipselect; --work only with CS1 for now
abus_read_ms <= abus_read;
abus_write_ms <= abus_write;
--abus_functioncode_ms <= abus_functioncode;
--abus_timing_ms <= abus_timing;
--abus_addressstrobe_ms <= abus_addressstrobe;
--2nd stage
abus_address_buf <= abus_address_ms;
abus_addressdata_buf <= abus_addressdata_ms;
abus_chipselect_buf <= abus_chipselect_ms;
abus_read_buf <= abus_read_ms;
abus_write_buf <= abus_write_ms;
--abus_functioncode_buf <= abus_functioncode_ms;
--abus_timing_buf <= abus_timing_ms;
--abus_addressstrobe_buf <= abus_addressstrobe_ms;
end if;
end process;
--excluding metastability protection is a bad behavior
--but it lloks like we're out of more options to optimize read pipeline
--abus_read_ms <= abus_read;
--abus_read_buf <= abus_read_ms;
--abus read/write latch
process (clock)
begin
if rising_edge(clock) then
abus_write_buf2 <= abus_write_buf;
abus_read_buf2 <= abus_read_buf;
abus_read_buf3 <= abus_read_buf2;
abus_read_buf4 <= abus_read_buf3;
abus_read_buf5 <= abus_read_buf4;
abus_read_buf6 <= abus_read_buf5;
abus_read_buf7 <= abus_read_buf6;
abus_chipselect_buf2 <= abus_chipselect_buf;
abus_anypulse2 <= abus_anypulse;
abus_anypulse3 <= abus_anypulse2;
abus_cspulse2 <= abus_cspulse;
abus_cspulse3 <= abus_cspulse2;
abus_cspulse4 <= abus_cspulse3;
abus_cspulse5 <= abus_cspulse4;
abus_cspulse6 <= abus_cspulse5;
abus_cspulse7 <= abus_cspulse6;
end if;
end process;
--abus write/read pulse is a falling edge since read and write signals are negative polarity
abus_write_pulse <= abus_write_buf2 and not abus_write_buf;
abus_read_pulse <= abus_read_buf2 and not abus_read_buf;
--abus_chipselect_pulse <= abus_chipselect_buf2 and not abus_chipselect_buf;
abus_chipselect_pulse <= abus_chipselect_buf and not abus_chipselect_ms;
abus_write_pulse_off <= abus_write_buf and not abus_write_buf2;
abus_read_pulse_off <= abus_read_buf and not abus_read_buf2;
abus_chipselect_pulse_off <= abus_chipselect_buf and not abus_chipselect_buf2;
abus_anypulse <= abus_write_pulse(0) or abus_write_pulse(1) or abus_read_pulse or
abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_anypulse_off <= abus_write_pulse_off(0) or abus_write_pulse_off(1) or abus_read_pulse_off or
abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
abus_cspulse <= abus_chipselect_pulse(0) or abus_chipselect_pulse(1) or abus_chipselect_pulse(2);
abus_cspulse_off <= abus_chipselect_pulse_off(0) or abus_chipselect_pulse_off(1) or abus_chipselect_pulse_off(2);
--whatever pulse we've got, latch address
--it might be latched twice per transaction, but it's not a problem
--multiplexer was switched to address after previous transaction or after boot,
--so we have address ready to latch
process (clock)
begin
if rising_edge(clock) then
if abus_anypulse = '1' then
--if abus_read_pulse = '1' or abus_write_pulse(0) = '1' or abus_write_pulse(1)='1' then
--Purpose of A0 line in PCB Rev 1.3 is unknown and consequently
--have to be ignored when building address. Instead, address
--top bit is stuffed with '0'.
--Address Mapping for U4 : And for U1 : (In PCB Rev 1.3)
-- A13 -> MUX12 A0 -> MUX0
-- A6 -> MUX13 A9 -> MUX1
-- A5 -> MUX14 A10 -> MUX2
-- A4 -> MUX15 A8 -> MUX3
-- A3 -> MUX4 A7 -> MUX8
-- A2 -> MUX5 A12 -> MUX9
-- A1 -> MUX6 A11 -> MUX10
-- DMY -> MUX7 A14 -> MUX11
--Which gives the following order for de-shuffling address :
-- A14 -> MUX11
-- A13 -> MUX12
-- A12 -> MUX9
-- A11 -> MUX10
-- A10 -> MUX2
-- A9 -> MUX1
-- A8 -> MUX3
-- A7 -> MUX8
-- A6 -> MUX13
-- A5 -> MUX14
-- A4 -> MUX15
-- A3 -> MUX4
-- A2 -> MUX5
-- A1 -> MUX6
-- A0 -> MUX0
abus_address_latched <= abus_address
& abus_addressdata_buf(11) -- A14
& abus_addressdata_buf(12) -- A13
& abus_addressdata_buf( 9) -- A12
& abus_addressdata_buf(10) -- A11
& abus_addressdata_buf( 2) -- A10
& abus_addressdata_buf( 1) -- A9
& abus_addressdata_buf( 3) -- A8
& abus_addressdata_buf( 8) -- A7
& abus_addressdata_buf(13) -- A6
& abus_addressdata_buf(14) -- A5
& abus_addressdata_buf(15) -- A4
& abus_addressdata_buf( 4) -- A3
& abus_addressdata_buf( 5) -- A2
& abus_addressdata_buf( 6) -- A1
& abus_addressdata_buf( 0); -- A0
-- Old de-shuffling logic used in PCB v1.0/v1.1, kept in case of :
-- abus_address_latched <= abus_address & abus_addressdata_buf(0) & abus_addressdata_buf(12) & abus_addressdata_buf(2) & abus_addressdata_buf(1)
-- & abus_addressdata_buf(9) & abus_addressdata_buf(10) & abus_addressdata_buf(8) & abus_addressdata_buf(3)
-- & abus_addressdata_buf(13) & abus_addressdata_buf(14) & abus_addressdata_buf(15) & abus_addressdata_buf(4)
-- & abus_addressdata_buf(5) & abus_addressdata_buf(6) & abus_addressdata_buf(11) & abus_addressdata_buf(7);
end if;
end if;
end process;
--latch transaction direction
process (clock)
begin
if rising_edge(clock) then
if abus_write_pulse(0) = '1' or abus_write_pulse(1) = '1' then
my_little_transaction_dir <= DIR_WRITE;
elsif abus_read_pulse = '1' then
my_little_transaction_dir <= DIR_READ;
elsif abus_anypulse_off = '1' and abus_cspulse_off = '0' then --ending anything but not cs
my_little_transaction_dir <= DIR_NONE;
end if;
end if;
end process;
--latch chipselect number
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_pulse(0) = '1' then
abus_chipselect_latched <= "00";
elsif abus_chipselect_pulse(1) = '1' then
abus_chipselect_latched <= "01";
elsif abus_chipselect_pulse(2) = '1' then
abus_chipselect_latched <= "10";
elsif abus_cspulse_off = '1' then
abus_chipselect_latched <= "11";
end if;
end if;
end process;
--if valid transaction captured, switch to corresponding multiplex mode
process (clock)
begin
if rising_edge(clock) then
if abus_chipselect_latched = "11" then
--chipselect deasserted
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "01"; --address
else
--chipselect asserted
case (my_little_transaction_dir) is
when DIR_NONE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
when DIR_READ =>
abus_direction_internal <= '1'; --active
abus_muxing_internal <= "10"; --data
when DIR_WRITE =>
abus_direction_internal <= '0'; --high-z
abus_muxing_internal <= "10"; --data
end case;
end if;
end if;
end process;
abus_disable_out <= '1' when abus_chipselect_latched(1) = '1' else
'0';
--if abus read access is detected, issue avalon read transaction
--wait until readdatavalid, then disable read and abus wait
process (clock)
begin
if rising_edge(clock) then
--if my_little_transaction_dir = DIR_READ and abus_chipselect_latched(1) = '0' and abus_anypulse2 = '1' then
--starting read transaction at either RD pulse or (CS pulse while RD is on)
--but if CS arrives less than 7 clocks after RD, then we ignore this CS
--this will get us 2 additional clocks at read pipeline
if abus_read_pulse = '1' or (abus_cspulse='1' and abus_read_buf = '0' and abus_read_buf7 = '0') then
avalon_read <= '1';
abus_waitrequest_read <= '1';
elsif avalon_readdatavalid = '1' then
-- Debug stuff around Rd/Wr access
rd_access_cntr <= rd_access_cntr + x"01";
last_rd_addr <= abus_address_latched(15 downto 0);
avalon_read <= '0';
abus_waitrequest_read <= '0';
if abus_chipselect_latched = "00" then
--CS0 access
if abus_address_latched(23 downto 0) = X"FF0FFE" then
--wasca specific SD card control register
abus_data_out <= X"CDCD";
elsif abus_address_latched(23 downto 0) = X"FFFFF0" then -- 0x23FFFFE0
abus_data_out <= X"FFFF"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF1" then -- 0x23FFFFE2
abus_data_out <= X"0000"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF2" then -- 0x23FFFFE4
abus_data_out <= X"A5A5"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF3" then -- 0x23FFFFE6
abus_data_out <= X"5A5A"; -- Test for cartridge assembly
elsif abus_address_latched(23 downto 0) = X"FFFFF4" then -- 0x23FFFFE8
abus_data_out <= x"CA" & rd_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF5" then -- 0x23FFFFEA
abus_data_out <= x"AC" & rd_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF6" then -- 0x23FFFFEC
abus_data_out <= x"FE" & wr_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF7" then -- 0x23FFFFEE
abus_data_out <= x"EF" & wr_access_cntr;
elsif abus_address_latched(23 downto 0) = X"FFFFF8" then -- 0x23FFFFF0
--wasca prepare counter
abus_data_out <= REG_PCNTR;
elsif abus_address_latched(23 downto 0) = X"FFFFF9" then -- 0x23FFFFF2
--wasca status register
abus_data_out <= REG_STATUS;
elsif abus_address_latched(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
abus_data_out <= REG_MODE;
elsif abus_address_latched(23 downto 0) = X"FFFFFB" then -- 0x23FFFFF6
--wasca hwver register
abus_data_out <= REG_HWVER;
elsif abus_address_latched(23 downto 0) = X"FFFFFC" then -- 0x23FFFFF8
--wasca swver register
abus_data_out <= REG_SWVER;
elsif abus_address_latched(23 downto 0) = X"FFFFFD" then -- 0x23FFFFFA
--wasca signature "wa"
abus_data_out <= X"7761";
elsif abus_address_latched(23 downto 0) = X"FFFFFE" then
--wasca signature "sc"
abus_data_out <= X"7363";
elsif abus_address_latched(23 downto 0) = X"FFFFFF" then
--wasca signature "a "
abus_data_out <= X"6120";
else
--normal CS0 read access
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FFFF";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FFFF";
when MODE_RAM_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_KOF95 => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_ROM_ULTRAMAN => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_BOOT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
end case;
end if;
elsif abus_chipselect_latched = "01" then
--CS1 access
if ( abus_address_latched(23 downto 0) = X"FFFFFF" or abus_address_latched(23 downto 0) = X"FFFFFD" ) then
--saturn cart id register
case wasca_mode is
when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= X"FF21";
when MODE_POWER_MEMORY_1M => abus_data_out <= X"FF22";
when MODE_POWER_MEMORY_2M => abus_data_out <= X"FF23";
when MODE_POWER_MEMORY_4M => abus_data_out <= X"FF24";
when MODE_RAM_1M => abus_data_out <= X"FF5A";
when MODE_RAM_4M => abus_data_out <= X"FF5C";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
else
--normal CS1 access
case wasca_mode is
-- [DEBUG]Show which address is being accessed,
-- [DEBUG]in order to verify multiplexer wiring.
when MODE_INIT => abus_data_out <= abus_address_latched(15 downto 0);
-- Initial logic, which should be restored someday ...
--when MODE_INIT => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_05M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_1M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_2M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_POWER_MEMORY_4M => abus_data_out <= avalon_readdata(7 downto 0) & avalon_readdata (15 downto 8) ;
when MODE_RAM_1M => abus_data_out <= X"FFFF";
when MODE_RAM_4M => abus_data_out <= X"FFFF";
when MODE_ROM_KOF95 => abus_data_out <= X"FFFF";
when MODE_ROM_ULTRAMAN => abus_data_out <= X"FFFF";
when MODE_BOOT => abus_data_out <= X"FFFF";
end case;
end if;
else
--CS2 access
abus_data_out <= X"EEEE";
end if;
end if;
end if;
end process;
--if abus write access is detected, issue avalon write transaction
--disable abus wait immediately
--TODO: check if avalon_writedata is already valid at this moment
process (clock)
begin
if rising_edge(clock) then
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched /= "11" and abus_cspulse7 = '1' then
--pass write to avalon
avalon_write <= '1';
abus_waitrequest_write <= '1';
elsif avalon_waitrequest = '0' then
avalon_write <= '0';
abus_waitrequest_write <= '0';
end if;
end if;
end process;
--wasca mode register write
--reset
process (clock)
begin
if rising_edge(clock) then
--if saturn_reset='0' then wasca_mode <= MODE_INIT;
--els
-- Debug stuff around Rd/Wr access
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' then
wr_access_cntr <= wr_access_cntr + x"01";
last_wr_addr <= abus_address_latched(15 downto 0);
last_wr_data <= abus_data_in;
end if;
if my_little_transaction_dir = DIR_WRITE and abus_chipselect_latched = "00" and abus_cspulse7 = '1' and
abus_address_latched(23 downto 0) = X"FFFFFA" then -- 0x23FFFFF4
--wasca mode register
REG_MODE <= abus_data_in;
case (abus_data_in (3 downto 0)) is
when X"1" => wasca_mode <= MODE_POWER_MEMORY_05M;
when X"2" => wasca_mode <= MODE_POWER_MEMORY_1M;
when X"3" => wasca_mode <= MODE_POWER_MEMORY_2M;
when X"4" => wasca_mode <= MODE_POWER_MEMORY_4M;
when others =>
case (abus_data_in (7 downto 4)) is
when X"1" => wasca_mode <= MODE_RAM_1M;
when X"2" => wasca_mode <= MODE_RAM_4M;
when others =>
case (abus_data_in (11 downto 8)) is
when X"1" => wasca_mode <= MODE_ROM_KOF95;
when X"2" => wasca_mode <= MODE_ROM_ULTRAMAN;
when others => null;-- wasca_mode <= MODE_INIT;
end case;
end case;
end case;
end if;
end if;
end process;
abus_data_in <= abus_addressdata_buf;
--working only if direction is 1
abus_addressdata <= (others => 'Z') when abus_direction_internal='0' else
abus_data_out;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read2 <= abus_waitrequest_read;
--abus_waitrequest_read3 <= abus_waitrequest_read2;
--abus_waitrequest_read4 <= abus_waitrequest_read3;
abus_waitrequest_write2 <= abus_waitrequest_write;
--abus_waitrequest_write3 <= abus_waitrequest_write3;
--abus_waitrequest_write4 <= abus_waitrequest_write4;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
abus_waitrequest_read_off <= '0';
abus_waitrequest_write_off <= '0';
if abus_waitrequest_read = '0' and abus_waitrequest_read2 = '1' then
abus_waitrequest_read_off <= '1';
end if;
if abus_waitrequest_write = '0' and abus_waitrequest_write2 = '1' then
abus_waitrequest_write_off <= '1';
end if;
end if;
end process;
--process (clock)
--begin
-- if rising_edge(clock) then
-- --if abus_read_pulse='1' or abus_write_pulse(0)='1' or abus_write_pulse(1)='1' then
-- --if abus_anypulse = '1' then
-- if abus_chipselect_pulse(0) = '1' or abus_chipselect_pulse(1) = '1' then
-- abus_waitrequest <= '0';
-- elsif abus_waitrequest_read_off='1' or abus_waitrequest_write_off='1' then
-- abus_waitrequest <= '1';
-- end if;
-- end if;
--end process;
--avalon-to-abus mapping
--SDRAM is mapped to both CS0 and CS1
--
-- Note about address : from NIOS side, SDRAM is mapped to 0x0400_0000,
-- | so that the prefix at upper bits of the address passed to avalon.
-- | And A-Bus data width is 16 bits so that lower address bit is zeroed.
avalon_address <= "010" & abus_address_latched(23 downto 0) & "0";
avalon_writedata <= abus_data_in(7 downto 0) & abus_data_in (15 downto 8) ;
avalon_burstcount <= '0';
-- Specify which byte(s) should be written.
avalon_byteenable(0) <= not (abus_read_ms or abus_write_ms(1));
avalon_byteenable(1) <= not (abus_read_ms or abus_write_ms(0));
abus_waitrequest <= not (abus_waitrequest_read or abus_waitrequest_write);
--Nios II read interface
process (clock)
begin
if rising_edge(clock) then
avalon_nios_readdatavalid <= '0';
if avalon_nios_read = '1' then
avalon_nios_readdatavalid <= '1';
case avalon_nios_address is
-- Debug stuff around Rd/Wr access
when X"E0" =>
avalon_nios_readdata <= x"CA" & rd_access_cntr;
when X"E2" =>
avalon_nios_readdata <= x"FE" & wr_access_cntr;
when X"E4" =>
avalon_nios_readdata <= last_rd_addr;
when X"E6" =>
avalon_nios_readdata <= last_wr_addr;
when X"E8" =>
avalon_nios_readdata <= last_wr_data;
when X"F0" =>
avalon_nios_readdata <= REG_PCNTR;
when X"F2" =>
avalon_nios_readdata <= REG_STATUS;
when X"F4" =>
avalon_nios_readdata <= REG_MODE;
when X"F6" =>
avalon_nios_readdata <= REG_HWVER;
when X"F8" =>
avalon_nios_readdata <= REG_SWVER;
when X"FA" =>
avalon_nios_readdata <= X"ABCD"; --for debug, remove later
when others =>
avalon_nios_readdata <= REG_HWVER; --to simplify mux
end case;
end if;
end if;
end process;
--Nios II write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_nios_write= '1' then
case avalon_nios_address is
when X"F0" =>
REG_PCNTR <= avalon_nios_writedata;
when X"F2" =>
REG_STATUS <= avalon_nios_writedata;
when X"F4" =>
null;
when X"F6" =>
null;
when X"F8" =>
REG_SWVER <= avalon_nios_writedata;
when others =>
null;
end case;
end if;
end if;
end process;
--Nios system interface is only regs, so always ready to write.
avalon_nios_waitrequest <= '0';
end architecture rtl; -- of abus_slave
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/wasca_10m08sc_20191205_abus_divide/wasca/wasca_inst.vhd
|
1
|
8090
|
component wasca is
port (
abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
abus_slave_0_abus_read : in std_logic := 'X'; -- read
abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
abus_slave_0_abus_interrupt : out std_logic; -- interrupt
abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
abus_slave_0_abus_direction : out std_logic; -- direction
abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_slave_0_abus_disableout : out std_logic; -- disableout
abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
leds_conn_export : out std_logic_vector(3 downto 0); -- export
sdram_clkout_clk : out std_logic; -- clk
switches_conn_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
abus_slave_0_abus_address => CONNECTED_TO_abus_slave_0_abus_address, -- abus_slave_0_abus.address
abus_slave_0_abus_chipselect => CONNECTED_TO_abus_slave_0_abus_chipselect, -- .chipselect
abus_slave_0_abus_read => CONNECTED_TO_abus_slave_0_abus_read, -- .read
abus_slave_0_abus_write => CONNECTED_TO_abus_slave_0_abus_write, -- .write
abus_slave_0_abus_waitrequest => CONNECTED_TO_abus_slave_0_abus_waitrequest, -- .waitrequest
abus_slave_0_abus_interrupt => CONNECTED_TO_abus_slave_0_abus_interrupt, -- .interrupt
abus_slave_0_abus_addressdata => CONNECTED_TO_abus_slave_0_abus_addressdata, -- .addressdata
abus_slave_0_abus_direction => CONNECTED_TO_abus_slave_0_abus_direction, -- .direction
abus_slave_0_abus_muxing => CONNECTED_TO_abus_slave_0_abus_muxing, -- .muxing
abus_slave_0_abus_disableout => CONNECTED_TO_abus_slave_0_abus_disableout, -- .disableout
abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_abus_slave_0_conduit_saturn_reset_saturn_reset, -- abus_slave_0_conduit_saturn_reset.saturn_reset
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
leds_conn_export => CONNECTED_TO_leds_conn_export, -- leds_conn.export
sdram_clkout_clk => CONNECTED_TO_sdram_clkout_clk, -- sdram_clkout.clk
switches_conn_export => CONNECTED_TO_switches_conn_export, -- switches_conn.export
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
|
gpl-2.0
|
cafe-alpha/wascafe
|
v10/fpga_firmware/wasca/wasca_inst.vhd
|
1
|
12504
|
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
altpll_0_locked_conduit_export : out std_logic; -- export
altpll_0_phasedone_conduit_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- ba
external_sdram_controller_wire_cas_n : out std_logic; -- cas_n
external_sdram_controller_wire_cke : out std_logic; -- cke
external_sdram_controller_wire_cs_n : out std_logic; -- cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
external_sdram_controller_wire_ras_n : out std_logic; -- ras_n
external_sdram_controller_wire_we_n : out std_logic; -- we_n
pio_0_external_connection_export : inout std_logic_vector(3 downto 0) := (others => 'X'); -- export
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad : out std_logic; -- sd_clk_o_pad
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i : in std_logic := 'X'; -- sd_cmd_dat_i
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o : out std_logic; -- sd_cmd_oe_o
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o : out std_logic; -- sd_cmd_out_o
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i : in std_logic_vector(3 downto 0) := (others => 'X'); -- sd_dat_dat_i
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o : out std_logic; -- sd_dat_oe_o
sd_mmc_controller_0_sd_card_io_sd_dat_out_o : out std_logic_vector(3 downto 0); -- sd_dat_out_o
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := 'X'; -- read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => 'X'); -- write
sega_saturn_abus_slave_0_abus_functioncode : in std_logic_vector(1 downto 0) := (others => 'X'); -- functioncode
sega_saturn_abus_slave_0_abus_timing : in std_logic_vector(2 downto 0) := (others => 'X'); -- timing
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe : in std_logic := 'X'; -- addressstrobe
sega_saturn_abus_slave_0_abus_interrupt : out std_logic; -- interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata
sega_saturn_abus_slave_0_abus_direction : out std_logic; -- direction
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
sega_saturn_abus_slave_0_abus_disableout : out std_logic; -- disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := 'X'; -- saturn_reset
uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd
uart_0_external_connection_txd : out std_logic -- txd
);
end component wasca;
u0 : component wasca
port map (
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export => CONNECTED_TO_altpll_0_phasedone_conduit_export, -- altpll_0_phasedone_conduit.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk
external_sdram_controller_wire_addr => CONNECTED_TO_external_sdram_controller_wire_addr, -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba => CONNECTED_TO_external_sdram_controller_wire_ba, -- .ba
external_sdram_controller_wire_cas_n => CONNECTED_TO_external_sdram_controller_wire_cas_n, -- .cas_n
external_sdram_controller_wire_cke => CONNECTED_TO_external_sdram_controller_wire_cke, -- .cke
external_sdram_controller_wire_cs_n => CONNECTED_TO_external_sdram_controller_wire_cs_n, -- .cs_n
external_sdram_controller_wire_dq => CONNECTED_TO_external_sdram_controller_wire_dq, -- .dq
external_sdram_controller_wire_dqm => CONNECTED_TO_external_sdram_controller_wire_dqm, -- .dqm
external_sdram_controller_wire_ras_n => CONNECTED_TO_external_sdram_controller_wire_ras_n, -- .ras_n
external_sdram_controller_wire_we_n => CONNECTED_TO_external_sdram_controller_wire_we_n, -- .we_n
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_clk_o_pad, -- sd_mmc_controller_0_sd_card_io.sd_clk_o_pad
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i, -- .sd_cmd_dat_i
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o, -- .sd_cmd_oe_o
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_cmd_out_o, -- .sd_cmd_out_o
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_dat_i, -- .sd_dat_dat_i
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_oe_o, -- .sd_dat_oe_o
sd_mmc_controller_0_sd_card_io_sd_dat_out_o => CONNECTED_TO_sd_mmc_controller_0_sd_card_io_sd_dat_out_o, -- .sd_dat_out_o
sega_saturn_abus_slave_0_abus_address => CONNECTED_TO_sega_saturn_abus_slave_0_abus_address, -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect => CONNECTED_TO_sega_saturn_abus_slave_0_abus_chipselect, -- .chipselect
sega_saturn_abus_slave_0_abus_read => CONNECTED_TO_sega_saturn_abus_slave_0_abus_read, -- .read
sega_saturn_abus_slave_0_abus_write => CONNECTED_TO_sega_saturn_abus_slave_0_abus_write, -- .write
sega_saturn_abus_slave_0_abus_functioncode => CONNECTED_TO_sega_saturn_abus_slave_0_abus_functioncode, -- .functioncode
sega_saturn_abus_slave_0_abus_timing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_timing, -- .timing
sega_saturn_abus_slave_0_abus_waitrequest => CONNECTED_TO_sega_saturn_abus_slave_0_abus_waitrequest, -- .waitrequest
sega_saturn_abus_slave_0_abus_addressstrobe => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressstrobe, -- .addressstrobe
sega_saturn_abus_slave_0_abus_interrupt => CONNECTED_TO_sega_saturn_abus_slave_0_abus_interrupt, -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata => CONNECTED_TO_sega_saturn_abus_slave_0_abus_addressdata, -- .addressdata
sega_saturn_abus_slave_0_abus_direction => CONNECTED_TO_sega_saturn_abus_slave_0_abus_direction, -- .direction
sega_saturn_abus_slave_0_abus_muxing => CONNECTED_TO_sega_saturn_abus_slave_0_abus_muxing, -- .muxing
sega_saturn_abus_slave_0_abus_disableout => CONNECTED_TO_sega_saturn_abus_slave_0_abus_disableout, -- .disableout
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => CONNECTED_TO_sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset, -- sega_saturn_abus_slave_0_conduit_saturn_reset.saturn_reset
uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd
uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd
);
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201010_abus3/wasca_toplevel.vhd
|
2
|
18731
|
-- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_controller_wire_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(25 downto 16) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'X'; -- b_SD_cmd
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'X'; -- b_SD_dat
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'X'; -- b_SD_dat3
--altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic ; -- o_SD_clock
uart_0_external_connection_txd : out std_logic := '0'; --
uart_0_external_connection_rxd : in std_logic := 'X'; --
hex0_conn_export : out std_logic_vector(6 downto 0);
hex1_conn_export : out std_logic_vector(6 downto 0);
hex2_conn_export : out std_logic_vector(6 downto 0);
hex3_conn_export : out std_logic_vector(6 downto 0);
hex4_conn_export : out std_logic_vector(6 downto 0);
hex5_conn_export : out std_logic_vector(6 downto 0);
hexdot_conn_export : out std_logic_vector(5 downto 0);
leds_conn_export : out std_logic_vector(3 downto 0); -- leds_conn_export[0]: ledr1, leds_conn_export[1]: ledg1, leds_conn_export[2]: ledo1, leds_conn_export[3]: ledo2
extra_leds_conn_export : out std_logic_vector(4 downto 0); -- Extra LEDs for DE10-lite only, mapped to their own control register
switches_conn_export : in std_logic_vector(7 downto 0); -- switches_conn_export[0]: sw1, switches_conn_export[1]: sw2, switches_conn_export[2]: unused clock (SCSPCLK from SIM, or EXT from same board)
spi_sync_conn_export : in std_logic; -- SPI synchronization
spi_stm32_MOSI : out std_logic := '0'; -- MOSI
spi_stm32_MISO : in std_logic; -- MISO
spi_stm32_SCLK : out std_logic := '0'; -- SCLK
spi_stm32_SS_n : out std_logic := '0' -- SS_n
--audio_out_BCLK : in std_logic := '0'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
--audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'Z'); -- address
abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'Z'; -- read
abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest
abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'Z'); -- addressdata
abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'Z'); -- chipselect
abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction
abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out
abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt
abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing
abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'Z'); -- writebyteenable_n
abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'Z'; -- reset
abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr
abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba
abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n
abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke
abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n
abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'Z'); -- dq
abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n
abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n
abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk
--audio_out_BCLK : in std_logic := 'Z'; -- BCLK
--audio_out_DACDAT : out std_logic; -- DACDAT
--audio_out_DACLRCK : in std_logic := 'Z'; -- DACLRCK
clk_clk : in std_logic := 'Z'; -- clk
clock_116_mhz_clk : out std_logic; -- clk
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'Z'; -- b_SD_cmd
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'Z'; -- b_SD_dat
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'Z'; -- b_SD_dat3
--sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic ; -- o_SD_clock
uart_0_external_connection_rxd : in std_logic := '0'; -- rxd
uart_0_external_connection_txd : out std_logic; -- txd
hex0_conn_export : out std_logic_vector(6 downto 0);
hex1_conn_export : out std_logic_vector(6 downto 0);
hex2_conn_export : out std_logic_vector(6 downto 0);
hex3_conn_export : out std_logic_vector(6 downto 0);
hex4_conn_export : out std_logic_vector(6 downto 0);
hex5_conn_export : out std_logic_vector(6 downto 0);
hexdot_conn_export : out std_logic_vector(5 downto 0);
leds_conn_export : out std_logic_vector(3 downto 0);
extra_leds_conn_export : out std_logic_vector(4 downto 0);
switches_conn_export : in std_logic_vector(7 downto 0);
spi_sync_conn_export : in std_logic; -- SPI synchronization
buffered_spi_miso : in std_logic; -- MISO
buffered_spi_mosi : out std_logic := 'Z'; -- MOSI
buffered_spi_clk : out std_logic := 'Z'; -- SCLK
buffered_spi_cs : out std_logic := 'Z'; -- SS_n
reset_reset_n : in std_logic := 'Z'; -- reset_n
reset_controller_0_reset_in1_reset : in std_logic := 'Z' ; -- reset
altpll_1_areset_conduit_export : in std_logic := 'Z'; -- export
altpll_1_locked_conduit_export : out std_logic; -- export
altpll_1_phasedone_conduit_export : out std_logic -- export
);
end component;
signal altpll_1_areset_conduit_export : std_logic := '0';
signal altpll_1_locked_conduit_export : std_logic := '0';
signal altpll_1_phasedone_conduit_export : std_logic := '0';
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
signal por_counter : unsigned(31 downto 0) := (others => '0');
signal por_reset : std_logic := '0';
signal por_reset_n : std_logic := '0';
begin
--sega_saturn_abus_slave_0_abus_muxing (0) <= not sega_saturn_abus_slave_0_abus_muxing(1);
external_sdram_controller_wire_clk <= not clock_116_mhz;
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
abus_avalon_sdram_bridge_0_sdram_addr => external_sdram_controller_wire_addr,
abus_avalon_sdram_bridge_0_sdram_ba => external_sdram_controller_wire_ba,
abus_avalon_sdram_bridge_0_sdram_cas_n => external_sdram_controller_wire_cas_n,
abus_avalon_sdram_bridge_0_sdram_cke => external_sdram_controller_wire_cke,
abus_avalon_sdram_bridge_0_sdram_cs_n => external_sdram_controller_wire_cs_n,
abus_avalon_sdram_bridge_0_sdram_dq => external_sdram_controller_wire_dq,
abus_avalon_sdram_bridge_0_sdram_dqm => external_sdram_controller_wire_dqm,
abus_avalon_sdram_bridge_0_sdram_ras_n => external_sdram_controller_wire_ras_n,
abus_avalon_sdram_bridge_0_sdram_we_n => external_sdram_controller_wire_we_n,
abus_avalon_sdram_bridge_0_abus_address => sega_saturn_abus_slave_0_abus_address,
abus_avalon_sdram_bridge_0_abus_chipselect => "1"&sega_saturn_abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
abus_avalon_sdram_bridge_0_abus_read => sega_saturn_abus_slave_0_abus_read,
abus_avalon_sdram_bridge_0_abus_writebyteenable_n => sega_saturn_abus_slave_0_abus_write,
abus_avalon_sdram_bridge_0_abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest,
abus_avalon_sdram_bridge_0_abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt,
abus_avalon_sdram_bridge_0_abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata,
abus_avalon_sdram_bridge_0_abus_direction => sega_saturn_abus_slave_0_abus_direction,
abus_avalon_sdram_bridge_0_abus_muxing => sega_saturn_abus_slave_0_abus_muxing,
abus_avalon_sdram_bridge_0_abus_disable_out => sega_saturn_abus_slave_0_abus_disableout,
abus_avalon_sdram_bridge_0_abus_reset => reset_reset_n,
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3,
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat,
--altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock => altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock,
--altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd => altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd,
altpll_1_areset_conduit_export => altpll_1_areset_conduit_export,
altpll_1_locked_conduit_export => altpll_1_locked_conduit_export,
altpll_1_phasedone_conduit_export => altpll_1_phasedone_conduit_export,
uart_0_external_connection_rxd => uart_0_external_connection_rxd,
uart_0_external_connection_txd => uart_0_external_connection_txd,
hex0_conn_export => hex0_conn_export,
hex1_conn_export => hex1_conn_export,
hex2_conn_export => hex2_conn_export,
hex3_conn_export => hex3_conn_export,
hex4_conn_export => hex4_conn_export,
hex5_conn_export => hex5_conn_export,
hexdot_conn_export => hexdot_conn_export,
leds_conn_export => leds_conn_export,
extra_leds_conn_export => extra_leds_conn_export,
switches_conn_export => switches_conn_export,
spi_sync_conn_export => spi_sync_conn_export,
buffered_spi_miso => spi_stm32_MISO,
buffered_spi_mosi => spi_stm32_MOSI,
buffered_spi_clk => spi_stm32_SCLK,
buffered_spi_cs => spi_stm32_SS_n,
--audio_out_BCLK => audio_out_BCLK,
--audio_out_DACDAT => audio_out_DACDAT,
--audio_out_DACLRCK => audio_out_DACLRCK,
reset_reset_n => por_reset_n,
reset_controller_0_reset_in1_reset => por_reset
);
--empty subsystem
-- external_sdram_controller_wire_addr <= (others => 'Z');
-- external_sdram_controller_wire_ba <= (others => 'Z');
-- external_sdram_controller_wire_cas_n <= (others => 'Z');
-- external_sdram_controller_wire_cke <= (others => 'Z');
-- external_sdram_controller_wire_cs_n <= (others => 'Z');
-- external_sdram_controller_wire_dq <= (others => 'Z');
-- external_sdram_controller_wire_dqm <= (others => 'Z');
-- external_sdram_controller_wire_ras_n <= (others => 'Z');
-- external_sdram_controller_wire_we_n <= (others => 'Z');
-- external_sdram_controller_wire_clk <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_addressdata <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_waitrequest <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_interrupt <= (others => 'Z');
-- sega_saturn_abus_slave_0_abus_disableout <= '1';
-- sega_saturn_abus_slave_0_abus_muxing <= "00";
-- sega_saturn_abus_slave_0_abus_direction <= '0';
-- spi_sd_card_MOSI <= 'Z';
-- spi_sd_card_SCLK <= 'Z';
-- spi_sd_card_SS_n <= 'Z';
-- uart_0_external_connection_txd <= 'Z';
-- spi_stm32_MISO <= 'Z';
-- audio_out_DACDAT <= 'Z';
--audio_SSEL <= '1';
--sega_saturn_abus_slave_0_abus_waitrequest <= '1';
--sega_saturn_abus_slave_0_abus_direction <= '0';
--sega_saturn_abus_slave_0_abus_muxing <= "01";
--por
process (clock_116_mhz)
begin
if std_logic(por_counter(24)) = '0' then
por_counter <= por_counter + 1;
end if;
end process;
por_reset <= (std_logic(por_counter(22)));
por_reset_n <= not (std_logic(por_counter(22)));
end architecture rtl; -- of wasca_toplevel
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_Memory_Block.vhd
|
7
|
12584
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Altera_UP_SD_Card_Memory_Block.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 215 05/29/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Altera_UP_SD_Card_Memory_Block IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END Altera_UP_SD_Card_Memory_Block;
ARCHITECTURE SYN OF altera_up_sd_card_memory_block IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
init_file_layout : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clocken0 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "initial_data.mif",
init_file_layout => "PORT_A",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 4096,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 12,
width_a => 16,
width_b => 1,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clocken0 => enable_a,
clocken1 => enable_b,
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING "initial_data.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INIT_FILE STRING "initial_data.mif"
-- Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
-- Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL data_b[0..0]
-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a
-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
-- Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL q_b[0..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
-- Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/Altera_UP_SD_Card_48_bit_Command_Generator.vhd
|
7
|
25262
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module takes a command ID and data, and generates a 48-bit message for it.
-- It will first check if the command is a valid 48-bit command and produce the
-- following outputs:
-- 1. o_dataout -> a single bit output that produces the message to be sent to the
-- SD card one bit at a time. Every time the i_message_bit_out input
-- is high and the i_clock has a positive edge, a new bit is produced.
-- 2. o_message_done -> a signal that is asserted high when the entire message has been
-- produced through the o_dataout output.
-- 3. o_valid -> is a signal that is asserted high if the specified message is valid.
-- 4. o_response_type -> indicates the command response type.
-- 5. o_returning_ocr -> the response from the SD card will contain the OCR register
-- 6. o_returning_cid -> the response from the SD card will contain the CID register
-- 7. o_returning_rca -> the response from the SD card will contain the RCA register
-- 8. o_returning_csd -> the response from the SD card will contain the CSD register
-- 9. o_data_read -> asserted when the command being sent is a data read command.
-- 10. o_data_write -> asserted when the command being sent is a data write command.
-- 11. o_wait_cmd_busy -> is set high when the response to this command will be
-- followed by a busy signal.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_48_bit_Command_Generator is
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS: STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_Card_48_bit_Command_Generator is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal last_command_id : std_logic_vector(5 downto 0);
signal message_bits : std_logic_vector(39 downto 0);
signal last_command_sent_was_CMD55, valid : std_logic;
signal bit_to_send, sending_CRC, command_valid : std_logic;
signal returning_cid_reg, returning_rca_reg, returning_csd_reg, returning_dsr_reg, returning_ocr_reg, returning_status_reg : std_logic;
-- UNREGISTERED
signal temp_4_bits : std_logic_vector(3 downto 0);
signal message_done, CRC_generator_out, produce_next_bit : std_logic;
signal app_specific_valid, regular_command_valid : std_logic;
signal response_type, response_type_reg : std_logic_vector(2 downto 0);
signal cmd_argument : std_logic_vector(31 downto 0);
begin
-- This set of bits is necessary to allow the SD card to accept a VDD level for communication.
temp_4_bits <= "1111" when ((i_OCR(23) = '1') or (i_OCR(22) = '1') or (i_OCR(21) = '1') or (i_OCR(20) = '1')) else "0000";
-- Generate the bits to be sent to the SD card. These bits must pass through the CRC generator
-- to produce error checking code. The error checking code will follow the message. The message terminates with
-- a logic '1'. Total message length is 48 bits.
message_data_generator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
message_bits <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Store type of a response.
response_type_reg <= response_type;
-- Generate a message. Please note that the predefined messages are used for initialization.
-- If executed in sequence, they will initialize the SD card to work correctly. Only once these
-- instructions are completed can the data transfer begin.
case (i_predefined_message) is
when "0000" =>
-- Generate a predefined message - CMD0.
message_bits <= ("01" & COMMAND_0_GO_IDLE & "00000000000000000000000000000000");
when "0001" =>
-- Generate a predefined message - CMD55.
message_bits <= ("01" & COMMAND_55_APP_CMD & "0000000000000000" & "0000000000000000");
when "0010" =>
-- Generate a predefined message - ACMD41.
message_bits <= ("01" & ACOMMAND_41_SEND_OP_CONDITION & "0000" & temp_4_bits & "000" & i_OCR(20) & "00000000000000000000");
when "0011" =>
-- Generate a predefined message - CMD2.
message_bits <= ("01" & COMMAND_2_ALL_SEND_CID & "00000000000000000000000000000000");
when "0100" =>
-- Generate a predefined message - CMD3.
message_bits <= ("01" & COMMAND_3_SEND_RCA & "00000000000000000000000000000000");
when "0101" =>
-- Generate a predefined message - CMD9.
message_bits <= ("01" & COMMAND_9_SEND_CSD & i_RCA & "0000000000000000");
when "0110" =>
-- Generate a predefined message - CMD4.
message_bits <= ("01" & COMMAND_4_SET_DSR & i_DSR & "0000000000000000");
when "0111" =>
-- Generate a predefined message - CMD16. Set block length to 512.
message_bits <= ("01" & COMMAND_16_SET_BLOCK_LENGTH & "0000000000000000" & "0000001000000000" );
when "1000" =>
-- Generate a predefined message - CMD7. Select the card so we can access it's data.
message_bits <= ("01" & COMMAND_7_SELECT_CARD & i_RCA & "0000001000000000" );
when "1001" =>
-- Generate a predefined message - CMD13. Send SD card status.
message_bits <= ("01" & COMMAND_13_SEND_STATUS & i_RCA & "0000000000000000");
when others =>
-- Generate a custom message
message_bits <= ("01" & i_command_ID & cmd_argument);
end case;
else
-- Shift bits out as needed
if (produce_next_bit = '1') then
-- Shift message bits.
message_bits(39 downto 1) <= message_bits(38 downto 0);
message_bits(0) <= '0';
end if;
end if;
end if;
end if;
end process;
-- Generate command argument based on the command_ID. For most commands, the argument is user specified.
-- For some commands, it is necessary to send a particular SD Card register contents. Hence, these contents are
-- sent instead of the user data.
argument_generator: process (i_command_ID, last_command_sent_was_CMD55, i_generate, i_RCA, i_DSR, i_OCR, i_argument)
begin
cmd_argument <= i_argument;
if (i_generate = '1') then
case (i_command_ID) is
when COMMAND_4_SET_DSR =>
cmd_argument <= i_DSR & i_argument(15 downto 0);
when COMMAND_7_SELECT_CARD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_9_SEND_CSD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_10_SEND_CID =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_13_SEND_STATUS =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_15_GO_INACTIVE =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when COMMAND_55_APP_CMD =>
cmd_argument <= i_RCA & i_argument(15 downto 0);
when ACOMMAND_41_SEND_OP_CONDITION =>
if (last_command_sent_was_CMD55 = '1') then
cmd_argument <= i_OCR;
end if;
when others =>
cmd_argument <= i_argument;
end case;
end if;
end process;
-- Validate the message ID before sending it out.
command_validator: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
command_valid <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
if (("0" & i_predefined_message) >= ("0" & FIRST_NON_PREDEFINED_COMMAND)) then
-- Check the custom message
if (last_command_sent_was_CMD55 = '1') then
-- Check the application specific messages
command_valid <= app_specific_valid;
else
-- Check the default messages.
command_valid <= regular_command_valid;
end if;
else
-- A command is valid if the message is predefined.
command_valid <= '1';
end if;
end if;
end if;
end if;
end process;
-- Registers that indicate that the command sent will return contents of a control register.
-- The contents of the response should therefore be stored in the appropriate register.
responses_with_control_regs: process(i_clock, i_reset_n, last_command_sent_was_CMD55, last_command_id, message_done)
begin
if (i_reset_n = '0') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (rising_edge(i_clock)) then
if (i_generate = '1') then
returning_ocr_reg <= '0';
returning_cid_reg <= '0';
returning_rca_reg <= '0';
returning_csd_reg <= '0';
returning_status_reg <= '0';
elsif (message_done = '1') then
-- OCR
if ((last_command_sent_was_CMD55 = '1') and (last_command_id = ACOMMAND_41_SEND_OP_CONDITION)) then
returning_ocr_reg <= '1';
end if;
-- CID
if (last_command_id = COMMAND_2_ALL_SEND_CID) then
returning_cid_reg <= '1';
end if;
-- RCA
if (last_command_id = COMMAND_3_SEND_RCA) then
returning_rca_reg <= '1';
end if;
-- CSD
if (last_command_id = COMMAND_9_SEND_CSD) then
returning_csd_reg <= '1';
end if;
-- Status
if ((last_command_sent_was_CMD55 = '0') and (last_command_id = COMMAND_13_SEND_STATUS)) then
returning_status_reg <= '1';
end if;
end if;
end if;
end process;
-- Count the number of bits sent using a counter.
sent_bit_counter: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Reset the counter indicating the number of bits produced.
counter <= "0000000";
else
if (produce_next_bit = '1') then
-- Update the number of message bits sent.
counter <= counter + '1';
end if;
end if;
end if;
end if;
end process;
-- Select the source for the output data to be either the message data or the CRC bits.
source_selector: process(i_clock, i_reset_n, i_generate)
begin
if (i_reset_n = '0') then
sending_CRC <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
-- Set sending CRC flag to 0.
sending_CRC <= '0';
else
-- If this is the last bit being sent, then bits that follow are the CRC bits.
if (counter = "0101000") then
sending_CRC <= '1';
end if;
end if;
end if;
end if;
end process;
-- When the message is sent, store its ID. In a special case when CMD55 is sent, the next command can be an application
-- specific command. We need to check those command IDs to verify the validity of the message.
CMD55_recognizer: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter, message_done, last_command_id)
begin
if (i_reset_n = '0') then
last_command_sent_was_CMD55 <= '0';
else
if (rising_edge(i_clock)) then
if (i_generate = '0') then
-- Store the ID of the current command.
if (produce_next_bit = '1') then
if (counter = "0000000") then
last_command_id <= message_bits(37 downto 32);
end if;
end if;
-- When message has been sent then check if it was CMD55.
if (message_done = '1') then
if (last_command_id = COMMAND_55_APP_CMD) then
last_command_sent_was_CMD55 <= '1';
else
last_command_sent_was_CMD55 <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
-- Instantiate a CRC7 generator. Message bits will pass through it to create the CRC code for the message.
CRC7_Gen: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => i_message_bit_out,
i_shift => sending_CRC,
i_datain => message_bits(39),
o_dataout => CRC_generator_out
);
-- Define the source of the data produced by this module, depending on the counter value and the sending_CRC register state.
data_bit_register: process(i_clock, i_reset_n, i_generate, produce_next_bit, counter)
begin
if (i_reset_n = '0') then
bit_to_send <= '1';
else
if (rising_edge(i_clock)) then
if (i_generate = '1') then
bit_to_send <= '1';
elsif (produce_next_bit = '1') then
-- Send data to output.
if (sending_CRC = '0') then
-- Send message bits
bit_to_send <= message_bits(39);
else
-- Send CRC bits
if ((counter = "0101111") or (counter = "0110000")) then
-- At the end of CRC bits put a 1.
bit_to_send <= '1';
else
bit_to_send <= CRC_generator_out;
end if;
end if;
end if;
end if;
end if;
end process;
-- Define conditions to produce the next message bit on the module output port o_dataout.
produce_next_bit <= i_message_bit_out and (not message_done);
-- Message is done when the last bit appears at the output.
message_done <= '1' when (counter = "0110001") else '0';
-- Check the application specific messages
app_specific_valid <= '1' when (
--(i_command_ID = COMMAND_0_GO_IDLE) or
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
--(i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = ACOMMAND_41_SEND_OP_CONDITION) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
-- Check the default messages.
regular_command_valid <= '1' when (
-------------------------------------------------------
-- Disabled to prevent malfunction of the core
-------------------------------------------------------
--(i_command_ID = COMMAND_0_GO_IDLE) or
--(i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
--(i_command_ID = COMMAND_7_SELECT_CARD) or
--(i_command_ID = COMMAND_15_GO_INACTIVE) or
--(i_command_ID = COMMAND_27_PROGRAM_CSD) or
--(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
--(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
-------------------------------------------------------
(i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_3_SEND_RCA) or
(i_command_ID = COMMAND_4_SET_DSR) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
-------------------------------------------------------
-- Disabled to simplify the circuit
-------------------------------------------------------
--(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
--(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
--(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
--(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
-------------------------------------------------------
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD)
)
else '0';
response_type <= "001" when -- Wait for type 1 response when
(
(i_predefined_message = "0001") or
(i_predefined_message = "0111") or
(i_predefined_message = "1000") or
(i_predefined_message = "1001") or
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_6_SWITCH_FUNCTION) or
(i_command_ID = COMMAND_7_SELECT_CARD) or
(i_command_ID = COMMAND_12_STOP_TRANSMISSION) or
(i_command_ID = COMMAND_13_SEND_STATUS) or
(i_command_ID = COMMAND_16_SET_BLOCK_LENGTH) or
(i_command_ID = COMMAND_17_READ_BLOCK) or
(i_command_ID = COMMAND_18_READ_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_24_WRITE_BLOCK) or
(i_command_ID = COMMAND_25_WRITE_MULTIPLE_BLOCKS) or
(i_command_ID = COMMAND_27_PROGRAM_CSD) or
(i_command_ID = COMMAND_28_SET_WRITE_PROTECT) or
(i_command_ID = COMMAND_29_CLEAR_WRITE_PROTECT) or
(i_command_ID = COMMAND_30_SEND_PROTECTED_GROUPS) or
(i_command_ID = COMMAND_32_ERASE_BLOCK_START) or
(i_command_ID = COMMAND_33_ERASE_BLOCK_END) or
(i_command_ID = COMMAND_38_ERASE_SELECTED_GROUPS) or
(i_command_ID = COMMAND_42_LOCK_UNLOCK) or
(i_command_ID = COMMAND_55_APP_CMD) or
(i_command_ID = COMMAND_56_GEN_CMD) or
((last_command_sent_was_CMD55 = '1') and
((i_command_ID = ACOMMAND_6_SET_BUS_WIDTH) or
(i_command_ID = ACOMMAND_13_SD_STATUS) or
(i_command_ID = ACOMMAND_22_SEND_NUM_WR_BLOCKS) or
(i_command_ID = ACOMMAND_23_SET_BLK_ERASE_COUNT) or
(i_command_ID = ACOMMAND_42_SET_CLR_CARD_DETECT) or
(i_command_ID = ACOMMAND_51_SEND_SCR)))))
) else
"010" when -- Wait for type 2 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and
((i_command_ID = COMMAND_2_ALL_SEND_CID) or
(i_command_ID = COMMAND_9_SEND_CSD) or
(i_command_ID = COMMAND_10_SEND_CID))) or
(i_predefined_message = "0011") or
(i_predefined_message = "0101")
) else
"011" when -- Wait for type 3 response when
(
((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (last_command_sent_was_CMD55 = '1') and (i_command_ID = ACOMMAND_41_SEND_OP_CONDITION)) or
(i_predefined_message = "0010")
) else
"110" when -- Wait for type 6 response when
(((i_predefined_message = FIRST_NON_PREDEFINED_COMMAND) and (i_command_ID = COMMAND_3_SEND_RCA)) or
(i_predefined_message = "0100"))
else "000"; -- Otherwise there is no response pending.
-- Define circuit outputs
o_message_done <= message_done;
o_response_type <= response_type_reg;
o_valid <= command_valid;
o_dataout <= bit_to_send;
o_returning_ocr <= returning_ocr_reg;
o_returning_cid <= returning_cid_reg;
o_returning_rca <= returning_rca_reg;
o_returning_csd <= returning_csd_reg;
o_returning_status <= returning_status_reg;
o_data_read <= '1' when (last_command_id = COMMAND_17_READ_BLOCK) else '0';
o_data_write <= '1' when (last_command_id = COMMAND_24_WRITE_BLOCK) else '0';
o_last_cmd_was_55 <= last_command_sent_was_CMD55;
o_wait_cmd_busy <= '1' when (
(last_command_id = COMMAND_7_SELECT_CARD) or
(last_command_id = COMMAND_12_STOP_TRANSMISSION) or
(last_command_id = COMMAND_28_SET_WRITE_PROTECT) or
(last_command_id = COMMAND_29_CLEAR_WRITE_PROTECT) or
(last_command_id = COMMAND_38_ERASE_SELECTED_GROUPS))
else '0';
end rtl;
|
gpl-2.0
|
cafe-alpha/wascafe
|
v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/Altera_UP_SD_Card_Avalon_Interface.vhd
|
7
|
23187
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
-- if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
-- next_state <= s_WAIT_RELEASE;
-- else
next_state <= s_WAIT_REQUEST;
-- end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
|
gpl-2.0
|
cafe-alpha/wascafe
|
v10/fpga_firmware/wasca/synthesis/submodules/Altera_UP_SD_CRC16_Generator.vhd
|
7
|
2732
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
----------------------------------------------------------------------------------------
-- This generates the necessary 16-CRC for Command and Response
-- Implementation: serial input/parallel output
-- When input stream ends, the crcout output is the CRC checksum for them
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC16_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC16_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(15 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_sync_reset = '1') then
shift_register <= (OTHERS => '0');
elsif (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(15);
shift_register(4 downto 1) <= shift_register(3 downto 0);
shift_register(5) <= shift_register(4) XOR i_datain XOR shift_register(15);
shift_register(11 downto 6) <= shift_register(10 downto 5);
shift_register(12) <= shift_register(11) XOR i_datain XOR shift_register(15);
shift_register(15 downto 13) <= shift_register(14 downto 12);
else -- shift CRC out (no more calculation now)
shift_register(15 downto 1) <= shift_register(14 downto 0);
shift_register(0) <= '0';
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(15);
o_crcout <= shift_register;
end rtl;
|
gpl-2.0
|
dummylink/plnk_fpga-stack
|
Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/POWERLINK/src/plb_master.vhd
|
5
|
2587
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\workspace\VHDL_IP-Cores_mairt\active_hdl\compile\plb_master.vhd
-- Generated : Mon Dec 5 16:05:25 2011
-- From : C:\mairt\workspace\VHDL_IP-Cores_mairt\active_hdl\src\template\plb_master.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity plb_master is
generic(
C_MASTER_PLB_AWIDTH : INTEGER := 32;
C_MASTER_PLB_DWIDTH : INTEGER := 32
);
port(
MASTER_Clk : in STD_LOGIC;
MASTER_MAddrAck : in STD_LOGIC;
MASTER_MBusy : in STD_LOGIC;
MASTER_MErr : in STD_LOGIC;
MASTER_MRdBTerm : in STD_LOGIC;
MASTER_MRdDAck : in STD_LOGIC;
MASTER_MRearbitrate : in STD_LOGIC;
MASTER_MWrBTerm : in STD_LOGIC;
MASTER_MWrDAck : in STD_LOGIC;
MASTER_Rst : in STD_LOGIC;
MASTER_MRdDBus : in STD_LOGIC_VECTOR(C_MASTER_PLB_DWIDTH - 1 downto 0);
MASTER_MRdWdAddr : in STD_LOGIC_VECTOR(3 downto 0);
MASTER_MSSize : in STD_LOGIC_VECTOR(1 downto 0);
MASTER_RNW : out STD_LOGIC;
MASTER_abort : out STD_LOGIC;
MASTER_busLock : out STD_LOGIC;
MASTER_compress : out STD_LOGIC;
MASTER_guarded : out STD_LOGIC;
MASTER_lockErr : out STD_LOGIC;
MASTER_ordered : out STD_LOGIC;
MASTER_rdBurst : out STD_LOGIC;
MASTER_request : out STD_LOGIC;
MASTER_wrBurst : out STD_LOGIC;
MASTER_ABus : out STD_LOGIC_VECTOR(C_MASTER_PLB_AWIDTH - 1 downto 0);
MASTER_BE : out STD_LOGIC_VECTOR(C_MASTER_PLB_DWIDTH / 8 - 1 downto 0);
MASTER_MSize : out STD_LOGIC_VECTOR(1 downto 0);
MASTER_priority : out STD_LOGIC_VECTOR(1 downto 0);
MASTER_size : out STD_LOGIC_VECTOR(3 downto 0);
MASTER_type : out STD_LOGIC_VECTOR(2 downto 0);
MASTER_wrDBus : out STD_LOGIC_VECTOR(C_MASTER_PLB_DWIDTH - 1 downto 0)
);
end plb_master;
architecture template of plb_master is
begin
end template;
|
gpl-2.0
|
dummylink/plnk_fpga-stack
|
Examples/xilinx_microblaze/avnet_lx150t/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster/dma_handler.vhd
|
5
|
8009
|
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated : Wed Aug 3 13:00:54 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-28 V0.02 zelenkaj Added DMA observer
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- Added generic for DMA observer
-- 2011-12-02 V0.04 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.05 zelenkaj Reduced Dma Req overflow cnt to pulse
-- Ack done if overflow occurs
-- 2011-12-23 V0.06 zelenkaj Minor change of dma_ack generation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
|
gpl-2.0
|
dummylink/plnk_fpga-stack
|
Examples/altera_nios2/SYSTEC_ECUcore-EP3C/design_nios2_directIO/POWERLINK/src/openMAC_DMAmaster/dma_handler.vhd
|
5
|
8009
|
-------------------------------------------------------------------------------
--
-- Title : dma_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : C:\my_designs\POWERLINK\src\openMAC_DMAmaster\dma_handler.vhd
-- Generated : Wed Aug 3 13:00:54 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-11-28 V0.02 zelenkaj Added DMA observer
-- 2011-11-30 V0.03 zelenkaj Removed unnecessary ports
-- Added generic for DMA observer
-- 2011-12-02 V0.04 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.05 zelenkaj Reduced Dma Req overflow cnt to pulse
-- Ack done if overflow occurs
-- 2011-12-23 V0.06 zelenkaj Minor change of dma_ack generation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
tx_fifo_word_size_log2_g : natural := 5;
rx_fifo_word_size_log2_g : natural := 5;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
rst : in std_logic;
mac_tx_off : in std_logic;
mac_rx_off : in std_logic;
dma_req_wr : in std_logic;
dma_req_rd : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_ack_wr : out std_logic;
dma_ack_rd : out std_logic;
tx_rd_clk : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_req : out std_logic;
rx_wr_full : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
rx_wr_req : out std_logic;
rx_aclr : out std_logic;
rx_wr_clk : in std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_wr : out std_logic;
dma_new_addr_rd : out std_logic;
dma_req_overflow : in std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic
);
end dma_handler;
architecture dma_handler of dma_handler is
--clock signal
signal clk : std_logic;
--fsm
type transfer_t is (idle, first, run);
signal tx_fsm, tx_fsm_next, rx_fsm, rx_fsm_next : transfer_t := idle;
--dma signals
signal dma_ack_rd_s, dma_ack_wr_s : std_logic;
--dma observer
signal observ_rd_err, observ_wr_err : std_logic;
signal observ_rd_err_next, observ_wr_err_next : std_logic;
begin
--dma_clk, tx_rd_clk and rx_wr_clk are the same!
clk <= dma_clk; --to ease typing
rx_aclr <= rst;
process(clk, rst)
begin
if rst = '1' then
if gen_tx_fifo_g then
tx_fsm <= idle;
if gen_dma_observer_g then
observ_rd_err <= '0';
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= idle;
if gen_dma_observer_g then
observ_wr_err <= '0';
end if;
end if;
elsif clk = '1' and clk'event then
if gen_tx_fifo_g then
tx_fsm <= tx_fsm_next;
if gen_dma_observer_g then
observ_rd_err <= observ_rd_err_next;
end if;
end if;
if gen_rx_fifo_g then
rx_fsm <= rx_fsm_next;
if gen_dma_observer_g then
observ_wr_err <= observ_wr_err_next;
end if;
end if;
end if;
end process;
tx_fsm_next <= idle when gen_tx_fifo_g = false else --hang here if generic disables tx handling
first when tx_fsm = idle and dma_req_rd = '1' else
run when tx_fsm = first and dma_ack_rd_s = '1' else
idle when mac_tx_off = '1' else
tx_fsm;
rx_fsm_next <= idle when gen_rx_fifo_g = false else --hang here if generic disables rx handling
first when rx_fsm = idle and dma_req_wr = '1' else
run when rx_fsm = first else
idle when mac_rx_off = '1' else
rx_fsm;
genDmaObserver : if gen_dma_observer_g generate
begin
observ_rd_err_next <= --monoflop (deassertion with rst only)
'0' when gen_tx_fifo_g = false else
'1' when dma_req_rd = '1' and dma_ack_rd_s = '0' and dma_req_overflow = '1' else
observ_rd_err;
observ_wr_err_next <= --monoflop (deassertion with rst only)
'0' when gen_rx_fifo_g = false else
'1' when dma_req_wr = '1' and dma_ack_wr_s = '0' and dma_req_overflow = '1' else
observ_wr_err;
end generate;
dma_rd_err <= observ_rd_err;
dma_wr_err <= observ_wr_err;
--acknowledge dma request (regular or overflow)
dma_ack_rd <= dma_req_rd and (dma_ack_rd_s or dma_req_overflow);
dma_ack_wr <= dma_req_wr and (dma_ack_wr_s or dma_req_overflow);
dma_new_addr_wr <= '1' when rx_fsm = first else '0';
dma_new_addr_rd <= '1' when tx_fsm = first else '0';
process(clk, rst)
begin
if rst = '1' then
dma_addr_out <= (others => '0');
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
end if;
elsif clk = '1' and clk'event then
--if the very first address is available, store it over the whole transfer
if tx_fsm = first or rx_fsm = first then
dma_addr_out <= dma_addr;
end if;
if gen_tx_fifo_g then
tx_rd_req <= '0';
dma_ack_rd_s <= '0';
--dma request, TX fifo is not empty and not yet ack'd
if dma_req_rd = '1' and tx_rd_empty = '0' and dma_ack_rd_s = '0' then
tx_rd_req <= '1'; --read from TX fifo
dma_ack_rd_s <= '1'; --ack the read request
end if;
end if;
if gen_rx_fifo_g then
rx_wr_req <= '0';
dma_ack_wr_s <= '0';
--dma request, RX fifo is not full and not yet ack'd
if dma_req_wr = '1' and rx_wr_full = '0' and dma_ack_wr_s = '0' then
rx_wr_req <= '1'; --write to RX fifo
dma_ack_wr_s <= '1'; --ack the read request
end if;
end if;
end if;
end process;
end dma_handler;
|
gpl-2.0
|
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