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mcoughli/root_of_trust
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operational_os/hls/contact_discovery_axi_experimental/solution1/syn/vhdl/contact_discovery_AXILiteS_s_axi.vhd
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3
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30190
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-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
operation :out STD_LOGIC_VECTOR(31 downto 0);
operation_ap_vld :out STD_LOGIC;
contact_in_V :out STD_LOGIC_VECTOR(511 downto 0);
offset :out STD_LOGIC_VECTOR(63 downto 0);
db_size_in :out STD_LOGIC_VECTOR(31 downto 0);
error_out :in STD_LOGIC_VECTOR(31 downto 0);
contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0)
);
end entity contact_discovery_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of operation
-- bit 31~0 - operation[31:0] (Read/Write)
-- 0x14 : Control signal of operation
-- bit 0 - operation_ap_vld (Read/Write/SC)
-- others - reserved
-- 0x18 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[31:0] (Read/Write)
-- 0x1c : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[63:32] (Read/Write)
-- 0x20 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[95:64] (Read/Write)
-- 0x24 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[127:96] (Read/Write)
-- 0x28 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[159:128] (Read/Write)
-- 0x2c : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[191:160] (Read/Write)
-- 0x30 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[223:192] (Read/Write)
-- 0x34 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[255:224] (Read/Write)
-- 0x38 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[287:256] (Read/Write)
-- 0x3c : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[319:288] (Read/Write)
-- 0x40 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[351:320] (Read/Write)
-- 0x44 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[383:352] (Read/Write)
-- 0x48 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[415:384] (Read/Write)
-- 0x4c : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[447:416] (Read/Write)
-- 0x50 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[479:448] (Read/Write)
-- 0x54 : Data signal of contact_in_V
-- bit 31~0 - contact_in_V[511:480] (Read/Write)
-- 0x58 : reserved
-- 0x5c : Data signal of offset
-- bit 31~0 - offset[31:0] (Read/Write)
-- 0x60 : Data signal of offset
-- bit 31~0 - offset[63:32] (Read/Write)
-- 0x64 : reserved
-- 0x68 : Data signal of db_size_in
-- bit 31~0 - db_size_in[31:0] (Read/Write)
-- 0x6c : reserved
-- 0x70 : Data signal of error_out
-- bit 31~0 - error_out[31:0] (Read)
-- 0x74 : reserved
-- 0x78 : Data signal of contacts_size_out
-- bit 31~0 - contacts_size_out[31:0] (Read)
-- 0x7c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of contact_discovery_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_OPERATION_DATA_0 : INTEGER := 16#10#;
constant ADDR_OPERATION_CTRL : INTEGER := 16#14#;
constant ADDR_CONTACT_IN_V_DATA_0 : INTEGER := 16#18#;
constant ADDR_CONTACT_IN_V_DATA_1 : INTEGER := 16#1c#;
constant ADDR_CONTACT_IN_V_DATA_2 : INTEGER := 16#20#;
constant ADDR_CONTACT_IN_V_DATA_3 : INTEGER := 16#24#;
constant ADDR_CONTACT_IN_V_DATA_4 : INTEGER := 16#28#;
constant ADDR_CONTACT_IN_V_DATA_5 : INTEGER := 16#2c#;
constant ADDR_CONTACT_IN_V_DATA_6 : INTEGER := 16#30#;
constant ADDR_CONTACT_IN_V_DATA_7 : INTEGER := 16#34#;
constant ADDR_CONTACT_IN_V_DATA_8 : INTEGER := 16#38#;
constant ADDR_CONTACT_IN_V_DATA_9 : INTEGER := 16#3c#;
constant ADDR_CONTACT_IN_V_DATA_10 : INTEGER := 16#40#;
constant ADDR_CONTACT_IN_V_DATA_11 : INTEGER := 16#44#;
constant ADDR_CONTACT_IN_V_DATA_12 : INTEGER := 16#48#;
constant ADDR_CONTACT_IN_V_DATA_13 : INTEGER := 16#4c#;
constant ADDR_CONTACT_IN_V_DATA_14 : INTEGER := 16#50#;
constant ADDR_CONTACT_IN_V_DATA_15 : INTEGER := 16#54#;
constant ADDR_CONTACT_IN_V_CTRL : INTEGER := 16#58#;
constant ADDR_OFFSET_DATA_0 : INTEGER := 16#5c#;
constant ADDR_OFFSET_DATA_1 : INTEGER := 16#60#;
constant ADDR_OFFSET_CTRL : INTEGER := 16#64#;
constant ADDR_DB_SIZE_IN_DATA_0 : INTEGER := 16#68#;
constant ADDR_DB_SIZE_IN_CTRL : INTEGER := 16#6c#;
constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#70#;
constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#74#;
constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#78#;
constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#7c#;
constant ADDR_BITS : INTEGER := 7;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_operation : UNSIGNED(31 downto 0) := (others => '0');
signal int_operation_ap_vld : STD_LOGIC := '0';
signal int_contact_in_V : UNSIGNED(511 downto 0) := (others => '0');
signal int_offset : UNSIGNED(63 downto 0) := (others => '0');
signal int_db_size_in : UNSIGNED(31 downto 0) := (others => '0');
signal int_error_out : UNSIGNED(31 downto 0) := (others => '0');
signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_OPERATION_DATA_0 =>
rdata_data <= RESIZE(int_operation(31 downto 0), 32);
when ADDR_OPERATION_CTRL =>
rdata_data <= (0 => int_operation_ap_vld, others => '0');
when ADDR_CONTACT_IN_V_DATA_0 =>
rdata_data <= RESIZE(int_contact_in_V(31 downto 0), 32);
when ADDR_CONTACT_IN_V_DATA_1 =>
rdata_data <= RESIZE(int_contact_in_V(63 downto 32), 32);
when ADDR_CONTACT_IN_V_DATA_2 =>
rdata_data <= RESIZE(int_contact_in_V(95 downto 64), 32);
when ADDR_CONTACT_IN_V_DATA_3 =>
rdata_data <= RESIZE(int_contact_in_V(127 downto 96), 32);
when ADDR_CONTACT_IN_V_DATA_4 =>
rdata_data <= RESIZE(int_contact_in_V(159 downto 128), 32);
when ADDR_CONTACT_IN_V_DATA_5 =>
rdata_data <= RESIZE(int_contact_in_V(191 downto 160), 32);
when ADDR_CONTACT_IN_V_DATA_6 =>
rdata_data <= RESIZE(int_contact_in_V(223 downto 192), 32);
when ADDR_CONTACT_IN_V_DATA_7 =>
rdata_data <= RESIZE(int_contact_in_V(255 downto 224), 32);
when ADDR_CONTACT_IN_V_DATA_8 =>
rdata_data <= RESIZE(int_contact_in_V(287 downto 256), 32);
when ADDR_CONTACT_IN_V_DATA_9 =>
rdata_data <= RESIZE(int_contact_in_V(319 downto 288), 32);
when ADDR_CONTACT_IN_V_DATA_10 =>
rdata_data <= RESIZE(int_contact_in_V(351 downto 320), 32);
when ADDR_CONTACT_IN_V_DATA_11 =>
rdata_data <= RESIZE(int_contact_in_V(383 downto 352), 32);
when ADDR_CONTACT_IN_V_DATA_12 =>
rdata_data <= RESIZE(int_contact_in_V(415 downto 384), 32);
when ADDR_CONTACT_IN_V_DATA_13 =>
rdata_data <= RESIZE(int_contact_in_V(447 downto 416), 32);
when ADDR_CONTACT_IN_V_DATA_14 =>
rdata_data <= RESIZE(int_contact_in_V(479 downto 448), 32);
when ADDR_CONTACT_IN_V_DATA_15 =>
rdata_data <= RESIZE(int_contact_in_V(511 downto 480), 32);
when ADDR_OFFSET_DATA_0 =>
rdata_data <= RESIZE(int_offset(31 downto 0), 32);
when ADDR_OFFSET_DATA_1 =>
rdata_data <= RESIZE(int_offset(63 downto 32), 32);
when ADDR_DB_SIZE_IN_DATA_0 =>
rdata_data <= RESIZE(int_db_size_in(31 downto 0), 32);
when ADDR_ERROR_OUT_DATA_0 =>
rdata_data <= RESIZE(int_error_out(31 downto 0), 32);
when ADDR_CONTACTS_SIZE_OUT_DATA_0 =>
rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
operation <= STD_LOGIC_VECTOR(int_operation);
operation_ap_vld <= int_operation_ap_vld;
contact_in_V <= STD_LOGIC_VECTOR(int_contact_in_V);
offset <= STD_LOGIC_VECTOR(int_offset);
db_size_in <= STD_LOGIC_VECTOR(int_db_size_in);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then
int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_operation_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_operation_ap_vld <= '1';
else
int_operation_ap_vld <= '0'; -- self clear
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_0) then
int_contact_in_V(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_1) then
int_contact_in_V(63 downto 32) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(63 downto 32));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_2) then
int_contact_in_V(95 downto 64) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(95 downto 64));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_3) then
int_contact_in_V(127 downto 96) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(127 downto 96));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_4) then
int_contact_in_V(159 downto 128) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(159 downto 128));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_5) then
int_contact_in_V(191 downto 160) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(191 downto 160));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_6) then
int_contact_in_V(223 downto 192) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(223 downto 192));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_7) then
int_contact_in_V(255 downto 224) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(255 downto 224));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_8) then
int_contact_in_V(287 downto 256) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(287 downto 256));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_9) then
int_contact_in_V(319 downto 288) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(319 downto 288));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_10) then
int_contact_in_V(351 downto 320) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(351 downto 320));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_11) then
int_contact_in_V(383 downto 352) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(383 downto 352));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_12) then
int_contact_in_V(415 downto 384) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(415 downto 384));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_13) then
int_contact_in_V(447 downto 416) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(447 downto 416));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_14) then
int_contact_in_V(479 downto 448) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(479 downto 448));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_CONTACT_IN_V_DATA_15) then
int_contact_in_V(511 downto 480) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_contact_in_V(511 downto 480));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OFFSET_DATA_0) then
int_offset(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_offset(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OFFSET_DATA_1) then
int_offset(63 downto 32) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_offset(63 downto 32));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_DB_SIZE_IN_DATA_0) then
int_db_size_in(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_db_size_in(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_error_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_error_out <= UNSIGNED(error_out); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_contacts_size_out <= (others => '0');
elsif (ACLK_EN = '1') then
if (true) then
int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
gpl-3.0
|
mcoughli/root_of_trust
|
experiments/secure_filesystem/secure_filesystem_hls/solution1/syn/vhdl/aestest_sboxes.vhd
|
1
|
717208
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aestest_sboxes_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
addr3 : in std_logic_vector(awidth-1 downto 0);
ce3 : in std_logic;
q3 : out std_logic_vector(dwidth-1 downto 0);
addr4 : in std_logic_vector(awidth-1 downto 0);
ce4 : in std_logic;
q4 : out std_logic_vector(dwidth-1 downto 0);
addr5 : in std_logic_vector(awidth-1 downto 0);
ce5 : in std_logic;
q5 : out std_logic_vector(dwidth-1 downto 0);
addr6 : in std_logic_vector(awidth-1 downto 0);
ce6 : in std_logic;
q6 : out std_logic_vector(dwidth-1 downto 0);
addr7 : in std_logic_vector(awidth-1 downto 0);
ce7 : in std_logic;
q7 : out std_logic_vector(dwidth-1 downto 0);
addr8 : in std_logic_vector(awidth-1 downto 0);
ce8 : in std_logic;
q8 : out std_logic_vector(dwidth-1 downto 0);
addr9 : in std_logic_vector(awidth-1 downto 0);
ce9 : in std_logic;
q9 : out std_logic_vector(dwidth-1 downto 0);
addr10 : in std_logic_vector(awidth-1 downto 0);
ce10 : in std_logic;
q10 : out std_logic_vector(dwidth-1 downto 0);
addr11 : in std_logic_vector(awidth-1 downto 0);
ce11 : in std_logic;
q11 : out std_logic_vector(dwidth-1 downto 0);
addr12 : in std_logic_vector(awidth-1 downto 0);
ce12 : in std_logic;
q12 : out std_logic_vector(dwidth-1 downto 0);
addr13 : in std_logic_vector(awidth-1 downto 0);
ce13 : in std_logic;
q13 : out std_logic_vector(dwidth-1 downto 0);
addr14 : in std_logic_vector(awidth-1 downto 0);
ce14 : in std_logic;
q14 : out std_logic_vector(dwidth-1 downto 0);
addr15 : in std_logic_vector(awidth-1 downto 0);
ce15 : in std_logic;
q15 : out std_logic_vector(dwidth-1 downto 0);
addr16 : in std_logic_vector(awidth-1 downto 0);
ce16 : in std_logic;
q16 : out std_logic_vector(dwidth-1 downto 0);
addr17 : in std_logic_vector(awidth-1 downto 0);
ce17 : in std_logic;
q17 : out std_logic_vector(dwidth-1 downto 0);
addr18 : in std_logic_vector(awidth-1 downto 0);
ce18 : in std_logic;
q18 : out std_logic_vector(dwidth-1 downto 0);
addr19 : in std_logic_vector(awidth-1 downto 0);
ce19 : in std_logic;
q19 : out std_logic_vector(dwidth-1 downto 0);
addr20 : in std_logic_vector(awidth-1 downto 0);
ce20 : in std_logic;
q20 : out std_logic_vector(dwidth-1 downto 0);
addr21 : in std_logic_vector(awidth-1 downto 0);
ce21 : in std_logic;
q21 : out std_logic_vector(dwidth-1 downto 0);
addr22 : in std_logic_vector(awidth-1 downto 0);
ce22 : in std_logic;
q22 : out std_logic_vector(dwidth-1 downto 0);
addr23 : in std_logic_vector(awidth-1 downto 0);
ce23 : in std_logic;
q23 : out std_logic_vector(dwidth-1 downto 0);
addr24 : in std_logic_vector(awidth-1 downto 0);
ce24 : in std_logic;
q24 : out std_logic_vector(dwidth-1 downto 0);
addr25 : in std_logic_vector(awidth-1 downto 0);
ce25 : in std_logic;
q25 : out std_logic_vector(dwidth-1 downto 0);
addr26 : in std_logic_vector(awidth-1 downto 0);
ce26 : in std_logic;
q26 : out std_logic_vector(dwidth-1 downto 0);
addr27 : in std_logic_vector(awidth-1 downto 0);
ce27 : in std_logic;
q27 : out std_logic_vector(dwidth-1 downto 0);
addr28 : in std_logic_vector(awidth-1 downto 0);
ce28 : in std_logic;
q28 : out std_logic_vector(dwidth-1 downto 0);
addr29 : in std_logic_vector(awidth-1 downto 0);
ce29 : in std_logic;
q29 : out std_logic_vector(dwidth-1 downto 0);
addr30 : in std_logic_vector(awidth-1 downto 0);
ce30 : in std_logic;
q30 : out std_logic_vector(dwidth-1 downto 0);
addr31 : in std_logic_vector(awidth-1 downto 0);
ce31 : in std_logic;
q31 : out std_logic_vector(dwidth-1 downto 0);
addr32 : in std_logic_vector(awidth-1 downto 0);
ce32 : in std_logic;
q32 : out std_logic_vector(dwidth-1 downto 0);
addr33 : in std_logic_vector(awidth-1 downto 0);
ce33 : in std_logic;
q33 : out std_logic_vector(dwidth-1 downto 0);
addr34 : in std_logic_vector(awidth-1 downto 0);
ce34 : in std_logic;
q34 : out std_logic_vector(dwidth-1 downto 0);
addr35 : in std_logic_vector(awidth-1 downto 0);
ce35 : in std_logic;
q35 : out std_logic_vector(dwidth-1 downto 0);
addr36 : in std_logic_vector(awidth-1 downto 0);
ce36 : in std_logic;
q36 : out std_logic_vector(dwidth-1 downto 0);
addr37 : in std_logic_vector(awidth-1 downto 0);
ce37 : in std_logic;
q37 : out std_logic_vector(dwidth-1 downto 0);
addr38 : in std_logic_vector(awidth-1 downto 0);
ce38 : in std_logic;
q38 : out std_logic_vector(dwidth-1 downto 0);
addr39 : in std_logic_vector(awidth-1 downto 0);
ce39 : in std_logic;
q39 : out std_logic_vector(dwidth-1 downto 0);
addr40 : in std_logic_vector(awidth-1 downto 0);
ce40 : in std_logic;
q40 : out std_logic_vector(dwidth-1 downto 0);
addr41 : in std_logic_vector(awidth-1 downto 0);
ce41 : in std_logic;
q41 : out std_logic_vector(dwidth-1 downto 0);
addr42 : in std_logic_vector(awidth-1 downto 0);
ce42 : in std_logic;
q42 : out std_logic_vector(dwidth-1 downto 0);
addr43 : in std_logic_vector(awidth-1 downto 0);
ce43 : in std_logic;
q43 : out std_logic_vector(dwidth-1 downto 0);
addr44 : in std_logic_vector(awidth-1 downto 0);
ce44 : in std_logic;
q44 : out std_logic_vector(dwidth-1 downto 0);
addr45 : in std_logic_vector(awidth-1 downto 0);
ce45 : in std_logic;
q45 : out std_logic_vector(dwidth-1 downto 0);
addr46 : in std_logic_vector(awidth-1 downto 0);
ce46 : in std_logic;
q46 : out std_logic_vector(dwidth-1 downto 0);
addr47 : in std_logic_vector(awidth-1 downto 0);
ce47 : in std_logic;
q47 : out std_logic_vector(dwidth-1 downto 0);
addr48 : in std_logic_vector(awidth-1 downto 0);
ce48 : in std_logic;
q48 : out std_logic_vector(dwidth-1 downto 0);
addr49 : in std_logic_vector(awidth-1 downto 0);
ce49 : in std_logic;
q49 : out std_logic_vector(dwidth-1 downto 0);
addr50 : in std_logic_vector(awidth-1 downto 0);
ce50 : in std_logic;
q50 : out std_logic_vector(dwidth-1 downto 0);
addr51 : in std_logic_vector(awidth-1 downto 0);
ce51 : in std_logic;
q51 : out std_logic_vector(dwidth-1 downto 0);
addr52 : in std_logic_vector(awidth-1 downto 0);
ce52 : in std_logic;
q52 : out std_logic_vector(dwidth-1 downto 0);
addr53 : in std_logic_vector(awidth-1 downto 0);
ce53 : in std_logic;
q53 : out std_logic_vector(dwidth-1 downto 0);
addr54 : in std_logic_vector(awidth-1 downto 0);
ce54 : in std_logic;
q54 : out std_logic_vector(dwidth-1 downto 0);
addr55 : in std_logic_vector(awidth-1 downto 0);
ce55 : in std_logic;
q55 : out std_logic_vector(dwidth-1 downto 0);
addr56 : in std_logic_vector(awidth-1 downto 0);
ce56 : in std_logic;
q56 : out std_logic_vector(dwidth-1 downto 0);
addr57 : in std_logic_vector(awidth-1 downto 0);
ce57 : in std_logic;
q57 : out std_logic_vector(dwidth-1 downto 0);
addr58 : in std_logic_vector(awidth-1 downto 0);
ce58 : in std_logic;
q58 : out std_logic_vector(dwidth-1 downto 0);
addr59 : in std_logic_vector(awidth-1 downto 0);
ce59 : in std_logic;
q59 : out std_logic_vector(dwidth-1 downto 0);
addr60 : in std_logic_vector(awidth-1 downto 0);
ce60 : in std_logic;
q60 : out std_logic_vector(dwidth-1 downto 0);
addr61 : in std_logic_vector(awidth-1 downto 0);
ce61 : in std_logic;
q61 : out std_logic_vector(dwidth-1 downto 0);
addr62 : in std_logic_vector(awidth-1 downto 0);
ce62 : in std_logic;
q62 : out std_logic_vector(dwidth-1 downto 0);
addr63 : in std_logic_vector(awidth-1 downto 0);
ce63 : in std_logic;
q63 : out std_logic_vector(dwidth-1 downto 0);
addr64 : in std_logic_vector(awidth-1 downto 0);
ce64 : in std_logic;
q64 : out std_logic_vector(dwidth-1 downto 0);
addr65 : in std_logic_vector(awidth-1 downto 0);
ce65 : in std_logic;
q65 : out std_logic_vector(dwidth-1 downto 0);
addr66 : in std_logic_vector(awidth-1 downto 0);
ce66 : in std_logic;
q66 : out std_logic_vector(dwidth-1 downto 0);
addr67 : in std_logic_vector(awidth-1 downto 0);
ce67 : in std_logic;
q67 : out std_logic_vector(dwidth-1 downto 0);
addr68 : in std_logic_vector(awidth-1 downto 0);
ce68 : in std_logic;
q68 : out std_logic_vector(dwidth-1 downto 0);
addr69 : in std_logic_vector(awidth-1 downto 0);
ce69 : in std_logic;
q69 : out std_logic_vector(dwidth-1 downto 0);
addr70 : in std_logic_vector(awidth-1 downto 0);
ce70 : in std_logic;
q70 : out std_logic_vector(dwidth-1 downto 0);
addr71 : in std_logic_vector(awidth-1 downto 0);
ce71 : in std_logic;
q71 : out std_logic_vector(dwidth-1 downto 0);
addr72 : in std_logic_vector(awidth-1 downto 0);
ce72 : in std_logic;
q72 : out std_logic_vector(dwidth-1 downto 0);
addr73 : in std_logic_vector(awidth-1 downto 0);
ce73 : in std_logic;
q73 : out std_logic_vector(dwidth-1 downto 0);
addr74 : in std_logic_vector(awidth-1 downto 0);
ce74 : in std_logic;
q74 : out std_logic_vector(dwidth-1 downto 0);
addr75 : in std_logic_vector(awidth-1 downto 0);
ce75 : in std_logic;
q75 : out std_logic_vector(dwidth-1 downto 0);
addr76 : in std_logic_vector(awidth-1 downto 0);
ce76 : in std_logic;
q76 : out std_logic_vector(dwidth-1 downto 0);
addr77 : in std_logic_vector(awidth-1 downto 0);
ce77 : in std_logic;
q77 : out std_logic_vector(dwidth-1 downto 0);
addr78 : in std_logic_vector(awidth-1 downto 0);
ce78 : in std_logic;
q78 : out std_logic_vector(dwidth-1 downto 0);
addr79 : in std_logic_vector(awidth-1 downto 0);
ce79 : in std_logic;
q79 : out std_logic_vector(dwidth-1 downto 0);
addr80 : in std_logic_vector(awidth-1 downto 0);
ce80 : in std_logic;
q80 : out std_logic_vector(dwidth-1 downto 0);
addr81 : in std_logic_vector(awidth-1 downto 0);
ce81 : in std_logic;
q81 : out std_logic_vector(dwidth-1 downto 0);
addr82 : in std_logic_vector(awidth-1 downto 0);
ce82 : in std_logic;
q82 : out std_logic_vector(dwidth-1 downto 0);
addr83 : in std_logic_vector(awidth-1 downto 0);
ce83 : in std_logic;
q83 : out std_logic_vector(dwidth-1 downto 0);
addr84 : in std_logic_vector(awidth-1 downto 0);
ce84 : in std_logic;
q84 : out std_logic_vector(dwidth-1 downto 0);
addr85 : in std_logic_vector(awidth-1 downto 0);
ce85 : in std_logic;
q85 : out std_logic_vector(dwidth-1 downto 0);
addr86 : in std_logic_vector(awidth-1 downto 0);
ce86 : in std_logic;
q86 : out std_logic_vector(dwidth-1 downto 0);
addr87 : in std_logic_vector(awidth-1 downto 0);
ce87 : in std_logic;
q87 : out std_logic_vector(dwidth-1 downto 0);
addr88 : in std_logic_vector(awidth-1 downto 0);
ce88 : in std_logic;
q88 : out std_logic_vector(dwidth-1 downto 0);
addr89 : in std_logic_vector(awidth-1 downto 0);
ce89 : in std_logic;
q89 : out std_logic_vector(dwidth-1 downto 0);
addr90 : in std_logic_vector(awidth-1 downto 0);
ce90 : in std_logic;
q90 : out std_logic_vector(dwidth-1 downto 0);
addr91 : in std_logic_vector(awidth-1 downto 0);
ce91 : in std_logic;
q91 : out std_logic_vector(dwidth-1 downto 0);
addr92 : in std_logic_vector(awidth-1 downto 0);
ce92 : in std_logic;
q92 : out std_logic_vector(dwidth-1 downto 0);
addr93 : in std_logic_vector(awidth-1 downto 0);
ce93 : in std_logic;
q93 : out std_logic_vector(dwidth-1 downto 0);
addr94 : in std_logic_vector(awidth-1 downto 0);
ce94 : in std_logic;
q94 : out std_logic_vector(dwidth-1 downto 0);
addr95 : in std_logic_vector(awidth-1 downto 0);
ce95 : in std_logic;
q95 : out std_logic_vector(dwidth-1 downto 0);
addr96 : in std_logic_vector(awidth-1 downto 0);
ce96 : in std_logic;
q96 : out std_logic_vector(dwidth-1 downto 0);
addr97 : in std_logic_vector(awidth-1 downto 0);
ce97 : in std_logic;
q97 : out std_logic_vector(dwidth-1 downto 0);
addr98 : in std_logic_vector(awidth-1 downto 0);
ce98 : in std_logic;
q98 : out std_logic_vector(dwidth-1 downto 0);
addr99 : in std_logic_vector(awidth-1 downto 0);
ce99 : in std_logic;
q99 : out std_logic_vector(dwidth-1 downto 0);
addr100 : in std_logic_vector(awidth-1 downto 0);
ce100 : in std_logic;
q100 : out std_logic_vector(dwidth-1 downto 0);
addr101 : in std_logic_vector(awidth-1 downto 0);
ce101 : in std_logic;
q101 : out std_logic_vector(dwidth-1 downto 0);
addr102 : in std_logic_vector(awidth-1 downto 0);
ce102 : in std_logic;
q102 : out std_logic_vector(dwidth-1 downto 0);
addr103 : in std_logic_vector(awidth-1 downto 0);
ce103 : in std_logic;
q103 : out std_logic_vector(dwidth-1 downto 0);
addr104 : in std_logic_vector(awidth-1 downto 0);
ce104 : in std_logic;
q104 : out std_logic_vector(dwidth-1 downto 0);
addr105 : in std_logic_vector(awidth-1 downto 0);
ce105 : in std_logic;
q105 : out std_logic_vector(dwidth-1 downto 0);
addr106 : in std_logic_vector(awidth-1 downto 0);
ce106 : in std_logic;
q106 : out std_logic_vector(dwidth-1 downto 0);
addr107 : in std_logic_vector(awidth-1 downto 0);
ce107 : in std_logic;
q107 : out std_logic_vector(dwidth-1 downto 0);
addr108 : in std_logic_vector(awidth-1 downto 0);
ce108 : in std_logic;
q108 : out std_logic_vector(dwidth-1 downto 0);
addr109 : in std_logic_vector(awidth-1 downto 0);
ce109 : in std_logic;
q109 : out std_logic_vector(dwidth-1 downto 0);
addr110 : in std_logic_vector(awidth-1 downto 0);
ce110 : in std_logic;
q110 : out std_logic_vector(dwidth-1 downto 0);
addr111 : in std_logic_vector(awidth-1 downto 0);
ce111 : in std_logic;
q111 : out std_logic_vector(dwidth-1 downto 0);
addr112 : in std_logic_vector(awidth-1 downto 0);
ce112 : in std_logic;
q112 : out std_logic_vector(dwidth-1 downto 0);
addr113 : in std_logic_vector(awidth-1 downto 0);
ce113 : in std_logic;
q113 : out std_logic_vector(dwidth-1 downto 0);
addr114 : in std_logic_vector(awidth-1 downto 0);
ce114 : in std_logic;
q114 : out std_logic_vector(dwidth-1 downto 0);
addr115 : in std_logic_vector(awidth-1 downto 0);
ce115 : in std_logic;
q115 : out std_logic_vector(dwidth-1 downto 0);
addr116 : in std_logic_vector(awidth-1 downto 0);
ce116 : in std_logic;
q116 : out std_logic_vector(dwidth-1 downto 0);
addr117 : in std_logic_vector(awidth-1 downto 0);
ce117 : in std_logic;
q117 : out std_logic_vector(dwidth-1 downto 0);
addr118 : in std_logic_vector(awidth-1 downto 0);
ce118 : in std_logic;
q118 : out std_logic_vector(dwidth-1 downto 0);
addr119 : in std_logic_vector(awidth-1 downto 0);
ce119 : in std_logic;
q119 : out std_logic_vector(dwidth-1 downto 0);
addr120 : in std_logic_vector(awidth-1 downto 0);
ce120 : in std_logic;
q120 : out std_logic_vector(dwidth-1 downto 0);
addr121 : in std_logic_vector(awidth-1 downto 0);
ce121 : in std_logic;
q121 : out std_logic_vector(dwidth-1 downto 0);
addr122 : in std_logic_vector(awidth-1 downto 0);
ce122 : in std_logic;
q122 : out std_logic_vector(dwidth-1 downto 0);
addr123 : in std_logic_vector(awidth-1 downto 0);
ce123 : in std_logic;
q123 : out std_logic_vector(dwidth-1 downto 0);
addr124 : in std_logic_vector(awidth-1 downto 0);
ce124 : in std_logic;
q124 : out std_logic_vector(dwidth-1 downto 0);
addr125 : in std_logic_vector(awidth-1 downto 0);
ce125 : in std_logic;
q125 : out std_logic_vector(dwidth-1 downto 0);
addr126 : in std_logic_vector(awidth-1 downto 0);
ce126 : in std_logic;
q126 : out std_logic_vector(dwidth-1 downto 0);
addr127 : in std_logic_vector(awidth-1 downto 0);
ce127 : in std_logic;
q127 : out std_logic_vector(dwidth-1 downto 0);
addr128 : in std_logic_vector(awidth-1 downto 0);
ce128 : in std_logic;
q128 : out std_logic_vector(dwidth-1 downto 0);
addr129 : in std_logic_vector(awidth-1 downto 0);
ce129 : in std_logic;
q129 : out std_logic_vector(dwidth-1 downto 0);
addr130 : in std_logic_vector(awidth-1 downto 0);
ce130 : in std_logic;
q130 : out std_logic_vector(dwidth-1 downto 0);
addr131 : in std_logic_vector(awidth-1 downto 0);
ce131 : in std_logic;
q131 : out std_logic_vector(dwidth-1 downto 0);
addr132 : in std_logic_vector(awidth-1 downto 0);
ce132 : in std_logic;
q132 : out std_logic_vector(dwidth-1 downto 0);
addr133 : in std_logic_vector(awidth-1 downto 0);
ce133 : in std_logic;
q133 : out std_logic_vector(dwidth-1 downto 0);
addr134 : in std_logic_vector(awidth-1 downto 0);
ce134 : in std_logic;
q134 : out std_logic_vector(dwidth-1 downto 0);
addr135 : in std_logic_vector(awidth-1 downto 0);
ce135 : in std_logic;
q135 : out std_logic_vector(dwidth-1 downto 0);
addr136 : in std_logic_vector(awidth-1 downto 0);
ce136 : in std_logic;
q136 : out std_logic_vector(dwidth-1 downto 0);
addr137 : in std_logic_vector(awidth-1 downto 0);
ce137 : in std_logic;
q137 : out std_logic_vector(dwidth-1 downto 0);
addr138 : in std_logic_vector(awidth-1 downto 0);
ce138 : in std_logic;
q138 : out std_logic_vector(dwidth-1 downto 0);
addr139 : in std_logic_vector(awidth-1 downto 0);
ce139 : in std_logic;
q139 : out std_logic_vector(dwidth-1 downto 0);
addr140 : in std_logic_vector(awidth-1 downto 0);
ce140 : in std_logic;
q140 : out std_logic_vector(dwidth-1 downto 0);
addr141 : in std_logic_vector(awidth-1 downto 0);
ce141 : in std_logic;
q141 : out std_logic_vector(dwidth-1 downto 0);
addr142 : in std_logic_vector(awidth-1 downto 0);
ce142 : in std_logic;
q142 : out std_logic_vector(dwidth-1 downto 0);
addr143 : in std_logic_vector(awidth-1 downto 0);
ce143 : in std_logic;
q143 : out std_logic_vector(dwidth-1 downto 0);
addr144 : in std_logic_vector(awidth-1 downto 0);
ce144 : in std_logic;
q144 : out std_logic_vector(dwidth-1 downto 0);
addr145 : in std_logic_vector(awidth-1 downto 0);
ce145 : in std_logic;
q145 : out std_logic_vector(dwidth-1 downto 0);
addr146 : in std_logic_vector(awidth-1 downto 0);
ce146 : in std_logic;
q146 : out std_logic_vector(dwidth-1 downto 0);
addr147 : in std_logic_vector(awidth-1 downto 0);
ce147 : in std_logic;
q147 : out std_logic_vector(dwidth-1 downto 0);
addr148 : in std_logic_vector(awidth-1 downto 0);
ce148 : in std_logic;
q148 : out std_logic_vector(dwidth-1 downto 0);
addr149 : in std_logic_vector(awidth-1 downto 0);
ce149 : in std_logic;
q149 : out std_logic_vector(dwidth-1 downto 0);
addr150 : in std_logic_vector(awidth-1 downto 0);
ce150 : in std_logic;
q150 : out std_logic_vector(dwidth-1 downto 0);
addr151 : in std_logic_vector(awidth-1 downto 0);
ce151 : in std_logic;
q151 : out std_logic_vector(dwidth-1 downto 0);
addr152 : in std_logic_vector(awidth-1 downto 0);
ce152 : in std_logic;
q152 : out std_logic_vector(dwidth-1 downto 0);
addr153 : in std_logic_vector(awidth-1 downto 0);
ce153 : in std_logic;
q153 : out std_logic_vector(dwidth-1 downto 0);
addr154 : in std_logic_vector(awidth-1 downto 0);
ce154 : in std_logic;
q154 : out std_logic_vector(dwidth-1 downto 0);
addr155 : in std_logic_vector(awidth-1 downto 0);
ce155 : in std_logic;
q155 : out std_logic_vector(dwidth-1 downto 0);
addr156 : in std_logic_vector(awidth-1 downto 0);
ce156 : in std_logic;
q156 : out std_logic_vector(dwidth-1 downto 0);
addr157 : in std_logic_vector(awidth-1 downto 0);
ce157 : in std_logic;
q157 : out std_logic_vector(dwidth-1 downto 0);
addr158 : in std_logic_vector(awidth-1 downto 0);
ce158 : in std_logic;
q158 : out std_logic_vector(dwidth-1 downto 0);
addr159 : in std_logic_vector(awidth-1 downto 0);
ce159 : in std_logic;
q159 : out std_logic_vector(dwidth-1 downto 0);
addr160 : in std_logic_vector(awidth-1 downto 0);
ce160 : in std_logic;
q160 : out std_logic_vector(dwidth-1 downto 0);
addr161 : in std_logic_vector(awidth-1 downto 0);
ce161 : in std_logic;
q161 : out std_logic_vector(dwidth-1 downto 0);
addr162 : in std_logic_vector(awidth-1 downto 0);
ce162 : in std_logic;
q162 : out std_logic_vector(dwidth-1 downto 0);
addr163 : in std_logic_vector(awidth-1 downto 0);
ce163 : in std_logic;
q163 : out std_logic_vector(dwidth-1 downto 0);
addr164 : in std_logic_vector(awidth-1 downto 0);
ce164 : in std_logic;
q164 : out std_logic_vector(dwidth-1 downto 0);
addr165 : in std_logic_vector(awidth-1 downto 0);
ce165 : in std_logic;
q165 : out std_logic_vector(dwidth-1 downto 0);
addr166 : in std_logic_vector(awidth-1 downto 0);
ce166 : in std_logic;
q166 : out std_logic_vector(dwidth-1 downto 0);
addr167 : in std_logic_vector(awidth-1 downto 0);
ce167 : in std_logic;
q167 : out std_logic_vector(dwidth-1 downto 0);
addr168 : in std_logic_vector(awidth-1 downto 0);
ce168 : in std_logic;
q168 : out std_logic_vector(dwidth-1 downto 0);
addr169 : in std_logic_vector(awidth-1 downto 0);
ce169 : in std_logic;
q169 : out std_logic_vector(dwidth-1 downto 0);
addr170 : in std_logic_vector(awidth-1 downto 0);
ce170 : in std_logic;
q170 : out std_logic_vector(dwidth-1 downto 0);
addr171 : in std_logic_vector(awidth-1 downto 0);
ce171 : in std_logic;
q171 : out std_logic_vector(dwidth-1 downto 0);
addr172 : in std_logic_vector(awidth-1 downto 0);
ce172 : in std_logic;
q172 : out std_logic_vector(dwidth-1 downto 0);
addr173 : in std_logic_vector(awidth-1 downto 0);
ce173 : in std_logic;
q173 : out std_logic_vector(dwidth-1 downto 0);
addr174 : in std_logic_vector(awidth-1 downto 0);
ce174 : in std_logic;
q174 : out std_logic_vector(dwidth-1 downto 0);
addr175 : in std_logic_vector(awidth-1 downto 0);
ce175 : in std_logic;
q175 : out std_logic_vector(dwidth-1 downto 0);
addr176 : in std_logic_vector(awidth-1 downto 0);
ce176 : in std_logic;
q176 : out std_logic_vector(dwidth-1 downto 0);
addr177 : in std_logic_vector(awidth-1 downto 0);
ce177 : in std_logic;
q177 : out std_logic_vector(dwidth-1 downto 0);
addr178 : in std_logic_vector(awidth-1 downto 0);
ce178 : in std_logic;
q178 : out std_logic_vector(dwidth-1 downto 0);
addr179 : in std_logic_vector(awidth-1 downto 0);
ce179 : in std_logic;
q179 : out std_logic_vector(dwidth-1 downto 0);
addr180 : in std_logic_vector(awidth-1 downto 0);
ce180 : in std_logic;
q180 : out std_logic_vector(dwidth-1 downto 0);
addr181 : in std_logic_vector(awidth-1 downto 0);
ce181 : in std_logic;
q181 : out std_logic_vector(dwidth-1 downto 0);
addr182 : in std_logic_vector(awidth-1 downto 0);
ce182 : in std_logic;
q182 : out std_logic_vector(dwidth-1 downto 0);
addr183 : in std_logic_vector(awidth-1 downto 0);
ce183 : in std_logic;
q183 : out std_logic_vector(dwidth-1 downto 0);
addr184 : in std_logic_vector(awidth-1 downto 0);
ce184 : in std_logic;
q184 : out std_logic_vector(dwidth-1 downto 0);
addr185 : in std_logic_vector(awidth-1 downto 0);
ce185 : in std_logic;
q185 : out std_logic_vector(dwidth-1 downto 0);
addr186 : in std_logic_vector(awidth-1 downto 0);
ce186 : in std_logic;
q186 : out std_logic_vector(dwidth-1 downto 0);
addr187 : in std_logic_vector(awidth-1 downto 0);
ce187 : in std_logic;
q187 : out std_logic_vector(dwidth-1 downto 0);
addr188 : in std_logic_vector(awidth-1 downto 0);
ce188 : in std_logic;
q188 : out std_logic_vector(dwidth-1 downto 0);
addr189 : in std_logic_vector(awidth-1 downto 0);
ce189 : in std_logic;
q189 : out std_logic_vector(dwidth-1 downto 0);
addr190 : in std_logic_vector(awidth-1 downto 0);
ce190 : in std_logic;
q190 : out std_logic_vector(dwidth-1 downto 0);
addr191 : in std_logic_vector(awidth-1 downto 0);
ce191 : in std_logic;
q191 : out std_logic_vector(dwidth-1 downto 0);
addr192 : in std_logic_vector(awidth-1 downto 0);
ce192 : in std_logic;
q192 : out std_logic_vector(dwidth-1 downto 0);
addr193 : in std_logic_vector(awidth-1 downto 0);
ce193 : in std_logic;
q193 : out std_logic_vector(dwidth-1 downto 0);
addr194 : in std_logic_vector(awidth-1 downto 0);
ce194 : in std_logic;
q194 : out std_logic_vector(dwidth-1 downto 0);
addr195 : in std_logic_vector(awidth-1 downto 0);
ce195 : in std_logic;
q195 : out std_logic_vector(dwidth-1 downto 0);
addr196 : in std_logic_vector(awidth-1 downto 0);
ce196 : in std_logic;
q196 : out std_logic_vector(dwidth-1 downto 0);
addr197 : in std_logic_vector(awidth-1 downto 0);
ce197 : in std_logic;
q197 : out std_logic_vector(dwidth-1 downto 0);
addr198 : in std_logic_vector(awidth-1 downto 0);
ce198 : in std_logic;
q198 : out std_logic_vector(dwidth-1 downto 0);
addr199 : in std_logic_vector(awidth-1 downto 0);
ce199 : in std_logic;
q199 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of aestest_sboxes_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
signal addr3_tmp : std_logic_vector(awidth-1 downto 0);
signal addr4_tmp : std_logic_vector(awidth-1 downto 0);
signal addr5_tmp : std_logic_vector(awidth-1 downto 0);
signal addr6_tmp : std_logic_vector(awidth-1 downto 0);
signal addr7_tmp : std_logic_vector(awidth-1 downto 0);
signal addr8_tmp : std_logic_vector(awidth-1 downto 0);
signal addr9_tmp : std_logic_vector(awidth-1 downto 0);
signal addr10_tmp : std_logic_vector(awidth-1 downto 0);
signal addr11_tmp : std_logic_vector(awidth-1 downto 0);
signal addr12_tmp : std_logic_vector(awidth-1 downto 0);
signal addr13_tmp : std_logic_vector(awidth-1 downto 0);
signal addr14_tmp : std_logic_vector(awidth-1 downto 0);
signal addr15_tmp : std_logic_vector(awidth-1 downto 0);
signal addr16_tmp : std_logic_vector(awidth-1 downto 0);
signal addr17_tmp : std_logic_vector(awidth-1 downto 0);
signal addr18_tmp : std_logic_vector(awidth-1 downto 0);
signal addr19_tmp : std_logic_vector(awidth-1 downto 0);
signal addr20_tmp : std_logic_vector(awidth-1 downto 0);
signal addr21_tmp : std_logic_vector(awidth-1 downto 0);
signal addr22_tmp : std_logic_vector(awidth-1 downto 0);
signal addr23_tmp : std_logic_vector(awidth-1 downto 0);
signal addr24_tmp : std_logic_vector(awidth-1 downto 0);
signal addr25_tmp : std_logic_vector(awidth-1 downto 0);
signal addr26_tmp : std_logic_vector(awidth-1 downto 0);
signal addr27_tmp : std_logic_vector(awidth-1 downto 0);
signal addr28_tmp : std_logic_vector(awidth-1 downto 0);
signal addr29_tmp : std_logic_vector(awidth-1 downto 0);
signal addr30_tmp : std_logic_vector(awidth-1 downto 0);
signal addr31_tmp : std_logic_vector(awidth-1 downto 0);
signal addr32_tmp : std_logic_vector(awidth-1 downto 0);
signal addr33_tmp : std_logic_vector(awidth-1 downto 0);
signal addr34_tmp : std_logic_vector(awidth-1 downto 0);
signal addr35_tmp : std_logic_vector(awidth-1 downto 0);
signal addr36_tmp : std_logic_vector(awidth-1 downto 0);
signal addr37_tmp : std_logic_vector(awidth-1 downto 0);
signal addr38_tmp : std_logic_vector(awidth-1 downto 0);
signal addr39_tmp : std_logic_vector(awidth-1 downto 0);
signal addr40_tmp : std_logic_vector(awidth-1 downto 0);
signal addr41_tmp : std_logic_vector(awidth-1 downto 0);
signal addr42_tmp : std_logic_vector(awidth-1 downto 0);
signal addr43_tmp : std_logic_vector(awidth-1 downto 0);
signal addr44_tmp : std_logic_vector(awidth-1 downto 0);
signal addr45_tmp : std_logic_vector(awidth-1 downto 0);
signal addr46_tmp : std_logic_vector(awidth-1 downto 0);
signal addr47_tmp : std_logic_vector(awidth-1 downto 0);
signal addr48_tmp : std_logic_vector(awidth-1 downto 0);
signal addr49_tmp : std_logic_vector(awidth-1 downto 0);
signal addr50_tmp : std_logic_vector(awidth-1 downto 0);
signal addr51_tmp : std_logic_vector(awidth-1 downto 0);
signal addr52_tmp : std_logic_vector(awidth-1 downto 0);
signal addr53_tmp : std_logic_vector(awidth-1 downto 0);
signal addr54_tmp : std_logic_vector(awidth-1 downto 0);
signal addr55_tmp : std_logic_vector(awidth-1 downto 0);
signal addr56_tmp : std_logic_vector(awidth-1 downto 0);
signal addr57_tmp : std_logic_vector(awidth-1 downto 0);
signal addr58_tmp : std_logic_vector(awidth-1 downto 0);
signal addr59_tmp : std_logic_vector(awidth-1 downto 0);
signal addr60_tmp : std_logic_vector(awidth-1 downto 0);
signal addr61_tmp : std_logic_vector(awidth-1 downto 0);
signal addr62_tmp : std_logic_vector(awidth-1 downto 0);
signal addr63_tmp : std_logic_vector(awidth-1 downto 0);
signal addr64_tmp : std_logic_vector(awidth-1 downto 0);
signal addr65_tmp : std_logic_vector(awidth-1 downto 0);
signal addr66_tmp : std_logic_vector(awidth-1 downto 0);
signal addr67_tmp : std_logic_vector(awidth-1 downto 0);
signal addr68_tmp : std_logic_vector(awidth-1 downto 0);
signal addr69_tmp : std_logic_vector(awidth-1 downto 0);
signal addr70_tmp : std_logic_vector(awidth-1 downto 0);
signal addr71_tmp : std_logic_vector(awidth-1 downto 0);
signal addr72_tmp : std_logic_vector(awidth-1 downto 0);
signal addr73_tmp : std_logic_vector(awidth-1 downto 0);
signal addr74_tmp : std_logic_vector(awidth-1 downto 0);
signal addr75_tmp : std_logic_vector(awidth-1 downto 0);
signal addr76_tmp : std_logic_vector(awidth-1 downto 0);
signal addr77_tmp : std_logic_vector(awidth-1 downto 0);
signal addr78_tmp : std_logic_vector(awidth-1 downto 0);
signal addr79_tmp : std_logic_vector(awidth-1 downto 0);
signal addr80_tmp : std_logic_vector(awidth-1 downto 0);
signal addr81_tmp : std_logic_vector(awidth-1 downto 0);
signal addr82_tmp : std_logic_vector(awidth-1 downto 0);
signal addr83_tmp : std_logic_vector(awidth-1 downto 0);
signal addr84_tmp : std_logic_vector(awidth-1 downto 0);
signal addr85_tmp : std_logic_vector(awidth-1 downto 0);
signal addr86_tmp : std_logic_vector(awidth-1 downto 0);
signal addr87_tmp : std_logic_vector(awidth-1 downto 0);
signal addr88_tmp : std_logic_vector(awidth-1 downto 0);
signal addr89_tmp : std_logic_vector(awidth-1 downto 0);
signal addr90_tmp : std_logic_vector(awidth-1 downto 0);
signal addr91_tmp : std_logic_vector(awidth-1 downto 0);
signal addr92_tmp : std_logic_vector(awidth-1 downto 0);
signal addr93_tmp : std_logic_vector(awidth-1 downto 0);
signal addr94_tmp : std_logic_vector(awidth-1 downto 0);
signal addr95_tmp : std_logic_vector(awidth-1 downto 0);
signal addr96_tmp : std_logic_vector(awidth-1 downto 0);
signal addr97_tmp : std_logic_vector(awidth-1 downto 0);
signal addr98_tmp : std_logic_vector(awidth-1 downto 0);
signal addr99_tmp : std_logic_vector(awidth-1 downto 0);
signal addr100_tmp : std_logic_vector(awidth-1 downto 0);
signal addr101_tmp : std_logic_vector(awidth-1 downto 0);
signal addr102_tmp : std_logic_vector(awidth-1 downto 0);
signal addr103_tmp : std_logic_vector(awidth-1 downto 0);
signal addr104_tmp : std_logic_vector(awidth-1 downto 0);
signal addr105_tmp : std_logic_vector(awidth-1 downto 0);
signal addr106_tmp : std_logic_vector(awidth-1 downto 0);
signal addr107_tmp : std_logic_vector(awidth-1 downto 0);
signal addr108_tmp : std_logic_vector(awidth-1 downto 0);
signal addr109_tmp : std_logic_vector(awidth-1 downto 0);
signal addr110_tmp : std_logic_vector(awidth-1 downto 0);
signal addr111_tmp : std_logic_vector(awidth-1 downto 0);
signal addr112_tmp : std_logic_vector(awidth-1 downto 0);
signal addr113_tmp : std_logic_vector(awidth-1 downto 0);
signal addr114_tmp : std_logic_vector(awidth-1 downto 0);
signal addr115_tmp : std_logic_vector(awidth-1 downto 0);
signal addr116_tmp : std_logic_vector(awidth-1 downto 0);
signal addr117_tmp : std_logic_vector(awidth-1 downto 0);
signal addr118_tmp : std_logic_vector(awidth-1 downto 0);
signal addr119_tmp : std_logic_vector(awidth-1 downto 0);
signal addr120_tmp : std_logic_vector(awidth-1 downto 0);
signal addr121_tmp : std_logic_vector(awidth-1 downto 0);
signal addr122_tmp : std_logic_vector(awidth-1 downto 0);
signal addr123_tmp : std_logic_vector(awidth-1 downto 0);
signal addr124_tmp : std_logic_vector(awidth-1 downto 0);
signal addr125_tmp : std_logic_vector(awidth-1 downto 0);
signal addr126_tmp : std_logic_vector(awidth-1 downto 0);
signal addr127_tmp : std_logic_vector(awidth-1 downto 0);
signal addr128_tmp : std_logic_vector(awidth-1 downto 0);
signal addr129_tmp : std_logic_vector(awidth-1 downto 0);
signal addr130_tmp : std_logic_vector(awidth-1 downto 0);
signal addr131_tmp : std_logic_vector(awidth-1 downto 0);
signal addr132_tmp : std_logic_vector(awidth-1 downto 0);
signal addr133_tmp : std_logic_vector(awidth-1 downto 0);
signal addr134_tmp : std_logic_vector(awidth-1 downto 0);
signal addr135_tmp : std_logic_vector(awidth-1 downto 0);
signal addr136_tmp : std_logic_vector(awidth-1 downto 0);
signal addr137_tmp : std_logic_vector(awidth-1 downto 0);
signal addr138_tmp : std_logic_vector(awidth-1 downto 0);
signal addr139_tmp : std_logic_vector(awidth-1 downto 0);
signal addr140_tmp : std_logic_vector(awidth-1 downto 0);
signal addr141_tmp : std_logic_vector(awidth-1 downto 0);
signal addr142_tmp : std_logic_vector(awidth-1 downto 0);
signal addr143_tmp : std_logic_vector(awidth-1 downto 0);
signal addr144_tmp : std_logic_vector(awidth-1 downto 0);
signal addr145_tmp : std_logic_vector(awidth-1 downto 0);
signal addr146_tmp : std_logic_vector(awidth-1 downto 0);
signal addr147_tmp : std_logic_vector(awidth-1 downto 0);
signal addr148_tmp : std_logic_vector(awidth-1 downto 0);
signal addr149_tmp : std_logic_vector(awidth-1 downto 0);
signal addr150_tmp : std_logic_vector(awidth-1 downto 0);
signal addr151_tmp : std_logic_vector(awidth-1 downto 0);
signal addr152_tmp : std_logic_vector(awidth-1 downto 0);
signal addr153_tmp : std_logic_vector(awidth-1 downto 0);
signal addr154_tmp : std_logic_vector(awidth-1 downto 0);
signal addr155_tmp : std_logic_vector(awidth-1 downto 0);
signal addr156_tmp : std_logic_vector(awidth-1 downto 0);
signal addr157_tmp : std_logic_vector(awidth-1 downto 0);
signal addr158_tmp : std_logic_vector(awidth-1 downto 0);
signal addr159_tmp : std_logic_vector(awidth-1 downto 0);
signal addr160_tmp : std_logic_vector(awidth-1 downto 0);
signal addr161_tmp : std_logic_vector(awidth-1 downto 0);
signal addr162_tmp : std_logic_vector(awidth-1 downto 0);
signal addr163_tmp : std_logic_vector(awidth-1 downto 0);
signal addr164_tmp : std_logic_vector(awidth-1 downto 0);
signal addr165_tmp : std_logic_vector(awidth-1 downto 0);
signal addr166_tmp : std_logic_vector(awidth-1 downto 0);
signal addr167_tmp : std_logic_vector(awidth-1 downto 0);
signal addr168_tmp : std_logic_vector(awidth-1 downto 0);
signal addr169_tmp : std_logic_vector(awidth-1 downto 0);
signal addr170_tmp : std_logic_vector(awidth-1 downto 0);
signal addr171_tmp : std_logic_vector(awidth-1 downto 0);
signal addr172_tmp : std_logic_vector(awidth-1 downto 0);
signal addr173_tmp : std_logic_vector(awidth-1 downto 0);
signal addr174_tmp : std_logic_vector(awidth-1 downto 0);
signal addr175_tmp : std_logic_vector(awidth-1 downto 0);
signal addr176_tmp : std_logic_vector(awidth-1 downto 0);
signal addr177_tmp : std_logic_vector(awidth-1 downto 0);
signal addr178_tmp : std_logic_vector(awidth-1 downto 0);
signal addr179_tmp : std_logic_vector(awidth-1 downto 0);
signal addr180_tmp : std_logic_vector(awidth-1 downto 0);
signal addr181_tmp : std_logic_vector(awidth-1 downto 0);
signal addr182_tmp : std_logic_vector(awidth-1 downto 0);
signal addr183_tmp : std_logic_vector(awidth-1 downto 0);
signal addr184_tmp : std_logic_vector(awidth-1 downto 0);
signal addr185_tmp : std_logic_vector(awidth-1 downto 0);
signal addr186_tmp : std_logic_vector(awidth-1 downto 0);
signal addr187_tmp : std_logic_vector(awidth-1 downto 0);
signal addr188_tmp : std_logic_vector(awidth-1 downto 0);
signal addr189_tmp : std_logic_vector(awidth-1 downto 0);
signal addr190_tmp : std_logic_vector(awidth-1 downto 0);
signal addr191_tmp : std_logic_vector(awidth-1 downto 0);
signal addr192_tmp : std_logic_vector(awidth-1 downto 0);
signal addr193_tmp : std_logic_vector(awidth-1 downto 0);
signal addr194_tmp : std_logic_vector(awidth-1 downto 0);
signal addr195_tmp : std_logic_vector(awidth-1 downto 0);
signal addr196_tmp : std_logic_vector(awidth-1 downto 0);
signal addr197_tmp : std_logic_vector(awidth-1 downto 0);
signal addr198_tmp : std_logic_vector(awidth-1 downto 0);
signal addr199_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem1 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem2 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem3 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem4 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem5 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem6 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem7 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem8 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem9 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem10 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem11 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem12 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem13 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem14 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem15 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem16 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem17 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem18 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem19 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem20 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem21 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem22 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem23 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem24 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem25 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem26 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem27 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem28 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem29 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem30 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem31 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem32 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem33 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem34 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem35 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem36 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem37 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem38 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem39 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem40 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem41 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem42 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem43 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem44 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem45 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem46 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem47 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem48 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem49 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem50 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem51 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem52 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem53 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem54 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem55 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem56 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem57 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem58 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem59 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem60 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem61 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem62 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem63 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem64 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem65 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem66 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem67 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem68 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem69 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem70 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem71 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem72 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem73 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem74 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem75 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem76 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem77 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem78 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem79 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem80 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem81 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem82 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem83 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem84 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem85 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem86 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem87 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem88 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem89 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem90 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem91 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem92 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem93 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem94 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem95 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem96 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem97 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem98 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
signal mem99 : mem_array := (
0 => "01100011", 1 => "01111100", 2 => "01110111", 3 => "01111011",
4 => "11110010", 5 => "01101011", 6 => "01101111", 7 => "11000101",
8 => "00110000", 9 => "00000001", 10 => "01100111", 11 => "00101011",
12 => "11111110", 13 => "11010111", 14 => "10101011", 15 => "01110110",
16 => "11001010", 17 => "10000010", 18 => "11001001", 19 => "01111101",
20 => "11111010", 21 => "01011001", 22 => "01000111", 23 => "11110000",
24 => "10101101", 25 => "11010100", 26 => "10100010", 27 => "10101111",
28 => "10011100", 29 => "10100100", 30 => "01110010", 31 => "11000000",
32 => "10110111", 33 => "11111101", 34 => "10010011", 35 => "00100110",
36 => "00110110", 37 => "00111111", 38 => "11110111", 39 => "11001100",
40 => "00110100", 41 => "10100101", 42 => "11100101", 43 => "11110001",
44 => "01110001", 45 => "11011000", 46 => "00110001", 47 => "00010101",
48 => "00000100", 49 => "11000111", 50 => "00100011", 51 => "11000011",
52 => "00011000", 53 => "10010110", 54 => "00000101", 55 => "10011010",
56 => "00000111", 57 => "00010010", 58 => "10000000", 59 => "11100010",
60 => "11101011", 61 => "00100111", 62 => "10110010", 63 => "01110101",
64 => "00001001", 65 => "10000011", 66 => "00101100", 67 => "00011010",
68 => "00011011", 69 => "01101110", 70 => "01011010", 71 => "10100000",
72 => "01010010", 73 => "00111011", 74 => "11010110", 75 => "10110011",
76 => "00101001", 77 => "11100011", 78 => "00101111", 79 => "10000100",
80 => "01010011", 81 => "11010001", 82 => "00000000", 83 => "11101101",
84 => "00100000", 85 => "11111100", 86 => "10110001", 87 => "01011011",
88 => "01101010", 89 => "11001011", 90 => "10111110", 91 => "00111001",
92 => "01001010", 93 => "01001100", 94 => "01011000", 95 => "11001111",
96 => "11010000", 97 => "11101111", 98 => "10101010", 99 => "11111011",
100 => "01000011", 101 => "01001101", 102 => "00110011", 103 => "10000101",
104 => "01000101", 105 => "11111001", 106 => "00000010", 107 => "01111111",
108 => "01010000", 109 => "00111100", 110 => "10011111", 111 => "10101000",
112 => "01010001", 113 => "10100011", 114 => "01000000", 115 => "10001111",
116 => "10010010", 117 => "10011101", 118 => "00111000", 119 => "11110101",
120 => "10111100", 121 => "10110110", 122 => "11011010", 123 => "00100001",
124 => "00010000", 125 => "11111111", 126 => "11110011", 127 => "11010010",
128 => "11001101", 129 => "00001100", 130 => "00010011", 131 => "11101100",
132 => "01011111", 133 => "10010111", 134 => "01000100", 135 => "00010111",
136 => "11000100", 137 => "10100111", 138 => "01111110", 139 => "00111101",
140 => "01100100", 141 => "01011101", 142 => "00011001", 143 => "01110011",
144 => "01100000", 145 => "10000001", 146 => "01001111", 147 => "11011100",
148 => "00100010", 149 => "00101010", 150 => "10010000", 151 => "10001000",
152 => "01000110", 153 => "11101110", 154 => "10111000", 155 => "00010100",
156 => "11011110", 157 => "01011110", 158 => "00001011", 159 => "11011011",
160 => "11100000", 161 => "00110010", 162 => "00111010", 163 => "00001010",
164 => "01001001", 165 => "00000110", 166 => "00100100", 167 => "01011100",
168 => "11000010", 169 => "11010011", 170 => "10101100", 171 => "01100010",
172 => "10010001", 173 => "10010101", 174 => "11100100", 175 => "01111001",
176 => "11100111", 177 => "11001000", 178 => "00110111", 179 => "01101101",
180 => "10001101", 181 => "11010101", 182 => "01001110", 183 => "10101001",
184 => "01101100", 185 => "01010110", 186 => "11110100", 187 => "11101010",
188 => "01100101", 189 => "01111010", 190 => "10101110", 191 => "00001000",
192 => "10111010", 193 => "01111000", 194 => "00100101", 195 => "00101110",
196 => "00011100", 197 => "10100110", 198 => "10110100", 199 => "11000110",
200 => "11101000", 201 => "11011101", 202 => "01110100", 203 => "00011111",
204 => "01001011", 205 => "10111101", 206 => "10001011", 207 => "10001010",
208 => "01110000", 209 => "00111110", 210 => "10110101", 211 => "01100110",
212 => "01001000", 213 => "00000011", 214 => "11110110", 215 => "00001110",
216 => "01100001", 217 => "00110101", 218 => "01010111", 219 => "10111001",
220 => "10000110", 221 => "11000001", 222 => "00011101", 223 => "10011110",
224 => "11100001", 225 => "11111000", 226 => "10011000", 227 => "00010001",
228 => "01101001", 229 => "11011001", 230 => "10001110", 231 => "10010100",
232 => "10011011", 233 => "00011110", 234 => "10000111", 235 => "11101001",
236 => "11001110", 237 => "01010101", 238 => "00101000", 239 => "11011111",
240 => "10001100", 241 => "10100001", 242 => "10001001", 243 => "00001101",
244 => "10111111", 245 => "11100110", 246 => "01000010", 247 => "01101000",
248 => "01000001", 249 => "10011001", 250 => "00101101", 251 => "00001111",
252 => "10110000", 253 => "01010100", 254 => "10111011", 255 => "00010110" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute syn_rom_style of mem2 : signal is "block_rom";
attribute syn_rom_style of mem3 : signal is "block_rom";
attribute syn_rom_style of mem4 : signal is "block_rom";
attribute syn_rom_style of mem5 : signal is "block_rom";
attribute syn_rom_style of mem6 : signal is "block_rom";
attribute syn_rom_style of mem7 : signal is "block_rom";
attribute syn_rom_style of mem8 : signal is "block_rom";
attribute syn_rom_style of mem9 : signal is "block_rom";
attribute syn_rom_style of mem10 : signal is "block_rom";
attribute syn_rom_style of mem11 : signal is "block_rom";
attribute syn_rom_style of mem12 : signal is "block_rom";
attribute syn_rom_style of mem13 : signal is "block_rom";
attribute syn_rom_style of mem14 : signal is "block_rom";
attribute syn_rom_style of mem15 : signal is "block_rom";
attribute syn_rom_style of mem16 : signal is "block_rom";
attribute syn_rom_style of mem17 : signal is "block_rom";
attribute syn_rom_style of mem18 : signal is "block_rom";
attribute syn_rom_style of mem19 : signal is "block_rom";
attribute syn_rom_style of mem20 : signal is "block_rom";
attribute syn_rom_style of mem21 : signal is "block_rom";
attribute syn_rom_style of mem22 : signal is "block_rom";
attribute syn_rom_style of mem23 : signal is "block_rom";
attribute syn_rom_style of mem24 : signal is "block_rom";
attribute syn_rom_style of mem25 : signal is "block_rom";
attribute syn_rom_style of mem26 : signal is "block_rom";
attribute syn_rom_style of mem27 : signal is "block_rom";
attribute syn_rom_style of mem28 : signal is "block_rom";
attribute syn_rom_style of mem29 : signal is "block_rom";
attribute syn_rom_style of mem30 : signal is "block_rom";
attribute syn_rom_style of mem31 : signal is "block_rom";
attribute syn_rom_style of mem32 : signal is "block_rom";
attribute syn_rom_style of mem33 : signal is "block_rom";
attribute syn_rom_style of mem34 : signal is "block_rom";
attribute syn_rom_style of mem35 : signal is "block_rom";
attribute syn_rom_style of mem36 : signal is "block_rom";
attribute syn_rom_style of mem37 : signal is "block_rom";
attribute syn_rom_style of mem38 : signal is "block_rom";
attribute syn_rom_style of mem39 : signal is "block_rom";
attribute syn_rom_style of mem40 : signal is "block_rom";
attribute syn_rom_style of mem41 : signal is "block_rom";
attribute syn_rom_style of mem42 : signal is "block_rom";
attribute syn_rom_style of mem43 : signal is "block_rom";
attribute syn_rom_style of mem44 : signal is "block_rom";
attribute syn_rom_style of mem45 : signal is "block_rom";
attribute syn_rom_style of mem46 : signal is "block_rom";
attribute syn_rom_style of mem47 : signal is "block_rom";
attribute syn_rom_style of mem48 : signal is "block_rom";
attribute syn_rom_style of mem49 : signal is "block_rom";
attribute syn_rom_style of mem50 : signal is "block_rom";
attribute syn_rom_style of mem51 : signal is "block_rom";
attribute syn_rom_style of mem52 : signal is "block_rom";
attribute syn_rom_style of mem53 : signal is "block_rom";
attribute syn_rom_style of mem54 : signal is "block_rom";
attribute syn_rom_style of mem55 : signal is "block_rom";
attribute syn_rom_style of mem56 : signal is "block_rom";
attribute syn_rom_style of mem57 : signal is "block_rom";
attribute syn_rom_style of mem58 : signal is "block_rom";
attribute syn_rom_style of mem59 : signal is "block_rom";
attribute syn_rom_style of mem60 : signal is "block_rom";
attribute syn_rom_style of mem61 : signal is "block_rom";
attribute syn_rom_style of mem62 : signal is "block_rom";
attribute syn_rom_style of mem63 : signal is "block_rom";
attribute syn_rom_style of mem64 : signal is "block_rom";
attribute syn_rom_style of mem65 : signal is "block_rom";
attribute syn_rom_style of mem66 : signal is "block_rom";
attribute syn_rom_style of mem67 : signal is "block_rom";
attribute syn_rom_style of mem68 : signal is "block_rom";
attribute syn_rom_style of mem69 : signal is "block_rom";
attribute syn_rom_style of mem70 : signal is "block_rom";
attribute syn_rom_style of mem71 : signal is "block_rom";
attribute syn_rom_style of mem72 : signal is "block_rom";
attribute syn_rom_style of mem73 : signal is "block_rom";
attribute syn_rom_style of mem74 : signal is "block_rom";
attribute syn_rom_style of mem75 : signal is "block_rom";
attribute syn_rom_style of mem76 : signal is "block_rom";
attribute syn_rom_style of mem77 : signal is "block_rom";
attribute syn_rom_style of mem78 : signal is "block_rom";
attribute syn_rom_style of mem79 : signal is "block_rom";
attribute syn_rom_style of mem80 : signal is "block_rom";
attribute syn_rom_style of mem81 : signal is "block_rom";
attribute syn_rom_style of mem82 : signal is "block_rom";
attribute syn_rom_style of mem83 : signal is "block_rom";
attribute syn_rom_style of mem84 : signal is "block_rom";
attribute syn_rom_style of mem85 : signal is "block_rom";
attribute syn_rom_style of mem86 : signal is "block_rom";
attribute syn_rom_style of mem87 : signal is "block_rom";
attribute syn_rom_style of mem88 : signal is "block_rom";
attribute syn_rom_style of mem89 : signal is "block_rom";
attribute syn_rom_style of mem90 : signal is "block_rom";
attribute syn_rom_style of mem91 : signal is "block_rom";
attribute syn_rom_style of mem92 : signal is "block_rom";
attribute syn_rom_style of mem93 : signal is "block_rom";
attribute syn_rom_style of mem94 : signal is "block_rom";
attribute syn_rom_style of mem95 : signal is "block_rom";
attribute syn_rom_style of mem96 : signal is "block_rom";
attribute syn_rom_style of mem97 : signal is "block_rom";
attribute syn_rom_style of mem98 : signal is "block_rom";
attribute syn_rom_style of mem99 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
attribute ROM_STYLE of mem2 : signal is "block";
attribute ROM_STYLE of mem3 : signal is "block";
attribute ROM_STYLE of mem4 : signal is "block";
attribute ROM_STYLE of mem5 : signal is "block";
attribute ROM_STYLE of mem6 : signal is "block";
attribute ROM_STYLE of mem7 : signal is "block";
attribute ROM_STYLE of mem8 : signal is "block";
attribute ROM_STYLE of mem9 : signal is "block";
attribute ROM_STYLE of mem10 : signal is "block";
attribute ROM_STYLE of mem11 : signal is "block";
attribute ROM_STYLE of mem12 : signal is "block";
attribute ROM_STYLE of mem13 : signal is "block";
attribute ROM_STYLE of mem14 : signal is "block";
attribute ROM_STYLE of mem15 : signal is "block";
attribute ROM_STYLE of mem16 : signal is "block";
attribute ROM_STYLE of mem17 : signal is "block";
attribute ROM_STYLE of mem18 : signal is "block";
attribute ROM_STYLE of mem19 : signal is "block";
attribute ROM_STYLE of mem20 : signal is "block";
attribute ROM_STYLE of mem21 : signal is "block";
attribute ROM_STYLE of mem22 : signal is "block";
attribute ROM_STYLE of mem23 : signal is "block";
attribute ROM_STYLE of mem24 : signal is "block";
attribute ROM_STYLE of mem25 : signal is "block";
attribute ROM_STYLE of mem26 : signal is "block";
attribute ROM_STYLE of mem27 : signal is "block";
attribute ROM_STYLE of mem28 : signal is "block";
attribute ROM_STYLE of mem29 : signal is "block";
attribute ROM_STYLE of mem30 : signal is "block";
attribute ROM_STYLE of mem31 : signal is "block";
attribute ROM_STYLE of mem32 : signal is "block";
attribute ROM_STYLE of mem33 : signal is "block";
attribute ROM_STYLE of mem34 : signal is "block";
attribute ROM_STYLE of mem35 : signal is "block";
attribute ROM_STYLE of mem36 : signal is "block";
attribute ROM_STYLE of mem37 : signal is "block";
attribute ROM_STYLE of mem38 : signal is "block";
attribute ROM_STYLE of mem39 : signal is "block";
attribute ROM_STYLE of mem40 : signal is "block";
attribute ROM_STYLE of mem41 : signal is "block";
attribute ROM_STYLE of mem42 : signal is "block";
attribute ROM_STYLE of mem43 : signal is "block";
attribute ROM_STYLE of mem44 : signal is "block";
attribute ROM_STYLE of mem45 : signal is "block";
attribute ROM_STYLE of mem46 : signal is "block";
attribute ROM_STYLE of mem47 : signal is "block";
attribute ROM_STYLE of mem48 : signal is "block";
attribute ROM_STYLE of mem49 : signal is "block";
attribute ROM_STYLE of mem50 : signal is "block";
attribute ROM_STYLE of mem51 : signal is "block";
attribute ROM_STYLE of mem52 : signal is "block";
attribute ROM_STYLE of mem53 : signal is "block";
attribute ROM_STYLE of mem54 : signal is "block";
attribute ROM_STYLE of mem55 : signal is "block";
attribute ROM_STYLE of mem56 : signal is "block";
attribute ROM_STYLE of mem57 : signal is "block";
attribute ROM_STYLE of mem58 : signal is "block";
attribute ROM_STYLE of mem59 : signal is "block";
attribute ROM_STYLE of mem60 : signal is "block";
attribute ROM_STYLE of mem61 : signal is "block";
attribute ROM_STYLE of mem62 : signal is "block";
attribute ROM_STYLE of mem63 : signal is "block";
attribute ROM_STYLE of mem64 : signal is "block";
attribute ROM_STYLE of mem65 : signal is "block";
attribute ROM_STYLE of mem66 : signal is "block";
attribute ROM_STYLE of mem67 : signal is "block";
attribute ROM_STYLE of mem68 : signal is "block";
attribute ROM_STYLE of mem69 : signal is "block";
attribute ROM_STYLE of mem70 : signal is "block";
attribute ROM_STYLE of mem71 : signal is "block";
attribute ROM_STYLE of mem72 : signal is "block";
attribute ROM_STYLE of mem73 : signal is "block";
attribute ROM_STYLE of mem74 : signal is "block";
attribute ROM_STYLE of mem75 : signal is "block";
attribute ROM_STYLE of mem76 : signal is "block";
attribute ROM_STYLE of mem77 : signal is "block";
attribute ROM_STYLE of mem78 : signal is "block";
attribute ROM_STYLE of mem79 : signal is "block";
attribute ROM_STYLE of mem80 : signal is "block";
attribute ROM_STYLE of mem81 : signal is "block";
attribute ROM_STYLE of mem82 : signal is "block";
attribute ROM_STYLE of mem83 : signal is "block";
attribute ROM_STYLE of mem84 : signal is "block";
attribute ROM_STYLE of mem85 : signal is "block";
attribute ROM_STYLE of mem86 : signal is "block";
attribute ROM_STYLE of mem87 : signal is "block";
attribute ROM_STYLE of mem88 : signal is "block";
attribute ROM_STYLE of mem89 : signal is "block";
attribute ROM_STYLE of mem90 : signal is "block";
attribute ROM_STYLE of mem91 : signal is "block";
attribute ROM_STYLE of mem92 : signal is "block";
attribute ROM_STYLE of mem93 : signal is "block";
attribute ROM_STYLE of mem94 : signal is "block";
attribute ROM_STYLE of mem95 : signal is "block";
attribute ROM_STYLE of mem96 : signal is "block";
attribute ROM_STYLE of mem97 : signal is "block";
attribute ROM_STYLE of mem98 : signal is "block";
attribute ROM_STYLE of mem99 : signal is "block";
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
memory_access_guard_3: process (addr3)
begin
addr3_tmp <= addr3;
--synthesis translate_off
if (CONV_INTEGER(addr3) > mem_size-1) then
addr3_tmp <= (others => '0');
else
addr3_tmp <= addr3;
end if;
--synthesis translate_on
end process;
memory_access_guard_4: process (addr4)
begin
addr4_tmp <= addr4;
--synthesis translate_off
if (CONV_INTEGER(addr4) > mem_size-1) then
addr4_tmp <= (others => '0');
else
addr4_tmp <= addr4;
end if;
--synthesis translate_on
end process;
memory_access_guard_5: process (addr5)
begin
addr5_tmp <= addr5;
--synthesis translate_off
if (CONV_INTEGER(addr5) > mem_size-1) then
addr5_tmp <= (others => '0');
else
addr5_tmp <= addr5;
end if;
--synthesis translate_on
end process;
memory_access_guard_6: process (addr6)
begin
addr6_tmp <= addr6;
--synthesis translate_off
if (CONV_INTEGER(addr6) > mem_size-1) then
addr6_tmp <= (others => '0');
else
addr6_tmp <= addr6;
end if;
--synthesis translate_on
end process;
memory_access_guard_7: process (addr7)
begin
addr7_tmp <= addr7;
--synthesis translate_off
if (CONV_INTEGER(addr7) > mem_size-1) then
addr7_tmp <= (others => '0');
else
addr7_tmp <= addr7;
end if;
--synthesis translate_on
end process;
memory_access_guard_8: process (addr8)
begin
addr8_tmp <= addr8;
--synthesis translate_off
if (CONV_INTEGER(addr8) > mem_size-1) then
addr8_tmp <= (others => '0');
else
addr8_tmp <= addr8;
end if;
--synthesis translate_on
end process;
memory_access_guard_9: process (addr9)
begin
addr9_tmp <= addr9;
--synthesis translate_off
if (CONV_INTEGER(addr9) > mem_size-1) then
addr9_tmp <= (others => '0');
else
addr9_tmp <= addr9;
end if;
--synthesis translate_on
end process;
memory_access_guard_10: process (addr10)
begin
addr10_tmp <= addr10;
--synthesis translate_off
if (CONV_INTEGER(addr10) > mem_size-1) then
addr10_tmp <= (others => '0');
else
addr10_tmp <= addr10;
end if;
--synthesis translate_on
end process;
memory_access_guard_11: process (addr11)
begin
addr11_tmp <= addr11;
--synthesis translate_off
if (CONV_INTEGER(addr11) > mem_size-1) then
addr11_tmp <= (others => '0');
else
addr11_tmp <= addr11;
end if;
--synthesis translate_on
end process;
memory_access_guard_12: process (addr12)
begin
addr12_tmp <= addr12;
--synthesis translate_off
if (CONV_INTEGER(addr12) > mem_size-1) then
addr12_tmp <= (others => '0');
else
addr12_tmp <= addr12;
end if;
--synthesis translate_on
end process;
memory_access_guard_13: process (addr13)
begin
addr13_tmp <= addr13;
--synthesis translate_off
if (CONV_INTEGER(addr13) > mem_size-1) then
addr13_tmp <= (others => '0');
else
addr13_tmp <= addr13;
end if;
--synthesis translate_on
end process;
memory_access_guard_14: process (addr14)
begin
addr14_tmp <= addr14;
--synthesis translate_off
if (CONV_INTEGER(addr14) > mem_size-1) then
addr14_tmp <= (others => '0');
else
addr14_tmp <= addr14;
end if;
--synthesis translate_on
end process;
memory_access_guard_15: process (addr15)
begin
addr15_tmp <= addr15;
--synthesis translate_off
if (CONV_INTEGER(addr15) > mem_size-1) then
addr15_tmp <= (others => '0');
else
addr15_tmp <= addr15;
end if;
--synthesis translate_on
end process;
memory_access_guard_16: process (addr16)
begin
addr16_tmp <= addr16;
--synthesis translate_off
if (CONV_INTEGER(addr16) > mem_size-1) then
addr16_tmp <= (others => '0');
else
addr16_tmp <= addr16;
end if;
--synthesis translate_on
end process;
memory_access_guard_17: process (addr17)
begin
addr17_tmp <= addr17;
--synthesis translate_off
if (CONV_INTEGER(addr17) > mem_size-1) then
addr17_tmp <= (others => '0');
else
addr17_tmp <= addr17;
end if;
--synthesis translate_on
end process;
memory_access_guard_18: process (addr18)
begin
addr18_tmp <= addr18;
--synthesis translate_off
if (CONV_INTEGER(addr18) > mem_size-1) then
addr18_tmp <= (others => '0');
else
addr18_tmp <= addr18;
end if;
--synthesis translate_on
end process;
memory_access_guard_19: process (addr19)
begin
addr19_tmp <= addr19;
--synthesis translate_off
if (CONV_INTEGER(addr19) > mem_size-1) then
addr19_tmp <= (others => '0');
else
addr19_tmp <= addr19;
end if;
--synthesis translate_on
end process;
memory_access_guard_20: process (addr20)
begin
addr20_tmp <= addr20;
--synthesis translate_off
if (CONV_INTEGER(addr20) > mem_size-1) then
addr20_tmp <= (others => '0');
else
addr20_tmp <= addr20;
end if;
--synthesis translate_on
end process;
memory_access_guard_21: process (addr21)
begin
addr21_tmp <= addr21;
--synthesis translate_off
if (CONV_INTEGER(addr21) > mem_size-1) then
addr21_tmp <= (others => '0');
else
addr21_tmp <= addr21;
end if;
--synthesis translate_on
end process;
memory_access_guard_22: process (addr22)
begin
addr22_tmp <= addr22;
--synthesis translate_off
if (CONV_INTEGER(addr22) > mem_size-1) then
addr22_tmp <= (others => '0');
else
addr22_tmp <= addr22;
end if;
--synthesis translate_on
end process;
memory_access_guard_23: process (addr23)
begin
addr23_tmp <= addr23;
--synthesis translate_off
if (CONV_INTEGER(addr23) > mem_size-1) then
addr23_tmp <= (others => '0');
else
addr23_tmp <= addr23;
end if;
--synthesis translate_on
end process;
memory_access_guard_24: process (addr24)
begin
addr24_tmp <= addr24;
--synthesis translate_off
if (CONV_INTEGER(addr24) > mem_size-1) then
addr24_tmp <= (others => '0');
else
addr24_tmp <= addr24;
end if;
--synthesis translate_on
end process;
memory_access_guard_25: process (addr25)
begin
addr25_tmp <= addr25;
--synthesis translate_off
if (CONV_INTEGER(addr25) > mem_size-1) then
addr25_tmp <= (others => '0');
else
addr25_tmp <= addr25;
end if;
--synthesis translate_on
end process;
memory_access_guard_26: process (addr26)
begin
addr26_tmp <= addr26;
--synthesis translate_off
if (CONV_INTEGER(addr26) > mem_size-1) then
addr26_tmp <= (others => '0');
else
addr26_tmp <= addr26;
end if;
--synthesis translate_on
end process;
memory_access_guard_27: process (addr27)
begin
addr27_tmp <= addr27;
--synthesis translate_off
if (CONV_INTEGER(addr27) > mem_size-1) then
addr27_tmp <= (others => '0');
else
addr27_tmp <= addr27;
end if;
--synthesis translate_on
end process;
memory_access_guard_28: process (addr28)
begin
addr28_tmp <= addr28;
--synthesis translate_off
if (CONV_INTEGER(addr28) > mem_size-1) then
addr28_tmp <= (others => '0');
else
addr28_tmp <= addr28;
end if;
--synthesis translate_on
end process;
memory_access_guard_29: process (addr29)
begin
addr29_tmp <= addr29;
--synthesis translate_off
if (CONV_INTEGER(addr29) > mem_size-1) then
addr29_tmp <= (others => '0');
else
addr29_tmp <= addr29;
end if;
--synthesis translate_on
end process;
memory_access_guard_30: process (addr30)
begin
addr30_tmp <= addr30;
--synthesis translate_off
if (CONV_INTEGER(addr30) > mem_size-1) then
addr30_tmp <= (others => '0');
else
addr30_tmp <= addr30;
end if;
--synthesis translate_on
end process;
memory_access_guard_31: process (addr31)
begin
addr31_tmp <= addr31;
--synthesis translate_off
if (CONV_INTEGER(addr31) > mem_size-1) then
addr31_tmp <= (others => '0');
else
addr31_tmp <= addr31;
end if;
--synthesis translate_on
end process;
memory_access_guard_32: process (addr32)
begin
addr32_tmp <= addr32;
--synthesis translate_off
if (CONV_INTEGER(addr32) > mem_size-1) then
addr32_tmp <= (others => '0');
else
addr32_tmp <= addr32;
end if;
--synthesis translate_on
end process;
memory_access_guard_33: process (addr33)
begin
addr33_tmp <= addr33;
--synthesis translate_off
if (CONV_INTEGER(addr33) > mem_size-1) then
addr33_tmp <= (others => '0');
else
addr33_tmp <= addr33;
end if;
--synthesis translate_on
end process;
memory_access_guard_34: process (addr34)
begin
addr34_tmp <= addr34;
--synthesis translate_off
if (CONV_INTEGER(addr34) > mem_size-1) then
addr34_tmp <= (others => '0');
else
addr34_tmp <= addr34;
end if;
--synthesis translate_on
end process;
memory_access_guard_35: process (addr35)
begin
addr35_tmp <= addr35;
--synthesis translate_off
if (CONV_INTEGER(addr35) > mem_size-1) then
addr35_tmp <= (others => '0');
else
addr35_tmp <= addr35;
end if;
--synthesis translate_on
end process;
memory_access_guard_36: process (addr36)
begin
addr36_tmp <= addr36;
--synthesis translate_off
if (CONV_INTEGER(addr36) > mem_size-1) then
addr36_tmp <= (others => '0');
else
addr36_tmp <= addr36;
end if;
--synthesis translate_on
end process;
memory_access_guard_37: process (addr37)
begin
addr37_tmp <= addr37;
--synthesis translate_off
if (CONV_INTEGER(addr37) > mem_size-1) then
addr37_tmp <= (others => '0');
else
addr37_tmp <= addr37;
end if;
--synthesis translate_on
end process;
memory_access_guard_38: process (addr38)
begin
addr38_tmp <= addr38;
--synthesis translate_off
if (CONV_INTEGER(addr38) > mem_size-1) then
addr38_tmp <= (others => '0');
else
addr38_tmp <= addr38;
end if;
--synthesis translate_on
end process;
memory_access_guard_39: process (addr39)
begin
addr39_tmp <= addr39;
--synthesis translate_off
if (CONV_INTEGER(addr39) > mem_size-1) then
addr39_tmp <= (others => '0');
else
addr39_tmp <= addr39;
end if;
--synthesis translate_on
end process;
memory_access_guard_40: process (addr40)
begin
addr40_tmp <= addr40;
--synthesis translate_off
if (CONV_INTEGER(addr40) > mem_size-1) then
addr40_tmp <= (others => '0');
else
addr40_tmp <= addr40;
end if;
--synthesis translate_on
end process;
memory_access_guard_41: process (addr41)
begin
addr41_tmp <= addr41;
--synthesis translate_off
if (CONV_INTEGER(addr41) > mem_size-1) then
addr41_tmp <= (others => '0');
else
addr41_tmp <= addr41;
end if;
--synthesis translate_on
end process;
memory_access_guard_42: process (addr42)
begin
addr42_tmp <= addr42;
--synthesis translate_off
if (CONV_INTEGER(addr42) > mem_size-1) then
addr42_tmp <= (others => '0');
else
addr42_tmp <= addr42;
end if;
--synthesis translate_on
end process;
memory_access_guard_43: process (addr43)
begin
addr43_tmp <= addr43;
--synthesis translate_off
if (CONV_INTEGER(addr43) > mem_size-1) then
addr43_tmp <= (others => '0');
else
addr43_tmp <= addr43;
end if;
--synthesis translate_on
end process;
memory_access_guard_44: process (addr44)
begin
addr44_tmp <= addr44;
--synthesis translate_off
if (CONV_INTEGER(addr44) > mem_size-1) then
addr44_tmp <= (others => '0');
else
addr44_tmp <= addr44;
end if;
--synthesis translate_on
end process;
memory_access_guard_45: process (addr45)
begin
addr45_tmp <= addr45;
--synthesis translate_off
if (CONV_INTEGER(addr45) > mem_size-1) then
addr45_tmp <= (others => '0');
else
addr45_tmp <= addr45;
end if;
--synthesis translate_on
end process;
memory_access_guard_46: process (addr46)
begin
addr46_tmp <= addr46;
--synthesis translate_off
if (CONV_INTEGER(addr46) > mem_size-1) then
addr46_tmp <= (others => '0');
else
addr46_tmp <= addr46;
end if;
--synthesis translate_on
end process;
memory_access_guard_47: process (addr47)
begin
addr47_tmp <= addr47;
--synthesis translate_off
if (CONV_INTEGER(addr47) > mem_size-1) then
addr47_tmp <= (others => '0');
else
addr47_tmp <= addr47;
end if;
--synthesis translate_on
end process;
memory_access_guard_48: process (addr48)
begin
addr48_tmp <= addr48;
--synthesis translate_off
if (CONV_INTEGER(addr48) > mem_size-1) then
addr48_tmp <= (others => '0');
else
addr48_tmp <= addr48;
end if;
--synthesis translate_on
end process;
memory_access_guard_49: process (addr49)
begin
addr49_tmp <= addr49;
--synthesis translate_off
if (CONV_INTEGER(addr49) > mem_size-1) then
addr49_tmp <= (others => '0');
else
addr49_tmp <= addr49;
end if;
--synthesis translate_on
end process;
memory_access_guard_50: process (addr50)
begin
addr50_tmp <= addr50;
--synthesis translate_off
if (CONV_INTEGER(addr50) > mem_size-1) then
addr50_tmp <= (others => '0');
else
addr50_tmp <= addr50;
end if;
--synthesis translate_on
end process;
memory_access_guard_51: process (addr51)
begin
addr51_tmp <= addr51;
--synthesis translate_off
if (CONV_INTEGER(addr51) > mem_size-1) then
addr51_tmp <= (others => '0');
else
addr51_tmp <= addr51;
end if;
--synthesis translate_on
end process;
memory_access_guard_52: process (addr52)
begin
addr52_tmp <= addr52;
--synthesis translate_off
if (CONV_INTEGER(addr52) > mem_size-1) then
addr52_tmp <= (others => '0');
else
addr52_tmp <= addr52;
end if;
--synthesis translate_on
end process;
memory_access_guard_53: process (addr53)
begin
addr53_tmp <= addr53;
--synthesis translate_off
if (CONV_INTEGER(addr53) > mem_size-1) then
addr53_tmp <= (others => '0');
else
addr53_tmp <= addr53;
end if;
--synthesis translate_on
end process;
memory_access_guard_54: process (addr54)
begin
addr54_tmp <= addr54;
--synthesis translate_off
if (CONV_INTEGER(addr54) > mem_size-1) then
addr54_tmp <= (others => '0');
else
addr54_tmp <= addr54;
end if;
--synthesis translate_on
end process;
memory_access_guard_55: process (addr55)
begin
addr55_tmp <= addr55;
--synthesis translate_off
if (CONV_INTEGER(addr55) > mem_size-1) then
addr55_tmp <= (others => '0');
else
addr55_tmp <= addr55;
end if;
--synthesis translate_on
end process;
memory_access_guard_56: process (addr56)
begin
addr56_tmp <= addr56;
--synthesis translate_off
if (CONV_INTEGER(addr56) > mem_size-1) then
addr56_tmp <= (others => '0');
else
addr56_tmp <= addr56;
end if;
--synthesis translate_on
end process;
memory_access_guard_57: process (addr57)
begin
addr57_tmp <= addr57;
--synthesis translate_off
if (CONV_INTEGER(addr57) > mem_size-1) then
addr57_tmp <= (others => '0');
else
addr57_tmp <= addr57;
end if;
--synthesis translate_on
end process;
memory_access_guard_58: process (addr58)
begin
addr58_tmp <= addr58;
--synthesis translate_off
if (CONV_INTEGER(addr58) > mem_size-1) then
addr58_tmp <= (others => '0');
else
addr58_tmp <= addr58;
end if;
--synthesis translate_on
end process;
memory_access_guard_59: process (addr59)
begin
addr59_tmp <= addr59;
--synthesis translate_off
if (CONV_INTEGER(addr59) > mem_size-1) then
addr59_tmp <= (others => '0');
else
addr59_tmp <= addr59;
end if;
--synthesis translate_on
end process;
memory_access_guard_60: process (addr60)
begin
addr60_tmp <= addr60;
--synthesis translate_off
if (CONV_INTEGER(addr60) > mem_size-1) then
addr60_tmp <= (others => '0');
else
addr60_tmp <= addr60;
end if;
--synthesis translate_on
end process;
memory_access_guard_61: process (addr61)
begin
addr61_tmp <= addr61;
--synthesis translate_off
if (CONV_INTEGER(addr61) > mem_size-1) then
addr61_tmp <= (others => '0');
else
addr61_tmp <= addr61;
end if;
--synthesis translate_on
end process;
memory_access_guard_62: process (addr62)
begin
addr62_tmp <= addr62;
--synthesis translate_off
if (CONV_INTEGER(addr62) > mem_size-1) then
addr62_tmp <= (others => '0');
else
addr62_tmp <= addr62;
end if;
--synthesis translate_on
end process;
memory_access_guard_63: process (addr63)
begin
addr63_tmp <= addr63;
--synthesis translate_off
if (CONV_INTEGER(addr63) > mem_size-1) then
addr63_tmp <= (others => '0');
else
addr63_tmp <= addr63;
end if;
--synthesis translate_on
end process;
memory_access_guard_64: process (addr64)
begin
addr64_tmp <= addr64;
--synthesis translate_off
if (CONV_INTEGER(addr64) > mem_size-1) then
addr64_tmp <= (others => '0');
else
addr64_tmp <= addr64;
end if;
--synthesis translate_on
end process;
memory_access_guard_65: process (addr65)
begin
addr65_tmp <= addr65;
--synthesis translate_off
if (CONV_INTEGER(addr65) > mem_size-1) then
addr65_tmp <= (others => '0');
else
addr65_tmp <= addr65;
end if;
--synthesis translate_on
end process;
memory_access_guard_66: process (addr66)
begin
addr66_tmp <= addr66;
--synthesis translate_off
if (CONV_INTEGER(addr66) > mem_size-1) then
addr66_tmp <= (others => '0');
else
addr66_tmp <= addr66;
end if;
--synthesis translate_on
end process;
memory_access_guard_67: process (addr67)
begin
addr67_tmp <= addr67;
--synthesis translate_off
if (CONV_INTEGER(addr67) > mem_size-1) then
addr67_tmp <= (others => '0');
else
addr67_tmp <= addr67;
end if;
--synthesis translate_on
end process;
memory_access_guard_68: process (addr68)
begin
addr68_tmp <= addr68;
--synthesis translate_off
if (CONV_INTEGER(addr68) > mem_size-1) then
addr68_tmp <= (others => '0');
else
addr68_tmp <= addr68;
end if;
--synthesis translate_on
end process;
memory_access_guard_69: process (addr69)
begin
addr69_tmp <= addr69;
--synthesis translate_off
if (CONV_INTEGER(addr69) > mem_size-1) then
addr69_tmp <= (others => '0');
else
addr69_tmp <= addr69;
end if;
--synthesis translate_on
end process;
memory_access_guard_70: process (addr70)
begin
addr70_tmp <= addr70;
--synthesis translate_off
if (CONV_INTEGER(addr70) > mem_size-1) then
addr70_tmp <= (others => '0');
else
addr70_tmp <= addr70;
end if;
--synthesis translate_on
end process;
memory_access_guard_71: process (addr71)
begin
addr71_tmp <= addr71;
--synthesis translate_off
if (CONV_INTEGER(addr71) > mem_size-1) then
addr71_tmp <= (others => '0');
else
addr71_tmp <= addr71;
end if;
--synthesis translate_on
end process;
memory_access_guard_72: process (addr72)
begin
addr72_tmp <= addr72;
--synthesis translate_off
if (CONV_INTEGER(addr72) > mem_size-1) then
addr72_tmp <= (others => '0');
else
addr72_tmp <= addr72;
end if;
--synthesis translate_on
end process;
memory_access_guard_73: process (addr73)
begin
addr73_tmp <= addr73;
--synthesis translate_off
if (CONV_INTEGER(addr73) > mem_size-1) then
addr73_tmp <= (others => '0');
else
addr73_tmp <= addr73;
end if;
--synthesis translate_on
end process;
memory_access_guard_74: process (addr74)
begin
addr74_tmp <= addr74;
--synthesis translate_off
if (CONV_INTEGER(addr74) > mem_size-1) then
addr74_tmp <= (others => '0');
else
addr74_tmp <= addr74;
end if;
--synthesis translate_on
end process;
memory_access_guard_75: process (addr75)
begin
addr75_tmp <= addr75;
--synthesis translate_off
if (CONV_INTEGER(addr75) > mem_size-1) then
addr75_tmp <= (others => '0');
else
addr75_tmp <= addr75;
end if;
--synthesis translate_on
end process;
memory_access_guard_76: process (addr76)
begin
addr76_tmp <= addr76;
--synthesis translate_off
if (CONV_INTEGER(addr76) > mem_size-1) then
addr76_tmp <= (others => '0');
else
addr76_tmp <= addr76;
end if;
--synthesis translate_on
end process;
memory_access_guard_77: process (addr77)
begin
addr77_tmp <= addr77;
--synthesis translate_off
if (CONV_INTEGER(addr77) > mem_size-1) then
addr77_tmp <= (others => '0');
else
addr77_tmp <= addr77;
end if;
--synthesis translate_on
end process;
memory_access_guard_78: process (addr78)
begin
addr78_tmp <= addr78;
--synthesis translate_off
if (CONV_INTEGER(addr78) > mem_size-1) then
addr78_tmp <= (others => '0');
else
addr78_tmp <= addr78;
end if;
--synthesis translate_on
end process;
memory_access_guard_79: process (addr79)
begin
addr79_tmp <= addr79;
--synthesis translate_off
if (CONV_INTEGER(addr79) > mem_size-1) then
addr79_tmp <= (others => '0');
else
addr79_tmp <= addr79;
end if;
--synthesis translate_on
end process;
memory_access_guard_80: process (addr80)
begin
addr80_tmp <= addr80;
--synthesis translate_off
if (CONV_INTEGER(addr80) > mem_size-1) then
addr80_tmp <= (others => '0');
else
addr80_tmp <= addr80;
end if;
--synthesis translate_on
end process;
memory_access_guard_81: process (addr81)
begin
addr81_tmp <= addr81;
--synthesis translate_off
if (CONV_INTEGER(addr81) > mem_size-1) then
addr81_tmp <= (others => '0');
else
addr81_tmp <= addr81;
end if;
--synthesis translate_on
end process;
memory_access_guard_82: process (addr82)
begin
addr82_tmp <= addr82;
--synthesis translate_off
if (CONV_INTEGER(addr82) > mem_size-1) then
addr82_tmp <= (others => '0');
else
addr82_tmp <= addr82;
end if;
--synthesis translate_on
end process;
memory_access_guard_83: process (addr83)
begin
addr83_tmp <= addr83;
--synthesis translate_off
if (CONV_INTEGER(addr83) > mem_size-1) then
addr83_tmp <= (others => '0');
else
addr83_tmp <= addr83;
end if;
--synthesis translate_on
end process;
memory_access_guard_84: process (addr84)
begin
addr84_tmp <= addr84;
--synthesis translate_off
if (CONV_INTEGER(addr84) > mem_size-1) then
addr84_tmp <= (others => '0');
else
addr84_tmp <= addr84;
end if;
--synthesis translate_on
end process;
memory_access_guard_85: process (addr85)
begin
addr85_tmp <= addr85;
--synthesis translate_off
if (CONV_INTEGER(addr85) > mem_size-1) then
addr85_tmp <= (others => '0');
else
addr85_tmp <= addr85;
end if;
--synthesis translate_on
end process;
memory_access_guard_86: process (addr86)
begin
addr86_tmp <= addr86;
--synthesis translate_off
if (CONV_INTEGER(addr86) > mem_size-1) then
addr86_tmp <= (others => '0');
else
addr86_tmp <= addr86;
end if;
--synthesis translate_on
end process;
memory_access_guard_87: process (addr87)
begin
addr87_tmp <= addr87;
--synthesis translate_off
if (CONV_INTEGER(addr87) > mem_size-1) then
addr87_tmp <= (others => '0');
else
addr87_tmp <= addr87;
end if;
--synthesis translate_on
end process;
memory_access_guard_88: process (addr88)
begin
addr88_tmp <= addr88;
--synthesis translate_off
if (CONV_INTEGER(addr88) > mem_size-1) then
addr88_tmp <= (others => '0');
else
addr88_tmp <= addr88;
end if;
--synthesis translate_on
end process;
memory_access_guard_89: process (addr89)
begin
addr89_tmp <= addr89;
--synthesis translate_off
if (CONV_INTEGER(addr89) > mem_size-1) then
addr89_tmp <= (others => '0');
else
addr89_tmp <= addr89;
end if;
--synthesis translate_on
end process;
memory_access_guard_90: process (addr90)
begin
addr90_tmp <= addr90;
--synthesis translate_off
if (CONV_INTEGER(addr90) > mem_size-1) then
addr90_tmp <= (others => '0');
else
addr90_tmp <= addr90;
end if;
--synthesis translate_on
end process;
memory_access_guard_91: process (addr91)
begin
addr91_tmp <= addr91;
--synthesis translate_off
if (CONV_INTEGER(addr91) > mem_size-1) then
addr91_tmp <= (others => '0');
else
addr91_tmp <= addr91;
end if;
--synthesis translate_on
end process;
memory_access_guard_92: process (addr92)
begin
addr92_tmp <= addr92;
--synthesis translate_off
if (CONV_INTEGER(addr92) > mem_size-1) then
addr92_tmp <= (others => '0');
else
addr92_tmp <= addr92;
end if;
--synthesis translate_on
end process;
memory_access_guard_93: process (addr93)
begin
addr93_tmp <= addr93;
--synthesis translate_off
if (CONV_INTEGER(addr93) > mem_size-1) then
addr93_tmp <= (others => '0');
else
addr93_tmp <= addr93;
end if;
--synthesis translate_on
end process;
memory_access_guard_94: process (addr94)
begin
addr94_tmp <= addr94;
--synthesis translate_off
if (CONV_INTEGER(addr94) > mem_size-1) then
addr94_tmp <= (others => '0');
else
addr94_tmp <= addr94;
end if;
--synthesis translate_on
end process;
memory_access_guard_95: process (addr95)
begin
addr95_tmp <= addr95;
--synthesis translate_off
if (CONV_INTEGER(addr95) > mem_size-1) then
addr95_tmp <= (others => '0');
else
addr95_tmp <= addr95;
end if;
--synthesis translate_on
end process;
memory_access_guard_96: process (addr96)
begin
addr96_tmp <= addr96;
--synthesis translate_off
if (CONV_INTEGER(addr96) > mem_size-1) then
addr96_tmp <= (others => '0');
else
addr96_tmp <= addr96;
end if;
--synthesis translate_on
end process;
memory_access_guard_97: process (addr97)
begin
addr97_tmp <= addr97;
--synthesis translate_off
if (CONV_INTEGER(addr97) > mem_size-1) then
addr97_tmp <= (others => '0');
else
addr97_tmp <= addr97;
end if;
--synthesis translate_on
end process;
memory_access_guard_98: process (addr98)
begin
addr98_tmp <= addr98;
--synthesis translate_off
if (CONV_INTEGER(addr98) > mem_size-1) then
addr98_tmp <= (others => '0');
else
addr98_tmp <= addr98;
end if;
--synthesis translate_on
end process;
memory_access_guard_99: process (addr99)
begin
addr99_tmp <= addr99;
--synthesis translate_off
if (CONV_INTEGER(addr99) > mem_size-1) then
addr99_tmp <= (others => '0');
else
addr99_tmp <= addr99;
end if;
--synthesis translate_on
end process;
memory_access_guard_100: process (addr100)
begin
addr100_tmp <= addr100;
--synthesis translate_off
if (CONV_INTEGER(addr100) > mem_size-1) then
addr100_tmp <= (others => '0');
else
addr100_tmp <= addr100;
end if;
--synthesis translate_on
end process;
memory_access_guard_101: process (addr101)
begin
addr101_tmp <= addr101;
--synthesis translate_off
if (CONV_INTEGER(addr101) > mem_size-1) then
addr101_tmp <= (others => '0');
else
addr101_tmp <= addr101;
end if;
--synthesis translate_on
end process;
memory_access_guard_102: process (addr102)
begin
addr102_tmp <= addr102;
--synthesis translate_off
if (CONV_INTEGER(addr102) > mem_size-1) then
addr102_tmp <= (others => '0');
else
addr102_tmp <= addr102;
end if;
--synthesis translate_on
end process;
memory_access_guard_103: process (addr103)
begin
addr103_tmp <= addr103;
--synthesis translate_off
if (CONV_INTEGER(addr103) > mem_size-1) then
addr103_tmp <= (others => '0');
else
addr103_tmp <= addr103;
end if;
--synthesis translate_on
end process;
memory_access_guard_104: process (addr104)
begin
addr104_tmp <= addr104;
--synthesis translate_off
if (CONV_INTEGER(addr104) > mem_size-1) then
addr104_tmp <= (others => '0');
else
addr104_tmp <= addr104;
end if;
--synthesis translate_on
end process;
memory_access_guard_105: process (addr105)
begin
addr105_tmp <= addr105;
--synthesis translate_off
if (CONV_INTEGER(addr105) > mem_size-1) then
addr105_tmp <= (others => '0');
else
addr105_tmp <= addr105;
end if;
--synthesis translate_on
end process;
memory_access_guard_106: process (addr106)
begin
addr106_tmp <= addr106;
--synthesis translate_off
if (CONV_INTEGER(addr106) > mem_size-1) then
addr106_tmp <= (others => '0');
else
addr106_tmp <= addr106;
end if;
--synthesis translate_on
end process;
memory_access_guard_107: process (addr107)
begin
addr107_tmp <= addr107;
--synthesis translate_off
if (CONV_INTEGER(addr107) > mem_size-1) then
addr107_tmp <= (others => '0');
else
addr107_tmp <= addr107;
end if;
--synthesis translate_on
end process;
memory_access_guard_108: process (addr108)
begin
addr108_tmp <= addr108;
--synthesis translate_off
if (CONV_INTEGER(addr108) > mem_size-1) then
addr108_tmp <= (others => '0');
else
addr108_tmp <= addr108;
end if;
--synthesis translate_on
end process;
memory_access_guard_109: process (addr109)
begin
addr109_tmp <= addr109;
--synthesis translate_off
if (CONV_INTEGER(addr109) > mem_size-1) then
addr109_tmp <= (others => '0');
else
addr109_tmp <= addr109;
end if;
--synthesis translate_on
end process;
memory_access_guard_110: process (addr110)
begin
addr110_tmp <= addr110;
--synthesis translate_off
if (CONV_INTEGER(addr110) > mem_size-1) then
addr110_tmp <= (others => '0');
else
addr110_tmp <= addr110;
end if;
--synthesis translate_on
end process;
memory_access_guard_111: process (addr111)
begin
addr111_tmp <= addr111;
--synthesis translate_off
if (CONV_INTEGER(addr111) > mem_size-1) then
addr111_tmp <= (others => '0');
else
addr111_tmp <= addr111;
end if;
--synthesis translate_on
end process;
memory_access_guard_112: process (addr112)
begin
addr112_tmp <= addr112;
--synthesis translate_off
if (CONV_INTEGER(addr112) > mem_size-1) then
addr112_tmp <= (others => '0');
else
addr112_tmp <= addr112;
end if;
--synthesis translate_on
end process;
memory_access_guard_113: process (addr113)
begin
addr113_tmp <= addr113;
--synthesis translate_off
if (CONV_INTEGER(addr113) > mem_size-1) then
addr113_tmp <= (others => '0');
else
addr113_tmp <= addr113;
end if;
--synthesis translate_on
end process;
memory_access_guard_114: process (addr114)
begin
addr114_tmp <= addr114;
--synthesis translate_off
if (CONV_INTEGER(addr114) > mem_size-1) then
addr114_tmp <= (others => '0');
else
addr114_tmp <= addr114;
end if;
--synthesis translate_on
end process;
memory_access_guard_115: process (addr115)
begin
addr115_tmp <= addr115;
--synthesis translate_off
if (CONV_INTEGER(addr115) > mem_size-1) then
addr115_tmp <= (others => '0');
else
addr115_tmp <= addr115;
end if;
--synthesis translate_on
end process;
memory_access_guard_116: process (addr116)
begin
addr116_tmp <= addr116;
--synthesis translate_off
if (CONV_INTEGER(addr116) > mem_size-1) then
addr116_tmp <= (others => '0');
else
addr116_tmp <= addr116;
end if;
--synthesis translate_on
end process;
memory_access_guard_117: process (addr117)
begin
addr117_tmp <= addr117;
--synthesis translate_off
if (CONV_INTEGER(addr117) > mem_size-1) then
addr117_tmp <= (others => '0');
else
addr117_tmp <= addr117;
end if;
--synthesis translate_on
end process;
memory_access_guard_118: process (addr118)
begin
addr118_tmp <= addr118;
--synthesis translate_off
if (CONV_INTEGER(addr118) > mem_size-1) then
addr118_tmp <= (others => '0');
else
addr118_tmp <= addr118;
end if;
--synthesis translate_on
end process;
memory_access_guard_119: process (addr119)
begin
addr119_tmp <= addr119;
--synthesis translate_off
if (CONV_INTEGER(addr119) > mem_size-1) then
addr119_tmp <= (others => '0');
else
addr119_tmp <= addr119;
end if;
--synthesis translate_on
end process;
memory_access_guard_120: process (addr120)
begin
addr120_tmp <= addr120;
--synthesis translate_off
if (CONV_INTEGER(addr120) > mem_size-1) then
addr120_tmp <= (others => '0');
else
addr120_tmp <= addr120;
end if;
--synthesis translate_on
end process;
memory_access_guard_121: process (addr121)
begin
addr121_tmp <= addr121;
--synthesis translate_off
if (CONV_INTEGER(addr121) > mem_size-1) then
addr121_tmp <= (others => '0');
else
addr121_tmp <= addr121;
end if;
--synthesis translate_on
end process;
memory_access_guard_122: process (addr122)
begin
addr122_tmp <= addr122;
--synthesis translate_off
if (CONV_INTEGER(addr122) > mem_size-1) then
addr122_tmp <= (others => '0');
else
addr122_tmp <= addr122;
end if;
--synthesis translate_on
end process;
memory_access_guard_123: process (addr123)
begin
addr123_tmp <= addr123;
--synthesis translate_off
if (CONV_INTEGER(addr123) > mem_size-1) then
addr123_tmp <= (others => '0');
else
addr123_tmp <= addr123;
end if;
--synthesis translate_on
end process;
memory_access_guard_124: process (addr124)
begin
addr124_tmp <= addr124;
--synthesis translate_off
if (CONV_INTEGER(addr124) > mem_size-1) then
addr124_tmp <= (others => '0');
else
addr124_tmp <= addr124;
end if;
--synthesis translate_on
end process;
memory_access_guard_125: process (addr125)
begin
addr125_tmp <= addr125;
--synthesis translate_off
if (CONV_INTEGER(addr125) > mem_size-1) then
addr125_tmp <= (others => '0');
else
addr125_tmp <= addr125;
end if;
--synthesis translate_on
end process;
memory_access_guard_126: process (addr126)
begin
addr126_tmp <= addr126;
--synthesis translate_off
if (CONV_INTEGER(addr126) > mem_size-1) then
addr126_tmp <= (others => '0');
else
addr126_tmp <= addr126;
end if;
--synthesis translate_on
end process;
memory_access_guard_127: process (addr127)
begin
addr127_tmp <= addr127;
--synthesis translate_off
if (CONV_INTEGER(addr127) > mem_size-1) then
addr127_tmp <= (others => '0');
else
addr127_tmp <= addr127;
end if;
--synthesis translate_on
end process;
memory_access_guard_128: process (addr128)
begin
addr128_tmp <= addr128;
--synthesis translate_off
if (CONV_INTEGER(addr128) > mem_size-1) then
addr128_tmp <= (others => '0');
else
addr128_tmp <= addr128;
end if;
--synthesis translate_on
end process;
memory_access_guard_129: process (addr129)
begin
addr129_tmp <= addr129;
--synthesis translate_off
if (CONV_INTEGER(addr129) > mem_size-1) then
addr129_tmp <= (others => '0');
else
addr129_tmp <= addr129;
end if;
--synthesis translate_on
end process;
memory_access_guard_130: process (addr130)
begin
addr130_tmp <= addr130;
--synthesis translate_off
if (CONV_INTEGER(addr130) > mem_size-1) then
addr130_tmp <= (others => '0');
else
addr130_tmp <= addr130;
end if;
--synthesis translate_on
end process;
memory_access_guard_131: process (addr131)
begin
addr131_tmp <= addr131;
--synthesis translate_off
if (CONV_INTEGER(addr131) > mem_size-1) then
addr131_tmp <= (others => '0');
else
addr131_tmp <= addr131;
end if;
--synthesis translate_on
end process;
memory_access_guard_132: process (addr132)
begin
addr132_tmp <= addr132;
--synthesis translate_off
if (CONV_INTEGER(addr132) > mem_size-1) then
addr132_tmp <= (others => '0');
else
addr132_tmp <= addr132;
end if;
--synthesis translate_on
end process;
memory_access_guard_133: process (addr133)
begin
addr133_tmp <= addr133;
--synthesis translate_off
if (CONV_INTEGER(addr133) > mem_size-1) then
addr133_tmp <= (others => '0');
else
addr133_tmp <= addr133;
end if;
--synthesis translate_on
end process;
memory_access_guard_134: process (addr134)
begin
addr134_tmp <= addr134;
--synthesis translate_off
if (CONV_INTEGER(addr134) > mem_size-1) then
addr134_tmp <= (others => '0');
else
addr134_tmp <= addr134;
end if;
--synthesis translate_on
end process;
memory_access_guard_135: process (addr135)
begin
addr135_tmp <= addr135;
--synthesis translate_off
if (CONV_INTEGER(addr135) > mem_size-1) then
addr135_tmp <= (others => '0');
else
addr135_tmp <= addr135;
end if;
--synthesis translate_on
end process;
memory_access_guard_136: process (addr136)
begin
addr136_tmp <= addr136;
--synthesis translate_off
if (CONV_INTEGER(addr136) > mem_size-1) then
addr136_tmp <= (others => '0');
else
addr136_tmp <= addr136;
end if;
--synthesis translate_on
end process;
memory_access_guard_137: process (addr137)
begin
addr137_tmp <= addr137;
--synthesis translate_off
if (CONV_INTEGER(addr137) > mem_size-1) then
addr137_tmp <= (others => '0');
else
addr137_tmp <= addr137;
end if;
--synthesis translate_on
end process;
memory_access_guard_138: process (addr138)
begin
addr138_tmp <= addr138;
--synthesis translate_off
if (CONV_INTEGER(addr138) > mem_size-1) then
addr138_tmp <= (others => '0');
else
addr138_tmp <= addr138;
end if;
--synthesis translate_on
end process;
memory_access_guard_139: process (addr139)
begin
addr139_tmp <= addr139;
--synthesis translate_off
if (CONV_INTEGER(addr139) > mem_size-1) then
addr139_tmp <= (others => '0');
else
addr139_tmp <= addr139;
end if;
--synthesis translate_on
end process;
memory_access_guard_140: process (addr140)
begin
addr140_tmp <= addr140;
--synthesis translate_off
if (CONV_INTEGER(addr140) > mem_size-1) then
addr140_tmp <= (others => '0');
else
addr140_tmp <= addr140;
end if;
--synthesis translate_on
end process;
memory_access_guard_141: process (addr141)
begin
addr141_tmp <= addr141;
--synthesis translate_off
if (CONV_INTEGER(addr141) > mem_size-1) then
addr141_tmp <= (others => '0');
else
addr141_tmp <= addr141;
end if;
--synthesis translate_on
end process;
memory_access_guard_142: process (addr142)
begin
addr142_tmp <= addr142;
--synthesis translate_off
if (CONV_INTEGER(addr142) > mem_size-1) then
addr142_tmp <= (others => '0');
else
addr142_tmp <= addr142;
end if;
--synthesis translate_on
end process;
memory_access_guard_143: process (addr143)
begin
addr143_tmp <= addr143;
--synthesis translate_off
if (CONV_INTEGER(addr143) > mem_size-1) then
addr143_tmp <= (others => '0');
else
addr143_tmp <= addr143;
end if;
--synthesis translate_on
end process;
memory_access_guard_144: process (addr144)
begin
addr144_tmp <= addr144;
--synthesis translate_off
if (CONV_INTEGER(addr144) > mem_size-1) then
addr144_tmp <= (others => '0');
else
addr144_tmp <= addr144;
end if;
--synthesis translate_on
end process;
memory_access_guard_145: process (addr145)
begin
addr145_tmp <= addr145;
--synthesis translate_off
if (CONV_INTEGER(addr145) > mem_size-1) then
addr145_tmp <= (others => '0');
else
addr145_tmp <= addr145;
end if;
--synthesis translate_on
end process;
memory_access_guard_146: process (addr146)
begin
addr146_tmp <= addr146;
--synthesis translate_off
if (CONV_INTEGER(addr146) > mem_size-1) then
addr146_tmp <= (others => '0');
else
addr146_tmp <= addr146;
end if;
--synthesis translate_on
end process;
memory_access_guard_147: process (addr147)
begin
addr147_tmp <= addr147;
--synthesis translate_off
if (CONV_INTEGER(addr147) > mem_size-1) then
addr147_tmp <= (others => '0');
else
addr147_tmp <= addr147;
end if;
--synthesis translate_on
end process;
memory_access_guard_148: process (addr148)
begin
addr148_tmp <= addr148;
--synthesis translate_off
if (CONV_INTEGER(addr148) > mem_size-1) then
addr148_tmp <= (others => '0');
else
addr148_tmp <= addr148;
end if;
--synthesis translate_on
end process;
memory_access_guard_149: process (addr149)
begin
addr149_tmp <= addr149;
--synthesis translate_off
if (CONV_INTEGER(addr149) > mem_size-1) then
addr149_tmp <= (others => '0');
else
addr149_tmp <= addr149;
end if;
--synthesis translate_on
end process;
memory_access_guard_150: process (addr150)
begin
addr150_tmp <= addr150;
--synthesis translate_off
if (CONV_INTEGER(addr150) > mem_size-1) then
addr150_tmp <= (others => '0');
else
addr150_tmp <= addr150;
end if;
--synthesis translate_on
end process;
memory_access_guard_151: process (addr151)
begin
addr151_tmp <= addr151;
--synthesis translate_off
if (CONV_INTEGER(addr151) > mem_size-1) then
addr151_tmp <= (others => '0');
else
addr151_tmp <= addr151;
end if;
--synthesis translate_on
end process;
memory_access_guard_152: process (addr152)
begin
addr152_tmp <= addr152;
--synthesis translate_off
if (CONV_INTEGER(addr152) > mem_size-1) then
addr152_tmp <= (others => '0');
else
addr152_tmp <= addr152;
end if;
--synthesis translate_on
end process;
memory_access_guard_153: process (addr153)
begin
addr153_tmp <= addr153;
--synthesis translate_off
if (CONV_INTEGER(addr153) > mem_size-1) then
addr153_tmp <= (others => '0');
else
addr153_tmp <= addr153;
end if;
--synthesis translate_on
end process;
memory_access_guard_154: process (addr154)
begin
addr154_tmp <= addr154;
--synthesis translate_off
if (CONV_INTEGER(addr154) > mem_size-1) then
addr154_tmp <= (others => '0');
else
addr154_tmp <= addr154;
end if;
--synthesis translate_on
end process;
memory_access_guard_155: process (addr155)
begin
addr155_tmp <= addr155;
--synthesis translate_off
if (CONV_INTEGER(addr155) > mem_size-1) then
addr155_tmp <= (others => '0');
else
addr155_tmp <= addr155;
end if;
--synthesis translate_on
end process;
memory_access_guard_156: process (addr156)
begin
addr156_tmp <= addr156;
--synthesis translate_off
if (CONV_INTEGER(addr156) > mem_size-1) then
addr156_tmp <= (others => '0');
else
addr156_tmp <= addr156;
end if;
--synthesis translate_on
end process;
memory_access_guard_157: process (addr157)
begin
addr157_tmp <= addr157;
--synthesis translate_off
if (CONV_INTEGER(addr157) > mem_size-1) then
addr157_tmp <= (others => '0');
else
addr157_tmp <= addr157;
end if;
--synthesis translate_on
end process;
memory_access_guard_158: process (addr158)
begin
addr158_tmp <= addr158;
--synthesis translate_off
if (CONV_INTEGER(addr158) > mem_size-1) then
addr158_tmp <= (others => '0');
else
addr158_tmp <= addr158;
end if;
--synthesis translate_on
end process;
memory_access_guard_159: process (addr159)
begin
addr159_tmp <= addr159;
--synthesis translate_off
if (CONV_INTEGER(addr159) > mem_size-1) then
addr159_tmp <= (others => '0');
else
addr159_tmp <= addr159;
end if;
--synthesis translate_on
end process;
memory_access_guard_160: process (addr160)
begin
addr160_tmp <= addr160;
--synthesis translate_off
if (CONV_INTEGER(addr160) > mem_size-1) then
addr160_tmp <= (others => '0');
else
addr160_tmp <= addr160;
end if;
--synthesis translate_on
end process;
memory_access_guard_161: process (addr161)
begin
addr161_tmp <= addr161;
--synthesis translate_off
if (CONV_INTEGER(addr161) > mem_size-1) then
addr161_tmp <= (others => '0');
else
addr161_tmp <= addr161;
end if;
--synthesis translate_on
end process;
memory_access_guard_162: process (addr162)
begin
addr162_tmp <= addr162;
--synthesis translate_off
if (CONV_INTEGER(addr162) > mem_size-1) then
addr162_tmp <= (others => '0');
else
addr162_tmp <= addr162;
end if;
--synthesis translate_on
end process;
memory_access_guard_163: process (addr163)
begin
addr163_tmp <= addr163;
--synthesis translate_off
if (CONV_INTEGER(addr163) > mem_size-1) then
addr163_tmp <= (others => '0');
else
addr163_tmp <= addr163;
end if;
--synthesis translate_on
end process;
memory_access_guard_164: process (addr164)
begin
addr164_tmp <= addr164;
--synthesis translate_off
if (CONV_INTEGER(addr164) > mem_size-1) then
addr164_tmp <= (others => '0');
else
addr164_tmp <= addr164;
end if;
--synthesis translate_on
end process;
memory_access_guard_165: process (addr165)
begin
addr165_tmp <= addr165;
--synthesis translate_off
if (CONV_INTEGER(addr165) > mem_size-1) then
addr165_tmp <= (others => '0');
else
addr165_tmp <= addr165;
end if;
--synthesis translate_on
end process;
memory_access_guard_166: process (addr166)
begin
addr166_tmp <= addr166;
--synthesis translate_off
if (CONV_INTEGER(addr166) > mem_size-1) then
addr166_tmp <= (others => '0');
else
addr166_tmp <= addr166;
end if;
--synthesis translate_on
end process;
memory_access_guard_167: process (addr167)
begin
addr167_tmp <= addr167;
--synthesis translate_off
if (CONV_INTEGER(addr167) > mem_size-1) then
addr167_tmp <= (others => '0');
else
addr167_tmp <= addr167;
end if;
--synthesis translate_on
end process;
memory_access_guard_168: process (addr168)
begin
addr168_tmp <= addr168;
--synthesis translate_off
if (CONV_INTEGER(addr168) > mem_size-1) then
addr168_tmp <= (others => '0');
else
addr168_tmp <= addr168;
end if;
--synthesis translate_on
end process;
memory_access_guard_169: process (addr169)
begin
addr169_tmp <= addr169;
--synthesis translate_off
if (CONV_INTEGER(addr169) > mem_size-1) then
addr169_tmp <= (others => '0');
else
addr169_tmp <= addr169;
end if;
--synthesis translate_on
end process;
memory_access_guard_170: process (addr170)
begin
addr170_tmp <= addr170;
--synthesis translate_off
if (CONV_INTEGER(addr170) > mem_size-1) then
addr170_tmp <= (others => '0');
else
addr170_tmp <= addr170;
end if;
--synthesis translate_on
end process;
memory_access_guard_171: process (addr171)
begin
addr171_tmp <= addr171;
--synthesis translate_off
if (CONV_INTEGER(addr171) > mem_size-1) then
addr171_tmp <= (others => '0');
else
addr171_tmp <= addr171;
end if;
--synthesis translate_on
end process;
memory_access_guard_172: process (addr172)
begin
addr172_tmp <= addr172;
--synthesis translate_off
if (CONV_INTEGER(addr172) > mem_size-1) then
addr172_tmp <= (others => '0');
else
addr172_tmp <= addr172;
end if;
--synthesis translate_on
end process;
memory_access_guard_173: process (addr173)
begin
addr173_tmp <= addr173;
--synthesis translate_off
if (CONV_INTEGER(addr173) > mem_size-1) then
addr173_tmp <= (others => '0');
else
addr173_tmp <= addr173;
end if;
--synthesis translate_on
end process;
memory_access_guard_174: process (addr174)
begin
addr174_tmp <= addr174;
--synthesis translate_off
if (CONV_INTEGER(addr174) > mem_size-1) then
addr174_tmp <= (others => '0');
else
addr174_tmp <= addr174;
end if;
--synthesis translate_on
end process;
memory_access_guard_175: process (addr175)
begin
addr175_tmp <= addr175;
--synthesis translate_off
if (CONV_INTEGER(addr175) > mem_size-1) then
addr175_tmp <= (others => '0');
else
addr175_tmp <= addr175;
end if;
--synthesis translate_on
end process;
memory_access_guard_176: process (addr176)
begin
addr176_tmp <= addr176;
--synthesis translate_off
if (CONV_INTEGER(addr176) > mem_size-1) then
addr176_tmp <= (others => '0');
else
addr176_tmp <= addr176;
end if;
--synthesis translate_on
end process;
memory_access_guard_177: process (addr177)
begin
addr177_tmp <= addr177;
--synthesis translate_off
if (CONV_INTEGER(addr177) > mem_size-1) then
addr177_tmp <= (others => '0');
else
addr177_tmp <= addr177;
end if;
--synthesis translate_on
end process;
memory_access_guard_178: process (addr178)
begin
addr178_tmp <= addr178;
--synthesis translate_off
if (CONV_INTEGER(addr178) > mem_size-1) then
addr178_tmp <= (others => '0');
else
addr178_tmp <= addr178;
end if;
--synthesis translate_on
end process;
memory_access_guard_179: process (addr179)
begin
addr179_tmp <= addr179;
--synthesis translate_off
if (CONV_INTEGER(addr179) > mem_size-1) then
addr179_tmp <= (others => '0');
else
addr179_tmp <= addr179;
end if;
--synthesis translate_on
end process;
memory_access_guard_180: process (addr180)
begin
addr180_tmp <= addr180;
--synthesis translate_off
if (CONV_INTEGER(addr180) > mem_size-1) then
addr180_tmp <= (others => '0');
else
addr180_tmp <= addr180;
end if;
--synthesis translate_on
end process;
memory_access_guard_181: process (addr181)
begin
addr181_tmp <= addr181;
--synthesis translate_off
if (CONV_INTEGER(addr181) > mem_size-1) then
addr181_tmp <= (others => '0');
else
addr181_tmp <= addr181;
end if;
--synthesis translate_on
end process;
memory_access_guard_182: process (addr182)
begin
addr182_tmp <= addr182;
--synthesis translate_off
if (CONV_INTEGER(addr182) > mem_size-1) then
addr182_tmp <= (others => '0');
else
addr182_tmp <= addr182;
end if;
--synthesis translate_on
end process;
memory_access_guard_183: process (addr183)
begin
addr183_tmp <= addr183;
--synthesis translate_off
if (CONV_INTEGER(addr183) > mem_size-1) then
addr183_tmp <= (others => '0');
else
addr183_tmp <= addr183;
end if;
--synthesis translate_on
end process;
memory_access_guard_184: process (addr184)
begin
addr184_tmp <= addr184;
--synthesis translate_off
if (CONV_INTEGER(addr184) > mem_size-1) then
addr184_tmp <= (others => '0');
else
addr184_tmp <= addr184;
end if;
--synthesis translate_on
end process;
memory_access_guard_185: process (addr185)
begin
addr185_tmp <= addr185;
--synthesis translate_off
if (CONV_INTEGER(addr185) > mem_size-1) then
addr185_tmp <= (others => '0');
else
addr185_tmp <= addr185;
end if;
--synthesis translate_on
end process;
memory_access_guard_186: process (addr186)
begin
addr186_tmp <= addr186;
--synthesis translate_off
if (CONV_INTEGER(addr186) > mem_size-1) then
addr186_tmp <= (others => '0');
else
addr186_tmp <= addr186;
end if;
--synthesis translate_on
end process;
memory_access_guard_187: process (addr187)
begin
addr187_tmp <= addr187;
--synthesis translate_off
if (CONV_INTEGER(addr187) > mem_size-1) then
addr187_tmp <= (others => '0');
else
addr187_tmp <= addr187;
end if;
--synthesis translate_on
end process;
memory_access_guard_188: process (addr188)
begin
addr188_tmp <= addr188;
--synthesis translate_off
if (CONV_INTEGER(addr188) > mem_size-1) then
addr188_tmp <= (others => '0');
else
addr188_tmp <= addr188;
end if;
--synthesis translate_on
end process;
memory_access_guard_189: process (addr189)
begin
addr189_tmp <= addr189;
--synthesis translate_off
if (CONV_INTEGER(addr189) > mem_size-1) then
addr189_tmp <= (others => '0');
else
addr189_tmp <= addr189;
end if;
--synthesis translate_on
end process;
memory_access_guard_190: process (addr190)
begin
addr190_tmp <= addr190;
--synthesis translate_off
if (CONV_INTEGER(addr190) > mem_size-1) then
addr190_tmp <= (others => '0');
else
addr190_tmp <= addr190;
end if;
--synthesis translate_on
end process;
memory_access_guard_191: process (addr191)
begin
addr191_tmp <= addr191;
--synthesis translate_off
if (CONV_INTEGER(addr191) > mem_size-1) then
addr191_tmp <= (others => '0');
else
addr191_tmp <= addr191;
end if;
--synthesis translate_on
end process;
memory_access_guard_192: process (addr192)
begin
addr192_tmp <= addr192;
--synthesis translate_off
if (CONV_INTEGER(addr192) > mem_size-1) then
addr192_tmp <= (others => '0');
else
addr192_tmp <= addr192;
end if;
--synthesis translate_on
end process;
memory_access_guard_193: process (addr193)
begin
addr193_tmp <= addr193;
--synthesis translate_off
if (CONV_INTEGER(addr193) > mem_size-1) then
addr193_tmp <= (others => '0');
else
addr193_tmp <= addr193;
end if;
--synthesis translate_on
end process;
memory_access_guard_194: process (addr194)
begin
addr194_tmp <= addr194;
--synthesis translate_off
if (CONV_INTEGER(addr194) > mem_size-1) then
addr194_tmp <= (others => '0');
else
addr194_tmp <= addr194;
end if;
--synthesis translate_on
end process;
memory_access_guard_195: process (addr195)
begin
addr195_tmp <= addr195;
--synthesis translate_off
if (CONV_INTEGER(addr195) > mem_size-1) then
addr195_tmp <= (others => '0');
else
addr195_tmp <= addr195;
end if;
--synthesis translate_on
end process;
memory_access_guard_196: process (addr196)
begin
addr196_tmp <= addr196;
--synthesis translate_off
if (CONV_INTEGER(addr196) > mem_size-1) then
addr196_tmp <= (others => '0');
else
addr196_tmp <= addr196;
end if;
--synthesis translate_on
end process;
memory_access_guard_197: process (addr197)
begin
addr197_tmp <= addr197;
--synthesis translate_off
if (CONV_INTEGER(addr197) > mem_size-1) then
addr197_tmp <= (others => '0');
else
addr197_tmp <= addr197;
end if;
--synthesis translate_on
end process;
memory_access_guard_198: process (addr198)
begin
addr198_tmp <= addr198;
--synthesis translate_off
if (CONV_INTEGER(addr198) > mem_size-1) then
addr198_tmp <= (others => '0');
else
addr198_tmp <= addr198;
end if;
--synthesis translate_on
end process;
memory_access_guard_199: process (addr199)
begin
addr199_tmp <= addr199;
--synthesis translate_off
if (CONV_INTEGER(addr199) > mem_size-1) then
addr199_tmp <= (others => '0');
else
addr199_tmp <= addr199;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
if (ce3 = '1') then
q3 <= mem1(CONV_INTEGER(addr3_tmp));
end if;
if (ce4 = '1') then
q4 <= mem2(CONV_INTEGER(addr4_tmp));
end if;
if (ce5 = '1') then
q5 <= mem2(CONV_INTEGER(addr5_tmp));
end if;
if (ce6 = '1') then
q6 <= mem3(CONV_INTEGER(addr6_tmp));
end if;
if (ce7 = '1') then
q7 <= mem3(CONV_INTEGER(addr7_tmp));
end if;
if (ce8 = '1') then
q8 <= mem4(CONV_INTEGER(addr8_tmp));
end if;
if (ce9 = '1') then
q9 <= mem4(CONV_INTEGER(addr9_tmp));
end if;
if (ce10 = '1') then
q10 <= mem5(CONV_INTEGER(addr10_tmp));
end if;
if (ce11 = '1') then
q11 <= mem5(CONV_INTEGER(addr11_tmp));
end if;
if (ce12 = '1') then
q12 <= mem6(CONV_INTEGER(addr12_tmp));
end if;
if (ce13 = '1') then
q13 <= mem6(CONV_INTEGER(addr13_tmp));
end if;
if (ce14 = '1') then
q14 <= mem7(CONV_INTEGER(addr14_tmp));
end if;
if (ce15 = '1') then
q15 <= mem7(CONV_INTEGER(addr15_tmp));
end if;
if (ce16 = '1') then
q16 <= mem8(CONV_INTEGER(addr16_tmp));
end if;
if (ce17 = '1') then
q17 <= mem8(CONV_INTEGER(addr17_tmp));
end if;
if (ce18 = '1') then
q18 <= mem9(CONV_INTEGER(addr18_tmp));
end if;
if (ce19 = '1') then
q19 <= mem9(CONV_INTEGER(addr19_tmp));
end if;
if (ce20 = '1') then
q20 <= mem10(CONV_INTEGER(addr20_tmp));
end if;
if (ce21 = '1') then
q21 <= mem10(CONV_INTEGER(addr21_tmp));
end if;
if (ce22 = '1') then
q22 <= mem11(CONV_INTEGER(addr22_tmp));
end if;
if (ce23 = '1') then
q23 <= mem11(CONV_INTEGER(addr23_tmp));
end if;
if (ce24 = '1') then
q24 <= mem12(CONV_INTEGER(addr24_tmp));
end if;
if (ce25 = '1') then
q25 <= mem12(CONV_INTEGER(addr25_tmp));
end if;
if (ce26 = '1') then
q26 <= mem13(CONV_INTEGER(addr26_tmp));
end if;
if (ce27 = '1') then
q27 <= mem13(CONV_INTEGER(addr27_tmp));
end if;
if (ce28 = '1') then
q28 <= mem14(CONV_INTEGER(addr28_tmp));
end if;
if (ce29 = '1') then
q29 <= mem14(CONV_INTEGER(addr29_tmp));
end if;
if (ce30 = '1') then
q30 <= mem15(CONV_INTEGER(addr30_tmp));
end if;
if (ce31 = '1') then
q31 <= mem15(CONV_INTEGER(addr31_tmp));
end if;
if (ce32 = '1') then
q32 <= mem16(CONV_INTEGER(addr32_tmp));
end if;
if (ce33 = '1') then
q33 <= mem16(CONV_INTEGER(addr33_tmp));
end if;
if (ce34 = '1') then
q34 <= mem17(CONV_INTEGER(addr34_tmp));
end if;
if (ce35 = '1') then
q35 <= mem17(CONV_INTEGER(addr35_tmp));
end if;
if (ce36 = '1') then
q36 <= mem18(CONV_INTEGER(addr36_tmp));
end if;
if (ce37 = '1') then
q37 <= mem18(CONV_INTEGER(addr37_tmp));
end if;
if (ce38 = '1') then
q38 <= mem19(CONV_INTEGER(addr38_tmp));
end if;
if (ce39 = '1') then
q39 <= mem19(CONV_INTEGER(addr39_tmp));
end if;
if (ce40 = '1') then
q40 <= mem20(CONV_INTEGER(addr40_tmp));
end if;
if (ce41 = '1') then
q41 <= mem20(CONV_INTEGER(addr41_tmp));
end if;
if (ce42 = '1') then
q42 <= mem21(CONV_INTEGER(addr42_tmp));
end if;
if (ce43 = '1') then
q43 <= mem21(CONV_INTEGER(addr43_tmp));
end if;
if (ce44 = '1') then
q44 <= mem22(CONV_INTEGER(addr44_tmp));
end if;
if (ce45 = '1') then
q45 <= mem22(CONV_INTEGER(addr45_tmp));
end if;
if (ce46 = '1') then
q46 <= mem23(CONV_INTEGER(addr46_tmp));
end if;
if (ce47 = '1') then
q47 <= mem23(CONV_INTEGER(addr47_tmp));
end if;
if (ce48 = '1') then
q48 <= mem24(CONV_INTEGER(addr48_tmp));
end if;
if (ce49 = '1') then
q49 <= mem24(CONV_INTEGER(addr49_tmp));
end if;
if (ce50 = '1') then
q50 <= mem25(CONV_INTEGER(addr50_tmp));
end if;
if (ce51 = '1') then
q51 <= mem25(CONV_INTEGER(addr51_tmp));
end if;
if (ce52 = '1') then
q52 <= mem26(CONV_INTEGER(addr52_tmp));
end if;
if (ce53 = '1') then
q53 <= mem26(CONV_INTEGER(addr53_tmp));
end if;
if (ce54 = '1') then
q54 <= mem27(CONV_INTEGER(addr54_tmp));
end if;
if (ce55 = '1') then
q55 <= mem27(CONV_INTEGER(addr55_tmp));
end if;
if (ce56 = '1') then
q56 <= mem28(CONV_INTEGER(addr56_tmp));
end if;
if (ce57 = '1') then
q57 <= mem28(CONV_INTEGER(addr57_tmp));
end if;
if (ce58 = '1') then
q58 <= mem29(CONV_INTEGER(addr58_tmp));
end if;
if (ce59 = '1') then
q59 <= mem29(CONV_INTEGER(addr59_tmp));
end if;
if (ce60 = '1') then
q60 <= mem30(CONV_INTEGER(addr60_tmp));
end if;
if (ce61 = '1') then
q61 <= mem30(CONV_INTEGER(addr61_tmp));
end if;
if (ce62 = '1') then
q62 <= mem31(CONV_INTEGER(addr62_tmp));
end if;
if (ce63 = '1') then
q63 <= mem31(CONV_INTEGER(addr63_tmp));
end if;
if (ce64 = '1') then
q64 <= mem32(CONV_INTEGER(addr64_tmp));
end if;
if (ce65 = '1') then
q65 <= mem32(CONV_INTEGER(addr65_tmp));
end if;
if (ce66 = '1') then
q66 <= mem33(CONV_INTEGER(addr66_tmp));
end if;
if (ce67 = '1') then
q67 <= mem33(CONV_INTEGER(addr67_tmp));
end if;
if (ce68 = '1') then
q68 <= mem34(CONV_INTEGER(addr68_tmp));
end if;
if (ce69 = '1') then
q69 <= mem34(CONV_INTEGER(addr69_tmp));
end if;
if (ce70 = '1') then
q70 <= mem35(CONV_INTEGER(addr70_tmp));
end if;
if (ce71 = '1') then
q71 <= mem35(CONV_INTEGER(addr71_tmp));
end if;
if (ce72 = '1') then
q72 <= mem36(CONV_INTEGER(addr72_tmp));
end if;
if (ce73 = '1') then
q73 <= mem36(CONV_INTEGER(addr73_tmp));
end if;
if (ce74 = '1') then
q74 <= mem37(CONV_INTEGER(addr74_tmp));
end if;
if (ce75 = '1') then
q75 <= mem37(CONV_INTEGER(addr75_tmp));
end if;
if (ce76 = '1') then
q76 <= mem38(CONV_INTEGER(addr76_tmp));
end if;
if (ce77 = '1') then
q77 <= mem38(CONV_INTEGER(addr77_tmp));
end if;
if (ce78 = '1') then
q78 <= mem39(CONV_INTEGER(addr78_tmp));
end if;
if (ce79 = '1') then
q79 <= mem39(CONV_INTEGER(addr79_tmp));
end if;
if (ce80 = '1') then
q80 <= mem40(CONV_INTEGER(addr80_tmp));
end if;
if (ce81 = '1') then
q81 <= mem40(CONV_INTEGER(addr81_tmp));
end if;
if (ce82 = '1') then
q82 <= mem41(CONV_INTEGER(addr82_tmp));
end if;
if (ce83 = '1') then
q83 <= mem41(CONV_INTEGER(addr83_tmp));
end if;
if (ce84 = '1') then
q84 <= mem42(CONV_INTEGER(addr84_tmp));
end if;
if (ce85 = '1') then
q85 <= mem42(CONV_INTEGER(addr85_tmp));
end if;
if (ce86 = '1') then
q86 <= mem43(CONV_INTEGER(addr86_tmp));
end if;
if (ce87 = '1') then
q87 <= mem43(CONV_INTEGER(addr87_tmp));
end if;
if (ce88 = '1') then
q88 <= mem44(CONV_INTEGER(addr88_tmp));
end if;
if (ce89 = '1') then
q89 <= mem44(CONV_INTEGER(addr89_tmp));
end if;
if (ce90 = '1') then
q90 <= mem45(CONV_INTEGER(addr90_tmp));
end if;
if (ce91 = '1') then
q91 <= mem45(CONV_INTEGER(addr91_tmp));
end if;
if (ce92 = '1') then
q92 <= mem46(CONV_INTEGER(addr92_tmp));
end if;
if (ce93 = '1') then
q93 <= mem46(CONV_INTEGER(addr93_tmp));
end if;
if (ce94 = '1') then
q94 <= mem47(CONV_INTEGER(addr94_tmp));
end if;
if (ce95 = '1') then
q95 <= mem47(CONV_INTEGER(addr95_tmp));
end if;
if (ce96 = '1') then
q96 <= mem48(CONV_INTEGER(addr96_tmp));
end if;
if (ce97 = '1') then
q97 <= mem48(CONV_INTEGER(addr97_tmp));
end if;
if (ce98 = '1') then
q98 <= mem49(CONV_INTEGER(addr98_tmp));
end if;
if (ce99 = '1') then
q99 <= mem49(CONV_INTEGER(addr99_tmp));
end if;
if (ce100 = '1') then
q100 <= mem50(CONV_INTEGER(addr100_tmp));
end if;
if (ce101 = '1') then
q101 <= mem50(CONV_INTEGER(addr101_tmp));
end if;
if (ce102 = '1') then
q102 <= mem51(CONV_INTEGER(addr102_tmp));
end if;
if (ce103 = '1') then
q103 <= mem51(CONV_INTEGER(addr103_tmp));
end if;
if (ce104 = '1') then
q104 <= mem52(CONV_INTEGER(addr104_tmp));
end if;
if (ce105 = '1') then
q105 <= mem52(CONV_INTEGER(addr105_tmp));
end if;
if (ce106 = '1') then
q106 <= mem53(CONV_INTEGER(addr106_tmp));
end if;
if (ce107 = '1') then
q107 <= mem53(CONV_INTEGER(addr107_tmp));
end if;
if (ce108 = '1') then
q108 <= mem54(CONV_INTEGER(addr108_tmp));
end if;
if (ce109 = '1') then
q109 <= mem54(CONV_INTEGER(addr109_tmp));
end if;
if (ce110 = '1') then
q110 <= mem55(CONV_INTEGER(addr110_tmp));
end if;
if (ce111 = '1') then
q111 <= mem55(CONV_INTEGER(addr111_tmp));
end if;
if (ce112 = '1') then
q112 <= mem56(CONV_INTEGER(addr112_tmp));
end if;
if (ce113 = '1') then
q113 <= mem56(CONV_INTEGER(addr113_tmp));
end if;
if (ce114 = '1') then
q114 <= mem57(CONV_INTEGER(addr114_tmp));
end if;
if (ce115 = '1') then
q115 <= mem57(CONV_INTEGER(addr115_tmp));
end if;
if (ce116 = '1') then
q116 <= mem58(CONV_INTEGER(addr116_tmp));
end if;
if (ce117 = '1') then
q117 <= mem58(CONV_INTEGER(addr117_tmp));
end if;
if (ce118 = '1') then
q118 <= mem59(CONV_INTEGER(addr118_tmp));
end if;
if (ce119 = '1') then
q119 <= mem59(CONV_INTEGER(addr119_tmp));
end if;
if (ce120 = '1') then
q120 <= mem60(CONV_INTEGER(addr120_tmp));
end if;
if (ce121 = '1') then
q121 <= mem60(CONV_INTEGER(addr121_tmp));
end if;
if (ce122 = '1') then
q122 <= mem61(CONV_INTEGER(addr122_tmp));
end if;
if (ce123 = '1') then
q123 <= mem61(CONV_INTEGER(addr123_tmp));
end if;
if (ce124 = '1') then
q124 <= mem62(CONV_INTEGER(addr124_tmp));
end if;
if (ce125 = '1') then
q125 <= mem62(CONV_INTEGER(addr125_tmp));
end if;
if (ce126 = '1') then
q126 <= mem63(CONV_INTEGER(addr126_tmp));
end if;
if (ce127 = '1') then
q127 <= mem63(CONV_INTEGER(addr127_tmp));
end if;
if (ce128 = '1') then
q128 <= mem64(CONV_INTEGER(addr128_tmp));
end if;
if (ce129 = '1') then
q129 <= mem64(CONV_INTEGER(addr129_tmp));
end if;
if (ce130 = '1') then
q130 <= mem65(CONV_INTEGER(addr130_tmp));
end if;
if (ce131 = '1') then
q131 <= mem65(CONV_INTEGER(addr131_tmp));
end if;
if (ce132 = '1') then
q132 <= mem66(CONV_INTEGER(addr132_tmp));
end if;
if (ce133 = '1') then
q133 <= mem66(CONV_INTEGER(addr133_tmp));
end if;
if (ce134 = '1') then
q134 <= mem67(CONV_INTEGER(addr134_tmp));
end if;
if (ce135 = '1') then
q135 <= mem67(CONV_INTEGER(addr135_tmp));
end if;
if (ce136 = '1') then
q136 <= mem68(CONV_INTEGER(addr136_tmp));
end if;
if (ce137 = '1') then
q137 <= mem68(CONV_INTEGER(addr137_tmp));
end if;
if (ce138 = '1') then
q138 <= mem69(CONV_INTEGER(addr138_tmp));
end if;
if (ce139 = '1') then
q139 <= mem69(CONV_INTEGER(addr139_tmp));
end if;
if (ce140 = '1') then
q140 <= mem70(CONV_INTEGER(addr140_tmp));
end if;
if (ce141 = '1') then
q141 <= mem70(CONV_INTEGER(addr141_tmp));
end if;
if (ce142 = '1') then
q142 <= mem71(CONV_INTEGER(addr142_tmp));
end if;
if (ce143 = '1') then
q143 <= mem71(CONV_INTEGER(addr143_tmp));
end if;
if (ce144 = '1') then
q144 <= mem72(CONV_INTEGER(addr144_tmp));
end if;
if (ce145 = '1') then
q145 <= mem72(CONV_INTEGER(addr145_tmp));
end if;
if (ce146 = '1') then
q146 <= mem73(CONV_INTEGER(addr146_tmp));
end if;
if (ce147 = '1') then
q147 <= mem73(CONV_INTEGER(addr147_tmp));
end if;
if (ce148 = '1') then
q148 <= mem74(CONV_INTEGER(addr148_tmp));
end if;
if (ce149 = '1') then
q149 <= mem74(CONV_INTEGER(addr149_tmp));
end if;
if (ce150 = '1') then
q150 <= mem75(CONV_INTEGER(addr150_tmp));
end if;
if (ce151 = '1') then
q151 <= mem75(CONV_INTEGER(addr151_tmp));
end if;
if (ce152 = '1') then
q152 <= mem76(CONV_INTEGER(addr152_tmp));
end if;
if (ce153 = '1') then
q153 <= mem76(CONV_INTEGER(addr153_tmp));
end if;
if (ce154 = '1') then
q154 <= mem77(CONV_INTEGER(addr154_tmp));
end if;
if (ce155 = '1') then
q155 <= mem77(CONV_INTEGER(addr155_tmp));
end if;
if (ce156 = '1') then
q156 <= mem78(CONV_INTEGER(addr156_tmp));
end if;
if (ce157 = '1') then
q157 <= mem78(CONV_INTEGER(addr157_tmp));
end if;
if (ce158 = '1') then
q158 <= mem79(CONV_INTEGER(addr158_tmp));
end if;
if (ce159 = '1') then
q159 <= mem79(CONV_INTEGER(addr159_tmp));
end if;
if (ce160 = '1') then
q160 <= mem80(CONV_INTEGER(addr160_tmp));
end if;
if (ce161 = '1') then
q161 <= mem80(CONV_INTEGER(addr161_tmp));
end if;
if (ce162 = '1') then
q162 <= mem81(CONV_INTEGER(addr162_tmp));
end if;
if (ce163 = '1') then
q163 <= mem81(CONV_INTEGER(addr163_tmp));
end if;
if (ce164 = '1') then
q164 <= mem82(CONV_INTEGER(addr164_tmp));
end if;
if (ce165 = '1') then
q165 <= mem82(CONV_INTEGER(addr165_tmp));
end if;
if (ce166 = '1') then
q166 <= mem83(CONV_INTEGER(addr166_tmp));
end if;
if (ce167 = '1') then
q167 <= mem83(CONV_INTEGER(addr167_tmp));
end if;
if (ce168 = '1') then
q168 <= mem84(CONV_INTEGER(addr168_tmp));
end if;
if (ce169 = '1') then
q169 <= mem84(CONV_INTEGER(addr169_tmp));
end if;
if (ce170 = '1') then
q170 <= mem85(CONV_INTEGER(addr170_tmp));
end if;
if (ce171 = '1') then
q171 <= mem85(CONV_INTEGER(addr171_tmp));
end if;
if (ce172 = '1') then
q172 <= mem86(CONV_INTEGER(addr172_tmp));
end if;
if (ce173 = '1') then
q173 <= mem86(CONV_INTEGER(addr173_tmp));
end if;
if (ce174 = '1') then
q174 <= mem87(CONV_INTEGER(addr174_tmp));
end if;
if (ce175 = '1') then
q175 <= mem87(CONV_INTEGER(addr175_tmp));
end if;
if (ce176 = '1') then
q176 <= mem88(CONV_INTEGER(addr176_tmp));
end if;
if (ce177 = '1') then
q177 <= mem88(CONV_INTEGER(addr177_tmp));
end if;
if (ce178 = '1') then
q178 <= mem89(CONV_INTEGER(addr178_tmp));
end if;
if (ce179 = '1') then
q179 <= mem89(CONV_INTEGER(addr179_tmp));
end if;
if (ce180 = '1') then
q180 <= mem90(CONV_INTEGER(addr180_tmp));
end if;
if (ce181 = '1') then
q181 <= mem90(CONV_INTEGER(addr181_tmp));
end if;
if (ce182 = '1') then
q182 <= mem91(CONV_INTEGER(addr182_tmp));
end if;
if (ce183 = '1') then
q183 <= mem91(CONV_INTEGER(addr183_tmp));
end if;
if (ce184 = '1') then
q184 <= mem92(CONV_INTEGER(addr184_tmp));
end if;
if (ce185 = '1') then
q185 <= mem92(CONV_INTEGER(addr185_tmp));
end if;
if (ce186 = '1') then
q186 <= mem93(CONV_INTEGER(addr186_tmp));
end if;
if (ce187 = '1') then
q187 <= mem93(CONV_INTEGER(addr187_tmp));
end if;
if (ce188 = '1') then
q188 <= mem94(CONV_INTEGER(addr188_tmp));
end if;
if (ce189 = '1') then
q189 <= mem94(CONV_INTEGER(addr189_tmp));
end if;
if (ce190 = '1') then
q190 <= mem95(CONV_INTEGER(addr190_tmp));
end if;
if (ce191 = '1') then
q191 <= mem95(CONV_INTEGER(addr191_tmp));
end if;
if (ce192 = '1') then
q192 <= mem96(CONV_INTEGER(addr192_tmp));
end if;
if (ce193 = '1') then
q193 <= mem96(CONV_INTEGER(addr193_tmp));
end if;
if (ce194 = '1') then
q194 <= mem97(CONV_INTEGER(addr194_tmp));
end if;
if (ce195 = '1') then
q195 <= mem97(CONV_INTEGER(addr195_tmp));
end if;
if (ce196 = '1') then
q196 <= mem98(CONV_INTEGER(addr196_tmp));
end if;
if (ce197 = '1') then
q197 <= mem98(CONV_INTEGER(addr197_tmp));
end if;
if (ce198 = '1') then
q198 <= mem99(CONV_INTEGER(addr198_tmp));
end if;
if (ce199 = '1') then
q199 <= mem99(CONV_INTEGER(addr199_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity aestest_sboxes is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address3 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce3 : IN STD_LOGIC;
q3 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address4 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce4 : IN STD_LOGIC;
q4 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address5 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce5 : IN STD_LOGIC;
q5 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address6 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce6 : IN STD_LOGIC;
q6 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address7 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce7 : IN STD_LOGIC;
q7 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address8 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce8 : IN STD_LOGIC;
q8 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address9 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce9 : IN STD_LOGIC;
q9 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address10 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce10 : IN STD_LOGIC;
q10 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address11 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce11 : IN STD_LOGIC;
q11 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address12 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce12 : IN STD_LOGIC;
q12 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address13 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce13 : IN STD_LOGIC;
q13 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address14 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce14 : IN STD_LOGIC;
q14 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address15 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce15 : IN STD_LOGIC;
q15 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address16 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce16 : IN STD_LOGIC;
q16 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address17 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce17 : IN STD_LOGIC;
q17 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address18 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce18 : IN STD_LOGIC;
q18 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address19 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce19 : IN STD_LOGIC;
q19 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address20 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce20 : IN STD_LOGIC;
q20 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address21 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce21 : IN STD_LOGIC;
q21 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address22 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce22 : IN STD_LOGIC;
q22 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address23 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce23 : IN STD_LOGIC;
q23 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address24 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce24 : IN STD_LOGIC;
q24 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address25 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce25 : IN STD_LOGIC;
q25 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address26 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce26 : IN STD_LOGIC;
q26 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address27 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce27 : IN STD_LOGIC;
q27 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address28 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce28 : IN STD_LOGIC;
q28 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address29 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce29 : IN STD_LOGIC;
q29 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address30 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce30 : IN STD_LOGIC;
q30 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address31 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce31 : IN STD_LOGIC;
q31 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address32 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce32 : IN STD_LOGIC;
q32 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address33 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce33 : IN STD_LOGIC;
q33 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address34 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce34 : IN STD_LOGIC;
q34 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address35 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce35 : IN STD_LOGIC;
q35 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address36 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce36 : IN STD_LOGIC;
q36 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address37 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce37 : IN STD_LOGIC;
q37 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address38 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce38 : IN STD_LOGIC;
q38 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address39 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce39 : IN STD_LOGIC;
q39 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address40 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce40 : IN STD_LOGIC;
q40 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address41 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce41 : IN STD_LOGIC;
q41 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address42 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce42 : IN STD_LOGIC;
q42 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address43 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce43 : IN STD_LOGIC;
q43 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address44 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce44 : IN STD_LOGIC;
q44 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address45 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce45 : IN STD_LOGIC;
q45 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address46 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce46 : IN STD_LOGIC;
q46 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address47 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce47 : IN STD_LOGIC;
q47 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address48 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce48 : IN STD_LOGIC;
q48 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address49 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce49 : IN STD_LOGIC;
q49 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address50 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce50 : IN STD_LOGIC;
q50 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address51 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce51 : IN STD_LOGIC;
q51 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address52 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce52 : IN STD_LOGIC;
q52 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address53 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce53 : IN STD_LOGIC;
q53 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address54 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce54 : IN STD_LOGIC;
q54 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address55 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce55 : IN STD_LOGIC;
q55 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address56 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce56 : IN STD_LOGIC;
q56 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address57 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce57 : IN STD_LOGIC;
q57 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address58 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce58 : IN STD_LOGIC;
q58 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address59 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce59 : IN STD_LOGIC;
q59 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address60 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce60 : IN STD_LOGIC;
q60 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address61 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce61 : IN STD_LOGIC;
q61 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address62 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce62 : IN STD_LOGIC;
q62 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address63 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce63 : IN STD_LOGIC;
q63 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address64 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce64 : IN STD_LOGIC;
q64 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address65 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce65 : IN STD_LOGIC;
q65 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address66 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce66 : IN STD_LOGIC;
q66 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address67 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce67 : IN STD_LOGIC;
q67 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address68 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce68 : IN STD_LOGIC;
q68 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address69 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce69 : IN STD_LOGIC;
q69 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address70 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce70 : IN STD_LOGIC;
q70 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address71 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce71 : IN STD_LOGIC;
q71 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address72 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce72 : IN STD_LOGIC;
q72 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address73 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce73 : IN STD_LOGIC;
q73 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address74 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce74 : IN STD_LOGIC;
q74 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address75 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce75 : IN STD_LOGIC;
q75 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address76 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce76 : IN STD_LOGIC;
q76 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address77 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce77 : IN STD_LOGIC;
q77 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address78 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce78 : IN STD_LOGIC;
q78 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address79 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce79 : IN STD_LOGIC;
q79 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address80 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce80 : IN STD_LOGIC;
q80 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address81 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce81 : IN STD_LOGIC;
q81 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address82 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce82 : IN STD_LOGIC;
q82 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address83 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce83 : IN STD_LOGIC;
q83 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address84 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce84 : IN STD_LOGIC;
q84 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address85 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce85 : IN STD_LOGIC;
q85 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address86 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce86 : IN STD_LOGIC;
q86 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address87 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce87 : IN STD_LOGIC;
q87 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address88 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce88 : IN STD_LOGIC;
q88 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address89 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce89 : IN STD_LOGIC;
q89 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address90 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce90 : IN STD_LOGIC;
q90 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address91 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce91 : IN STD_LOGIC;
q91 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address92 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce92 : IN STD_LOGIC;
q92 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address93 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce93 : IN STD_LOGIC;
q93 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address94 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce94 : IN STD_LOGIC;
q94 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address95 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce95 : IN STD_LOGIC;
q95 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address96 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce96 : IN STD_LOGIC;
q96 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address97 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce97 : IN STD_LOGIC;
q97 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address98 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce98 : IN STD_LOGIC;
q98 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address99 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce99 : IN STD_LOGIC;
q99 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address100 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce100 : IN STD_LOGIC;
q100 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address101 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce101 : IN STD_LOGIC;
q101 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address102 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce102 : IN STD_LOGIC;
q102 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address103 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce103 : IN STD_LOGIC;
q103 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address104 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce104 : IN STD_LOGIC;
q104 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address105 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce105 : IN STD_LOGIC;
q105 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address106 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce106 : IN STD_LOGIC;
q106 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address107 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce107 : IN STD_LOGIC;
q107 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address108 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce108 : IN STD_LOGIC;
q108 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address109 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce109 : IN STD_LOGIC;
q109 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address110 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce110 : IN STD_LOGIC;
q110 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address111 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce111 : IN STD_LOGIC;
q111 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address112 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce112 : IN STD_LOGIC;
q112 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address113 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce113 : IN STD_LOGIC;
q113 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address114 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce114 : IN STD_LOGIC;
q114 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address115 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce115 : IN STD_LOGIC;
q115 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address116 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce116 : IN STD_LOGIC;
q116 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address117 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce117 : IN STD_LOGIC;
q117 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address118 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce118 : IN STD_LOGIC;
q118 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address119 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce119 : IN STD_LOGIC;
q119 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address120 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce120 : IN STD_LOGIC;
q120 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address121 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce121 : IN STD_LOGIC;
q121 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address122 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce122 : IN STD_LOGIC;
q122 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address123 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce123 : IN STD_LOGIC;
q123 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address124 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce124 : IN STD_LOGIC;
q124 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address125 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce125 : IN STD_LOGIC;
q125 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address126 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce126 : IN STD_LOGIC;
q126 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address127 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce127 : IN STD_LOGIC;
q127 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address128 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce128 : IN STD_LOGIC;
q128 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address129 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce129 : IN STD_LOGIC;
q129 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address130 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce130 : IN STD_LOGIC;
q130 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address131 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce131 : IN STD_LOGIC;
q131 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address132 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce132 : IN STD_LOGIC;
q132 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address133 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce133 : IN STD_LOGIC;
q133 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address134 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce134 : IN STD_LOGIC;
q134 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address135 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce135 : IN STD_LOGIC;
q135 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address136 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce136 : IN STD_LOGIC;
q136 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address137 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce137 : IN STD_LOGIC;
q137 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address138 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce138 : IN STD_LOGIC;
q138 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address139 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce139 : IN STD_LOGIC;
q139 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address140 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce140 : IN STD_LOGIC;
q140 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address141 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce141 : IN STD_LOGIC;
q141 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address142 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce142 : IN STD_LOGIC;
q142 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address143 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce143 : IN STD_LOGIC;
q143 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address144 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce144 : IN STD_LOGIC;
q144 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address145 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce145 : IN STD_LOGIC;
q145 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address146 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce146 : IN STD_LOGIC;
q146 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address147 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce147 : IN STD_LOGIC;
q147 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address148 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce148 : IN STD_LOGIC;
q148 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address149 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce149 : IN STD_LOGIC;
q149 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address150 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce150 : IN STD_LOGIC;
q150 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address151 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce151 : IN STD_LOGIC;
q151 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address152 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce152 : IN STD_LOGIC;
q152 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address153 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce153 : IN STD_LOGIC;
q153 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address154 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce154 : IN STD_LOGIC;
q154 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address155 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce155 : IN STD_LOGIC;
q155 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address156 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce156 : IN STD_LOGIC;
q156 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address157 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce157 : IN STD_LOGIC;
q157 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address158 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce158 : IN STD_LOGIC;
q158 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address159 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce159 : IN STD_LOGIC;
q159 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address160 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce160 : IN STD_LOGIC;
q160 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address161 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce161 : IN STD_LOGIC;
q161 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address162 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce162 : IN STD_LOGIC;
q162 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address163 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce163 : IN STD_LOGIC;
q163 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address164 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce164 : IN STD_LOGIC;
q164 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address165 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce165 : IN STD_LOGIC;
q165 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address166 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce166 : IN STD_LOGIC;
q166 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address167 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce167 : IN STD_LOGIC;
q167 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address168 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce168 : IN STD_LOGIC;
q168 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address169 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce169 : IN STD_LOGIC;
q169 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address170 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce170 : IN STD_LOGIC;
q170 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address171 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce171 : IN STD_LOGIC;
q171 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address172 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce172 : IN STD_LOGIC;
q172 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address173 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce173 : IN STD_LOGIC;
q173 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address174 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce174 : IN STD_LOGIC;
q174 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address175 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce175 : IN STD_LOGIC;
q175 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address176 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce176 : IN STD_LOGIC;
q176 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address177 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce177 : IN STD_LOGIC;
q177 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address178 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce178 : IN STD_LOGIC;
q178 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address179 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce179 : IN STD_LOGIC;
q179 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address180 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce180 : IN STD_LOGIC;
q180 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address181 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce181 : IN STD_LOGIC;
q181 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address182 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce182 : IN STD_LOGIC;
q182 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address183 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce183 : IN STD_LOGIC;
q183 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address184 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce184 : IN STD_LOGIC;
q184 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address185 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce185 : IN STD_LOGIC;
q185 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address186 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce186 : IN STD_LOGIC;
q186 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address187 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce187 : IN STD_LOGIC;
q187 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address188 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce188 : IN STD_LOGIC;
q188 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address189 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce189 : IN STD_LOGIC;
q189 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address190 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce190 : IN STD_LOGIC;
q190 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address191 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce191 : IN STD_LOGIC;
q191 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address192 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce192 : IN STD_LOGIC;
q192 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address193 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce193 : IN STD_LOGIC;
q193 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address194 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce194 : IN STD_LOGIC;
q194 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address195 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce195 : IN STD_LOGIC;
q195 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address196 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce196 : IN STD_LOGIC;
q196 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address197 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce197 : IN STD_LOGIC;
q197 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address198 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce198 : IN STD_LOGIC;
q198 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address199 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce199 : IN STD_LOGIC;
q199 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of aestest_sboxes is
component aestest_sboxes_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR;
addr3 : IN STD_LOGIC_VECTOR;
ce3 : IN STD_LOGIC;
q3 : OUT STD_LOGIC_VECTOR;
addr4 : IN STD_LOGIC_VECTOR;
ce4 : IN STD_LOGIC;
q4 : OUT STD_LOGIC_VECTOR;
addr5 : IN STD_LOGIC_VECTOR;
ce5 : IN STD_LOGIC;
q5 : OUT STD_LOGIC_VECTOR;
addr6 : IN STD_LOGIC_VECTOR;
ce6 : IN STD_LOGIC;
q6 : OUT STD_LOGIC_VECTOR;
addr7 : IN STD_LOGIC_VECTOR;
ce7 : IN STD_LOGIC;
q7 : OUT STD_LOGIC_VECTOR;
addr8 : IN STD_LOGIC_VECTOR;
ce8 : IN STD_LOGIC;
q8 : OUT STD_LOGIC_VECTOR;
addr9 : IN STD_LOGIC_VECTOR;
ce9 : IN STD_LOGIC;
q9 : OUT STD_LOGIC_VECTOR;
addr10 : IN STD_LOGIC_VECTOR;
ce10 : IN STD_LOGIC;
q10 : OUT STD_LOGIC_VECTOR;
addr11 : IN STD_LOGIC_VECTOR;
ce11 : IN STD_LOGIC;
q11 : OUT STD_LOGIC_VECTOR;
addr12 : IN STD_LOGIC_VECTOR;
ce12 : IN STD_LOGIC;
q12 : OUT STD_LOGIC_VECTOR;
addr13 : IN STD_LOGIC_VECTOR;
ce13 : IN STD_LOGIC;
q13 : OUT STD_LOGIC_VECTOR;
addr14 : IN STD_LOGIC_VECTOR;
ce14 : IN STD_LOGIC;
q14 : OUT STD_LOGIC_VECTOR;
addr15 : IN STD_LOGIC_VECTOR;
ce15 : IN STD_LOGIC;
q15 : OUT STD_LOGIC_VECTOR;
addr16 : IN STD_LOGIC_VECTOR;
ce16 : IN STD_LOGIC;
q16 : OUT STD_LOGIC_VECTOR;
addr17 : IN STD_LOGIC_VECTOR;
ce17 : IN STD_LOGIC;
q17 : OUT STD_LOGIC_VECTOR;
addr18 : IN STD_LOGIC_VECTOR;
ce18 : IN STD_LOGIC;
q18 : OUT STD_LOGIC_VECTOR;
addr19 : IN STD_LOGIC_VECTOR;
ce19 : IN STD_LOGIC;
q19 : OUT STD_LOGIC_VECTOR;
addr20 : IN STD_LOGIC_VECTOR;
ce20 : IN STD_LOGIC;
q20 : OUT STD_LOGIC_VECTOR;
addr21 : IN STD_LOGIC_VECTOR;
ce21 : IN STD_LOGIC;
q21 : OUT STD_LOGIC_VECTOR;
addr22 : IN STD_LOGIC_VECTOR;
ce22 : IN STD_LOGIC;
q22 : OUT STD_LOGIC_VECTOR;
addr23 : IN STD_LOGIC_VECTOR;
ce23 : IN STD_LOGIC;
q23 : OUT STD_LOGIC_VECTOR;
addr24 : IN STD_LOGIC_VECTOR;
ce24 : IN STD_LOGIC;
q24 : OUT STD_LOGIC_VECTOR;
addr25 : IN STD_LOGIC_VECTOR;
ce25 : IN STD_LOGIC;
q25 : OUT STD_LOGIC_VECTOR;
addr26 : IN STD_LOGIC_VECTOR;
ce26 : IN STD_LOGIC;
q26 : OUT STD_LOGIC_VECTOR;
addr27 : IN STD_LOGIC_VECTOR;
ce27 : IN STD_LOGIC;
q27 : OUT STD_LOGIC_VECTOR;
addr28 : IN STD_LOGIC_VECTOR;
ce28 : IN STD_LOGIC;
q28 : OUT STD_LOGIC_VECTOR;
addr29 : IN STD_LOGIC_VECTOR;
ce29 : IN STD_LOGIC;
q29 : OUT STD_LOGIC_VECTOR;
addr30 : IN STD_LOGIC_VECTOR;
ce30 : IN STD_LOGIC;
q30 : OUT STD_LOGIC_VECTOR;
addr31 : IN STD_LOGIC_VECTOR;
ce31 : IN STD_LOGIC;
q31 : OUT STD_LOGIC_VECTOR;
addr32 : IN STD_LOGIC_VECTOR;
ce32 : IN STD_LOGIC;
q32 : OUT STD_LOGIC_VECTOR;
addr33 : IN STD_LOGIC_VECTOR;
ce33 : IN STD_LOGIC;
q33 : OUT STD_LOGIC_VECTOR;
addr34 : IN STD_LOGIC_VECTOR;
ce34 : IN STD_LOGIC;
q34 : OUT STD_LOGIC_VECTOR;
addr35 : IN STD_LOGIC_VECTOR;
ce35 : IN STD_LOGIC;
q35 : OUT STD_LOGIC_VECTOR;
addr36 : IN STD_LOGIC_VECTOR;
ce36 : IN STD_LOGIC;
q36 : OUT STD_LOGIC_VECTOR;
addr37 : IN STD_LOGIC_VECTOR;
ce37 : IN STD_LOGIC;
q37 : OUT STD_LOGIC_VECTOR;
addr38 : IN STD_LOGIC_VECTOR;
ce38 : IN STD_LOGIC;
q38 : OUT STD_LOGIC_VECTOR;
addr39 : IN STD_LOGIC_VECTOR;
ce39 : IN STD_LOGIC;
q39 : OUT STD_LOGIC_VECTOR;
addr40 : IN STD_LOGIC_VECTOR;
ce40 : IN STD_LOGIC;
q40 : OUT STD_LOGIC_VECTOR;
addr41 : IN STD_LOGIC_VECTOR;
ce41 : IN STD_LOGIC;
q41 : OUT STD_LOGIC_VECTOR;
addr42 : IN STD_LOGIC_VECTOR;
ce42 : IN STD_LOGIC;
q42 : OUT STD_LOGIC_VECTOR;
addr43 : IN STD_LOGIC_VECTOR;
ce43 : IN STD_LOGIC;
q43 : OUT STD_LOGIC_VECTOR;
addr44 : IN STD_LOGIC_VECTOR;
ce44 : IN STD_LOGIC;
q44 : OUT STD_LOGIC_VECTOR;
addr45 : IN STD_LOGIC_VECTOR;
ce45 : IN STD_LOGIC;
q45 : OUT STD_LOGIC_VECTOR;
addr46 : IN STD_LOGIC_VECTOR;
ce46 : IN STD_LOGIC;
q46 : OUT STD_LOGIC_VECTOR;
addr47 : IN STD_LOGIC_VECTOR;
ce47 : IN STD_LOGIC;
q47 : OUT STD_LOGIC_VECTOR;
addr48 : IN STD_LOGIC_VECTOR;
ce48 : IN STD_LOGIC;
q48 : OUT STD_LOGIC_VECTOR;
addr49 : IN STD_LOGIC_VECTOR;
ce49 : IN STD_LOGIC;
q49 : OUT STD_LOGIC_VECTOR;
addr50 : IN STD_LOGIC_VECTOR;
ce50 : IN STD_LOGIC;
q50 : OUT STD_LOGIC_VECTOR;
addr51 : IN STD_LOGIC_VECTOR;
ce51 : IN STD_LOGIC;
q51 : OUT STD_LOGIC_VECTOR;
addr52 : IN STD_LOGIC_VECTOR;
ce52 : IN STD_LOGIC;
q52 : OUT STD_LOGIC_VECTOR;
addr53 : IN STD_LOGIC_VECTOR;
ce53 : IN STD_LOGIC;
q53 : OUT STD_LOGIC_VECTOR;
addr54 : IN STD_LOGIC_VECTOR;
ce54 : IN STD_LOGIC;
q54 : OUT STD_LOGIC_VECTOR;
addr55 : IN STD_LOGIC_VECTOR;
ce55 : IN STD_LOGIC;
q55 : OUT STD_LOGIC_VECTOR;
addr56 : IN STD_LOGIC_VECTOR;
ce56 : IN STD_LOGIC;
q56 : OUT STD_LOGIC_VECTOR;
addr57 : IN STD_LOGIC_VECTOR;
ce57 : IN STD_LOGIC;
q57 : OUT STD_LOGIC_VECTOR;
addr58 : IN STD_LOGIC_VECTOR;
ce58 : IN STD_LOGIC;
q58 : OUT STD_LOGIC_VECTOR;
addr59 : IN STD_LOGIC_VECTOR;
ce59 : IN STD_LOGIC;
q59 : OUT STD_LOGIC_VECTOR;
addr60 : IN STD_LOGIC_VECTOR;
ce60 : IN STD_LOGIC;
q60 : OUT STD_LOGIC_VECTOR;
addr61 : IN STD_LOGIC_VECTOR;
ce61 : IN STD_LOGIC;
q61 : OUT STD_LOGIC_VECTOR;
addr62 : IN STD_LOGIC_VECTOR;
ce62 : IN STD_LOGIC;
q62 : OUT STD_LOGIC_VECTOR;
addr63 : IN STD_LOGIC_VECTOR;
ce63 : IN STD_LOGIC;
q63 : OUT STD_LOGIC_VECTOR;
addr64 : IN STD_LOGIC_VECTOR;
ce64 : IN STD_LOGIC;
q64 : OUT STD_LOGIC_VECTOR;
addr65 : IN STD_LOGIC_VECTOR;
ce65 : IN STD_LOGIC;
q65 : OUT STD_LOGIC_VECTOR;
addr66 : IN STD_LOGIC_VECTOR;
ce66 : IN STD_LOGIC;
q66 : OUT STD_LOGIC_VECTOR;
addr67 : IN STD_LOGIC_VECTOR;
ce67 : IN STD_LOGIC;
q67 : OUT STD_LOGIC_VECTOR;
addr68 : IN STD_LOGIC_VECTOR;
ce68 : IN STD_LOGIC;
q68 : OUT STD_LOGIC_VECTOR;
addr69 : IN STD_LOGIC_VECTOR;
ce69 : IN STD_LOGIC;
q69 : OUT STD_LOGIC_VECTOR;
addr70 : IN STD_LOGIC_VECTOR;
ce70 : IN STD_LOGIC;
q70 : OUT STD_LOGIC_VECTOR;
addr71 : IN STD_LOGIC_VECTOR;
ce71 : IN STD_LOGIC;
q71 : OUT STD_LOGIC_VECTOR;
addr72 : IN STD_LOGIC_VECTOR;
ce72 : IN STD_LOGIC;
q72 : OUT STD_LOGIC_VECTOR;
addr73 : IN STD_LOGIC_VECTOR;
ce73 : IN STD_LOGIC;
q73 : OUT STD_LOGIC_VECTOR;
addr74 : IN STD_LOGIC_VECTOR;
ce74 : IN STD_LOGIC;
q74 : OUT STD_LOGIC_VECTOR;
addr75 : IN STD_LOGIC_VECTOR;
ce75 : IN STD_LOGIC;
q75 : OUT STD_LOGIC_VECTOR;
addr76 : IN STD_LOGIC_VECTOR;
ce76 : IN STD_LOGIC;
q76 : OUT STD_LOGIC_VECTOR;
addr77 : IN STD_LOGIC_VECTOR;
ce77 : IN STD_LOGIC;
q77 : OUT STD_LOGIC_VECTOR;
addr78 : IN STD_LOGIC_VECTOR;
ce78 : IN STD_LOGIC;
q78 : OUT STD_LOGIC_VECTOR;
addr79 : IN STD_LOGIC_VECTOR;
ce79 : IN STD_LOGIC;
q79 : OUT STD_LOGIC_VECTOR;
addr80 : IN STD_LOGIC_VECTOR;
ce80 : IN STD_LOGIC;
q80 : OUT STD_LOGIC_VECTOR;
addr81 : IN STD_LOGIC_VECTOR;
ce81 : IN STD_LOGIC;
q81 : OUT STD_LOGIC_VECTOR;
addr82 : IN STD_LOGIC_VECTOR;
ce82 : IN STD_LOGIC;
q82 : OUT STD_LOGIC_VECTOR;
addr83 : IN STD_LOGIC_VECTOR;
ce83 : IN STD_LOGIC;
q83 : OUT STD_LOGIC_VECTOR;
addr84 : IN STD_LOGIC_VECTOR;
ce84 : IN STD_LOGIC;
q84 : OUT STD_LOGIC_VECTOR;
addr85 : IN STD_LOGIC_VECTOR;
ce85 : IN STD_LOGIC;
q85 : OUT STD_LOGIC_VECTOR;
addr86 : IN STD_LOGIC_VECTOR;
ce86 : IN STD_LOGIC;
q86 : OUT STD_LOGIC_VECTOR;
addr87 : IN STD_LOGIC_VECTOR;
ce87 : IN STD_LOGIC;
q87 : OUT STD_LOGIC_VECTOR;
addr88 : IN STD_LOGIC_VECTOR;
ce88 : IN STD_LOGIC;
q88 : OUT STD_LOGIC_VECTOR;
addr89 : IN STD_LOGIC_VECTOR;
ce89 : IN STD_LOGIC;
q89 : OUT STD_LOGIC_VECTOR;
addr90 : IN STD_LOGIC_VECTOR;
ce90 : IN STD_LOGIC;
q90 : OUT STD_LOGIC_VECTOR;
addr91 : IN STD_LOGIC_VECTOR;
ce91 : IN STD_LOGIC;
q91 : OUT STD_LOGIC_VECTOR;
addr92 : IN STD_LOGIC_VECTOR;
ce92 : IN STD_LOGIC;
q92 : OUT STD_LOGIC_VECTOR;
addr93 : IN STD_LOGIC_VECTOR;
ce93 : IN STD_LOGIC;
q93 : OUT STD_LOGIC_VECTOR;
addr94 : IN STD_LOGIC_VECTOR;
ce94 : IN STD_LOGIC;
q94 : OUT STD_LOGIC_VECTOR;
addr95 : IN STD_LOGIC_VECTOR;
ce95 : IN STD_LOGIC;
q95 : OUT STD_LOGIC_VECTOR;
addr96 : IN STD_LOGIC_VECTOR;
ce96 : IN STD_LOGIC;
q96 : OUT STD_LOGIC_VECTOR;
addr97 : IN STD_LOGIC_VECTOR;
ce97 : IN STD_LOGIC;
q97 : OUT STD_LOGIC_VECTOR;
addr98 : IN STD_LOGIC_VECTOR;
ce98 : IN STD_LOGIC;
q98 : OUT STD_LOGIC_VECTOR;
addr99 : IN STD_LOGIC_VECTOR;
ce99 : IN STD_LOGIC;
q99 : OUT STD_LOGIC_VECTOR;
addr100 : IN STD_LOGIC_VECTOR;
ce100 : IN STD_LOGIC;
q100 : OUT STD_LOGIC_VECTOR;
addr101 : IN STD_LOGIC_VECTOR;
ce101 : IN STD_LOGIC;
q101 : OUT STD_LOGIC_VECTOR;
addr102 : IN STD_LOGIC_VECTOR;
ce102 : IN STD_LOGIC;
q102 : OUT STD_LOGIC_VECTOR;
addr103 : IN STD_LOGIC_VECTOR;
ce103 : IN STD_LOGIC;
q103 : OUT STD_LOGIC_VECTOR;
addr104 : IN STD_LOGIC_VECTOR;
ce104 : IN STD_LOGIC;
q104 : OUT STD_LOGIC_VECTOR;
addr105 : IN STD_LOGIC_VECTOR;
ce105 : IN STD_LOGIC;
q105 : OUT STD_LOGIC_VECTOR;
addr106 : IN STD_LOGIC_VECTOR;
ce106 : IN STD_LOGIC;
q106 : OUT STD_LOGIC_VECTOR;
addr107 : IN STD_LOGIC_VECTOR;
ce107 : IN STD_LOGIC;
q107 : OUT STD_LOGIC_VECTOR;
addr108 : IN STD_LOGIC_VECTOR;
ce108 : IN STD_LOGIC;
q108 : OUT STD_LOGIC_VECTOR;
addr109 : IN STD_LOGIC_VECTOR;
ce109 : IN STD_LOGIC;
q109 : OUT STD_LOGIC_VECTOR;
addr110 : IN STD_LOGIC_VECTOR;
ce110 : IN STD_LOGIC;
q110 : OUT STD_LOGIC_VECTOR;
addr111 : IN STD_LOGIC_VECTOR;
ce111 : IN STD_LOGIC;
q111 : OUT STD_LOGIC_VECTOR;
addr112 : IN STD_LOGIC_VECTOR;
ce112 : IN STD_LOGIC;
q112 : OUT STD_LOGIC_VECTOR;
addr113 : IN STD_LOGIC_VECTOR;
ce113 : IN STD_LOGIC;
q113 : OUT STD_LOGIC_VECTOR;
addr114 : IN STD_LOGIC_VECTOR;
ce114 : IN STD_LOGIC;
q114 : OUT STD_LOGIC_VECTOR;
addr115 : IN STD_LOGIC_VECTOR;
ce115 : IN STD_LOGIC;
q115 : OUT STD_LOGIC_VECTOR;
addr116 : IN STD_LOGIC_VECTOR;
ce116 : IN STD_LOGIC;
q116 : OUT STD_LOGIC_VECTOR;
addr117 : IN STD_LOGIC_VECTOR;
ce117 : IN STD_LOGIC;
q117 : OUT STD_LOGIC_VECTOR;
addr118 : IN STD_LOGIC_VECTOR;
ce118 : IN STD_LOGIC;
q118 : OUT STD_LOGIC_VECTOR;
addr119 : IN STD_LOGIC_VECTOR;
ce119 : IN STD_LOGIC;
q119 : OUT STD_LOGIC_VECTOR;
addr120 : IN STD_LOGIC_VECTOR;
ce120 : IN STD_LOGIC;
q120 : OUT STD_LOGIC_VECTOR;
addr121 : IN STD_LOGIC_VECTOR;
ce121 : IN STD_LOGIC;
q121 : OUT STD_LOGIC_VECTOR;
addr122 : IN STD_LOGIC_VECTOR;
ce122 : IN STD_LOGIC;
q122 : OUT STD_LOGIC_VECTOR;
addr123 : IN STD_LOGIC_VECTOR;
ce123 : IN STD_LOGIC;
q123 : OUT STD_LOGIC_VECTOR;
addr124 : IN STD_LOGIC_VECTOR;
ce124 : IN STD_LOGIC;
q124 : OUT STD_LOGIC_VECTOR;
addr125 : IN STD_LOGIC_VECTOR;
ce125 : IN STD_LOGIC;
q125 : OUT STD_LOGIC_VECTOR;
addr126 : IN STD_LOGIC_VECTOR;
ce126 : IN STD_LOGIC;
q126 : OUT STD_LOGIC_VECTOR;
addr127 : IN STD_LOGIC_VECTOR;
ce127 : IN STD_LOGIC;
q127 : OUT STD_LOGIC_VECTOR;
addr128 : IN STD_LOGIC_VECTOR;
ce128 : IN STD_LOGIC;
q128 : OUT STD_LOGIC_VECTOR;
addr129 : IN STD_LOGIC_VECTOR;
ce129 : IN STD_LOGIC;
q129 : OUT STD_LOGIC_VECTOR;
addr130 : IN STD_LOGIC_VECTOR;
ce130 : IN STD_LOGIC;
q130 : OUT STD_LOGIC_VECTOR;
addr131 : IN STD_LOGIC_VECTOR;
ce131 : IN STD_LOGIC;
q131 : OUT STD_LOGIC_VECTOR;
addr132 : IN STD_LOGIC_VECTOR;
ce132 : IN STD_LOGIC;
q132 : OUT STD_LOGIC_VECTOR;
addr133 : IN STD_LOGIC_VECTOR;
ce133 : IN STD_LOGIC;
q133 : OUT STD_LOGIC_VECTOR;
addr134 : IN STD_LOGIC_VECTOR;
ce134 : IN STD_LOGIC;
q134 : OUT STD_LOGIC_VECTOR;
addr135 : IN STD_LOGIC_VECTOR;
ce135 : IN STD_LOGIC;
q135 : OUT STD_LOGIC_VECTOR;
addr136 : IN STD_LOGIC_VECTOR;
ce136 : IN STD_LOGIC;
q136 : OUT STD_LOGIC_VECTOR;
addr137 : IN STD_LOGIC_VECTOR;
ce137 : IN STD_LOGIC;
q137 : OUT STD_LOGIC_VECTOR;
addr138 : IN STD_LOGIC_VECTOR;
ce138 : IN STD_LOGIC;
q138 : OUT STD_LOGIC_VECTOR;
addr139 : IN STD_LOGIC_VECTOR;
ce139 : IN STD_LOGIC;
q139 : OUT STD_LOGIC_VECTOR;
addr140 : IN STD_LOGIC_VECTOR;
ce140 : IN STD_LOGIC;
q140 : OUT STD_LOGIC_VECTOR;
addr141 : IN STD_LOGIC_VECTOR;
ce141 : IN STD_LOGIC;
q141 : OUT STD_LOGIC_VECTOR;
addr142 : IN STD_LOGIC_VECTOR;
ce142 : IN STD_LOGIC;
q142 : OUT STD_LOGIC_VECTOR;
addr143 : IN STD_LOGIC_VECTOR;
ce143 : IN STD_LOGIC;
q143 : OUT STD_LOGIC_VECTOR;
addr144 : IN STD_LOGIC_VECTOR;
ce144 : IN STD_LOGIC;
q144 : OUT STD_LOGIC_VECTOR;
addr145 : IN STD_LOGIC_VECTOR;
ce145 : IN STD_LOGIC;
q145 : OUT STD_LOGIC_VECTOR;
addr146 : IN STD_LOGIC_VECTOR;
ce146 : IN STD_LOGIC;
q146 : OUT STD_LOGIC_VECTOR;
addr147 : IN STD_LOGIC_VECTOR;
ce147 : IN STD_LOGIC;
q147 : OUT STD_LOGIC_VECTOR;
addr148 : IN STD_LOGIC_VECTOR;
ce148 : IN STD_LOGIC;
q148 : OUT STD_LOGIC_VECTOR;
addr149 : IN STD_LOGIC_VECTOR;
ce149 : IN STD_LOGIC;
q149 : OUT STD_LOGIC_VECTOR;
addr150 : IN STD_LOGIC_VECTOR;
ce150 : IN STD_LOGIC;
q150 : OUT STD_LOGIC_VECTOR;
addr151 : IN STD_LOGIC_VECTOR;
ce151 : IN STD_LOGIC;
q151 : OUT STD_LOGIC_VECTOR;
addr152 : IN STD_LOGIC_VECTOR;
ce152 : IN STD_LOGIC;
q152 : OUT STD_LOGIC_VECTOR;
addr153 : IN STD_LOGIC_VECTOR;
ce153 : IN STD_LOGIC;
q153 : OUT STD_LOGIC_VECTOR;
addr154 : IN STD_LOGIC_VECTOR;
ce154 : IN STD_LOGIC;
q154 : OUT STD_LOGIC_VECTOR;
addr155 : IN STD_LOGIC_VECTOR;
ce155 : IN STD_LOGIC;
q155 : OUT STD_LOGIC_VECTOR;
addr156 : IN STD_LOGIC_VECTOR;
ce156 : IN STD_LOGIC;
q156 : OUT STD_LOGIC_VECTOR;
addr157 : IN STD_LOGIC_VECTOR;
ce157 : IN STD_LOGIC;
q157 : OUT STD_LOGIC_VECTOR;
addr158 : IN STD_LOGIC_VECTOR;
ce158 : IN STD_LOGIC;
q158 : OUT STD_LOGIC_VECTOR;
addr159 : IN STD_LOGIC_VECTOR;
ce159 : IN STD_LOGIC;
q159 : OUT STD_LOGIC_VECTOR;
addr160 : IN STD_LOGIC_VECTOR;
ce160 : IN STD_LOGIC;
q160 : OUT STD_LOGIC_VECTOR;
addr161 : IN STD_LOGIC_VECTOR;
ce161 : IN STD_LOGIC;
q161 : OUT STD_LOGIC_VECTOR;
addr162 : IN STD_LOGIC_VECTOR;
ce162 : IN STD_LOGIC;
q162 : OUT STD_LOGIC_VECTOR;
addr163 : IN STD_LOGIC_VECTOR;
ce163 : IN STD_LOGIC;
q163 : OUT STD_LOGIC_VECTOR;
addr164 : IN STD_LOGIC_VECTOR;
ce164 : IN STD_LOGIC;
q164 : OUT STD_LOGIC_VECTOR;
addr165 : IN STD_LOGIC_VECTOR;
ce165 : IN STD_LOGIC;
q165 : OUT STD_LOGIC_VECTOR;
addr166 : IN STD_LOGIC_VECTOR;
ce166 : IN STD_LOGIC;
q166 : OUT STD_LOGIC_VECTOR;
addr167 : IN STD_LOGIC_VECTOR;
ce167 : IN STD_LOGIC;
q167 : OUT STD_LOGIC_VECTOR;
addr168 : IN STD_LOGIC_VECTOR;
ce168 : IN STD_LOGIC;
q168 : OUT STD_LOGIC_VECTOR;
addr169 : IN STD_LOGIC_VECTOR;
ce169 : IN STD_LOGIC;
q169 : OUT STD_LOGIC_VECTOR;
addr170 : IN STD_LOGIC_VECTOR;
ce170 : IN STD_LOGIC;
q170 : OUT STD_LOGIC_VECTOR;
addr171 : IN STD_LOGIC_VECTOR;
ce171 : IN STD_LOGIC;
q171 : OUT STD_LOGIC_VECTOR;
addr172 : IN STD_LOGIC_VECTOR;
ce172 : IN STD_LOGIC;
q172 : OUT STD_LOGIC_VECTOR;
addr173 : IN STD_LOGIC_VECTOR;
ce173 : IN STD_LOGIC;
q173 : OUT STD_LOGIC_VECTOR;
addr174 : IN STD_LOGIC_VECTOR;
ce174 : IN STD_LOGIC;
q174 : OUT STD_LOGIC_VECTOR;
addr175 : IN STD_LOGIC_VECTOR;
ce175 : IN STD_LOGIC;
q175 : OUT STD_LOGIC_VECTOR;
addr176 : IN STD_LOGIC_VECTOR;
ce176 : IN STD_LOGIC;
q176 : OUT STD_LOGIC_VECTOR;
addr177 : IN STD_LOGIC_VECTOR;
ce177 : IN STD_LOGIC;
q177 : OUT STD_LOGIC_VECTOR;
addr178 : IN STD_LOGIC_VECTOR;
ce178 : IN STD_LOGIC;
q178 : OUT STD_LOGIC_VECTOR;
addr179 : IN STD_LOGIC_VECTOR;
ce179 : IN STD_LOGIC;
q179 : OUT STD_LOGIC_VECTOR;
addr180 : IN STD_LOGIC_VECTOR;
ce180 : IN STD_LOGIC;
q180 : OUT STD_LOGIC_VECTOR;
addr181 : IN STD_LOGIC_VECTOR;
ce181 : IN STD_LOGIC;
q181 : OUT STD_LOGIC_VECTOR;
addr182 : IN STD_LOGIC_VECTOR;
ce182 : IN STD_LOGIC;
q182 : OUT STD_LOGIC_VECTOR;
addr183 : IN STD_LOGIC_VECTOR;
ce183 : IN STD_LOGIC;
q183 : OUT STD_LOGIC_VECTOR;
addr184 : IN STD_LOGIC_VECTOR;
ce184 : IN STD_LOGIC;
q184 : OUT STD_LOGIC_VECTOR;
addr185 : IN STD_LOGIC_VECTOR;
ce185 : IN STD_LOGIC;
q185 : OUT STD_LOGIC_VECTOR;
addr186 : IN STD_LOGIC_VECTOR;
ce186 : IN STD_LOGIC;
q186 : OUT STD_LOGIC_VECTOR;
addr187 : IN STD_LOGIC_VECTOR;
ce187 : IN STD_LOGIC;
q187 : OUT STD_LOGIC_VECTOR;
addr188 : IN STD_LOGIC_VECTOR;
ce188 : IN STD_LOGIC;
q188 : OUT STD_LOGIC_VECTOR;
addr189 : IN STD_LOGIC_VECTOR;
ce189 : IN STD_LOGIC;
q189 : OUT STD_LOGIC_VECTOR;
addr190 : IN STD_LOGIC_VECTOR;
ce190 : IN STD_LOGIC;
q190 : OUT STD_LOGIC_VECTOR;
addr191 : IN STD_LOGIC_VECTOR;
ce191 : IN STD_LOGIC;
q191 : OUT STD_LOGIC_VECTOR;
addr192 : IN STD_LOGIC_VECTOR;
ce192 : IN STD_LOGIC;
q192 : OUT STD_LOGIC_VECTOR;
addr193 : IN STD_LOGIC_VECTOR;
ce193 : IN STD_LOGIC;
q193 : OUT STD_LOGIC_VECTOR;
addr194 : IN STD_LOGIC_VECTOR;
ce194 : IN STD_LOGIC;
q194 : OUT STD_LOGIC_VECTOR;
addr195 : IN STD_LOGIC_VECTOR;
ce195 : IN STD_LOGIC;
q195 : OUT STD_LOGIC_VECTOR;
addr196 : IN STD_LOGIC_VECTOR;
ce196 : IN STD_LOGIC;
q196 : OUT STD_LOGIC_VECTOR;
addr197 : IN STD_LOGIC_VECTOR;
ce197 : IN STD_LOGIC;
q197 : OUT STD_LOGIC_VECTOR;
addr198 : IN STD_LOGIC_VECTOR;
ce198 : IN STD_LOGIC;
q198 : OUT STD_LOGIC_VECTOR;
addr199 : IN STD_LOGIC_VECTOR;
ce199 : IN STD_LOGIC;
q199 : OUT STD_LOGIC_VECTOR);
end component;
begin
aestest_sboxes_rom_U : component aestest_sboxes_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2,
addr3 => address3,
ce3 => ce3,
q3 => q3,
addr4 => address4,
ce4 => ce4,
q4 => q4,
addr5 => address5,
ce5 => ce5,
q5 => q5,
addr6 => address6,
ce6 => ce6,
q6 => q6,
addr7 => address7,
ce7 => ce7,
q7 => q7,
addr8 => address8,
ce8 => ce8,
q8 => q8,
addr9 => address9,
ce9 => ce9,
q9 => q9,
addr10 => address10,
ce10 => ce10,
q10 => q10,
addr11 => address11,
ce11 => ce11,
q11 => q11,
addr12 => address12,
ce12 => ce12,
q12 => q12,
addr13 => address13,
ce13 => ce13,
q13 => q13,
addr14 => address14,
ce14 => ce14,
q14 => q14,
addr15 => address15,
ce15 => ce15,
q15 => q15,
addr16 => address16,
ce16 => ce16,
q16 => q16,
addr17 => address17,
ce17 => ce17,
q17 => q17,
addr18 => address18,
ce18 => ce18,
q18 => q18,
addr19 => address19,
ce19 => ce19,
q19 => q19,
addr20 => address20,
ce20 => ce20,
q20 => q20,
addr21 => address21,
ce21 => ce21,
q21 => q21,
addr22 => address22,
ce22 => ce22,
q22 => q22,
addr23 => address23,
ce23 => ce23,
q23 => q23,
addr24 => address24,
ce24 => ce24,
q24 => q24,
addr25 => address25,
ce25 => ce25,
q25 => q25,
addr26 => address26,
ce26 => ce26,
q26 => q26,
addr27 => address27,
ce27 => ce27,
q27 => q27,
addr28 => address28,
ce28 => ce28,
q28 => q28,
addr29 => address29,
ce29 => ce29,
q29 => q29,
addr30 => address30,
ce30 => ce30,
q30 => q30,
addr31 => address31,
ce31 => ce31,
q31 => q31,
addr32 => address32,
ce32 => ce32,
q32 => q32,
addr33 => address33,
ce33 => ce33,
q33 => q33,
addr34 => address34,
ce34 => ce34,
q34 => q34,
addr35 => address35,
ce35 => ce35,
q35 => q35,
addr36 => address36,
ce36 => ce36,
q36 => q36,
addr37 => address37,
ce37 => ce37,
q37 => q37,
addr38 => address38,
ce38 => ce38,
q38 => q38,
addr39 => address39,
ce39 => ce39,
q39 => q39,
addr40 => address40,
ce40 => ce40,
q40 => q40,
addr41 => address41,
ce41 => ce41,
q41 => q41,
addr42 => address42,
ce42 => ce42,
q42 => q42,
addr43 => address43,
ce43 => ce43,
q43 => q43,
addr44 => address44,
ce44 => ce44,
q44 => q44,
addr45 => address45,
ce45 => ce45,
q45 => q45,
addr46 => address46,
ce46 => ce46,
q46 => q46,
addr47 => address47,
ce47 => ce47,
q47 => q47,
addr48 => address48,
ce48 => ce48,
q48 => q48,
addr49 => address49,
ce49 => ce49,
q49 => q49,
addr50 => address50,
ce50 => ce50,
q50 => q50,
addr51 => address51,
ce51 => ce51,
q51 => q51,
addr52 => address52,
ce52 => ce52,
q52 => q52,
addr53 => address53,
ce53 => ce53,
q53 => q53,
addr54 => address54,
ce54 => ce54,
q54 => q54,
addr55 => address55,
ce55 => ce55,
q55 => q55,
addr56 => address56,
ce56 => ce56,
q56 => q56,
addr57 => address57,
ce57 => ce57,
q57 => q57,
addr58 => address58,
ce58 => ce58,
q58 => q58,
addr59 => address59,
ce59 => ce59,
q59 => q59,
addr60 => address60,
ce60 => ce60,
q60 => q60,
addr61 => address61,
ce61 => ce61,
q61 => q61,
addr62 => address62,
ce62 => ce62,
q62 => q62,
addr63 => address63,
ce63 => ce63,
q63 => q63,
addr64 => address64,
ce64 => ce64,
q64 => q64,
addr65 => address65,
ce65 => ce65,
q65 => q65,
addr66 => address66,
ce66 => ce66,
q66 => q66,
addr67 => address67,
ce67 => ce67,
q67 => q67,
addr68 => address68,
ce68 => ce68,
q68 => q68,
addr69 => address69,
ce69 => ce69,
q69 => q69,
addr70 => address70,
ce70 => ce70,
q70 => q70,
addr71 => address71,
ce71 => ce71,
q71 => q71,
addr72 => address72,
ce72 => ce72,
q72 => q72,
addr73 => address73,
ce73 => ce73,
q73 => q73,
addr74 => address74,
ce74 => ce74,
q74 => q74,
addr75 => address75,
ce75 => ce75,
q75 => q75,
addr76 => address76,
ce76 => ce76,
q76 => q76,
addr77 => address77,
ce77 => ce77,
q77 => q77,
addr78 => address78,
ce78 => ce78,
q78 => q78,
addr79 => address79,
ce79 => ce79,
q79 => q79,
addr80 => address80,
ce80 => ce80,
q80 => q80,
addr81 => address81,
ce81 => ce81,
q81 => q81,
addr82 => address82,
ce82 => ce82,
q82 => q82,
addr83 => address83,
ce83 => ce83,
q83 => q83,
addr84 => address84,
ce84 => ce84,
q84 => q84,
addr85 => address85,
ce85 => ce85,
q85 => q85,
addr86 => address86,
ce86 => ce86,
q86 => q86,
addr87 => address87,
ce87 => ce87,
q87 => q87,
addr88 => address88,
ce88 => ce88,
q88 => q88,
addr89 => address89,
ce89 => ce89,
q89 => q89,
addr90 => address90,
ce90 => ce90,
q90 => q90,
addr91 => address91,
ce91 => ce91,
q91 => q91,
addr92 => address92,
ce92 => ce92,
q92 => q92,
addr93 => address93,
ce93 => ce93,
q93 => q93,
addr94 => address94,
ce94 => ce94,
q94 => q94,
addr95 => address95,
ce95 => ce95,
q95 => q95,
addr96 => address96,
ce96 => ce96,
q96 => q96,
addr97 => address97,
ce97 => ce97,
q97 => q97,
addr98 => address98,
ce98 => ce98,
q98 => q98,
addr99 => address99,
ce99 => ce99,
q99 => q99,
addr100 => address100,
ce100 => ce100,
q100 => q100,
addr101 => address101,
ce101 => ce101,
q101 => q101,
addr102 => address102,
ce102 => ce102,
q102 => q102,
addr103 => address103,
ce103 => ce103,
q103 => q103,
addr104 => address104,
ce104 => ce104,
q104 => q104,
addr105 => address105,
ce105 => ce105,
q105 => q105,
addr106 => address106,
ce106 => ce106,
q106 => q106,
addr107 => address107,
ce107 => ce107,
q107 => q107,
addr108 => address108,
ce108 => ce108,
q108 => q108,
addr109 => address109,
ce109 => ce109,
q109 => q109,
addr110 => address110,
ce110 => ce110,
q110 => q110,
addr111 => address111,
ce111 => ce111,
q111 => q111,
addr112 => address112,
ce112 => ce112,
q112 => q112,
addr113 => address113,
ce113 => ce113,
q113 => q113,
addr114 => address114,
ce114 => ce114,
q114 => q114,
addr115 => address115,
ce115 => ce115,
q115 => q115,
addr116 => address116,
ce116 => ce116,
q116 => q116,
addr117 => address117,
ce117 => ce117,
q117 => q117,
addr118 => address118,
ce118 => ce118,
q118 => q118,
addr119 => address119,
ce119 => ce119,
q119 => q119,
addr120 => address120,
ce120 => ce120,
q120 => q120,
addr121 => address121,
ce121 => ce121,
q121 => q121,
addr122 => address122,
ce122 => ce122,
q122 => q122,
addr123 => address123,
ce123 => ce123,
q123 => q123,
addr124 => address124,
ce124 => ce124,
q124 => q124,
addr125 => address125,
ce125 => ce125,
q125 => q125,
addr126 => address126,
ce126 => ce126,
q126 => q126,
addr127 => address127,
ce127 => ce127,
q127 => q127,
addr128 => address128,
ce128 => ce128,
q128 => q128,
addr129 => address129,
ce129 => ce129,
q129 => q129,
addr130 => address130,
ce130 => ce130,
q130 => q130,
addr131 => address131,
ce131 => ce131,
q131 => q131,
addr132 => address132,
ce132 => ce132,
q132 => q132,
addr133 => address133,
ce133 => ce133,
q133 => q133,
addr134 => address134,
ce134 => ce134,
q134 => q134,
addr135 => address135,
ce135 => ce135,
q135 => q135,
addr136 => address136,
ce136 => ce136,
q136 => q136,
addr137 => address137,
ce137 => ce137,
q137 => q137,
addr138 => address138,
ce138 => ce138,
q138 => q138,
addr139 => address139,
ce139 => ce139,
q139 => q139,
addr140 => address140,
ce140 => ce140,
q140 => q140,
addr141 => address141,
ce141 => ce141,
q141 => q141,
addr142 => address142,
ce142 => ce142,
q142 => q142,
addr143 => address143,
ce143 => ce143,
q143 => q143,
addr144 => address144,
ce144 => ce144,
q144 => q144,
addr145 => address145,
ce145 => ce145,
q145 => q145,
addr146 => address146,
ce146 => ce146,
q146 => q146,
addr147 => address147,
ce147 => ce147,
q147 => q147,
addr148 => address148,
ce148 => ce148,
q148 => q148,
addr149 => address149,
ce149 => ce149,
q149 => q149,
addr150 => address150,
ce150 => ce150,
q150 => q150,
addr151 => address151,
ce151 => ce151,
q151 => q151,
addr152 => address152,
ce152 => ce152,
q152 => q152,
addr153 => address153,
ce153 => ce153,
q153 => q153,
addr154 => address154,
ce154 => ce154,
q154 => q154,
addr155 => address155,
ce155 => ce155,
q155 => q155,
addr156 => address156,
ce156 => ce156,
q156 => q156,
addr157 => address157,
ce157 => ce157,
q157 => q157,
addr158 => address158,
ce158 => ce158,
q158 => q158,
addr159 => address159,
ce159 => ce159,
q159 => q159,
addr160 => address160,
ce160 => ce160,
q160 => q160,
addr161 => address161,
ce161 => ce161,
q161 => q161,
addr162 => address162,
ce162 => ce162,
q162 => q162,
addr163 => address163,
ce163 => ce163,
q163 => q163,
addr164 => address164,
ce164 => ce164,
q164 => q164,
addr165 => address165,
ce165 => ce165,
q165 => q165,
addr166 => address166,
ce166 => ce166,
q166 => q166,
addr167 => address167,
ce167 => ce167,
q167 => q167,
addr168 => address168,
ce168 => ce168,
q168 => q168,
addr169 => address169,
ce169 => ce169,
q169 => q169,
addr170 => address170,
ce170 => ce170,
q170 => q170,
addr171 => address171,
ce171 => ce171,
q171 => q171,
addr172 => address172,
ce172 => ce172,
q172 => q172,
addr173 => address173,
ce173 => ce173,
q173 => q173,
addr174 => address174,
ce174 => ce174,
q174 => q174,
addr175 => address175,
ce175 => ce175,
q175 => q175,
addr176 => address176,
ce176 => ce176,
q176 => q176,
addr177 => address177,
ce177 => ce177,
q177 => q177,
addr178 => address178,
ce178 => ce178,
q178 => q178,
addr179 => address179,
ce179 => ce179,
q179 => q179,
addr180 => address180,
ce180 => ce180,
q180 => q180,
addr181 => address181,
ce181 => ce181,
q181 => q181,
addr182 => address182,
ce182 => ce182,
q182 => q182,
addr183 => address183,
ce183 => ce183,
q183 => q183,
addr184 => address184,
ce184 => ce184,
q184 => q184,
addr185 => address185,
ce185 => ce185,
q185 => q185,
addr186 => address186,
ce186 => ce186,
q186 => q186,
addr187 => address187,
ce187 => ce187,
q187 => q187,
addr188 => address188,
ce188 => ce188,
q188 => q188,
addr189 => address189,
ce189 => ce189,
q189 => q189,
addr190 => address190,
ce190 => ce190,
q190 => q190,
addr191 => address191,
ce191 => ce191,
q191 => q191,
addr192 => address192,
ce192 => ce192,
q192 => q192,
addr193 => address193,
ce193 => ce193,
q193 => q193,
addr194 => address194,
ce194 => ce194,
q194 => q194,
addr195 => address195,
ce195 => ce195,
q195 => q195,
addr196 => address196,
ce196 => ce196,
q196 => q196,
addr197 => address197,
ce197 => ce197,
q197 => q197,
addr198 => address198,
ce198 => ce198,
q198 => q198,
addr199 => address199,
ce199 => ce199,
q199 => q199);
end architecture;
|
gpl-3.0
|
mcoughli/root_of_trust
|
experiments/secure_filesystem/secure_filesystem_hls/solution1/syn/vhdl/aestest.vhd
|
1
|
460185
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity aestest is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
inptext_V_read : IN STD_LOGIC_VECTOR (127 downto 0);
key_V_read : IN STD_LOGIC_VECTOR (127 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (127 downto 0) );
end;
architecture behav of aestest is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_78 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_70 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110000";
constant ap_const_lv32_77 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110111";
constant ap_const_lv32_68 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101000";
constant ap_const_lv32_6F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001101111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_67 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100111";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_48 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001000";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_47 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv8_1B : STD_LOGIC_VECTOR (7 downto 0) := "00011011";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_8 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_const_lv8_10 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_const_lv8_20 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_const_lv8_40 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_36 : STD_LOGIC_VECTOR (7 downto 0) := "00110110";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state2_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal sboxes_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce0 : STD_LOGIC;
signal sboxes_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce1 : STD_LOGIC;
signal sboxes_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce2 : STD_LOGIC;
signal sboxes_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address3 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce3 : STD_LOGIC;
signal sboxes_q3 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address4 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce4 : STD_LOGIC;
signal sboxes_q4 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address5 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce5 : STD_LOGIC;
signal sboxes_q5 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address6 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce6 : STD_LOGIC;
signal sboxes_q6 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address7 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce7 : STD_LOGIC;
signal sboxes_q7 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address8 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce8 : STD_LOGIC;
signal sboxes_q8 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address9 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce9 : STD_LOGIC;
signal sboxes_q9 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address10 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce10 : STD_LOGIC;
signal sboxes_q10 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address11 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce11 : STD_LOGIC;
signal sboxes_q11 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address12 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce12 : STD_LOGIC;
signal sboxes_q12 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address13 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce13 : STD_LOGIC;
signal sboxes_q13 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address14 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce14 : STD_LOGIC;
signal sboxes_q14 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address15 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce15 : STD_LOGIC;
signal sboxes_q15 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address16 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce16 : STD_LOGIC;
signal sboxes_q16 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address17 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce17 : STD_LOGIC;
signal sboxes_q17 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address18 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce18 : STD_LOGIC;
signal sboxes_q18 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address19 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce19 : STD_LOGIC;
signal sboxes_q19 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address20 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce20 : STD_LOGIC;
signal sboxes_q20 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address21 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce21 : STD_LOGIC;
signal sboxes_q21 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address22 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce22 : STD_LOGIC;
signal sboxes_q22 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address23 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce23 : STD_LOGIC;
signal sboxes_q23 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address24 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce24 : STD_LOGIC;
signal sboxes_q24 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address25 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce25 : STD_LOGIC;
signal sboxes_q25 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address26 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce26 : STD_LOGIC;
signal sboxes_q26 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address27 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce27 : STD_LOGIC;
signal sboxes_q27 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address28 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce28 : STD_LOGIC;
signal sboxes_q28 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address29 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce29 : STD_LOGIC;
signal sboxes_q29 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address30 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce30 : STD_LOGIC;
signal sboxes_q30 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address31 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce31 : STD_LOGIC;
signal sboxes_q31 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address32 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce32 : STD_LOGIC;
signal sboxes_q32 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address33 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce33 : STD_LOGIC;
signal sboxes_q33 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address34 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce34 : STD_LOGIC;
signal sboxes_q34 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address35 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce35 : STD_LOGIC;
signal sboxes_q35 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address36 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce36 : STD_LOGIC;
signal sboxes_q36 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address37 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce37 : STD_LOGIC;
signal sboxes_q37 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address38 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce38 : STD_LOGIC;
signal sboxes_q38 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address39 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce39 : STD_LOGIC;
signal sboxes_q39 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address40 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce40 : STD_LOGIC;
signal sboxes_q40 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address41 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce41 : STD_LOGIC;
signal sboxes_q41 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address42 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce42 : STD_LOGIC;
signal sboxes_q42 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address43 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce43 : STD_LOGIC;
signal sboxes_q43 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address44 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce44 : STD_LOGIC;
signal sboxes_q44 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address45 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce45 : STD_LOGIC;
signal sboxes_q45 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address46 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce46 : STD_LOGIC;
signal sboxes_q46 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address47 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce47 : STD_LOGIC;
signal sboxes_q47 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address48 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce48 : STD_LOGIC;
signal sboxes_q48 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address49 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce49 : STD_LOGIC;
signal sboxes_q49 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address50 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce50 : STD_LOGIC;
signal sboxes_q50 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address51 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce51 : STD_LOGIC;
signal sboxes_q51 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address52 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce52 : STD_LOGIC;
signal sboxes_q52 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address53 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce53 : STD_LOGIC;
signal sboxes_q53 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address54 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce54 : STD_LOGIC;
signal sboxes_q54 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address55 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce55 : STD_LOGIC;
signal sboxes_q55 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address56 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce56 : STD_LOGIC;
signal sboxes_q56 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address57 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce57 : STD_LOGIC;
signal sboxes_q57 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address58 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce58 : STD_LOGIC;
signal sboxes_q58 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address59 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce59 : STD_LOGIC;
signal sboxes_q59 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address60 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce60 : STD_LOGIC;
signal sboxes_q60 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address61 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce61 : STD_LOGIC;
signal sboxes_q61 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address62 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce62 : STD_LOGIC;
signal sboxes_q62 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address63 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce63 : STD_LOGIC;
signal sboxes_q63 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address64 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce64 : STD_LOGIC;
signal sboxes_q64 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address65 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce65 : STD_LOGIC;
signal sboxes_q65 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address66 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce66 : STD_LOGIC;
signal sboxes_q66 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address67 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce67 : STD_LOGIC;
signal sboxes_q67 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address68 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce68 : STD_LOGIC;
signal sboxes_q68 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address69 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce69 : STD_LOGIC;
signal sboxes_q69 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address70 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce70 : STD_LOGIC;
signal sboxes_q70 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address71 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce71 : STD_LOGIC;
signal sboxes_q71 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address72 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce72 : STD_LOGIC;
signal sboxes_q72 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address73 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce73 : STD_LOGIC;
signal sboxes_q73 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address74 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce74 : STD_LOGIC;
signal sboxes_q74 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address75 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce75 : STD_LOGIC;
signal sboxes_q75 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address76 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce76 : STD_LOGIC;
signal sboxes_q76 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address77 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce77 : STD_LOGIC;
signal sboxes_q77 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address78 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce78 : STD_LOGIC;
signal sboxes_q78 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address79 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce79 : STD_LOGIC;
signal sboxes_q79 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address80 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce80 : STD_LOGIC;
signal sboxes_q80 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address81 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce81 : STD_LOGIC;
signal sboxes_q81 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address82 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce82 : STD_LOGIC;
signal sboxes_q82 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address83 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce83 : STD_LOGIC;
signal sboxes_q83 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address84 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce84 : STD_LOGIC;
signal sboxes_q84 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address85 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce85 : STD_LOGIC;
signal sboxes_q85 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address86 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce86 : STD_LOGIC;
signal sboxes_q86 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address87 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce87 : STD_LOGIC;
signal sboxes_q87 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address88 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce88 : STD_LOGIC;
signal sboxes_q88 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address89 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce89 : STD_LOGIC;
signal sboxes_q89 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address90 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce90 : STD_LOGIC;
signal sboxes_q90 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address91 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce91 : STD_LOGIC;
signal sboxes_q91 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address92 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce92 : STD_LOGIC;
signal sboxes_q92 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address93 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce93 : STD_LOGIC;
signal sboxes_q93 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address94 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce94 : STD_LOGIC;
signal sboxes_q94 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address95 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce95 : STD_LOGIC;
signal sboxes_q95 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address96 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce96 : STD_LOGIC;
signal sboxes_q96 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address97 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce97 : STD_LOGIC;
signal sboxes_q97 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address98 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce98 : STD_LOGIC;
signal sboxes_q98 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address99 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce99 : STD_LOGIC;
signal sboxes_q99 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address100 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce100 : STD_LOGIC;
signal sboxes_q100 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address101 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce101 : STD_LOGIC;
signal sboxes_q101 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address102 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce102 : STD_LOGIC;
signal sboxes_q102 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address103 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce103 : STD_LOGIC;
signal sboxes_q103 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address104 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce104 : STD_LOGIC;
signal sboxes_q104 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address105 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce105 : STD_LOGIC;
signal sboxes_q105 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address106 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce106 : STD_LOGIC;
signal sboxes_q106 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address107 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce107 : STD_LOGIC;
signal sboxes_q107 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address108 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce108 : STD_LOGIC;
signal sboxes_q108 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address109 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce109 : STD_LOGIC;
signal sboxes_q109 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address110 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce110 : STD_LOGIC;
signal sboxes_q110 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address111 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce111 : STD_LOGIC;
signal sboxes_q111 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address112 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce112 : STD_LOGIC;
signal sboxes_q112 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address113 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce113 : STD_LOGIC;
signal sboxes_q113 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address114 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce114 : STD_LOGIC;
signal sboxes_q114 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address115 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce115 : STD_LOGIC;
signal sboxes_q115 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address116 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce116 : STD_LOGIC;
signal sboxes_q116 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address117 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce117 : STD_LOGIC;
signal sboxes_q117 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address118 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce118 : STD_LOGIC;
signal sboxes_q118 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address119 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce119 : STD_LOGIC;
signal sboxes_q119 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address120 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce120 : STD_LOGIC;
signal sboxes_q120 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address121 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce121 : STD_LOGIC;
signal sboxes_q121 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address122 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce122 : STD_LOGIC;
signal sboxes_q122 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address123 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce123 : STD_LOGIC;
signal sboxes_q123 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address124 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce124 : STD_LOGIC;
signal sboxes_q124 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address125 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce125 : STD_LOGIC;
signal sboxes_q125 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address126 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce126 : STD_LOGIC;
signal sboxes_q126 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address127 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce127 : STD_LOGIC;
signal sboxes_q127 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address128 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce128 : STD_LOGIC;
signal sboxes_q128 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address129 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce129 : STD_LOGIC;
signal sboxes_q129 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address130 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce130 : STD_LOGIC;
signal sboxes_q130 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address131 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce131 : STD_LOGIC;
signal sboxes_q131 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address132 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce132 : STD_LOGIC;
signal sboxes_q132 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address133 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce133 : STD_LOGIC;
signal sboxes_q133 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address134 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce134 : STD_LOGIC;
signal sboxes_q134 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address135 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce135 : STD_LOGIC;
signal sboxes_q135 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address136 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce136 : STD_LOGIC;
signal sboxes_q136 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address137 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce137 : STD_LOGIC;
signal sboxes_q137 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address138 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce138 : STD_LOGIC;
signal sboxes_q138 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address139 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce139 : STD_LOGIC;
signal sboxes_q139 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address140 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce140 : STD_LOGIC;
signal sboxes_q140 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address141 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce141 : STD_LOGIC;
signal sboxes_q141 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address142 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce142 : STD_LOGIC;
signal sboxes_q142 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address143 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce143 : STD_LOGIC;
signal sboxes_q143 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address144 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce144 : STD_LOGIC;
signal sboxes_q144 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address145 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce145 : STD_LOGIC;
signal sboxes_q145 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address146 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce146 : STD_LOGIC;
signal sboxes_q146 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address147 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce147 : STD_LOGIC;
signal sboxes_q147 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address148 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce148 : STD_LOGIC;
signal sboxes_q148 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address149 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce149 : STD_LOGIC;
signal sboxes_q149 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address150 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce150 : STD_LOGIC;
signal sboxes_q150 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address151 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce151 : STD_LOGIC;
signal sboxes_q151 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address152 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce152 : STD_LOGIC;
signal sboxes_q152 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address153 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce153 : STD_LOGIC;
signal sboxes_q153 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address154 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce154 : STD_LOGIC;
signal sboxes_q154 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address155 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce155 : STD_LOGIC;
signal sboxes_q155 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address156 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce156 : STD_LOGIC;
signal sboxes_q156 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address157 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce157 : STD_LOGIC;
signal sboxes_q157 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address158 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce158 : STD_LOGIC;
signal sboxes_q158 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address159 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce159 : STD_LOGIC;
signal sboxes_q159 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address160 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce160 : STD_LOGIC;
signal sboxes_q160 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address161 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce161 : STD_LOGIC;
signal sboxes_q161 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address162 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce162 : STD_LOGIC;
signal sboxes_q162 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address163 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce163 : STD_LOGIC;
signal sboxes_q163 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address164 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce164 : STD_LOGIC;
signal sboxes_q164 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address165 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce165 : STD_LOGIC;
signal sboxes_q165 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address166 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce166 : STD_LOGIC;
signal sboxes_q166 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address167 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce167 : STD_LOGIC;
signal sboxes_q167 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address168 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce168 : STD_LOGIC;
signal sboxes_q168 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address169 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce169 : STD_LOGIC;
signal sboxes_q169 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address170 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce170 : STD_LOGIC;
signal sboxes_q170 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address171 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce171 : STD_LOGIC;
signal sboxes_q171 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address172 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce172 : STD_LOGIC;
signal sboxes_q172 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address173 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce173 : STD_LOGIC;
signal sboxes_q173 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address174 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce174 : STD_LOGIC;
signal sboxes_q174 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address175 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce175 : STD_LOGIC;
signal sboxes_q175 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address176 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce176 : STD_LOGIC;
signal sboxes_q176 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address177 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce177 : STD_LOGIC;
signal sboxes_q177 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address178 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce178 : STD_LOGIC;
signal sboxes_q178 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address179 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce179 : STD_LOGIC;
signal sboxes_q179 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address180 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce180 : STD_LOGIC;
signal sboxes_q180 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address181 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce181 : STD_LOGIC;
signal sboxes_q181 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address182 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce182 : STD_LOGIC;
signal sboxes_q182 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address183 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce183 : STD_LOGIC;
signal sboxes_q183 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address184 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce184 : STD_LOGIC;
signal sboxes_q184 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address185 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce185 : STD_LOGIC;
signal sboxes_q185 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address186 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce186 : STD_LOGIC;
signal sboxes_q186 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address187 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce187 : STD_LOGIC;
signal sboxes_q187 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address188 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce188 : STD_LOGIC;
signal sboxes_q188 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address189 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce189 : STD_LOGIC;
signal sboxes_q189 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address190 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce190 : STD_LOGIC;
signal sboxes_q190 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address191 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce191 : STD_LOGIC;
signal sboxes_q191 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address192 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce192 : STD_LOGIC;
signal sboxes_q192 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address193 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce193 : STD_LOGIC;
signal sboxes_q193 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address194 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce194 : STD_LOGIC;
signal sboxes_q194 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address195 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce195 : STD_LOGIC;
signal sboxes_q195 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address196 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce196 : STD_LOGIC;
signal sboxes_q196 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address197 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce197 : STD_LOGIC;
signal sboxes_q197 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address198 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce198 : STD_LOGIC;
signal sboxes_q198 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_address199 : STD_LOGIC_VECTOR (7 downto 0);
signal sboxes_ce199 : STD_LOGIC;
signal sboxes_q199 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_fu_2331_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_reg_12421 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_1_fu_2351_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_1_reg_12426 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_2_fu_2371_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_2_reg_12431 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_3_fu_2391_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_3_reg_12436 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_4_fu_2411_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_4_reg_12441 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_4_reg_12441 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_5_fu_2431_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_5_reg_12447 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_5_reg_12447 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_6_fu_2451_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_6_reg_12453 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_6_reg_12453 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_7_fu_2471_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_7_reg_12459 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_7_reg_12459 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_8_fu_2491_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_8_reg_12465 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_9_fu_2511_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_9_reg_12470 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_s_fu_2531_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_s_reg_12475 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_10_fu_2551_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_10_reg_12480 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_11_fu_2571_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_11_reg_12485 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_11_reg_12485 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_p_Result_1_11_reg_12485 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_p_Result_1_11_reg_12485 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_12_fu_2591_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_12_reg_12492 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_12_reg_12492 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_p_Result_1_12_reg_12492 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_p_Result_1_12_reg_12492 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_13_fu_2611_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_1_13_reg_12499 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_p_Result_1_13_reg_12499 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_p_Result_1_13_reg_12499 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_p_Result_1_13_reg_12499 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_100_fu_2625_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_100_reg_12506 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter1_tmp_100_reg_12506 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_100_reg_12506 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_100_reg_12506 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_fu_3422_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_reg_12613 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_fu_3428_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_reg_12618 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_fu_3433_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_reg_12623 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_fu_3438_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_reg_12628 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_fu_3463_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_reg_12633 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_73_reg_12633 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_fu_3468_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_reg_12639 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_74_reg_12639 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_fu_3473_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_reg_12645 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_75_reg_12645 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_fu_3478_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_reg_12651 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_76_reg_12651 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_1_fu_4465_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_1_reg_12757 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_1_fu_4470_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_1_reg_12762 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_1_fu_4475_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_1_reg_12767 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_1_fu_4480_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_1_reg_12772 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_1_fu_4485_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_1_reg_12777 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_69_1_reg_12777 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_1_fu_4490_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_1_reg_12783 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_70_1_reg_12783 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_1_fu_4495_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_1_reg_12789 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_71_1_reg_12789 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_1_fu_4500_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_1_reg_12795 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_72_1_reg_12795 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_1_fu_4505_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_1_reg_12801 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_1_fu_4510_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_1_reg_12806 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_1_fu_4515_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_1_reg_12811 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_1_fu_4520_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_1_reg_12816 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_2_fu_5506_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_2_reg_12921 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_2_fu_5512_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_2_reg_12926 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_2_fu_5517_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_2_reg_12931 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_2_fu_5522_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_2_reg_12936 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_2_fu_5527_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_2_reg_12941 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_73_2_reg_12941 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_2_fu_5532_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_2_reg_12947 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_74_2_reg_12947 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_2_fu_5537_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_2_reg_12953 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_75_2_reg_12953 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_2_fu_5542_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_2_reg_12959 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_76_2_reg_12959 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_3_fu_6549_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_3_reg_13065 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_3_fu_6554_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_3_reg_13070 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_3_fu_6559_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_3_reg_13075 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_3_fu_6564_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_3_reg_13080 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_3_fu_6569_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_3_reg_13085 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_69_3_reg_13085 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_3_fu_6574_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_3_reg_13091 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_70_3_reg_13091 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_3_fu_6579_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_3_reg_13097 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_71_3_reg_13097 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_3_fu_6584_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_3_reg_13103 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_72_3_reg_13103 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_3_fu_6589_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_3_reg_13109 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_77_3_reg_13109 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_77_3_reg_13109 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_77_3_reg_13109 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_3_fu_6594_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_3_reg_13116 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_78_3_reg_13116 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_78_3_reg_13116 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_78_3_reg_13116 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_3_fu_6599_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_3_reg_13123 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_79_3_reg_13123 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_79_3_reg_13123 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_79_3_reg_13123 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_3_fu_6604_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_3_reg_13130 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_80_3_reg_13130 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_80_3_reg_13130 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_80_3_reg_13130 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_4_fu_7590_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_4_reg_13237 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_4_fu_7596_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_4_reg_13242 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_4_fu_7601_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_4_reg_13247 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_4_fu_7606_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_4_reg_13252 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_4_fu_7611_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_4_reg_13257 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_73_4_reg_13257 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_4_fu_7616_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_4_reg_13263 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_74_4_reg_13263 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_4_fu_7621_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_4_reg_13269 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_75_4_reg_13269 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_4_fu_7626_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_4_reg_13275 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_76_4_reg_13275 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_5_fu_8633_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_5_reg_13381 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_5_fu_8638_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_5_reg_13386 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_5_fu_8643_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_5_reg_13391 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_5_fu_8648_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_5_reg_13396 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_5_fu_8653_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_5_reg_13401 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_69_5_reg_13401 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_5_fu_8658_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_5_reg_13407 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_70_5_reg_13407 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_5_fu_8663_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_5_reg_13413 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_71_5_reg_13413 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_5_fu_8668_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_5_reg_13419 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_72_5_reg_13419 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_5_fu_8673_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_5_reg_13425 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_5_fu_8678_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_5_reg_13430 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_5_fu_8683_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_5_reg_13435 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_5_fu_8688_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_5_reg_13440 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_6_fu_9674_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_6_reg_13545 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_6_fu_9680_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_6_reg_13550 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_6_fu_9685_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_6_reg_13555 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_6_fu_9690_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_6_reg_13560 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_6_fu_9695_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_6_reg_13565 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_73_6_reg_13565 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_6_fu_9700_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_6_reg_13571 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_74_6_reg_13571 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_6_fu_9705_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_6_reg_13577 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_75_6_reg_13577 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_6_fu_9710_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_6_reg_13583 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_76_6_reg_13583 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_7_fu_10717_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_7_reg_13689 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_7_fu_10722_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_7_reg_13694 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_7_fu_10727_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_7_reg_13699 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_7_fu_10732_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_7_reg_13704 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_7_fu_10737_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_7_reg_13709 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_69_7_reg_13709 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_7_fu_10742_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_7_reg_13715 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_70_7_reg_13715 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_7_fu_10747_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_7_reg_13721 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_71_7_reg_13721 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_7_fu_10752_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_7_reg_13727 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_72_7_reg_13727 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_7_fu_10757_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_7_reg_13733 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_77_7_reg_13733 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_7_fu_10762_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_7_reg_13739 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_78_7_reg_13739 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_7_fu_10767_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_7_reg_13745 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_79_7_reg_13745 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_7_fu_10772_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_7_reg_13751 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_80_7_reg_13751 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_8_fu_11758_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_65_8_reg_13857 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_8_fu_11764_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_66_8_reg_13862 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_8_fu_11769_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_67_8_reg_13867 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_8_fu_11774_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_68_8_reg_13872 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_8_fu_11779_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_73_8_reg_13877 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_8_fu_11784_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_74_8_reg_13882 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_8_fu_11789_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_75_8_reg_13887 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_8_fu_11794_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_76_8_reg_13892 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal tmp_35_fu_2725_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_1_fu_2730_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_2_fu_2735_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_3_fu_2740_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_4_fu_2745_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_5_fu_2750_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_6_fu_2755_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_7_fu_2760_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_8_fu_2765_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_9_fu_2770_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_s_fu_2775_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_10_fu_2780_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_11_fu_2785_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_12_fu_2790_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_13_fu_2795_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_0_14_fu_2800_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_fu_2805_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_fu_2810_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_fu_2815_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_fu_2820_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_fu_3767_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_1_fu_3772_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_2_fu_3777_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_3_fu_3782_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_4_fu_3787_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_5_fu_3792_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_6_fu_3797_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_7_fu_3802_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_8_fu_3807_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_9_fu_3812_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_s_fu_3817_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_10_fu_3822_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_11_fu_3827_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_12_fu_3832_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_13_fu_3837_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_1_14_fu_3842_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_1_fu_3847_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_1_fu_3852_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_1_fu_3857_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_1_fu_3862_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_fu_4809_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_1_fu_4814_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_2_fu_4819_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_3_fu_4824_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_4_fu_4829_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_5_fu_4834_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_6_fu_4839_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_7_fu_4844_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_8_fu_4849_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_9_fu_4854_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_s_fu_4859_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_10_fu_4864_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_11_fu_4869_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_12_fu_4874_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_13_fu_4879_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_2_14_fu_4884_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_2_fu_4889_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_2_fu_4894_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_2_fu_4899_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_2_fu_4904_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_fu_5851_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_1_fu_5856_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_2_fu_5861_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_3_fu_5866_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_4_fu_5871_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_5_fu_5876_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_6_fu_5881_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_7_fu_5886_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_8_fu_5891_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_9_fu_5896_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_s_fu_5901_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_10_fu_5906_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_11_fu_5911_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_12_fu_5916_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_13_fu_5921_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_3_14_fu_5926_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_3_fu_5931_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_3_fu_5936_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_3_fu_5941_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_3_fu_5946_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_fu_6893_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_1_fu_6898_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_2_fu_6903_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_3_fu_6908_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_4_fu_6913_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_5_fu_6918_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_6_fu_6923_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_7_fu_6928_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_8_fu_6933_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_9_fu_6938_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_s_fu_6943_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_10_fu_6948_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_11_fu_6953_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_12_fu_6958_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_13_fu_6963_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_4_14_fu_6968_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_4_fu_6973_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_4_fu_6978_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_4_fu_6983_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_4_fu_6988_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_fu_7935_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_1_fu_7940_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_2_fu_7945_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_3_fu_7950_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_4_fu_7955_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_5_fu_7960_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_6_fu_7965_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_7_fu_7970_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_8_fu_7975_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_9_fu_7980_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_s_fu_7985_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_10_fu_7990_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_11_fu_7995_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_12_fu_8000_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_13_fu_8005_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_5_14_fu_8010_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_5_fu_8015_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_5_fu_8020_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_5_fu_8025_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_5_fu_8030_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_fu_8977_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_1_fu_8982_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_2_fu_8987_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_3_fu_8992_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_4_fu_8997_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_5_fu_9002_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_6_fu_9007_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_7_fu_9012_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_8_fu_9017_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_9_fu_9022_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_s_fu_9027_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_10_fu_9032_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_11_fu_9037_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_12_fu_9042_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_13_fu_9047_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_6_14_fu_9052_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_6_fu_9057_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_6_fu_9062_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_6_fu_9067_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_6_fu_9072_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_fu_10019_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_1_fu_10024_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_2_fu_10029_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_3_fu_10034_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_4_fu_10039_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_5_fu_10044_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_6_fu_10049_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_7_fu_10054_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_8_fu_10059_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_9_fu_10064_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_s_fu_10069_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_10_fu_10074_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_11_fu_10079_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_12_fu_10084_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_13_fu_10089_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_7_14_fu_10094_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_7_fu_10099_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_7_fu_10104_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_7_fu_10109_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_7_fu_10114_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_fu_11061_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_1_fu_11066_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_2_fu_11071_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_3_fu_11076_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_4_fu_11081_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_5_fu_11086_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_6_fu_11091_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_7_fu_11096_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_8_fu_11101_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_9_fu_11106_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_s_fu_11111_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_10_fu_11116_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_11_fu_11121_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_12_fu_11126_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_13_fu_11131_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_8_14_fu_11136_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_60_8_fu_11141_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_61_8_fu_11146_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_62_8_fu_11151_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_63_8_fu_11156_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_fu_12103_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_1_fu_12108_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_2_fu_12113_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_3_fu_12118_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_4_fu_12123_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_5_fu_12128_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_6_fu_12133_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_7_fu_12138_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_8_fu_12143_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_9_fu_12148_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_s_fu_12153_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_10_fu_12158_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_11_fu_12163_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_12_fu_12168_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_13_fu_12173_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_33_14_fu_12178_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_12183_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_1_fu_12188_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_2_fu_12193_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_12198_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Result_s_fu_2321_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_s_39_fu_2341_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_2_fu_2361_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_3_fu_2381_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_4_fu_2401_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_5_fu_2421_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_6_fu_2441_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_7_fu_2461_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_8_fu_2481_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_9_fu_2501_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_10_fu_2521_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_11_fu_2541_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_12_fu_2561_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_13_fu_2581_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Result_14_fu_2601_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_99_fu_2621_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_fu_2629_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_1_fu_2635_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_2_fu_2641_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_3_fu_2647_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_4_fu_2653_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_5_fu_2659_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_6_fu_2665_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_7_fu_2671_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_8_fu_2677_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_9_fu_2683_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_s_fu_2689_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_10_fu_2695_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_11_fu_2701_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_12_fu_2707_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_13_fu_2713_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_14_fu_2719_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_fu_2825_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_fu_2831_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_101_fu_2843_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_102_fu_2849_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_fu_2857_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_fu_2871_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_103_fu_2877_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_104_fu_2883_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_fu_2891_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_fu_2905_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_105_fu_2911_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_106_fu_2917_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_fu_2925_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_fu_2939_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_107_fu_2945_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_108_fu_2951_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_s_fu_2959_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_0_1_fu_2973_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_0_1_fu_2979_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_109_fu_2991_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_110_fu_2997_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_0_1_fu_3005_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_0_1_fu_3019_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_111_fu_3025_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_112_fu_3031_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_0_1_fu_3039_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_0_1_fu_3053_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_113_fu_3059_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_114_fu_3065_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_0_1_fu_3073_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_0_1_fu_3087_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_115_fu_3093_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_116_fu_3099_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_0_1_fu_3107_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_0_2_fu_3121_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_0_2_fu_3127_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_117_fu_3139_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_118_fu_3145_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_0_2_fu_3153_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_0_2_fu_3167_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_119_fu_3173_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_120_fu_3179_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_0_2_fu_3187_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_0_2_fu_3201_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_121_fu_3207_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_122_fu_3213_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_0_2_fu_3221_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_0_2_fu_3235_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_123_fu_3241_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_124_fu_3247_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_0_2_fu_3255_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_0_3_fu_3269_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_0_3_fu_3275_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_125_fu_3287_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_126_fu_3293_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_0_3_fu_3301_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_0_3_fu_3315_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_127_fu_3321_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_128_fu_3327_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_0_3_fu_3335_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_0_3_fu_3349_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_129_fu_3355_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_130_fu_3361_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_0_3_fu_3369_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_0_3_fu_3383_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_131_fu_3389_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_132_fu_3395_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_0_3_fu_3403_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_fu_3417_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_69_fu_3443_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_70_fu_3448_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_71_fu_3453_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_72_fu_3458_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_fu_2863_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_fu_2837_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp2_fu_3509_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp1_fu_3503_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_fu_2897_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp4_fu_3527_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp3_fu_3521_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_fu_2931_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp6_fu_3545_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp5_fu_3539_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp7_fu_3557_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_3_fu_2965_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_0_1_fu_3011_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_0_1_fu_2985_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp9_fu_3575_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp8_fu_3569_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_0_1_fu_3045_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp11_fu_3593_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp10_fu_3587_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_0_1_fu_3079_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp13_fu_3611_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp12_fu_3605_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp14_fu_3623_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_0_1_fu_3113_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_0_2_fu_3159_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_0_2_fu_3133_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp16_fu_3641_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp15_fu_3635_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_0_2_fu_3193_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp18_fu_3659_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp17_fu_3653_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_0_2_fu_3227_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp20_fu_3677_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp19_fu_3671_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp21_fu_3689_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_0_2_fu_3261_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_0_3_fu_3307_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_0_3_fu_3281_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_fu_3483_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp23_fu_3707_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp22_fu_3701_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_0_3_fu_3341_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_fu_3488_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp25_fu_3725_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp24_fu_3719_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_0_3_fu_3375_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_3493_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp27_fu_3743_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp26_fu_3737_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_fu_3498_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp28_fu_3755_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_0_3_fu_3409_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_fu_3515_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_1_fu_3533_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_2_fu_3551_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_3_fu_3563_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_4_fu_3581_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_5_fu_3599_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_6_fu_3617_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_7_fu_3629_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_8_fu_3647_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_9_fu_3665_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_s_fu_3683_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_10_fu_3695_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_11_fu_3713_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_12_fu_3731_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_13_fu_3749_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_0_14_fu_3761_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_s_fu_3867_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_1_fu_3873_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_133_fu_3885_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_134_fu_3891_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_1_fu_3899_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_1_fu_3913_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_135_fu_3919_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_136_fu_3925_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_1_fu_3933_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_1_fu_3947_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_137_fu_3953_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_138_fu_3959_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_1_fu_3967_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_1_fu_3981_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_139_fu_3987_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_140_fu_3993_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_1_fu_4001_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_171_1_fu_4015_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_1_1_fu_4021_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_141_fu_4033_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_142_fu_4039_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_1_1_fu_4047_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_1_1_fu_4061_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_143_fu_4067_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_144_fu_4073_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_1_1_fu_4081_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_1_1_fu_4095_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_145_fu_4101_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_146_fu_4107_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_1_1_fu_4115_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_1_1_fu_4129_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_147_fu_4135_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_148_fu_4141_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_1_1_fu_4149_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_171_2_fu_4163_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_1_2_fu_4169_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_149_fu_4181_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_150_fu_4187_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_1_2_fu_4195_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_1_2_fu_4209_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_151_fu_4215_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_152_fu_4221_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_1_2_fu_4229_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_1_2_fu_4243_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_153_fu_4249_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_154_fu_4255_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_1_2_fu_4263_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_1_2_fu_4277_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_155_fu_4283_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_156_fu_4289_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_1_2_fu_4297_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_171_3_fu_4311_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_1_3_fu_4317_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_157_fu_4329_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_158_fu_4335_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_1_3_fu_4343_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_1_3_fu_4357_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_159_fu_4363_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_160_fu_4369_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_1_3_fu_4377_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_1_3_fu_4391_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_161_fu_4397_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_162_fu_4403_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_1_3_fu_4411_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_1_3_fu_4425_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_163_fu_4431_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_164_fu_4437_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_1_3_fu_4445_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_64_1_fu_4459_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_1_fu_3905_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_1_fu_3879_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp30_fu_4531_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp29_fu_4525_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_1_fu_3939_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp32_fu_4549_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp31_fu_4543_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_1_fu_3973_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp34_fu_4567_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp33_fu_4561_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp35_fu_4579_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_1_fu_4007_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_1_1_fu_4053_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_1_1_fu_4027_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp37_fu_4597_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp36_fu_4591_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_1_1_fu_4087_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp39_fu_4615_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp38_fu_4609_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_1_1_fu_4121_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp41_fu_4633_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp40_fu_4627_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp42_fu_4645_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_1_1_fu_4155_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_1_2_fu_4201_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp45_fu_4663_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_1_2_fu_4175_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp44_fu_4668_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp43_fu_4657_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp48_fu_4686_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_1_2_fu_4235_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp47_fu_4691_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp46_fu_4680_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp51_fu_4709_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_1_2_fu_4269_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp50_fu_4714_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp49_fu_4703_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_1_2_fu_4303_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp53_fu_4732_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp52_fu_4726_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_1_3_fu_4349_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_1_3_fu_4323_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp55_fu_4749_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp54_fu_4743_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_1_3_fu_4383_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp57_fu_4767_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp56_fu_4761_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_1_3_fu_4417_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp59_fu_4785_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp58_fu_4779_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp60_fu_4797_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_1_3_fu_4451_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_fu_4537_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_1_fu_4555_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_2_fu_4573_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_3_fu_4585_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_4_fu_4603_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_5_fu_4621_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_6_fu_4639_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_7_fu_4651_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_8_fu_4674_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_9_fu_4697_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_s_fu_4720_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_10_fu_4737_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_11_fu_4755_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_12_fu_4773_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_13_fu_4791_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_1_14_fu_4803_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_9_fu_4909_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_2_fu_4915_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_165_fu_4927_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_166_fu_4933_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_2_fu_4941_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_2_fu_4955_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_167_fu_4961_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_168_fu_4967_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_2_fu_4975_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_2_fu_4989_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_169_fu_4995_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_170_fu_5001_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_2_fu_5009_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_2_fu_5023_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_171_fu_5029_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_172_fu_5035_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_2_fu_5043_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_273_1_fu_5057_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_2_1_fu_5063_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_173_fu_5075_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_174_fu_5081_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_2_1_fu_5089_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_2_1_fu_5103_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_175_fu_5109_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_176_fu_5115_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_2_1_fu_5123_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_2_1_fu_5137_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_177_fu_5143_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_178_fu_5149_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_2_1_fu_5157_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_2_1_fu_5171_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_179_fu_5177_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_180_fu_5183_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_2_1_fu_5191_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_273_2_fu_5205_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_2_2_fu_5211_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_181_fu_5223_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_182_fu_5229_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_2_2_fu_5237_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_2_2_fu_5251_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_183_fu_5257_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_184_fu_5263_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_2_2_fu_5271_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_2_2_fu_5285_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_185_fu_5291_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_186_fu_5297_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_2_2_fu_5305_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_2_2_fu_5319_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_187_fu_5325_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_188_fu_5331_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_2_2_fu_5339_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_273_3_fu_5353_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_2_3_fu_5359_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_189_fu_5371_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_190_fu_5377_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_2_3_fu_5385_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_2_3_fu_5399_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_191_fu_5405_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_192_fu_5411_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_2_3_fu_5419_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_2_3_fu_5433_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_193_fu_5439_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_194_fu_5445_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_2_3_fu_5453_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_2_3_fu_5467_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_195_fu_5473_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_196_fu_5479_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_2_3_fu_5487_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp61_fu_5501_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_2_fu_4947_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_2_fu_4921_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp63_fu_5573_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp62_fu_5567_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_2_fu_4981_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp65_fu_5591_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp64_fu_5585_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_2_fu_5015_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp67_fu_5609_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp66_fu_5603_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp68_fu_5621_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_2_fu_5049_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_2_1_fu_5095_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp71_fu_5639_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_2_1_fu_5069_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp70_fu_5644_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp69_fu_5633_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp74_fu_5662_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_2_1_fu_5129_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp73_fu_5667_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp72_fu_5656_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp77_fu_5685_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_2_1_fu_5163_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp76_fu_5690_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp75_fu_5679_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_2_1_fu_5197_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp79_fu_5708_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp78_fu_5702_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_2_2_fu_5243_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_2_2_fu_5217_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp81_fu_5725_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp80_fu_5719_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_2_2_fu_5277_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp83_fu_5743_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp82_fu_5737_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_2_2_fu_5311_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp85_fu_5761_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp84_fu_5755_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp86_fu_5773_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_2_2_fu_5345_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_2_3_fu_5391_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_2_3_fu_5365_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_2_fu_5547_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp88_fu_5791_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp87_fu_5785_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_2_3_fu_5425_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_2_fu_5552_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp90_fu_5809_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp89_fu_5803_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_2_3_fu_5459_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_2_fu_5557_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp92_fu_5827_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp91_fu_5821_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_2_fu_5562_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp93_fu_5839_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_2_3_fu_5493_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_fu_5579_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_1_fu_5597_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_2_fu_5615_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_3_fu_5627_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_4_fu_5650_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_5_fu_5673_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_6_fu_5696_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_7_fu_5713_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_8_fu_5731_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_9_fu_5749_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_s_fu_5767_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_10_fu_5779_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_11_fu_5797_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_12_fu_5815_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_13_fu_5833_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_2_14_fu_5845_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_10_fu_5951_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_3_fu_5957_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_197_fu_5969_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_198_fu_5975_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_3_fu_5983_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_3_fu_5997_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_199_fu_6003_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_200_fu_6009_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_3_fu_6017_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_3_fu_6031_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_201_fu_6037_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_202_fu_6043_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_3_fu_6051_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_3_fu_6065_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_203_fu_6071_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_204_fu_6077_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_3_fu_6085_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_375_1_fu_6099_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_3_1_fu_6105_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_205_fu_6117_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_206_fu_6123_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_3_1_fu_6131_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_3_1_fu_6145_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_207_fu_6151_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_208_fu_6157_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_3_1_fu_6165_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_3_1_fu_6179_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_209_fu_6185_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_210_fu_6191_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_3_1_fu_6199_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_3_1_fu_6213_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_211_fu_6219_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_212_fu_6225_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_3_1_fu_6233_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_375_2_fu_6247_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_3_2_fu_6253_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_213_fu_6265_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_214_fu_6271_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_3_2_fu_6279_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_3_2_fu_6293_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_215_fu_6299_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_216_fu_6305_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_3_2_fu_6313_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_3_2_fu_6327_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_217_fu_6333_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_218_fu_6339_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_3_2_fu_6347_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_3_2_fu_6361_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_219_fu_6367_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_220_fu_6373_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_3_2_fu_6381_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_375_3_fu_6395_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_3_3_fu_6401_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_221_fu_6413_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_222_fu_6419_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_3_3_fu_6427_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_3_3_fu_6441_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_223_fu_6447_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_224_fu_6453_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_3_3_fu_6461_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_3_3_fu_6475_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_225_fu_6481_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_226_fu_6487_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_3_3_fu_6495_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_3_3_fu_6509_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_227_fu_6515_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_228_fu_6521_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_3_3_fu_6529_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_64_3_fu_6543_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_3_fu_5989_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_3_fu_5963_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp95_fu_6615_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp94_fu_6609_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_3_fu_6023_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp97_fu_6633_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp96_fu_6627_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_3_fu_6057_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp99_fu_6651_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp98_fu_6645_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp100_fu_6663_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_3_fu_6091_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_3_1_fu_6137_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_3_1_fu_6111_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp102_fu_6681_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp101_fu_6675_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_3_1_fu_6171_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp104_fu_6699_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp103_fu_6693_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_3_1_fu_6205_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp106_fu_6717_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp105_fu_6711_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp107_fu_6729_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_3_1_fu_6239_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_3_2_fu_6285_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp110_fu_6747_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_3_2_fu_6259_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp109_fu_6752_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp108_fu_6741_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp113_fu_6770_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_3_2_fu_6319_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp112_fu_6775_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp111_fu_6764_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp116_fu_6793_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_3_2_fu_6353_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp115_fu_6798_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp114_fu_6787_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_3_2_fu_6387_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp118_fu_6816_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp117_fu_6810_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_3_3_fu_6433_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_3_3_fu_6407_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp120_fu_6833_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp119_fu_6827_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_3_3_fu_6467_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp122_fu_6851_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp121_fu_6845_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_3_3_fu_6501_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp124_fu_6869_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp123_fu_6863_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp125_fu_6881_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_3_3_fu_6535_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_fu_6621_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_1_fu_6639_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_2_fu_6657_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_3_fu_6669_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_4_fu_6687_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_5_fu_6705_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_6_fu_6723_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_7_fu_6735_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_8_fu_6758_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_9_fu_6781_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_s_fu_6804_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_10_fu_6821_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_11_fu_6839_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_12_fu_6857_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_13_fu_6875_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_3_14_fu_6887_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_4_fu_6993_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_4_fu_6999_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_229_fu_7011_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_230_fu_7017_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_4_fu_7025_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_4_fu_7039_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_231_fu_7045_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_232_fu_7051_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_4_fu_7059_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_4_fu_7073_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_233_fu_7079_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_234_fu_7085_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_4_fu_7093_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_4_fu_7107_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_235_fu_7113_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_236_fu_7119_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_4_fu_7127_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_4_1_fu_7141_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_4_1_fu_7147_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_237_fu_7159_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_238_fu_7165_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_4_1_fu_7173_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_4_1_fu_7187_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_239_fu_7193_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_240_fu_7199_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_4_1_fu_7207_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_4_1_fu_7221_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_241_fu_7227_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_242_fu_7233_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_4_1_fu_7241_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_4_1_fu_7255_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_243_fu_7261_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_244_fu_7267_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_4_1_fu_7275_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_4_2_fu_7289_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_4_2_fu_7295_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_245_fu_7307_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_246_fu_7313_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_4_2_fu_7321_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_4_2_fu_7335_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_247_fu_7341_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_248_fu_7347_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_4_2_fu_7355_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_4_2_fu_7369_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_249_fu_7375_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_250_fu_7381_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_4_2_fu_7389_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_4_2_fu_7403_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_251_fu_7409_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_252_fu_7415_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_4_2_fu_7423_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_4_3_fu_7437_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_4_3_fu_7443_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_253_fu_7455_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_254_fu_7461_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_4_3_fu_7469_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_4_3_fu_7483_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_255_fu_7489_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_256_fu_7495_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_4_3_fu_7503_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_4_3_fu_7517_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_257_fu_7523_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_258_fu_7529_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_4_3_fu_7537_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_4_3_fu_7551_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_259_fu_7557_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_260_fu_7563_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_4_3_fu_7571_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp126_fu_7585_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_4_fu_7031_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_4_fu_7005_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp128_fu_7657_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp127_fu_7651_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_4_fu_7065_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp130_fu_7675_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp129_fu_7669_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_4_fu_7099_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp132_fu_7693_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp131_fu_7687_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp133_fu_7705_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_4_fu_7133_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_4_1_fu_7179_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp136_fu_7723_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_4_1_fu_7153_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp135_fu_7728_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp134_fu_7717_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp139_fu_7746_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_4_1_fu_7213_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp138_fu_7751_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp137_fu_7740_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp142_fu_7769_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_4_1_fu_7247_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp141_fu_7774_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp140_fu_7763_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_4_1_fu_7281_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp144_fu_7792_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp143_fu_7786_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_4_2_fu_7327_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_4_2_fu_7301_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp146_fu_7809_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp145_fu_7803_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_4_2_fu_7361_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp148_fu_7827_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp147_fu_7821_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_4_2_fu_7395_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp150_fu_7845_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp149_fu_7839_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp151_fu_7857_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_4_2_fu_7429_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_4_3_fu_7475_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_4_3_fu_7449_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_4_fu_7631_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp153_fu_7875_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp152_fu_7869_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_4_3_fu_7509_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_4_fu_7636_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp155_fu_7893_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp154_fu_7887_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_4_3_fu_7543_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_4_fu_7641_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp157_fu_7911_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp156_fu_7905_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_4_fu_7646_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp158_fu_7923_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_4_3_fu_7577_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_fu_7663_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_1_fu_7681_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_2_fu_7699_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_3_fu_7711_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_4_fu_7734_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_5_fu_7757_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_6_fu_7780_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_7_fu_7797_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_8_fu_7815_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_9_fu_7833_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_s_fu_7851_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_10_fu_7863_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_11_fu_7881_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_12_fu_7899_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_13_fu_7917_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_4_14_fu_7929_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_5_fu_8035_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_5_fu_8041_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_261_fu_8053_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_262_fu_8059_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_5_fu_8067_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_5_fu_8081_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_263_fu_8087_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_264_fu_8093_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_5_fu_8101_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_5_fu_8115_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_265_fu_8121_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_266_fu_8127_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_5_fu_8135_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_5_fu_8149_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_267_fu_8155_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_268_fu_8161_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_5_fu_8169_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_5_1_fu_8183_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_5_1_fu_8189_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_269_fu_8201_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_270_fu_8207_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_5_1_fu_8215_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_5_1_fu_8229_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_271_fu_8235_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_272_fu_8241_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_5_1_fu_8249_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_5_1_fu_8263_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_273_fu_8269_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_274_fu_8275_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_5_1_fu_8283_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_5_1_fu_8297_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_275_fu_8303_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_276_fu_8309_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_5_1_fu_8317_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_5_2_fu_8331_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_5_2_fu_8337_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_277_fu_8349_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_278_fu_8355_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_5_2_fu_8363_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_5_2_fu_8377_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_279_fu_8383_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_280_fu_8389_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_5_2_fu_8397_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_5_2_fu_8411_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_281_fu_8417_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_282_fu_8423_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_5_2_fu_8431_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_5_2_fu_8445_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_283_fu_8451_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_284_fu_8457_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_5_2_fu_8465_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_5_3_fu_8479_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_5_3_fu_8485_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_285_fu_8497_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_286_fu_8503_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_5_3_fu_8511_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_5_3_fu_8525_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_287_fu_8531_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_288_fu_8537_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_5_3_fu_8545_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_5_3_fu_8559_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_289_fu_8565_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_290_fu_8571_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_5_3_fu_8579_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_5_3_fu_8593_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_291_fu_8599_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_292_fu_8605_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_5_3_fu_8613_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_64_5_fu_8627_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_5_fu_8073_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_5_fu_8047_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp160_fu_8699_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp159_fu_8693_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_5_fu_8107_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp162_fu_8717_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp161_fu_8711_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_5_fu_8141_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp164_fu_8735_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp163_fu_8729_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp165_fu_8747_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_5_fu_8175_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_5_1_fu_8221_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_5_1_fu_8195_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp167_fu_8765_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp166_fu_8759_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_5_1_fu_8255_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp169_fu_8783_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp168_fu_8777_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_5_1_fu_8289_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp171_fu_8801_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp170_fu_8795_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp172_fu_8813_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_5_1_fu_8323_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_5_2_fu_8369_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp175_fu_8831_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_5_2_fu_8343_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp174_fu_8836_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp173_fu_8825_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp178_fu_8854_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_5_2_fu_8403_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp177_fu_8859_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp176_fu_8848_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp181_fu_8877_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_5_2_fu_8437_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp180_fu_8882_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp179_fu_8871_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_5_2_fu_8471_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp183_fu_8900_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp182_fu_8894_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_5_3_fu_8517_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_5_3_fu_8491_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp185_fu_8917_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp184_fu_8911_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_5_3_fu_8551_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp187_fu_8935_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp186_fu_8929_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_5_3_fu_8585_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp189_fu_8953_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp188_fu_8947_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp190_fu_8965_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_5_3_fu_8619_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_fu_8705_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_1_fu_8723_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_2_fu_8741_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_3_fu_8753_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_4_fu_8771_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_5_fu_8789_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_6_fu_8807_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_7_fu_8819_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_8_fu_8842_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_9_fu_8865_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_s_fu_8888_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_10_fu_8905_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_11_fu_8923_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_12_fu_8941_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_13_fu_8959_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_5_14_fu_8971_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_6_fu_9077_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_6_fu_9083_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_293_fu_9095_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_294_fu_9101_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_6_fu_9109_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_6_fu_9123_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_295_fu_9129_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_296_fu_9135_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_6_fu_9143_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_6_fu_9157_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_297_fu_9163_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_298_fu_9169_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_6_fu_9177_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_6_fu_9191_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_299_fu_9197_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_300_fu_9203_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_6_fu_9211_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_6_1_fu_9225_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_6_1_fu_9231_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_301_fu_9243_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_302_fu_9249_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_6_1_fu_9257_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_6_1_fu_9271_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_303_fu_9277_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_304_fu_9283_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_6_1_fu_9291_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_6_1_fu_9305_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_305_fu_9311_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_306_fu_9317_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_6_1_fu_9325_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_6_1_fu_9339_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_307_fu_9345_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_308_fu_9351_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_6_1_fu_9359_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_6_2_fu_9373_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_6_2_fu_9379_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_309_fu_9391_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_310_fu_9397_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_6_2_fu_9405_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_6_2_fu_9419_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_311_fu_9425_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_312_fu_9431_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_6_2_fu_9439_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_6_2_fu_9453_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_313_fu_9459_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_314_fu_9465_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_6_2_fu_9473_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_6_2_fu_9487_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_315_fu_9493_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_316_fu_9499_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_6_2_fu_9507_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_6_3_fu_9521_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_6_3_fu_9527_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_317_fu_9539_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_318_fu_9545_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_6_3_fu_9553_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_6_3_fu_9567_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_319_fu_9573_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_320_fu_9579_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_6_3_fu_9587_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_6_3_fu_9601_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_321_fu_9607_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_322_fu_9613_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_6_3_fu_9621_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_6_3_fu_9635_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_323_fu_9641_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_324_fu_9647_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_6_3_fu_9655_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp191_fu_9669_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_6_fu_9115_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_6_fu_9089_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp193_fu_9741_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp192_fu_9735_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_6_fu_9149_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp195_fu_9759_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp194_fu_9753_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_6_fu_9183_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp197_fu_9777_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp196_fu_9771_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp198_fu_9789_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_6_fu_9217_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_6_1_fu_9263_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp201_fu_9807_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_6_1_fu_9237_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp200_fu_9812_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp199_fu_9801_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp204_fu_9830_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_6_1_fu_9297_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp203_fu_9835_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp202_fu_9824_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp207_fu_9853_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_6_1_fu_9331_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp206_fu_9858_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp205_fu_9847_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_6_1_fu_9365_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp209_fu_9876_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp208_fu_9870_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_6_2_fu_9411_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_6_2_fu_9385_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp211_fu_9893_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp210_fu_9887_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_6_2_fu_9445_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp213_fu_9911_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp212_fu_9905_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_6_2_fu_9479_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp215_fu_9929_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp214_fu_9923_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp216_fu_9941_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_6_2_fu_9513_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_6_3_fu_9559_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_6_3_fu_9533_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_6_fu_9715_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp218_fu_9959_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp217_fu_9953_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_6_3_fu_9593_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_6_fu_9720_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp220_fu_9977_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp219_fu_9971_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_6_3_fu_9627_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_6_fu_9725_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp222_fu_9995_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp221_fu_9989_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_6_fu_9730_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp223_fu_10007_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_6_3_fu_9661_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_fu_9747_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_1_fu_9765_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_2_fu_9783_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_3_fu_9795_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_4_fu_9818_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_5_fu_9841_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_6_fu_9864_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_7_fu_9881_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_8_fu_9899_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_9_fu_9917_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_s_fu_9935_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_10_fu_9947_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_11_fu_9965_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_12_fu_9983_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_13_fu_10001_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_6_14_fu_10013_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_7_fu_10119_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_7_fu_10125_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_325_fu_10137_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_326_fu_10143_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_7_fu_10151_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_7_fu_10165_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_327_fu_10171_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_328_fu_10177_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_7_fu_10185_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_7_fu_10199_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_329_fu_10205_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_330_fu_10211_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_7_fu_10219_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_7_fu_10233_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_331_fu_10239_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_332_fu_10245_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_7_fu_10253_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_7_1_fu_10267_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_7_1_fu_10273_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_333_fu_10285_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_334_fu_10291_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_7_1_fu_10299_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_7_1_fu_10313_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_335_fu_10319_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_336_fu_10325_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_7_1_fu_10333_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_7_1_fu_10347_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_337_fu_10353_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_338_fu_10359_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_7_1_fu_10367_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_7_1_fu_10381_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_339_fu_10387_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_340_fu_10393_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_7_1_fu_10401_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_7_2_fu_10415_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_7_2_fu_10421_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_341_fu_10433_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_342_fu_10439_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_7_2_fu_10447_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_7_2_fu_10461_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_343_fu_10467_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_344_fu_10473_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_7_2_fu_10481_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_7_2_fu_10495_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_345_fu_10501_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_346_fu_10507_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_7_2_fu_10515_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_7_2_fu_10529_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_347_fu_10535_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_348_fu_10541_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_7_2_fu_10549_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_7_3_fu_10563_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_7_3_fu_10569_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_349_fu_10581_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_10587_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_7_3_fu_10595_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_7_3_fu_10609_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_351_fu_10615_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_352_fu_10621_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_7_3_fu_10629_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_7_3_fu_10643_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_10649_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_354_fu_10655_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_7_3_fu_10663_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_7_3_fu_10677_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_355_fu_10683_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_356_fu_10689_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_7_3_fu_10697_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_64_7_fu_10711_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_7_fu_10157_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_7_fu_10131_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp225_fu_10783_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp224_fu_10777_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_7_fu_10191_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp227_fu_10801_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp226_fu_10795_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_7_fu_10225_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp229_fu_10819_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp228_fu_10813_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp230_fu_10831_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_7_fu_10259_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_7_1_fu_10305_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_7_1_fu_10279_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp232_fu_10849_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp231_fu_10843_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_7_1_fu_10339_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp234_fu_10867_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp233_fu_10861_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_7_1_fu_10373_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp236_fu_10885_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp235_fu_10879_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp237_fu_10897_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_7_1_fu_10407_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_7_2_fu_10453_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp240_fu_10915_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_7_2_fu_10427_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp239_fu_10920_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp238_fu_10909_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp243_fu_10938_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_7_2_fu_10487_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp242_fu_10943_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp241_fu_10932_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp246_fu_10961_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_7_2_fu_10521_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp245_fu_10966_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp244_fu_10955_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_7_2_fu_10555_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp248_fu_10984_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp247_fu_10978_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_7_3_fu_10601_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_7_3_fu_10575_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp250_fu_11001_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp249_fu_10995_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_7_3_fu_10635_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp252_fu_11019_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp251_fu_11013_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_7_3_fu_10669_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp254_fu_11037_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp253_fu_11031_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp255_fu_11049_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_7_3_fu_10703_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_fu_10789_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_1_fu_10807_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_2_fu_10825_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_3_fu_10837_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_4_fu_10855_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_5_fu_10873_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_6_fu_10891_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_7_fu_10903_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_8_fu_10926_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_9_fu_10949_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_s_fu_10972_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_10_fu_10989_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_11_fu_11007_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_12_fu_11025_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_13_fu_11043_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_7_14_fu_11055_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_8_fu_11161_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_8_fu_11167_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_357_fu_11179_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_358_fu_11185_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_8_fu_11193_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_8_fu_11207_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_359_fu_11213_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_360_fu_11219_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_8_fu_11227_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_8_fu_11241_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_361_fu_11247_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_362_fu_11253_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_8_fu_11261_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_8_fu_11275_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_363_fu_11281_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_364_fu_11287_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_8_fu_11295_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_8_1_fu_11309_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_8_1_fu_11315_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_365_fu_11327_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_366_fu_11333_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_8_1_fu_11341_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_8_1_fu_11355_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_367_fu_11361_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_368_fu_11367_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_8_1_fu_11375_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_8_1_fu_11389_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_369_fu_11395_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_370_fu_11401_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_8_1_fu_11409_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_8_1_fu_11423_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_371_fu_11429_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_372_fu_11435_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_8_1_fu_11443_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_8_2_fu_11457_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_8_2_fu_11463_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_373_fu_11475_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_374_fu_11481_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_8_2_fu_11489_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_8_2_fu_11503_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_375_fu_11509_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_376_fu_11515_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_8_2_fu_11523_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_8_2_fu_11537_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_377_fu_11543_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_378_fu_11549_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_8_2_fu_11557_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_8_2_fu_11571_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_379_fu_11577_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_380_fu_11583_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_8_2_fu_11591_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_8_3_fu_11605_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_47_8_3_fu_11611_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_381_fu_11623_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_382_fu_11629_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_1_8_3_fu_11637_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_1_8_3_fu_11651_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_383_fu_11657_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_384_fu_11663_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_4_8_3_fu_11671_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_2_8_3_fu_11685_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_385_fu_11691_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_386_fu_11697_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_7_8_3_fu_11705_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal x_assign_3_8_3_fu_11719_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_387_fu_11725_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_388_fu_11731_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal rv_10_8_3_fu_11739_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp256_fu_11753_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_8_fu_11199_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_8_fu_11173_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp258_fu_11825_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp257_fu_11819_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_8_fu_11233_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp260_fu_11843_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp259_fu_11837_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_8_fu_11267_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp262_fu_11861_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp261_fu_11855_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp263_fu_11873_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_8_fu_11301_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_8_1_fu_11347_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp266_fu_11891_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal e_8_1_fu_11321_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp265_fu_11896_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp264_fu_11885_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp269_fu_11914_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_8_1_fu_11381_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp268_fu_11919_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp267_fu_11908_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp272_fu_11937_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_8_1_fu_11415_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp271_fu_11942_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp270_fu_11931_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_8_1_fu_11449_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp274_fu_11960_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp273_fu_11954_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_8_2_fu_11495_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_8_2_fu_11469_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp276_fu_11977_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp275_fu_11971_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_8_2_fu_11529_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp278_fu_11995_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp277_fu_11989_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_8_2_fu_11563_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp280_fu_12013_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp279_fu_12007_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp281_fu_12025_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_8_2_fu_11597_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_2_8_3_fu_11643_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal e_8_3_fu_11617_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_77_8_fu_11799_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp283_fu_12043_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp282_fu_12037_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_5_8_3_fu_11677_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_78_8_fu_11804_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp285_fu_12061_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp284_fu_12055_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_8_8_3_fu_11711_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_8_fu_11809_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp287_fu_12079_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp286_fu_12073_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_80_8_fu_11814_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp288_fu_12091_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal rv_11_8_3_fu_11745_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_fu_11831_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_1_fu_11849_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_2_fu_11867_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_3_fu_11879_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_4_fu_11902_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_5_fu_11925_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_6_fu_11948_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_7_fu_11965_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_8_fu_11983_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_9_fu_12001_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_s_fu_12019_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_10_fu_12031_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_11_fu_12049_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_12_fu_12067_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_13_fu_12085_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_85_8_14_fu_12097_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_4_fu_12203_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp289_fu_12229_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp290_fu_12240_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp291_fu_12251_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp292_fu_12262_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_fu_12209_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_11_fu_12214_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_12_fu_12219_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_fu_12224_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp293_fu_12297_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp294_fu_12308_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp295_fu_12319_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp296_fu_12330_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp297_fu_12341_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp298_fu_12352_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp299_fu_12363_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp300_fu_12374_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_fu_12234_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_1_fu_12245_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_2_fu_12256_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_3_fu_12267_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_4_fu_12273_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_5_fu_12279_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_6_fu_12285_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_7_fu_12291_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_8_fu_12302_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_9_fu_12313_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_s_fu_12324_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_10_fu_12335_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_11_fu_12346_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_12_fu_12357_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_13_fu_12368_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_38_14_fu_12379_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_idle_pp0_0to9 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_reset_start_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component aestest_sboxes IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0);
address3 : IN STD_LOGIC_VECTOR (7 downto 0);
ce3 : IN STD_LOGIC;
q3 : OUT STD_LOGIC_VECTOR (7 downto 0);
address4 : IN STD_LOGIC_VECTOR (7 downto 0);
ce4 : IN STD_LOGIC;
q4 : OUT STD_LOGIC_VECTOR (7 downto 0);
address5 : IN STD_LOGIC_VECTOR (7 downto 0);
ce5 : IN STD_LOGIC;
q5 : OUT STD_LOGIC_VECTOR (7 downto 0);
address6 : IN STD_LOGIC_VECTOR (7 downto 0);
ce6 : IN STD_LOGIC;
q6 : OUT STD_LOGIC_VECTOR (7 downto 0);
address7 : IN STD_LOGIC_VECTOR (7 downto 0);
ce7 : IN STD_LOGIC;
q7 : OUT STD_LOGIC_VECTOR (7 downto 0);
address8 : IN STD_LOGIC_VECTOR (7 downto 0);
ce8 : IN STD_LOGIC;
q8 : OUT STD_LOGIC_VECTOR (7 downto 0);
address9 : IN STD_LOGIC_VECTOR (7 downto 0);
ce9 : IN STD_LOGIC;
q9 : OUT STD_LOGIC_VECTOR (7 downto 0);
address10 : IN STD_LOGIC_VECTOR (7 downto 0);
ce10 : IN STD_LOGIC;
q10 : OUT STD_LOGIC_VECTOR (7 downto 0);
address11 : IN STD_LOGIC_VECTOR (7 downto 0);
ce11 : IN STD_LOGIC;
q11 : OUT STD_LOGIC_VECTOR (7 downto 0);
address12 : IN STD_LOGIC_VECTOR (7 downto 0);
ce12 : IN STD_LOGIC;
q12 : OUT STD_LOGIC_VECTOR (7 downto 0);
address13 : IN STD_LOGIC_VECTOR (7 downto 0);
ce13 : IN STD_LOGIC;
q13 : OUT STD_LOGIC_VECTOR (7 downto 0);
address14 : IN STD_LOGIC_VECTOR (7 downto 0);
ce14 : IN STD_LOGIC;
q14 : OUT STD_LOGIC_VECTOR (7 downto 0);
address15 : IN STD_LOGIC_VECTOR (7 downto 0);
ce15 : IN STD_LOGIC;
q15 : OUT STD_LOGIC_VECTOR (7 downto 0);
address16 : IN STD_LOGIC_VECTOR (7 downto 0);
ce16 : IN STD_LOGIC;
q16 : OUT STD_LOGIC_VECTOR (7 downto 0);
address17 : IN STD_LOGIC_VECTOR (7 downto 0);
ce17 : IN STD_LOGIC;
q17 : OUT STD_LOGIC_VECTOR (7 downto 0);
address18 : IN STD_LOGIC_VECTOR (7 downto 0);
ce18 : IN STD_LOGIC;
q18 : OUT STD_LOGIC_VECTOR (7 downto 0);
address19 : IN STD_LOGIC_VECTOR (7 downto 0);
ce19 : IN STD_LOGIC;
q19 : OUT STD_LOGIC_VECTOR (7 downto 0);
address20 : IN STD_LOGIC_VECTOR (7 downto 0);
ce20 : IN STD_LOGIC;
q20 : OUT STD_LOGIC_VECTOR (7 downto 0);
address21 : IN STD_LOGIC_VECTOR (7 downto 0);
ce21 : IN STD_LOGIC;
q21 : OUT STD_LOGIC_VECTOR (7 downto 0);
address22 : IN STD_LOGIC_VECTOR (7 downto 0);
ce22 : IN STD_LOGIC;
q22 : OUT STD_LOGIC_VECTOR (7 downto 0);
address23 : IN STD_LOGIC_VECTOR (7 downto 0);
ce23 : IN STD_LOGIC;
q23 : OUT STD_LOGIC_VECTOR (7 downto 0);
address24 : IN STD_LOGIC_VECTOR (7 downto 0);
ce24 : IN STD_LOGIC;
q24 : OUT STD_LOGIC_VECTOR (7 downto 0);
address25 : IN STD_LOGIC_VECTOR (7 downto 0);
ce25 : IN STD_LOGIC;
q25 : OUT STD_LOGIC_VECTOR (7 downto 0);
address26 : IN STD_LOGIC_VECTOR (7 downto 0);
ce26 : IN STD_LOGIC;
q26 : OUT STD_LOGIC_VECTOR (7 downto 0);
address27 : IN STD_LOGIC_VECTOR (7 downto 0);
ce27 : IN STD_LOGIC;
q27 : OUT STD_LOGIC_VECTOR (7 downto 0);
address28 : IN STD_LOGIC_VECTOR (7 downto 0);
ce28 : IN STD_LOGIC;
q28 : OUT STD_LOGIC_VECTOR (7 downto 0);
address29 : IN STD_LOGIC_VECTOR (7 downto 0);
ce29 : IN STD_LOGIC;
q29 : OUT STD_LOGIC_VECTOR (7 downto 0);
address30 : IN STD_LOGIC_VECTOR (7 downto 0);
ce30 : IN STD_LOGIC;
q30 : OUT STD_LOGIC_VECTOR (7 downto 0);
address31 : IN STD_LOGIC_VECTOR (7 downto 0);
ce31 : IN STD_LOGIC;
q31 : OUT STD_LOGIC_VECTOR (7 downto 0);
address32 : IN STD_LOGIC_VECTOR (7 downto 0);
ce32 : IN STD_LOGIC;
q32 : OUT STD_LOGIC_VECTOR (7 downto 0);
address33 : IN STD_LOGIC_VECTOR (7 downto 0);
ce33 : IN STD_LOGIC;
q33 : OUT STD_LOGIC_VECTOR (7 downto 0);
address34 : IN STD_LOGIC_VECTOR (7 downto 0);
ce34 : IN STD_LOGIC;
q34 : OUT STD_LOGIC_VECTOR (7 downto 0);
address35 : IN STD_LOGIC_VECTOR (7 downto 0);
ce35 : IN STD_LOGIC;
q35 : OUT STD_LOGIC_VECTOR (7 downto 0);
address36 : IN STD_LOGIC_VECTOR (7 downto 0);
ce36 : IN STD_LOGIC;
q36 : OUT STD_LOGIC_VECTOR (7 downto 0);
address37 : IN STD_LOGIC_VECTOR (7 downto 0);
ce37 : IN STD_LOGIC;
q37 : OUT STD_LOGIC_VECTOR (7 downto 0);
address38 : IN STD_LOGIC_VECTOR (7 downto 0);
ce38 : IN STD_LOGIC;
q38 : OUT STD_LOGIC_VECTOR (7 downto 0);
address39 : IN STD_LOGIC_VECTOR (7 downto 0);
ce39 : IN STD_LOGIC;
q39 : OUT STD_LOGIC_VECTOR (7 downto 0);
address40 : IN STD_LOGIC_VECTOR (7 downto 0);
ce40 : IN STD_LOGIC;
q40 : OUT STD_LOGIC_VECTOR (7 downto 0);
address41 : IN STD_LOGIC_VECTOR (7 downto 0);
ce41 : IN STD_LOGIC;
q41 : OUT STD_LOGIC_VECTOR (7 downto 0);
address42 : IN STD_LOGIC_VECTOR (7 downto 0);
ce42 : IN STD_LOGIC;
q42 : OUT STD_LOGIC_VECTOR (7 downto 0);
address43 : IN STD_LOGIC_VECTOR (7 downto 0);
ce43 : IN STD_LOGIC;
q43 : OUT STD_LOGIC_VECTOR (7 downto 0);
address44 : IN STD_LOGIC_VECTOR (7 downto 0);
ce44 : IN STD_LOGIC;
q44 : OUT STD_LOGIC_VECTOR (7 downto 0);
address45 : IN STD_LOGIC_VECTOR (7 downto 0);
ce45 : IN STD_LOGIC;
q45 : OUT STD_LOGIC_VECTOR (7 downto 0);
address46 : IN STD_LOGIC_VECTOR (7 downto 0);
ce46 : IN STD_LOGIC;
q46 : OUT STD_LOGIC_VECTOR (7 downto 0);
address47 : IN STD_LOGIC_VECTOR (7 downto 0);
ce47 : IN STD_LOGIC;
q47 : OUT STD_LOGIC_VECTOR (7 downto 0);
address48 : IN STD_LOGIC_VECTOR (7 downto 0);
ce48 : IN STD_LOGIC;
q48 : OUT STD_LOGIC_VECTOR (7 downto 0);
address49 : IN STD_LOGIC_VECTOR (7 downto 0);
ce49 : IN STD_LOGIC;
q49 : OUT STD_LOGIC_VECTOR (7 downto 0);
address50 : IN STD_LOGIC_VECTOR (7 downto 0);
ce50 : IN STD_LOGIC;
q50 : OUT STD_LOGIC_VECTOR (7 downto 0);
address51 : IN STD_LOGIC_VECTOR (7 downto 0);
ce51 : IN STD_LOGIC;
q51 : OUT STD_LOGIC_VECTOR (7 downto 0);
address52 : IN STD_LOGIC_VECTOR (7 downto 0);
ce52 : IN STD_LOGIC;
q52 : OUT STD_LOGIC_VECTOR (7 downto 0);
address53 : IN STD_LOGIC_VECTOR (7 downto 0);
ce53 : IN STD_LOGIC;
q53 : OUT STD_LOGIC_VECTOR (7 downto 0);
address54 : IN STD_LOGIC_VECTOR (7 downto 0);
ce54 : IN STD_LOGIC;
q54 : OUT STD_LOGIC_VECTOR (7 downto 0);
address55 : IN STD_LOGIC_VECTOR (7 downto 0);
ce55 : IN STD_LOGIC;
q55 : OUT STD_LOGIC_VECTOR (7 downto 0);
address56 : IN STD_LOGIC_VECTOR (7 downto 0);
ce56 : IN STD_LOGIC;
q56 : OUT STD_LOGIC_VECTOR (7 downto 0);
address57 : IN STD_LOGIC_VECTOR (7 downto 0);
ce57 : IN STD_LOGIC;
q57 : OUT STD_LOGIC_VECTOR (7 downto 0);
address58 : IN STD_LOGIC_VECTOR (7 downto 0);
ce58 : IN STD_LOGIC;
q58 : OUT STD_LOGIC_VECTOR (7 downto 0);
address59 : IN STD_LOGIC_VECTOR (7 downto 0);
ce59 : IN STD_LOGIC;
q59 : OUT STD_LOGIC_VECTOR (7 downto 0);
address60 : IN STD_LOGIC_VECTOR (7 downto 0);
ce60 : IN STD_LOGIC;
q60 : OUT STD_LOGIC_VECTOR (7 downto 0);
address61 : IN STD_LOGIC_VECTOR (7 downto 0);
ce61 : IN STD_LOGIC;
q61 : OUT STD_LOGIC_VECTOR (7 downto 0);
address62 : IN STD_LOGIC_VECTOR (7 downto 0);
ce62 : IN STD_LOGIC;
q62 : OUT STD_LOGIC_VECTOR (7 downto 0);
address63 : IN STD_LOGIC_VECTOR (7 downto 0);
ce63 : IN STD_LOGIC;
q63 : OUT STD_LOGIC_VECTOR (7 downto 0);
address64 : IN STD_LOGIC_VECTOR (7 downto 0);
ce64 : IN STD_LOGIC;
q64 : OUT STD_LOGIC_VECTOR (7 downto 0);
address65 : IN STD_LOGIC_VECTOR (7 downto 0);
ce65 : IN STD_LOGIC;
q65 : OUT STD_LOGIC_VECTOR (7 downto 0);
address66 : IN STD_LOGIC_VECTOR (7 downto 0);
ce66 : IN STD_LOGIC;
q66 : OUT STD_LOGIC_VECTOR (7 downto 0);
address67 : IN STD_LOGIC_VECTOR (7 downto 0);
ce67 : IN STD_LOGIC;
q67 : OUT STD_LOGIC_VECTOR (7 downto 0);
address68 : IN STD_LOGIC_VECTOR (7 downto 0);
ce68 : IN STD_LOGIC;
q68 : OUT STD_LOGIC_VECTOR (7 downto 0);
address69 : IN STD_LOGIC_VECTOR (7 downto 0);
ce69 : IN STD_LOGIC;
q69 : OUT STD_LOGIC_VECTOR (7 downto 0);
address70 : IN STD_LOGIC_VECTOR (7 downto 0);
ce70 : IN STD_LOGIC;
q70 : OUT STD_LOGIC_VECTOR (7 downto 0);
address71 : IN STD_LOGIC_VECTOR (7 downto 0);
ce71 : IN STD_LOGIC;
q71 : OUT STD_LOGIC_VECTOR (7 downto 0);
address72 : IN STD_LOGIC_VECTOR (7 downto 0);
ce72 : IN STD_LOGIC;
q72 : OUT STD_LOGIC_VECTOR (7 downto 0);
address73 : IN STD_LOGIC_VECTOR (7 downto 0);
ce73 : IN STD_LOGIC;
q73 : OUT STD_LOGIC_VECTOR (7 downto 0);
address74 : IN STD_LOGIC_VECTOR (7 downto 0);
ce74 : IN STD_LOGIC;
q74 : OUT STD_LOGIC_VECTOR (7 downto 0);
address75 : IN STD_LOGIC_VECTOR (7 downto 0);
ce75 : IN STD_LOGIC;
q75 : OUT STD_LOGIC_VECTOR (7 downto 0);
address76 : IN STD_LOGIC_VECTOR (7 downto 0);
ce76 : IN STD_LOGIC;
q76 : OUT STD_LOGIC_VECTOR (7 downto 0);
address77 : IN STD_LOGIC_VECTOR (7 downto 0);
ce77 : IN STD_LOGIC;
q77 : OUT STD_LOGIC_VECTOR (7 downto 0);
address78 : IN STD_LOGIC_VECTOR (7 downto 0);
ce78 : IN STD_LOGIC;
q78 : OUT STD_LOGIC_VECTOR (7 downto 0);
address79 : IN STD_LOGIC_VECTOR (7 downto 0);
ce79 : IN STD_LOGIC;
q79 : OUT STD_LOGIC_VECTOR (7 downto 0);
address80 : IN STD_LOGIC_VECTOR (7 downto 0);
ce80 : IN STD_LOGIC;
q80 : OUT STD_LOGIC_VECTOR (7 downto 0);
address81 : IN STD_LOGIC_VECTOR (7 downto 0);
ce81 : IN STD_LOGIC;
q81 : OUT STD_LOGIC_VECTOR (7 downto 0);
address82 : IN STD_LOGIC_VECTOR (7 downto 0);
ce82 : IN STD_LOGIC;
q82 : OUT STD_LOGIC_VECTOR (7 downto 0);
address83 : IN STD_LOGIC_VECTOR (7 downto 0);
ce83 : IN STD_LOGIC;
q83 : OUT STD_LOGIC_VECTOR (7 downto 0);
address84 : IN STD_LOGIC_VECTOR (7 downto 0);
ce84 : IN STD_LOGIC;
q84 : OUT STD_LOGIC_VECTOR (7 downto 0);
address85 : IN STD_LOGIC_VECTOR (7 downto 0);
ce85 : IN STD_LOGIC;
q85 : OUT STD_LOGIC_VECTOR (7 downto 0);
address86 : IN STD_LOGIC_VECTOR (7 downto 0);
ce86 : IN STD_LOGIC;
q86 : OUT STD_LOGIC_VECTOR (7 downto 0);
address87 : IN STD_LOGIC_VECTOR (7 downto 0);
ce87 : IN STD_LOGIC;
q87 : OUT STD_LOGIC_VECTOR (7 downto 0);
address88 : IN STD_LOGIC_VECTOR (7 downto 0);
ce88 : IN STD_LOGIC;
q88 : OUT STD_LOGIC_VECTOR (7 downto 0);
address89 : IN STD_LOGIC_VECTOR (7 downto 0);
ce89 : IN STD_LOGIC;
q89 : OUT STD_LOGIC_VECTOR (7 downto 0);
address90 : IN STD_LOGIC_VECTOR (7 downto 0);
ce90 : IN STD_LOGIC;
q90 : OUT STD_LOGIC_VECTOR (7 downto 0);
address91 : IN STD_LOGIC_VECTOR (7 downto 0);
ce91 : IN STD_LOGIC;
q91 : OUT STD_LOGIC_VECTOR (7 downto 0);
address92 : IN STD_LOGIC_VECTOR (7 downto 0);
ce92 : IN STD_LOGIC;
q92 : OUT STD_LOGIC_VECTOR (7 downto 0);
address93 : IN STD_LOGIC_VECTOR (7 downto 0);
ce93 : IN STD_LOGIC;
q93 : OUT STD_LOGIC_VECTOR (7 downto 0);
address94 : IN STD_LOGIC_VECTOR (7 downto 0);
ce94 : IN STD_LOGIC;
q94 : OUT STD_LOGIC_VECTOR (7 downto 0);
address95 : IN STD_LOGIC_VECTOR (7 downto 0);
ce95 : IN STD_LOGIC;
q95 : OUT STD_LOGIC_VECTOR (7 downto 0);
address96 : IN STD_LOGIC_VECTOR (7 downto 0);
ce96 : IN STD_LOGIC;
q96 : OUT STD_LOGIC_VECTOR (7 downto 0);
address97 : IN STD_LOGIC_VECTOR (7 downto 0);
ce97 : IN STD_LOGIC;
q97 : OUT STD_LOGIC_VECTOR (7 downto 0);
address98 : IN STD_LOGIC_VECTOR (7 downto 0);
ce98 : IN STD_LOGIC;
q98 : OUT STD_LOGIC_VECTOR (7 downto 0);
address99 : IN STD_LOGIC_VECTOR (7 downto 0);
ce99 : IN STD_LOGIC;
q99 : OUT STD_LOGIC_VECTOR (7 downto 0);
address100 : IN STD_LOGIC_VECTOR (7 downto 0);
ce100 : IN STD_LOGIC;
q100 : OUT STD_LOGIC_VECTOR (7 downto 0);
address101 : IN STD_LOGIC_VECTOR (7 downto 0);
ce101 : IN STD_LOGIC;
q101 : OUT STD_LOGIC_VECTOR (7 downto 0);
address102 : IN STD_LOGIC_VECTOR (7 downto 0);
ce102 : IN STD_LOGIC;
q102 : OUT STD_LOGIC_VECTOR (7 downto 0);
address103 : IN STD_LOGIC_VECTOR (7 downto 0);
ce103 : IN STD_LOGIC;
q103 : OUT STD_LOGIC_VECTOR (7 downto 0);
address104 : IN STD_LOGIC_VECTOR (7 downto 0);
ce104 : IN STD_LOGIC;
q104 : OUT STD_LOGIC_VECTOR (7 downto 0);
address105 : IN STD_LOGIC_VECTOR (7 downto 0);
ce105 : IN STD_LOGIC;
q105 : OUT STD_LOGIC_VECTOR (7 downto 0);
address106 : IN STD_LOGIC_VECTOR (7 downto 0);
ce106 : IN STD_LOGIC;
q106 : OUT STD_LOGIC_VECTOR (7 downto 0);
address107 : IN STD_LOGIC_VECTOR (7 downto 0);
ce107 : IN STD_LOGIC;
q107 : OUT STD_LOGIC_VECTOR (7 downto 0);
address108 : IN STD_LOGIC_VECTOR (7 downto 0);
ce108 : IN STD_LOGIC;
q108 : OUT STD_LOGIC_VECTOR (7 downto 0);
address109 : IN STD_LOGIC_VECTOR (7 downto 0);
ce109 : IN STD_LOGIC;
q109 : OUT STD_LOGIC_VECTOR (7 downto 0);
address110 : IN STD_LOGIC_VECTOR (7 downto 0);
ce110 : IN STD_LOGIC;
q110 : OUT STD_LOGIC_VECTOR (7 downto 0);
address111 : IN STD_LOGIC_VECTOR (7 downto 0);
ce111 : IN STD_LOGIC;
q111 : OUT STD_LOGIC_VECTOR (7 downto 0);
address112 : IN STD_LOGIC_VECTOR (7 downto 0);
ce112 : IN STD_LOGIC;
q112 : OUT STD_LOGIC_VECTOR (7 downto 0);
address113 : IN STD_LOGIC_VECTOR (7 downto 0);
ce113 : IN STD_LOGIC;
q113 : OUT STD_LOGIC_VECTOR (7 downto 0);
address114 : IN STD_LOGIC_VECTOR (7 downto 0);
ce114 : IN STD_LOGIC;
q114 : OUT STD_LOGIC_VECTOR (7 downto 0);
address115 : IN STD_LOGIC_VECTOR (7 downto 0);
ce115 : IN STD_LOGIC;
q115 : OUT STD_LOGIC_VECTOR (7 downto 0);
address116 : IN STD_LOGIC_VECTOR (7 downto 0);
ce116 : IN STD_LOGIC;
q116 : OUT STD_LOGIC_VECTOR (7 downto 0);
address117 : IN STD_LOGIC_VECTOR (7 downto 0);
ce117 : IN STD_LOGIC;
q117 : OUT STD_LOGIC_VECTOR (7 downto 0);
address118 : IN STD_LOGIC_VECTOR (7 downto 0);
ce118 : IN STD_LOGIC;
q118 : OUT STD_LOGIC_VECTOR (7 downto 0);
address119 : IN STD_LOGIC_VECTOR (7 downto 0);
ce119 : IN STD_LOGIC;
q119 : OUT STD_LOGIC_VECTOR (7 downto 0);
address120 : IN STD_LOGIC_VECTOR (7 downto 0);
ce120 : IN STD_LOGIC;
q120 : OUT STD_LOGIC_VECTOR (7 downto 0);
address121 : IN STD_LOGIC_VECTOR (7 downto 0);
ce121 : IN STD_LOGIC;
q121 : OUT STD_LOGIC_VECTOR (7 downto 0);
address122 : IN STD_LOGIC_VECTOR (7 downto 0);
ce122 : IN STD_LOGIC;
q122 : OUT STD_LOGIC_VECTOR (7 downto 0);
address123 : IN STD_LOGIC_VECTOR (7 downto 0);
ce123 : IN STD_LOGIC;
q123 : OUT STD_LOGIC_VECTOR (7 downto 0);
address124 : IN STD_LOGIC_VECTOR (7 downto 0);
ce124 : IN STD_LOGIC;
q124 : OUT STD_LOGIC_VECTOR (7 downto 0);
address125 : IN STD_LOGIC_VECTOR (7 downto 0);
ce125 : IN STD_LOGIC;
q125 : OUT STD_LOGIC_VECTOR (7 downto 0);
address126 : IN STD_LOGIC_VECTOR (7 downto 0);
ce126 : IN STD_LOGIC;
q126 : OUT STD_LOGIC_VECTOR (7 downto 0);
address127 : IN STD_LOGIC_VECTOR (7 downto 0);
ce127 : IN STD_LOGIC;
q127 : OUT STD_LOGIC_VECTOR (7 downto 0);
address128 : IN STD_LOGIC_VECTOR (7 downto 0);
ce128 : IN STD_LOGIC;
q128 : OUT STD_LOGIC_VECTOR (7 downto 0);
address129 : IN STD_LOGIC_VECTOR (7 downto 0);
ce129 : IN STD_LOGIC;
q129 : OUT STD_LOGIC_VECTOR (7 downto 0);
address130 : IN STD_LOGIC_VECTOR (7 downto 0);
ce130 : IN STD_LOGIC;
q130 : OUT STD_LOGIC_VECTOR (7 downto 0);
address131 : IN STD_LOGIC_VECTOR (7 downto 0);
ce131 : IN STD_LOGIC;
q131 : OUT STD_LOGIC_VECTOR (7 downto 0);
address132 : IN STD_LOGIC_VECTOR (7 downto 0);
ce132 : IN STD_LOGIC;
q132 : OUT STD_LOGIC_VECTOR (7 downto 0);
address133 : IN STD_LOGIC_VECTOR (7 downto 0);
ce133 : IN STD_LOGIC;
q133 : OUT STD_LOGIC_VECTOR (7 downto 0);
address134 : IN STD_LOGIC_VECTOR (7 downto 0);
ce134 : IN STD_LOGIC;
q134 : OUT STD_LOGIC_VECTOR (7 downto 0);
address135 : IN STD_LOGIC_VECTOR (7 downto 0);
ce135 : IN STD_LOGIC;
q135 : OUT STD_LOGIC_VECTOR (7 downto 0);
address136 : IN STD_LOGIC_VECTOR (7 downto 0);
ce136 : IN STD_LOGIC;
q136 : OUT STD_LOGIC_VECTOR (7 downto 0);
address137 : IN STD_LOGIC_VECTOR (7 downto 0);
ce137 : IN STD_LOGIC;
q137 : OUT STD_LOGIC_VECTOR (7 downto 0);
address138 : IN STD_LOGIC_VECTOR (7 downto 0);
ce138 : IN STD_LOGIC;
q138 : OUT STD_LOGIC_VECTOR (7 downto 0);
address139 : IN STD_LOGIC_VECTOR (7 downto 0);
ce139 : IN STD_LOGIC;
q139 : OUT STD_LOGIC_VECTOR (7 downto 0);
address140 : IN STD_LOGIC_VECTOR (7 downto 0);
ce140 : IN STD_LOGIC;
q140 : OUT STD_LOGIC_VECTOR (7 downto 0);
address141 : IN STD_LOGIC_VECTOR (7 downto 0);
ce141 : IN STD_LOGIC;
q141 : OUT STD_LOGIC_VECTOR (7 downto 0);
address142 : IN STD_LOGIC_VECTOR (7 downto 0);
ce142 : IN STD_LOGIC;
q142 : OUT STD_LOGIC_VECTOR (7 downto 0);
address143 : IN STD_LOGIC_VECTOR (7 downto 0);
ce143 : IN STD_LOGIC;
q143 : OUT STD_LOGIC_VECTOR (7 downto 0);
address144 : IN STD_LOGIC_VECTOR (7 downto 0);
ce144 : IN STD_LOGIC;
q144 : OUT STD_LOGIC_VECTOR (7 downto 0);
address145 : IN STD_LOGIC_VECTOR (7 downto 0);
ce145 : IN STD_LOGIC;
q145 : OUT STD_LOGIC_VECTOR (7 downto 0);
address146 : IN STD_LOGIC_VECTOR (7 downto 0);
ce146 : IN STD_LOGIC;
q146 : OUT STD_LOGIC_VECTOR (7 downto 0);
address147 : IN STD_LOGIC_VECTOR (7 downto 0);
ce147 : IN STD_LOGIC;
q147 : OUT STD_LOGIC_VECTOR (7 downto 0);
address148 : IN STD_LOGIC_VECTOR (7 downto 0);
ce148 : IN STD_LOGIC;
q148 : OUT STD_LOGIC_VECTOR (7 downto 0);
address149 : IN STD_LOGIC_VECTOR (7 downto 0);
ce149 : IN STD_LOGIC;
q149 : OUT STD_LOGIC_VECTOR (7 downto 0);
address150 : IN STD_LOGIC_VECTOR (7 downto 0);
ce150 : IN STD_LOGIC;
q150 : OUT STD_LOGIC_VECTOR (7 downto 0);
address151 : IN STD_LOGIC_VECTOR (7 downto 0);
ce151 : IN STD_LOGIC;
q151 : OUT STD_LOGIC_VECTOR (7 downto 0);
address152 : IN STD_LOGIC_VECTOR (7 downto 0);
ce152 : IN STD_LOGIC;
q152 : OUT STD_LOGIC_VECTOR (7 downto 0);
address153 : IN STD_LOGIC_VECTOR (7 downto 0);
ce153 : IN STD_LOGIC;
q153 : OUT STD_LOGIC_VECTOR (7 downto 0);
address154 : IN STD_LOGIC_VECTOR (7 downto 0);
ce154 : IN STD_LOGIC;
q154 : OUT STD_LOGIC_VECTOR (7 downto 0);
address155 : IN STD_LOGIC_VECTOR (7 downto 0);
ce155 : IN STD_LOGIC;
q155 : OUT STD_LOGIC_VECTOR (7 downto 0);
address156 : IN STD_LOGIC_VECTOR (7 downto 0);
ce156 : IN STD_LOGIC;
q156 : OUT STD_LOGIC_VECTOR (7 downto 0);
address157 : IN STD_LOGIC_VECTOR (7 downto 0);
ce157 : IN STD_LOGIC;
q157 : OUT STD_LOGIC_VECTOR (7 downto 0);
address158 : IN STD_LOGIC_VECTOR (7 downto 0);
ce158 : IN STD_LOGIC;
q158 : OUT STD_LOGIC_VECTOR (7 downto 0);
address159 : IN STD_LOGIC_VECTOR (7 downto 0);
ce159 : IN STD_LOGIC;
q159 : OUT STD_LOGIC_VECTOR (7 downto 0);
address160 : IN STD_LOGIC_VECTOR (7 downto 0);
ce160 : IN STD_LOGIC;
q160 : OUT STD_LOGIC_VECTOR (7 downto 0);
address161 : IN STD_LOGIC_VECTOR (7 downto 0);
ce161 : IN STD_LOGIC;
q161 : OUT STD_LOGIC_VECTOR (7 downto 0);
address162 : IN STD_LOGIC_VECTOR (7 downto 0);
ce162 : IN STD_LOGIC;
q162 : OUT STD_LOGIC_VECTOR (7 downto 0);
address163 : IN STD_LOGIC_VECTOR (7 downto 0);
ce163 : IN STD_LOGIC;
q163 : OUT STD_LOGIC_VECTOR (7 downto 0);
address164 : IN STD_LOGIC_VECTOR (7 downto 0);
ce164 : IN STD_LOGIC;
q164 : OUT STD_LOGIC_VECTOR (7 downto 0);
address165 : IN STD_LOGIC_VECTOR (7 downto 0);
ce165 : IN STD_LOGIC;
q165 : OUT STD_LOGIC_VECTOR (7 downto 0);
address166 : IN STD_LOGIC_VECTOR (7 downto 0);
ce166 : IN STD_LOGIC;
q166 : OUT STD_LOGIC_VECTOR (7 downto 0);
address167 : IN STD_LOGIC_VECTOR (7 downto 0);
ce167 : IN STD_LOGIC;
q167 : OUT STD_LOGIC_VECTOR (7 downto 0);
address168 : IN STD_LOGIC_VECTOR (7 downto 0);
ce168 : IN STD_LOGIC;
q168 : OUT STD_LOGIC_VECTOR (7 downto 0);
address169 : IN STD_LOGIC_VECTOR (7 downto 0);
ce169 : IN STD_LOGIC;
q169 : OUT STD_LOGIC_VECTOR (7 downto 0);
address170 : IN STD_LOGIC_VECTOR (7 downto 0);
ce170 : IN STD_LOGIC;
q170 : OUT STD_LOGIC_VECTOR (7 downto 0);
address171 : IN STD_LOGIC_VECTOR (7 downto 0);
ce171 : IN STD_LOGIC;
q171 : OUT STD_LOGIC_VECTOR (7 downto 0);
address172 : IN STD_LOGIC_VECTOR (7 downto 0);
ce172 : IN STD_LOGIC;
q172 : OUT STD_LOGIC_VECTOR (7 downto 0);
address173 : IN STD_LOGIC_VECTOR (7 downto 0);
ce173 : IN STD_LOGIC;
q173 : OUT STD_LOGIC_VECTOR (7 downto 0);
address174 : IN STD_LOGIC_VECTOR (7 downto 0);
ce174 : IN STD_LOGIC;
q174 : OUT STD_LOGIC_VECTOR (7 downto 0);
address175 : IN STD_LOGIC_VECTOR (7 downto 0);
ce175 : IN STD_LOGIC;
q175 : OUT STD_LOGIC_VECTOR (7 downto 0);
address176 : IN STD_LOGIC_VECTOR (7 downto 0);
ce176 : IN STD_LOGIC;
q176 : OUT STD_LOGIC_VECTOR (7 downto 0);
address177 : IN STD_LOGIC_VECTOR (7 downto 0);
ce177 : IN STD_LOGIC;
q177 : OUT STD_LOGIC_VECTOR (7 downto 0);
address178 : IN STD_LOGIC_VECTOR (7 downto 0);
ce178 : IN STD_LOGIC;
q178 : OUT STD_LOGIC_VECTOR (7 downto 0);
address179 : IN STD_LOGIC_VECTOR (7 downto 0);
ce179 : IN STD_LOGIC;
q179 : OUT STD_LOGIC_VECTOR (7 downto 0);
address180 : IN STD_LOGIC_VECTOR (7 downto 0);
ce180 : IN STD_LOGIC;
q180 : OUT STD_LOGIC_VECTOR (7 downto 0);
address181 : IN STD_LOGIC_VECTOR (7 downto 0);
ce181 : IN STD_LOGIC;
q181 : OUT STD_LOGIC_VECTOR (7 downto 0);
address182 : IN STD_LOGIC_VECTOR (7 downto 0);
ce182 : IN STD_LOGIC;
q182 : OUT STD_LOGIC_VECTOR (7 downto 0);
address183 : IN STD_LOGIC_VECTOR (7 downto 0);
ce183 : IN STD_LOGIC;
q183 : OUT STD_LOGIC_VECTOR (7 downto 0);
address184 : IN STD_LOGIC_VECTOR (7 downto 0);
ce184 : IN STD_LOGIC;
q184 : OUT STD_LOGIC_VECTOR (7 downto 0);
address185 : IN STD_LOGIC_VECTOR (7 downto 0);
ce185 : IN STD_LOGIC;
q185 : OUT STD_LOGIC_VECTOR (7 downto 0);
address186 : IN STD_LOGIC_VECTOR (7 downto 0);
ce186 : IN STD_LOGIC;
q186 : OUT STD_LOGIC_VECTOR (7 downto 0);
address187 : IN STD_LOGIC_VECTOR (7 downto 0);
ce187 : IN STD_LOGIC;
q187 : OUT STD_LOGIC_VECTOR (7 downto 0);
address188 : IN STD_LOGIC_VECTOR (7 downto 0);
ce188 : IN STD_LOGIC;
q188 : OUT STD_LOGIC_VECTOR (7 downto 0);
address189 : IN STD_LOGIC_VECTOR (7 downto 0);
ce189 : IN STD_LOGIC;
q189 : OUT STD_LOGIC_VECTOR (7 downto 0);
address190 : IN STD_LOGIC_VECTOR (7 downto 0);
ce190 : IN STD_LOGIC;
q190 : OUT STD_LOGIC_VECTOR (7 downto 0);
address191 : IN STD_LOGIC_VECTOR (7 downto 0);
ce191 : IN STD_LOGIC;
q191 : OUT STD_LOGIC_VECTOR (7 downto 0);
address192 : IN STD_LOGIC_VECTOR (7 downto 0);
ce192 : IN STD_LOGIC;
q192 : OUT STD_LOGIC_VECTOR (7 downto 0);
address193 : IN STD_LOGIC_VECTOR (7 downto 0);
ce193 : IN STD_LOGIC;
q193 : OUT STD_LOGIC_VECTOR (7 downto 0);
address194 : IN STD_LOGIC_VECTOR (7 downto 0);
ce194 : IN STD_LOGIC;
q194 : OUT STD_LOGIC_VECTOR (7 downto 0);
address195 : IN STD_LOGIC_VECTOR (7 downto 0);
ce195 : IN STD_LOGIC;
q195 : OUT STD_LOGIC_VECTOR (7 downto 0);
address196 : IN STD_LOGIC_VECTOR (7 downto 0);
ce196 : IN STD_LOGIC;
q196 : OUT STD_LOGIC_VECTOR (7 downto 0);
address197 : IN STD_LOGIC_VECTOR (7 downto 0);
ce197 : IN STD_LOGIC;
q197 : OUT STD_LOGIC_VECTOR (7 downto 0);
address198 : IN STD_LOGIC_VECTOR (7 downto 0);
ce198 : IN STD_LOGIC;
q198 : OUT STD_LOGIC_VECTOR (7 downto 0);
address199 : IN STD_LOGIC_VECTOR (7 downto 0);
ce199 : IN STD_LOGIC;
q199 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
sboxes_U : component aestest_sboxes
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => sboxes_address0,
ce0 => sboxes_ce0,
q0 => sboxes_q0,
address1 => sboxes_address1,
ce1 => sboxes_ce1,
q1 => sboxes_q1,
address2 => sboxes_address2,
ce2 => sboxes_ce2,
q2 => sboxes_q2,
address3 => sboxes_address3,
ce3 => sboxes_ce3,
q3 => sboxes_q3,
address4 => sboxes_address4,
ce4 => sboxes_ce4,
q4 => sboxes_q4,
address5 => sboxes_address5,
ce5 => sboxes_ce5,
q5 => sboxes_q5,
address6 => sboxes_address6,
ce6 => sboxes_ce6,
q6 => sboxes_q6,
address7 => sboxes_address7,
ce7 => sboxes_ce7,
q7 => sboxes_q7,
address8 => sboxes_address8,
ce8 => sboxes_ce8,
q8 => sboxes_q8,
address9 => sboxes_address9,
ce9 => sboxes_ce9,
q9 => sboxes_q9,
address10 => sboxes_address10,
ce10 => sboxes_ce10,
q10 => sboxes_q10,
address11 => sboxes_address11,
ce11 => sboxes_ce11,
q11 => sboxes_q11,
address12 => sboxes_address12,
ce12 => sboxes_ce12,
q12 => sboxes_q12,
address13 => sboxes_address13,
ce13 => sboxes_ce13,
q13 => sboxes_q13,
address14 => sboxes_address14,
ce14 => sboxes_ce14,
q14 => sboxes_q14,
address15 => sboxes_address15,
ce15 => sboxes_ce15,
q15 => sboxes_q15,
address16 => sboxes_address16,
ce16 => sboxes_ce16,
q16 => sboxes_q16,
address17 => sboxes_address17,
ce17 => sboxes_ce17,
q17 => sboxes_q17,
address18 => sboxes_address18,
ce18 => sboxes_ce18,
q18 => sboxes_q18,
address19 => sboxes_address19,
ce19 => sboxes_ce19,
q19 => sboxes_q19,
address20 => sboxes_address20,
ce20 => sboxes_ce20,
q20 => sboxes_q20,
address21 => sboxes_address21,
ce21 => sboxes_ce21,
q21 => sboxes_q21,
address22 => sboxes_address22,
ce22 => sboxes_ce22,
q22 => sboxes_q22,
address23 => sboxes_address23,
ce23 => sboxes_ce23,
q23 => sboxes_q23,
address24 => sboxes_address24,
ce24 => sboxes_ce24,
q24 => sboxes_q24,
address25 => sboxes_address25,
ce25 => sboxes_ce25,
q25 => sboxes_q25,
address26 => sboxes_address26,
ce26 => sboxes_ce26,
q26 => sboxes_q26,
address27 => sboxes_address27,
ce27 => sboxes_ce27,
q27 => sboxes_q27,
address28 => sboxes_address28,
ce28 => sboxes_ce28,
q28 => sboxes_q28,
address29 => sboxes_address29,
ce29 => sboxes_ce29,
q29 => sboxes_q29,
address30 => sboxes_address30,
ce30 => sboxes_ce30,
q30 => sboxes_q30,
address31 => sboxes_address31,
ce31 => sboxes_ce31,
q31 => sboxes_q31,
address32 => sboxes_address32,
ce32 => sboxes_ce32,
q32 => sboxes_q32,
address33 => sboxes_address33,
ce33 => sboxes_ce33,
q33 => sboxes_q33,
address34 => sboxes_address34,
ce34 => sboxes_ce34,
q34 => sboxes_q34,
address35 => sboxes_address35,
ce35 => sboxes_ce35,
q35 => sboxes_q35,
address36 => sboxes_address36,
ce36 => sboxes_ce36,
q36 => sboxes_q36,
address37 => sboxes_address37,
ce37 => sboxes_ce37,
q37 => sboxes_q37,
address38 => sboxes_address38,
ce38 => sboxes_ce38,
q38 => sboxes_q38,
address39 => sboxes_address39,
ce39 => sboxes_ce39,
q39 => sboxes_q39,
address40 => sboxes_address40,
ce40 => sboxes_ce40,
q40 => sboxes_q40,
address41 => sboxes_address41,
ce41 => sboxes_ce41,
q41 => sboxes_q41,
address42 => sboxes_address42,
ce42 => sboxes_ce42,
q42 => sboxes_q42,
address43 => sboxes_address43,
ce43 => sboxes_ce43,
q43 => sboxes_q43,
address44 => sboxes_address44,
ce44 => sboxes_ce44,
q44 => sboxes_q44,
address45 => sboxes_address45,
ce45 => sboxes_ce45,
q45 => sboxes_q45,
address46 => sboxes_address46,
ce46 => sboxes_ce46,
q46 => sboxes_q46,
address47 => sboxes_address47,
ce47 => sboxes_ce47,
q47 => sboxes_q47,
address48 => sboxes_address48,
ce48 => sboxes_ce48,
q48 => sboxes_q48,
address49 => sboxes_address49,
ce49 => sboxes_ce49,
q49 => sboxes_q49,
address50 => sboxes_address50,
ce50 => sboxes_ce50,
q50 => sboxes_q50,
address51 => sboxes_address51,
ce51 => sboxes_ce51,
q51 => sboxes_q51,
address52 => sboxes_address52,
ce52 => sboxes_ce52,
q52 => sboxes_q52,
address53 => sboxes_address53,
ce53 => sboxes_ce53,
q53 => sboxes_q53,
address54 => sboxes_address54,
ce54 => sboxes_ce54,
q54 => sboxes_q54,
address55 => sboxes_address55,
ce55 => sboxes_ce55,
q55 => sboxes_q55,
address56 => sboxes_address56,
ce56 => sboxes_ce56,
q56 => sboxes_q56,
address57 => sboxes_address57,
ce57 => sboxes_ce57,
q57 => sboxes_q57,
address58 => sboxes_address58,
ce58 => sboxes_ce58,
q58 => sboxes_q58,
address59 => sboxes_address59,
ce59 => sboxes_ce59,
q59 => sboxes_q59,
address60 => sboxes_address60,
ce60 => sboxes_ce60,
q60 => sboxes_q60,
address61 => sboxes_address61,
ce61 => sboxes_ce61,
q61 => sboxes_q61,
address62 => sboxes_address62,
ce62 => sboxes_ce62,
q62 => sboxes_q62,
address63 => sboxes_address63,
ce63 => sboxes_ce63,
q63 => sboxes_q63,
address64 => sboxes_address64,
ce64 => sboxes_ce64,
q64 => sboxes_q64,
address65 => sboxes_address65,
ce65 => sboxes_ce65,
q65 => sboxes_q65,
address66 => sboxes_address66,
ce66 => sboxes_ce66,
q66 => sboxes_q66,
address67 => sboxes_address67,
ce67 => sboxes_ce67,
q67 => sboxes_q67,
address68 => sboxes_address68,
ce68 => sboxes_ce68,
q68 => sboxes_q68,
address69 => sboxes_address69,
ce69 => sboxes_ce69,
q69 => sboxes_q69,
address70 => sboxes_address70,
ce70 => sboxes_ce70,
q70 => sboxes_q70,
address71 => sboxes_address71,
ce71 => sboxes_ce71,
q71 => sboxes_q71,
address72 => sboxes_address72,
ce72 => sboxes_ce72,
q72 => sboxes_q72,
address73 => sboxes_address73,
ce73 => sboxes_ce73,
q73 => sboxes_q73,
address74 => sboxes_address74,
ce74 => sboxes_ce74,
q74 => sboxes_q74,
address75 => sboxes_address75,
ce75 => sboxes_ce75,
q75 => sboxes_q75,
address76 => sboxes_address76,
ce76 => sboxes_ce76,
q76 => sboxes_q76,
address77 => sboxes_address77,
ce77 => sboxes_ce77,
q77 => sboxes_q77,
address78 => sboxes_address78,
ce78 => sboxes_ce78,
q78 => sboxes_q78,
address79 => sboxes_address79,
ce79 => sboxes_ce79,
q79 => sboxes_q79,
address80 => sboxes_address80,
ce80 => sboxes_ce80,
q80 => sboxes_q80,
address81 => sboxes_address81,
ce81 => sboxes_ce81,
q81 => sboxes_q81,
address82 => sboxes_address82,
ce82 => sboxes_ce82,
q82 => sboxes_q82,
address83 => sboxes_address83,
ce83 => sboxes_ce83,
q83 => sboxes_q83,
address84 => sboxes_address84,
ce84 => sboxes_ce84,
q84 => sboxes_q84,
address85 => sboxes_address85,
ce85 => sboxes_ce85,
q85 => sboxes_q85,
address86 => sboxes_address86,
ce86 => sboxes_ce86,
q86 => sboxes_q86,
address87 => sboxes_address87,
ce87 => sboxes_ce87,
q87 => sboxes_q87,
address88 => sboxes_address88,
ce88 => sboxes_ce88,
q88 => sboxes_q88,
address89 => sboxes_address89,
ce89 => sboxes_ce89,
q89 => sboxes_q89,
address90 => sboxes_address90,
ce90 => sboxes_ce90,
q90 => sboxes_q90,
address91 => sboxes_address91,
ce91 => sboxes_ce91,
q91 => sboxes_q91,
address92 => sboxes_address92,
ce92 => sboxes_ce92,
q92 => sboxes_q92,
address93 => sboxes_address93,
ce93 => sboxes_ce93,
q93 => sboxes_q93,
address94 => sboxes_address94,
ce94 => sboxes_ce94,
q94 => sboxes_q94,
address95 => sboxes_address95,
ce95 => sboxes_ce95,
q95 => sboxes_q95,
address96 => sboxes_address96,
ce96 => sboxes_ce96,
q96 => sboxes_q96,
address97 => sboxes_address97,
ce97 => sboxes_ce97,
q97 => sboxes_q97,
address98 => sboxes_address98,
ce98 => sboxes_ce98,
q98 => sboxes_q98,
address99 => sboxes_address99,
ce99 => sboxes_ce99,
q99 => sboxes_q99,
address100 => sboxes_address100,
ce100 => sboxes_ce100,
q100 => sboxes_q100,
address101 => sboxes_address101,
ce101 => sboxes_ce101,
q101 => sboxes_q101,
address102 => sboxes_address102,
ce102 => sboxes_ce102,
q102 => sboxes_q102,
address103 => sboxes_address103,
ce103 => sboxes_ce103,
q103 => sboxes_q103,
address104 => sboxes_address104,
ce104 => sboxes_ce104,
q104 => sboxes_q104,
address105 => sboxes_address105,
ce105 => sboxes_ce105,
q105 => sboxes_q105,
address106 => sboxes_address106,
ce106 => sboxes_ce106,
q106 => sboxes_q106,
address107 => sboxes_address107,
ce107 => sboxes_ce107,
q107 => sboxes_q107,
address108 => sboxes_address108,
ce108 => sboxes_ce108,
q108 => sboxes_q108,
address109 => sboxes_address109,
ce109 => sboxes_ce109,
q109 => sboxes_q109,
address110 => sboxes_address110,
ce110 => sboxes_ce110,
q110 => sboxes_q110,
address111 => sboxes_address111,
ce111 => sboxes_ce111,
q111 => sboxes_q111,
address112 => sboxes_address112,
ce112 => sboxes_ce112,
q112 => sboxes_q112,
address113 => sboxes_address113,
ce113 => sboxes_ce113,
q113 => sboxes_q113,
address114 => sboxes_address114,
ce114 => sboxes_ce114,
q114 => sboxes_q114,
address115 => sboxes_address115,
ce115 => sboxes_ce115,
q115 => sboxes_q115,
address116 => sboxes_address116,
ce116 => sboxes_ce116,
q116 => sboxes_q116,
address117 => sboxes_address117,
ce117 => sboxes_ce117,
q117 => sboxes_q117,
address118 => sboxes_address118,
ce118 => sboxes_ce118,
q118 => sboxes_q118,
address119 => sboxes_address119,
ce119 => sboxes_ce119,
q119 => sboxes_q119,
address120 => sboxes_address120,
ce120 => sboxes_ce120,
q120 => sboxes_q120,
address121 => sboxes_address121,
ce121 => sboxes_ce121,
q121 => sboxes_q121,
address122 => sboxes_address122,
ce122 => sboxes_ce122,
q122 => sboxes_q122,
address123 => sboxes_address123,
ce123 => sboxes_ce123,
q123 => sboxes_q123,
address124 => sboxes_address124,
ce124 => sboxes_ce124,
q124 => sboxes_q124,
address125 => sboxes_address125,
ce125 => sboxes_ce125,
q125 => sboxes_q125,
address126 => sboxes_address126,
ce126 => sboxes_ce126,
q126 => sboxes_q126,
address127 => sboxes_address127,
ce127 => sboxes_ce127,
q127 => sboxes_q127,
address128 => sboxes_address128,
ce128 => sboxes_ce128,
q128 => sboxes_q128,
address129 => sboxes_address129,
ce129 => sboxes_ce129,
q129 => sboxes_q129,
address130 => sboxes_address130,
ce130 => sboxes_ce130,
q130 => sboxes_q130,
address131 => sboxes_address131,
ce131 => sboxes_ce131,
q131 => sboxes_q131,
address132 => sboxes_address132,
ce132 => sboxes_ce132,
q132 => sboxes_q132,
address133 => sboxes_address133,
ce133 => sboxes_ce133,
q133 => sboxes_q133,
address134 => sboxes_address134,
ce134 => sboxes_ce134,
q134 => sboxes_q134,
address135 => sboxes_address135,
ce135 => sboxes_ce135,
q135 => sboxes_q135,
address136 => sboxes_address136,
ce136 => sboxes_ce136,
q136 => sboxes_q136,
address137 => sboxes_address137,
ce137 => sboxes_ce137,
q137 => sboxes_q137,
address138 => sboxes_address138,
ce138 => sboxes_ce138,
q138 => sboxes_q138,
address139 => sboxes_address139,
ce139 => sboxes_ce139,
q139 => sboxes_q139,
address140 => sboxes_address140,
ce140 => sboxes_ce140,
q140 => sboxes_q140,
address141 => sboxes_address141,
ce141 => sboxes_ce141,
q141 => sboxes_q141,
address142 => sboxes_address142,
ce142 => sboxes_ce142,
q142 => sboxes_q142,
address143 => sboxes_address143,
ce143 => sboxes_ce143,
q143 => sboxes_q143,
address144 => sboxes_address144,
ce144 => sboxes_ce144,
q144 => sboxes_q144,
address145 => sboxes_address145,
ce145 => sboxes_ce145,
q145 => sboxes_q145,
address146 => sboxes_address146,
ce146 => sboxes_ce146,
q146 => sboxes_q146,
address147 => sboxes_address147,
ce147 => sboxes_ce147,
q147 => sboxes_q147,
address148 => sboxes_address148,
ce148 => sboxes_ce148,
q148 => sboxes_q148,
address149 => sboxes_address149,
ce149 => sboxes_ce149,
q149 => sboxes_q149,
address150 => sboxes_address150,
ce150 => sboxes_ce150,
q150 => sboxes_q150,
address151 => sboxes_address151,
ce151 => sboxes_ce151,
q151 => sboxes_q151,
address152 => sboxes_address152,
ce152 => sboxes_ce152,
q152 => sboxes_q152,
address153 => sboxes_address153,
ce153 => sboxes_ce153,
q153 => sboxes_q153,
address154 => sboxes_address154,
ce154 => sboxes_ce154,
q154 => sboxes_q154,
address155 => sboxes_address155,
ce155 => sboxes_ce155,
q155 => sboxes_q155,
address156 => sboxes_address156,
ce156 => sboxes_ce156,
q156 => sboxes_q156,
address157 => sboxes_address157,
ce157 => sboxes_ce157,
q157 => sboxes_q157,
address158 => sboxes_address158,
ce158 => sboxes_ce158,
q158 => sboxes_q158,
address159 => sboxes_address159,
ce159 => sboxes_ce159,
q159 => sboxes_q159,
address160 => sboxes_address160,
ce160 => sboxes_ce160,
q160 => sboxes_q160,
address161 => sboxes_address161,
ce161 => sboxes_ce161,
q161 => sboxes_q161,
address162 => sboxes_address162,
ce162 => sboxes_ce162,
q162 => sboxes_q162,
address163 => sboxes_address163,
ce163 => sboxes_ce163,
q163 => sboxes_q163,
address164 => sboxes_address164,
ce164 => sboxes_ce164,
q164 => sboxes_q164,
address165 => sboxes_address165,
ce165 => sboxes_ce165,
q165 => sboxes_q165,
address166 => sboxes_address166,
ce166 => sboxes_ce166,
q166 => sboxes_q166,
address167 => sboxes_address167,
ce167 => sboxes_ce167,
q167 => sboxes_q167,
address168 => sboxes_address168,
ce168 => sboxes_ce168,
q168 => sboxes_q168,
address169 => sboxes_address169,
ce169 => sboxes_ce169,
q169 => sboxes_q169,
address170 => sboxes_address170,
ce170 => sboxes_ce170,
q170 => sboxes_q170,
address171 => sboxes_address171,
ce171 => sboxes_ce171,
q171 => sboxes_q171,
address172 => sboxes_address172,
ce172 => sboxes_ce172,
q172 => sboxes_q172,
address173 => sboxes_address173,
ce173 => sboxes_ce173,
q173 => sboxes_q173,
address174 => sboxes_address174,
ce174 => sboxes_ce174,
q174 => sboxes_q174,
address175 => sboxes_address175,
ce175 => sboxes_ce175,
q175 => sboxes_q175,
address176 => sboxes_address176,
ce176 => sboxes_ce176,
q176 => sboxes_q176,
address177 => sboxes_address177,
ce177 => sboxes_ce177,
q177 => sboxes_q177,
address178 => sboxes_address178,
ce178 => sboxes_ce178,
q178 => sboxes_q178,
address179 => sboxes_address179,
ce179 => sboxes_ce179,
q179 => sboxes_q179,
address180 => sboxes_address180,
ce180 => sboxes_ce180,
q180 => sboxes_q180,
address181 => sboxes_address181,
ce181 => sboxes_ce181,
q181 => sboxes_q181,
address182 => sboxes_address182,
ce182 => sboxes_ce182,
q182 => sboxes_q182,
address183 => sboxes_address183,
ce183 => sboxes_ce183,
q183 => sboxes_q183,
address184 => sboxes_address184,
ce184 => sboxes_ce184,
q184 => sboxes_q184,
address185 => sboxes_address185,
ce185 => sboxes_ce185,
q185 => sboxes_q185,
address186 => sboxes_address186,
ce186 => sboxes_ce186,
q186 => sboxes_q186,
address187 => sboxes_address187,
ce187 => sboxes_ce187,
q187 => sboxes_q187,
address188 => sboxes_address188,
ce188 => sboxes_ce188,
q188 => sboxes_q188,
address189 => sboxes_address189,
ce189 => sboxes_ce189,
q189 => sboxes_q189,
address190 => sboxes_address190,
ce190 => sboxes_ce190,
q190 => sboxes_q190,
address191 => sboxes_address191,
ce191 => sboxes_ce191,
q191 => sboxes_q191,
address192 => sboxes_address192,
ce192 => sboxes_ce192,
q192 => sboxes_q192,
address193 => sboxes_address193,
ce193 => sboxes_ce193,
q193 => sboxes_q193,
address194 => sboxes_address194,
ce194 => sboxes_ce194,
q194 => sboxes_q194,
address195 => sboxes_address195,
ce195 => sboxes_ce195,
q195 => sboxes_q195,
address196 => sboxes_address196,
ce196 => sboxes_ce196,
q196 => sboxes_q196,
address197 => sboxes_address197,
ce197 => sboxes_ce197,
q197 => sboxes_q197,
address198 => sboxes_address198,
ce198 => sboxes_ce198,
q198 => sboxes_q198,
address199 => sboxes_address199,
ce199 => sboxes_ce199,
q199 => sboxes_q199);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
ap_reg_pp0_iter1_p_Result_1_11_reg_12485 <= p_Result_1_11_reg_12485;
ap_reg_pp0_iter1_p_Result_1_12_reg_12492 <= p_Result_1_12_reg_12492;
ap_reg_pp0_iter1_p_Result_1_13_reg_12499 <= p_Result_1_13_reg_12499;
ap_reg_pp0_iter1_p_Result_1_4_reg_12441 <= p_Result_1_4_reg_12441;
ap_reg_pp0_iter1_p_Result_1_5_reg_12447 <= p_Result_1_5_reg_12447;
ap_reg_pp0_iter1_p_Result_1_6_reg_12453 <= p_Result_1_6_reg_12453;
ap_reg_pp0_iter1_p_Result_1_7_reg_12459 <= p_Result_1_7_reg_12459;
ap_reg_pp0_iter1_tmp_100_reg_12506 <= tmp_100_reg_12506;
p_Result_1_10_reg_12480 <= key_V_read(39 downto 32);
p_Result_1_11_reg_12485 <= key_V_read(31 downto 24);
p_Result_1_12_reg_12492 <= key_V_read(23 downto 16);
p_Result_1_13_reg_12499 <= key_V_read(15 downto 8);
p_Result_1_1_reg_12426 <= key_V_read(119 downto 112);
p_Result_1_2_reg_12431 <= key_V_read(111 downto 104);
p_Result_1_3_reg_12436 <= key_V_read(103 downto 96);
p_Result_1_4_reg_12441 <= key_V_read(95 downto 88);
p_Result_1_5_reg_12447 <= key_V_read(87 downto 80);
p_Result_1_6_reg_12453 <= key_V_read(79 downto 72);
p_Result_1_7_reg_12459 <= key_V_read(71 downto 64);
p_Result_1_8_reg_12465 <= key_V_read(63 downto 56);
p_Result_1_9_reg_12470 <= key_V_read(55 downto 48);
p_Result_1_reg_12421 <= key_V_read(127 downto 120);
p_Result_1_s_reg_12475 <= key_V_read(47 downto 40);
tmp_100_reg_12506 <= tmp_100_fu_2625_p1;
tmp_65_reg_12613 <= tmp_65_fu_3422_p2;
tmp_66_reg_12618 <= tmp_66_fu_3428_p2;
tmp_67_reg_12623 <= tmp_67_fu_3433_p2;
tmp_68_reg_12628 <= tmp_68_fu_3438_p2;
tmp_73_reg_12633 <= tmp_73_fu_3463_p2;
tmp_74_reg_12639 <= tmp_74_fu_3468_p2;
tmp_75_reg_12645 <= tmp_75_fu_3473_p2;
tmp_76_reg_12651 <= tmp_76_fu_3478_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
ap_reg_pp0_iter2_p_Result_1_11_reg_12485 <= ap_reg_pp0_iter1_p_Result_1_11_reg_12485;
ap_reg_pp0_iter2_p_Result_1_12_reg_12492 <= ap_reg_pp0_iter1_p_Result_1_12_reg_12492;
ap_reg_pp0_iter2_p_Result_1_13_reg_12499 <= ap_reg_pp0_iter1_p_Result_1_13_reg_12499;
ap_reg_pp0_iter2_tmp_100_reg_12506 <= ap_reg_pp0_iter1_tmp_100_reg_12506;
ap_reg_pp0_iter2_tmp_73_reg_12633 <= tmp_73_reg_12633;
ap_reg_pp0_iter2_tmp_74_reg_12639 <= tmp_74_reg_12639;
ap_reg_pp0_iter2_tmp_75_reg_12645 <= tmp_75_reg_12645;
ap_reg_pp0_iter2_tmp_76_reg_12651 <= tmp_76_reg_12651;
ap_reg_pp0_iter3_p_Result_1_11_reg_12485 <= ap_reg_pp0_iter2_p_Result_1_11_reg_12485;
ap_reg_pp0_iter3_p_Result_1_12_reg_12492 <= ap_reg_pp0_iter2_p_Result_1_12_reg_12492;
ap_reg_pp0_iter3_p_Result_1_13_reg_12499 <= ap_reg_pp0_iter2_p_Result_1_13_reg_12499;
ap_reg_pp0_iter3_tmp_100_reg_12506 <= ap_reg_pp0_iter2_tmp_100_reg_12506;
ap_reg_pp0_iter3_tmp_69_1_reg_12777 <= tmp_69_1_reg_12777;
ap_reg_pp0_iter3_tmp_70_1_reg_12783 <= tmp_70_1_reg_12783;
ap_reg_pp0_iter3_tmp_71_1_reg_12789 <= tmp_71_1_reg_12789;
ap_reg_pp0_iter3_tmp_72_1_reg_12795 <= tmp_72_1_reg_12795;
ap_reg_pp0_iter4_tmp_73_2_reg_12941 <= tmp_73_2_reg_12941;
ap_reg_pp0_iter4_tmp_74_2_reg_12947 <= tmp_74_2_reg_12947;
ap_reg_pp0_iter4_tmp_75_2_reg_12953 <= tmp_75_2_reg_12953;
ap_reg_pp0_iter4_tmp_76_2_reg_12959 <= tmp_76_2_reg_12959;
ap_reg_pp0_iter5_tmp_69_3_reg_13085 <= tmp_69_3_reg_13085;
ap_reg_pp0_iter5_tmp_70_3_reg_13091 <= tmp_70_3_reg_13091;
ap_reg_pp0_iter5_tmp_71_3_reg_13097 <= tmp_71_3_reg_13097;
ap_reg_pp0_iter5_tmp_72_3_reg_13103 <= tmp_72_3_reg_13103;
ap_reg_pp0_iter5_tmp_77_3_reg_13109 <= tmp_77_3_reg_13109;
ap_reg_pp0_iter5_tmp_78_3_reg_13116 <= tmp_78_3_reg_13116;
ap_reg_pp0_iter5_tmp_79_3_reg_13123 <= tmp_79_3_reg_13123;
ap_reg_pp0_iter5_tmp_80_3_reg_13130 <= tmp_80_3_reg_13130;
ap_reg_pp0_iter6_tmp_73_4_reg_13257 <= tmp_73_4_reg_13257;
ap_reg_pp0_iter6_tmp_74_4_reg_13263 <= tmp_74_4_reg_13263;
ap_reg_pp0_iter6_tmp_75_4_reg_13269 <= tmp_75_4_reg_13269;
ap_reg_pp0_iter6_tmp_76_4_reg_13275 <= tmp_76_4_reg_13275;
ap_reg_pp0_iter6_tmp_77_3_reg_13109 <= ap_reg_pp0_iter5_tmp_77_3_reg_13109;
ap_reg_pp0_iter6_tmp_78_3_reg_13116 <= ap_reg_pp0_iter5_tmp_78_3_reg_13116;
ap_reg_pp0_iter6_tmp_79_3_reg_13123 <= ap_reg_pp0_iter5_tmp_79_3_reg_13123;
ap_reg_pp0_iter6_tmp_80_3_reg_13130 <= ap_reg_pp0_iter5_tmp_80_3_reg_13130;
ap_reg_pp0_iter7_tmp_69_5_reg_13401 <= tmp_69_5_reg_13401;
ap_reg_pp0_iter7_tmp_70_5_reg_13407 <= tmp_70_5_reg_13407;
ap_reg_pp0_iter7_tmp_71_5_reg_13413 <= tmp_71_5_reg_13413;
ap_reg_pp0_iter7_tmp_72_5_reg_13419 <= tmp_72_5_reg_13419;
ap_reg_pp0_iter7_tmp_77_3_reg_13109 <= ap_reg_pp0_iter6_tmp_77_3_reg_13109;
ap_reg_pp0_iter7_tmp_78_3_reg_13116 <= ap_reg_pp0_iter6_tmp_78_3_reg_13116;
ap_reg_pp0_iter7_tmp_79_3_reg_13123 <= ap_reg_pp0_iter6_tmp_79_3_reg_13123;
ap_reg_pp0_iter7_tmp_80_3_reg_13130 <= ap_reg_pp0_iter6_tmp_80_3_reg_13130;
ap_reg_pp0_iter8_tmp_73_6_reg_13565 <= tmp_73_6_reg_13565;
ap_reg_pp0_iter8_tmp_74_6_reg_13571 <= tmp_74_6_reg_13571;
ap_reg_pp0_iter8_tmp_75_6_reg_13577 <= tmp_75_6_reg_13577;
ap_reg_pp0_iter8_tmp_76_6_reg_13583 <= tmp_76_6_reg_13583;
ap_reg_pp0_iter9_tmp_69_7_reg_13709 <= tmp_69_7_reg_13709;
ap_reg_pp0_iter9_tmp_70_7_reg_13715 <= tmp_70_7_reg_13715;
ap_reg_pp0_iter9_tmp_71_7_reg_13721 <= tmp_71_7_reg_13721;
ap_reg_pp0_iter9_tmp_72_7_reg_13727 <= tmp_72_7_reg_13727;
ap_reg_pp0_iter9_tmp_77_7_reg_13733 <= tmp_77_7_reg_13733;
ap_reg_pp0_iter9_tmp_78_7_reg_13739 <= tmp_78_7_reg_13739;
ap_reg_pp0_iter9_tmp_79_7_reg_13745 <= tmp_79_7_reg_13745;
ap_reg_pp0_iter9_tmp_80_7_reg_13751 <= tmp_80_7_reg_13751;
tmp_65_1_reg_12757 <= tmp_65_1_fu_4465_p2;
tmp_65_2_reg_12921 <= tmp_65_2_fu_5506_p2;
tmp_65_3_reg_13065 <= tmp_65_3_fu_6549_p2;
tmp_65_4_reg_13237 <= tmp_65_4_fu_7590_p2;
tmp_65_5_reg_13381 <= tmp_65_5_fu_8633_p2;
tmp_65_6_reg_13545 <= tmp_65_6_fu_9674_p2;
tmp_65_7_reg_13689 <= tmp_65_7_fu_10717_p2;
tmp_65_8_reg_13857 <= tmp_65_8_fu_11758_p2;
tmp_66_1_reg_12762 <= tmp_66_1_fu_4470_p2;
tmp_66_2_reg_12926 <= tmp_66_2_fu_5512_p2;
tmp_66_3_reg_13070 <= tmp_66_3_fu_6554_p2;
tmp_66_4_reg_13242 <= tmp_66_4_fu_7596_p2;
tmp_66_5_reg_13386 <= tmp_66_5_fu_8638_p2;
tmp_66_6_reg_13550 <= tmp_66_6_fu_9680_p2;
tmp_66_7_reg_13694 <= tmp_66_7_fu_10722_p2;
tmp_66_8_reg_13862 <= tmp_66_8_fu_11764_p2;
tmp_67_1_reg_12767 <= tmp_67_1_fu_4475_p2;
tmp_67_2_reg_12931 <= tmp_67_2_fu_5517_p2;
tmp_67_3_reg_13075 <= tmp_67_3_fu_6559_p2;
tmp_67_4_reg_13247 <= tmp_67_4_fu_7601_p2;
tmp_67_5_reg_13391 <= tmp_67_5_fu_8643_p2;
tmp_67_6_reg_13555 <= tmp_67_6_fu_9685_p2;
tmp_67_7_reg_13699 <= tmp_67_7_fu_10727_p2;
tmp_67_8_reg_13867 <= tmp_67_8_fu_11769_p2;
tmp_68_1_reg_12772 <= tmp_68_1_fu_4480_p2;
tmp_68_2_reg_12936 <= tmp_68_2_fu_5522_p2;
tmp_68_3_reg_13080 <= tmp_68_3_fu_6564_p2;
tmp_68_4_reg_13252 <= tmp_68_4_fu_7606_p2;
tmp_68_5_reg_13396 <= tmp_68_5_fu_8648_p2;
tmp_68_6_reg_13560 <= tmp_68_6_fu_9690_p2;
tmp_68_7_reg_13704 <= tmp_68_7_fu_10732_p2;
tmp_68_8_reg_13872 <= tmp_68_8_fu_11774_p2;
tmp_69_1_reg_12777 <= tmp_69_1_fu_4485_p2;
tmp_69_3_reg_13085 <= tmp_69_3_fu_6569_p2;
tmp_69_5_reg_13401 <= tmp_69_5_fu_8653_p2;
tmp_69_7_reg_13709 <= tmp_69_7_fu_10737_p2;
tmp_70_1_reg_12783 <= tmp_70_1_fu_4490_p2;
tmp_70_3_reg_13091 <= tmp_70_3_fu_6574_p2;
tmp_70_5_reg_13407 <= tmp_70_5_fu_8658_p2;
tmp_70_7_reg_13715 <= tmp_70_7_fu_10742_p2;
tmp_71_1_reg_12789 <= tmp_71_1_fu_4495_p2;
tmp_71_3_reg_13097 <= tmp_71_3_fu_6579_p2;
tmp_71_5_reg_13413 <= tmp_71_5_fu_8663_p2;
tmp_71_7_reg_13721 <= tmp_71_7_fu_10747_p2;
tmp_72_1_reg_12795 <= tmp_72_1_fu_4500_p2;
tmp_72_3_reg_13103 <= tmp_72_3_fu_6584_p2;
tmp_72_5_reg_13419 <= tmp_72_5_fu_8668_p2;
tmp_72_7_reg_13727 <= tmp_72_7_fu_10752_p2;
tmp_73_2_reg_12941 <= tmp_73_2_fu_5527_p2;
tmp_73_4_reg_13257 <= tmp_73_4_fu_7611_p2;
tmp_73_6_reg_13565 <= tmp_73_6_fu_9695_p2;
tmp_73_8_reg_13877 <= tmp_73_8_fu_11779_p2;
tmp_74_2_reg_12947 <= tmp_74_2_fu_5532_p2;
tmp_74_4_reg_13263 <= tmp_74_4_fu_7616_p2;
tmp_74_6_reg_13571 <= tmp_74_6_fu_9700_p2;
tmp_74_8_reg_13882 <= tmp_74_8_fu_11784_p2;
tmp_75_2_reg_12953 <= tmp_75_2_fu_5537_p2;
tmp_75_4_reg_13269 <= tmp_75_4_fu_7621_p2;
tmp_75_6_reg_13577 <= tmp_75_6_fu_9705_p2;
tmp_75_8_reg_13887 <= tmp_75_8_fu_11789_p2;
tmp_76_2_reg_12959 <= tmp_76_2_fu_5542_p2;
tmp_76_4_reg_13275 <= tmp_76_4_fu_7626_p2;
tmp_76_6_reg_13583 <= tmp_76_6_fu_9710_p2;
tmp_76_8_reg_13892 <= tmp_76_8_fu_11794_p2;
tmp_77_1_reg_12801 <= tmp_77_1_fu_4505_p2;
tmp_77_3_reg_13109 <= tmp_77_3_fu_6589_p2;
tmp_77_5_reg_13425 <= tmp_77_5_fu_8673_p2;
tmp_77_7_reg_13733 <= tmp_77_7_fu_10757_p2;
tmp_78_1_reg_12806 <= tmp_78_1_fu_4510_p2;
tmp_78_3_reg_13116 <= tmp_78_3_fu_6594_p2;
tmp_78_5_reg_13430 <= tmp_78_5_fu_8678_p2;
tmp_78_7_reg_13739 <= tmp_78_7_fu_10762_p2;
tmp_79_1_reg_12811 <= tmp_79_1_fu_4515_p2;
tmp_79_3_reg_13123 <= tmp_79_3_fu_6599_p2;
tmp_79_5_reg_13435 <= tmp_79_5_fu_8683_p2;
tmp_79_7_reg_13745 <= tmp_79_7_fu_10767_p2;
tmp_80_1_reg_12816 <= tmp_80_1_fu_4520_p2;
tmp_80_3_reg_13130 <= tmp_80_3_fu_6604_p2;
tmp_80_5_reg_13440 <= tmp_80_5_fu_8688_p2;
tmp_80_7_reg_13751 <= tmp_80_7_fu_10772_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_reset_idle_pp0, ap_reset_start_pp0)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_start));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_ce)
begin
ap_block_pp0_stage0_flag00011011 <= (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_start)) or (ap_ce = ap_const_logic_0));
end process;
ap_block_state10_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state2_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter10, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter10)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0 <= ap_start;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter10))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to9_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9))) then
ap_idle_pp0_0to9 <= ap_const_logic_1;
else
ap_idle_pp0_0to9 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to9)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to9))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_reset_start_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to9)
begin
if (((ap_const_logic_1 = ap_idle_pp0_0to9) and (ap_const_logic_1 = ap_start))) then
ap_reset_start_pp0 <= ap_const_logic_1;
else
ap_reset_start_pp0 <= ap_const_logic_0;
end if;
end process;
ap_return <= (((((((((((((((tmp_38_fu_12234_p2 & tmp_38_1_fu_12245_p2) & tmp_38_2_fu_12256_p2) & tmp_38_3_fu_12267_p2) & tmp_38_4_fu_12273_p2) & tmp_38_5_fu_12279_p2) & tmp_38_6_fu_12285_p2) & tmp_38_7_fu_12291_p2) & tmp_38_8_fu_12302_p2) & tmp_38_9_fu_12313_p2) & tmp_38_s_fu_12324_p2) & tmp_38_10_fu_12335_p2) & tmp_38_11_fu_12346_p2) & tmp_38_12_fu_12357_p2) & tmp_38_13_fu_12368_p2) & tmp_38_14_fu_12379_p2);
e_0_1_fu_2985_p2 <= (sboxes_q3 xor tmp_47_0_1_fu_2979_p2);
e_0_2_fu_3133_p2 <= (sboxes_q7 xor tmp_47_0_2_fu_3127_p2);
e_0_3_fu_3281_p2 <= (sboxes_q11 xor tmp_47_0_3_fu_3275_p2);
e_1_1_fu_4027_p2 <= (sboxes_q23 xor tmp_47_1_1_fu_4021_p2);
e_1_2_fu_4175_p2 <= (sboxes_q27 xor tmp_47_1_2_fu_4169_p2);
e_1_3_fu_4323_p2 <= (sboxes_q31 xor tmp_47_1_3_fu_4317_p2);
e_1_fu_3879_p2 <= (sboxes_q35 xor tmp_47_1_fu_3873_p2);
e_2_1_fu_5069_p2 <= (sboxes_q43 xor tmp_47_2_1_fu_5063_p2);
e_2_2_fu_5217_p2 <= (sboxes_q47 xor tmp_47_2_2_fu_5211_p2);
e_2_3_fu_5365_p2 <= (sboxes_q51 xor tmp_47_2_3_fu_5359_p2);
e_2_fu_4921_p2 <= (sboxes_q55 xor tmp_47_2_fu_4915_p2);
e_3_1_fu_6111_p2 <= (sboxes_q63 xor tmp_47_3_1_fu_6105_p2);
e_3_2_fu_6259_p2 <= (sboxes_q67 xor tmp_47_3_2_fu_6253_p2);
e_3_3_fu_6407_p2 <= (sboxes_q71 xor tmp_47_3_3_fu_6401_p2);
e_3_fu_5963_p2 <= (sboxes_q75 xor tmp_47_3_fu_5957_p2);
e_4_1_fu_7153_p2 <= (sboxes_q83 xor tmp_47_4_1_fu_7147_p2);
e_4_2_fu_7301_p2 <= (sboxes_q87 xor tmp_47_4_2_fu_7295_p2);
e_4_3_fu_7449_p2 <= (sboxes_q91 xor tmp_47_4_3_fu_7443_p2);
e_4_fu_7005_p2 <= (sboxes_q95 xor tmp_47_4_fu_6999_p2);
e_5_1_fu_8195_p2 <= (sboxes_q103 xor tmp_47_5_1_fu_8189_p2);
e_5_2_fu_8343_p2 <= (sboxes_q107 xor tmp_47_5_2_fu_8337_p2);
e_5_3_fu_8491_p2 <= (sboxes_q111 xor tmp_47_5_3_fu_8485_p2);
e_5_fu_8047_p2 <= (sboxes_q115 xor tmp_47_5_fu_8041_p2);
e_6_1_fu_9237_p2 <= (sboxes_q123 xor tmp_47_6_1_fu_9231_p2);
e_6_2_fu_9385_p2 <= (sboxes_q127 xor tmp_47_6_2_fu_9379_p2);
e_6_3_fu_9533_p2 <= (sboxes_q131 xor tmp_47_6_3_fu_9527_p2);
e_6_fu_9089_p2 <= (sboxes_q135 xor tmp_47_6_fu_9083_p2);
e_7_1_fu_10279_p2 <= (sboxes_q143 xor tmp_47_7_1_fu_10273_p2);
e_7_2_fu_10427_p2 <= (sboxes_q147 xor tmp_47_7_2_fu_10421_p2);
e_7_3_fu_10575_p2 <= (sboxes_q151 xor tmp_47_7_3_fu_10569_p2);
e_7_fu_10131_p2 <= (sboxes_q155 xor tmp_47_7_fu_10125_p2);
e_8_1_fu_11321_p2 <= (sboxes_q163 xor tmp_47_8_1_fu_11315_p2);
e_8_2_fu_11469_p2 <= (sboxes_q167 xor tmp_47_8_2_fu_11463_p2);
e_8_3_fu_11617_p2 <= (sboxes_q171 xor tmp_47_8_3_fu_11611_p2);
e_8_fu_11173_p2 <= (sboxes_q175 xor tmp_47_8_fu_11167_p2);
e_fu_2837_p2 <= (sboxes_q15 xor tmp_47_fu_2831_p2);
p_Result_10_fu_2521_p4 <= inptext_V_read(47 downto 40);
p_Result_11_fu_2541_p4 <= inptext_V_read(39 downto 32);
p_Result_12_fu_2561_p4 <= inptext_V_read(31 downto 24);
p_Result_13_fu_2581_p4 <= inptext_V_read(23 downto 16);
p_Result_14_fu_2601_p4 <= inptext_V_read(15 downto 8);
p_Result_1_10_fu_2551_p4 <= key_V_read(39 downto 32);
p_Result_1_11_fu_2571_p4 <= key_V_read(31 downto 24);
p_Result_1_12_fu_2591_p4 <= key_V_read(23 downto 16);
p_Result_1_13_fu_2611_p4 <= key_V_read(15 downto 8);
p_Result_1_1_fu_2351_p4 <= key_V_read(119 downto 112);
p_Result_1_2_fu_2371_p4 <= key_V_read(111 downto 104);
p_Result_1_3_fu_2391_p4 <= key_V_read(103 downto 96);
p_Result_1_4_fu_2411_p4 <= key_V_read(95 downto 88);
p_Result_1_5_fu_2431_p4 <= key_V_read(87 downto 80);
p_Result_1_6_fu_2451_p4 <= key_V_read(79 downto 72);
p_Result_1_7_fu_2471_p4 <= key_V_read(71 downto 64);
p_Result_1_8_fu_2491_p4 <= key_V_read(63 downto 56);
p_Result_1_9_fu_2511_p4 <= key_V_read(55 downto 48);
p_Result_1_fu_2331_p4 <= key_V_read(127 downto 120);
p_Result_1_s_fu_2531_p4 <= key_V_read(47 downto 40);
p_Result_2_fu_2361_p4 <= inptext_V_read(111 downto 104);
p_Result_3_fu_2381_p4 <= inptext_V_read(103 downto 96);
p_Result_4_fu_2401_p4 <= inptext_V_read(95 downto 88);
p_Result_5_fu_2421_p4 <= inptext_V_read(87 downto 80);
p_Result_6_fu_2441_p4 <= inptext_V_read(79 downto 72);
p_Result_7_fu_2461_p4 <= inptext_V_read(71 downto 64);
p_Result_8_fu_2481_p4 <= inptext_V_read(63 downto 56);
p_Result_9_fu_2501_p4 <= inptext_V_read(55 downto 48);
p_Result_s_39_fu_2341_p4 <= inptext_V_read(119 downto 112);
p_Result_s_fu_2321_p4 <= inptext_V_read(127 downto 120);
rv_10_0_1_fu_3107_p2 <= (tmp_115_fu_3093_p2 xor ap_const_lv8_1B);
rv_10_0_2_fu_3255_p2 <= (tmp_123_fu_3241_p2 xor ap_const_lv8_1B);
rv_10_0_3_fu_3403_p2 <= (tmp_131_fu_3389_p2 xor ap_const_lv8_1B);
rv_10_1_1_fu_4149_p2 <= (tmp_147_fu_4135_p2 xor ap_const_lv8_1B);
rv_10_1_2_fu_4297_p2 <= (tmp_155_fu_4283_p2 xor ap_const_lv8_1B);
rv_10_1_3_fu_4445_p2 <= (tmp_163_fu_4431_p2 xor ap_const_lv8_1B);
rv_10_1_fu_4001_p2 <= (tmp_139_fu_3987_p2 xor ap_const_lv8_1B);
rv_10_2_1_fu_5191_p2 <= (tmp_179_fu_5177_p2 xor ap_const_lv8_1B);
rv_10_2_2_fu_5339_p2 <= (tmp_187_fu_5325_p2 xor ap_const_lv8_1B);
rv_10_2_3_fu_5487_p2 <= (tmp_195_fu_5473_p2 xor ap_const_lv8_1B);
rv_10_2_fu_5043_p2 <= (tmp_171_fu_5029_p2 xor ap_const_lv8_1B);
rv_10_3_1_fu_6233_p2 <= (tmp_211_fu_6219_p2 xor ap_const_lv8_1B);
rv_10_3_2_fu_6381_p2 <= (tmp_219_fu_6367_p2 xor ap_const_lv8_1B);
rv_10_3_3_fu_6529_p2 <= (tmp_227_fu_6515_p2 xor ap_const_lv8_1B);
rv_10_3_fu_6085_p2 <= (tmp_203_fu_6071_p2 xor ap_const_lv8_1B);
rv_10_4_1_fu_7275_p2 <= (tmp_243_fu_7261_p2 xor ap_const_lv8_1B);
rv_10_4_2_fu_7423_p2 <= (tmp_251_fu_7409_p2 xor ap_const_lv8_1B);
rv_10_4_3_fu_7571_p2 <= (tmp_259_fu_7557_p2 xor ap_const_lv8_1B);
rv_10_4_fu_7127_p2 <= (tmp_235_fu_7113_p2 xor ap_const_lv8_1B);
rv_10_5_1_fu_8317_p2 <= (tmp_275_fu_8303_p2 xor ap_const_lv8_1B);
rv_10_5_2_fu_8465_p2 <= (tmp_283_fu_8451_p2 xor ap_const_lv8_1B);
rv_10_5_3_fu_8613_p2 <= (tmp_291_fu_8599_p2 xor ap_const_lv8_1B);
rv_10_5_fu_8169_p2 <= (tmp_267_fu_8155_p2 xor ap_const_lv8_1B);
rv_10_6_1_fu_9359_p2 <= (tmp_307_fu_9345_p2 xor ap_const_lv8_1B);
rv_10_6_2_fu_9507_p2 <= (tmp_315_fu_9493_p2 xor ap_const_lv8_1B);
rv_10_6_3_fu_9655_p2 <= (tmp_323_fu_9641_p2 xor ap_const_lv8_1B);
rv_10_6_fu_9211_p2 <= (tmp_299_fu_9197_p2 xor ap_const_lv8_1B);
rv_10_7_1_fu_10401_p2 <= (tmp_339_fu_10387_p2 xor ap_const_lv8_1B);
rv_10_7_2_fu_10549_p2 <= (tmp_347_fu_10535_p2 xor ap_const_lv8_1B);
rv_10_7_3_fu_10697_p2 <= (tmp_355_fu_10683_p2 xor ap_const_lv8_1B);
rv_10_7_fu_10253_p2 <= (tmp_331_fu_10239_p2 xor ap_const_lv8_1B);
rv_10_8_1_fu_11443_p2 <= (tmp_371_fu_11429_p2 xor ap_const_lv8_1B);
rv_10_8_2_fu_11591_p2 <= (tmp_379_fu_11577_p2 xor ap_const_lv8_1B);
rv_10_8_3_fu_11739_p2 <= (tmp_387_fu_11725_p2 xor ap_const_lv8_1B);
rv_10_8_fu_11295_p2 <= (tmp_363_fu_11281_p2 xor ap_const_lv8_1B);
rv_11_0_1_fu_3113_p3 <=
rv_10_0_1_fu_3107_p2 when (tmp_116_fu_3099_p3(0) = '1') else
tmp_115_fu_3093_p2;
rv_11_0_2_fu_3261_p3 <=
rv_10_0_2_fu_3255_p2 when (tmp_124_fu_3247_p3(0) = '1') else
tmp_123_fu_3241_p2;
rv_11_0_3_fu_3409_p3 <=
rv_10_0_3_fu_3403_p2 when (tmp_132_fu_3395_p3(0) = '1') else
tmp_131_fu_3389_p2;
rv_11_1_1_fu_4155_p3 <=
rv_10_1_1_fu_4149_p2 when (tmp_148_fu_4141_p3(0) = '1') else
tmp_147_fu_4135_p2;
rv_11_1_2_fu_4303_p3 <=
rv_10_1_2_fu_4297_p2 when (tmp_156_fu_4289_p3(0) = '1') else
tmp_155_fu_4283_p2;
rv_11_1_3_fu_4451_p3 <=
rv_10_1_3_fu_4445_p2 when (tmp_164_fu_4437_p3(0) = '1') else
tmp_163_fu_4431_p2;
rv_11_1_fu_4007_p3 <=
rv_10_1_fu_4001_p2 when (tmp_140_fu_3993_p3(0) = '1') else
tmp_139_fu_3987_p2;
rv_11_2_1_fu_5197_p3 <=
rv_10_2_1_fu_5191_p2 when (tmp_180_fu_5183_p3(0) = '1') else
tmp_179_fu_5177_p2;
rv_11_2_2_fu_5345_p3 <=
rv_10_2_2_fu_5339_p2 when (tmp_188_fu_5331_p3(0) = '1') else
tmp_187_fu_5325_p2;
rv_11_2_3_fu_5493_p3 <=
rv_10_2_3_fu_5487_p2 when (tmp_196_fu_5479_p3(0) = '1') else
tmp_195_fu_5473_p2;
rv_11_2_fu_5049_p3 <=
rv_10_2_fu_5043_p2 when (tmp_172_fu_5035_p3(0) = '1') else
tmp_171_fu_5029_p2;
rv_11_3_1_fu_6239_p3 <=
rv_10_3_1_fu_6233_p2 when (tmp_212_fu_6225_p3(0) = '1') else
tmp_211_fu_6219_p2;
rv_11_3_2_fu_6387_p3 <=
rv_10_3_2_fu_6381_p2 when (tmp_220_fu_6373_p3(0) = '1') else
tmp_219_fu_6367_p2;
rv_11_3_3_fu_6535_p3 <=
rv_10_3_3_fu_6529_p2 when (tmp_228_fu_6521_p3(0) = '1') else
tmp_227_fu_6515_p2;
rv_11_3_fu_6091_p3 <=
rv_10_3_fu_6085_p2 when (tmp_204_fu_6077_p3(0) = '1') else
tmp_203_fu_6071_p2;
rv_11_4_1_fu_7281_p3 <=
rv_10_4_1_fu_7275_p2 when (tmp_244_fu_7267_p3(0) = '1') else
tmp_243_fu_7261_p2;
rv_11_4_2_fu_7429_p3 <=
rv_10_4_2_fu_7423_p2 when (tmp_252_fu_7415_p3(0) = '1') else
tmp_251_fu_7409_p2;
rv_11_4_3_fu_7577_p3 <=
rv_10_4_3_fu_7571_p2 when (tmp_260_fu_7563_p3(0) = '1') else
tmp_259_fu_7557_p2;
rv_11_4_fu_7133_p3 <=
rv_10_4_fu_7127_p2 when (tmp_236_fu_7119_p3(0) = '1') else
tmp_235_fu_7113_p2;
rv_11_5_1_fu_8323_p3 <=
rv_10_5_1_fu_8317_p2 when (tmp_276_fu_8309_p3(0) = '1') else
tmp_275_fu_8303_p2;
rv_11_5_2_fu_8471_p3 <=
rv_10_5_2_fu_8465_p2 when (tmp_284_fu_8457_p3(0) = '1') else
tmp_283_fu_8451_p2;
rv_11_5_3_fu_8619_p3 <=
rv_10_5_3_fu_8613_p2 when (tmp_292_fu_8605_p3(0) = '1') else
tmp_291_fu_8599_p2;
rv_11_5_fu_8175_p3 <=
rv_10_5_fu_8169_p2 when (tmp_268_fu_8161_p3(0) = '1') else
tmp_267_fu_8155_p2;
rv_11_6_1_fu_9365_p3 <=
rv_10_6_1_fu_9359_p2 when (tmp_308_fu_9351_p3(0) = '1') else
tmp_307_fu_9345_p2;
rv_11_6_2_fu_9513_p3 <=
rv_10_6_2_fu_9507_p2 when (tmp_316_fu_9499_p3(0) = '1') else
tmp_315_fu_9493_p2;
rv_11_6_3_fu_9661_p3 <=
rv_10_6_3_fu_9655_p2 when (tmp_324_fu_9647_p3(0) = '1') else
tmp_323_fu_9641_p2;
rv_11_6_fu_9217_p3 <=
rv_10_6_fu_9211_p2 when (tmp_300_fu_9203_p3(0) = '1') else
tmp_299_fu_9197_p2;
rv_11_7_1_fu_10407_p3 <=
rv_10_7_1_fu_10401_p2 when (tmp_340_fu_10393_p3(0) = '1') else
tmp_339_fu_10387_p2;
rv_11_7_2_fu_10555_p3 <=
rv_10_7_2_fu_10549_p2 when (tmp_348_fu_10541_p3(0) = '1') else
tmp_347_fu_10535_p2;
rv_11_7_3_fu_10703_p3 <=
rv_10_7_3_fu_10697_p2 when (tmp_356_fu_10689_p3(0) = '1') else
tmp_355_fu_10683_p2;
rv_11_7_fu_10259_p3 <=
rv_10_7_fu_10253_p2 when (tmp_332_fu_10245_p3(0) = '1') else
tmp_331_fu_10239_p2;
rv_11_8_1_fu_11449_p3 <=
rv_10_8_1_fu_11443_p2 when (tmp_372_fu_11435_p3(0) = '1') else
tmp_371_fu_11429_p2;
rv_11_8_2_fu_11597_p3 <=
rv_10_8_2_fu_11591_p2 when (tmp_380_fu_11583_p3(0) = '1') else
tmp_379_fu_11577_p2;
rv_11_8_3_fu_11745_p3 <=
rv_10_8_3_fu_11739_p2 when (tmp_388_fu_11731_p3(0) = '1') else
tmp_387_fu_11725_p2;
rv_11_8_fu_11301_p3 <=
rv_10_8_fu_11295_p2 when (tmp_364_fu_11287_p3(0) = '1') else
tmp_363_fu_11281_p2;
rv_1_0_1_fu_3005_p2 <= (tmp_109_fu_2991_p2 xor ap_const_lv8_1B);
rv_1_0_2_fu_3153_p2 <= (tmp_117_fu_3139_p2 xor ap_const_lv8_1B);
rv_1_0_3_fu_3301_p2 <= (tmp_125_fu_3287_p2 xor ap_const_lv8_1B);
rv_1_1_1_fu_4047_p2 <= (tmp_141_fu_4033_p2 xor ap_const_lv8_1B);
rv_1_1_2_fu_4195_p2 <= (tmp_149_fu_4181_p2 xor ap_const_lv8_1B);
rv_1_1_3_fu_4343_p2 <= (tmp_157_fu_4329_p2 xor ap_const_lv8_1B);
rv_1_1_fu_3899_p2 <= (tmp_133_fu_3885_p2 xor ap_const_lv8_1B);
rv_1_2_1_fu_5089_p2 <= (tmp_173_fu_5075_p2 xor ap_const_lv8_1B);
rv_1_2_2_fu_5237_p2 <= (tmp_181_fu_5223_p2 xor ap_const_lv8_1B);
rv_1_2_3_fu_5385_p2 <= (tmp_189_fu_5371_p2 xor ap_const_lv8_1B);
rv_1_2_fu_4941_p2 <= (tmp_165_fu_4927_p2 xor ap_const_lv8_1B);
rv_1_3_1_fu_6131_p2 <= (tmp_205_fu_6117_p2 xor ap_const_lv8_1B);
rv_1_3_2_fu_6279_p2 <= (tmp_213_fu_6265_p2 xor ap_const_lv8_1B);
rv_1_3_3_fu_6427_p2 <= (tmp_221_fu_6413_p2 xor ap_const_lv8_1B);
rv_1_3_fu_5983_p2 <= (tmp_197_fu_5969_p2 xor ap_const_lv8_1B);
rv_1_4_1_fu_7173_p2 <= (tmp_237_fu_7159_p2 xor ap_const_lv8_1B);
rv_1_4_2_fu_7321_p2 <= (tmp_245_fu_7307_p2 xor ap_const_lv8_1B);
rv_1_4_3_fu_7469_p2 <= (tmp_253_fu_7455_p2 xor ap_const_lv8_1B);
rv_1_4_fu_7025_p2 <= (tmp_229_fu_7011_p2 xor ap_const_lv8_1B);
rv_1_5_1_fu_8215_p2 <= (tmp_269_fu_8201_p2 xor ap_const_lv8_1B);
rv_1_5_2_fu_8363_p2 <= (tmp_277_fu_8349_p2 xor ap_const_lv8_1B);
rv_1_5_3_fu_8511_p2 <= (tmp_285_fu_8497_p2 xor ap_const_lv8_1B);
rv_1_5_fu_8067_p2 <= (tmp_261_fu_8053_p2 xor ap_const_lv8_1B);
rv_1_6_1_fu_9257_p2 <= (tmp_301_fu_9243_p2 xor ap_const_lv8_1B);
rv_1_6_2_fu_9405_p2 <= (tmp_309_fu_9391_p2 xor ap_const_lv8_1B);
rv_1_6_3_fu_9553_p2 <= (tmp_317_fu_9539_p2 xor ap_const_lv8_1B);
rv_1_6_fu_9109_p2 <= (tmp_293_fu_9095_p2 xor ap_const_lv8_1B);
rv_1_7_1_fu_10299_p2 <= (tmp_333_fu_10285_p2 xor ap_const_lv8_1B);
rv_1_7_2_fu_10447_p2 <= (tmp_341_fu_10433_p2 xor ap_const_lv8_1B);
rv_1_7_3_fu_10595_p2 <= (tmp_349_fu_10581_p2 xor ap_const_lv8_1B);
rv_1_7_fu_10151_p2 <= (tmp_325_fu_10137_p2 xor ap_const_lv8_1B);
rv_1_8_1_fu_11341_p2 <= (tmp_365_fu_11327_p2 xor ap_const_lv8_1B);
rv_1_8_2_fu_11489_p2 <= (tmp_373_fu_11475_p2 xor ap_const_lv8_1B);
rv_1_8_3_fu_11637_p2 <= (tmp_381_fu_11623_p2 xor ap_const_lv8_1B);
rv_1_8_fu_11193_p2 <= (tmp_357_fu_11179_p2 xor ap_const_lv8_1B);
rv_1_fu_2857_p2 <= (tmp_101_fu_2843_p2 xor ap_const_lv8_1B);
rv_2_0_1_fu_3011_p3 <=
rv_1_0_1_fu_3005_p2 when (tmp_110_fu_2997_p3(0) = '1') else
tmp_109_fu_2991_p2;
rv_2_0_2_fu_3159_p3 <=
rv_1_0_2_fu_3153_p2 when (tmp_118_fu_3145_p3(0) = '1') else
tmp_117_fu_3139_p2;
rv_2_0_3_fu_3307_p3 <=
rv_1_0_3_fu_3301_p2 when (tmp_126_fu_3293_p3(0) = '1') else
tmp_125_fu_3287_p2;
rv_2_1_1_fu_4053_p3 <=
rv_1_1_1_fu_4047_p2 when (tmp_142_fu_4039_p3(0) = '1') else
tmp_141_fu_4033_p2;
rv_2_1_2_fu_4201_p3 <=
rv_1_1_2_fu_4195_p2 when (tmp_150_fu_4187_p3(0) = '1') else
tmp_149_fu_4181_p2;
rv_2_1_3_fu_4349_p3 <=
rv_1_1_3_fu_4343_p2 when (tmp_158_fu_4335_p3(0) = '1') else
tmp_157_fu_4329_p2;
rv_2_1_fu_3905_p3 <=
rv_1_1_fu_3899_p2 when (tmp_134_fu_3891_p3(0) = '1') else
tmp_133_fu_3885_p2;
rv_2_2_1_fu_5095_p3 <=
rv_1_2_1_fu_5089_p2 when (tmp_174_fu_5081_p3(0) = '1') else
tmp_173_fu_5075_p2;
rv_2_2_2_fu_5243_p3 <=
rv_1_2_2_fu_5237_p2 when (tmp_182_fu_5229_p3(0) = '1') else
tmp_181_fu_5223_p2;
rv_2_2_3_fu_5391_p3 <=
rv_1_2_3_fu_5385_p2 when (tmp_190_fu_5377_p3(0) = '1') else
tmp_189_fu_5371_p2;
rv_2_2_fu_4947_p3 <=
rv_1_2_fu_4941_p2 when (tmp_166_fu_4933_p3(0) = '1') else
tmp_165_fu_4927_p2;
rv_2_3_1_fu_6137_p3 <=
rv_1_3_1_fu_6131_p2 when (tmp_206_fu_6123_p3(0) = '1') else
tmp_205_fu_6117_p2;
rv_2_3_2_fu_6285_p3 <=
rv_1_3_2_fu_6279_p2 when (tmp_214_fu_6271_p3(0) = '1') else
tmp_213_fu_6265_p2;
rv_2_3_3_fu_6433_p3 <=
rv_1_3_3_fu_6427_p2 when (tmp_222_fu_6419_p3(0) = '1') else
tmp_221_fu_6413_p2;
rv_2_3_fu_5989_p3 <=
rv_1_3_fu_5983_p2 when (tmp_198_fu_5975_p3(0) = '1') else
tmp_197_fu_5969_p2;
rv_2_4_1_fu_7179_p3 <=
rv_1_4_1_fu_7173_p2 when (tmp_238_fu_7165_p3(0) = '1') else
tmp_237_fu_7159_p2;
rv_2_4_2_fu_7327_p3 <=
rv_1_4_2_fu_7321_p2 when (tmp_246_fu_7313_p3(0) = '1') else
tmp_245_fu_7307_p2;
rv_2_4_3_fu_7475_p3 <=
rv_1_4_3_fu_7469_p2 when (tmp_254_fu_7461_p3(0) = '1') else
tmp_253_fu_7455_p2;
rv_2_4_fu_7031_p3 <=
rv_1_4_fu_7025_p2 when (tmp_230_fu_7017_p3(0) = '1') else
tmp_229_fu_7011_p2;
rv_2_5_1_fu_8221_p3 <=
rv_1_5_1_fu_8215_p2 when (tmp_270_fu_8207_p3(0) = '1') else
tmp_269_fu_8201_p2;
rv_2_5_2_fu_8369_p3 <=
rv_1_5_2_fu_8363_p2 when (tmp_278_fu_8355_p3(0) = '1') else
tmp_277_fu_8349_p2;
rv_2_5_3_fu_8517_p3 <=
rv_1_5_3_fu_8511_p2 when (tmp_286_fu_8503_p3(0) = '1') else
tmp_285_fu_8497_p2;
rv_2_5_fu_8073_p3 <=
rv_1_5_fu_8067_p2 when (tmp_262_fu_8059_p3(0) = '1') else
tmp_261_fu_8053_p2;
rv_2_6_1_fu_9263_p3 <=
rv_1_6_1_fu_9257_p2 when (tmp_302_fu_9249_p3(0) = '1') else
tmp_301_fu_9243_p2;
rv_2_6_2_fu_9411_p3 <=
rv_1_6_2_fu_9405_p2 when (tmp_310_fu_9397_p3(0) = '1') else
tmp_309_fu_9391_p2;
rv_2_6_3_fu_9559_p3 <=
rv_1_6_3_fu_9553_p2 when (tmp_318_fu_9545_p3(0) = '1') else
tmp_317_fu_9539_p2;
rv_2_6_fu_9115_p3 <=
rv_1_6_fu_9109_p2 when (tmp_294_fu_9101_p3(0) = '1') else
tmp_293_fu_9095_p2;
rv_2_7_1_fu_10305_p3 <=
rv_1_7_1_fu_10299_p2 when (tmp_334_fu_10291_p3(0) = '1') else
tmp_333_fu_10285_p2;
rv_2_7_2_fu_10453_p3 <=
rv_1_7_2_fu_10447_p2 when (tmp_342_fu_10439_p3(0) = '1') else
tmp_341_fu_10433_p2;
rv_2_7_3_fu_10601_p3 <=
rv_1_7_3_fu_10595_p2 when (tmp_350_fu_10587_p3(0) = '1') else
tmp_349_fu_10581_p2;
rv_2_7_fu_10157_p3 <=
rv_1_7_fu_10151_p2 when (tmp_326_fu_10143_p3(0) = '1') else
tmp_325_fu_10137_p2;
rv_2_8_1_fu_11347_p3 <=
rv_1_8_1_fu_11341_p2 when (tmp_366_fu_11333_p3(0) = '1') else
tmp_365_fu_11327_p2;
rv_2_8_2_fu_11495_p3 <=
rv_1_8_2_fu_11489_p2 when (tmp_374_fu_11481_p3(0) = '1') else
tmp_373_fu_11475_p2;
rv_2_8_3_fu_11643_p3 <=
rv_1_8_3_fu_11637_p2 when (tmp_382_fu_11629_p3(0) = '1') else
tmp_381_fu_11623_p2;
rv_2_8_fu_11199_p3 <=
rv_1_8_fu_11193_p2 when (tmp_358_fu_11185_p3(0) = '1') else
tmp_357_fu_11179_p2;
rv_2_fu_2863_p3 <=
rv_1_fu_2857_p2 when (tmp_102_fu_2849_p3(0) = '1') else
tmp_101_fu_2843_p2;
rv_3_fu_2965_p3 <=
rv_s_fu_2959_p2 when (tmp_108_fu_2951_p3(0) = '1') else
tmp_107_fu_2945_p2;
rv_4_0_1_fu_3039_p2 <= (tmp_111_fu_3025_p2 xor ap_const_lv8_1B);
rv_4_0_2_fu_3187_p2 <= (tmp_119_fu_3173_p2 xor ap_const_lv8_1B);
rv_4_0_3_fu_3335_p2 <= (tmp_127_fu_3321_p2 xor ap_const_lv8_1B);
rv_4_1_1_fu_4081_p2 <= (tmp_143_fu_4067_p2 xor ap_const_lv8_1B);
rv_4_1_2_fu_4229_p2 <= (tmp_151_fu_4215_p2 xor ap_const_lv8_1B);
rv_4_1_3_fu_4377_p2 <= (tmp_159_fu_4363_p2 xor ap_const_lv8_1B);
rv_4_1_fu_3933_p2 <= (tmp_135_fu_3919_p2 xor ap_const_lv8_1B);
rv_4_2_1_fu_5123_p2 <= (tmp_175_fu_5109_p2 xor ap_const_lv8_1B);
rv_4_2_2_fu_5271_p2 <= (tmp_183_fu_5257_p2 xor ap_const_lv8_1B);
rv_4_2_3_fu_5419_p2 <= (tmp_191_fu_5405_p2 xor ap_const_lv8_1B);
rv_4_2_fu_4975_p2 <= (tmp_167_fu_4961_p2 xor ap_const_lv8_1B);
rv_4_3_1_fu_6165_p2 <= (tmp_207_fu_6151_p2 xor ap_const_lv8_1B);
rv_4_3_2_fu_6313_p2 <= (tmp_215_fu_6299_p2 xor ap_const_lv8_1B);
rv_4_3_3_fu_6461_p2 <= (tmp_223_fu_6447_p2 xor ap_const_lv8_1B);
rv_4_3_fu_6017_p2 <= (tmp_199_fu_6003_p2 xor ap_const_lv8_1B);
rv_4_4_1_fu_7207_p2 <= (tmp_239_fu_7193_p2 xor ap_const_lv8_1B);
rv_4_4_2_fu_7355_p2 <= (tmp_247_fu_7341_p2 xor ap_const_lv8_1B);
rv_4_4_3_fu_7503_p2 <= (tmp_255_fu_7489_p2 xor ap_const_lv8_1B);
rv_4_4_fu_7059_p2 <= (tmp_231_fu_7045_p2 xor ap_const_lv8_1B);
rv_4_5_1_fu_8249_p2 <= (tmp_271_fu_8235_p2 xor ap_const_lv8_1B);
rv_4_5_2_fu_8397_p2 <= (tmp_279_fu_8383_p2 xor ap_const_lv8_1B);
rv_4_5_3_fu_8545_p2 <= (tmp_287_fu_8531_p2 xor ap_const_lv8_1B);
rv_4_5_fu_8101_p2 <= (tmp_263_fu_8087_p2 xor ap_const_lv8_1B);
rv_4_6_1_fu_9291_p2 <= (tmp_303_fu_9277_p2 xor ap_const_lv8_1B);
rv_4_6_2_fu_9439_p2 <= (tmp_311_fu_9425_p2 xor ap_const_lv8_1B);
rv_4_6_3_fu_9587_p2 <= (tmp_319_fu_9573_p2 xor ap_const_lv8_1B);
rv_4_6_fu_9143_p2 <= (tmp_295_fu_9129_p2 xor ap_const_lv8_1B);
rv_4_7_1_fu_10333_p2 <= (tmp_335_fu_10319_p2 xor ap_const_lv8_1B);
rv_4_7_2_fu_10481_p2 <= (tmp_343_fu_10467_p2 xor ap_const_lv8_1B);
rv_4_7_3_fu_10629_p2 <= (tmp_351_fu_10615_p2 xor ap_const_lv8_1B);
rv_4_7_fu_10185_p2 <= (tmp_327_fu_10171_p2 xor ap_const_lv8_1B);
rv_4_8_1_fu_11375_p2 <= (tmp_367_fu_11361_p2 xor ap_const_lv8_1B);
rv_4_8_2_fu_11523_p2 <= (tmp_375_fu_11509_p2 xor ap_const_lv8_1B);
rv_4_8_3_fu_11671_p2 <= (tmp_383_fu_11657_p2 xor ap_const_lv8_1B);
rv_4_8_fu_11227_p2 <= (tmp_359_fu_11213_p2 xor ap_const_lv8_1B);
rv_4_fu_2891_p2 <= (tmp_103_fu_2877_p2 xor ap_const_lv8_1B);
rv_5_0_1_fu_3045_p3 <=
rv_4_0_1_fu_3039_p2 when (tmp_112_fu_3031_p3(0) = '1') else
tmp_111_fu_3025_p2;
rv_5_0_2_fu_3193_p3 <=
rv_4_0_2_fu_3187_p2 when (tmp_120_fu_3179_p3(0) = '1') else
tmp_119_fu_3173_p2;
rv_5_0_3_fu_3341_p3 <=
rv_4_0_3_fu_3335_p2 when (tmp_128_fu_3327_p3(0) = '1') else
tmp_127_fu_3321_p2;
rv_5_1_1_fu_4087_p3 <=
rv_4_1_1_fu_4081_p2 when (tmp_144_fu_4073_p3(0) = '1') else
tmp_143_fu_4067_p2;
rv_5_1_2_fu_4235_p3 <=
rv_4_1_2_fu_4229_p2 when (tmp_152_fu_4221_p3(0) = '1') else
tmp_151_fu_4215_p2;
rv_5_1_3_fu_4383_p3 <=
rv_4_1_3_fu_4377_p2 when (tmp_160_fu_4369_p3(0) = '1') else
tmp_159_fu_4363_p2;
rv_5_1_fu_3939_p3 <=
rv_4_1_fu_3933_p2 when (tmp_136_fu_3925_p3(0) = '1') else
tmp_135_fu_3919_p2;
rv_5_2_1_fu_5129_p3 <=
rv_4_2_1_fu_5123_p2 when (tmp_176_fu_5115_p3(0) = '1') else
tmp_175_fu_5109_p2;
rv_5_2_2_fu_5277_p3 <=
rv_4_2_2_fu_5271_p2 when (tmp_184_fu_5263_p3(0) = '1') else
tmp_183_fu_5257_p2;
rv_5_2_3_fu_5425_p3 <=
rv_4_2_3_fu_5419_p2 when (tmp_192_fu_5411_p3(0) = '1') else
tmp_191_fu_5405_p2;
rv_5_2_fu_4981_p3 <=
rv_4_2_fu_4975_p2 when (tmp_168_fu_4967_p3(0) = '1') else
tmp_167_fu_4961_p2;
rv_5_3_1_fu_6171_p3 <=
rv_4_3_1_fu_6165_p2 when (tmp_208_fu_6157_p3(0) = '1') else
tmp_207_fu_6151_p2;
rv_5_3_2_fu_6319_p3 <=
rv_4_3_2_fu_6313_p2 when (tmp_216_fu_6305_p3(0) = '1') else
tmp_215_fu_6299_p2;
rv_5_3_3_fu_6467_p3 <=
rv_4_3_3_fu_6461_p2 when (tmp_224_fu_6453_p3(0) = '1') else
tmp_223_fu_6447_p2;
rv_5_3_fu_6023_p3 <=
rv_4_3_fu_6017_p2 when (tmp_200_fu_6009_p3(0) = '1') else
tmp_199_fu_6003_p2;
rv_5_4_1_fu_7213_p3 <=
rv_4_4_1_fu_7207_p2 when (tmp_240_fu_7199_p3(0) = '1') else
tmp_239_fu_7193_p2;
rv_5_4_2_fu_7361_p3 <=
rv_4_4_2_fu_7355_p2 when (tmp_248_fu_7347_p3(0) = '1') else
tmp_247_fu_7341_p2;
rv_5_4_3_fu_7509_p3 <=
rv_4_4_3_fu_7503_p2 when (tmp_256_fu_7495_p3(0) = '1') else
tmp_255_fu_7489_p2;
rv_5_4_fu_7065_p3 <=
rv_4_4_fu_7059_p2 when (tmp_232_fu_7051_p3(0) = '1') else
tmp_231_fu_7045_p2;
rv_5_5_1_fu_8255_p3 <=
rv_4_5_1_fu_8249_p2 when (tmp_272_fu_8241_p3(0) = '1') else
tmp_271_fu_8235_p2;
rv_5_5_2_fu_8403_p3 <=
rv_4_5_2_fu_8397_p2 when (tmp_280_fu_8389_p3(0) = '1') else
tmp_279_fu_8383_p2;
rv_5_5_3_fu_8551_p3 <=
rv_4_5_3_fu_8545_p2 when (tmp_288_fu_8537_p3(0) = '1') else
tmp_287_fu_8531_p2;
rv_5_5_fu_8107_p3 <=
rv_4_5_fu_8101_p2 when (tmp_264_fu_8093_p3(0) = '1') else
tmp_263_fu_8087_p2;
rv_5_6_1_fu_9297_p3 <=
rv_4_6_1_fu_9291_p2 when (tmp_304_fu_9283_p3(0) = '1') else
tmp_303_fu_9277_p2;
rv_5_6_2_fu_9445_p3 <=
rv_4_6_2_fu_9439_p2 when (tmp_312_fu_9431_p3(0) = '1') else
tmp_311_fu_9425_p2;
rv_5_6_3_fu_9593_p3 <=
rv_4_6_3_fu_9587_p2 when (tmp_320_fu_9579_p3(0) = '1') else
tmp_319_fu_9573_p2;
rv_5_6_fu_9149_p3 <=
rv_4_6_fu_9143_p2 when (tmp_296_fu_9135_p3(0) = '1') else
tmp_295_fu_9129_p2;
rv_5_7_1_fu_10339_p3 <=
rv_4_7_1_fu_10333_p2 when (tmp_336_fu_10325_p3(0) = '1') else
tmp_335_fu_10319_p2;
rv_5_7_2_fu_10487_p3 <=
rv_4_7_2_fu_10481_p2 when (tmp_344_fu_10473_p3(0) = '1') else
tmp_343_fu_10467_p2;
rv_5_7_3_fu_10635_p3 <=
rv_4_7_3_fu_10629_p2 when (tmp_352_fu_10621_p3(0) = '1') else
tmp_351_fu_10615_p2;
rv_5_7_fu_10191_p3 <=
rv_4_7_fu_10185_p2 when (tmp_328_fu_10177_p3(0) = '1') else
tmp_327_fu_10171_p2;
rv_5_8_1_fu_11381_p3 <=
rv_4_8_1_fu_11375_p2 when (tmp_368_fu_11367_p3(0) = '1') else
tmp_367_fu_11361_p2;
rv_5_8_2_fu_11529_p3 <=
rv_4_8_2_fu_11523_p2 when (tmp_376_fu_11515_p3(0) = '1') else
tmp_375_fu_11509_p2;
rv_5_8_3_fu_11677_p3 <=
rv_4_8_3_fu_11671_p2 when (tmp_384_fu_11663_p3(0) = '1') else
tmp_383_fu_11657_p2;
rv_5_8_fu_11233_p3 <=
rv_4_8_fu_11227_p2 when (tmp_360_fu_11219_p3(0) = '1') else
tmp_359_fu_11213_p2;
rv_5_fu_2897_p3 <=
rv_4_fu_2891_p2 when (tmp_104_fu_2883_p3(0) = '1') else
tmp_103_fu_2877_p2;
rv_7_0_1_fu_3073_p2 <= (tmp_113_fu_3059_p2 xor ap_const_lv8_1B);
rv_7_0_2_fu_3221_p2 <= (tmp_121_fu_3207_p2 xor ap_const_lv8_1B);
rv_7_0_3_fu_3369_p2 <= (tmp_129_fu_3355_p2 xor ap_const_lv8_1B);
rv_7_1_1_fu_4115_p2 <= (tmp_145_fu_4101_p2 xor ap_const_lv8_1B);
rv_7_1_2_fu_4263_p2 <= (tmp_153_fu_4249_p2 xor ap_const_lv8_1B);
rv_7_1_3_fu_4411_p2 <= (tmp_161_fu_4397_p2 xor ap_const_lv8_1B);
rv_7_1_fu_3967_p2 <= (tmp_137_fu_3953_p2 xor ap_const_lv8_1B);
rv_7_2_1_fu_5157_p2 <= (tmp_177_fu_5143_p2 xor ap_const_lv8_1B);
rv_7_2_2_fu_5305_p2 <= (tmp_185_fu_5291_p2 xor ap_const_lv8_1B);
rv_7_2_3_fu_5453_p2 <= (tmp_193_fu_5439_p2 xor ap_const_lv8_1B);
rv_7_2_fu_5009_p2 <= (tmp_169_fu_4995_p2 xor ap_const_lv8_1B);
rv_7_3_1_fu_6199_p2 <= (tmp_209_fu_6185_p2 xor ap_const_lv8_1B);
rv_7_3_2_fu_6347_p2 <= (tmp_217_fu_6333_p2 xor ap_const_lv8_1B);
rv_7_3_3_fu_6495_p2 <= (tmp_225_fu_6481_p2 xor ap_const_lv8_1B);
rv_7_3_fu_6051_p2 <= (tmp_201_fu_6037_p2 xor ap_const_lv8_1B);
rv_7_4_1_fu_7241_p2 <= (tmp_241_fu_7227_p2 xor ap_const_lv8_1B);
rv_7_4_2_fu_7389_p2 <= (tmp_249_fu_7375_p2 xor ap_const_lv8_1B);
rv_7_4_3_fu_7537_p2 <= (tmp_257_fu_7523_p2 xor ap_const_lv8_1B);
rv_7_4_fu_7093_p2 <= (tmp_233_fu_7079_p2 xor ap_const_lv8_1B);
rv_7_5_1_fu_8283_p2 <= (tmp_273_fu_8269_p2 xor ap_const_lv8_1B);
rv_7_5_2_fu_8431_p2 <= (tmp_281_fu_8417_p2 xor ap_const_lv8_1B);
rv_7_5_3_fu_8579_p2 <= (tmp_289_fu_8565_p2 xor ap_const_lv8_1B);
rv_7_5_fu_8135_p2 <= (tmp_265_fu_8121_p2 xor ap_const_lv8_1B);
rv_7_6_1_fu_9325_p2 <= (tmp_305_fu_9311_p2 xor ap_const_lv8_1B);
rv_7_6_2_fu_9473_p2 <= (tmp_313_fu_9459_p2 xor ap_const_lv8_1B);
rv_7_6_3_fu_9621_p2 <= (tmp_321_fu_9607_p2 xor ap_const_lv8_1B);
rv_7_6_fu_9177_p2 <= (tmp_297_fu_9163_p2 xor ap_const_lv8_1B);
rv_7_7_1_fu_10367_p2 <= (tmp_337_fu_10353_p2 xor ap_const_lv8_1B);
rv_7_7_2_fu_10515_p2 <= (tmp_345_fu_10501_p2 xor ap_const_lv8_1B);
rv_7_7_3_fu_10663_p2 <= (tmp_353_fu_10649_p2 xor ap_const_lv8_1B);
rv_7_7_fu_10219_p2 <= (tmp_329_fu_10205_p2 xor ap_const_lv8_1B);
rv_7_8_1_fu_11409_p2 <= (tmp_369_fu_11395_p2 xor ap_const_lv8_1B);
rv_7_8_2_fu_11557_p2 <= (tmp_377_fu_11543_p2 xor ap_const_lv8_1B);
rv_7_8_3_fu_11705_p2 <= (tmp_385_fu_11691_p2 xor ap_const_lv8_1B);
rv_7_8_fu_11261_p2 <= (tmp_361_fu_11247_p2 xor ap_const_lv8_1B);
rv_7_fu_2925_p2 <= (tmp_105_fu_2911_p2 xor ap_const_lv8_1B);
rv_8_0_1_fu_3079_p3 <=
rv_7_0_1_fu_3073_p2 when (tmp_114_fu_3065_p3(0) = '1') else
tmp_113_fu_3059_p2;
rv_8_0_2_fu_3227_p3 <=
rv_7_0_2_fu_3221_p2 when (tmp_122_fu_3213_p3(0) = '1') else
tmp_121_fu_3207_p2;
rv_8_0_3_fu_3375_p3 <=
rv_7_0_3_fu_3369_p2 when (tmp_130_fu_3361_p3(0) = '1') else
tmp_129_fu_3355_p2;
rv_8_1_1_fu_4121_p3 <=
rv_7_1_1_fu_4115_p2 when (tmp_146_fu_4107_p3(0) = '1') else
tmp_145_fu_4101_p2;
rv_8_1_2_fu_4269_p3 <=
rv_7_1_2_fu_4263_p2 when (tmp_154_fu_4255_p3(0) = '1') else
tmp_153_fu_4249_p2;
rv_8_1_3_fu_4417_p3 <=
rv_7_1_3_fu_4411_p2 when (tmp_162_fu_4403_p3(0) = '1') else
tmp_161_fu_4397_p2;
rv_8_1_fu_3973_p3 <=
rv_7_1_fu_3967_p2 when (tmp_138_fu_3959_p3(0) = '1') else
tmp_137_fu_3953_p2;
rv_8_2_1_fu_5163_p3 <=
rv_7_2_1_fu_5157_p2 when (tmp_178_fu_5149_p3(0) = '1') else
tmp_177_fu_5143_p2;
rv_8_2_2_fu_5311_p3 <=
rv_7_2_2_fu_5305_p2 when (tmp_186_fu_5297_p3(0) = '1') else
tmp_185_fu_5291_p2;
rv_8_2_3_fu_5459_p3 <=
rv_7_2_3_fu_5453_p2 when (tmp_194_fu_5445_p3(0) = '1') else
tmp_193_fu_5439_p2;
rv_8_2_fu_5015_p3 <=
rv_7_2_fu_5009_p2 when (tmp_170_fu_5001_p3(0) = '1') else
tmp_169_fu_4995_p2;
rv_8_3_1_fu_6205_p3 <=
rv_7_3_1_fu_6199_p2 when (tmp_210_fu_6191_p3(0) = '1') else
tmp_209_fu_6185_p2;
rv_8_3_2_fu_6353_p3 <=
rv_7_3_2_fu_6347_p2 when (tmp_218_fu_6339_p3(0) = '1') else
tmp_217_fu_6333_p2;
rv_8_3_3_fu_6501_p3 <=
rv_7_3_3_fu_6495_p2 when (tmp_226_fu_6487_p3(0) = '1') else
tmp_225_fu_6481_p2;
rv_8_3_fu_6057_p3 <=
rv_7_3_fu_6051_p2 when (tmp_202_fu_6043_p3(0) = '1') else
tmp_201_fu_6037_p2;
rv_8_4_1_fu_7247_p3 <=
rv_7_4_1_fu_7241_p2 when (tmp_242_fu_7233_p3(0) = '1') else
tmp_241_fu_7227_p2;
rv_8_4_2_fu_7395_p3 <=
rv_7_4_2_fu_7389_p2 when (tmp_250_fu_7381_p3(0) = '1') else
tmp_249_fu_7375_p2;
rv_8_4_3_fu_7543_p3 <=
rv_7_4_3_fu_7537_p2 when (tmp_258_fu_7529_p3(0) = '1') else
tmp_257_fu_7523_p2;
rv_8_4_fu_7099_p3 <=
rv_7_4_fu_7093_p2 when (tmp_234_fu_7085_p3(0) = '1') else
tmp_233_fu_7079_p2;
rv_8_5_1_fu_8289_p3 <=
rv_7_5_1_fu_8283_p2 when (tmp_274_fu_8275_p3(0) = '1') else
tmp_273_fu_8269_p2;
rv_8_5_2_fu_8437_p3 <=
rv_7_5_2_fu_8431_p2 when (tmp_282_fu_8423_p3(0) = '1') else
tmp_281_fu_8417_p2;
rv_8_5_3_fu_8585_p3 <=
rv_7_5_3_fu_8579_p2 when (tmp_290_fu_8571_p3(0) = '1') else
tmp_289_fu_8565_p2;
rv_8_5_fu_8141_p3 <=
rv_7_5_fu_8135_p2 when (tmp_266_fu_8127_p3(0) = '1') else
tmp_265_fu_8121_p2;
rv_8_6_1_fu_9331_p3 <=
rv_7_6_1_fu_9325_p2 when (tmp_306_fu_9317_p3(0) = '1') else
tmp_305_fu_9311_p2;
rv_8_6_2_fu_9479_p3 <=
rv_7_6_2_fu_9473_p2 when (tmp_314_fu_9465_p3(0) = '1') else
tmp_313_fu_9459_p2;
rv_8_6_3_fu_9627_p3 <=
rv_7_6_3_fu_9621_p2 when (tmp_322_fu_9613_p3(0) = '1') else
tmp_321_fu_9607_p2;
rv_8_6_fu_9183_p3 <=
rv_7_6_fu_9177_p2 when (tmp_298_fu_9169_p3(0) = '1') else
tmp_297_fu_9163_p2;
rv_8_7_1_fu_10373_p3 <=
rv_7_7_1_fu_10367_p2 when (tmp_338_fu_10359_p3(0) = '1') else
tmp_337_fu_10353_p2;
rv_8_7_2_fu_10521_p3 <=
rv_7_7_2_fu_10515_p2 when (tmp_346_fu_10507_p3(0) = '1') else
tmp_345_fu_10501_p2;
rv_8_7_3_fu_10669_p3 <=
rv_7_7_3_fu_10663_p2 when (tmp_354_fu_10655_p3(0) = '1') else
tmp_353_fu_10649_p2;
rv_8_7_fu_10225_p3 <=
rv_7_7_fu_10219_p2 when (tmp_330_fu_10211_p3(0) = '1') else
tmp_329_fu_10205_p2;
rv_8_8_1_fu_11415_p3 <=
rv_7_8_1_fu_11409_p2 when (tmp_370_fu_11401_p3(0) = '1') else
tmp_369_fu_11395_p2;
rv_8_8_2_fu_11563_p3 <=
rv_7_8_2_fu_11557_p2 when (tmp_378_fu_11549_p3(0) = '1') else
tmp_377_fu_11543_p2;
rv_8_8_3_fu_11711_p3 <=
rv_7_8_3_fu_11705_p2 when (tmp_386_fu_11697_p3(0) = '1') else
tmp_385_fu_11691_p2;
rv_8_8_fu_11267_p3 <=
rv_7_8_fu_11261_p2 when (tmp_362_fu_11253_p3(0) = '1') else
tmp_361_fu_11247_p2;
rv_8_fu_2931_p3 <=
rv_7_fu_2925_p2 when (tmp_106_fu_2917_p3(0) = '1') else
tmp_105_fu_2911_p2;
rv_s_fu_2959_p2 <= (tmp_107_fu_2945_p2 xor ap_const_lv8_1B);
sboxes_address0 <= tmp_35_fu_2725_p1(8 - 1 downto 0);
sboxes_address1 <= tmp_35_0_1_fu_2730_p1(8 - 1 downto 0);
sboxes_address10 <= tmp_35_0_s_fu_2775_p1(8 - 1 downto 0);
sboxes_address100 <= tmp_35_5_fu_7935_p1(8 - 1 downto 0);
sboxes_address101 <= tmp_35_5_1_fu_7940_p1(8 - 1 downto 0);
sboxes_address102 <= tmp_35_5_2_fu_7945_p1(8 - 1 downto 0);
sboxes_address103 <= tmp_35_5_3_fu_7950_p1(8 - 1 downto 0);
sboxes_address104 <= tmp_35_5_4_fu_7955_p1(8 - 1 downto 0);
sboxes_address105 <= tmp_35_5_5_fu_7960_p1(8 - 1 downto 0);
sboxes_address106 <= tmp_35_5_6_fu_7965_p1(8 - 1 downto 0);
sboxes_address107 <= tmp_35_5_7_fu_7970_p1(8 - 1 downto 0);
sboxes_address108 <= tmp_35_5_8_fu_7975_p1(8 - 1 downto 0);
sboxes_address109 <= tmp_35_5_9_fu_7980_p1(8 - 1 downto 0);
sboxes_address11 <= tmp_35_0_10_fu_2780_p1(8 - 1 downto 0);
sboxes_address110 <= tmp_35_5_s_fu_7985_p1(8 - 1 downto 0);
sboxes_address111 <= tmp_35_5_10_fu_7990_p1(8 - 1 downto 0);
sboxes_address112 <= tmp_35_5_11_fu_7995_p1(8 - 1 downto 0);
sboxes_address113 <= tmp_35_5_12_fu_8000_p1(8 - 1 downto 0);
sboxes_address114 <= tmp_35_5_13_fu_8005_p1(8 - 1 downto 0);
sboxes_address115 <= tmp_35_5_14_fu_8010_p1(8 - 1 downto 0);
sboxes_address116 <= tmp_60_5_fu_8015_p1(8 - 1 downto 0);
sboxes_address117 <= tmp_61_5_fu_8020_p1(8 - 1 downto 0);
sboxes_address118 <= tmp_62_5_fu_8025_p1(8 - 1 downto 0);
sboxes_address119 <= tmp_63_5_fu_8030_p1(8 - 1 downto 0);
sboxes_address12 <= tmp_35_0_11_fu_2785_p1(8 - 1 downto 0);
sboxes_address120 <= tmp_35_6_fu_8977_p1(8 - 1 downto 0);
sboxes_address121 <= tmp_35_6_1_fu_8982_p1(8 - 1 downto 0);
sboxes_address122 <= tmp_35_6_2_fu_8987_p1(8 - 1 downto 0);
sboxes_address123 <= tmp_35_6_3_fu_8992_p1(8 - 1 downto 0);
sboxes_address124 <= tmp_35_6_4_fu_8997_p1(8 - 1 downto 0);
sboxes_address125 <= tmp_35_6_5_fu_9002_p1(8 - 1 downto 0);
sboxes_address126 <= tmp_35_6_6_fu_9007_p1(8 - 1 downto 0);
sboxes_address127 <= tmp_35_6_7_fu_9012_p1(8 - 1 downto 0);
sboxes_address128 <= tmp_35_6_8_fu_9017_p1(8 - 1 downto 0);
sboxes_address129 <= tmp_35_6_9_fu_9022_p1(8 - 1 downto 0);
sboxes_address13 <= tmp_35_0_12_fu_2790_p1(8 - 1 downto 0);
sboxes_address130 <= tmp_35_6_s_fu_9027_p1(8 - 1 downto 0);
sboxes_address131 <= tmp_35_6_10_fu_9032_p1(8 - 1 downto 0);
sboxes_address132 <= tmp_35_6_11_fu_9037_p1(8 - 1 downto 0);
sboxes_address133 <= tmp_35_6_12_fu_9042_p1(8 - 1 downto 0);
sboxes_address134 <= tmp_35_6_13_fu_9047_p1(8 - 1 downto 0);
sboxes_address135 <= tmp_35_6_14_fu_9052_p1(8 - 1 downto 0);
sboxes_address136 <= tmp_60_6_fu_9057_p1(8 - 1 downto 0);
sboxes_address137 <= tmp_61_6_fu_9062_p1(8 - 1 downto 0);
sboxes_address138 <= tmp_62_6_fu_9067_p1(8 - 1 downto 0);
sboxes_address139 <= tmp_63_6_fu_9072_p1(8 - 1 downto 0);
sboxes_address14 <= tmp_35_0_13_fu_2795_p1(8 - 1 downto 0);
sboxes_address140 <= tmp_35_7_fu_10019_p1(8 - 1 downto 0);
sboxes_address141 <= tmp_35_7_1_fu_10024_p1(8 - 1 downto 0);
sboxes_address142 <= tmp_35_7_2_fu_10029_p1(8 - 1 downto 0);
sboxes_address143 <= tmp_35_7_3_fu_10034_p1(8 - 1 downto 0);
sboxes_address144 <= tmp_35_7_4_fu_10039_p1(8 - 1 downto 0);
sboxes_address145 <= tmp_35_7_5_fu_10044_p1(8 - 1 downto 0);
sboxes_address146 <= tmp_35_7_6_fu_10049_p1(8 - 1 downto 0);
sboxes_address147 <= tmp_35_7_7_fu_10054_p1(8 - 1 downto 0);
sboxes_address148 <= tmp_35_7_8_fu_10059_p1(8 - 1 downto 0);
sboxes_address149 <= tmp_35_7_9_fu_10064_p1(8 - 1 downto 0);
sboxes_address15 <= tmp_35_0_14_fu_2800_p1(8 - 1 downto 0);
sboxes_address150 <= tmp_35_7_s_fu_10069_p1(8 - 1 downto 0);
sboxes_address151 <= tmp_35_7_10_fu_10074_p1(8 - 1 downto 0);
sboxes_address152 <= tmp_35_7_11_fu_10079_p1(8 - 1 downto 0);
sboxes_address153 <= tmp_35_7_12_fu_10084_p1(8 - 1 downto 0);
sboxes_address154 <= tmp_35_7_13_fu_10089_p1(8 - 1 downto 0);
sboxes_address155 <= tmp_35_7_14_fu_10094_p1(8 - 1 downto 0);
sboxes_address156 <= tmp_60_7_fu_10099_p1(8 - 1 downto 0);
sboxes_address157 <= tmp_61_7_fu_10104_p1(8 - 1 downto 0);
sboxes_address158 <= tmp_62_7_fu_10109_p1(8 - 1 downto 0);
sboxes_address159 <= tmp_63_7_fu_10114_p1(8 - 1 downto 0);
sboxes_address16 <= tmp_60_fu_2805_p1(8 - 1 downto 0);
sboxes_address160 <= tmp_35_8_fu_11061_p1(8 - 1 downto 0);
sboxes_address161 <= tmp_35_8_1_fu_11066_p1(8 - 1 downto 0);
sboxes_address162 <= tmp_35_8_2_fu_11071_p1(8 - 1 downto 0);
sboxes_address163 <= tmp_35_8_3_fu_11076_p1(8 - 1 downto 0);
sboxes_address164 <= tmp_35_8_4_fu_11081_p1(8 - 1 downto 0);
sboxes_address165 <= tmp_35_8_5_fu_11086_p1(8 - 1 downto 0);
sboxes_address166 <= tmp_35_8_6_fu_11091_p1(8 - 1 downto 0);
sboxes_address167 <= tmp_35_8_7_fu_11096_p1(8 - 1 downto 0);
sboxes_address168 <= tmp_35_8_8_fu_11101_p1(8 - 1 downto 0);
sboxes_address169 <= tmp_35_8_9_fu_11106_p1(8 - 1 downto 0);
sboxes_address17 <= tmp_61_fu_2810_p1(8 - 1 downto 0);
sboxes_address170 <= tmp_35_8_s_fu_11111_p1(8 - 1 downto 0);
sboxes_address171 <= tmp_35_8_10_fu_11116_p1(8 - 1 downto 0);
sboxes_address172 <= tmp_35_8_11_fu_11121_p1(8 - 1 downto 0);
sboxes_address173 <= tmp_35_8_12_fu_11126_p1(8 - 1 downto 0);
sboxes_address174 <= tmp_35_8_13_fu_11131_p1(8 - 1 downto 0);
sboxes_address175 <= tmp_35_8_14_fu_11136_p1(8 - 1 downto 0);
sboxes_address176 <= tmp_60_8_fu_11141_p1(8 - 1 downto 0);
sboxes_address177 <= tmp_61_8_fu_11146_p1(8 - 1 downto 0);
sboxes_address178 <= tmp_62_8_fu_11151_p1(8 - 1 downto 0);
sboxes_address179 <= tmp_63_8_fu_11156_p1(8 - 1 downto 0);
sboxes_address18 <= tmp_62_fu_2815_p1(8 - 1 downto 0);
sboxes_address180 <= tmp_33_fu_12103_p1(8 - 1 downto 0);
sboxes_address181 <= tmp_33_1_fu_12108_p1(8 - 1 downto 0);
sboxes_address182 <= tmp_33_2_fu_12113_p1(8 - 1 downto 0);
sboxes_address183 <= tmp_33_3_fu_12118_p1(8 - 1 downto 0);
sboxes_address184 <= tmp_33_4_fu_12123_p1(8 - 1 downto 0);
sboxes_address185 <= tmp_33_5_fu_12128_p1(8 - 1 downto 0);
sboxes_address186 <= tmp_33_6_fu_12133_p1(8 - 1 downto 0);
sboxes_address187 <= tmp_33_7_fu_12138_p1(8 - 1 downto 0);
sboxes_address188 <= tmp_33_8_fu_12143_p1(8 - 1 downto 0);
sboxes_address189 <= tmp_33_9_fu_12148_p1(8 - 1 downto 0);
sboxes_address19 <= tmp_63_fu_2820_p1(8 - 1 downto 0);
sboxes_address190 <= tmp_33_s_fu_12153_p1(8 - 1 downto 0);
sboxes_address191 <= tmp_33_10_fu_12158_p1(8 - 1 downto 0);
sboxes_address192 <= tmp_33_11_fu_12163_p1(8 - 1 downto 0);
sboxes_address193 <= tmp_33_12_fu_12168_p1(8 - 1 downto 0);
sboxes_address194 <= tmp_33_13_fu_12173_p1(8 - 1 downto 0);
sboxes_address195 <= tmp_33_14_fu_12178_p1(8 - 1 downto 0);
sboxes_address196 <= tmp_s_fu_12183_p1(8 - 1 downto 0);
sboxes_address197 <= tmp_1_fu_12188_p1(8 - 1 downto 0);
sboxes_address198 <= tmp_2_fu_12193_p1(8 - 1 downto 0);
sboxes_address199 <= tmp_3_fu_12198_p1(8 - 1 downto 0);
sboxes_address2 <= tmp_35_0_2_fu_2735_p1(8 - 1 downto 0);
sboxes_address20 <= tmp_35_1_fu_3767_p1(8 - 1 downto 0);
sboxes_address21 <= tmp_35_1_1_fu_3772_p1(8 - 1 downto 0);
sboxes_address22 <= tmp_35_1_2_fu_3777_p1(8 - 1 downto 0);
sboxes_address23 <= tmp_35_1_3_fu_3782_p1(8 - 1 downto 0);
sboxes_address24 <= tmp_35_1_4_fu_3787_p1(8 - 1 downto 0);
sboxes_address25 <= tmp_35_1_5_fu_3792_p1(8 - 1 downto 0);
sboxes_address26 <= tmp_35_1_6_fu_3797_p1(8 - 1 downto 0);
sboxes_address27 <= tmp_35_1_7_fu_3802_p1(8 - 1 downto 0);
sboxes_address28 <= tmp_35_1_8_fu_3807_p1(8 - 1 downto 0);
sboxes_address29 <= tmp_35_1_9_fu_3812_p1(8 - 1 downto 0);
sboxes_address3 <= tmp_35_0_3_fu_2740_p1(8 - 1 downto 0);
sboxes_address30 <= tmp_35_1_s_fu_3817_p1(8 - 1 downto 0);
sboxes_address31 <= tmp_35_1_10_fu_3822_p1(8 - 1 downto 0);
sboxes_address32 <= tmp_35_1_11_fu_3827_p1(8 - 1 downto 0);
sboxes_address33 <= tmp_35_1_12_fu_3832_p1(8 - 1 downto 0);
sboxes_address34 <= tmp_35_1_13_fu_3837_p1(8 - 1 downto 0);
sboxes_address35 <= tmp_35_1_14_fu_3842_p1(8 - 1 downto 0);
sboxes_address36 <= tmp_60_1_fu_3847_p1(8 - 1 downto 0);
sboxes_address37 <= tmp_61_1_fu_3852_p1(8 - 1 downto 0);
sboxes_address38 <= tmp_62_1_fu_3857_p1(8 - 1 downto 0);
sboxes_address39 <= tmp_63_1_fu_3862_p1(8 - 1 downto 0);
sboxes_address4 <= tmp_35_0_4_fu_2745_p1(8 - 1 downto 0);
sboxes_address40 <= tmp_35_2_fu_4809_p1(8 - 1 downto 0);
sboxes_address41 <= tmp_35_2_1_fu_4814_p1(8 - 1 downto 0);
sboxes_address42 <= tmp_35_2_2_fu_4819_p1(8 - 1 downto 0);
sboxes_address43 <= tmp_35_2_3_fu_4824_p1(8 - 1 downto 0);
sboxes_address44 <= tmp_35_2_4_fu_4829_p1(8 - 1 downto 0);
sboxes_address45 <= tmp_35_2_5_fu_4834_p1(8 - 1 downto 0);
sboxes_address46 <= tmp_35_2_6_fu_4839_p1(8 - 1 downto 0);
sboxes_address47 <= tmp_35_2_7_fu_4844_p1(8 - 1 downto 0);
sboxes_address48 <= tmp_35_2_8_fu_4849_p1(8 - 1 downto 0);
sboxes_address49 <= tmp_35_2_9_fu_4854_p1(8 - 1 downto 0);
sboxes_address5 <= tmp_35_0_5_fu_2750_p1(8 - 1 downto 0);
sboxes_address50 <= tmp_35_2_s_fu_4859_p1(8 - 1 downto 0);
sboxes_address51 <= tmp_35_2_10_fu_4864_p1(8 - 1 downto 0);
sboxes_address52 <= tmp_35_2_11_fu_4869_p1(8 - 1 downto 0);
sboxes_address53 <= tmp_35_2_12_fu_4874_p1(8 - 1 downto 0);
sboxes_address54 <= tmp_35_2_13_fu_4879_p1(8 - 1 downto 0);
sboxes_address55 <= tmp_35_2_14_fu_4884_p1(8 - 1 downto 0);
sboxes_address56 <= tmp_60_2_fu_4889_p1(8 - 1 downto 0);
sboxes_address57 <= tmp_61_2_fu_4894_p1(8 - 1 downto 0);
sboxes_address58 <= tmp_62_2_fu_4899_p1(8 - 1 downto 0);
sboxes_address59 <= tmp_63_2_fu_4904_p1(8 - 1 downto 0);
sboxes_address6 <= tmp_35_0_6_fu_2755_p1(8 - 1 downto 0);
sboxes_address60 <= tmp_35_3_fu_5851_p1(8 - 1 downto 0);
sboxes_address61 <= tmp_35_3_1_fu_5856_p1(8 - 1 downto 0);
sboxes_address62 <= tmp_35_3_2_fu_5861_p1(8 - 1 downto 0);
sboxes_address63 <= tmp_35_3_3_fu_5866_p1(8 - 1 downto 0);
sboxes_address64 <= tmp_35_3_4_fu_5871_p1(8 - 1 downto 0);
sboxes_address65 <= tmp_35_3_5_fu_5876_p1(8 - 1 downto 0);
sboxes_address66 <= tmp_35_3_6_fu_5881_p1(8 - 1 downto 0);
sboxes_address67 <= tmp_35_3_7_fu_5886_p1(8 - 1 downto 0);
sboxes_address68 <= tmp_35_3_8_fu_5891_p1(8 - 1 downto 0);
sboxes_address69 <= tmp_35_3_9_fu_5896_p1(8 - 1 downto 0);
sboxes_address7 <= tmp_35_0_7_fu_2760_p1(8 - 1 downto 0);
sboxes_address70 <= tmp_35_3_s_fu_5901_p1(8 - 1 downto 0);
sboxes_address71 <= tmp_35_3_10_fu_5906_p1(8 - 1 downto 0);
sboxes_address72 <= tmp_35_3_11_fu_5911_p1(8 - 1 downto 0);
sboxes_address73 <= tmp_35_3_12_fu_5916_p1(8 - 1 downto 0);
sboxes_address74 <= tmp_35_3_13_fu_5921_p1(8 - 1 downto 0);
sboxes_address75 <= tmp_35_3_14_fu_5926_p1(8 - 1 downto 0);
sboxes_address76 <= tmp_60_3_fu_5931_p1(8 - 1 downto 0);
sboxes_address77 <= tmp_61_3_fu_5936_p1(8 - 1 downto 0);
sboxes_address78 <= tmp_62_3_fu_5941_p1(8 - 1 downto 0);
sboxes_address79 <= tmp_63_3_fu_5946_p1(8 - 1 downto 0);
sboxes_address8 <= tmp_35_0_8_fu_2765_p1(8 - 1 downto 0);
sboxes_address80 <= tmp_35_4_fu_6893_p1(8 - 1 downto 0);
sboxes_address81 <= tmp_35_4_1_fu_6898_p1(8 - 1 downto 0);
sboxes_address82 <= tmp_35_4_2_fu_6903_p1(8 - 1 downto 0);
sboxes_address83 <= tmp_35_4_3_fu_6908_p1(8 - 1 downto 0);
sboxes_address84 <= tmp_35_4_4_fu_6913_p1(8 - 1 downto 0);
sboxes_address85 <= tmp_35_4_5_fu_6918_p1(8 - 1 downto 0);
sboxes_address86 <= tmp_35_4_6_fu_6923_p1(8 - 1 downto 0);
sboxes_address87 <= tmp_35_4_7_fu_6928_p1(8 - 1 downto 0);
sboxes_address88 <= tmp_35_4_8_fu_6933_p1(8 - 1 downto 0);
sboxes_address89 <= tmp_35_4_9_fu_6938_p1(8 - 1 downto 0);
sboxes_address9 <= tmp_35_0_9_fu_2770_p1(8 - 1 downto 0);
sboxes_address90 <= tmp_35_4_s_fu_6943_p1(8 - 1 downto 0);
sboxes_address91 <= tmp_35_4_10_fu_6948_p1(8 - 1 downto 0);
sboxes_address92 <= tmp_35_4_11_fu_6953_p1(8 - 1 downto 0);
sboxes_address93 <= tmp_35_4_12_fu_6958_p1(8 - 1 downto 0);
sboxes_address94 <= tmp_35_4_13_fu_6963_p1(8 - 1 downto 0);
sboxes_address95 <= tmp_35_4_14_fu_6968_p1(8 - 1 downto 0);
sboxes_address96 <= tmp_60_4_fu_6973_p1(8 - 1 downto 0);
sboxes_address97 <= tmp_61_4_fu_6978_p1(8 - 1 downto 0);
sboxes_address98 <= tmp_62_4_fu_6983_p1(8 - 1 downto 0);
sboxes_address99 <= tmp_63_4_fu_6988_p1(8 - 1 downto 0);
sboxes_ce0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce0 <= ap_const_logic_1;
else
sboxes_ce0 <= ap_const_logic_0;
end if;
end process;
sboxes_ce1_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce1 <= ap_const_logic_1;
else
sboxes_ce1 <= ap_const_logic_0;
end if;
end process;
sboxes_ce10_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce10 <= ap_const_logic_1;
else
sboxes_ce10 <= ap_const_logic_0;
end if;
end process;
sboxes_ce100_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce100 <= ap_const_logic_1;
else
sboxes_ce100 <= ap_const_logic_0;
end if;
end process;
sboxes_ce101_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce101 <= ap_const_logic_1;
else
sboxes_ce101 <= ap_const_logic_0;
end if;
end process;
sboxes_ce102_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce102 <= ap_const_logic_1;
else
sboxes_ce102 <= ap_const_logic_0;
end if;
end process;
sboxes_ce103_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce103 <= ap_const_logic_1;
else
sboxes_ce103 <= ap_const_logic_0;
end if;
end process;
sboxes_ce104_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce104 <= ap_const_logic_1;
else
sboxes_ce104 <= ap_const_logic_0;
end if;
end process;
sboxes_ce105_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce105 <= ap_const_logic_1;
else
sboxes_ce105 <= ap_const_logic_0;
end if;
end process;
sboxes_ce106_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce106 <= ap_const_logic_1;
else
sboxes_ce106 <= ap_const_logic_0;
end if;
end process;
sboxes_ce107_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce107 <= ap_const_logic_1;
else
sboxes_ce107 <= ap_const_logic_0;
end if;
end process;
sboxes_ce108_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce108 <= ap_const_logic_1;
else
sboxes_ce108 <= ap_const_logic_0;
end if;
end process;
sboxes_ce109_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce109 <= ap_const_logic_1;
else
sboxes_ce109 <= ap_const_logic_0;
end if;
end process;
sboxes_ce11_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce11 <= ap_const_logic_1;
else
sboxes_ce11 <= ap_const_logic_0;
end if;
end process;
sboxes_ce110_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce110 <= ap_const_logic_1;
else
sboxes_ce110 <= ap_const_logic_0;
end if;
end process;
sboxes_ce111_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce111 <= ap_const_logic_1;
else
sboxes_ce111 <= ap_const_logic_0;
end if;
end process;
sboxes_ce112_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce112 <= ap_const_logic_1;
else
sboxes_ce112 <= ap_const_logic_0;
end if;
end process;
sboxes_ce113_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce113 <= ap_const_logic_1;
else
sboxes_ce113 <= ap_const_logic_0;
end if;
end process;
sboxes_ce114_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce114 <= ap_const_logic_1;
else
sboxes_ce114 <= ap_const_logic_0;
end if;
end process;
sboxes_ce115_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce115 <= ap_const_logic_1;
else
sboxes_ce115 <= ap_const_logic_0;
end if;
end process;
sboxes_ce116_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce116 <= ap_const_logic_1;
else
sboxes_ce116 <= ap_const_logic_0;
end if;
end process;
sboxes_ce117_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce117 <= ap_const_logic_1;
else
sboxes_ce117 <= ap_const_logic_0;
end if;
end process;
sboxes_ce118_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce118 <= ap_const_logic_1;
else
sboxes_ce118 <= ap_const_logic_0;
end if;
end process;
sboxes_ce119_assign_proc : process(ap_enable_reg_pp0_iter5, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
sboxes_ce119 <= ap_const_logic_1;
else
sboxes_ce119 <= ap_const_logic_0;
end if;
end process;
sboxes_ce12_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce12 <= ap_const_logic_1;
else
sboxes_ce12 <= ap_const_logic_0;
end if;
end process;
sboxes_ce120_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce120 <= ap_const_logic_1;
else
sboxes_ce120 <= ap_const_logic_0;
end if;
end process;
sboxes_ce121_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce121 <= ap_const_logic_1;
else
sboxes_ce121 <= ap_const_logic_0;
end if;
end process;
sboxes_ce122_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce122 <= ap_const_logic_1;
else
sboxes_ce122 <= ap_const_logic_0;
end if;
end process;
sboxes_ce123_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce123 <= ap_const_logic_1;
else
sboxes_ce123 <= ap_const_logic_0;
end if;
end process;
sboxes_ce124_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce124 <= ap_const_logic_1;
else
sboxes_ce124 <= ap_const_logic_0;
end if;
end process;
sboxes_ce125_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce125 <= ap_const_logic_1;
else
sboxes_ce125 <= ap_const_logic_0;
end if;
end process;
sboxes_ce126_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce126 <= ap_const_logic_1;
else
sboxes_ce126 <= ap_const_logic_0;
end if;
end process;
sboxes_ce127_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce127 <= ap_const_logic_1;
else
sboxes_ce127 <= ap_const_logic_0;
end if;
end process;
sboxes_ce128_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce128 <= ap_const_logic_1;
else
sboxes_ce128 <= ap_const_logic_0;
end if;
end process;
sboxes_ce129_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce129 <= ap_const_logic_1;
else
sboxes_ce129 <= ap_const_logic_0;
end if;
end process;
sboxes_ce13_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce13 <= ap_const_logic_1;
else
sboxes_ce13 <= ap_const_logic_0;
end if;
end process;
sboxes_ce130_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce130 <= ap_const_logic_1;
else
sboxes_ce130 <= ap_const_logic_0;
end if;
end process;
sboxes_ce131_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce131 <= ap_const_logic_1;
else
sboxes_ce131 <= ap_const_logic_0;
end if;
end process;
sboxes_ce132_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce132 <= ap_const_logic_1;
else
sboxes_ce132 <= ap_const_logic_0;
end if;
end process;
sboxes_ce133_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce133 <= ap_const_logic_1;
else
sboxes_ce133 <= ap_const_logic_0;
end if;
end process;
sboxes_ce134_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce134 <= ap_const_logic_1;
else
sboxes_ce134 <= ap_const_logic_0;
end if;
end process;
sboxes_ce135_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce135 <= ap_const_logic_1;
else
sboxes_ce135 <= ap_const_logic_0;
end if;
end process;
sboxes_ce136_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce136 <= ap_const_logic_1;
else
sboxes_ce136 <= ap_const_logic_0;
end if;
end process;
sboxes_ce137_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce137 <= ap_const_logic_1;
else
sboxes_ce137 <= ap_const_logic_0;
end if;
end process;
sboxes_ce138_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce138 <= ap_const_logic_1;
else
sboxes_ce138 <= ap_const_logic_0;
end if;
end process;
sboxes_ce139_assign_proc : process(ap_enable_reg_pp0_iter6, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
sboxes_ce139 <= ap_const_logic_1;
else
sboxes_ce139 <= ap_const_logic_0;
end if;
end process;
sboxes_ce14_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce14 <= ap_const_logic_1;
else
sboxes_ce14 <= ap_const_logic_0;
end if;
end process;
sboxes_ce140_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce140 <= ap_const_logic_1;
else
sboxes_ce140 <= ap_const_logic_0;
end if;
end process;
sboxes_ce141_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce141 <= ap_const_logic_1;
else
sboxes_ce141 <= ap_const_logic_0;
end if;
end process;
sboxes_ce142_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce142 <= ap_const_logic_1;
else
sboxes_ce142 <= ap_const_logic_0;
end if;
end process;
sboxes_ce143_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce143 <= ap_const_logic_1;
else
sboxes_ce143 <= ap_const_logic_0;
end if;
end process;
sboxes_ce144_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce144 <= ap_const_logic_1;
else
sboxes_ce144 <= ap_const_logic_0;
end if;
end process;
sboxes_ce145_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce145 <= ap_const_logic_1;
else
sboxes_ce145 <= ap_const_logic_0;
end if;
end process;
sboxes_ce146_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce146 <= ap_const_logic_1;
else
sboxes_ce146 <= ap_const_logic_0;
end if;
end process;
sboxes_ce147_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce147 <= ap_const_logic_1;
else
sboxes_ce147 <= ap_const_logic_0;
end if;
end process;
sboxes_ce148_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce148 <= ap_const_logic_1;
else
sboxes_ce148 <= ap_const_logic_0;
end if;
end process;
sboxes_ce149_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce149 <= ap_const_logic_1;
else
sboxes_ce149 <= ap_const_logic_0;
end if;
end process;
sboxes_ce15_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce15 <= ap_const_logic_1;
else
sboxes_ce15 <= ap_const_logic_0;
end if;
end process;
sboxes_ce150_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce150 <= ap_const_logic_1;
else
sboxes_ce150 <= ap_const_logic_0;
end if;
end process;
sboxes_ce151_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce151 <= ap_const_logic_1;
else
sboxes_ce151 <= ap_const_logic_0;
end if;
end process;
sboxes_ce152_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce152 <= ap_const_logic_1;
else
sboxes_ce152 <= ap_const_logic_0;
end if;
end process;
sboxes_ce153_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce153 <= ap_const_logic_1;
else
sboxes_ce153 <= ap_const_logic_0;
end if;
end process;
sboxes_ce154_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce154 <= ap_const_logic_1;
else
sboxes_ce154 <= ap_const_logic_0;
end if;
end process;
sboxes_ce155_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce155 <= ap_const_logic_1;
else
sboxes_ce155 <= ap_const_logic_0;
end if;
end process;
sboxes_ce156_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce156 <= ap_const_logic_1;
else
sboxes_ce156 <= ap_const_logic_0;
end if;
end process;
sboxes_ce157_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce157 <= ap_const_logic_1;
else
sboxes_ce157 <= ap_const_logic_0;
end if;
end process;
sboxes_ce158_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce158 <= ap_const_logic_1;
else
sboxes_ce158 <= ap_const_logic_0;
end if;
end process;
sboxes_ce159_assign_proc : process(ap_enable_reg_pp0_iter7, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
sboxes_ce159 <= ap_const_logic_1;
else
sboxes_ce159 <= ap_const_logic_0;
end if;
end process;
sboxes_ce16_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce16 <= ap_const_logic_1;
else
sboxes_ce16 <= ap_const_logic_0;
end if;
end process;
sboxes_ce160_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce160 <= ap_const_logic_1;
else
sboxes_ce160 <= ap_const_logic_0;
end if;
end process;
sboxes_ce161_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce161 <= ap_const_logic_1;
else
sboxes_ce161 <= ap_const_logic_0;
end if;
end process;
sboxes_ce162_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce162 <= ap_const_logic_1;
else
sboxes_ce162 <= ap_const_logic_0;
end if;
end process;
sboxes_ce163_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce163 <= ap_const_logic_1;
else
sboxes_ce163 <= ap_const_logic_0;
end if;
end process;
sboxes_ce164_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce164 <= ap_const_logic_1;
else
sboxes_ce164 <= ap_const_logic_0;
end if;
end process;
sboxes_ce165_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce165 <= ap_const_logic_1;
else
sboxes_ce165 <= ap_const_logic_0;
end if;
end process;
sboxes_ce166_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce166 <= ap_const_logic_1;
else
sboxes_ce166 <= ap_const_logic_0;
end if;
end process;
sboxes_ce167_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce167 <= ap_const_logic_1;
else
sboxes_ce167 <= ap_const_logic_0;
end if;
end process;
sboxes_ce168_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce168 <= ap_const_logic_1;
else
sboxes_ce168 <= ap_const_logic_0;
end if;
end process;
sboxes_ce169_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce169 <= ap_const_logic_1;
else
sboxes_ce169 <= ap_const_logic_0;
end if;
end process;
sboxes_ce17_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce17 <= ap_const_logic_1;
else
sboxes_ce17 <= ap_const_logic_0;
end if;
end process;
sboxes_ce170_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce170 <= ap_const_logic_1;
else
sboxes_ce170 <= ap_const_logic_0;
end if;
end process;
sboxes_ce171_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce171 <= ap_const_logic_1;
else
sboxes_ce171 <= ap_const_logic_0;
end if;
end process;
sboxes_ce172_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce172 <= ap_const_logic_1;
else
sboxes_ce172 <= ap_const_logic_0;
end if;
end process;
sboxes_ce173_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce173 <= ap_const_logic_1;
else
sboxes_ce173 <= ap_const_logic_0;
end if;
end process;
sboxes_ce174_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce174 <= ap_const_logic_1;
else
sboxes_ce174 <= ap_const_logic_0;
end if;
end process;
sboxes_ce175_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce175 <= ap_const_logic_1;
else
sboxes_ce175 <= ap_const_logic_0;
end if;
end process;
sboxes_ce176_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce176 <= ap_const_logic_1;
else
sboxes_ce176 <= ap_const_logic_0;
end if;
end process;
sboxes_ce177_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce177 <= ap_const_logic_1;
else
sboxes_ce177 <= ap_const_logic_0;
end if;
end process;
sboxes_ce178_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce178 <= ap_const_logic_1;
else
sboxes_ce178 <= ap_const_logic_0;
end if;
end process;
sboxes_ce179_assign_proc : process(ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
sboxes_ce179 <= ap_const_logic_1;
else
sboxes_ce179 <= ap_const_logic_0;
end if;
end process;
sboxes_ce18_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce18 <= ap_const_logic_1;
else
sboxes_ce18 <= ap_const_logic_0;
end if;
end process;
sboxes_ce180_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce180 <= ap_const_logic_1;
else
sboxes_ce180 <= ap_const_logic_0;
end if;
end process;
sboxes_ce181_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce181 <= ap_const_logic_1;
else
sboxes_ce181 <= ap_const_logic_0;
end if;
end process;
sboxes_ce182_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce182 <= ap_const_logic_1;
else
sboxes_ce182 <= ap_const_logic_0;
end if;
end process;
sboxes_ce183_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce183 <= ap_const_logic_1;
else
sboxes_ce183 <= ap_const_logic_0;
end if;
end process;
sboxes_ce184_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce184 <= ap_const_logic_1;
else
sboxes_ce184 <= ap_const_logic_0;
end if;
end process;
sboxes_ce185_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce185 <= ap_const_logic_1;
else
sboxes_ce185 <= ap_const_logic_0;
end if;
end process;
sboxes_ce186_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce186 <= ap_const_logic_1;
else
sboxes_ce186 <= ap_const_logic_0;
end if;
end process;
sboxes_ce187_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce187 <= ap_const_logic_1;
else
sboxes_ce187 <= ap_const_logic_0;
end if;
end process;
sboxes_ce188_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce188 <= ap_const_logic_1;
else
sboxes_ce188 <= ap_const_logic_0;
end if;
end process;
sboxes_ce189_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce189 <= ap_const_logic_1;
else
sboxes_ce189 <= ap_const_logic_0;
end if;
end process;
sboxes_ce19_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce19 <= ap_const_logic_1;
else
sboxes_ce19 <= ap_const_logic_0;
end if;
end process;
sboxes_ce190_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce190 <= ap_const_logic_1;
else
sboxes_ce190 <= ap_const_logic_0;
end if;
end process;
sboxes_ce191_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce191 <= ap_const_logic_1;
else
sboxes_ce191 <= ap_const_logic_0;
end if;
end process;
sboxes_ce192_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce192 <= ap_const_logic_1;
else
sboxes_ce192 <= ap_const_logic_0;
end if;
end process;
sboxes_ce193_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce193 <= ap_const_logic_1;
else
sboxes_ce193 <= ap_const_logic_0;
end if;
end process;
sboxes_ce194_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce194 <= ap_const_logic_1;
else
sboxes_ce194 <= ap_const_logic_0;
end if;
end process;
sboxes_ce195_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce195 <= ap_const_logic_1;
else
sboxes_ce195 <= ap_const_logic_0;
end if;
end process;
sboxes_ce196_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce196 <= ap_const_logic_1;
else
sboxes_ce196 <= ap_const_logic_0;
end if;
end process;
sboxes_ce197_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce197 <= ap_const_logic_1;
else
sboxes_ce197 <= ap_const_logic_0;
end if;
end process;
sboxes_ce198_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce198 <= ap_const_logic_1;
else
sboxes_ce198 <= ap_const_logic_0;
end if;
end process;
sboxes_ce199_assign_proc : process(ap_enable_reg_pp0_iter9, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
sboxes_ce199 <= ap_const_logic_1;
else
sboxes_ce199 <= ap_const_logic_0;
end if;
end process;
sboxes_ce2_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce2 <= ap_const_logic_1;
else
sboxes_ce2 <= ap_const_logic_0;
end if;
end process;
sboxes_ce20_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce20 <= ap_const_logic_1;
else
sboxes_ce20 <= ap_const_logic_0;
end if;
end process;
sboxes_ce21_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce21 <= ap_const_logic_1;
else
sboxes_ce21 <= ap_const_logic_0;
end if;
end process;
sboxes_ce22_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce22 <= ap_const_logic_1;
else
sboxes_ce22 <= ap_const_logic_0;
end if;
end process;
sboxes_ce23_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce23 <= ap_const_logic_1;
else
sboxes_ce23 <= ap_const_logic_0;
end if;
end process;
sboxes_ce24_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce24 <= ap_const_logic_1;
else
sboxes_ce24 <= ap_const_logic_0;
end if;
end process;
sboxes_ce25_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce25 <= ap_const_logic_1;
else
sboxes_ce25 <= ap_const_logic_0;
end if;
end process;
sboxes_ce26_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce26 <= ap_const_logic_1;
else
sboxes_ce26 <= ap_const_logic_0;
end if;
end process;
sboxes_ce27_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce27 <= ap_const_logic_1;
else
sboxes_ce27 <= ap_const_logic_0;
end if;
end process;
sboxes_ce28_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce28 <= ap_const_logic_1;
else
sboxes_ce28 <= ap_const_logic_0;
end if;
end process;
sboxes_ce29_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce29 <= ap_const_logic_1;
else
sboxes_ce29 <= ap_const_logic_0;
end if;
end process;
sboxes_ce3_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce3 <= ap_const_logic_1;
else
sboxes_ce3 <= ap_const_logic_0;
end if;
end process;
sboxes_ce30_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce30 <= ap_const_logic_1;
else
sboxes_ce30 <= ap_const_logic_0;
end if;
end process;
sboxes_ce31_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce31 <= ap_const_logic_1;
else
sboxes_ce31 <= ap_const_logic_0;
end if;
end process;
sboxes_ce32_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce32 <= ap_const_logic_1;
else
sboxes_ce32 <= ap_const_logic_0;
end if;
end process;
sboxes_ce33_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce33 <= ap_const_logic_1;
else
sboxes_ce33 <= ap_const_logic_0;
end if;
end process;
sboxes_ce34_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce34 <= ap_const_logic_1;
else
sboxes_ce34 <= ap_const_logic_0;
end if;
end process;
sboxes_ce35_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce35 <= ap_const_logic_1;
else
sboxes_ce35 <= ap_const_logic_0;
end if;
end process;
sboxes_ce36_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce36 <= ap_const_logic_1;
else
sboxes_ce36 <= ap_const_logic_0;
end if;
end process;
sboxes_ce37_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce37 <= ap_const_logic_1;
else
sboxes_ce37 <= ap_const_logic_0;
end if;
end process;
sboxes_ce38_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce38 <= ap_const_logic_1;
else
sboxes_ce38 <= ap_const_logic_0;
end if;
end process;
sboxes_ce39_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
sboxes_ce39 <= ap_const_logic_1;
else
sboxes_ce39 <= ap_const_logic_0;
end if;
end process;
sboxes_ce4_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce4 <= ap_const_logic_1;
else
sboxes_ce4 <= ap_const_logic_0;
end if;
end process;
sboxes_ce40_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce40 <= ap_const_logic_1;
else
sboxes_ce40 <= ap_const_logic_0;
end if;
end process;
sboxes_ce41_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce41 <= ap_const_logic_1;
else
sboxes_ce41 <= ap_const_logic_0;
end if;
end process;
sboxes_ce42_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce42 <= ap_const_logic_1;
else
sboxes_ce42 <= ap_const_logic_0;
end if;
end process;
sboxes_ce43_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce43 <= ap_const_logic_1;
else
sboxes_ce43 <= ap_const_logic_0;
end if;
end process;
sboxes_ce44_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce44 <= ap_const_logic_1;
else
sboxes_ce44 <= ap_const_logic_0;
end if;
end process;
sboxes_ce45_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce45 <= ap_const_logic_1;
else
sboxes_ce45 <= ap_const_logic_0;
end if;
end process;
sboxes_ce46_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce46 <= ap_const_logic_1;
else
sboxes_ce46 <= ap_const_logic_0;
end if;
end process;
sboxes_ce47_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce47 <= ap_const_logic_1;
else
sboxes_ce47 <= ap_const_logic_0;
end if;
end process;
sboxes_ce48_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce48 <= ap_const_logic_1;
else
sboxes_ce48 <= ap_const_logic_0;
end if;
end process;
sboxes_ce49_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce49 <= ap_const_logic_1;
else
sboxes_ce49 <= ap_const_logic_0;
end if;
end process;
sboxes_ce5_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce5 <= ap_const_logic_1;
else
sboxes_ce5 <= ap_const_logic_0;
end if;
end process;
sboxes_ce50_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce50 <= ap_const_logic_1;
else
sboxes_ce50 <= ap_const_logic_0;
end if;
end process;
sboxes_ce51_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce51 <= ap_const_logic_1;
else
sboxes_ce51 <= ap_const_logic_0;
end if;
end process;
sboxes_ce52_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce52 <= ap_const_logic_1;
else
sboxes_ce52 <= ap_const_logic_0;
end if;
end process;
sboxes_ce53_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce53 <= ap_const_logic_1;
else
sboxes_ce53 <= ap_const_logic_0;
end if;
end process;
sboxes_ce54_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce54 <= ap_const_logic_1;
else
sboxes_ce54 <= ap_const_logic_0;
end if;
end process;
sboxes_ce55_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce55 <= ap_const_logic_1;
else
sboxes_ce55 <= ap_const_logic_0;
end if;
end process;
sboxes_ce56_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce56 <= ap_const_logic_1;
else
sboxes_ce56 <= ap_const_logic_0;
end if;
end process;
sboxes_ce57_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce57 <= ap_const_logic_1;
else
sboxes_ce57 <= ap_const_logic_0;
end if;
end process;
sboxes_ce58_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce58 <= ap_const_logic_1;
else
sboxes_ce58 <= ap_const_logic_0;
end if;
end process;
sboxes_ce59_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
sboxes_ce59 <= ap_const_logic_1;
else
sboxes_ce59 <= ap_const_logic_0;
end if;
end process;
sboxes_ce6_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce6 <= ap_const_logic_1;
else
sboxes_ce6 <= ap_const_logic_0;
end if;
end process;
sboxes_ce60_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce60 <= ap_const_logic_1;
else
sboxes_ce60 <= ap_const_logic_0;
end if;
end process;
sboxes_ce61_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce61 <= ap_const_logic_1;
else
sboxes_ce61 <= ap_const_logic_0;
end if;
end process;
sboxes_ce62_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce62 <= ap_const_logic_1;
else
sboxes_ce62 <= ap_const_logic_0;
end if;
end process;
sboxes_ce63_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce63 <= ap_const_logic_1;
else
sboxes_ce63 <= ap_const_logic_0;
end if;
end process;
sboxes_ce64_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce64 <= ap_const_logic_1;
else
sboxes_ce64 <= ap_const_logic_0;
end if;
end process;
sboxes_ce65_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce65 <= ap_const_logic_1;
else
sboxes_ce65 <= ap_const_logic_0;
end if;
end process;
sboxes_ce66_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce66 <= ap_const_logic_1;
else
sboxes_ce66 <= ap_const_logic_0;
end if;
end process;
sboxes_ce67_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce67 <= ap_const_logic_1;
else
sboxes_ce67 <= ap_const_logic_0;
end if;
end process;
sboxes_ce68_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce68 <= ap_const_logic_1;
else
sboxes_ce68 <= ap_const_logic_0;
end if;
end process;
sboxes_ce69_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce69 <= ap_const_logic_1;
else
sboxes_ce69 <= ap_const_logic_0;
end if;
end process;
sboxes_ce7_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce7 <= ap_const_logic_1;
else
sboxes_ce7 <= ap_const_logic_0;
end if;
end process;
sboxes_ce70_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce70 <= ap_const_logic_1;
else
sboxes_ce70 <= ap_const_logic_0;
end if;
end process;
sboxes_ce71_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce71 <= ap_const_logic_1;
else
sboxes_ce71 <= ap_const_logic_0;
end if;
end process;
sboxes_ce72_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce72 <= ap_const_logic_1;
else
sboxes_ce72 <= ap_const_logic_0;
end if;
end process;
sboxes_ce73_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce73 <= ap_const_logic_1;
else
sboxes_ce73 <= ap_const_logic_0;
end if;
end process;
sboxes_ce74_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce74 <= ap_const_logic_1;
else
sboxes_ce74 <= ap_const_logic_0;
end if;
end process;
sboxes_ce75_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce75 <= ap_const_logic_1;
else
sboxes_ce75 <= ap_const_logic_0;
end if;
end process;
sboxes_ce76_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce76 <= ap_const_logic_1;
else
sboxes_ce76 <= ap_const_logic_0;
end if;
end process;
sboxes_ce77_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce77 <= ap_const_logic_1;
else
sboxes_ce77 <= ap_const_logic_0;
end if;
end process;
sboxes_ce78_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce78 <= ap_const_logic_1;
else
sboxes_ce78 <= ap_const_logic_0;
end if;
end process;
sboxes_ce79_assign_proc : process(ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
sboxes_ce79 <= ap_const_logic_1;
else
sboxes_ce79 <= ap_const_logic_0;
end if;
end process;
sboxes_ce8_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce8 <= ap_const_logic_1;
else
sboxes_ce8 <= ap_const_logic_0;
end if;
end process;
sboxes_ce80_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce80 <= ap_const_logic_1;
else
sboxes_ce80 <= ap_const_logic_0;
end if;
end process;
sboxes_ce81_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce81 <= ap_const_logic_1;
else
sboxes_ce81 <= ap_const_logic_0;
end if;
end process;
sboxes_ce82_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce82 <= ap_const_logic_1;
else
sboxes_ce82 <= ap_const_logic_0;
end if;
end process;
sboxes_ce83_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce83 <= ap_const_logic_1;
else
sboxes_ce83 <= ap_const_logic_0;
end if;
end process;
sboxes_ce84_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce84 <= ap_const_logic_1;
else
sboxes_ce84 <= ap_const_logic_0;
end if;
end process;
sboxes_ce85_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce85 <= ap_const_logic_1;
else
sboxes_ce85 <= ap_const_logic_0;
end if;
end process;
sboxes_ce86_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce86 <= ap_const_logic_1;
else
sboxes_ce86 <= ap_const_logic_0;
end if;
end process;
sboxes_ce87_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce87 <= ap_const_logic_1;
else
sboxes_ce87 <= ap_const_logic_0;
end if;
end process;
sboxes_ce88_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce88 <= ap_const_logic_1;
else
sboxes_ce88 <= ap_const_logic_0;
end if;
end process;
sboxes_ce89_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce89 <= ap_const_logic_1;
else
sboxes_ce89 <= ap_const_logic_0;
end if;
end process;
sboxes_ce9_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_start) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
sboxes_ce9 <= ap_const_logic_1;
else
sboxes_ce9 <= ap_const_logic_0;
end if;
end process;
sboxes_ce90_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce90 <= ap_const_logic_1;
else
sboxes_ce90 <= ap_const_logic_0;
end if;
end process;
sboxes_ce91_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce91 <= ap_const_logic_1;
else
sboxes_ce91 <= ap_const_logic_0;
end if;
end process;
sboxes_ce92_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce92 <= ap_const_logic_1;
else
sboxes_ce92 <= ap_const_logic_0;
end if;
end process;
sboxes_ce93_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce93 <= ap_const_logic_1;
else
sboxes_ce93 <= ap_const_logic_0;
end if;
end process;
sboxes_ce94_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce94 <= ap_const_logic_1;
else
sboxes_ce94 <= ap_const_logic_0;
end if;
end process;
sboxes_ce95_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce95 <= ap_const_logic_1;
else
sboxes_ce95 <= ap_const_logic_0;
end if;
end process;
sboxes_ce96_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce96 <= ap_const_logic_1;
else
sboxes_ce96 <= ap_const_logic_0;
end if;
end process;
sboxes_ce97_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce97 <= ap_const_logic_1;
else
sboxes_ce97 <= ap_const_logic_0;
end if;
end process;
sboxes_ce98_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce98 <= ap_const_logic_1;
else
sboxes_ce98 <= ap_const_logic_0;
end if;
end process;
sboxes_ce99_assign_proc : process(ap_enable_reg_pp0_iter4, ap_block_pp0_stage0_flag00011001, ap_ce)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
sboxes_ce99 <= ap_const_logic_1;
else
sboxes_ce99 <= ap_const_logic_0;
end if;
end process;
tmp100_fu_6663_p2 <= (tmp_47_3_fu_5957_p2 xor tmp_68_3_fu_6564_p2);
tmp101_fu_6675_p2 <= (sboxes_q64 xor rv_2_3_1_fu_6137_p3);
tmp102_fu_6681_p2 <= (e_3_1_fu_6111_p2 xor tmp_69_3_fu_6569_p2);
tmp103_fu_6693_p2 <= (sboxes_q69 xor e_3_1_fu_6111_p2);
tmp104_fu_6699_p2 <= (rv_5_3_1_fu_6171_p3 xor tmp_70_3_fu_6574_p2);
tmp105_fu_6711_p2 <= (sboxes_q63 xor x_assign_375_1_fu_6099_p2);
tmp106_fu_6717_p2 <= (rv_8_3_1_fu_6205_p3 xor tmp_71_3_fu_6579_p2);
tmp107_fu_6729_p2 <= (tmp_47_3_1_fu_6105_p2 xor tmp_72_3_fu_6584_p2);
tmp108_fu_6741_p2 <= (sboxes_q68 xor rv_2_3_2_fu_6285_p3);
tmp109_fu_6752_p2 <= (tmp110_fu_6747_p2 xor e_3_2_fu_6259_p2);
tmp10_fu_3587_p2 <= (sboxes_q9 xor e_0_1_fu_2985_p2);
tmp110_fu_6747_p2 <= (tmp_69_3_fu_6569_p2 xor tmp_73_2_reg_12941);
tmp111_fu_6764_p2 <= (sboxes_q73 xor e_3_2_fu_6259_p2);
tmp112_fu_6775_p2 <= (tmp113_fu_6770_p2 xor rv_5_3_2_fu_6319_p3);
tmp113_fu_6770_p2 <= (tmp_70_3_fu_6574_p2 xor tmp_74_2_reg_12947);
tmp114_fu_6787_p2 <= (sboxes_q67 xor x_assign_375_2_fu_6247_p2);
tmp115_fu_6798_p2 <= (tmp116_fu_6793_p2 xor rv_8_3_2_fu_6353_p3);
tmp116_fu_6793_p2 <= (tmp_71_3_fu_6579_p2 xor tmp_75_2_reg_12953);
tmp117_fu_6810_p2 <= (rv_11_3_2_fu_6387_p3 xor tmp_47_3_2_fu_6253_p2);
tmp118_fu_6816_p2 <= (tmp_72_3_fu_6584_p2 xor tmp_76_2_reg_12959);
tmp119_fu_6827_p2 <= (sboxes_q72 xor rv_2_3_3_fu_6433_p3);
tmp11_fu_3593_p2 <= (rv_5_0_1_fu_3045_p3 xor tmp_70_fu_3448_p2);
tmp120_fu_6833_p2 <= (e_3_3_fu_6407_p2 xor tmp_77_3_fu_6589_p2);
tmp121_fu_6845_p2 <= (sboxes_q61 xor e_3_3_fu_6407_p2);
tmp122_fu_6851_p2 <= (rv_5_3_3_fu_6467_p3 xor tmp_78_3_fu_6594_p2);
tmp123_fu_6863_p2 <= (sboxes_q71 xor x_assign_375_3_fu_6395_p2);
tmp124_fu_6869_p2 <= (rv_8_3_3_fu_6501_p3 xor tmp_79_3_fu_6599_p2);
tmp125_fu_6881_p2 <= (tmp_47_3_3_fu_6401_p2 xor tmp_80_3_fu_6604_p2);
tmp126_fu_7585_p2 <= (tmp_65_3_reg_13065 xor ap_const_lv8_10);
tmp127_fu_7651_p2 <= (sboxes_q80 xor rv_2_4_fu_7031_p3);
tmp128_fu_7657_p2 <= (e_4_fu_7005_p2 xor tmp_65_4_fu_7590_p2);
tmp129_fu_7669_p2 <= (sboxes_q85 xor e_4_fu_7005_p2);
tmp12_fu_3605_p2 <= (sboxes_q3 xor x_assign_0_1_fu_2973_p2);
tmp130_fu_7675_p2 <= (rv_5_4_fu_7065_p3 xor tmp_66_4_fu_7596_p2);
tmp131_fu_7687_p2 <= (sboxes_q95 xor x_assign_4_fu_6993_p2);
tmp132_fu_7693_p2 <= (rv_8_4_fu_7099_p3 xor tmp_67_4_fu_7601_p2);
tmp133_fu_7705_p2 <= (tmp_47_4_fu_6999_p2 xor tmp_68_4_fu_7606_p2);
tmp134_fu_7717_p2 <= (sboxes_q84 xor rv_2_4_1_fu_7179_p3);
tmp135_fu_7728_p2 <= (tmp136_fu_7723_p2 xor e_4_1_fu_7153_p2);
tmp136_fu_7723_p2 <= (tmp_65_4_fu_7590_p2 xor tmp_69_3_reg_13085);
tmp137_fu_7740_p2 <= (sboxes_q89 xor e_4_1_fu_7153_p2);
tmp138_fu_7751_p2 <= (tmp139_fu_7746_p2 xor rv_5_4_1_fu_7213_p3);
tmp139_fu_7746_p2 <= (tmp_66_4_fu_7596_p2 xor tmp_70_3_reg_13091);
tmp13_fu_3611_p2 <= (rv_8_0_1_fu_3079_p3 xor tmp_71_fu_3453_p2);
tmp140_fu_7763_p2 <= (sboxes_q83 xor x_assign_4_1_fu_7141_p2);
tmp141_fu_7774_p2 <= (tmp142_fu_7769_p2 xor rv_8_4_1_fu_7247_p3);
tmp142_fu_7769_p2 <= (tmp_67_4_fu_7601_p2 xor tmp_71_3_reg_13097);
tmp143_fu_7786_p2 <= (rv_11_4_1_fu_7281_p3 xor tmp_47_4_1_fu_7147_p2);
tmp144_fu_7792_p2 <= (tmp_68_4_fu_7606_p2 xor tmp_72_3_reg_13103);
tmp145_fu_7803_p2 <= (sboxes_q88 xor rv_2_4_2_fu_7327_p3);
tmp146_fu_7809_p2 <= (e_4_2_fu_7301_p2 xor tmp_73_4_fu_7611_p2);
tmp147_fu_7821_p2 <= (sboxes_q93 xor e_4_2_fu_7301_p2);
tmp148_fu_7827_p2 <= (rv_5_4_2_fu_7361_p3 xor tmp_74_4_fu_7616_p2);
tmp149_fu_7839_p2 <= (sboxes_q87 xor x_assign_4_2_fu_7289_p2);
tmp14_fu_3623_p2 <= (tmp_47_0_1_fu_2979_p2 xor tmp_72_fu_3458_p2);
tmp150_fu_7845_p2 <= (rv_8_4_2_fu_7395_p3 xor tmp_75_4_fu_7621_p2);
tmp151_fu_7857_p2 <= (tmp_47_4_2_fu_7295_p2 xor tmp_76_4_fu_7626_p2);
tmp152_fu_7869_p2 <= (sboxes_q92 xor rv_2_4_3_fu_7475_p3);
tmp153_fu_7875_p2 <= (e_4_3_fu_7449_p2 xor tmp_77_4_fu_7631_p2);
tmp154_fu_7887_p2 <= (sboxes_q81 xor e_4_3_fu_7449_p2);
tmp155_fu_7893_p2 <= (rv_5_4_3_fu_7509_p3 xor tmp_78_4_fu_7636_p2);
tmp156_fu_7905_p2 <= (sboxes_q91 xor x_assign_4_3_fu_7437_p2);
tmp157_fu_7911_p2 <= (rv_8_4_3_fu_7543_p3 xor tmp_79_4_fu_7641_p2);
tmp158_fu_7923_p2 <= (tmp_47_4_3_fu_7443_p2 xor tmp_80_4_fu_7646_p2);
tmp159_fu_8693_p2 <= (sboxes_q100 xor rv_2_5_fu_8073_p3);
tmp15_fu_3635_p2 <= (sboxes_q8 xor rv_2_0_2_fu_3159_p3);
tmp160_fu_8699_p2 <= (e_5_fu_8047_p2 xor tmp_65_5_fu_8633_p2);
tmp161_fu_8711_p2 <= (sboxes_q105 xor e_5_fu_8047_p2);
tmp162_fu_8717_p2 <= (rv_5_5_fu_8107_p3 xor tmp_66_5_fu_8638_p2);
tmp163_fu_8729_p2 <= (sboxes_q115 xor x_assign_5_fu_8035_p2);
tmp164_fu_8735_p2 <= (rv_8_5_fu_8141_p3 xor tmp_67_5_fu_8643_p2);
tmp165_fu_8747_p2 <= (tmp_47_5_fu_8041_p2 xor tmp_68_5_fu_8648_p2);
tmp166_fu_8759_p2 <= (sboxes_q104 xor rv_2_5_1_fu_8221_p3);
tmp167_fu_8765_p2 <= (e_5_1_fu_8195_p2 xor tmp_69_5_fu_8653_p2);
tmp168_fu_8777_p2 <= (sboxes_q109 xor e_5_1_fu_8195_p2);
tmp169_fu_8783_p2 <= (rv_5_5_1_fu_8255_p3 xor tmp_70_5_fu_8658_p2);
tmp16_fu_3641_p2 <= (e_0_2_fu_3133_p2 xor tmp_73_fu_3463_p2);
tmp170_fu_8795_p2 <= (sboxes_q103 xor x_assign_5_1_fu_8183_p2);
tmp171_fu_8801_p2 <= (rv_8_5_1_fu_8289_p3 xor tmp_71_5_fu_8663_p2);
tmp172_fu_8813_p2 <= (tmp_47_5_1_fu_8189_p2 xor tmp_72_5_fu_8668_p2);
tmp173_fu_8825_p2 <= (sboxes_q108 xor rv_2_5_2_fu_8369_p3);
tmp174_fu_8836_p2 <= (tmp175_fu_8831_p2 xor e_5_2_fu_8343_p2);
tmp175_fu_8831_p2 <= (tmp_69_5_fu_8653_p2 xor tmp_73_4_reg_13257);
tmp176_fu_8848_p2 <= (sboxes_q113 xor e_5_2_fu_8343_p2);
tmp177_fu_8859_p2 <= (tmp178_fu_8854_p2 xor rv_5_5_2_fu_8403_p3);
tmp178_fu_8854_p2 <= (tmp_70_5_fu_8658_p2 xor tmp_74_4_reg_13263);
tmp179_fu_8871_p2 <= (sboxes_q107 xor x_assign_5_2_fu_8331_p2);
tmp17_fu_3653_p2 <= (sboxes_q13 xor e_0_2_fu_3133_p2);
tmp180_fu_8882_p2 <= (tmp181_fu_8877_p2 xor rv_8_5_2_fu_8437_p3);
tmp181_fu_8877_p2 <= (tmp_71_5_fu_8663_p2 xor tmp_75_4_reg_13269);
tmp182_fu_8894_p2 <= (rv_11_5_2_fu_8471_p3 xor tmp_47_5_2_fu_8337_p2);
tmp183_fu_8900_p2 <= (tmp_72_5_fu_8668_p2 xor tmp_76_4_reg_13275);
tmp184_fu_8911_p2 <= (sboxes_q112 xor rv_2_5_3_fu_8517_p3);
tmp185_fu_8917_p2 <= (e_5_3_fu_8491_p2 xor tmp_77_5_fu_8673_p2);
tmp186_fu_8929_p2 <= (sboxes_q101 xor e_5_3_fu_8491_p2);
tmp187_fu_8935_p2 <= (rv_5_5_3_fu_8551_p3 xor tmp_78_5_fu_8678_p2);
tmp188_fu_8947_p2 <= (sboxes_q111 xor x_assign_5_3_fu_8479_p2);
tmp189_fu_8953_p2 <= (rv_8_5_3_fu_8585_p3 xor tmp_79_5_fu_8683_p2);
tmp18_fu_3659_p2 <= (rv_5_0_2_fu_3193_p3 xor tmp_74_fu_3468_p2);
tmp190_fu_8965_p2 <= (tmp_47_5_3_fu_8485_p2 xor tmp_80_5_fu_8688_p2);
tmp191_fu_9669_p2 <= (tmp_65_5_reg_13381 xor ap_const_lv8_40);
tmp192_fu_9735_p2 <= (sboxes_q120 xor rv_2_6_fu_9115_p3);
tmp193_fu_9741_p2 <= (e_6_fu_9089_p2 xor tmp_65_6_fu_9674_p2);
tmp194_fu_9753_p2 <= (sboxes_q125 xor e_6_fu_9089_p2);
tmp195_fu_9759_p2 <= (rv_5_6_fu_9149_p3 xor tmp_66_6_fu_9680_p2);
tmp196_fu_9771_p2 <= (sboxes_q135 xor x_assign_6_fu_9077_p2);
tmp197_fu_9777_p2 <= (rv_8_6_fu_9183_p3 xor tmp_67_6_fu_9685_p2);
tmp198_fu_9789_p2 <= (tmp_47_6_fu_9083_p2 xor tmp_68_6_fu_9690_p2);
tmp199_fu_9801_p2 <= (sboxes_q124 xor rv_2_6_1_fu_9263_p3);
tmp19_fu_3671_p2 <= (sboxes_q7 xor x_assign_0_2_fu_3121_p2);
tmp1_fu_3503_p2 <= (sboxes_q0 xor rv_2_fu_2863_p3);
tmp200_fu_9812_p2 <= (tmp201_fu_9807_p2 xor e_6_1_fu_9237_p2);
tmp201_fu_9807_p2 <= (tmp_65_6_fu_9674_p2 xor tmp_69_5_reg_13401);
tmp202_fu_9824_p2 <= (sboxes_q129 xor e_6_1_fu_9237_p2);
tmp203_fu_9835_p2 <= (tmp204_fu_9830_p2 xor rv_5_6_1_fu_9297_p3);
tmp204_fu_9830_p2 <= (tmp_66_6_fu_9680_p2 xor tmp_70_5_reg_13407);
tmp205_fu_9847_p2 <= (sboxes_q123 xor x_assign_6_1_fu_9225_p2);
tmp206_fu_9858_p2 <= (tmp207_fu_9853_p2 xor rv_8_6_1_fu_9331_p3);
tmp207_fu_9853_p2 <= (tmp_67_6_fu_9685_p2 xor tmp_71_5_reg_13413);
tmp208_fu_9870_p2 <= (rv_11_6_1_fu_9365_p3 xor tmp_47_6_1_fu_9231_p2);
tmp209_fu_9876_p2 <= (tmp_68_6_fu_9690_p2 xor tmp_72_5_reg_13419);
tmp20_fu_3677_p2 <= (rv_8_0_2_fu_3227_p3 xor tmp_75_fu_3473_p2);
tmp210_fu_9887_p2 <= (sboxes_q128 xor rv_2_6_2_fu_9411_p3);
tmp211_fu_9893_p2 <= (e_6_2_fu_9385_p2 xor tmp_73_6_fu_9695_p2);
tmp212_fu_9905_p2 <= (sboxes_q133 xor e_6_2_fu_9385_p2);
tmp213_fu_9911_p2 <= (rv_5_6_2_fu_9445_p3 xor tmp_74_6_fu_9700_p2);
tmp214_fu_9923_p2 <= (sboxes_q127 xor x_assign_6_2_fu_9373_p2);
tmp215_fu_9929_p2 <= (rv_8_6_2_fu_9479_p3 xor tmp_75_6_fu_9705_p2);
tmp216_fu_9941_p2 <= (tmp_47_6_2_fu_9379_p2 xor tmp_76_6_fu_9710_p2);
tmp217_fu_9953_p2 <= (sboxes_q132 xor rv_2_6_3_fu_9559_p3);
tmp218_fu_9959_p2 <= (e_6_3_fu_9533_p2 xor tmp_77_6_fu_9715_p2);
tmp219_fu_9971_p2 <= (sboxes_q121 xor e_6_3_fu_9533_p2);
tmp21_fu_3689_p2 <= (tmp_47_0_2_fu_3127_p2 xor tmp_76_fu_3478_p2);
tmp220_fu_9977_p2 <= (rv_5_6_3_fu_9593_p3 xor tmp_78_6_fu_9720_p2);
tmp221_fu_9989_p2 <= (sboxes_q131 xor x_assign_6_3_fu_9521_p2);
tmp222_fu_9995_p2 <= (rv_8_6_3_fu_9627_p3 xor tmp_79_6_fu_9725_p2);
tmp223_fu_10007_p2 <= (tmp_47_6_3_fu_9527_p2 xor tmp_80_6_fu_9730_p2);
tmp224_fu_10777_p2 <= (sboxes_q140 xor rv_2_7_fu_10157_p3);
tmp225_fu_10783_p2 <= (e_7_fu_10131_p2 xor tmp_65_7_fu_10717_p2);
tmp226_fu_10795_p2 <= (sboxes_q145 xor e_7_fu_10131_p2);
tmp227_fu_10801_p2 <= (rv_5_7_fu_10191_p3 xor tmp_66_7_fu_10722_p2);
tmp228_fu_10813_p2 <= (sboxes_q155 xor x_assign_7_fu_10119_p2);
tmp229_fu_10819_p2 <= (rv_8_7_fu_10225_p3 xor tmp_67_7_fu_10727_p2);
tmp22_fu_3701_p2 <= (sboxes_q12 xor rv_2_0_3_fu_3307_p3);
tmp230_fu_10831_p2 <= (tmp_47_7_fu_10125_p2 xor tmp_68_7_fu_10732_p2);
tmp231_fu_10843_p2 <= (sboxes_q144 xor rv_2_7_1_fu_10305_p3);
tmp232_fu_10849_p2 <= (e_7_1_fu_10279_p2 xor tmp_69_7_fu_10737_p2);
tmp233_fu_10861_p2 <= (sboxes_q149 xor e_7_1_fu_10279_p2);
tmp234_fu_10867_p2 <= (rv_5_7_1_fu_10339_p3 xor tmp_70_7_fu_10742_p2);
tmp235_fu_10879_p2 <= (sboxes_q143 xor x_assign_7_1_fu_10267_p2);
tmp236_fu_10885_p2 <= (rv_8_7_1_fu_10373_p3 xor tmp_71_7_fu_10747_p2);
tmp237_fu_10897_p2 <= (tmp_47_7_1_fu_10273_p2 xor tmp_72_7_fu_10752_p2);
tmp238_fu_10909_p2 <= (sboxes_q148 xor rv_2_7_2_fu_10453_p3);
tmp239_fu_10920_p2 <= (tmp240_fu_10915_p2 xor e_7_2_fu_10427_p2);
tmp23_fu_3707_p2 <= (e_0_3_fu_3281_p2 xor tmp_77_fu_3483_p2);
tmp240_fu_10915_p2 <= (tmp_69_7_fu_10737_p2 xor tmp_73_6_reg_13565);
tmp241_fu_10932_p2 <= (sboxes_q153 xor e_7_2_fu_10427_p2);
tmp242_fu_10943_p2 <= (tmp243_fu_10938_p2 xor rv_5_7_2_fu_10487_p3);
tmp243_fu_10938_p2 <= (tmp_70_7_fu_10742_p2 xor tmp_74_6_reg_13571);
tmp244_fu_10955_p2 <= (sboxes_q147 xor x_assign_7_2_fu_10415_p2);
tmp245_fu_10966_p2 <= (tmp246_fu_10961_p2 xor rv_8_7_2_fu_10521_p3);
tmp246_fu_10961_p2 <= (tmp_71_7_fu_10747_p2 xor tmp_75_6_reg_13577);
tmp247_fu_10978_p2 <= (rv_11_7_2_fu_10555_p3 xor tmp_47_7_2_fu_10421_p2);
tmp248_fu_10984_p2 <= (tmp_72_7_fu_10752_p2 xor tmp_76_6_reg_13583);
tmp249_fu_10995_p2 <= (sboxes_q152 xor rv_2_7_3_fu_10601_p3);
tmp24_fu_3719_p2 <= (sboxes_q1 xor e_0_3_fu_3281_p2);
tmp250_fu_11001_p2 <= (e_7_3_fu_10575_p2 xor tmp_77_7_fu_10757_p2);
tmp251_fu_11013_p2 <= (sboxes_q141 xor e_7_3_fu_10575_p2);
tmp252_fu_11019_p2 <= (rv_5_7_3_fu_10635_p3 xor tmp_78_7_fu_10762_p2);
tmp253_fu_11031_p2 <= (sboxes_q151 xor x_assign_7_3_fu_10563_p2);
tmp254_fu_11037_p2 <= (rv_8_7_3_fu_10669_p3 xor tmp_79_7_fu_10767_p2);
tmp255_fu_11049_p2 <= (tmp_47_7_3_fu_10569_p2 xor tmp_80_7_fu_10772_p2);
tmp256_fu_11753_p2 <= (tmp_65_7_reg_13689 xor ap_const_lv8_1B);
tmp257_fu_11819_p2 <= (sboxes_q160 xor rv_2_8_fu_11199_p3);
tmp258_fu_11825_p2 <= (e_8_fu_11173_p2 xor tmp_65_8_fu_11758_p2);
tmp259_fu_11837_p2 <= (sboxes_q165 xor e_8_fu_11173_p2);
tmp25_fu_3725_p2 <= (rv_5_0_3_fu_3341_p3 xor tmp_78_fu_3488_p2);
tmp260_fu_11843_p2 <= (rv_5_8_fu_11233_p3 xor tmp_66_8_fu_11764_p2);
tmp261_fu_11855_p2 <= (sboxes_q175 xor x_assign_8_fu_11161_p2);
tmp262_fu_11861_p2 <= (rv_8_8_fu_11267_p3 xor tmp_67_8_fu_11769_p2);
tmp263_fu_11873_p2 <= (tmp_47_8_fu_11167_p2 xor tmp_68_8_fu_11774_p2);
tmp264_fu_11885_p2 <= (sboxes_q164 xor rv_2_8_1_fu_11347_p3);
tmp265_fu_11896_p2 <= (tmp266_fu_11891_p2 xor e_8_1_fu_11321_p2);
tmp266_fu_11891_p2 <= (tmp_65_8_fu_11758_p2 xor tmp_69_7_reg_13709);
tmp267_fu_11908_p2 <= (sboxes_q169 xor e_8_1_fu_11321_p2);
tmp268_fu_11919_p2 <= (tmp269_fu_11914_p2 xor rv_5_8_1_fu_11381_p3);
tmp269_fu_11914_p2 <= (tmp_66_8_fu_11764_p2 xor tmp_70_7_reg_13715);
tmp26_fu_3737_p2 <= (sboxes_q11 xor x_assign_0_3_fu_3269_p2);
tmp270_fu_11931_p2 <= (sboxes_q163 xor x_assign_8_1_fu_11309_p2);
tmp271_fu_11942_p2 <= (tmp272_fu_11937_p2 xor rv_8_8_1_fu_11415_p3);
tmp272_fu_11937_p2 <= (tmp_67_8_fu_11769_p2 xor tmp_71_7_reg_13721);
tmp273_fu_11954_p2 <= (rv_11_8_1_fu_11449_p3 xor tmp_47_8_1_fu_11315_p2);
tmp274_fu_11960_p2 <= (tmp_68_8_fu_11774_p2 xor tmp_72_7_reg_13727);
tmp275_fu_11971_p2 <= (sboxes_q168 xor rv_2_8_2_fu_11495_p3);
tmp276_fu_11977_p2 <= (e_8_2_fu_11469_p2 xor tmp_73_8_fu_11779_p2);
tmp277_fu_11989_p2 <= (sboxes_q173 xor e_8_2_fu_11469_p2);
tmp278_fu_11995_p2 <= (rv_5_8_2_fu_11529_p3 xor tmp_74_8_fu_11784_p2);
tmp279_fu_12007_p2 <= (sboxes_q167 xor x_assign_8_2_fu_11457_p2);
tmp27_fu_3743_p2 <= (rv_8_0_3_fu_3375_p3 xor tmp_79_fu_3493_p2);
tmp280_fu_12013_p2 <= (rv_8_8_2_fu_11563_p3 xor tmp_75_8_fu_11789_p2);
tmp281_fu_12025_p2 <= (tmp_47_8_2_fu_11463_p2 xor tmp_76_8_fu_11794_p2);
tmp282_fu_12037_p2 <= (sboxes_q172 xor rv_2_8_3_fu_11643_p3);
tmp283_fu_12043_p2 <= (e_8_3_fu_11617_p2 xor tmp_77_8_fu_11799_p2);
tmp284_fu_12055_p2 <= (sboxes_q161 xor e_8_3_fu_11617_p2);
tmp285_fu_12061_p2 <= (rv_5_8_3_fu_11677_p3 xor tmp_78_8_fu_11804_p2);
tmp286_fu_12073_p2 <= (sboxes_q171 xor x_assign_8_3_fu_11605_p2);
tmp287_fu_12079_p2 <= (rv_8_8_3_fu_11711_p3 xor tmp_79_8_fu_11809_p2);
tmp288_fu_12091_p2 <= (tmp_47_8_3_fu_11611_p2 xor tmp_80_8_fu_11814_p2);
tmp289_fu_12229_p2 <= (tmp_4_fu_12203_p2 xor tmp_65_8_reg_13857);
tmp28_fu_3755_p2 <= (tmp_47_0_3_fu_3275_p2 xor tmp_80_fu_3498_p2);
tmp290_fu_12240_p2 <= (sboxes_q185 xor tmp_66_8_reg_13862);
tmp291_fu_12251_p2 <= (sboxes_q190 xor tmp_67_8_reg_13867);
tmp292_fu_12262_p2 <= (sboxes_q195 xor tmp_68_8_reg_13872);
tmp293_fu_12297_p2 <= (tmp_73_8_reg_13877 xor tmp_9_fu_12209_p2);
tmp294_fu_12308_p2 <= (tmp_74_8_reg_13882 xor tmp_11_fu_12214_p2);
tmp295_fu_12319_p2 <= (tmp_75_8_reg_13887 xor tmp_12_fu_12219_p2);
tmp296_fu_12330_p2 <= (tmp_76_8_reg_13892 xor tmp_13_fu_12224_p2);
tmp297_fu_12341_p2 <= (tmp_9_fu_12209_p2 xor ap_reg_pp0_iter9_tmp_77_7_reg_13733);
tmp298_fu_12352_p2 <= (tmp_11_fu_12214_p2 xor ap_reg_pp0_iter9_tmp_78_7_reg_13739);
tmp299_fu_12363_p2 <= (tmp_12_fu_12219_p2 xor ap_reg_pp0_iter9_tmp_79_7_reg_13745);
tmp29_fu_4525_p2 <= (sboxes_q20 xor rv_2_1_fu_3905_p3);
tmp2_fu_3509_p2 <= (e_fu_2837_p2 xor tmp_65_fu_3422_p2);
tmp300_fu_12374_p2 <= (tmp_13_fu_12224_p2 xor ap_reg_pp0_iter9_tmp_80_7_reg_13751);
tmp30_fu_4531_p2 <= (e_1_fu_3879_p2 xor tmp_65_1_fu_4465_p2);
tmp31_fu_4543_p2 <= (sboxes_q25 xor e_1_fu_3879_p2);
tmp32_fu_4549_p2 <= (rv_5_1_fu_3939_p3 xor tmp_66_1_fu_4470_p2);
tmp33_fu_4561_p2 <= (sboxes_q35 xor x_assign_s_fu_3867_p2);
tmp34_fu_4567_p2 <= (rv_8_1_fu_3973_p3 xor tmp_67_1_fu_4475_p2);
tmp35_fu_4579_p2 <= (tmp_47_1_fu_3873_p2 xor tmp_68_1_fu_4480_p2);
tmp36_fu_4591_p2 <= (sboxes_q24 xor rv_2_1_1_fu_4053_p3);
tmp37_fu_4597_p2 <= (e_1_1_fu_4027_p2 xor tmp_69_1_fu_4485_p2);
tmp38_fu_4609_p2 <= (sboxes_q29 xor e_1_1_fu_4027_p2);
tmp39_fu_4615_p2 <= (rv_5_1_1_fu_4087_p3 xor tmp_70_1_fu_4490_p2);
tmp3_fu_3521_p2 <= (sboxes_q5 xor e_fu_2837_p2);
tmp40_fu_4627_p2 <= (sboxes_q23 xor x_assign_171_1_fu_4015_p2);
tmp41_fu_4633_p2 <= (rv_8_1_1_fu_4121_p3 xor tmp_71_1_fu_4495_p2);
tmp42_fu_4645_p2 <= (tmp_47_1_1_fu_4021_p2 xor tmp_72_1_fu_4500_p2);
tmp43_fu_4657_p2 <= (sboxes_q28 xor rv_2_1_2_fu_4201_p3);
tmp44_fu_4668_p2 <= (tmp45_fu_4663_p2 xor e_1_2_fu_4175_p2);
tmp45_fu_4663_p2 <= (tmp_69_1_fu_4485_p2 xor tmp_73_reg_12633);
tmp46_fu_4680_p2 <= (sboxes_q33 xor e_1_2_fu_4175_p2);
tmp47_fu_4691_p2 <= (tmp48_fu_4686_p2 xor rv_5_1_2_fu_4235_p3);
tmp48_fu_4686_p2 <= (tmp_70_1_fu_4490_p2 xor tmp_74_reg_12639);
tmp49_fu_4703_p2 <= (sboxes_q27 xor x_assign_171_2_fu_4163_p2);
tmp4_fu_3527_p2 <= (rv_5_fu_2897_p3 xor tmp_66_fu_3428_p2);
tmp50_fu_4714_p2 <= (tmp51_fu_4709_p2 xor rv_8_1_2_fu_4269_p3);
tmp51_fu_4709_p2 <= (tmp_71_1_fu_4495_p2 xor tmp_75_reg_12645);
tmp52_fu_4726_p2 <= (rv_11_1_2_fu_4303_p3 xor tmp_47_1_2_fu_4169_p2);
tmp53_fu_4732_p2 <= (tmp_72_1_fu_4500_p2 xor tmp_76_reg_12651);
tmp54_fu_4743_p2 <= (sboxes_q32 xor rv_2_1_3_fu_4349_p3);
tmp55_fu_4749_p2 <= (e_1_3_fu_4323_p2 xor tmp_77_1_fu_4505_p2);
tmp56_fu_4761_p2 <= (sboxes_q21 xor e_1_3_fu_4323_p2);
tmp57_fu_4767_p2 <= (rv_5_1_3_fu_4383_p3 xor tmp_78_1_fu_4510_p2);
tmp58_fu_4779_p2 <= (sboxes_q31 xor x_assign_171_3_fu_4311_p2);
tmp59_fu_4785_p2 <= (rv_8_1_3_fu_4417_p3 xor tmp_79_1_fu_4515_p2);
tmp5_fu_3539_p2 <= (sboxes_q15 xor x_assign_fu_2825_p2);
tmp60_fu_4797_p2 <= (tmp_47_1_3_fu_4317_p2 xor tmp_80_1_fu_4520_p2);
tmp61_fu_5501_p2 <= (tmp_65_1_reg_12757 xor ap_const_lv8_4);
tmp62_fu_5567_p2 <= (sboxes_q40 xor rv_2_2_fu_4947_p3);
tmp63_fu_5573_p2 <= (e_2_fu_4921_p2 xor tmp_65_2_fu_5506_p2);
tmp64_fu_5585_p2 <= (sboxes_q45 xor e_2_fu_4921_p2);
tmp65_fu_5591_p2 <= (rv_5_2_fu_4981_p3 xor tmp_66_2_fu_5512_p2);
tmp66_fu_5603_p2 <= (sboxes_q55 xor x_assign_9_fu_4909_p2);
tmp67_fu_5609_p2 <= (rv_8_2_fu_5015_p3 xor tmp_67_2_fu_5517_p2);
tmp68_fu_5621_p2 <= (tmp_47_2_fu_4915_p2 xor tmp_68_2_fu_5522_p2);
tmp69_fu_5633_p2 <= (sboxes_q44 xor rv_2_2_1_fu_5095_p3);
tmp6_fu_3545_p2 <= (rv_8_fu_2931_p3 xor tmp_67_fu_3433_p2);
tmp70_fu_5644_p2 <= (tmp71_fu_5639_p2 xor e_2_1_fu_5069_p2);
tmp71_fu_5639_p2 <= (tmp_65_2_fu_5506_p2 xor tmp_69_1_reg_12777);
tmp72_fu_5656_p2 <= (sboxes_q49 xor e_2_1_fu_5069_p2);
tmp73_fu_5667_p2 <= (tmp74_fu_5662_p2 xor rv_5_2_1_fu_5129_p3);
tmp74_fu_5662_p2 <= (tmp_66_2_fu_5512_p2 xor tmp_70_1_reg_12783);
tmp75_fu_5679_p2 <= (sboxes_q43 xor x_assign_273_1_fu_5057_p2);
tmp76_fu_5690_p2 <= (tmp77_fu_5685_p2 xor rv_8_2_1_fu_5163_p3);
tmp77_fu_5685_p2 <= (tmp_67_2_fu_5517_p2 xor tmp_71_1_reg_12789);
tmp78_fu_5702_p2 <= (rv_11_2_1_fu_5197_p3 xor tmp_47_2_1_fu_5063_p2);
tmp79_fu_5708_p2 <= (tmp_68_2_fu_5522_p2 xor tmp_72_1_reg_12795);
tmp7_fu_3557_p2 <= (tmp_47_fu_2831_p2 xor tmp_68_fu_3438_p2);
tmp80_fu_5719_p2 <= (sboxes_q48 xor rv_2_2_2_fu_5243_p3);
tmp81_fu_5725_p2 <= (e_2_2_fu_5217_p2 xor tmp_73_2_fu_5527_p2);
tmp82_fu_5737_p2 <= (sboxes_q53 xor e_2_2_fu_5217_p2);
tmp83_fu_5743_p2 <= (rv_5_2_2_fu_5277_p3 xor tmp_74_2_fu_5532_p2);
tmp84_fu_5755_p2 <= (sboxes_q47 xor x_assign_273_2_fu_5205_p2);
tmp85_fu_5761_p2 <= (rv_8_2_2_fu_5311_p3 xor tmp_75_2_fu_5537_p2);
tmp86_fu_5773_p2 <= (tmp_47_2_2_fu_5211_p2 xor tmp_76_2_fu_5542_p2);
tmp87_fu_5785_p2 <= (sboxes_q52 xor rv_2_2_3_fu_5391_p3);
tmp88_fu_5791_p2 <= (e_2_3_fu_5365_p2 xor tmp_77_2_fu_5547_p2);
tmp89_fu_5803_p2 <= (sboxes_q41 xor e_2_3_fu_5365_p2);
tmp8_fu_3569_p2 <= (sboxes_q4 xor rv_2_0_1_fu_3011_p3);
tmp90_fu_5809_p2 <= (rv_5_2_3_fu_5425_p3 xor tmp_78_2_fu_5552_p2);
tmp91_fu_5821_p2 <= (sboxes_q51 xor x_assign_273_3_fu_5353_p2);
tmp92_fu_5827_p2 <= (rv_8_2_3_fu_5459_p3 xor tmp_79_2_fu_5557_p2);
tmp93_fu_5839_p2 <= (tmp_47_2_3_fu_5359_p2 xor tmp_80_2_fu_5562_p2);
tmp94_fu_6609_p2 <= (sboxes_q60 xor rv_2_3_fu_5989_p3);
tmp95_fu_6615_p2 <= (e_3_fu_5963_p2 xor tmp_65_3_fu_6549_p2);
tmp96_fu_6627_p2 <= (sboxes_q65 xor e_3_fu_5963_p2);
tmp97_fu_6633_p2 <= (rv_5_3_fu_6023_p3 xor tmp_66_3_fu_6554_p2);
tmp98_fu_6645_p2 <= (sboxes_q75 xor x_assign_10_fu_5951_p2);
tmp99_fu_6651_p2 <= (rv_8_3_fu_6057_p3 xor tmp_67_3_fu_6559_p2);
tmp9_fu_3575_p2 <= (e_0_1_fu_2985_p2 xor tmp_69_fu_3443_p2);
tmp_100_fu_2625_p1 <= key_V_read(8 - 1 downto 0);
tmp_101_fu_2843_p2 <= std_logic_vector(shift_left(unsigned(x_assign_fu_2825_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_102_fu_2849_p3 <= x_assign_fu_2825_p2(7 downto 7);
tmp_103_fu_2877_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_fu_2871_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_104_fu_2883_p3 <= x_assign_1_fu_2871_p2(7 downto 7);
tmp_105_fu_2911_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_fu_2905_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_106_fu_2917_p3 <= x_assign_2_fu_2905_p2(7 downto 7);
tmp_107_fu_2945_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_fu_2939_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_108_fu_2951_p3 <= x_assign_3_fu_2939_p2(7 downto 7);
tmp_109_fu_2991_p2 <= std_logic_vector(shift_left(unsigned(x_assign_0_1_fu_2973_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_10_10_fu_2695_p2 <= (p_Result_11_fu_2541_p4 xor p_Result_1_10_fu_2551_p4);
tmp_10_11_fu_2701_p2 <= (p_Result_12_fu_2561_p4 xor p_Result_1_11_fu_2571_p4);
tmp_10_12_fu_2707_p2 <= (p_Result_13_fu_2581_p4 xor p_Result_1_12_fu_2591_p4);
tmp_10_13_fu_2713_p2 <= (p_Result_14_fu_2601_p4 xor p_Result_1_13_fu_2611_p4);
tmp_10_14_fu_2719_p2 <= (tmp_99_fu_2621_p1 xor tmp_100_fu_2625_p1);
tmp_10_1_fu_2635_p2 <= (p_Result_s_39_fu_2341_p4 xor p_Result_1_1_fu_2351_p4);
tmp_10_2_fu_2641_p2 <= (p_Result_2_fu_2361_p4 xor p_Result_1_2_fu_2371_p4);
tmp_10_3_fu_2647_p2 <= (p_Result_3_fu_2381_p4 xor p_Result_1_3_fu_2391_p4);
tmp_10_4_fu_2653_p2 <= (p_Result_4_fu_2401_p4 xor p_Result_1_4_fu_2411_p4);
tmp_10_5_fu_2659_p2 <= (p_Result_5_fu_2421_p4 xor p_Result_1_5_fu_2431_p4);
tmp_10_6_fu_2665_p2 <= (p_Result_6_fu_2441_p4 xor p_Result_1_6_fu_2451_p4);
tmp_10_7_fu_2671_p2 <= (p_Result_7_fu_2461_p4 xor p_Result_1_7_fu_2471_p4);
tmp_10_8_fu_2677_p2 <= (p_Result_8_fu_2481_p4 xor p_Result_1_8_fu_2491_p4);
tmp_10_9_fu_2683_p2 <= (p_Result_9_fu_2501_p4 xor p_Result_1_9_fu_2511_p4);
tmp_10_fu_2629_p2 <= (p_Result_s_fu_2321_p4 xor p_Result_1_fu_2331_p4);
tmp_10_s_fu_2689_p2 <= (p_Result_10_fu_2521_p4 xor p_Result_1_s_fu_2531_p4);
tmp_110_fu_2997_p3 <= x_assign_0_1_fu_2973_p2(7 downto 7);
tmp_111_fu_3025_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_0_1_fu_3019_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_112_fu_3031_p3 <= x_assign_1_0_1_fu_3019_p2(7 downto 7);
tmp_113_fu_3059_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_0_1_fu_3053_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_114_fu_3065_p3 <= x_assign_2_0_1_fu_3053_p2(7 downto 7);
tmp_115_fu_3093_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_0_1_fu_3087_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_116_fu_3099_p3 <= x_assign_3_0_1_fu_3087_p2(7 downto 7);
tmp_117_fu_3139_p2 <= std_logic_vector(shift_left(unsigned(x_assign_0_2_fu_3121_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_118_fu_3145_p3 <= x_assign_0_2_fu_3121_p2(7 downto 7);
tmp_119_fu_3173_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_0_2_fu_3167_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_11_fu_12214_p2 <= (sboxes_q197 xor ap_reg_pp0_iter9_tmp_70_7_reg_13715);
tmp_120_fu_3179_p3 <= x_assign_1_0_2_fu_3167_p2(7 downto 7);
tmp_121_fu_3207_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_0_2_fu_3201_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_122_fu_3213_p3 <= x_assign_2_0_2_fu_3201_p2(7 downto 7);
tmp_123_fu_3241_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_0_2_fu_3235_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_124_fu_3247_p3 <= x_assign_3_0_2_fu_3235_p2(7 downto 7);
tmp_125_fu_3287_p2 <= std_logic_vector(shift_left(unsigned(x_assign_0_3_fu_3269_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_126_fu_3293_p3 <= x_assign_0_3_fu_3269_p2(7 downto 7);
tmp_127_fu_3321_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_0_3_fu_3315_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_128_fu_3327_p3 <= x_assign_1_0_3_fu_3315_p2(7 downto 7);
tmp_129_fu_3355_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_0_3_fu_3349_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_12_fu_12219_p2 <= (sboxes_q198 xor ap_reg_pp0_iter9_tmp_71_7_reg_13721);
tmp_130_fu_3361_p3 <= x_assign_2_0_3_fu_3349_p2(7 downto 7);
tmp_131_fu_3389_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_0_3_fu_3383_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_132_fu_3395_p3 <= x_assign_3_0_3_fu_3383_p2(7 downto 7);
tmp_133_fu_3885_p2 <= std_logic_vector(shift_left(unsigned(x_assign_s_fu_3867_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_134_fu_3891_p3 <= x_assign_s_fu_3867_p2(7 downto 7);
tmp_135_fu_3919_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_1_fu_3913_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_136_fu_3925_p3 <= x_assign_1_1_fu_3913_p2(7 downto 7);
tmp_137_fu_3953_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_1_fu_3947_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_138_fu_3959_p3 <= x_assign_2_1_fu_3947_p2(7 downto 7);
tmp_139_fu_3987_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_1_fu_3981_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_13_fu_12224_p2 <= (sboxes_q199 xor ap_reg_pp0_iter9_tmp_72_7_reg_13727);
tmp_140_fu_3993_p3 <= x_assign_3_1_fu_3981_p2(7 downto 7);
tmp_141_fu_4033_p2 <= std_logic_vector(shift_left(unsigned(x_assign_171_1_fu_4015_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_142_fu_4039_p3 <= x_assign_171_1_fu_4015_p2(7 downto 7);
tmp_143_fu_4067_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_1_1_fu_4061_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_144_fu_4073_p3 <= x_assign_1_1_1_fu_4061_p2(7 downto 7);
tmp_145_fu_4101_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_1_1_fu_4095_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_146_fu_4107_p3 <= x_assign_2_1_1_fu_4095_p2(7 downto 7);
tmp_147_fu_4135_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_1_1_fu_4129_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_148_fu_4141_p3 <= x_assign_3_1_1_fu_4129_p2(7 downto 7);
tmp_149_fu_4181_p2 <= std_logic_vector(shift_left(unsigned(x_assign_171_2_fu_4163_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_150_fu_4187_p3 <= x_assign_171_2_fu_4163_p2(7 downto 7);
tmp_151_fu_4215_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_1_2_fu_4209_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_152_fu_4221_p3 <= x_assign_1_1_2_fu_4209_p2(7 downto 7);
tmp_153_fu_4249_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_1_2_fu_4243_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_154_fu_4255_p3 <= x_assign_2_1_2_fu_4243_p2(7 downto 7);
tmp_155_fu_4283_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_1_2_fu_4277_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_156_fu_4289_p3 <= x_assign_3_1_2_fu_4277_p2(7 downto 7);
tmp_157_fu_4329_p2 <= std_logic_vector(shift_left(unsigned(x_assign_171_3_fu_4311_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_158_fu_4335_p3 <= x_assign_171_3_fu_4311_p2(7 downto 7);
tmp_159_fu_4363_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_1_3_fu_4357_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_160_fu_4369_p3 <= x_assign_1_1_3_fu_4357_p2(7 downto 7);
tmp_161_fu_4397_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_1_3_fu_4391_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_162_fu_4403_p3 <= x_assign_2_1_3_fu_4391_p2(7 downto 7);
tmp_163_fu_4431_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_1_3_fu_4425_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_164_fu_4437_p3 <= x_assign_3_1_3_fu_4425_p2(7 downto 7);
tmp_165_fu_4927_p2 <= std_logic_vector(shift_left(unsigned(x_assign_9_fu_4909_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_166_fu_4933_p3 <= x_assign_9_fu_4909_p2(7 downto 7);
tmp_167_fu_4961_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_2_fu_4955_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_168_fu_4967_p3 <= x_assign_1_2_fu_4955_p2(7 downto 7);
tmp_169_fu_4995_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_2_fu_4989_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_170_fu_5001_p3 <= x_assign_2_2_fu_4989_p2(7 downto 7);
tmp_171_fu_5029_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_2_fu_5023_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_172_fu_5035_p3 <= x_assign_3_2_fu_5023_p2(7 downto 7);
tmp_173_fu_5075_p2 <= std_logic_vector(shift_left(unsigned(x_assign_273_1_fu_5057_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_174_fu_5081_p3 <= x_assign_273_1_fu_5057_p2(7 downto 7);
tmp_175_fu_5109_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_2_1_fu_5103_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_176_fu_5115_p3 <= x_assign_1_2_1_fu_5103_p2(7 downto 7);
tmp_177_fu_5143_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_2_1_fu_5137_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_178_fu_5149_p3 <= x_assign_2_2_1_fu_5137_p2(7 downto 7);
tmp_179_fu_5177_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_2_1_fu_5171_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_180_fu_5183_p3 <= x_assign_3_2_1_fu_5171_p2(7 downto 7);
tmp_181_fu_5223_p2 <= std_logic_vector(shift_left(unsigned(x_assign_273_2_fu_5205_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_182_fu_5229_p3 <= x_assign_273_2_fu_5205_p2(7 downto 7);
tmp_183_fu_5257_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_2_2_fu_5251_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_184_fu_5263_p3 <= x_assign_1_2_2_fu_5251_p2(7 downto 7);
tmp_185_fu_5291_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_2_2_fu_5285_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_186_fu_5297_p3 <= x_assign_2_2_2_fu_5285_p2(7 downto 7);
tmp_187_fu_5325_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_2_2_fu_5319_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_188_fu_5331_p3 <= x_assign_3_2_2_fu_5319_p2(7 downto 7);
tmp_189_fu_5371_p2 <= std_logic_vector(shift_left(unsigned(x_assign_273_3_fu_5353_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_190_fu_5377_p3 <= x_assign_273_3_fu_5353_p2(7 downto 7);
tmp_191_fu_5405_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_2_3_fu_5399_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_192_fu_5411_p3 <= x_assign_1_2_3_fu_5399_p2(7 downto 7);
tmp_193_fu_5439_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_2_3_fu_5433_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_194_fu_5445_p3 <= x_assign_2_2_3_fu_5433_p2(7 downto 7);
tmp_195_fu_5473_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_2_3_fu_5467_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_196_fu_5479_p3 <= x_assign_3_2_3_fu_5467_p2(7 downto 7);
tmp_197_fu_5969_p2 <= std_logic_vector(shift_left(unsigned(x_assign_10_fu_5951_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_198_fu_5975_p3 <= x_assign_10_fu_5951_p2(7 downto 7);
tmp_199_fu_6003_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_3_fu_5997_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_1_fu_12188_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_8_fu_11809_p2),64));
tmp_200_fu_6009_p3 <= x_assign_1_3_fu_5997_p2(7 downto 7);
tmp_201_fu_6037_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_3_fu_6031_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_202_fu_6043_p3 <= x_assign_2_3_fu_6031_p2(7 downto 7);
tmp_203_fu_6071_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_3_fu_6065_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_204_fu_6077_p3 <= x_assign_3_3_fu_6065_p2(7 downto 7);
tmp_205_fu_6117_p2 <= std_logic_vector(shift_left(unsigned(x_assign_375_1_fu_6099_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_206_fu_6123_p3 <= x_assign_375_1_fu_6099_p2(7 downto 7);
tmp_207_fu_6151_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_3_1_fu_6145_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_208_fu_6157_p3 <= x_assign_1_3_1_fu_6145_p2(7 downto 7);
tmp_209_fu_6185_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_3_1_fu_6179_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_210_fu_6191_p3 <= x_assign_2_3_1_fu_6179_p2(7 downto 7);
tmp_211_fu_6219_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_3_1_fu_6213_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_212_fu_6225_p3 <= x_assign_3_3_1_fu_6213_p2(7 downto 7);
tmp_213_fu_6265_p2 <= std_logic_vector(shift_left(unsigned(x_assign_375_2_fu_6247_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_214_fu_6271_p3 <= x_assign_375_2_fu_6247_p2(7 downto 7);
tmp_215_fu_6299_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_3_2_fu_6293_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_216_fu_6305_p3 <= x_assign_1_3_2_fu_6293_p2(7 downto 7);
tmp_217_fu_6333_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_3_2_fu_6327_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_218_fu_6339_p3 <= x_assign_2_3_2_fu_6327_p2(7 downto 7);
tmp_219_fu_6367_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_3_2_fu_6361_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_220_fu_6373_p3 <= x_assign_3_3_2_fu_6361_p2(7 downto 7);
tmp_221_fu_6413_p2 <= std_logic_vector(shift_left(unsigned(x_assign_375_3_fu_6395_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_222_fu_6419_p3 <= x_assign_375_3_fu_6395_p2(7 downto 7);
tmp_223_fu_6447_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_3_3_fu_6441_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_224_fu_6453_p3 <= x_assign_1_3_3_fu_6441_p2(7 downto 7);
tmp_225_fu_6481_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_3_3_fu_6475_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_226_fu_6487_p3 <= x_assign_2_3_3_fu_6475_p2(7 downto 7);
tmp_227_fu_6515_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_3_3_fu_6509_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_228_fu_6521_p3 <= x_assign_3_3_3_fu_6509_p2(7 downto 7);
tmp_229_fu_7011_p2 <= std_logic_vector(shift_left(unsigned(x_assign_4_fu_6993_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_230_fu_7017_p3 <= x_assign_4_fu_6993_p2(7 downto 7);
tmp_231_fu_7045_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_4_fu_7039_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_232_fu_7051_p3 <= x_assign_1_4_fu_7039_p2(7 downto 7);
tmp_233_fu_7079_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_4_fu_7073_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_234_fu_7085_p3 <= x_assign_2_4_fu_7073_p2(7 downto 7);
tmp_235_fu_7113_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_4_fu_7107_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_236_fu_7119_p3 <= x_assign_3_4_fu_7107_p2(7 downto 7);
tmp_237_fu_7159_p2 <= std_logic_vector(shift_left(unsigned(x_assign_4_1_fu_7141_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_238_fu_7165_p3 <= x_assign_4_1_fu_7141_p2(7 downto 7);
tmp_239_fu_7193_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_4_1_fu_7187_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_240_fu_7199_p3 <= x_assign_1_4_1_fu_7187_p2(7 downto 7);
tmp_241_fu_7227_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_4_1_fu_7221_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_242_fu_7233_p3 <= x_assign_2_4_1_fu_7221_p2(7 downto 7);
tmp_243_fu_7261_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_4_1_fu_7255_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_244_fu_7267_p3 <= x_assign_3_4_1_fu_7255_p2(7 downto 7);
tmp_245_fu_7307_p2 <= std_logic_vector(shift_left(unsigned(x_assign_4_2_fu_7289_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_246_fu_7313_p3 <= x_assign_4_2_fu_7289_p2(7 downto 7);
tmp_247_fu_7341_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_4_2_fu_7335_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_248_fu_7347_p3 <= x_assign_1_4_2_fu_7335_p2(7 downto 7);
tmp_249_fu_7375_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_4_2_fu_7369_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_250_fu_7381_p3 <= x_assign_2_4_2_fu_7369_p2(7 downto 7);
tmp_251_fu_7409_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_4_2_fu_7403_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_252_fu_7415_p3 <= x_assign_3_4_2_fu_7403_p2(7 downto 7);
tmp_253_fu_7455_p2 <= std_logic_vector(shift_left(unsigned(x_assign_4_3_fu_7437_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_254_fu_7461_p3 <= x_assign_4_3_fu_7437_p2(7 downto 7);
tmp_255_fu_7489_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_4_3_fu_7483_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_256_fu_7495_p3 <= x_assign_1_4_3_fu_7483_p2(7 downto 7);
tmp_257_fu_7523_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_4_3_fu_7517_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_258_fu_7529_p3 <= x_assign_2_4_3_fu_7517_p2(7 downto 7);
tmp_259_fu_7557_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_4_3_fu_7551_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_260_fu_7563_p3 <= x_assign_3_4_3_fu_7551_p2(7 downto 7);
tmp_261_fu_8053_p2 <= std_logic_vector(shift_left(unsigned(x_assign_5_fu_8035_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_262_fu_8059_p3 <= x_assign_5_fu_8035_p2(7 downto 7);
tmp_263_fu_8087_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_5_fu_8081_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_264_fu_8093_p3 <= x_assign_1_5_fu_8081_p2(7 downto 7);
tmp_265_fu_8121_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_5_fu_8115_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_266_fu_8127_p3 <= x_assign_2_5_fu_8115_p2(7 downto 7);
tmp_267_fu_8155_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_5_fu_8149_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_268_fu_8161_p3 <= x_assign_3_5_fu_8149_p2(7 downto 7);
tmp_269_fu_8201_p2 <= std_logic_vector(shift_left(unsigned(x_assign_5_1_fu_8183_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_270_fu_8207_p3 <= x_assign_5_1_fu_8183_p2(7 downto 7);
tmp_271_fu_8235_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_5_1_fu_8229_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_272_fu_8241_p3 <= x_assign_1_5_1_fu_8229_p2(7 downto 7);
tmp_273_fu_8269_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_5_1_fu_8263_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_274_fu_8275_p3 <= x_assign_2_5_1_fu_8263_p2(7 downto 7);
tmp_275_fu_8303_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_5_1_fu_8297_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_276_fu_8309_p3 <= x_assign_3_5_1_fu_8297_p2(7 downto 7);
tmp_277_fu_8349_p2 <= std_logic_vector(shift_left(unsigned(x_assign_5_2_fu_8331_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_278_fu_8355_p3 <= x_assign_5_2_fu_8331_p2(7 downto 7);
tmp_279_fu_8383_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_5_2_fu_8377_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_280_fu_8389_p3 <= x_assign_1_5_2_fu_8377_p2(7 downto 7);
tmp_281_fu_8417_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_5_2_fu_8411_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_282_fu_8423_p3 <= x_assign_2_5_2_fu_8411_p2(7 downto 7);
tmp_283_fu_8451_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_5_2_fu_8445_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_284_fu_8457_p3 <= x_assign_3_5_2_fu_8445_p2(7 downto 7);
tmp_285_fu_8497_p2 <= std_logic_vector(shift_left(unsigned(x_assign_5_3_fu_8479_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_286_fu_8503_p3 <= x_assign_5_3_fu_8479_p2(7 downto 7);
tmp_287_fu_8531_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_5_3_fu_8525_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_288_fu_8537_p3 <= x_assign_1_5_3_fu_8525_p2(7 downto 7);
tmp_289_fu_8565_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_5_3_fu_8559_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_290_fu_8571_p3 <= x_assign_2_5_3_fu_8559_p2(7 downto 7);
tmp_291_fu_8599_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_5_3_fu_8593_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_292_fu_8605_p3 <= x_assign_3_5_3_fu_8593_p2(7 downto 7);
tmp_293_fu_9095_p2 <= std_logic_vector(shift_left(unsigned(x_assign_6_fu_9077_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_294_fu_9101_p3 <= x_assign_6_fu_9077_p2(7 downto 7);
tmp_295_fu_9129_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_6_fu_9123_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_296_fu_9135_p3 <= x_assign_1_6_fu_9123_p2(7 downto 7);
tmp_297_fu_9163_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_6_fu_9157_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_298_fu_9169_p3 <= x_assign_2_6_fu_9157_p2(7 downto 7);
tmp_299_fu_9197_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_6_fu_9191_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_2_fu_12193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_8_fu_11814_p2),64));
tmp_300_fu_9203_p3 <= x_assign_3_6_fu_9191_p2(7 downto 7);
tmp_301_fu_9243_p2 <= std_logic_vector(shift_left(unsigned(x_assign_6_1_fu_9225_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_302_fu_9249_p3 <= x_assign_6_1_fu_9225_p2(7 downto 7);
tmp_303_fu_9277_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_6_1_fu_9271_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_304_fu_9283_p3 <= x_assign_1_6_1_fu_9271_p2(7 downto 7);
tmp_305_fu_9311_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_6_1_fu_9305_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_306_fu_9317_p3 <= x_assign_2_6_1_fu_9305_p2(7 downto 7);
tmp_307_fu_9345_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_6_1_fu_9339_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_308_fu_9351_p3 <= x_assign_3_6_1_fu_9339_p2(7 downto 7);
tmp_309_fu_9391_p2 <= std_logic_vector(shift_left(unsigned(x_assign_6_2_fu_9373_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_310_fu_9397_p3 <= x_assign_6_2_fu_9373_p2(7 downto 7);
tmp_311_fu_9425_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_6_2_fu_9419_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_312_fu_9431_p3 <= x_assign_1_6_2_fu_9419_p2(7 downto 7);
tmp_313_fu_9459_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_6_2_fu_9453_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_314_fu_9465_p3 <= x_assign_2_6_2_fu_9453_p2(7 downto 7);
tmp_315_fu_9493_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_6_2_fu_9487_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_316_fu_9499_p3 <= x_assign_3_6_2_fu_9487_p2(7 downto 7);
tmp_317_fu_9539_p2 <= std_logic_vector(shift_left(unsigned(x_assign_6_3_fu_9521_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_318_fu_9545_p3 <= x_assign_6_3_fu_9521_p2(7 downto 7);
tmp_319_fu_9573_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_6_3_fu_9567_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_320_fu_9579_p3 <= x_assign_1_6_3_fu_9567_p2(7 downto 7);
tmp_321_fu_9607_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_6_3_fu_9601_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_322_fu_9613_p3 <= x_assign_2_6_3_fu_9601_p2(7 downto 7);
tmp_323_fu_9641_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_6_3_fu_9635_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_324_fu_9647_p3 <= x_assign_3_6_3_fu_9635_p2(7 downto 7);
tmp_325_fu_10137_p2 <= std_logic_vector(shift_left(unsigned(x_assign_7_fu_10119_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_326_fu_10143_p3 <= x_assign_7_fu_10119_p2(7 downto 7);
tmp_327_fu_10171_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_7_fu_10165_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_328_fu_10177_p3 <= x_assign_1_7_fu_10165_p2(7 downto 7);
tmp_329_fu_10205_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_7_fu_10199_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_330_fu_10211_p3 <= x_assign_2_7_fu_10199_p2(7 downto 7);
tmp_331_fu_10239_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_7_fu_10233_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_332_fu_10245_p3 <= x_assign_3_7_fu_10233_p2(7 downto 7);
tmp_333_fu_10285_p2 <= std_logic_vector(shift_left(unsigned(x_assign_7_1_fu_10267_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_334_fu_10291_p3 <= x_assign_7_1_fu_10267_p2(7 downto 7);
tmp_335_fu_10319_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_7_1_fu_10313_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_336_fu_10325_p3 <= x_assign_1_7_1_fu_10313_p2(7 downto 7);
tmp_337_fu_10353_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_7_1_fu_10347_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_338_fu_10359_p3 <= x_assign_2_7_1_fu_10347_p2(7 downto 7);
tmp_339_fu_10387_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_7_1_fu_10381_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_33_10_fu_12158_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_10_fu_12031_p2),64));
tmp_33_11_fu_12163_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_11_fu_12049_p2),64));
tmp_33_12_fu_12168_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_12_fu_12067_p2),64));
tmp_33_13_fu_12173_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_13_fu_12085_p2),64));
tmp_33_14_fu_12178_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_14_fu_12097_p2),64));
tmp_33_1_fu_12108_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_1_fu_11849_p2),64));
tmp_33_2_fu_12113_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_2_fu_11867_p2),64));
tmp_33_3_fu_12118_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_3_fu_11879_p2),64));
tmp_33_4_fu_12123_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_4_fu_11902_p2),64));
tmp_33_5_fu_12128_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_5_fu_11925_p2),64));
tmp_33_6_fu_12133_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_6_fu_11948_p2),64));
tmp_33_7_fu_12138_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_7_fu_11965_p2),64));
tmp_33_8_fu_12143_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_8_fu_11983_p2),64));
tmp_33_9_fu_12148_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_9_fu_12001_p2),64));
tmp_33_fu_12103_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_fu_11831_p2),64));
tmp_33_s_fu_12153_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_8_s_fu_12019_p2),64));
tmp_340_fu_10393_p3 <= x_assign_3_7_1_fu_10381_p2(7 downto 7);
tmp_341_fu_10433_p2 <= std_logic_vector(shift_left(unsigned(x_assign_7_2_fu_10415_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_342_fu_10439_p3 <= x_assign_7_2_fu_10415_p2(7 downto 7);
tmp_343_fu_10467_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_7_2_fu_10461_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_344_fu_10473_p3 <= x_assign_1_7_2_fu_10461_p2(7 downto 7);
tmp_345_fu_10501_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_7_2_fu_10495_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_346_fu_10507_p3 <= x_assign_2_7_2_fu_10495_p2(7 downto 7);
tmp_347_fu_10535_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_7_2_fu_10529_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_348_fu_10541_p3 <= x_assign_3_7_2_fu_10529_p2(7 downto 7);
tmp_349_fu_10581_p2 <= std_logic_vector(shift_left(unsigned(x_assign_7_3_fu_10563_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_350_fu_10587_p3 <= x_assign_7_3_fu_10563_p2(7 downto 7);
tmp_351_fu_10615_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_7_3_fu_10609_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_352_fu_10621_p3 <= x_assign_1_7_3_fu_10609_p2(7 downto 7);
tmp_353_fu_10649_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_7_3_fu_10643_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_354_fu_10655_p3 <= x_assign_2_7_3_fu_10643_p2(7 downto 7);
tmp_355_fu_10683_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_7_3_fu_10677_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_356_fu_10689_p3 <= x_assign_3_7_3_fu_10677_p2(7 downto 7);
tmp_357_fu_11179_p2 <= std_logic_vector(shift_left(unsigned(x_assign_8_fu_11161_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_358_fu_11185_p3 <= x_assign_8_fu_11161_p2(7 downto 7);
tmp_359_fu_11213_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_8_fu_11207_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_35_0_10_fu_2780_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_10_fu_2695_p2),64));
tmp_35_0_11_fu_2785_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_11_fu_2701_p2),64));
tmp_35_0_12_fu_2790_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_12_fu_2707_p2),64));
tmp_35_0_13_fu_2795_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_13_fu_2713_p2),64));
tmp_35_0_14_fu_2800_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_14_fu_2719_p2),64));
tmp_35_0_1_fu_2730_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_1_fu_2635_p2),64));
tmp_35_0_2_fu_2735_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_2_fu_2641_p2),64));
tmp_35_0_3_fu_2740_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_3_fu_2647_p2),64));
tmp_35_0_4_fu_2745_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_4_fu_2653_p2),64));
tmp_35_0_5_fu_2750_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_5_fu_2659_p2),64));
tmp_35_0_6_fu_2755_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_6_fu_2665_p2),64));
tmp_35_0_7_fu_2760_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_7_fu_2671_p2),64));
tmp_35_0_8_fu_2765_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_8_fu_2677_p2),64));
tmp_35_0_9_fu_2770_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_9_fu_2683_p2),64));
tmp_35_0_s_fu_2775_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_s_fu_2689_p2),64));
tmp_35_1_10_fu_3822_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_10_fu_3695_p2),64));
tmp_35_1_11_fu_3827_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_11_fu_3713_p2),64));
tmp_35_1_12_fu_3832_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_12_fu_3731_p2),64));
tmp_35_1_13_fu_3837_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_13_fu_3749_p2),64));
tmp_35_1_14_fu_3842_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_14_fu_3761_p2),64));
tmp_35_1_1_fu_3772_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_1_fu_3533_p2),64));
tmp_35_1_2_fu_3777_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_2_fu_3551_p2),64));
tmp_35_1_3_fu_3782_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_3_fu_3563_p2),64));
tmp_35_1_4_fu_3787_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_4_fu_3581_p2),64));
tmp_35_1_5_fu_3792_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_5_fu_3599_p2),64));
tmp_35_1_6_fu_3797_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_6_fu_3617_p2),64));
tmp_35_1_7_fu_3802_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_7_fu_3629_p2),64));
tmp_35_1_8_fu_3807_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_8_fu_3647_p2),64));
tmp_35_1_9_fu_3812_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_9_fu_3665_p2),64));
tmp_35_1_fu_3767_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_fu_3515_p2),64));
tmp_35_1_s_fu_3817_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_0_s_fu_3683_p2),64));
tmp_35_2_10_fu_4864_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_10_fu_4737_p2),64));
tmp_35_2_11_fu_4869_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_11_fu_4755_p2),64));
tmp_35_2_12_fu_4874_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_12_fu_4773_p2),64));
tmp_35_2_13_fu_4879_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_13_fu_4791_p2),64));
tmp_35_2_14_fu_4884_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_14_fu_4803_p2),64));
tmp_35_2_1_fu_4814_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_1_fu_4555_p2),64));
tmp_35_2_2_fu_4819_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_2_fu_4573_p2),64));
tmp_35_2_3_fu_4824_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_3_fu_4585_p2),64));
tmp_35_2_4_fu_4829_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_4_fu_4603_p2),64));
tmp_35_2_5_fu_4834_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_5_fu_4621_p2),64));
tmp_35_2_6_fu_4839_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_6_fu_4639_p2),64));
tmp_35_2_7_fu_4844_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_7_fu_4651_p2),64));
tmp_35_2_8_fu_4849_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_8_fu_4674_p2),64));
tmp_35_2_9_fu_4854_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_9_fu_4697_p2),64));
tmp_35_2_fu_4809_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_fu_4537_p2),64));
tmp_35_2_s_fu_4859_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_1_s_fu_4720_p2),64));
tmp_35_3_10_fu_5906_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_10_fu_5779_p2),64));
tmp_35_3_11_fu_5911_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_11_fu_5797_p2),64));
tmp_35_3_12_fu_5916_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_12_fu_5815_p2),64));
tmp_35_3_13_fu_5921_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_13_fu_5833_p2),64));
tmp_35_3_14_fu_5926_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_14_fu_5845_p2),64));
tmp_35_3_1_fu_5856_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_1_fu_5597_p2),64));
tmp_35_3_2_fu_5861_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_2_fu_5615_p2),64));
tmp_35_3_3_fu_5866_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_3_fu_5627_p2),64));
tmp_35_3_4_fu_5871_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_4_fu_5650_p2),64));
tmp_35_3_5_fu_5876_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_5_fu_5673_p2),64));
tmp_35_3_6_fu_5881_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_6_fu_5696_p2),64));
tmp_35_3_7_fu_5886_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_7_fu_5713_p2),64));
tmp_35_3_8_fu_5891_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_8_fu_5731_p2),64));
tmp_35_3_9_fu_5896_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_9_fu_5749_p2),64));
tmp_35_3_fu_5851_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_fu_5579_p2),64));
tmp_35_3_s_fu_5901_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_2_s_fu_5767_p2),64));
tmp_35_4_10_fu_6948_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_10_fu_6821_p2),64));
tmp_35_4_11_fu_6953_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_11_fu_6839_p2),64));
tmp_35_4_12_fu_6958_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_12_fu_6857_p2),64));
tmp_35_4_13_fu_6963_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_13_fu_6875_p2),64));
tmp_35_4_14_fu_6968_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_14_fu_6887_p2),64));
tmp_35_4_1_fu_6898_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_1_fu_6639_p2),64));
tmp_35_4_2_fu_6903_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_2_fu_6657_p2),64));
tmp_35_4_3_fu_6908_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_3_fu_6669_p2),64));
tmp_35_4_4_fu_6913_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_4_fu_6687_p2),64));
tmp_35_4_5_fu_6918_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_5_fu_6705_p2),64));
tmp_35_4_6_fu_6923_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_6_fu_6723_p2),64));
tmp_35_4_7_fu_6928_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_7_fu_6735_p2),64));
tmp_35_4_8_fu_6933_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_8_fu_6758_p2),64));
tmp_35_4_9_fu_6938_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_9_fu_6781_p2),64));
tmp_35_4_fu_6893_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_fu_6621_p2),64));
tmp_35_4_s_fu_6943_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_3_s_fu_6804_p2),64));
tmp_35_5_10_fu_7990_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_10_fu_7863_p2),64));
tmp_35_5_11_fu_7995_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_11_fu_7881_p2),64));
tmp_35_5_12_fu_8000_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_12_fu_7899_p2),64));
tmp_35_5_13_fu_8005_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_13_fu_7917_p2),64));
tmp_35_5_14_fu_8010_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_14_fu_7929_p2),64));
tmp_35_5_1_fu_7940_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_1_fu_7681_p2),64));
tmp_35_5_2_fu_7945_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_2_fu_7699_p2),64));
tmp_35_5_3_fu_7950_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_3_fu_7711_p2),64));
tmp_35_5_4_fu_7955_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_4_fu_7734_p2),64));
tmp_35_5_5_fu_7960_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_5_fu_7757_p2),64));
tmp_35_5_6_fu_7965_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_6_fu_7780_p2),64));
tmp_35_5_7_fu_7970_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_7_fu_7797_p2),64));
tmp_35_5_8_fu_7975_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_8_fu_7815_p2),64));
tmp_35_5_9_fu_7980_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_9_fu_7833_p2),64));
tmp_35_5_fu_7935_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_fu_7663_p2),64));
tmp_35_5_s_fu_7985_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_4_s_fu_7851_p2),64));
tmp_35_6_10_fu_9032_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_10_fu_8905_p2),64));
tmp_35_6_11_fu_9037_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_11_fu_8923_p2),64));
tmp_35_6_12_fu_9042_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_12_fu_8941_p2),64));
tmp_35_6_13_fu_9047_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_13_fu_8959_p2),64));
tmp_35_6_14_fu_9052_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_14_fu_8971_p2),64));
tmp_35_6_1_fu_8982_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_1_fu_8723_p2),64));
tmp_35_6_2_fu_8987_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_2_fu_8741_p2),64));
tmp_35_6_3_fu_8992_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_3_fu_8753_p2),64));
tmp_35_6_4_fu_8997_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_4_fu_8771_p2),64));
tmp_35_6_5_fu_9002_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_5_fu_8789_p2),64));
tmp_35_6_6_fu_9007_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_6_fu_8807_p2),64));
tmp_35_6_7_fu_9012_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_7_fu_8819_p2),64));
tmp_35_6_8_fu_9017_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_8_fu_8842_p2),64));
tmp_35_6_9_fu_9022_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_9_fu_8865_p2),64));
tmp_35_6_fu_8977_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_fu_8705_p2),64));
tmp_35_6_s_fu_9027_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_5_s_fu_8888_p2),64));
tmp_35_7_10_fu_10074_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_10_fu_9947_p2),64));
tmp_35_7_11_fu_10079_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_11_fu_9965_p2),64));
tmp_35_7_12_fu_10084_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_12_fu_9983_p2),64));
tmp_35_7_13_fu_10089_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_13_fu_10001_p2),64));
tmp_35_7_14_fu_10094_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_14_fu_10013_p2),64));
tmp_35_7_1_fu_10024_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_1_fu_9765_p2),64));
tmp_35_7_2_fu_10029_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_2_fu_9783_p2),64));
tmp_35_7_3_fu_10034_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_3_fu_9795_p2),64));
tmp_35_7_4_fu_10039_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_4_fu_9818_p2),64));
tmp_35_7_5_fu_10044_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_5_fu_9841_p2),64));
tmp_35_7_6_fu_10049_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_6_fu_9864_p2),64));
tmp_35_7_7_fu_10054_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_7_fu_9881_p2),64));
tmp_35_7_8_fu_10059_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_8_fu_9899_p2),64));
tmp_35_7_9_fu_10064_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_9_fu_9917_p2),64));
tmp_35_7_fu_10019_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_fu_9747_p2),64));
tmp_35_7_s_fu_10069_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_6_s_fu_9935_p2),64));
tmp_35_8_10_fu_11116_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_10_fu_10989_p2),64));
tmp_35_8_11_fu_11121_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_11_fu_11007_p2),64));
tmp_35_8_12_fu_11126_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_12_fu_11025_p2),64));
tmp_35_8_13_fu_11131_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_13_fu_11043_p2),64));
tmp_35_8_14_fu_11136_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_14_fu_11055_p2),64));
tmp_35_8_1_fu_11066_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_1_fu_10807_p2),64));
tmp_35_8_2_fu_11071_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_2_fu_10825_p2),64));
tmp_35_8_3_fu_11076_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_3_fu_10837_p2),64));
tmp_35_8_4_fu_11081_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_4_fu_10855_p2),64));
tmp_35_8_5_fu_11086_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_5_fu_10873_p2),64));
tmp_35_8_6_fu_11091_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_6_fu_10891_p2),64));
tmp_35_8_7_fu_11096_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_7_fu_10903_p2),64));
tmp_35_8_8_fu_11101_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_8_fu_10926_p2),64));
tmp_35_8_9_fu_11106_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_9_fu_10949_p2),64));
tmp_35_8_fu_11061_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_fu_10789_p2),64));
tmp_35_8_s_fu_11111_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_85_7_s_fu_10972_p2),64));
tmp_35_fu_2725_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_fu_2629_p2),64));
tmp_360_fu_11219_p3 <= x_assign_1_8_fu_11207_p2(7 downto 7);
tmp_361_fu_11247_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_8_fu_11241_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_362_fu_11253_p3 <= x_assign_2_8_fu_11241_p2(7 downto 7);
tmp_363_fu_11281_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_8_fu_11275_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_364_fu_11287_p3 <= x_assign_3_8_fu_11275_p2(7 downto 7);
tmp_365_fu_11327_p2 <= std_logic_vector(shift_left(unsigned(x_assign_8_1_fu_11309_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_366_fu_11333_p3 <= x_assign_8_1_fu_11309_p2(7 downto 7);
tmp_367_fu_11361_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_8_1_fu_11355_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_368_fu_11367_p3 <= x_assign_1_8_1_fu_11355_p2(7 downto 7);
tmp_369_fu_11395_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_8_1_fu_11389_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_370_fu_11401_p3 <= x_assign_2_8_1_fu_11389_p2(7 downto 7);
tmp_371_fu_11429_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_8_1_fu_11423_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_372_fu_11435_p3 <= x_assign_3_8_1_fu_11423_p2(7 downto 7);
tmp_373_fu_11475_p2 <= std_logic_vector(shift_left(unsigned(x_assign_8_2_fu_11457_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_374_fu_11481_p3 <= x_assign_8_2_fu_11457_p2(7 downto 7);
tmp_375_fu_11509_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_8_2_fu_11503_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_376_fu_11515_p3 <= x_assign_1_8_2_fu_11503_p2(7 downto 7);
tmp_377_fu_11543_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_8_2_fu_11537_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_378_fu_11549_p3 <= x_assign_2_8_2_fu_11537_p2(7 downto 7);
tmp_379_fu_11577_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_8_2_fu_11571_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_380_fu_11583_p3 <= x_assign_3_8_2_fu_11571_p2(7 downto 7);
tmp_381_fu_11623_p2 <= std_logic_vector(shift_left(unsigned(x_assign_8_3_fu_11605_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_382_fu_11629_p3 <= x_assign_8_3_fu_11605_p2(7 downto 7);
tmp_383_fu_11657_p2 <= std_logic_vector(shift_left(unsigned(x_assign_1_8_3_fu_11651_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_384_fu_11663_p3 <= x_assign_1_8_3_fu_11651_p2(7 downto 7);
tmp_385_fu_11691_p2 <= std_logic_vector(shift_left(unsigned(x_assign_2_8_3_fu_11685_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_386_fu_11697_p3 <= x_assign_2_8_3_fu_11685_p2(7 downto 7);
tmp_387_fu_11725_p2 <= std_logic_vector(shift_left(unsigned(x_assign_3_8_3_fu_11719_p2),to_integer(unsigned('0' & ap_const_lv8_1(8-1 downto 0)))));
tmp_388_fu_11731_p3 <= x_assign_3_8_3_fu_11719_p2(7 downto 7);
tmp_38_10_fu_12335_p2 <= (tmp296_fu_12330_p2 xor sboxes_q187);
tmp_38_11_fu_12346_p2 <= (tmp297_fu_12341_p2 xor sboxes_q192);
tmp_38_12_fu_12357_p2 <= (tmp298_fu_12352_p2 xor sboxes_q181);
tmp_38_13_fu_12368_p2 <= (tmp299_fu_12363_p2 xor sboxes_q186);
tmp_38_14_fu_12379_p2 <= (tmp300_fu_12374_p2 xor sboxes_q191);
tmp_38_1_fu_12245_p2 <= (tmp290_fu_12240_p2 xor sboxes_q197);
tmp_38_2_fu_12256_p2 <= (tmp291_fu_12251_p2 xor sboxes_q198);
tmp_38_3_fu_12267_p2 <= (tmp292_fu_12262_p2 xor sboxes_q199);
tmp_38_4_fu_12273_p2 <= (sboxes_q184 xor tmp_9_fu_12209_p2);
tmp_38_5_fu_12279_p2 <= (sboxes_q189 xor tmp_11_fu_12214_p2);
tmp_38_6_fu_12285_p2 <= (sboxes_q194 xor tmp_12_fu_12219_p2);
tmp_38_7_fu_12291_p2 <= (sboxes_q183 xor tmp_13_fu_12224_p2);
tmp_38_8_fu_12302_p2 <= (tmp293_fu_12297_p2 xor sboxes_q188);
tmp_38_9_fu_12313_p2 <= (tmp294_fu_12308_p2 xor sboxes_q193);
tmp_38_fu_12234_p2 <= (tmp289_fu_12229_p2 xor sboxes_q180);
tmp_38_s_fu_12324_p2 <= (tmp295_fu_12319_p2 xor sboxes_q182);
tmp_3_fu_12198_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_8_fu_11799_p2),64));
tmp_47_0_1_fu_2979_p2 <= (sboxes_q14 xor x_assign_0_1_fu_2973_p2);
tmp_47_0_2_fu_3127_p2 <= (sboxes_q2 xor x_assign_0_2_fu_3121_p2);
tmp_47_0_3_fu_3275_p2 <= (sboxes_q6 xor x_assign_0_3_fu_3269_p2);
tmp_47_1_1_fu_4021_p2 <= (sboxes_q34 xor x_assign_171_1_fu_4015_p2);
tmp_47_1_2_fu_4169_p2 <= (sboxes_q22 xor x_assign_171_2_fu_4163_p2);
tmp_47_1_3_fu_4317_p2 <= (sboxes_q26 xor x_assign_171_3_fu_4311_p2);
tmp_47_1_fu_3873_p2 <= (sboxes_q30 xor x_assign_s_fu_3867_p2);
tmp_47_2_1_fu_5063_p2 <= (sboxes_q54 xor x_assign_273_1_fu_5057_p2);
tmp_47_2_2_fu_5211_p2 <= (sboxes_q42 xor x_assign_273_2_fu_5205_p2);
tmp_47_2_3_fu_5359_p2 <= (sboxes_q46 xor x_assign_273_3_fu_5353_p2);
tmp_47_2_fu_4915_p2 <= (sboxes_q50 xor x_assign_9_fu_4909_p2);
tmp_47_3_1_fu_6105_p2 <= (sboxes_q74 xor x_assign_375_1_fu_6099_p2);
tmp_47_3_2_fu_6253_p2 <= (sboxes_q62 xor x_assign_375_2_fu_6247_p2);
tmp_47_3_3_fu_6401_p2 <= (sboxes_q66 xor x_assign_375_3_fu_6395_p2);
tmp_47_3_fu_5957_p2 <= (sboxes_q70 xor x_assign_10_fu_5951_p2);
tmp_47_4_1_fu_7147_p2 <= (sboxes_q94 xor x_assign_4_1_fu_7141_p2);
tmp_47_4_2_fu_7295_p2 <= (sboxes_q82 xor x_assign_4_2_fu_7289_p2);
tmp_47_4_3_fu_7443_p2 <= (sboxes_q86 xor x_assign_4_3_fu_7437_p2);
tmp_47_4_fu_6999_p2 <= (sboxes_q90 xor x_assign_4_fu_6993_p2);
tmp_47_5_1_fu_8189_p2 <= (sboxes_q114 xor x_assign_5_1_fu_8183_p2);
tmp_47_5_2_fu_8337_p2 <= (sboxes_q102 xor x_assign_5_2_fu_8331_p2);
tmp_47_5_3_fu_8485_p2 <= (sboxes_q106 xor x_assign_5_3_fu_8479_p2);
tmp_47_5_fu_8041_p2 <= (sboxes_q110 xor x_assign_5_fu_8035_p2);
tmp_47_6_1_fu_9231_p2 <= (sboxes_q134 xor x_assign_6_1_fu_9225_p2);
tmp_47_6_2_fu_9379_p2 <= (sboxes_q122 xor x_assign_6_2_fu_9373_p2);
tmp_47_6_3_fu_9527_p2 <= (sboxes_q126 xor x_assign_6_3_fu_9521_p2);
tmp_47_6_fu_9083_p2 <= (sboxes_q130 xor x_assign_6_fu_9077_p2);
tmp_47_7_1_fu_10273_p2 <= (sboxes_q154 xor x_assign_7_1_fu_10267_p2);
tmp_47_7_2_fu_10421_p2 <= (sboxes_q142 xor x_assign_7_2_fu_10415_p2);
tmp_47_7_3_fu_10569_p2 <= (sboxes_q146 xor x_assign_7_3_fu_10563_p2);
tmp_47_7_fu_10125_p2 <= (sboxes_q150 xor x_assign_7_fu_10119_p2);
tmp_47_8_1_fu_11315_p2 <= (sboxes_q174 xor x_assign_8_1_fu_11309_p2);
tmp_47_8_2_fu_11463_p2 <= (sboxes_q162 xor x_assign_8_2_fu_11457_p2);
tmp_47_8_3_fu_11611_p2 <= (sboxes_q166 xor x_assign_8_3_fu_11605_p2);
tmp_47_8_fu_11167_p2 <= (sboxes_q170 xor x_assign_8_fu_11161_p2);
tmp_47_fu_2831_p2 <= (sboxes_q10 xor x_assign_fu_2825_p2);
tmp_4_fu_12203_p2 <= (sboxes_q196 xor ap_const_lv8_36);
tmp_60_1_fu_3847_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_fu_3488_p2),64));
tmp_60_2_fu_4889_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_1_fu_4510_p2),64));
tmp_60_3_fu_5931_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_2_fu_5552_p2),64));
tmp_60_4_fu_6973_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_3_fu_6594_p2),64));
tmp_60_5_fu_8015_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_4_fu_7636_p2),64));
tmp_60_6_fu_9057_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_5_fu_8678_p2),64));
tmp_60_7_fu_10099_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_6_fu_9720_p2),64));
tmp_60_8_fu_11141_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_7_fu_10762_p2),64));
tmp_60_fu_2805_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Result_1_12_fu_2591_p4),64));
tmp_61_1_fu_3852_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_fu_3493_p2),64));
tmp_61_2_fu_4894_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_1_fu_4515_p2),64));
tmp_61_3_fu_5936_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_2_fu_5557_p2),64));
tmp_61_4_fu_6978_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_3_fu_6599_p2),64));
tmp_61_5_fu_8020_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_4_fu_7641_p2),64));
tmp_61_6_fu_9062_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_5_fu_8683_p2),64));
tmp_61_7_fu_10104_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_6_fu_9725_p2),64));
tmp_61_8_fu_11146_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_79_7_fu_10767_p2),64));
tmp_61_fu_2810_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Result_1_13_fu_2611_p4),64));
tmp_62_1_fu_3857_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_fu_3498_p2),64));
tmp_62_2_fu_4899_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_1_fu_4520_p2),64));
tmp_62_3_fu_5941_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_2_fu_5562_p2),64));
tmp_62_4_fu_6983_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_3_fu_6604_p2),64));
tmp_62_5_fu_8025_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_4_fu_7646_p2),64));
tmp_62_6_fu_9067_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_5_fu_8688_p2),64));
tmp_62_7_fu_10109_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_6_fu_9730_p2),64));
tmp_62_8_fu_11151_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_80_7_fu_10772_p2),64));
tmp_62_fu_2815_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_100_fu_2625_p1),64));
tmp_63_1_fu_3862_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_fu_3483_p2),64));
tmp_63_2_fu_4904_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_1_fu_4505_p2),64));
tmp_63_3_fu_5946_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_2_fu_5547_p2),64));
tmp_63_4_fu_6988_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_3_fu_6589_p2),64));
tmp_63_5_fu_8030_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_4_fu_7631_p2),64));
tmp_63_6_fu_9072_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_5_fu_8673_p2),64));
tmp_63_7_fu_10114_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_6_fu_9715_p2),64));
tmp_63_8_fu_11156_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_77_7_fu_10757_p2),64));
tmp_63_fu_2820_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Result_1_11_fu_2571_p4),64));
tmp_64_1_fu_4459_p2 <= (sboxes_q36 xor ap_const_lv8_2);
tmp_64_3_fu_6543_p2 <= (sboxes_q76 xor ap_const_lv8_8);
tmp_64_5_fu_8627_p2 <= (sboxes_q116 xor ap_const_lv8_20);
tmp_64_7_fu_10711_p2 <= (sboxes_q156 xor ap_const_lv8_80);
tmp_65_1_fu_4465_p2 <= (tmp_64_1_fu_4459_p2 xor tmp_65_reg_12613);
tmp_65_2_fu_5506_p2 <= (tmp61_fu_5501_p2 xor sboxes_q56);
tmp_65_3_fu_6549_p2 <= (tmp_64_3_fu_6543_p2 xor tmp_65_2_reg_12921);
tmp_65_4_fu_7590_p2 <= (tmp126_fu_7585_p2 xor sboxes_q96);
tmp_65_5_fu_8633_p2 <= (tmp_64_5_fu_8627_p2 xor tmp_65_4_reg_13237);
tmp_65_6_fu_9674_p2 <= (tmp191_fu_9669_p2 xor sboxes_q136);
tmp_65_7_fu_10717_p2 <= (tmp_64_7_fu_10711_p2 xor tmp_65_6_reg_13545);
tmp_65_8_fu_11758_p2 <= (tmp256_fu_11753_p2 xor sboxes_q176);
tmp_65_fu_3422_p2 <= (tmp_fu_3417_p2 xor sboxes_q16);
tmp_66_1_fu_4470_p2 <= (sboxes_q37 xor tmp_66_reg_12618);
tmp_66_2_fu_5512_p2 <= (sboxes_q57 xor tmp_66_1_reg_12762);
tmp_66_3_fu_6554_p2 <= (sboxes_q77 xor tmp_66_2_reg_12926);
tmp_66_4_fu_7596_p2 <= (sboxes_q97 xor tmp_66_3_reg_13070);
tmp_66_5_fu_8638_p2 <= (sboxes_q117 xor tmp_66_4_reg_13242);
tmp_66_6_fu_9680_p2 <= (sboxes_q137 xor tmp_66_5_reg_13386);
tmp_66_7_fu_10722_p2 <= (sboxes_q157 xor tmp_66_6_reg_13550);
tmp_66_8_fu_11764_p2 <= (sboxes_q177 xor tmp_66_7_reg_13694);
tmp_66_fu_3428_p2 <= (sboxes_q17 xor p_Result_1_1_reg_12426);
tmp_67_1_fu_4475_p2 <= (sboxes_q38 xor tmp_67_reg_12623);
tmp_67_2_fu_5517_p2 <= (sboxes_q58 xor tmp_67_1_reg_12767);
tmp_67_3_fu_6559_p2 <= (sboxes_q78 xor tmp_67_2_reg_12931);
tmp_67_4_fu_7601_p2 <= (sboxes_q98 xor tmp_67_3_reg_13075);
tmp_67_5_fu_8643_p2 <= (sboxes_q118 xor tmp_67_4_reg_13247);
tmp_67_6_fu_9685_p2 <= (sboxes_q138 xor tmp_67_5_reg_13391);
tmp_67_7_fu_10727_p2 <= (sboxes_q158 xor tmp_67_6_reg_13555);
tmp_67_8_fu_11769_p2 <= (sboxes_q178 xor tmp_67_7_reg_13699);
tmp_67_fu_3433_p2 <= (sboxes_q18 xor p_Result_1_2_reg_12431);
tmp_68_1_fu_4480_p2 <= (sboxes_q39 xor tmp_68_reg_12628);
tmp_68_2_fu_5522_p2 <= (sboxes_q59 xor tmp_68_1_reg_12772);
tmp_68_3_fu_6564_p2 <= (sboxes_q79 xor tmp_68_2_reg_12936);
tmp_68_4_fu_7606_p2 <= (sboxes_q99 xor tmp_68_3_reg_13080);
tmp_68_5_fu_8648_p2 <= (sboxes_q119 xor tmp_68_4_reg_13252);
tmp_68_6_fu_9690_p2 <= (sboxes_q139 xor tmp_68_5_reg_13396);
tmp_68_7_fu_10732_p2 <= (sboxes_q159 xor tmp_68_6_reg_13560);
tmp_68_8_fu_11774_p2 <= (sboxes_q179 xor tmp_68_7_reg_13704);
tmp_68_fu_3438_p2 <= (sboxes_q19 xor p_Result_1_3_reg_12436);
tmp_69_1_fu_4485_p2 <= (ap_reg_pp0_iter1_p_Result_1_4_reg_12441 xor tmp_64_1_fu_4459_p2);
tmp_69_3_fu_6569_p2 <= (ap_reg_pp0_iter3_tmp_69_1_reg_12777 xor tmp_64_3_fu_6543_p2);
tmp_69_5_fu_8653_p2 <= (ap_reg_pp0_iter5_tmp_69_3_reg_13085 xor tmp_64_5_fu_8627_p2);
tmp_69_7_fu_10737_p2 <= (ap_reg_pp0_iter7_tmp_69_5_reg_13401 xor tmp_64_7_fu_10711_p2);
tmp_69_fu_3443_p2 <= (p_Result_1_4_reg_12441 xor tmp_65_fu_3422_p2);
tmp_70_1_fu_4490_p2 <= (sboxes_q37 xor ap_reg_pp0_iter1_p_Result_1_5_reg_12447);
tmp_70_3_fu_6574_p2 <= (sboxes_q77 xor ap_reg_pp0_iter3_tmp_70_1_reg_12783);
tmp_70_5_fu_8658_p2 <= (sboxes_q117 xor ap_reg_pp0_iter5_tmp_70_3_reg_13091);
tmp_70_7_fu_10742_p2 <= (sboxes_q157 xor ap_reg_pp0_iter7_tmp_70_5_reg_13407);
tmp_70_fu_3448_p2 <= (p_Result_1_5_reg_12447 xor tmp_66_fu_3428_p2);
tmp_71_1_fu_4495_p2 <= (sboxes_q38 xor ap_reg_pp0_iter1_p_Result_1_6_reg_12453);
tmp_71_3_fu_6579_p2 <= (sboxes_q78 xor ap_reg_pp0_iter3_tmp_71_1_reg_12789);
tmp_71_5_fu_8663_p2 <= (sboxes_q118 xor ap_reg_pp0_iter5_tmp_71_3_reg_13097);
tmp_71_7_fu_10747_p2 <= (sboxes_q158 xor ap_reg_pp0_iter7_tmp_71_5_reg_13413);
tmp_71_fu_3453_p2 <= (p_Result_1_6_reg_12453 xor tmp_67_fu_3433_p2);
tmp_72_1_fu_4500_p2 <= (sboxes_q39 xor ap_reg_pp0_iter1_p_Result_1_7_reg_12459);
tmp_72_3_fu_6584_p2 <= (sboxes_q79 xor ap_reg_pp0_iter3_tmp_72_1_reg_12795);
tmp_72_5_fu_8668_p2 <= (sboxes_q119 xor ap_reg_pp0_iter5_tmp_72_3_reg_13103);
tmp_72_7_fu_10752_p2 <= (sboxes_q159 xor ap_reg_pp0_iter7_tmp_72_5_reg_13419);
tmp_72_fu_3458_p2 <= (p_Result_1_7_reg_12459 xor tmp_68_fu_3438_p2);
tmp_73_2_fu_5527_p2 <= (ap_reg_pp0_iter2_tmp_73_reg_12633 xor tmp_65_2_fu_5506_p2);
tmp_73_4_fu_7611_p2 <= (ap_reg_pp0_iter4_tmp_73_2_reg_12941 xor tmp_65_4_fu_7590_p2);
tmp_73_6_fu_9695_p2 <= (ap_reg_pp0_iter6_tmp_73_4_reg_13257 xor tmp_65_6_fu_9674_p2);
tmp_73_8_fu_11779_p2 <= (ap_reg_pp0_iter8_tmp_73_6_reg_13565 xor tmp_65_8_fu_11758_p2);
tmp_73_fu_3463_p2 <= (p_Result_1_8_reg_12465 xor tmp_69_fu_3443_p2);
tmp_74_2_fu_5532_p2 <= (ap_reg_pp0_iter2_tmp_74_reg_12639 xor tmp_66_2_fu_5512_p2);
tmp_74_4_fu_7616_p2 <= (ap_reg_pp0_iter4_tmp_74_2_reg_12947 xor tmp_66_4_fu_7596_p2);
tmp_74_6_fu_9700_p2 <= (ap_reg_pp0_iter6_tmp_74_4_reg_13263 xor tmp_66_6_fu_9680_p2);
tmp_74_8_fu_11784_p2 <= (ap_reg_pp0_iter8_tmp_74_6_reg_13571 xor tmp_66_8_fu_11764_p2);
tmp_74_fu_3468_p2 <= (p_Result_1_9_reg_12470 xor tmp_70_fu_3448_p2);
tmp_75_2_fu_5537_p2 <= (ap_reg_pp0_iter2_tmp_75_reg_12645 xor tmp_67_2_fu_5517_p2);
tmp_75_4_fu_7621_p2 <= (ap_reg_pp0_iter4_tmp_75_2_reg_12953 xor tmp_67_4_fu_7601_p2);
tmp_75_6_fu_9705_p2 <= (ap_reg_pp0_iter6_tmp_75_4_reg_13269 xor tmp_67_6_fu_9685_p2);
tmp_75_8_fu_11789_p2 <= (ap_reg_pp0_iter8_tmp_75_6_reg_13577 xor tmp_67_8_fu_11769_p2);
tmp_75_fu_3473_p2 <= (p_Result_1_s_reg_12475 xor tmp_71_fu_3453_p2);
tmp_76_2_fu_5542_p2 <= (ap_reg_pp0_iter2_tmp_76_reg_12651 xor tmp_68_2_fu_5522_p2);
tmp_76_4_fu_7626_p2 <= (ap_reg_pp0_iter4_tmp_76_2_reg_12959 xor tmp_68_4_fu_7606_p2);
tmp_76_6_fu_9710_p2 <= (ap_reg_pp0_iter6_tmp_76_4_reg_13275 xor tmp_68_6_fu_9690_p2);
tmp_76_8_fu_11794_p2 <= (ap_reg_pp0_iter8_tmp_76_6_reg_13583 xor tmp_68_8_fu_11774_p2);
tmp_76_fu_3478_p2 <= (p_Result_1_10_reg_12480 xor tmp_72_fu_3458_p2);
tmp_77_1_fu_4505_p2 <= (tmp_69_1_fu_4485_p2 xor ap_reg_pp0_iter1_p_Result_1_11_reg_12485);
tmp_77_2_fu_5547_p2 <= (tmp_73_2_fu_5527_p2 xor tmp_77_1_reg_12801);
tmp_77_3_fu_6589_p2 <= (tmp_64_3_fu_6543_p2 xor ap_reg_pp0_iter3_p_Result_1_11_reg_12485);
tmp_77_4_fu_7631_p2 <= (tmp_73_4_fu_7611_p2 xor tmp_77_3_reg_13109);
tmp_77_5_fu_8673_p2 <= (tmp_69_5_fu_8653_p2 xor ap_reg_pp0_iter5_tmp_77_3_reg_13109);
tmp_77_6_fu_9715_p2 <= (tmp_73_6_fu_9695_p2 xor tmp_77_5_reg_13425);
tmp_77_7_fu_10757_p2 <= (tmp_64_7_fu_10711_p2 xor ap_reg_pp0_iter7_tmp_77_3_reg_13109);
tmp_77_8_fu_11799_p2 <= (tmp_73_8_fu_11779_p2 xor tmp_77_7_reg_13733);
tmp_77_fu_3483_p2 <= (tmp_73_fu_3463_p2 xor p_Result_1_11_reg_12485);
tmp_78_1_fu_4510_p2 <= (tmp_70_1_fu_4490_p2 xor ap_reg_pp0_iter1_p_Result_1_12_reg_12492);
tmp_78_2_fu_5552_p2 <= (tmp_74_2_fu_5532_p2 xor tmp_78_1_reg_12806);
tmp_78_3_fu_6594_p2 <= (sboxes_q77 xor ap_reg_pp0_iter3_p_Result_1_12_reg_12492);
tmp_78_4_fu_7636_p2 <= (tmp_74_4_fu_7616_p2 xor tmp_78_3_reg_13116);
tmp_78_5_fu_8678_p2 <= (tmp_70_5_fu_8658_p2 xor ap_reg_pp0_iter5_tmp_78_3_reg_13116);
tmp_78_6_fu_9720_p2 <= (tmp_74_6_fu_9700_p2 xor tmp_78_5_reg_13430);
tmp_78_7_fu_10762_p2 <= (sboxes_q157 xor ap_reg_pp0_iter7_tmp_78_3_reg_13116);
tmp_78_8_fu_11804_p2 <= (tmp_74_8_fu_11784_p2 xor tmp_78_7_reg_13739);
tmp_78_fu_3488_p2 <= (tmp_74_fu_3468_p2 xor p_Result_1_12_reg_12492);
tmp_79_1_fu_4515_p2 <= (tmp_71_1_fu_4495_p2 xor ap_reg_pp0_iter1_p_Result_1_13_reg_12499);
tmp_79_2_fu_5557_p2 <= (tmp_75_2_fu_5537_p2 xor tmp_79_1_reg_12811);
tmp_79_3_fu_6599_p2 <= (sboxes_q78 xor ap_reg_pp0_iter3_p_Result_1_13_reg_12499);
tmp_79_4_fu_7641_p2 <= (tmp_75_4_fu_7621_p2 xor tmp_79_3_reg_13123);
tmp_79_5_fu_8683_p2 <= (tmp_71_5_fu_8663_p2 xor ap_reg_pp0_iter5_tmp_79_3_reg_13123);
tmp_79_6_fu_9725_p2 <= (tmp_75_6_fu_9705_p2 xor tmp_79_5_reg_13435);
tmp_79_7_fu_10767_p2 <= (sboxes_q158 xor ap_reg_pp0_iter7_tmp_79_3_reg_13123);
tmp_79_8_fu_11809_p2 <= (tmp_75_8_fu_11789_p2 xor tmp_79_7_reg_13745);
tmp_79_fu_3493_p2 <= (tmp_75_fu_3473_p2 xor p_Result_1_13_reg_12499);
tmp_80_1_fu_4520_p2 <= (tmp_72_1_fu_4500_p2 xor ap_reg_pp0_iter1_tmp_100_reg_12506);
tmp_80_2_fu_5562_p2 <= (tmp_76_2_fu_5542_p2 xor tmp_80_1_reg_12816);
tmp_80_3_fu_6604_p2 <= (sboxes_q79 xor ap_reg_pp0_iter3_tmp_100_reg_12506);
tmp_80_4_fu_7646_p2 <= (tmp_76_4_fu_7626_p2 xor tmp_80_3_reg_13130);
tmp_80_5_fu_8688_p2 <= (tmp_72_5_fu_8668_p2 xor ap_reg_pp0_iter5_tmp_80_3_reg_13130);
tmp_80_6_fu_9730_p2 <= (tmp_76_6_fu_9710_p2 xor tmp_80_5_reg_13440);
tmp_80_7_fu_10772_p2 <= (sboxes_q159 xor ap_reg_pp0_iter7_tmp_80_3_reg_13130);
tmp_80_8_fu_11814_p2 <= (tmp_76_8_fu_11794_p2 xor tmp_80_7_reg_13751);
tmp_80_fu_3498_p2 <= (tmp_76_fu_3478_p2 xor tmp_100_reg_12506);
tmp_85_0_10_fu_3695_p2 <= (tmp21_fu_3689_p2 xor rv_11_0_2_fu_3261_p3);
tmp_85_0_11_fu_3713_p2 <= (tmp23_fu_3707_p2 xor tmp22_fu_3701_p2);
tmp_85_0_12_fu_3731_p2 <= (tmp25_fu_3725_p2 xor tmp24_fu_3719_p2);
tmp_85_0_13_fu_3749_p2 <= (tmp27_fu_3743_p2 xor tmp26_fu_3737_p2);
tmp_85_0_14_fu_3761_p2 <= (tmp28_fu_3755_p2 xor rv_11_0_3_fu_3409_p3);
tmp_85_0_1_fu_3533_p2 <= (tmp4_fu_3527_p2 xor tmp3_fu_3521_p2);
tmp_85_0_2_fu_3551_p2 <= (tmp6_fu_3545_p2 xor tmp5_fu_3539_p2);
tmp_85_0_3_fu_3563_p2 <= (tmp7_fu_3557_p2 xor rv_3_fu_2965_p3);
tmp_85_0_4_fu_3581_p2 <= (tmp9_fu_3575_p2 xor tmp8_fu_3569_p2);
tmp_85_0_5_fu_3599_p2 <= (tmp11_fu_3593_p2 xor tmp10_fu_3587_p2);
tmp_85_0_6_fu_3617_p2 <= (tmp13_fu_3611_p2 xor tmp12_fu_3605_p2);
tmp_85_0_7_fu_3629_p2 <= (tmp14_fu_3623_p2 xor rv_11_0_1_fu_3113_p3);
tmp_85_0_8_fu_3647_p2 <= (tmp16_fu_3641_p2 xor tmp15_fu_3635_p2);
tmp_85_0_9_fu_3665_p2 <= (tmp18_fu_3659_p2 xor tmp17_fu_3653_p2);
tmp_85_0_s_fu_3683_p2 <= (tmp20_fu_3677_p2 xor tmp19_fu_3671_p2);
tmp_85_1_10_fu_4737_p2 <= (tmp53_fu_4732_p2 xor tmp52_fu_4726_p2);
tmp_85_1_11_fu_4755_p2 <= (tmp55_fu_4749_p2 xor tmp54_fu_4743_p2);
tmp_85_1_12_fu_4773_p2 <= (tmp57_fu_4767_p2 xor tmp56_fu_4761_p2);
tmp_85_1_13_fu_4791_p2 <= (tmp59_fu_4785_p2 xor tmp58_fu_4779_p2);
tmp_85_1_14_fu_4803_p2 <= (tmp60_fu_4797_p2 xor rv_11_1_3_fu_4451_p3);
tmp_85_1_1_fu_4555_p2 <= (tmp32_fu_4549_p2 xor tmp31_fu_4543_p2);
tmp_85_1_2_fu_4573_p2 <= (tmp34_fu_4567_p2 xor tmp33_fu_4561_p2);
tmp_85_1_3_fu_4585_p2 <= (tmp35_fu_4579_p2 xor rv_11_1_fu_4007_p3);
tmp_85_1_4_fu_4603_p2 <= (tmp37_fu_4597_p2 xor tmp36_fu_4591_p2);
tmp_85_1_5_fu_4621_p2 <= (tmp39_fu_4615_p2 xor tmp38_fu_4609_p2);
tmp_85_1_6_fu_4639_p2 <= (tmp41_fu_4633_p2 xor tmp40_fu_4627_p2);
tmp_85_1_7_fu_4651_p2 <= (tmp42_fu_4645_p2 xor rv_11_1_1_fu_4155_p3);
tmp_85_1_8_fu_4674_p2 <= (tmp44_fu_4668_p2 xor tmp43_fu_4657_p2);
tmp_85_1_9_fu_4697_p2 <= (tmp47_fu_4691_p2 xor tmp46_fu_4680_p2);
tmp_85_1_fu_4537_p2 <= (tmp30_fu_4531_p2 xor tmp29_fu_4525_p2);
tmp_85_1_s_fu_4720_p2 <= (tmp50_fu_4714_p2 xor tmp49_fu_4703_p2);
tmp_85_2_10_fu_5779_p2 <= (tmp86_fu_5773_p2 xor rv_11_2_2_fu_5345_p3);
tmp_85_2_11_fu_5797_p2 <= (tmp88_fu_5791_p2 xor tmp87_fu_5785_p2);
tmp_85_2_12_fu_5815_p2 <= (tmp90_fu_5809_p2 xor tmp89_fu_5803_p2);
tmp_85_2_13_fu_5833_p2 <= (tmp92_fu_5827_p2 xor tmp91_fu_5821_p2);
tmp_85_2_14_fu_5845_p2 <= (tmp93_fu_5839_p2 xor rv_11_2_3_fu_5493_p3);
tmp_85_2_1_fu_5597_p2 <= (tmp65_fu_5591_p2 xor tmp64_fu_5585_p2);
tmp_85_2_2_fu_5615_p2 <= (tmp67_fu_5609_p2 xor tmp66_fu_5603_p2);
tmp_85_2_3_fu_5627_p2 <= (tmp68_fu_5621_p2 xor rv_11_2_fu_5049_p3);
tmp_85_2_4_fu_5650_p2 <= (tmp70_fu_5644_p2 xor tmp69_fu_5633_p2);
tmp_85_2_5_fu_5673_p2 <= (tmp73_fu_5667_p2 xor tmp72_fu_5656_p2);
tmp_85_2_6_fu_5696_p2 <= (tmp76_fu_5690_p2 xor tmp75_fu_5679_p2);
tmp_85_2_7_fu_5713_p2 <= (tmp79_fu_5708_p2 xor tmp78_fu_5702_p2);
tmp_85_2_8_fu_5731_p2 <= (tmp81_fu_5725_p2 xor tmp80_fu_5719_p2);
tmp_85_2_9_fu_5749_p2 <= (tmp83_fu_5743_p2 xor tmp82_fu_5737_p2);
tmp_85_2_fu_5579_p2 <= (tmp63_fu_5573_p2 xor tmp62_fu_5567_p2);
tmp_85_2_s_fu_5767_p2 <= (tmp85_fu_5761_p2 xor tmp84_fu_5755_p2);
tmp_85_3_10_fu_6821_p2 <= (tmp118_fu_6816_p2 xor tmp117_fu_6810_p2);
tmp_85_3_11_fu_6839_p2 <= (tmp120_fu_6833_p2 xor tmp119_fu_6827_p2);
tmp_85_3_12_fu_6857_p2 <= (tmp122_fu_6851_p2 xor tmp121_fu_6845_p2);
tmp_85_3_13_fu_6875_p2 <= (tmp124_fu_6869_p2 xor tmp123_fu_6863_p2);
tmp_85_3_14_fu_6887_p2 <= (tmp125_fu_6881_p2 xor rv_11_3_3_fu_6535_p3);
tmp_85_3_1_fu_6639_p2 <= (tmp97_fu_6633_p2 xor tmp96_fu_6627_p2);
tmp_85_3_2_fu_6657_p2 <= (tmp99_fu_6651_p2 xor tmp98_fu_6645_p2);
tmp_85_3_3_fu_6669_p2 <= (tmp100_fu_6663_p2 xor rv_11_3_fu_6091_p3);
tmp_85_3_4_fu_6687_p2 <= (tmp102_fu_6681_p2 xor tmp101_fu_6675_p2);
tmp_85_3_5_fu_6705_p2 <= (tmp104_fu_6699_p2 xor tmp103_fu_6693_p2);
tmp_85_3_6_fu_6723_p2 <= (tmp106_fu_6717_p2 xor tmp105_fu_6711_p2);
tmp_85_3_7_fu_6735_p2 <= (tmp107_fu_6729_p2 xor rv_11_3_1_fu_6239_p3);
tmp_85_3_8_fu_6758_p2 <= (tmp109_fu_6752_p2 xor tmp108_fu_6741_p2);
tmp_85_3_9_fu_6781_p2 <= (tmp112_fu_6775_p2 xor tmp111_fu_6764_p2);
tmp_85_3_fu_6621_p2 <= (tmp95_fu_6615_p2 xor tmp94_fu_6609_p2);
tmp_85_3_s_fu_6804_p2 <= (tmp115_fu_6798_p2 xor tmp114_fu_6787_p2);
tmp_85_4_10_fu_7863_p2 <= (tmp151_fu_7857_p2 xor rv_11_4_2_fu_7429_p3);
tmp_85_4_11_fu_7881_p2 <= (tmp153_fu_7875_p2 xor tmp152_fu_7869_p2);
tmp_85_4_12_fu_7899_p2 <= (tmp155_fu_7893_p2 xor tmp154_fu_7887_p2);
tmp_85_4_13_fu_7917_p2 <= (tmp157_fu_7911_p2 xor tmp156_fu_7905_p2);
tmp_85_4_14_fu_7929_p2 <= (tmp158_fu_7923_p2 xor rv_11_4_3_fu_7577_p3);
tmp_85_4_1_fu_7681_p2 <= (tmp130_fu_7675_p2 xor tmp129_fu_7669_p2);
tmp_85_4_2_fu_7699_p2 <= (tmp132_fu_7693_p2 xor tmp131_fu_7687_p2);
tmp_85_4_3_fu_7711_p2 <= (tmp133_fu_7705_p2 xor rv_11_4_fu_7133_p3);
tmp_85_4_4_fu_7734_p2 <= (tmp135_fu_7728_p2 xor tmp134_fu_7717_p2);
tmp_85_4_5_fu_7757_p2 <= (tmp138_fu_7751_p2 xor tmp137_fu_7740_p2);
tmp_85_4_6_fu_7780_p2 <= (tmp141_fu_7774_p2 xor tmp140_fu_7763_p2);
tmp_85_4_7_fu_7797_p2 <= (tmp144_fu_7792_p2 xor tmp143_fu_7786_p2);
tmp_85_4_8_fu_7815_p2 <= (tmp146_fu_7809_p2 xor tmp145_fu_7803_p2);
tmp_85_4_9_fu_7833_p2 <= (tmp148_fu_7827_p2 xor tmp147_fu_7821_p2);
tmp_85_4_fu_7663_p2 <= (tmp128_fu_7657_p2 xor tmp127_fu_7651_p2);
tmp_85_4_s_fu_7851_p2 <= (tmp150_fu_7845_p2 xor tmp149_fu_7839_p2);
tmp_85_5_10_fu_8905_p2 <= (tmp183_fu_8900_p2 xor tmp182_fu_8894_p2);
tmp_85_5_11_fu_8923_p2 <= (tmp185_fu_8917_p2 xor tmp184_fu_8911_p2);
tmp_85_5_12_fu_8941_p2 <= (tmp187_fu_8935_p2 xor tmp186_fu_8929_p2);
tmp_85_5_13_fu_8959_p2 <= (tmp189_fu_8953_p2 xor tmp188_fu_8947_p2);
tmp_85_5_14_fu_8971_p2 <= (tmp190_fu_8965_p2 xor rv_11_5_3_fu_8619_p3);
tmp_85_5_1_fu_8723_p2 <= (tmp162_fu_8717_p2 xor tmp161_fu_8711_p2);
tmp_85_5_2_fu_8741_p2 <= (tmp164_fu_8735_p2 xor tmp163_fu_8729_p2);
tmp_85_5_3_fu_8753_p2 <= (tmp165_fu_8747_p2 xor rv_11_5_fu_8175_p3);
tmp_85_5_4_fu_8771_p2 <= (tmp167_fu_8765_p2 xor tmp166_fu_8759_p2);
tmp_85_5_5_fu_8789_p2 <= (tmp169_fu_8783_p2 xor tmp168_fu_8777_p2);
tmp_85_5_6_fu_8807_p2 <= (tmp171_fu_8801_p2 xor tmp170_fu_8795_p2);
tmp_85_5_7_fu_8819_p2 <= (tmp172_fu_8813_p2 xor rv_11_5_1_fu_8323_p3);
tmp_85_5_8_fu_8842_p2 <= (tmp174_fu_8836_p2 xor tmp173_fu_8825_p2);
tmp_85_5_9_fu_8865_p2 <= (tmp177_fu_8859_p2 xor tmp176_fu_8848_p2);
tmp_85_5_fu_8705_p2 <= (tmp160_fu_8699_p2 xor tmp159_fu_8693_p2);
tmp_85_5_s_fu_8888_p2 <= (tmp180_fu_8882_p2 xor tmp179_fu_8871_p2);
tmp_85_6_10_fu_9947_p2 <= (tmp216_fu_9941_p2 xor rv_11_6_2_fu_9513_p3);
tmp_85_6_11_fu_9965_p2 <= (tmp218_fu_9959_p2 xor tmp217_fu_9953_p2);
tmp_85_6_12_fu_9983_p2 <= (tmp220_fu_9977_p2 xor tmp219_fu_9971_p2);
tmp_85_6_13_fu_10001_p2 <= (tmp222_fu_9995_p2 xor tmp221_fu_9989_p2);
tmp_85_6_14_fu_10013_p2 <= (tmp223_fu_10007_p2 xor rv_11_6_3_fu_9661_p3);
tmp_85_6_1_fu_9765_p2 <= (tmp195_fu_9759_p2 xor tmp194_fu_9753_p2);
tmp_85_6_2_fu_9783_p2 <= (tmp197_fu_9777_p2 xor tmp196_fu_9771_p2);
tmp_85_6_3_fu_9795_p2 <= (tmp198_fu_9789_p2 xor rv_11_6_fu_9217_p3);
tmp_85_6_4_fu_9818_p2 <= (tmp200_fu_9812_p2 xor tmp199_fu_9801_p2);
tmp_85_6_5_fu_9841_p2 <= (tmp203_fu_9835_p2 xor tmp202_fu_9824_p2);
tmp_85_6_6_fu_9864_p2 <= (tmp206_fu_9858_p2 xor tmp205_fu_9847_p2);
tmp_85_6_7_fu_9881_p2 <= (tmp209_fu_9876_p2 xor tmp208_fu_9870_p2);
tmp_85_6_8_fu_9899_p2 <= (tmp211_fu_9893_p2 xor tmp210_fu_9887_p2);
tmp_85_6_9_fu_9917_p2 <= (tmp213_fu_9911_p2 xor tmp212_fu_9905_p2);
tmp_85_6_fu_9747_p2 <= (tmp193_fu_9741_p2 xor tmp192_fu_9735_p2);
tmp_85_6_s_fu_9935_p2 <= (tmp215_fu_9929_p2 xor tmp214_fu_9923_p2);
tmp_85_7_10_fu_10989_p2 <= (tmp248_fu_10984_p2 xor tmp247_fu_10978_p2);
tmp_85_7_11_fu_11007_p2 <= (tmp250_fu_11001_p2 xor tmp249_fu_10995_p2);
tmp_85_7_12_fu_11025_p2 <= (tmp252_fu_11019_p2 xor tmp251_fu_11013_p2);
tmp_85_7_13_fu_11043_p2 <= (tmp254_fu_11037_p2 xor tmp253_fu_11031_p2);
tmp_85_7_14_fu_11055_p2 <= (tmp255_fu_11049_p2 xor rv_11_7_3_fu_10703_p3);
tmp_85_7_1_fu_10807_p2 <= (tmp227_fu_10801_p2 xor tmp226_fu_10795_p2);
tmp_85_7_2_fu_10825_p2 <= (tmp229_fu_10819_p2 xor tmp228_fu_10813_p2);
tmp_85_7_3_fu_10837_p2 <= (tmp230_fu_10831_p2 xor rv_11_7_fu_10259_p3);
tmp_85_7_4_fu_10855_p2 <= (tmp232_fu_10849_p2 xor tmp231_fu_10843_p2);
tmp_85_7_5_fu_10873_p2 <= (tmp234_fu_10867_p2 xor tmp233_fu_10861_p2);
tmp_85_7_6_fu_10891_p2 <= (tmp236_fu_10885_p2 xor tmp235_fu_10879_p2);
tmp_85_7_7_fu_10903_p2 <= (tmp237_fu_10897_p2 xor rv_11_7_1_fu_10407_p3);
tmp_85_7_8_fu_10926_p2 <= (tmp239_fu_10920_p2 xor tmp238_fu_10909_p2);
tmp_85_7_9_fu_10949_p2 <= (tmp242_fu_10943_p2 xor tmp241_fu_10932_p2);
tmp_85_7_fu_10789_p2 <= (tmp225_fu_10783_p2 xor tmp224_fu_10777_p2);
tmp_85_7_s_fu_10972_p2 <= (tmp245_fu_10966_p2 xor tmp244_fu_10955_p2);
tmp_85_8_10_fu_12031_p2 <= (tmp281_fu_12025_p2 xor rv_11_8_2_fu_11597_p3);
tmp_85_8_11_fu_12049_p2 <= (tmp283_fu_12043_p2 xor tmp282_fu_12037_p2);
tmp_85_8_12_fu_12067_p2 <= (tmp285_fu_12061_p2 xor tmp284_fu_12055_p2);
tmp_85_8_13_fu_12085_p2 <= (tmp287_fu_12079_p2 xor tmp286_fu_12073_p2);
tmp_85_8_14_fu_12097_p2 <= (tmp288_fu_12091_p2 xor rv_11_8_3_fu_11745_p3);
tmp_85_8_1_fu_11849_p2 <= (tmp260_fu_11843_p2 xor tmp259_fu_11837_p2);
tmp_85_8_2_fu_11867_p2 <= (tmp262_fu_11861_p2 xor tmp261_fu_11855_p2);
tmp_85_8_3_fu_11879_p2 <= (tmp263_fu_11873_p2 xor rv_11_8_fu_11301_p3);
tmp_85_8_4_fu_11902_p2 <= (tmp265_fu_11896_p2 xor tmp264_fu_11885_p2);
tmp_85_8_5_fu_11925_p2 <= (tmp268_fu_11919_p2 xor tmp267_fu_11908_p2);
tmp_85_8_6_fu_11948_p2 <= (tmp271_fu_11942_p2 xor tmp270_fu_11931_p2);
tmp_85_8_7_fu_11965_p2 <= (tmp274_fu_11960_p2 xor tmp273_fu_11954_p2);
tmp_85_8_8_fu_11983_p2 <= (tmp276_fu_11977_p2 xor tmp275_fu_11971_p2);
tmp_85_8_9_fu_12001_p2 <= (tmp278_fu_11995_p2 xor tmp277_fu_11989_p2);
tmp_85_8_fu_11831_p2 <= (tmp258_fu_11825_p2 xor tmp257_fu_11819_p2);
tmp_85_8_s_fu_12019_p2 <= (tmp280_fu_12013_p2 xor tmp279_fu_12007_p2);
tmp_85_fu_3515_p2 <= (tmp2_fu_3509_p2 xor tmp1_fu_3503_p2);
tmp_99_fu_2621_p1 <= inptext_V_read(8 - 1 downto 0);
tmp_9_fu_12209_p2 <= (ap_reg_pp0_iter9_tmp_69_7_reg_13709 xor tmp_4_fu_12203_p2);
tmp_fu_3417_p2 <= (p_Result_1_reg_12421 xor ap_const_lv8_1);
tmp_s_fu_12183_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_78_8_fu_11804_p2),64));
x_assign_0_1_fu_2973_p2 <= (sboxes_q9 xor sboxes_q4);
x_assign_0_2_fu_3121_p2 <= (sboxes_q13 xor sboxes_q8);
x_assign_0_3_fu_3269_p2 <= (sboxes_q1 xor sboxes_q12);
x_assign_10_fu_5951_p2 <= (sboxes_q65 xor sboxes_q60);
x_assign_171_1_fu_4015_p2 <= (sboxes_q29 xor sboxes_q24);
x_assign_171_2_fu_4163_p2 <= (sboxes_q33 xor sboxes_q28);
x_assign_171_3_fu_4311_p2 <= (sboxes_q21 xor sboxes_q32);
x_assign_1_0_1_fu_3019_p2 <= (sboxes_q14 xor sboxes_q9);
x_assign_1_0_2_fu_3167_p2 <= (sboxes_q2 xor sboxes_q13);
x_assign_1_0_3_fu_3315_p2 <= (sboxes_q6 xor sboxes_q1);
x_assign_1_1_1_fu_4061_p2 <= (sboxes_q34 xor sboxes_q29);
x_assign_1_1_2_fu_4209_p2 <= (sboxes_q22 xor sboxes_q33);
x_assign_1_1_3_fu_4357_p2 <= (sboxes_q26 xor sboxes_q21);
x_assign_1_1_fu_3913_p2 <= (sboxes_q30 xor sboxes_q25);
x_assign_1_2_1_fu_5103_p2 <= (sboxes_q54 xor sboxes_q49);
x_assign_1_2_2_fu_5251_p2 <= (sboxes_q42 xor sboxes_q53);
x_assign_1_2_3_fu_5399_p2 <= (sboxes_q46 xor sboxes_q41);
x_assign_1_2_fu_4955_p2 <= (sboxes_q50 xor sboxes_q45);
x_assign_1_3_1_fu_6145_p2 <= (sboxes_q74 xor sboxes_q69);
x_assign_1_3_2_fu_6293_p2 <= (sboxes_q62 xor sboxes_q73);
x_assign_1_3_3_fu_6441_p2 <= (sboxes_q66 xor sboxes_q61);
x_assign_1_3_fu_5997_p2 <= (sboxes_q70 xor sboxes_q65);
x_assign_1_4_1_fu_7187_p2 <= (sboxes_q94 xor sboxes_q89);
x_assign_1_4_2_fu_7335_p2 <= (sboxes_q82 xor sboxes_q93);
x_assign_1_4_3_fu_7483_p2 <= (sboxes_q86 xor sboxes_q81);
x_assign_1_4_fu_7039_p2 <= (sboxes_q90 xor sboxes_q85);
x_assign_1_5_1_fu_8229_p2 <= (sboxes_q114 xor sboxes_q109);
x_assign_1_5_2_fu_8377_p2 <= (sboxes_q102 xor sboxes_q113);
x_assign_1_5_3_fu_8525_p2 <= (sboxes_q106 xor sboxes_q101);
x_assign_1_5_fu_8081_p2 <= (sboxes_q110 xor sboxes_q105);
x_assign_1_6_1_fu_9271_p2 <= (sboxes_q134 xor sboxes_q129);
x_assign_1_6_2_fu_9419_p2 <= (sboxes_q122 xor sboxes_q133);
x_assign_1_6_3_fu_9567_p2 <= (sboxes_q126 xor sboxes_q121);
x_assign_1_6_fu_9123_p2 <= (sboxes_q130 xor sboxes_q125);
x_assign_1_7_1_fu_10313_p2 <= (sboxes_q154 xor sboxes_q149);
x_assign_1_7_2_fu_10461_p2 <= (sboxes_q142 xor sboxes_q153);
x_assign_1_7_3_fu_10609_p2 <= (sboxes_q146 xor sboxes_q141);
x_assign_1_7_fu_10165_p2 <= (sboxes_q150 xor sboxes_q145);
x_assign_1_8_1_fu_11355_p2 <= (sboxes_q174 xor sboxes_q169);
x_assign_1_8_2_fu_11503_p2 <= (sboxes_q162 xor sboxes_q173);
x_assign_1_8_3_fu_11651_p2 <= (sboxes_q166 xor sboxes_q161);
x_assign_1_8_fu_11207_p2 <= (sboxes_q170 xor sboxes_q165);
x_assign_1_fu_2871_p2 <= (sboxes_q10 xor sboxes_q5);
x_assign_273_1_fu_5057_p2 <= (sboxes_q49 xor sboxes_q44);
x_assign_273_2_fu_5205_p2 <= (sboxes_q53 xor sboxes_q48);
x_assign_273_3_fu_5353_p2 <= (sboxes_q41 xor sboxes_q52);
x_assign_2_0_1_fu_3053_p2 <= (sboxes_q3 xor sboxes_q14);
x_assign_2_0_2_fu_3201_p2 <= (sboxes_q7 xor sboxes_q2);
x_assign_2_0_3_fu_3349_p2 <= (sboxes_q11 xor sboxes_q6);
x_assign_2_1_1_fu_4095_p2 <= (sboxes_q23 xor sboxes_q34);
x_assign_2_1_2_fu_4243_p2 <= (sboxes_q27 xor sboxes_q22);
x_assign_2_1_3_fu_4391_p2 <= (sboxes_q31 xor sboxes_q26);
x_assign_2_1_fu_3947_p2 <= (sboxes_q35 xor sboxes_q30);
x_assign_2_2_1_fu_5137_p2 <= (sboxes_q43 xor sboxes_q54);
x_assign_2_2_2_fu_5285_p2 <= (sboxes_q47 xor sboxes_q42);
x_assign_2_2_3_fu_5433_p2 <= (sboxes_q51 xor sboxes_q46);
x_assign_2_2_fu_4989_p2 <= (sboxes_q55 xor sboxes_q50);
x_assign_2_3_1_fu_6179_p2 <= (sboxes_q63 xor sboxes_q74);
x_assign_2_3_2_fu_6327_p2 <= (sboxes_q67 xor sboxes_q62);
x_assign_2_3_3_fu_6475_p2 <= (sboxes_q71 xor sboxes_q66);
x_assign_2_3_fu_6031_p2 <= (sboxes_q75 xor sboxes_q70);
x_assign_2_4_1_fu_7221_p2 <= (sboxes_q83 xor sboxes_q94);
x_assign_2_4_2_fu_7369_p2 <= (sboxes_q87 xor sboxes_q82);
x_assign_2_4_3_fu_7517_p2 <= (sboxes_q91 xor sboxes_q86);
x_assign_2_4_fu_7073_p2 <= (sboxes_q95 xor sboxes_q90);
x_assign_2_5_1_fu_8263_p2 <= (sboxes_q103 xor sboxes_q114);
x_assign_2_5_2_fu_8411_p2 <= (sboxes_q107 xor sboxes_q102);
x_assign_2_5_3_fu_8559_p2 <= (sboxes_q111 xor sboxes_q106);
x_assign_2_5_fu_8115_p2 <= (sboxes_q115 xor sboxes_q110);
x_assign_2_6_1_fu_9305_p2 <= (sboxes_q123 xor sboxes_q134);
x_assign_2_6_2_fu_9453_p2 <= (sboxes_q127 xor sboxes_q122);
x_assign_2_6_3_fu_9601_p2 <= (sboxes_q131 xor sboxes_q126);
x_assign_2_6_fu_9157_p2 <= (sboxes_q135 xor sboxes_q130);
x_assign_2_7_1_fu_10347_p2 <= (sboxes_q143 xor sboxes_q154);
x_assign_2_7_2_fu_10495_p2 <= (sboxes_q147 xor sboxes_q142);
x_assign_2_7_3_fu_10643_p2 <= (sboxes_q151 xor sboxes_q146);
x_assign_2_7_fu_10199_p2 <= (sboxes_q155 xor sboxes_q150);
x_assign_2_8_1_fu_11389_p2 <= (sboxes_q163 xor sboxes_q174);
x_assign_2_8_2_fu_11537_p2 <= (sboxes_q167 xor sboxes_q162);
x_assign_2_8_3_fu_11685_p2 <= (sboxes_q171 xor sboxes_q166);
x_assign_2_8_fu_11241_p2 <= (sboxes_q175 xor sboxes_q170);
x_assign_2_fu_2905_p2 <= (sboxes_q15 xor sboxes_q10);
x_assign_375_1_fu_6099_p2 <= (sboxes_q69 xor sboxes_q64);
x_assign_375_2_fu_6247_p2 <= (sboxes_q73 xor sboxes_q68);
x_assign_375_3_fu_6395_p2 <= (sboxes_q61 xor sboxes_q72);
x_assign_3_0_1_fu_3087_p2 <= (sboxes_q3 xor sboxes_q4);
x_assign_3_0_2_fu_3235_p2 <= (sboxes_q7 xor sboxes_q8);
x_assign_3_0_3_fu_3383_p2 <= (sboxes_q11 xor sboxes_q12);
x_assign_3_1_1_fu_4129_p2 <= (sboxes_q23 xor sboxes_q24);
x_assign_3_1_2_fu_4277_p2 <= (sboxes_q27 xor sboxes_q28);
x_assign_3_1_3_fu_4425_p2 <= (sboxes_q31 xor sboxes_q32);
x_assign_3_1_fu_3981_p2 <= (sboxes_q35 xor sboxes_q20);
x_assign_3_2_1_fu_5171_p2 <= (sboxes_q43 xor sboxes_q44);
x_assign_3_2_2_fu_5319_p2 <= (sboxes_q47 xor sboxes_q48);
x_assign_3_2_3_fu_5467_p2 <= (sboxes_q51 xor sboxes_q52);
x_assign_3_2_fu_5023_p2 <= (sboxes_q55 xor sboxes_q40);
x_assign_3_3_1_fu_6213_p2 <= (sboxes_q63 xor sboxes_q64);
x_assign_3_3_2_fu_6361_p2 <= (sboxes_q67 xor sboxes_q68);
x_assign_3_3_3_fu_6509_p2 <= (sboxes_q71 xor sboxes_q72);
x_assign_3_3_fu_6065_p2 <= (sboxes_q75 xor sboxes_q60);
x_assign_3_4_1_fu_7255_p2 <= (sboxes_q83 xor sboxes_q84);
x_assign_3_4_2_fu_7403_p2 <= (sboxes_q87 xor sboxes_q88);
x_assign_3_4_3_fu_7551_p2 <= (sboxes_q91 xor sboxes_q92);
x_assign_3_4_fu_7107_p2 <= (sboxes_q95 xor sboxes_q80);
x_assign_3_5_1_fu_8297_p2 <= (sboxes_q103 xor sboxes_q104);
x_assign_3_5_2_fu_8445_p2 <= (sboxes_q107 xor sboxes_q108);
x_assign_3_5_3_fu_8593_p2 <= (sboxes_q111 xor sboxes_q112);
x_assign_3_5_fu_8149_p2 <= (sboxes_q115 xor sboxes_q100);
x_assign_3_6_1_fu_9339_p2 <= (sboxes_q123 xor sboxes_q124);
x_assign_3_6_2_fu_9487_p2 <= (sboxes_q127 xor sboxes_q128);
x_assign_3_6_3_fu_9635_p2 <= (sboxes_q131 xor sboxes_q132);
x_assign_3_6_fu_9191_p2 <= (sboxes_q135 xor sboxes_q120);
x_assign_3_7_1_fu_10381_p2 <= (sboxes_q143 xor sboxes_q144);
x_assign_3_7_2_fu_10529_p2 <= (sboxes_q147 xor sboxes_q148);
x_assign_3_7_3_fu_10677_p2 <= (sboxes_q151 xor sboxes_q152);
x_assign_3_7_fu_10233_p2 <= (sboxes_q155 xor sboxes_q140);
x_assign_3_8_1_fu_11423_p2 <= (sboxes_q163 xor sboxes_q164);
x_assign_3_8_2_fu_11571_p2 <= (sboxes_q167 xor sboxes_q168);
x_assign_3_8_3_fu_11719_p2 <= (sboxes_q171 xor sboxes_q172);
x_assign_3_8_fu_11275_p2 <= (sboxes_q175 xor sboxes_q160);
x_assign_3_fu_2939_p2 <= (sboxes_q15 xor sboxes_q0);
x_assign_4_1_fu_7141_p2 <= (sboxes_q89 xor sboxes_q84);
x_assign_4_2_fu_7289_p2 <= (sboxes_q93 xor sboxes_q88);
x_assign_4_3_fu_7437_p2 <= (sboxes_q81 xor sboxes_q92);
x_assign_4_fu_6993_p2 <= (sboxes_q85 xor sboxes_q80);
x_assign_5_1_fu_8183_p2 <= (sboxes_q109 xor sboxes_q104);
x_assign_5_2_fu_8331_p2 <= (sboxes_q113 xor sboxes_q108);
x_assign_5_3_fu_8479_p2 <= (sboxes_q101 xor sboxes_q112);
x_assign_5_fu_8035_p2 <= (sboxes_q105 xor sboxes_q100);
x_assign_6_1_fu_9225_p2 <= (sboxes_q129 xor sboxes_q124);
x_assign_6_2_fu_9373_p2 <= (sboxes_q133 xor sboxes_q128);
x_assign_6_3_fu_9521_p2 <= (sboxes_q121 xor sboxes_q132);
x_assign_6_fu_9077_p2 <= (sboxes_q125 xor sboxes_q120);
x_assign_7_1_fu_10267_p2 <= (sboxes_q149 xor sboxes_q144);
x_assign_7_2_fu_10415_p2 <= (sboxes_q153 xor sboxes_q148);
x_assign_7_3_fu_10563_p2 <= (sboxes_q141 xor sboxes_q152);
x_assign_7_fu_10119_p2 <= (sboxes_q145 xor sboxes_q140);
x_assign_8_1_fu_11309_p2 <= (sboxes_q169 xor sboxes_q164);
x_assign_8_2_fu_11457_p2 <= (sboxes_q173 xor sboxes_q168);
x_assign_8_3_fu_11605_p2 <= (sboxes_q161 xor sboxes_q172);
x_assign_8_fu_11161_p2 <= (sboxes_q165 xor sboxes_q160);
x_assign_9_fu_4909_p2 <= (sboxes_q45 xor sboxes_q40);
x_assign_fu_2825_p2 <= (sboxes_q5 xor sboxes_q0);
x_assign_s_fu_3867_p2 <= (sboxes_q25 xor sboxes_q20);
end behav;
|
gpl-3.0
|
mcoughli/root_of_trust
|
operational_os/hls/contact_discovery_hls_2017.1/solution1/impl/vhdl/contact_discoverycud.vhd
|
3
|
3126
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity contact_discoverycud_ram is
generic(
mem_type : string := "distributed";
dwidth : integer := 8;
awidth : integer := 6;
mem_size : integer := 64
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of contact_discoverycud_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "select_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity contact_discoverycud is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 64;
AddressWidth : INTEGER := 6);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of contact_discoverycud is
component contact_discoverycud_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
contact_discoverycud_ram_U : component contact_discoverycud_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
gpl-3.0
|
mcoughli/root_of_trust
|
operational_os/hls/contact_discovery_hls_2017.1/solution1/impl/ip/hdl/vhdl/contact_discovery.vhd
|
3
|
60167
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity contact_discovery is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
contacts_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
contacts_in_V_TVALID : IN STD_LOGIC;
contacts_in_V_TREADY : OUT STD_LOGIC;
database_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
database_in_V_TVALID : IN STD_LOGIC;
database_in_V_TREADY : OUT STD_LOGIC;
matched_out_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0);
matched_out_V_TVALID : OUT STD_LOGIC;
matched_out_V_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of contact_discovery is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.932500,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=4,HLS_SYN_DSP=0,HLS_SYN_FF=461,HLS_SYN_LUT=838}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal operation : STD_LOGIC_VECTOR (31 downto 0);
signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal operation_ap_vld : STD_LOGIC;
signal operation_ap_vld_preg : STD_LOGIC := '0';
signal operation_ap_vld_in_sig : STD_LOGIC;
signal matched_out_V_1_data_out : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_vld_in : STD_LOGIC;
signal matched_out_V_1_vld_out : STD_LOGIC;
signal matched_out_V_1_ack_in : STD_LOGIC;
signal matched_out_V_1_ack_out : STD_LOGIC;
signal matched_out_V_1_payload_A : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_payload_B : STD_LOGIC_VECTOR (7 downto 0);
signal matched_out_V_1_sel_rd : STD_LOGIC := '0';
signal matched_out_V_1_sel_wr : STD_LOGIC := '0';
signal matched_out_V_1_sel : STD_LOGIC;
signal matched_out_V_1_load_A : STD_LOGIC;
signal matched_out_V_1_load_B : STD_LOGIC;
signal matched_out_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal matched_out_V_1_state_cmp_full : STD_LOGIC;
signal matched_finished_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal matched_finished_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal matched_finished_1_vld_reg : STD_LOGIC := '0';
signal matched_finished_1_vld_in : STD_LOGIC;
signal matched_finished_1_ack_in : STD_LOGIC;
signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal error_out_1_vld_reg : STD_LOGIC := '0';
signal error_out_1_vld_in : STD_LOGIC;
signal error_out_1_ack_in : STD_LOGIC;
signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal contacts_size_out_1_vld_reg : STD_LOGIC := '0';
signal contacts_size_out_1_vld_in : STD_LOGIC;
signal contacts_size_out_1_ack_in : STD_LOGIC;
signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal contacts_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal contacts_ce0 : STD_LOGIC;
signal contacts_we0 : STD_LOGIC;
signal contacts_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal contacts_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal current_database_ite_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal current_database_ite_ce0 : STD_LOGIC;
signal current_database_ite_we0 : STD_LOGIC;
signal current_database_ite_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal operation_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal contacts_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal ap_CS_fsm_state13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none";
signal exitcond9_fu_444_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal database_in_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal exitcond8_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal matched_out_V_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal exitcond7_fu_346_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal grp_read_fu_98_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_fu_318_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_2_fu_335_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state6 : BOOLEAN;
signal i_5_fu_352_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_5_reg_512 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state7_io : BOOLEAN;
signal tmp_i_fu_362_p3 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_i_reg_517 : STD_LOGIC_VECTOR (12 downto 0);
signal cast_fu_370_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal i_6_fu_385_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal i_6_reg_530 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal exitcond_i_fu_379_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal found_1_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal icmp_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_nbreadreq_fu_151_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_450_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_block_state13 : BOOLEAN;
signal tmp_9_fu_473_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_3_reg_217 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal exitcond_fu_312_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_reg_228 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_1_nbreadreq_fu_129_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_239 : STD_LOGIC_VECTOR (0 downto 0);
signal contact_index_assign_reg_251 : STD_LOGIC_VECTOR (7 downto 0);
signal i_i_reg_262 : STD_LOGIC_VECTOR (6 downto 0);
signal comp_reg_273 : STD_LOGIC_VECTOR (0 downto 0);
signal i1_reg_285 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_fu_324_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_7_fu_341_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_i_7_fu_391_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_13_i_fu_401_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_468_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_11_fu_358_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal i_i_cast7_fu_375_p1 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_12_i_fu_396_p2 : STD_LOGIC_VECTOR (12 downto 0);
signal tmp_14_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_424_p4 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_6_fu_456_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i1_cast_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal ap_block_state11 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0);
component contact_discoverybkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discoverycud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (7 downto 0);
q0 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component contact_discovery_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
operation : OUT STD_LOGIC_VECTOR (31 downto 0);
operation_ap_vld : OUT STD_LOGIC;
matched_finished : IN STD_LOGIC_VECTOR (31 downto 0);
error_out : IN STD_LOGIC_VECTOR (31 downto 0);
contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
contacts_U : component contact_discoverybkb
generic map (
DataWidth => 8,
AddressRange => 8192,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => contacts_address0,
ce0 => contacts_ce0,
we0 => contacts_we0,
d0 => contacts_d0,
q0 => contacts_q0);
current_database_ite_U : component contact_discoverycud
generic map (
DataWidth => 8,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => current_database_ite_address0,
ce0 => current_database_ite_ce0,
we0 => current_database_ite_we0,
d0 => database_in_V_TDATA,
q0 => current_database_ite_q0);
contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
operation => operation,
operation_ap_vld => operation_ap_vld,
matched_finished => matched_finished_1_data_reg,
error_out => error_out_1_data_reg,
contacts_size_out => contacts_size_out_1_data_reg);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
matched_out_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_ack_out) and (ap_const_logic_1 = matched_out_V_1_vld_out))) then
matched_out_V_1_sel_rd <= not(matched_out_V_1_sel_rd);
end if;
end if;
end if;
end process;
matched_out_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_in))) then
matched_out_V_1_sel_wr <= not(matched_out_V_1_sel_wr);
end if;
end if;
end if;
end process;
matched_out_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
matched_out_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)))) then
matched_out_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)))) then
matched_out_V_1_state <= ap_const_lv2_1;
elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)) or ((matched_out_V_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out))) and not(((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out)))))) then
matched_out_V_1_state <= ap_const_lv2_3;
else
matched_out_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
operation_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_ap_vld_preg <= operation_ap_vld;
elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
operation_ap_vld_preg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
operation_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
operation_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
operation_preg <= operation;
end if;
end if;
end if;
end process;
comp_reg_273_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
comp_reg_273 <= found_1_fu_418_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
comp_reg_273 <= ap_const_lv1_1;
end if;
end if;
end process;
contact_index_assign_reg_251_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
contact_index_assign_reg_251 <= ap_const_lv8_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
contact_index_assign_reg_251 <= i_5_reg_512;
end if;
end if;
end process;
contacts_size_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size <= tmp_9_fu_473_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size <= ap_const_lv32_0;
end if;
end if;
end process;
contacts_size_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
error_out_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
i1_reg_285_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
i1_reg_285 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
i1_reg_285 <= i_4_fu_450_p2;
end if;
end if;
end process;
i_1_reg_228_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
i_1_reg_228 <= ap_const_lv7_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
i_1_reg_228 <= i_2_fu_335_p2;
end if;
end if;
end process;
i_3_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2))) then
i_3_reg_217 <= i_fu_318_p2;
elsif (((grp_read_fu_98_p2 = ap_const_lv32_2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
i_3_reg_217 <= ap_const_lv8_0;
end if;
end if;
end process;
i_i_reg_262_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
i_i_reg_262 <= i_6_reg_530;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
i_i_reg_262 <= ap_const_lv7_0;
end if;
end if;
end process;
matched_finished_1_vld_reg_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
end if;
end process;
tmp_10_reg_239_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
tmp_10_reg_239 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
tmp_10_reg_239 <= found_fu_406_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_data_reg <= contacts_size_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_data_reg <= error_out_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0))) then
i_5_reg_512 <= i_5_fu_352_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
i_6_reg_530 <= i_6_fu_385_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_0 = matched_finished_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_data_reg <= matched_finished_1_data_in;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_A)) then
matched_out_V_1_payload_A <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = matched_out_V_1_load_B)) then
matched_out_V_1_payload_B <= cast_fu_370_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
tmp_i_reg_517(12 downto 6) <= tmp_i_fu_362_p3(12 downto 6);
end if;
end if;
end process;
tmp_i_reg_517(5 downto 0) <= "000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_in_V_TVALID, database_in_V_TVALID, matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state2, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10, grp_read_fu_98_p2, ap_CS_fsm_state4, ap_block_state7_io, ap_CS_fsm_state8, exitcond_i_fu_379_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3, ap_CS_fsm_state3, exitcond_fu_312_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3, ap_CS_fsm_state11)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
if ((not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_lv32_0 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state12;
elsif (((ap_const_lv32_1 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_312_p2))) then
ap_NS_fsm <= ap_ST_fsm_state11;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then
ap_NS_fsm <= ap_ST_fsm_state8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state8 =>
if (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state9;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state8;
when ap_ST_fsm_state10 =>
if (((ap_const_logic_1 = ap_CS_fsm_state10) and (matched_out_V_1_ack_in = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state11 =>
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state11;
end if;
when ap_ST_fsm_state12 =>
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_0 = tmp_nbreadreq_fu_151_p3))) then
ap_NS_fsm <= ap_ST_fsm_state11;
elsif (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then
ap_NS_fsm <= ap_ST_fsm_state13;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when ap_ST_fsm_state13 =>
if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then
ap_NS_fsm <= ap_ST_fsm_state13;
elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state13;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state15 =>
if (((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_state15;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state13 <= ap_CS_fsm(12);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state11_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in)
begin
ap_block_state11 <= ((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in));
end process;
ap_block_state13_assign_proc : process(contacts_in_V_TVALID, exitcond9_fu_444_p2)
begin
ap_block_state13 <= ((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID));
end process;
ap_block_state6_assign_proc : process(database_in_V_TVALID, exitcond8_fu_329_p2)
begin
ap_block_state6 <= ((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID));
end process;
ap_block_state7_io_assign_proc : process(matched_out_V_1_ack_in, exitcond7_fu_346_p2)
begin
ap_block_state7_io <= ((ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_const_logic_0 = matched_out_V_1_ack_in));
end process;
ap_done_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
cast_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_239),8));
contacts_address0_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state4, ap_CS_fsm_state8, tmp_3_fu_324_p1, tmp_13_i_fu_401_p1, tmp_s_fu_468_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_address0 <= tmp_s_fu_468_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then
contacts_address0 <= tmp_13_i_fu_401_p1(13 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_address0 <= tmp_3_fu_324_p1(13 - 1 downto 0);
else
contacts_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
contacts_ce0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, ap_CS_fsm_state8)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_ce0 <= ap_const_logic_1;
else
contacts_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_d0_assign_proc : process(contacts_in_V_TDATA, ap_CS_fsm_state13, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state13)) then
contacts_d0 <= contacts_in_V_TDATA;
elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then
contacts_d0 <= ap_const_lv8_0;
else
contacts_d0 <= "XXXXXXXX";
end if;
end process;
contacts_in_V_TDATA_blk_n_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2)))) then
contacts_in_V_TDATA_blk_n <= contacts_in_V_TVALID;
else
contacts_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
contacts_in_V_TREADY_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1)))) then
contacts_in_V_TREADY <= ap_const_logic_1;
else
contacts_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg)
begin
if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
contacts_size_out_1_ack_in <= ap_const_logic_1;
else
contacts_size_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
contacts_size_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, contacts_size, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, tmp_9_fu_473_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then
contacts_size_out_1_data_in <= tmp_9_fu_473_p2;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))))) then
contacts_size_out_1_data_in <= contacts_size;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then
contacts_size_out_1_data_in <= ap_const_lv32_0;
else
contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
contacts_size_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
contacts_size_out_1_vld_in <= ap_const_logic_1;
else
contacts_size_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
contacts_we0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, exitcond_fu_312_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then
contacts_we0 <= ap_const_logic_1;
else
contacts_we0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_address0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state8, tmp_7_fu_341_p1, tmp_i_7_fu_391_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
current_database_ite_address0 <= tmp_i_7_fu_391_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
current_database_ite_address0 <= tmp_7_fu_341_p1(6 - 1 downto 0);
else
current_database_ite_address0 <= "XXXXXX";
end if;
end process;
current_database_ite_ce0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state8)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID)))) or (ap_const_logic_1 = ap_CS_fsm_state8))) then
current_database_ite_ce0 <= ap_const_logic_1;
else
current_database_ite_ce0 <= ap_const_logic_0;
end if;
end process;
current_database_ite_we0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
current_database_ite_we0 <= ap_const_logic_1;
else
current_database_ite_we0 <= ap_const_logic_0;
end if;
end process;
database_in_V_TDATA_blk_n_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2))) then
database_in_V_TDATA_blk_n <= database_in_V_TVALID;
else
database_in_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
database_in_V_TREADY_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then
database_in_V_TREADY <= ap_const_logic_1;
else
database_in_V_TREADY <= ap_const_logic_0;
end if;
end process;
error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg)
begin
if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
error_out_1_ack_in <= ap_const_logic_1;
else
error_out_1_ack_in <= ap_const_logic_0;
end if;
end process;
error_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2))) then
error_out_1_data_in <= ap_const_lv32_1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_3;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
error_out_1_data_in <= ap_const_lv32_0;
else
error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
error_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2)))) then
error_out_1_vld_in <= ap_const_logic_1;
else
error_out_1_vld_in <= ap_const_logic_0;
end if;
end process;
exitcond7_fu_346_p2 <= "1" when (contact_index_assign_reg_251 = ap_const_lv8_80) else "0";
exitcond8_fu_329_p2 <= "1" when (i_1_reg_228 = ap_const_lv7_40) else "0";
exitcond9_fu_444_p2 <= "1" when (i1_reg_285 = ap_const_lv7_40) else "0";
exitcond_fu_312_p2 <= "1" when (i_3_reg_217 = ap_const_lv8_80) else "0";
exitcond_i_fu_379_p2 <= "1" when (i_i_reg_262 = ap_const_lv7_40) else "0";
found_1_fu_418_p2 <= (tmp_14_i_fu_412_p2 and comp_reg_273);
found_fu_406_p2 <= (comp_reg_273 or tmp_10_reg_239);
grp_read_fu_98_p2 <= operation_preg;
i1_cast_fu_440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_reg_285),32));
i_2_fu_335_p2 <= std_logic_vector(unsigned(i_1_reg_228) + unsigned(ap_const_lv7_1));
i_4_fu_450_p2 <= std_logic_vector(unsigned(i1_reg_285) + unsigned(ap_const_lv7_1));
i_5_fu_352_p2 <= std_logic_vector(unsigned(contact_index_assign_reg_251) + unsigned(ap_const_lv8_1));
i_6_fu_385_p2 <= std_logic_vector(unsigned(i_i_reg_262) + unsigned(ap_const_lv7_1));
i_fu_318_p2 <= std_logic_vector(unsigned(i_3_reg_217) + unsigned(ap_const_lv8_1));
i_i_cast7_fu_375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),13));
icmp_fu_434_p2 <= "1" when (signed(tmp_2_fu_424_p4) > signed(ap_const_lv25_0)) else "0";
matched_finished_1_ack_in_assign_proc : process(matched_finished_1_vld_reg)
begin
if (((ap_const_logic_0 = matched_finished_1_vld_reg) or ((ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then
matched_finished_1_ack_in <= ap_const_logic_1;
else
matched_finished_1_ack_in <= ap_const_logic_0;
end if;
end process;
matched_finished_1_data_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3))) then
matched_finished_1_data_in <= ap_const_lv32_1;
elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then
matched_finished_1_data_in <= ap_const_lv32_0;
else
matched_finished_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
matched_finished_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3)))) then
matched_finished_1_vld_in <= ap_const_logic_1;
else
matched_finished_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_ack_in <= matched_out_V_1_state(1);
matched_out_V_1_ack_out <= matched_out_V_TREADY;
matched_out_V_1_data_out_assign_proc : process(matched_out_V_1_payload_A, matched_out_V_1_payload_B, matched_out_V_1_sel)
begin
if ((ap_const_logic_1 = matched_out_V_1_sel)) then
matched_out_V_1_data_out <= matched_out_V_1_payload_B;
else
matched_out_V_1_data_out <= matched_out_V_1_payload_A;
end if;
end process;
matched_out_V_1_load_A <= (matched_out_V_1_state_cmp_full and not(matched_out_V_1_sel_wr));
matched_out_V_1_load_B <= (matched_out_V_1_sel_wr and matched_out_V_1_state_cmp_full);
matched_out_V_1_sel <= matched_out_V_1_sel_rd;
matched_out_V_1_state_cmp_full <= '0' when (matched_out_V_1_state = ap_const_lv2_1) else '1';
matched_out_V_1_vld_in_assign_proc : process(ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_block_state7_io)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then
matched_out_V_1_vld_in <= ap_const_logic_1;
else
matched_out_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
matched_out_V_1_vld_out <= matched_out_V_1_state(0);
matched_out_V_TDATA <= matched_out_V_1_data_out;
matched_out_V_TDATA_blk_n_assign_proc : process(matched_out_V_1_state, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2)) or (ap_const_logic_1 = ap_CS_fsm_state10))) then
matched_out_V_TDATA_blk_n <= matched_out_V_1_state(1);
else
matched_out_V_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
matched_out_V_TVALID <= matched_out_V_1_state(0);
operation_ap_vld_in_sig <= operation_ap_vld_preg;
operation_blk_n_assign_proc : process(ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
operation_blk_n <= ap_const_logic_0;
else
operation_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_11_fu_358_p1 <= contact_index_assign_reg_251(7 - 1 downto 0);
tmp_12_i_fu_396_p2 <= std_logic_vector(unsigned(i_i_cast7_fu_375_p1) + unsigned(tmp_i_reg_517));
tmp_13_i_fu_401_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_i_fu_396_p2),64));
tmp_14_i_fu_412_p2 <= "1" when (current_database_ite_q0 = contacts_q0) else "0";
tmp_1_nbreadreq_fu_129_p3 <= (0=>database_in_V_TVALID, others=>'-');
tmp_2_fu_424_p4 <= contacts_size(31 downto 7);
tmp_3_fu_324_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_3_reg_217),64));
tmp_6_fu_456_p2 <= std_logic_vector(shift_left(unsigned(contacts_size),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
tmp_7_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_228),64));
tmp_8_fu_462_p2 <= std_logic_vector(unsigned(tmp_6_fu_456_p2) + unsigned(i1_cast_fu_440_p1));
tmp_9_fu_473_p2 <= std_logic_vector(unsigned(contacts_size) + unsigned(ap_const_lv32_1));
tmp_i_7_fu_391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),64));
tmp_i_fu_362_p3 <= (tmp_11_fu_358_p1 & ap_const_lv6_0);
tmp_nbreadreq_fu_151_p3 <= (0=>contacts_in_V_TVALID, others=>'-');
tmp_s_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_fu_462_p2),64));
end behav;
|
gpl-3.0
|
scottlbaker/Nova-SOC
|
src/mem.vhd
|
2
|
7347
|
--=================================================================
-- MEM.VHD :: 8Kx16 RAM model loaded with Hex Format
--
-- (c) Scott L. Baker, Sierra Circuit Design
--=================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
entity RAM is
port(
RADDR : in std_logic_vector(12 downto 0);
WADDR : in std_logic_vector(12 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
BYTEOP : in std_logic; -- byte operation
REN : in std_logic; -- read enable
WEN : in std_logic; -- write enable
WCLK : in std_logic;
RCLK : in std_logic
);
end RAM;
architecture BEHAVIORAL of RAM is
type Memtype is array (integer range 0 to 16383) of std_logic_vector(7 downto 0);
file progfile : TEXT OPEN read_mode is "mem.hex";
signal Rd_Addr : integer range 16383 downto 0;
signal Wr_Addr : integer range 16383 downto 0;
signal Initialized : boolean := FALSE;
--==========================================
-- character to integer conversion function
--==========================================
function char_to_int(ch : character ) return integer is
variable result : integer := 0;
begin
case ch is
when '0' => result := 0;
when '1' => result := 1;
when '2' => result := 2;
when '3' => result := 3;
when '4' => result := 4;
when '5' => result := 5;
when '6' => result := 6;
when '7' => result := 7;
when '8' => result := 8;
when '9' => result := 9;
when 'a' => result := 10;
when 'b' => result := 11;
when 'c' => result := 12;
when 'd' => result := 13;
when 'e' => result := 14;
when 'f' => result := 15;
when 'A' => result := 10;
when 'B' => result := 11;
when 'C' => result := 12;
when 'D' => result := 13;
when 'E' => result := 14;
when 'F' => result := 15;
when others => result := 0;
end case;
return result;
end function char_to_int;
begin
Rd_Addr <= conv_integer(RADDR(12 downto 1) & '0');
Wr_Addr <= conv_integer(WADDR(12 downto 1) & '0');
--==========================================
-- Configurable Memory Model
--==========================================
MEMORY:
process (DATA_IN, Rd_Addr, Wr_Addr, RCLK, WCLK)
variable DATA : Memtype;
variable L : line;
variable ch : character;
variable rec_type : character;
variable digit : integer;
variable byte : integer;
variable byte_no : integer;
variable num_bytes : integer;
variable address : integer;
variable offset : integer;
variable end_of_data : boolean;
variable line_num : integer;
begin
-- Init from file
if not Initialized then
Initialized <= TRUE;
line_num := 0;
offset := 0;
end_of_data := FALSE;
while not (endfile(progfile) or end_of_data) loop
-- Reset the variables for the line
address := 0;
line_num := line_num + 1;
readline(progfile, L);
-- Read in the : character
read(L, ch);
if ch /= ':' then
next; -- get the next character
end if;
-- Read in the number of bytes
read(L, ch); -- msb
digit := char_to_int(ch);
read(L, ch); -- lsb
num_bytes := digit*16 + char_to_int(ch);
-- Read in the address
for k in 3 downto 0 loop
read(L, ch);
digit := char_to_int(ch);
address := address + digit * 16**k;
end loop;
-- Read in the record type
read(L,ch);
ASSERT ch = '0'
REPORT "Illegal record on line " & INTEGER'IMAGE(line_num);
read(L,rec_type);
-- If it is a line of all zeros, then it is the end of data.
if (num_bytes = 0) and (address = 0) then
end_of_data := TRUE;
-- If it is normal data, then read in all of the bytes to program_mem
elsif rec_type = '0' then -- it has normal data
byte_no := 0;
for byte_no in 0 to num_bytes-1 loop
read(L,ch);
digit := char_to_int(ch);
read(L,ch);
byte := digit*16 + char_to_int(ch);
DATA(offset + address + byte_no) := conv_std_logic_vector(byte, 8);
-- REPORT "writing data " & INTEGER'IMAGE(byte) & " to address " &
-- INTEGER'IMAGE(offset + address + byte_no);
end loop;
-- If it is an end of file record, then set end_of_data true
elsif rec_type = '1' then -- it is an end of file record
end_of_data := true;
-- If is an address-offset record update offset
elsif rec_type = '2' then
offset := 0;
for k in 3 downto 0 loop
read(l, ch);
digit := char_to_int(ch);
offset := offset + digit*16**k;
end loop;
offset := offset *16;
end if;
end loop;
else
-- Synchronous Read
if (RCLK = '1' and RCLK'event) then
if (REN = '1') then
DATA_OUT <= DATA(Rd_Addr+1) & DATA(Rd_Addr);
end if;
end if;
-- Synchronous Write
if (WCLK = '1' and WCLK'event) then
if (WEN = '1') then
if (BYTEOP = '1') then
if (WADDR(0) = '1') then
DATA(Wr_Addr+1) := DATA_IN(15 downto 8);
else
DATA(Wr_Addr) := DATA_IN( 7 downto 0);
end if;
else
DATA(Wr_Addr+1) := DATA_IN(15 downto 8);
DATA(Wr_Addr) := DATA_IN( 7 downto 0);
end if;
end if;
end if;
end if;
end process;
end BEHAVIORAL;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/1541/vhdl_source/gcr2bin.vhd
|
5
|
1154
|
library ieee;
use ieee.std_logic_1164.all;
entity gcr2bin is
port (
d_in : in std_logic_vector(4 downto 0);
d_out : out std_logic_vector(3 downto 0);
error : out std_logic );
end gcr2bin;
architecture rom of gcr2bin is
begin
process(d_in)
begin
d_out <= X"0";
error <= '0';
case d_in is
when "01010" => d_out <= "0000";
when "01011" => d_out <= "0001";
when "10010" => d_out <= "0010";
when "10011" => d_out <= "0011";
when "01110" => d_out <= "0100";
when "01111" => d_out <= "0101";
when "10110" => d_out <= "0110";
when "10111" => d_out <= "0111";
when "01001" => d_out <= "1000";
when "11001" => d_out <= "1001";
when "11010" => d_out <= "1010";
when "11011" => d_out <= "1011";
when "01101" => d_out <= "1100";
when "11101" => d_out <= "1101";
when "11110" => d_out <= "1110";
when "10101" => d_out <= "1111";
when others =>
error <= '1';
end case;
end process;
end rom;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/1541/vhdl_source/floppy_sound.vhd
|
4
|
6762
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
rate_div : natural := 2176; -- 22050 Hz
sound_base : unsigned(27 downto 16) := X"103";
motor_hum_addr : unsigned(15 downto 0) := X"0000";
flop_slip_addr : unsigned(15 downto 0) := X"1200";
track_in_addr : unsigned(15 downto 0) := X"2400";
track_out_addr : unsigned(15 downto 0) := X"2E00";
head_bang_addr : unsigned(15 downto 0) := X"3800";
motor_len : integer := 4410;
track_in_len : unsigned(15 downto 0) := X"089D"; -- 100 ms;
track_out_len : unsigned(15 downto 0) := X"089D"; -- 100 ms;
head_bang_len : unsigned(15 downto 0) := X"089D" ); -- 100 ms;
port (
clock : in std_logic;
reset : in std_logic;
do_trk_out : in std_logic;
do_trk_in : in std_logic;
do_head_bang : in std_logic;
en_hum : in std_logic;
en_slip : in std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- audio
sample_out : out signed(12 downto 0) := (others => '0'));
end floppy_sound;
architecture gideon of floppy_sound is
signal rate_count : integer range 0 to rate_div;
signal motor_sample : signed(7 downto 0);
signal head_sample : signed(7 downto 0);
signal sample_tick : std_logic;
type t_voice_state is (idle, play);
type t_serve_state is (idle, wait_voice1, serve_voice2, wait_voice2);
signal voice1 : t_voice_state;
signal serve_state : t_serve_state;
signal voice1_cnt : unsigned(13 downto 0); -- max 16K
signal voice1_addr : unsigned(15 downto 0);
signal voice2_cnt : unsigned(13 downto 0); -- max 16K
signal mem_addr_i : unsigned(15 downto 0);
signal mem_rack : std_logic;
signal mem_dack : std_logic;
begin
mem_req.tag <= g_tag;
mem_req.read_writen <= '1'; -- always read
mem_req.address <= sound_base(25 downto 16) & mem_addr_i;
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
process(clock)
variable signed_sum : signed(12 downto 0);
begin
if rising_edge(clock) then
sample_tick <= '0';
if rate_count = 0 then
signed_sum := motor_sample + (head_sample(head_sample'high) & head_sample & "0000");
sample_out <= signed_sum;
rate_count <= rate_div;
sample_tick <= '1';
else
rate_count <= rate_count - 1;
end if;
case serve_state is
when idle =>
if sample_tick='1' then
case voice1 is
when play =>
if voice1_cnt = 0 then
voice1 <= idle;
else
mem_req.request <= '1';
mem_addr_i <= voice1_addr;
serve_state <= wait_voice1;
end if;
when others =>
head_sample <= X"00";
serve_state <= serve_voice2;
end case;
end if;
when wait_voice1 =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
head_sample <= signed(mem_resp.data);
voice1_cnt <= voice1_cnt - 1;
voice1_addr <= voice1_addr + 1;
serve_state <= serve_voice2;
end if;
when serve_voice2 =>
if en_hum = '1' then
mem_req.request <= '1';
mem_addr_i <= motor_hum_addr(15 downto 0) + ("00" & voice2_cnt);
serve_state <= wait_voice2;
elsif en_slip = '1' then
mem_req.request <= '1';
mem_addr_i <= flop_slip_addr(15 downto 0) + ("00" & voice2_cnt);
serve_state <= wait_voice2;
else
serve_state <= idle;
-- if motor_sample(7)='1' then
-- motor_sample <= motor_sample + 1; -- is negative, go to zero
-- elsif motor_sample /= 0 then
-- motor_sample <= motor_sample - 1;
-- end if;
end if;
when wait_voice2 =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
motor_sample <= signed(mem_resp.data);
if voice2_cnt = motor_len-1 then
voice2_cnt <= (others => '0');
else
voice2_cnt <= voice2_cnt + 1;
end if;
serve_state <= idle;
end if;
when others =>
null;
end case;
if do_trk_out = '1' then
voice1 <= play;
voice1_cnt <= track_out_len(voice1_cnt'range);
voice1_addr <= track_out_addr(voice1_addr'range);
end if;
if do_trk_in = '1' then
voice1 <= play;
voice1_cnt <= track_in_len(voice1_cnt'range);
voice1_addr <= track_in_addr(voice1_addr'range);
end if;
if do_head_bang = '1' then
voice1 <= play;
voice1_cnt <= head_bang_len(voice1_cnt'range);
voice1_addr <= head_bang_addr(voice1_addr'range);
end if;
if reset='1' then
mem_req.request <= '0';
serve_state <= idle;
voice1 <= idle;
voice1_cnt <= (others => '0');
voice2_cnt <= (others => '0');
voice1_addr <= (others => '0');
sample_out <= (others => '0');
motor_sample <= (others => '0');
end if;
end if;
end process;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/1541/vhdl_source/via6522.vhd
|
1
|
21899
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity via6522 is
port (
clock : in std_logic;
clock_en : in std_logic; -- for counters and stuff
reset : in std_logic;
addr : in std_logic_vector(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- handshake pins
ca1_i : in std_logic;
ca2_o : out std_logic;
ca2_i : in std_logic;
ca2_t : out std_logic;
cb1_o : out std_logic;
cb1_i : in std_logic;
cb1_t : out std_logic;
cb2_o : out std_logic;
cb2_i : in std_logic;
cb2_t : out std_logic;
irq : out std_logic );
end via6522;
architecture Gideon of via6522 is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
signal pio_i : pio_t;
signal irq_mask : std_logic_vector(6 downto 0) := (others => '0');
signal irq_flags : std_logic_vector(6 downto 0) := (others => '0');
signal irq_events : std_logic_vector(6 downto 0) := (others => '0');
signal irq_out : std_logic;
signal timer_a_latch : std_logic_vector(15 downto 0);
signal timer_b_latch : std_logic_vector(7 downto 0);
signal timer_a_count : std_logic_vector(15 downto 0) := X"0000";
signal timer_b_count : std_logic_vector(15 downto 0) := X"0000";
signal timer_a_out : std_logic;
signal timer_b_tick : std_logic;
signal acr, pcr : std_logic_vector(7 downto 0) := X"00";
signal shift_reg : std_logic_vector(7 downto 0) := X"00";
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
alias cb2_event : std_logic is irq_events(3);
alias cb1_event : std_logic is irq_events(4);
alias timer_b_event : std_logic is irq_events(5);
alias timer_a_event : std_logic is irq_events(6);
alias ca2_flag : std_logic is irq_flags(0);
alias ca1_flag : std_logic is irq_flags(1);
alias serial_flag : std_logic is irq_flags(2);
alias cb2_flag : std_logic is irq_flags(3);
alias cb1_flag : std_logic is irq_flags(4);
alias timer_b_flag : std_logic is irq_flags(5);
alias timer_a_flag : std_logic is irq_flags(6);
alias tmr_a_output_en : std_logic is acr(7);
alias tmr_a_freerun : std_logic is acr(6);
alias tmr_b_count_mode : std_logic is acr(5);
alias shift_dir : std_logic is acr(4);
alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2);
alias pb_latch_en : std_logic is acr(1);
alias pa_latch_en : std_logic is acr(0);
alias cb2_is_output : std_logic is pcr(7);
alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input
alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input
alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5);
alias cb1_edge_select : std_logic is pcr(4);
alias ca2_is_output : std_logic is pcr(3);
alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input
alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input
alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1);
alias ca1_edge_select : std_logic is pcr(0);
signal ira, irb : std_logic_vector(7 downto 0) := (others => '0');
signal write_t1c_h : std_logic;
signal write_t2c_h : std_logic;
signal ca1_c, ca2_c : std_logic;
signal cb1_c, cb2_c : std_logic;
signal ca1_d, ca2_d : std_logic;
signal cb1_d, cb2_d : std_logic;
signal set_ca2_low : std_logic;
signal set_cb2_low : std_logic;
begin
irq <= irq_out;
irq_out <= '0' when (irq_flags and irq_mask) = "0000000" else '1';
write_t1c_h <= '1' when addr = X"5" and wen='1' else '0';
write_t2c_h <= '1' when addr = X"9" and wen='1' else '0';
-- input latches
-- ira <= port_a_i when (ca1_flag='0') or (pa_latch_en='0'); -- latch
-- moved to clocked process
irb <= port_b_i;-- when (ca1_flag='0') or (pb_latch_en='0'); -- latch. Port doesn't have a latch!
ca1_event <= (ca1_c xor ca1_d) and (ca1_d xor ca1_edge_select);
ca2_event <= (ca2_c xor ca2_d) and (ca2_d xor ca2_edge_select);
cb1_event <= (cb1_c xor cb1_d) and (cb1_d xor cb1_edge_select);
cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o <= hs_cb2_o when serport_en='0' else ser_cb2_o;
process(clock)
begin
if rising_edge(clock) then
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
ca1_d <= ca1_c;
ca2_d <= ca2_c;
cb1_d <= cb1_c;
cb2_d <= cb2_c;
-- input latch for port a
if ca1_flag='0' or pa_latch_en='0' then
ira <= port_a_i;
end if;
-- CA2 output logic
case ca2_out_mode is
when "00" =>
if ca1_event='1' then
ca2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"1" then
ca2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
ca2_o <= not set_ca2_low;
set_ca2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"1" then
if clock_en='1' then
ca2_o <= '0';
else
set_ca2_low <= '1';
end if;
end if;
when "10" =>
ca2_o <= '0';
when "11" =>
ca2_o <= '1';
when others =>
null;
end case;
-- CB2 output logic
case cb2_out_mode is
when "00" =>
if cb1_event='1' then
hs_cb2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"0" then
hs_cb2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
hs_cb2_o <= not set_cb2_low;
set_cb2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"0" then
if clock_en='1' then
hs_cb2_o <= '0';
else
set_cb2_low <= '1';
end if;
end if;
when "10" =>
hs_cb2_o <= '0';
when "11" =>
hs_cb2_o <= '1';
when others =>
null;
end case;
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
-- Writes --
if wen='1' then
case addr is
when X"0" => -- ORB
pio_i.prb <= data_in;
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
pio_i.pra <= data_in;
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"2" => -- DDRB
pio_i.ddrb <= data_in;
when X"3" => -- DDRA
pio_i.ddra <= data_in;
when X"4" => -- TA LO counter (write=latch)
timer_a_latch(7 downto 0) <= data_in;
when X"5" => -- TA HI counter
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"6" => -- TA LO latch
timer_a_latch(7 downto 0) <= data_in;
when X"7" => -- TA HI latch
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"8" => -- TB LO latch
timer_b_latch(7 downto 0) <= data_in;
when X"9" => -- TB HI counter
timer_b_flag <= '0';
when X"A" => -- Serial port
serial_flag <= '0';
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
when X"C" => -- PCR (Peripheral Control Register)
pcr <= data_in;
when X"D" => -- IFR
irq_flags <= irq_flags and not data_in(6 downto 0);
when X"E" => -- IER
if data_in(7)='1' then -- set
irq_mask <= irq_mask or data_in(6 downto 0);
else -- clear
irq_mask <= irq_mask and not data_in(6 downto 0);
end if;
when X"F" => -- ORA no handshake
pio_i.pra <= data_in;
when others =>
null;
end case;
end if;
-- Reads --
case addr is
when X"0" => -- ORB
data_out <= irb;
if cb2_no_irq_clr='0' and ren='1' then
cb2_flag <= '0';
end if;
if ren='1' then
cb1_flag <= '0';
end if;
when X"1" => -- ORA
data_out <= ira;
if ca2_no_irq_clr='0' and ren='1' then
ca2_flag <= '0';
end if;
if ren='1' then
ca1_flag <= '0';
end if;
when X"2" => -- DDRB
data_out <= pio_i.ddrb;
when X"3" => -- DDRA
data_out <= pio_i.ddrb;
when X"4" => -- TA LO counter
data_out <= timer_a_count(7 downto 0);
if ren='1' then
timer_a_flag <= '0';
end if;
when X"5" => -- TA HI counter
data_out <= timer_a_count(15 downto 8);
when X"6" => -- TA LO latch
data_out <= timer_a_latch(7 downto 0);
when X"7" => -- TA HI latch
data_out <= timer_a_latch(15 downto 8);
when X"8" => -- TA LO counter
data_out <= timer_b_count(7 downto 0);
if ren='1' then
timer_b_flag <= '0';
end if;
when X"9" => -- TA HI counter
data_out <= timer_b_count(15 downto 8);
when X"A" => -- SR
data_out <= shift_reg;
if ren='1' then
serial_flag <= '0';
end if;
when X"B" => -- ACR
data_out <= acr;
when X"C" => -- PCR
data_out <= pcr;
when X"D" => -- IFR
data_out <= irq_out & irq_flags;
when X"E" => -- IER
data_out <= '0' & irq_mask;
when X"F" => -- ORA
data_out <= port_a_i;
when others =>
null;
end case;
if reset='1' then
pio_i <= pio_default;
irq_mask <= (others => '0');
irq_flags <= (others => '0');
timer_a_latch <= (others => '0');
timer_b_latch <= (others => '0');
acr <= (others => '0');
pcr <= (others => '0');
ca2_o <= '1';
hs_cb2_o <= '1';
set_ca2_low <= '0';
set_cb2_low <= '0';
end if;
end if;
end process;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(6 downto 0) <= pio_i.prb(6 downto 0);
port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out;
port_a_t <= pio_i.ddra;
port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0);
port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en;
-- Timer A
tmr_a: block
signal timer_a_reload : std_logic;
signal timer_a_run : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
timer_a_event <= '0';
if clock_en='1' then
-- always count, or load
if timer_a_reload = '1' then
timer_a_count <= timer_a_latch;
timer_a_reload <= '0';
else
timer_a_count <= timer_a_count - 1;
end if;
if timer_a_count = 0 then
-- generate an event if we were triggered
timer_a_event <= timer_a_run;
-- continue to be triggered in free running mode
timer_a_run <= tmr_a_freerun;
-- toggle output
timer_a_out <= not timer_a_out;
-- if in free running mode, set a flag to reload
timer_a_reload <= tmr_a_freerun;
end if;
end if;
if write_t1c_h = '1' then
timer_a_out <= '0';
timer_a_count <= data_in & timer_a_latch(7 downto 0);
timer_a_run <= '1';
end if;
if reset='1' then
timer_a_count <= (others => '0');
timer_a_out <= '1';
timer_a_reload <= '0';
timer_a_run <= '0';
end if;
end if;
end process;
end block tmr_a;
-- Timer B
tmr_b: block
signal timer_b_trig : std_logic;
signal pb6_c, pb6_d : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
timer_b_event <= '0';
timer_b_tick <= '0';
pb6_c <= port_b_i(6);
if timer_b_count = X"0000" and timer_b_trig='1' then
timer_b_event <= '1';
timer_b_trig <= '0';
end if;
if clock_en='1' then
pb6_d <= pb6_c;
if tmr_b_count_mode = '1' then
if (pb6_d='0' and pb6_c='1') then
timer_b_count <= timer_b_count - 1;
end if;
else -- one shot or used for shirt register
if timer_b_count = X"0000" then
timer_b_count <= X"00" & timer_b_latch(7 downto 0);
timer_b_tick <= '1';
else
timer_b_count <= timer_b_count - 1;
end if;
end if;
end if;
if write_t2c_h = '1' then
timer_b_count <= data_in & timer_b_latch(7 downto 0);
timer_b_trig <= '1';
end if;
if reset='1' then
timer_b_count <= (others => '0');
timer_b_trig <= '0';
end if;
end if;
end process;
end block tmr_b;
ser: block
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal cb1_c, cb2_c : std_logic;
signal mpu_write : std_logic;
signal mpu_read : std_logic;
signal bit_cnt : integer range 0 to 7;
signal shift_active : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
case shift_clk_sel is
when "10" =>
if shift_active='0' then
shift_clock <= '1';
elsif clock_en='1' then
shift_clock <= not shift_clock;
end if;
when "00"|"01" =>
if shift_active='0' then
shift_clock <= '1';
elsif timer_b_tick='1' then
shift_clock <= not shift_clock;
end if;
when others => -- "11"
shift_clock <= To_X01(cb1_i);
end case;
shift_clock_d <= shift_clock;
end if;
end process;
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
cb1_t <= '0' when shift_clk_sel="11" else serport_en;
cb1_o <= shift_clock;
mpu_write <= wen when addr=X"A" else '0';
mpu_read <= ren when addr=X"A" else '0';
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
process(clock)
begin
if rising_edge(clock) then
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
if shift_clk_sel = "00" then
bit_cnt <= 7;
if shift_dir='0' then -- disabled mode
shift_active <= '0';
end if;
end if;
if mpu_read='1' or mpu_write='1' then
bit_cnt <= 7;
shift_active <= '1';
if mpu_write='1' then
shift_reg <= data_in;
end if;
end if;
serial_event <= '0';
if shift_active='1' then
if shift_tick_f='1' then
ser_cb2_o <= shift_reg(7);
end if;
if shift_tick_r='1' then
if shift_dir='1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
else
shift_reg <= shift_reg(6 downto 0) & cb2_c;
end if;
if bit_cnt=0 then
serial_event <= '1';
shift_active <= '0';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
if reset='1' then
shift_reg <= (others => '1');
shift_active <= '0';
bit_cnt <= 0;
ser_cb2_o <= '1';
end if;
end if;
end process;
end block ser;
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/sync_fifo/vhdl_source/sync_fifo.vhd
|
4
|
5506
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sync_fifo is
generic (
g_depth : integer := 512; -- Actual depth.
g_data_width : integer := 32;
g_threshold : integer := 13;
g_storage : string := "auto"; -- can also be "blockram" or "distributed"
g_fall_through : boolean := false);
port (
clock : in std_logic;
reset : in std_logic;
rd_en : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(g_data_width-1 downto 0);
dout : out std_logic_vector(g_data_width-1 downto 0);
flush : in std_logic;
full : out std_logic;
almost_full : out std_logic;
empty : out std_logic;
count : out integer range 0 to g_depth
);
end sync_fifo;
architecture rtl of sync_fifo is
subtype t_data_element is std_logic_vector(g_data_width-1 downto 0);
type t_data_array is array (0 to g_depth-1) of t_data_element;
signal data_array : t_data_array;
attribute ram_style : string;
attribute ram_style of data_array : signal is g_storage;
signal rd_data : std_logic_vector(g_data_width-1 downto 0);
signal din_reg : std_logic_vector(g_data_width-1 downto 0);
signal rd_inhibit : std_logic;
signal rd_inhibit_d : std_logic;
signal rd_en_flt : std_logic;
signal rd_enable : std_logic;
signal rd_pnt : integer range 0 to g_depth-1;
signal rd_pnt_next : integer range 0 to g_depth-1;
signal rd_index : integer range 0 to g_depth-1;
signal wr_en_flt : std_logic;
signal wr_pnt : integer range 0 to g_depth-1;
signal num_el : integer range 0 to g_depth;
begin
-- Check generic values (also for synthesis)
assert(g_threshold <= g_depth) report "Invalid parameter 'g_threshold'" severity failure;
-- Filter fifo read/write enables for full/empty conditions
rd_en_flt <= '1' when (num_el /= 0) and (rd_en='1') else '0';
wr_en_flt <= '1' when (num_el /= g_depth) and (wr_en='1') else '0';
-- Read enable depends on 'fall through' mode. In case fall through: prevent
-- read & write at same address (when fifo is empty)
rd_enable <= rd_en_flt when not(g_fall_through) else
'0' when rd_inhibit = '1' else
'1';
rd_inhibit <= '1' when rd_index = wr_pnt and wr_en_flt = '1' and g_fall_through else '0';
rd_index <= rd_pnt_next when g_fall_through and rd_en_flt = '1' and num_el /= 0 else rd_pnt;
-- FIFO output data. Combinatoric switch to fix simultaneous read/write issues.
dout <= din_reg when rd_inhibit_d = '1' else rd_data;
p_dpram: process(clock)
begin
if rising_edge(clock) then
if (wr_en_flt = '1') then
data_array(wr_pnt) <= din;
end if;
if (rd_enable = '1') then
rd_data <= data_array(rd_index);
end if;
end if;
end process;
rd_pnt_next <= 0 when (rd_pnt=g_depth-1) else rd_pnt + 1;
process(clock)
variable v_new_cnt : integer range 0 to g_depth;
begin
if (clock'event and clock='1') then
rd_inhibit_d <= rd_inhibit;
-- Modify read/write pointers
if (rd_en_flt='1') then
rd_pnt <= rd_pnt_next;
end if;
if (wr_en_flt='1') then
-- Registered din is needed for BlockRAM based 'fall through' FIFO
din_reg <= din;
if (wr_pnt=g_depth-1) then
wr_pnt <= 0;
else
wr_pnt <= wr_pnt + 1;
end if;
end if;
-- Update number of elements in fifo for next clock cycle
if (rd_en_flt = '1') and (wr_en_flt = '0') then
v_new_cnt := num_el - 1;
elsif (rd_en_flt = '0') and (wr_en_flt = '1') then
v_new_cnt := num_el + 1;
elsif (flush='1') then
v_new_cnt := 0;
else
v_new_cnt := num_el;
end if;
num_el <= v_new_cnt;
-- update (almost)full and empty indications
almost_full <= '0';
if (v_new_cnt >= g_threshold) then
almost_full <= '1';
end if;
empty <= '0';
if (v_new_cnt = 0) then
empty <= '1';
end if;
full <= '0';
if (v_new_cnt = g_depth) then
full <= '1';
end if;
if (flush='1') or (reset='1') then
rd_pnt <= 0;
wr_pnt <= 0;
num_el <= 0;
rd_inhibit_d <= '0';
if (reset='1') then
full <= '0';
empty <= '1';
almost_full <= '0';
end if;
end if;
end if;
end process;
count <= num_el;
end rtl;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4.vhd
|
5
|
9586
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (no burst)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4 is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v4;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v4 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"0220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(req.tag'range);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack : std_logic;
signal rack : std_logic;
signal rack_tag : std_logic_vector(req.tag'range);
signal dack_tag : std_logic_vector(req.tag'range);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
attribute iob of SDRAM_CKE : signal is "false";
begin
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_i;
resp.rack <= rack;
resp.rack_tag <= rack_tag;
resp.dack_tag <= dack_tag;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
sram_d_t <= '0'; --not req.read_writen;
sram_d_o <= req.data;
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
dout_sel <= '0';
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
SDRAM_CSn <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= not rwn_i; -- enable for writes
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 2;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
if rwn_i = '1' then -- read
dack <= '1';
dack_tag <= tag;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sram_d_t <= '0';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/spi/vhdl_source/spi_peripheral.vhd
|
5
|
3591
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_peripheral is
generic (
g_fixed_rate : boolean := false;
g_init_rate : integer := 500;
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi_peripheral;
architecture gideon of spi_peripheral is
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy : std_logic;
signal rate : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(g_init_rate, 9));
signal rdata : std_logic_vector(7 downto 0);
signal wdata : std_logic_vector(7 downto 0);
signal clear_crc : std_logic;
signal crc_out : std_logic_vector(7 downto 0);
begin
spi1: entity work.spi
generic map (
g_crc => g_crc )
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy,
rate => rate,
cpol => '0',
cpha => '0',
wdata => wdata,
rdata => rdata,
crc_out => crc_out,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO );
process(clock)
begin
if rising_edge(clock) then
do_send <= '0';
clear_crc <= '0';
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" =>
do_send <= '1';
wdata <= bus_wdata;
when "01" =>
if not g_fixed_rate then
rate(7 downto 0) <= bus_wdata;
rate(8) <= bus_wdata(7);
end if;
when "10" =>
force_ss <= bus_wdata(0);
level_ss <= bus_wdata(1);
when "11" =>
clear_crc <= '1';
when others =>
null;
end case;
end if;
if reset='1' then
rate <= std_logic_vector(to_unsigned(g_init_rate, 9));
force_ss <= '0';
level_ss <= '1';
wdata <= (others => '0');
end if;
end if;
end process;
with bus_addr select bus_rdata <=
rdata when "00",
rate(7 downto 0) when "01",
busy & "00000" & level_ss & force_ss when "10",
crc_out when "11",
X"FF" when others;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/zpu/vhdl_source/zpu_8bit_loadb.vhd
|
5
|
33125
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit_loadb(Behave) (Entity and architecture) ----
---- File name: zpu_8bit_loadb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
--use work.tl_string_util_pkg.all;
entity zpu_8bit_loadb is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_size_o : out std_logic_vector(1 downto 0); -- indicates size of transfer 00=byte, 11=dword
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in std_logic_vector(c_opcode_width-1 downto 0);
c_data_o : out std_logic_vector(c_opcode_width-1 downto 0) );
end entity zpu_8bit_loadb;
architecture Behave of zpu_8bit_loadb is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or, st_compare, st_loadb2,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_pop_int, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb, dec_neqbranch,
dec_compare);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
-- helper signals for compare instructions
signal compare_dec : std_logic_vector(2 downto 0);
signal compare_oper : std_logic_vector(2 downto 0);
signal compare_bool : boolean;
signal compare_res : unsigned(31 downto 0);
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= unsigned(c_data_i);
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
c_inst_o <= not c_mux_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
compare_dec <= "000";
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
case opcode(5 downto 0) is
when OPCODE_LOADB =>
d_opcode <= dec_loadb;
when OPCODE_STOREB =>
d_opcode <= dec_storeb;
when OPCODE_NEQBRANCH =>
d_opcode <= dec_neqbranch;
when OPCODE_EQ =>
d_opcode <= dec_compare;
compare_dec <= "001";
when OPCODE_LESSTHAN => -- 00
d_opcode <= dec_compare;
compare_dec <= "100";
when OPCODE_LESSTHANOREQUAL => -- 01
d_opcode <= dec_compare;
compare_dec <= "101";
when OPCODE_ULESSTHAN => -- 10
d_opcode <= dec_compare;
compare_dec <= "110";
when OPCODE_ULESSTHANOREQUAL => -- 11
d_opcode <= dec_compare;
compare_dec <= "111";
when others =>
d_opcode <= dec_emulate;
end case;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when OPCODE_POPINT =>
d_opcode <= dec_pop_int;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
procedure emulate is
begin
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
end procedure;
procedure execute_def is
begin
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
end procedure;
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
compare_oper <= compare_dec;
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
execute_def;
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
emulate;
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_pop_int =>
-- Pop(PC)
in_irq_r <= '0'; -- no longer in an interrupt
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_compare =>
-- Push(Compare(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_compare;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_loadb =>
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
state <= st_loadb2;
else
a_r <= (others => '0');
c_req_r <= '1';
c_mux_r <= '1';
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
c_size_o <= "00";
state <= st_read_mem;
end if;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);-- xor "11";
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
-- report "Load: " & hstr(a_i);
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
c_size_o <= "11";
state <= st_read_mem;
end if;
when dec_store =>
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
-- a=Pop(), b=Pop(), [a]=b
state <= st_write_mem;
byte_req_cnt <= "11"; -- 4 bytes
c_size_o <= "11";
end if;
when dec_storeb =>
if a_i(31) = '1' then
emulate;
else
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
c_size_o <= "00";
byte_req_cnt <= "00"; -- 1 byte
state <= st_write_mem;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when dec_neqbranch =>
-- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
-- Branches are almost always taken as they form loops
sp_r <= sp_r + 2;
-- Need to fetch stack again.
state <= st_resync;
if b_i/=0 then
pc_r <= pc_r + a_i(pc_r'range);
end if;
when others => -- includes 'nop'
null;
end case;
when st_loadb2 =>
-- select the correct stack byte
if a_en_r='0' then -- wait one cycle until BRAM data is available
a_r <= (others => '0');
case addr_r(1 downto 0) is
when "11" => a_r( 7 downto 0) <= a_i( 7 downto 0);
when "10" => a_r( 7 downto 0) <= a_i(15 downto 8);
when "01" => a_r( 7 downto 0) <= a_i(23 downto 16);
when "00" => a_r( 7 downto 0) <= a_i(31 downto 24);
when others => null;
end case;
-- report "LoadB: " & hstr(a_i) & ", addr: " & hstr(addr_r(1 downto 0));
-- a_r <= a_i; -- dummy
a_addr_r <= sp_r;
a_en_r <= '1';
a_we_r <= '1';
state <= st_fetch;
end if;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
-- when st_storeb =>
-- sp_r <= sp_r+1; -- for a store we need to pop 2!
-- a_we_r <= '1';
-- a_en_r <= '1';
-- a_addr_r <= a_i(g_stack_size-1 downto 2);
-- a_r <= b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0);
-- state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
-- report "Returning " & hstr(a_r(31 downto 8)) & hstr(c_data_i) &
-- " while reading from " & hstr(addr_r);
a_r(7 downto 0) <= unsigned(c_data_i);
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= unsigned(c_data_i);
when "10" =>
a_r(23 downto 16) <= unsigned(c_data_i);
when others => -- 11
a_r(31 downto 24) <= unsigned(c_data_i);
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_compare =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= compare_res;
state <= st_fetch;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
c_size_o <= "11";
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= std_logic_vector(b_i(7 downto 0));
when "01" =>
c_data_o <= std_logic_vector(b_i(15 downto 8));
when "10" =>
c_data_o <= std_logic_vector(b_i(23 downto 16));
when others => -- 11
c_data_o <= std_logic_vector(b_i(31 downto 24));
end case;
end process;
i_compare: entity work.zpu_compare
port map (
a => a_i,
b => b_i,
oper => compare_oper,
y => compare_bool );
compare_res <= X"00000001" when compare_bool else X"00000000";
end architecture Behave; -- Entity: zpu_8bit_loadb
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/6502/vhdl_source/shifter.vhd
|
3
|
1946
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1)
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
data_out : out std_logic_vector(7 downto 0) := X"00");
end shifter;
architecture gideon of shifter is
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal zero : std_logic := '0';
signal oper4 : std_logic_vector(3 downto 0) := X"0";
begin
-- ASL $nn ROL $nn LSR $nn ROR $nn STX $nn LDX $nn DEC $nn INC $nn
with operation select data_out_i <=
data_in(6 downto 0) & '0' when "000",
data_in(6 downto 0) & c_in when "001",
'0' & data_in(7 downto 1) when "010",
c_in & data_in(7 downto 1) when "011",
data_in - 1 when "110",
data_in + 1 when "111",
data_in when others;
zero <= '1' when data_out_i = X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
data_in(7) when "1000" | "1001",
data_in(0) when "1010" | "1011",
c_in when others;
with oper4 select z_out <=
zero when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
z_in when others;
with oper4 select n_out <=
data_out_i(7) when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
n_in when others;
data_out <= data_out_i when enable='1' else data_in;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v7_tb.vhd
|
5
|
10543
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v7_tb is
end ext_mem_ctrl_v7_tb;
architecture tb of ext_mem_ctrl_v7_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 12 ns;
clk_2x <= not clk_2x after 6 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
p_test: process
procedure queue_req(rw : std_logic; bank : integer; row : integer; col : integer) is
begin
req.request <= '1';
req.read_writen <= rw;
req.address <= to_unsigned(bank*8192 + col*8 + row*32768, req.address'length);
wait for 2 ns;
while resp.ready='0' loop
wait until clock='1';
end loop;
wait until clock='1';
req.request <= '0';
end procedure;
begin
req.read_writen <= '1'; -- read
req.request <= '0';
req.address <= unsigned(to_signed(-32, req.address'length));
req.data_pop <= '0';
wait until reset='0';
wait until clock='1';
-- simple write / readback test
queue_req('0', 0, 0, 0);
queue_req('1', 0, 0, 0);
while true loop
-- read-read, other row, other bank
queue_req('1', 0, 16, 127);
queue_req('1', 1, 17, 0);
-- read-read, other row, same bank
queue_req('1', 1, 18, 1);
-- read-read, same row, other bank
queue_req('1', 2, 18, 2);
-- read-read, same row, same bank
queue_req('1', 2, 18, 3);
-- read-write, other row, other bank
queue_req('0', 0, 16, 4);
-- read-write, other row, same bank
queue_req('1', 0, 16, 127);
queue_req('0', 0, 17, 5);
-- read-write, same row, other bank
queue_req('1', 0, 18, 127);
queue_req('0', 1, 18, 6);
-- read-write, same row, same bank
queue_req('1', 2, 19, 127);
queue_req('0', 2, 19, 7);
-- write-read, other row, other bank
queue_req('1', 3, 20, 8);
-- write-read, other row, same bank
queue_req('0', 0, 16, 127);
queue_req('1', 0, 17, 9);
-- write-read, same row, other bank
queue_req('0', 1, 18, 127);
queue_req('1', 2, 18, 10);
-- write-read, same row, same bank
queue_req('0', 3, 19, 127);
queue_req('1', 3, 19, 11);
-- write-write, other row, other bank
queue_req('0', 0, 20, 127);
queue_req('0', 1, 21, 12);
-- write-write, other row, same bank
queue_req('0', 1, 22, 13);
-- write-write, same row, other bank
queue_req('0', 2, 22, 14);
-- write-write, same row, same bank
queue_req('0', 2, 22, 15);
-- read write toggle performance tests..
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 1, 0, i);
end loop;
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 0, 0, i);
end loop;
for i in 1 to 10 loop
queue_req('1', 0, 0, i);
queue_req('0', 0, 1, i);
end loop;
for i in 1 to 1000 loop
queue_req('1', 0, 0, i);
end loop;
end loop;
wait;
end process;
p_write: process(clock)
variable v_data : unsigned(31 downto 0) := X"DEAD4001";
begin
if rising_edge(clock) then
if resp.wdata_full='0' and reset='0' then
req.data_push <= '1';
req.data <= std_logic_vector(v_data);
req.byte_en <= "0111";
v_data := v_data + 1;
else
req.data_push <= '0';
end if;
end if;
end process;
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => SDRAM_BA(0),
BA1 => SDRAM_BA(1),
DQMH => dummy_dqm(1),
DQML => SDRAM_DQM,
DQ0 => SDRAM_DQ(0),
DQ1 => SDRAM_DQ(1),
DQ2 => SDRAM_DQ(2),
DQ3 => SDRAM_DQ(3),
DQ4 => SDRAM_DQ(4),
DQ5 => SDRAM_DQ(5),
DQ6 => SDRAM_DQ(6),
DQ7 => SDRAM_DQ(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A0 => SDRAM_A(0),
A1 => SDRAM_A(1),
A2 => SDRAM_A(2),
A3 => SDRAM_A(3),
A4 => SDRAM_A(4),
A5 => SDRAM_A(5),
A6 => SDRAM_A(6),
A7 => SDRAM_A(7),
A8 => SDRAM_A(8),
A9 => SDRAM_A(9),
A10 => SDRAM_A(10),
A11 => SDRAM_A(11),
A12 => SDRAM_A(12),
WENeg => SDRAM_WEn,
RASNeg => SDRAM_RASn,
CSNeg => SDRAM_CSn,
CASNeg => SDRAM_CASn );
end;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/usb2/vhdl_source/usb_memory_ctrl.vhd
|
3
|
7350
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_bus_pkg.all;
-- This module performs the memory operations that are instructed
-- by the nano_cpu. This controller copies data to or from a
-- designated BRAM, and notifies the nano_cpu that the transfer
-- is complete.
entity usb_memory_ctrl is
generic (
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
clock : in std_logic;
reset : in std_logic;
-- cmd interface
cmd_addr : in std_logic_vector(3 downto 0);
cmd_valid : in std_logic;
cmd_write : in std_logic;
cmd_wdata : in std_logic_vector(15 downto 0);
cmd_ack : out std_logic;
cmd_ready : out std_logic;
-- BRAM interface
ram_addr : out std_logic_vector(10 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
ram_wdata : out std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(7 downto 0);
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end entity;
architecture gideon of usb_memory_ctrl is
type t_state is (idle, reading, writing, init);
signal state : t_state;
signal mem_addr_r : unsigned(25 downto 0) := (others => '0');
signal mem_addr_i : unsigned(25 downto 0) := (others => '0');
signal ram_addr_i : unsigned(10 downto 0) := (others => '0');
signal remaining : unsigned(10 downto 0) := (others => '0');
signal mreq : std_logic := '0';
signal size : unsigned(1 downto 0) := (others => '0');
signal rwn : std_logic := '1';
signal addr_do_load : std_logic;
signal addr_do_inc : std_logic;
signal addr_inc_by_4 : std_logic;
signal rem_do_load : std_logic;
signal rem_do_dec : std_logic;
signal remain_is_0 : std_logic;
signal remain_less4 : std_logic;
begin
mem_req.tag <= g_tag;
mem_req.request <= mreq;
mem_req.address <= mem_addr_i;
mem_req.read_writen <= rwn;
mem_req.size <= size;
mem_req.data <= ram_rdata;
-- pop from fifo when we process the access
cmd_ack <= '1' when (state = idle) and (cmd_valid='1') else '0';
process(state, mreq, mem_resp, ram_addr_i)
begin
ram_addr <= std_logic_vector(ram_addr_i);
ram_wdata <= mem_resp.data;
ram_we <= '0';
ram_en <= '0';
-- for writing to memory, we enable the BRAM only when we are going to set
-- the request, such that the data and the request comes at the same time
case state is
when writing =>
if (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0') then
ram_en <= '1';
end if;
when others =>
null;
end case;
-- for reading from memory, it doesn't matter in which state we are:
if mem_resp.dack_tag=g_tag then
ram_we <= '1';
ram_en <= '1';
end if;
end process;
process(clock)
variable temp : unsigned(2 downto 0);
begin
if rising_edge(clock) then
rem_do_dec <= '0';
case state is
when idle =>
rwn <= '1';
if cmd_valid='1' then
if cmd_write='1' then
cmd_ready <= '0';
case cmd_addr is
when X"0" =>
mem_addr_r(15 downto 0) <= unsigned(cmd_wdata);
when X"1" =>
mem_addr_r(25 downto 16) <= unsigned(cmd_wdata(9 downto 0));
when X"2" =>
rwn <= '0';
state <= init;
when X"3" =>
state <= init;
when others =>
null;
end case;
end if;
end if;
when init =>
ram_addr_i <= (others => '0');
if rwn='1' then
state <= reading;
else
state <= writing;
end if;
when reading =>
rwn <= '1';
if (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0') then
if remain_less4='1' then
if remain_is_0='1' then
state <= idle;
cmd_ready <= '1';
mreq <= '0';
else
rem_do_dec <= '1';
mreq <= '1';
size <= "00";
end if;
else
rem_do_dec <= '1';
size <= "11";
mreq <= '1';
end if;
end if;
when writing =>
rwn <= '0';
size <= "00";
if (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0') then
ram_addr_i <= ram_addr_i + 1;
if remain_is_0 = '1' then
mreq <= '0';
state <= idle;
cmd_ready <= '1';
else
mreq <= '1';
rem_do_dec <= '1';
end if;
end if;
when others =>
null;
end case;
if mem_resp.dack_tag=g_tag then
ram_addr_i <= ram_addr_i + 1;
end if;
if reset='1' then
state <= idle;
mreq <= '0';
cmd_ready <= '0';
end if;
end if;
end process;
addr_do_load <= '1' when (state = init) else '0';
addr_do_inc <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) else '0';
addr_inc_by_4 <= '1' when (size = "11") else '0';
i_addr: entity work.mem_addr_counter
port map (
clock => clock,
load_value => mem_addr_r,
do_load => addr_do_load,
do_inc => addr_do_inc,
inc_by_4 => addr_inc_by_4,
address => mem_addr_i );
rem_do_load <= '1' when cmd_valid='1' and cmd_write='1' and cmd_addr(3 downto 1)="001" else '0';
-- rem_do_dec <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag = g_tag) or (mreq = '0' and state/=idle and state/=init) else '0';
i_rem: entity work.mem_remain_counter
port map (
clock => clock,
load_value => unsigned(cmd_wdata(10 downto 0)),
do_load => rem_do_load,
do_dec => rem_do_dec,
dec_by_4 => addr_inc_by_4,
remain => remaining,
remain_is_0 => remain_is_0,
remain_less4=> remain_less4 );
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb2/vhdl_source/usb_host_nano.vhd
|
1
|
9473
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_host_controller
-- Date:2015-02-12
-- Author: Gideon
-- Description: Top level of second generation USB controller with memory
-- interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_nano is
generic (
g_tag : std_logic_vector(7 downto 0) := X"05";
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
ulpi_nxt : in std_logic;
ulpi_dir : in std_logic;
ulpi_stp : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
--
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req_32;
sys_mem_resp: in t_mem_resp_32;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp;
sys_irq : out std_logic );
end entity;
architecture arch of usb_host_nano is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal nano_rdata_regs : std_logic_vector(15 downto 0);
signal nano_rdata_cmd : std_logic_vector(15 downto 0);
signal nano_stall : std_logic := '0';
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_address : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal reg_rdata : std_logic_vector(7 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal status : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10";
signal do_chirp : std_logic;
signal chirp_data : std_logic;
signal sof_enable : std_logic;
signal mem_ctrl_ready : std_logic;
signal buf_address : unsigned(10 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_addr : std_logic_vector(10 downto 2);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic_vector(3 downto 0);
signal sys_buf_wdata : std_logic_vector(31 downto 0);
signal sys_buf_rdata : std_logic_vector(31 downto 0);
signal sys_buf_wdata_le: std_logic_vector(31 downto 0);
signal sys_buf_rdata_le: std_logic_vector(31 downto 0);
signal usb_tx_req : t_usb_tx_req;
signal usb_tx_resp : t_usb_tx_resp;
signal usb_rx : t_usb_rx;
signal usb_cmd_req : t_usb_cmd_req;
signal usb_cmd_resp : t_usb_cmd_resp;
signal frame_count : unsigned(15 downto 0);
signal sof_tick : std_logic;
signal interrupt : std_logic;
begin
i_intf: entity work.usb_host_interface
generic map (
g_simulation => g_simulation )
port map (
clock => clock,
reset => reset,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp,
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
reg_ack => reg_ack,
do_chirp => do_chirp,
chirp_data => chirp_data,
status => status,
speed => speed,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_seq: entity work.host_sequencer
port map (
clock => clock,
reset => reset,
buf_address => buf_address,
buf_en => buf_en,
buf_we => buf_we,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
frame_count => frame_count,
usb_cmd_req => usb_cmd_req,
usb_cmd_resp => usb_cmd_resp,
usb_rx => usb_rx,
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
i_buf_ram: RAMB16BWE_S36_S9
port map (
CLKB => clock,
SSRB => reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => std_logic_vector(buf_address),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata_le,
DIPA => "0000",
DOA => sys_buf_rdata_le );
sys_buf_wdata_le <= byte_swap(sys_buf_wdata);
sys_buf_rdata <= byte_swap(sys_buf_rdata_le);
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => clock,
ulpi_reset => reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_sync: entity work.level_synchronizer
port map (
clock => clock,
reset => reset,
input => cmd_ready,
input_c => mem_ctrl_ready );
i_nano_io: entity work.nano_minimal_io
generic map (
g_support_suspend => false )
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata_regs,
stall => nano_stall,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_rdata => reg_rdata,
status => status,
mem_ctrl_ready => mem_ctrl_ready,
frame_count => frame_count,
do_chirp => do_chirp,
chirp_data => chirp_data,
connected => open,
operational => open,
suspended => open,
sof_enable => sof_enable,
sof_tick => sof_tick,
speed => speed,
interrupt_out => interrupt );
i_sync2: entity work.pulse_synchronizer
port map (
clock_in => clock,
pulse_in => interrupt,
clock_out => sys_clock,
pulse_out => sys_irq );
i_cmd_io: entity work.usb_cmd_nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata_cmd,
cmd_req => usb_cmd_req,
cmd_resp => usb_cmd_resp );
i_nano: entity work.nano
port map (
clock => clock,
reset => reset,
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => nano_stall,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
nano_rdata <= nano_rdata_regs or nano_rdata_cmd;
end arch;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/sid6581/vhdl_source/Q_table.vhd
|
5
|
1580
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q_table is
port (
Q_reg : in unsigned(3 downto 0);
filter_q : out signed(17 downto 0) );
end Q_table;
architecture Gideon of Q_table is
type t_18_bit_array is array(natural range <>) of signed(17 downto 0);
function create_factors(max_Q: real) return t_18_bit_array is
variable critical : real := 0.70710678; -- no resonance at 0.5*sqrt(2)
variable q_step : real;
variable q : real;
variable scaled : real;
variable ret : t_18_bit_array(0 to 15);
begin
q_step := (max_Q - critical) / 15.0; -- linear
for i in 0 to 15 loop
q := critical + (real(i) * q_step);
scaled := 65536.0 / q;
ret(i) := to_signed(integer(scaled), 18);
end loop;
return ret;
end function;
constant c_table : t_18_bit_array(0 to 15) := create_factors(1.8);
begin
filter_q <= c_table(to_integer(Q_reg));
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/6502/vhdl_source/alu.vhd
|
2
|
4855
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
generic (
support_bcd : boolean := true );
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic;
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
data_a : in std_logic_vector(7 downto 0);
data_b : in std_logic_vector(7 downto 0);
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
data_out : out std_logic_vector(7 downto 0));
end alu;
architecture gideon of alu is
signal data_out_i : std_logic_vector(7 downto 0) := X"FF";
signal zero : std_logic;
signal sum_c : std_logic;
signal sum_n : std_logic;
signal sum_z : std_logic;
signal sum_v : std_logic;
signal sum_result : std_logic_vector(7 downto 0) := X"FF";
signal oper4 : std_logic_vector(3 downto 0);
begin
-- ORA $nn AND $nn EOR $nn ADC $nn STA $nn LDA $nn CMP $nn SBC $nn
with oper4 select data_out_i <=
data_a or data_b when "1000",
data_a and data_b when "1001",
data_a xor data_b when "1010",
sum_result when "1011" | "1110" | "1111",
data_b when others;
zero <= '1' when data_out_i = X"00" else '0';
sum: process(data_a, data_b, c_in, operation, d_in)
variable b : std_logic_vector(7 downto 0);
variable sum_l : std_logic_vector(4 downto 0);
variable sum_h : std_logic_vector(4 downto 0);
begin
-- for subtraction invert second operand
if operation(2)='1' then -- invert b
b := not data_b;
else
b := data_b;
end if;
-- sum_l(4) = carry of lower end, carry in is masked to '1' for CMP
sum_l := ('0' & data_a(3 downto 0)) + ('0' & b(3 downto 0)) + (c_in or not operation(0));
sum_h := ('0' & data_a(7 downto 4)) + ('0' & b(7 downto 4)) + sum_l(4);
if sum_l(3 downto 0)="0000" and sum_h(3 downto 0)="0000" then
sum_z <= '1';
else
sum_z <= '0';
end if;
sum_n <= sum_h(3);
sum_c <= sum_h(4);
sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
-- fix up in decimal mode (not for CMP!)
if d_in='1' and support_bcd then
if operation(2)='0' then -- ADC
if sum_l(4) = '1' or sum_l(3 downto 2)="11" or sum_l(3 downto 1)="101" then -- >9 (10-11, 12-15)
sum_l := sum_l + (sum_l(4) & X"6"); -- adding sum_l(4) another time, prevents
-- double fixup of high nibble.
end if;
-- negative when sum_h + sum_l(4) = 8
sum_h := sum_h + sum_l(4);
sum_n <= sum_h(3);
if sum_h(4) = '1' or sum_h(3 downto 2)="11" or sum_h(3 downto 1)="101" or
(sum_l(4)='1' and sum_h(3 downto 0)="1001") then -- >9 (10-11, 12-15)
sum_h := sum_h + 6;
end if;
-- carry and overflow are output after fix
sum_c <= sum_h(4);
-- sum_v <= (sum_h(3) xor data_a(7)) and (sum_h(3) xor data_b(7) xor operation(2));
elsif operation(0)='1' then -- SBC
-- flags are not adjusted in subtract mode
if sum_l(4) = '0' then
sum_l := sum_l - 6;
end if;
if sum_h(4) = '0' then
sum_h := sum_h - 6;
end if;
end if;
end if;
sum_result <= sum_h(3 downto 0) & sum_l(3 downto 0);
end process;
oper4 <= enable & operation;
with oper4 select c_out <=
sum_c when "1011" | "1111" | "1110",
c_in when others;
with oper4 select z_out <=
sum_z when "1011" | "1111" | "1110",
zero when "1000" | "1001" | "1010" | "1101",
z_in when others;
with oper4 select n_out <=
sum_n when "1011" | "1111",
data_out_i(7) when "1000" | "1001" | "1010" | "1101" | "1110",
n_in when others;
with oper4 select v_out <=
sum_v when "1011" | "1111",
v_in when others;
data_out <= data_out_i;
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/zpu/vhdl_source/zpu_8bit.vhd
|
5
|
28407
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/fpga_top/video_fpga/vhdl_source/s3e_clockgen.vhd
|
5
|
4287
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3e_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_shifted : out std_logic;
pix_clock : out std_logic; -- * 7/25 (14 MHz)
pix_clock_en: out std_logic;
pix_reset : out std_logic );
end s3e_clockgen;
architecture Gideon of s3e_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sysrst_cnt : integer range 0 to 63;
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal pix_clock_pre : std_logic;
signal pix_clock_ii : std_logic;
signal pix_clock_i : std_logic;
signal pixrst_cnt : integer range 0 to 63;
signal pix_reset_i : std_logic := '1';
signal pix_reset_p : std_logic := '1';
signal pixdiv : integer range 0 to 7;
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_270_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
CLKFX_MULTIPLY => 5,
CLKFX_DIVIDE => 2,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK270 => clk_270_pre,
CLKFX => pix_clock_pre,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_pix: BUFG port map (I => pix_clock_pre, O => pix_clock_ii);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_shft: BUFG port map (I => clk_270_pre, O => sys_shifted);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
pix_clock <= pix_clock_ii;
pix_clock_i <= pix_clock_ii;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
process(pix_clock_i, dcm1_locked)
begin
if rising_edge(pix_clock_i) then
if pixdiv = 0 then
pixdiv <= 4;
pix_clock_en <= '1';
else
pixdiv <= pixdiv - 1;
pix_clock_en <= '0';
end if;
if pixrst_cnt = 63 then
pix_reset_i <= '0';
else
pixrst_cnt <= pixrst_cnt + 1;
end if;
pix_reset_p <= pix_reset_i;
end if;
if dcm1_locked='0' then
pixrst_cnt <= 0;
pix_reset_i <= '1';
pix_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
pix_reset <= pix_reset_p;
end Gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/usb/vhdl_sim/data_crc_tb.vhd
|
2
|
1786
|
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity data_crc_tb is
end data_crc_tb;
architecture tb of data_crc_tb is
signal clock : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0);
signal crc : std_logic_vector(15 downto 0);
signal valid : std_logic := '0';
signal sync : std_logic := '0';
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant test_array : t_byte_array := (
X"80", X"06", X"00", X"01", X"00", X"00", X"40", X"00" );
begin
i_mut: entity work.usb1_data_crc
port map (
clock => clock,
sync => sync,
valid => valid,
data_in => data_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
wait until clock='1';
wait until clock='1';
sync <= '1';
wait until clock='1';
sync <= '0';
for i in test_array'range loop
data_in <= test_array(i);
valid <= '1';
wait until clock = '1';
end loop;
valid <= '0';
wait;
end process;
end tb;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/ip/busses/vhdl_source/io_dummy.vhd
|
5
|
468
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_dummy is
port (
clock : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end entity;
architecture dummy of io_dummy is
begin
io_resp.data <= X"00";
process(clock)
begin
if rising_edge(clock) then
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
end dummy;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/zpu/vhdl_source/zpu_small.vhdl
|
5
|
23125
|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/io/uart_lite/vhdl_source/tx.vhd
|
4
|
2804
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Transmitter: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
-- Description: This module sends a character over a serial line
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
cts : in std_logic := '1';
txd : out std_logic;
done : out std_logic );
end tx;
architecture gideon of tx is
signal bitcnt : integer range 0 to 9;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, Waiting, Transmitting);
signal state : state_t;
signal cts_c : std_logic := '1';
begin
process(clk, reset)
begin
if rising_edge(clk) then
cts_c <= cts;
case state is
when Idle =>
if DoTx='1' then
if cts_c='1' then
state <= Transmitting;
else
state <= Waiting;
end if;
bitcnt <= 9;
bitvec <= not(txchar) & '1';
timer <= clks_per_bit - 1;
end if;
when Waiting =>
if cts_c='1' then
state <= Transmitting;
end if;
when Transmitting =>
if timer=0 then
timer <= clks_per_bit - 1;
if bitcnt = 0 then
state <= Idle;
else
bitcnt <= bitcnt - 1;
bitvec <= '0' & bitvec(8 downto 1);
end if;
else
timer <= timer - 1;
end if;
end case;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
done <= '1' when state=Idle else '0';
txd <= not(bitvec(0));
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
fpga/1541/vhdl_source/c1541_drive.vhd
|
4
|
10338
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity c1541_drive is
generic (
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_floppy_tag : std_logic_vector(7 downto 0) := X"02";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_div : integer := 2222; -- 22500 Hz (from 50 MHz)
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
-- master port on memory bus
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
iec_reset_n : in std_logic;
c64_reset_n : in std_logic;
-- LED
act_led_n : out std_logic;
motor_led_n : out std_logic;
dirty_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) );
end c1541_drive;
architecture structural of c1541_drive is
signal cpu_clock_en : std_logic;
signal drv_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal param_write : std_logic;
signal param_ram_en : std_logic;
signal param_addr : std_logic_vector(10 downto 0);
signal param_wdata : std_logic_vector(7 downto 0);
signal param_rdata : std_logic_vector(7 downto 0);
signal do_track_out : std_logic;
signal do_track_in : std_logic;
signal do_head_bang : std_logic;
signal en_hum : std_logic;
signal en_slip : std_logic;
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal bank_is_ram : std_logic_vector(7 downto 0);
signal power : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal track : std_logic_vector(6 downto 0);
signal track_is_0 : std_logic;
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal drv_reset : std_logic := '1';
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_flop : t_mem_req;
signal mem_resp_flop : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
drive_stop_i <= drive_stop and stop_on_freeze;
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
drive_stop => drive_stop_i,
drv_clock_en => drv_clock_en, -- 1/12.5 (4 MHz)
cpu_clock_en => cpu_clock_en ); -- 1/50 (1 MHz)
i_cpu: entity work.cpu_part_1541
generic map (
g_tag => g_cpu_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
clock_en => cpu_clock_en,
reset => drv_reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- trace data
cpu_pc => open, --cpu_pc_1541,
-- configuration
bank_is_ram => bank_is_ram,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_on => motor_on,
mode => mode,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
track_is_0 => track_is_0,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
act_led => act_led_n );
i_flop: entity work.floppy
generic map (
g_tag => g_floppy_tag )
port map (
sys_clock => clock,
drv_clock_en => drv_clock_en, -- resulting in 4 MHz
drv_reset => drv_reset,
-- signals from MOS 6522 VIA
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
track_is_0 => track_is_0,
---
cpu_write => param_write,
cpu_ram_en => param_ram_en,
cpu_addr => param_addr,
cpu_wdata => param_wdata,
cpu_rdata => param_rdata,
---
floppy_inserted => floppy_inserted,
do_track_out => do_track_out,
do_track_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
---
mem_req => mem_req_flop,
mem_resp => mem_resp_flop );
r_snd: if g_audio generate
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
rate_div => g_audio_div, -- 22050 Hz
sound_base => g_audio_base(27 downto 16),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms;
track_out_len => X"0880", -- ~100 ms;
head_bang_len => X"0880" ) -- ~100 ms;
port map (
clock => clock, -- 50 MHz
reset => drv_reset,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
generic map (
g_audio_base => g_audio_base,
g_ram_base => g_ram_base )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
param_write => param_write,
param_ram_en => param_ram_en,
param_addr => param_addr,
param_wdata => param_wdata,
param_rdata => param_rdata,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
write_prot_n => write_prot_n,
bank_is_ram => bank_is_ram,
dirty_led_n => dirty_led_n,
stop_on_freeze => stop_on_freeze,
track => track,
mode => mode,
motor_on => motor_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_flop,
reqs(1) => mem_req_cpu,
reqs(2) => mem_req_snd,
resps(0) => mem_resp_flop,
resps(1) => mem_resp_cpu,
resps(2) => mem_resp_snd,
req => mem_req,
resp => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
|
gpl-3.0
|
KB777/1541UltimateII
|
legacy/2.6k/fpga/io/uart_lite/vhdl_source/uart_peripheral.vhd
|
5
|
4651
|
library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral;
architecture gideon of uart_peripheral is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done)
begin
if not tx_fifo then
txfifo_put <= '0';
txchar <= bus_wdata;
if bus_select='1' and bus_write='1' and bus_addr="00" then
dotx <= '1';
else
dotx <= '0';
end if;
else -- there is a fifo
dotx <= txfifo_dav and done;
txchar <= txfifo_dout;
if bus_select='1' and bus_write='1' and bus_addr="00" then
txfifo_put <= '1';
else
txfifo_put <= '0';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" => -- dout
null; -- covered by combi statement
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select bus_rdata <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
|
gpl-3.0
|
KB777/1541UltimateII
|
target/simulation/packages/vhdl_bfm/wave_pkg.vhd
|
5
|
5471
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Wave package
-------------------------------------------------------------------------------
-- File : wave_pkg.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package provides ways to write (and maybe in future read)
-- .wav files.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.tl_file_io_pkg.all;
package wave_pkg is
type t_wave_channel is record
number_of_samples : integer;
memory : h_mem_object;
end record;
type t_wave_channel_array is array(natural range <>) of t_wave_channel;
procedure open_channel(chan : out t_wave_channel);
procedure push_sample(chan : inout t_wave_channel; sample : integer);
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array);
end package;
package body wave_pkg is
procedure open_channel(chan : out t_wave_channel) is
variable ch : t_wave_channel;
begin
register_mem_model("path", "channel", ch.memory);
ch.number_of_samples := 0;
chan := ch;
end procedure;
procedure push_sample(chan : inout t_wave_channel; sample : integer) is
variable s : integer;
begin
s := sample;
if s > 32767 then s := 32767; end if;
if s < -32768 then s := -32768; end if;
write_memory_int(chan.memory, chan.number_of_samples, s);
chan.number_of_samples := chan.number_of_samples + 1;
end procedure;
procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is
variable bytes : integer := (x'length + 7) / 8;
variable xa : std_logic_vector(7+bytes*8 downto 0);
begin
xa := (others => '0');
xa(x'length-1 downto 0) := x;
for i in 0 to bytes-1 loop
write_byte(f, xa(i*8+7 downto i*8), r);
end loop;
end procedure;
procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(31 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 32));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is
variable x_slv : std_logic_vector(15 downto 0);
begin
x_slv := std_logic_vector(to_signed(x, 16));
write_vector_le(x_slv, f, r);
end procedure;
procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
variable stat : file_open_status;
variable file_size : integer;
variable data_size : integer;
variable max_length : integer;
begin
-- open file
file_open(stat, myfile, name, write_mode);
assert (stat = open_ok)
report "Could not open file " & name & " for writing."
severity failure;
init_record(myrec);
max_length := 0;
for i in channels'range loop
if channels(i).number_of_samples > max_length then
max_length := channels(i).number_of_samples;
end if;
end loop;
data_size := (max_length * channels'length * 2);
file_size := 12 + 16 + 8 + data_size;
-- header
write_vector_le(X"46464952", myfile, myrec); -- "RIFF"
write_int_le (file_size-8, myfile, myrec);
write_vector_le(X"45564157", myfile, myrec); -- "WAVE"
-- chunk header
write_vector_le(X"20746D66", myfile, myrec); -- "fmt "
write_int_le (16, myfile, myrec);
write_short_le (1, myfile, myrec); -- compression code = uncompressed
write_short_le (channels'length, myfile, myrec);
write_int_le (rate, myfile, myrec); -- sample rate
write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps
write_short_le (channels'length * 2, myfile, myrec); -- alignment
write_short_le (16, myfile, myrec); -- bits per sample
write_vector_le(X"61746164", myfile, myrec); -- "data"
write_int_le (data_size, myfile, myrec);
-- now write out all data!
for i in 0 to max_length-1 loop
for j in channels'range loop
write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec);
end loop;
end loop;
purge(myfile, myrec);
file_close(myfile);
end procedure;
end;
|
gpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/r2t2/dac/dac.vhdl
|
1
|
4301
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;
LIBRARY unisim;
USE unisim.vcomponents.all;
ENTITY radio_dac_if IS
PORT(
DCLKIO : IN std_logic;
S_AXIS_DAC_A_tdata : IN std_logic_vector (15 DOWNTO 0);
S_AXIS_DAC_A_tvalid : IN std_logic;
S_AXIS_DAC_B_tdata : IN std_logic_vector (15 DOWNTO 0);
S_AXIS_DAC_B_tvalid : IN std_logic;
clk : IN std_logic;
resetn : IN std_logic;
clk_ioctrl_200MHz : IN std_logic;
DB : OUT std_logic_vector (13 DOWNTO 0)
);
END ENTITY radio_dac_if;
ARCHITECTURE struct OF radio_dac_if IS
SIGNAL dac_clk : std_logic;
SIGNAL data_I : std_logic_vector(13 DOWNTO 0);
SIGNAL data_Q : std_logic_vector(13 DOWNTO 0);
-- Component Declarations
COMPONENT IDELAYCTRL
PORT (
REFCLK : IN std_ulogic;
RST : IN std_ulogic;
RDY : OUT std_ulogic
);
END COMPONENT IDELAYCTRL;
COMPONENT IDELAYE2
GENERIC (
CINVCTRL_SEL : string := "FALSE";
DELAY_SRC : string := "IDATAIN";
HIGH_PERFORMANCE_MODE : string := "FALSE";
IDELAY_TYPE : string := "FIXED";
IDELAY_VALUE : integer := 0;
PIPE_SEL : string := "FALSE";
REFCLK_FREQUENCY : real := 200.0;
SIGNAL_PATTERN : string := "DATA"
);
PORT (
C : IN std_ulogic;
CE : IN std_ulogic;
CINVCTRL : IN std_ulogic;
CNTVALUEIN : IN std_logic_vector (4 DOWNTO 0);
DATAIN : IN std_ulogic;
IDATAIN : IN std_ulogic;
INC : IN std_ulogic;
LD : IN std_ulogic;
LDPIPEEN : IN std_ulogic;
REGRST : IN std_ulogic;
CNTVALUEOUT : OUT std_logic_vector (4 DOWNTO 0);
DATAOUT : OUT std_ulogic
);
END COMPONENT IDELAYE2;
COMPONENT BUFR
GENERIC (
BUFR_DIVIDE : string := "BYPASS";
SIM_DEVICE : string := "VIRTEX4"
);
PORT (
CE : IN std_ulogic;
CLR : IN std_ulogic;
I : IN std_ulogic;
O : OUT std_ulogic
);
END COMPONENT BUFR;
COMPONENT ODDR
GENERIC (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
PORT (
C : IN std_ulogic;
CE : IN std_ulogic;
D1 : IN std_ulogic;
D2 : IN std_ulogic;
R : IN std_ulogic := 'L';
S : IN std_ulogic := 'L';
Q : OUT std_ulogic
);
END COMPONENT ODDR;
BEGIN
dac_clk_delay : IDELAYE2
GENERIC MAP (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "IDATAIN",
HIGH_PERFORMANCE_MODE => "FALSE",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 10, -- 25: 125MHz -> 8ns/4/78ps
PIPE_SEL => "FALSE",
REFCLK_FREQUENCY => 200.0,
SIGNAL_PATTERN => "CLOCK"
)
PORT MAP (
CNTVALUEOUT => OPEN,
DATAOUT => dac_clk,
C => '0',
CE => '0',
CINVCTRL => '0',
CNTVALUEIN => (others => '0'),
DATAIN => '0',
IDATAIN => DCLKIO,
INC => '0',
LD => '0',
LDPIPEEN => '0',
REGRST => '0'
);
DAC_DDRs1: FOR i IN 0 TO 13 GENERATE
BEGIN
DAC_d : ODDR
GENERIC MAP (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
PORT MAP (
Q => DB(i),
C => dac_clk,
CE => '1',
D1 => data_Q(i),
D2 => data_I(i),
R => not resetn,
S => '0'
);
END GENERATE DAC_DDRs1;
read_data : PROCESS(clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
if S_AXIS_DAC_A_tvalid = '1' then
data_I <= S_AXIS_DAC_A_tdata(15 downto 2);
else
data_I <= (others => '0');
end if;
if S_AXIS_DAC_B_tvalid = '1' then
data_Q <= S_AXIS_DAC_B_tdata(15 downto 2);
else
data_Q <= (others => '0');
end if;
end if;
END PROCESS;
END ARCHITECTURE struct;
|
gpl-3.0
|
r2t2sdr/r2t2
|
fpga/modules/r2t2/adc/adc_fco_alignment_ctrl.vhd
|
1
|
1588
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;
LIBRARY unisim;
USE unisim.VCOMPONENTS.all;
ENTITY adc_fco_align_ctrl IS
PORT(
adc_clk_div : IN std_logic;
fco_serdes : IN std_logic_vector (7 DOWNTO 0);
bitslip : OUT std_logic;
serdes_ce : OUT std_logic;
serdes_rst : OUT std_logic
);
END ENTITY adc_fco_align_ctrl ;
--
ARCHITECTURE rtl OF adc_fco_align_ctrl IS
CONSTANT fco_pattern_c : std_logic_vector(7 DOWNTO 0) := "11110000";
-- CONSTANT fco_pattern_c : std_logic_vector(7 DOWNTO 0) := "00001111";
SIGNAL pattern_match : std_logic := '0';
SIGNAL timer : unsigned(1 DOWNTO 0) := "00";
SIGNAL fco_align_ce : std_logic := '0';
SIGNAL serdes_init : std_logic := '0';
BEGIN
serdes_rst <= not serdes_init;
serdes_ce <= serdes_init;
PROCESS(adc_clk_div)
BEGIN
IF adc_clk_div'EVENT AND adc_clk_div = '1' THEN
-- SERDES control...
serdes_init <= '1';
-- timer counting 16-bits...
fco_align_ce <= '0';
timer <= timer + 1;
IF timer = 3 THEN
fco_align_ce <= '1';
END IF;
-- Pattern comparator...
IF fco_serdes = fco_pattern_c THEN
pattern_match <= '1';
ELSE
pattern_match <= '0';
END IF;
bitslip <= '0'; -- default
IF fco_align_ce = '1' THEN
IF pattern_match = '0' THEN
bitslip <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/1541/vhdl_source/floppy.vhd
|
1
|
6555
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity floppy is
generic (
g_big_endian : boolean;
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
clock : in std_logic;
reset : in std_logic;
tick_16MHz : in std_logic;
-- signals from MOS 6522 VIA
motor_on : in std_logic;
stepper_en : in std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
side : in std_logic := '0';
step : in std_logic_vector(1 downto 0);
rate_ctrl : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
sync : out std_logic;
track : out unsigned(6 downto 0);
track_is_0 : out std_logic;
read_data : out std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
-- signals connected to sd-cpu
io_req_param : in t_io_req;
io_resp_param : out t_io_resp;
io_req_dirty : in t_io_req;
io_resp_dirty : out t_io_resp;
floppy_inserted : in std_logic := '0';
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
en_hum : out std_logic;
en_slip : out std_logic;
dirty_led_n : out std_logic;
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy;
architecture structural of floppy is
signal mem_rdata : std_logic_vector(7 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal do_advance : std_logic;
signal track_start : std_logic_vector(25 downto 0);
signal max_offset : std_logic_vector(13 downto 0);
signal track_i : unsigned(6 downto 0);
signal bit_time : unsigned(9 downto 0);
begin
en_hum <= motor_on and not floppy_inserted;
en_slip <= motor_on and floppy_inserted;
track <= track_i;
stream: entity work.floppy_stream
port map (
clock => clock,
reset => reset,
tick_16MHz => tick_16MHz,
mem_rdata => mem_rdata,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
floppy_inserted => floppy_inserted,
track => track_i,
track_is_0 => track_is_0,
do_head_bang => do_head_bang,
do_track_in => do_track_in,
do_track_out => do_track_out,
motor_on => motor_on,
stepper_en => stepper_en,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
rate_ctrl => rate_ctrl,
bit_time => bit_time,
read_data => read_data );
params: entity work.floppy_param_mem
generic map (
g_big_endian => g_big_endian )
port map (
clock => clock,
reset => reset,
io_req => io_req_param,
io_resp => io_resp_param,
track => track_i,
side => side,
track_start => track_start,
max_offset => max_offset,
bit_time => bit_time );
fetch_wb: entity work.floppy_mem
generic map (
g_tag => g_tag )
port map (
clock => clock,
reset => reset,
drv_rdata => mem_rdata,
drv_wdata => write_data,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
track_start => track_start,
max_offset => max_offset,
mem_req => mem_req,
mem_resp => mem_resp );
b_dirty: block
signal any_dirty : std_logic;
signal dirty_bits : std_logic_vector(127 downto 0) := (others => '0');
signal wa : integer range 0 to 127 := 0;
signal wr, wd : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
wa <= to_integer(unsigned(side & track_i(6 downto 1)));
wd <= '1';
wr <= '0';
if mode = '0' and motor_on='1' and floppy_inserted='1' then
wr <= '1';
any_dirty <= '1';
end if;
io_resp_dirty <= c_io_resp_init;
if io_req_dirty.read = '1' then
io_resp_dirty.ack <= '1';
io_resp_dirty.data(7) <= any_dirty;
io_resp_dirty.data(0) <= dirty_bits(to_integer(io_req_dirty.address(6 downto 0)));
end if;
if io_req_dirty.write = '1' then
io_resp_dirty.ack <= '1';
if io_req_dirty.data(7) = '1' then
any_dirty <= '0';
else
wa <= to_integer(io_req_dirty.address(6 downto 0));
wr <= '1';
wd <= '0';
end if;
end if;
if wr = '1' then
dirty_bits(wa) <= wd;
end if;
if reset = '1' then
any_dirty <= '0';
end if;
end if;
end process;
dirty_led_n <= not any_dirty;
end block;
end structural;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/sigma_delta_dac/vhdl_source/pdm_with_volume.vhd
|
1
|
4711
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
entity pdm_with_volume is
generic (
g_width : positive := 12;
g_invert : boolean := false;
g_use_mid_only : boolean := true;
g_left_shift : natural := 1 );
port (
clock : in std_logic;
reset : in std_logic;
volume : in std_logic_vector(3 downto 0) := X"F";
dac_in : in signed(g_width-1 downto 0);
dac_out : out std_logic );
end entity;
architecture gideon of pdm_with_volume is
signal dac_in_scaled : signed(g_width-1 downto g_left_shift);
signal converted : unsigned(g_width downto g_left_shift);
signal out_i : std_logic;
signal accu : unsigned(converted'range);
signal divider : integer range 0 to 15;
signal pattern : std_logic_vector(15 downto 0);
type t_patterns is array(0 to 15) of std_logic_vector(15 downto 0);
-- constant c_patterns : t_patterns := (
-- 0 => X"FF00", -- 8 ones and 8 zeros (off, but you may hear the unbalance)
-- 1 => X"FF80", -- 9 ones and 7 zeros
-- 2 => X"FFC0", -- 10 ones and 6 zeros
-- 3 => X"FFE0", -- 11 ones and 5 zeros
-- 4 => X"FFF0", -- 12 ones and 4 zeros
-- 5 => X"FFF8", -- 13 ones and 3 zeros
-- 6 => X"FFFC", -- 14 ones and 2 zeros
-- 7 => X"FFFE", -- 15 ones and 1 zero
-- 8 => X"FFFF", -- 16 ones and 0 zeros
-- 9 => X"FF08", -- experimental 8 ones 7 zeros (short '1')
-- 10 => X"F88F", -- experimental 9 ones 6 zeros (short '1')
-- 11 => X"FC0F", -- 10 ones and 6 zeros shifted
-- 12 => X"FE0F", -- 11 ones and 5 zeros shifted
-- 13 => X"FF0F", -- 12 ones and 4 zeros shifted
-- 14 => X"FF8F", -- 13 ones and 3 zeros shifted
-- 15 => X"FFCF" -- 14 ones and 2 zeros shifted
-- );
constant c_patterns : t_patterns := (
1 => "1111000010001111", -- 9 ones and 7 zeros (single one separate)
2 => "1111100000001111", -- 9 ones and 7 zeros (one extended)
3 => "1111100010001111", -- 10 ones and 6 zeros (single one separate)
4 => "1111100000011111", -- 10 ones and 6 zeros (one extended)
5 => "1111110000011111", -- 11 ones and 5 zeros
6 => "1111110000111111", -- 12 ones and 4 zeros
7 => "1111111000111111", -- 13 ones and 3 zeros
8 => "1111111001111111", -- 14 ones and 2 zeros
9 => "1111111101111111", -- 15 ones and 1 zero
10 => "1111111111111111", -- 16 ones and 0 zeros
others => "1111000000001111" -- 8 ones and 8 zeros (off, but you may hear the unbalance)
);
begin
dac_in_scaled <= left_scale(dac_in, g_left_shift);
converted <= (not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high downto g_left_shift))) when g_use_mid_only else
(not dac_in_scaled(dac_in_scaled'high) & unsigned(dac_in_scaled(dac_in_scaled'high-1 downto g_left_shift))) & '0';
process(clock)
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
variable a_new : unsigned(accu'range);
variable carry : std_logic;
begin
if rising_edge(clock) then
if divider = 15 then
if out_i = '0' then
pattern <= c_patterns(to_integer(unsigned(volume)));
else
pattern <= not c_patterns(to_integer(unsigned(volume)));
end if;
divider <= 0;
sum_with_carry(accu, converted, a_new, carry);
accu <= a_new;
if g_invert then
out_i <= not carry;
else
out_i <= carry;
end if;
else
divider <= divider + 1;
pattern <= '0' & pattern(pattern'high downto 1);
end if;
if reset='1' then
out_i <= not out_i;
accu <= (others => '0');
pattern <= X"5555";
end if;
end if;
end process;
dac_out <= pattern(0);
end gideon;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/issue217.vhd
|
5
|
863
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/protected1.vhd
|
5
|
1241
|
entity protected1 is
end entity;
architecture test of protected1 is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
variable dummy: Integer;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
shared variable x : SharedCounter;
begin
process is
begin
assert x.value = 0;
x.increment;
report "value is now " & integer'image(x.value);
x.increment(2);
assert x.value = 3;
wait;
end process;
process is
begin
wait for 1 ns;
assert x.value = 3;
x.decrement;
assert x.value = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/1541/vhdl_source/gcr2bin.vhd
|
5
|
1154
|
library ieee;
use ieee.std_logic_1164.all;
entity gcr2bin is
port (
d_in : in std_logic_vector(4 downto 0);
d_out : out std_logic_vector(3 downto 0);
error : out std_logic );
end gcr2bin;
architecture rom of gcr2bin is
begin
process(d_in)
begin
d_out <= X"0";
error <= '0';
case d_in is
when "01010" => d_out <= "0000";
when "01011" => d_out <= "0001";
when "10010" => d_out <= "0010";
when "10011" => d_out <= "0011";
when "01110" => d_out <= "0100";
when "01111" => d_out <= "0101";
when "10110" => d_out <= "0110";
when "10111" => d_out <= "0111";
when "01001" => d_out <= "1000";
when "11001" => d_out <= "1001";
when "11010" => d_out <= "1010";
when "11011" => d_out <= "1011";
when "01101" => d_out <= "1100";
when "11101" => d_out <= "1101";
when "11110" => d_out <= "1110";
when "10101" => d_out <= "1111";
when others =>
error <= '1';
end case;
end process;
end rom;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v2_mk1.vhd
|
5
|
10827
|
library work;
use work.tl_flat_memory_model_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity harness_v2_mk1 is
end harness_v2_mk1;
architecture tb of harness_v2_mk1 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := '1';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal LB_ADDR : std_logic_vector(21 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal MEM_WEn : std_logic;
signal MEM_OEn : std_logic;
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "111";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal ETH_CLK : std_logic;
signal ETH_RST : std_logic;
signal ETH_CSn : std_logic;
signal ETH_CS : std_logic;
signal FLASH_CSn : std_logic;
signal SRAM_CSn : std_logic;
signal ONE_WIRE : std_logic := 'H';
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
shared variable sram : h_mem_object;
-- shared variable bram : h_mem_object;
begin
mut: entity work.ultimate_1541_250e
generic map (
g_simulation => true )
port map (
CLOCK => sys_clock,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
LB_ADDR => LB_ADDR,
LB_DATA => LB_DATA,
FLASH_CSn => FLASH_CSn,
SRAM_CSn => SRAM_CSn,
MEM_WEn => MEM_WEn,
MEM_OEn => MEM_OEn,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
SDRAM_DQM => SDRAM_DQM,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- USB
USB_IOP => open,
USB_ION => open,
USB_SEP => '1',
USB_SEN => '0',
USB_DET => open,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_WP => '0',
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Ethernet Interface
ETH_CLK => ETH_CLK,
ETH_IRQ => '0',
ETH_CSn => ETH_CSn,
ETH_CS => ETH_CS,
ETH_RST => ETH_RST,
ONE_WIRE => ONE_WIRE,
-- Buttons
BUTTON => BUTTON );
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', '1' after 6 us;
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
bind_mem_model("sram", sram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
load_memory("../../software/ultimate/result/ultimate_V1.bin", sram, X"00030000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"7FF0";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
sram_bfm: entity work.sram_model_8
generic map("sram", 19, 10 ns)
port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn);
flash_bfm: entity work.sram_model_8
generic map("flash", 21, 70 ns)
port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1');
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
-- assert not (ADDRESS(18 downto 16)="011" and ADDRESS(15 downto 0)=X"86A0" and SRAM_CSn='0' and MEM_WEn='0')
-- report "writing to jump address."
-- severity failure;
-- sram: entity work.sram_model_8
-- generic map("sram", 19, 10 ns)
-- port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn);
--
-- flash: entity work.sram_model_8
-- generic map("flash", 21, 70 ns)
-- port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1');
-- process(ETH_CS, ETH_CSn, LB_ADDR)
-- begin
-- if ETH_CS='1' and ETH_CSn='0' then
-- LB_DATA <= not LB_ADDR(7 downto 0) after 135 ns;
-- else
-- LB_DATA <= (others => 'Z') after 50 ns;
-- end if;
-- end process;
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm_pkg.vhd
|
5
|
5996
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.slot_bus_pkg.all;
package slot_bus_master_bfm_pkg is
type t_slot_bus_master_bfm_object;
type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object;
type t_slot_bus_bfm_command is ( e_slot_none, e_slot_io_read, e_slot_bus_read,
e_slot_io_write, e_slot_bus_write );
type t_slot_bus_master_bfm_object is record
next_bfm : p_slot_bus_master_bfm_object;
name : string(1 to 256);
command : t_slot_bus_bfm_command;
poll_time : time;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
irq_pending : boolean;
end record;
------------------------------------------------------------------------------------
shared variable slot_bus_master_bfms : p_slot_bus_master_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
procedure bind_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
------------------------------------------------------------------------------------
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object);
end slot_bus_master_bfm_pkg;
package body slot_bus_master_bfm_pkg is
procedure register_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_slot_bus_master_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if slot_bus_master_bfms = null then -- first entry
slot_bus_master_bfms := pntr;
else -- insert new entry
pntr.next_bfm := slot_bus_master_bfms;
slot_bus_master_bfms := pntr;
end if;
pntr.irq_pending := false;
pntr.poll_time := 10 ns;
end register_slot_bus_master_bfm;
procedure bind_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
variable p : p_slot_bus_master_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := slot_bus_master_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_slot_bus_master_bfm;
------------------------------------------------------------------------------
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object) is
begin
while not m.irq_pending loop
wait for m.poll_time;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/iec_interface/vhdl_sim/dual_iec_processor_tb.vhd
|
5
|
5118
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_string_util_pkg.all;
entity dual_iec_processor_tb is
end dual_iec_processor_tb;
architecture tb of dual_iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal master_req : t_io_req;
signal master_resp : t_io_resp;
signal slave_req : t_io_req;
signal slave_resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_master: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => master_req,
resp => master_resp,
clk_o => master_clk_o,
clk_i => iec_clock,
data_o => master_data_o,
data_i => iec_data,
atn_o => master_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
i_slave: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => slave_req,
resp => slave_resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => open,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm_master" )
port map (
clock => clock,
req => master_req,
resp => master_resp );
i_io_bfm2: entity work.io_bus_bfm
generic map (
g_name => "io_bfm_slave" )
port map (
clock => clock,
req => slave_req,
resp => slave_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm_master", iom);
io_write(iom, X"3", X"01"); -- enable master
io_write(iom, X"5", X"4D"); -- switch to master mode
io_write(iom, X"4", X"2A"); -- listen 10
io_write(iom, X"4", X"F0"); -- open file on channel 0
io_write(iom, X"5", X"4C"); -- attention to TX
io_write(iom, X"4", X"41"); -- 'A'
io_write(iom, X"5", X"01"); -- EOI
io_write(iom, X"4", X"42"); -- 'B'
io_write(iom, X"5", X"4D"); -- again, be master
io_write(iom, X"4", X"3F"); -- unlisten
io_write(iom, X"4", X"4A"); -- talk #10!
io_write(iom, X"4", X"60"); -- give data from channel 0
io_write(iom, X"5", X"4A"); -- attention to RX turnaround
wait;
end process;
process
variable ios : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm_slave", ios);
io_write(ios, X"3", X"01"); -- enable slave
while true loop
io_read(ios, X"2", stat);
if stat(0)='0' then -- byte available
io_read(ios, X"6", data);
if stat(7)='1' then -- control byte
report "Control byte received: " & hstr(data);
if (data = X"43") then
report "Talk back!";
io_write(ios, X"4", X"31");
io_write(ios, X"4", X"32");
io_write(ios, X"4", X"33");
io_write(ios, X"5", X"01"); -- EOI
io_write(ios, X"4", X"34");
end if;
else
report "Data byte received: " & hstr(data);
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/altera/xilinx_primitives/RAMB16_S9_S18-model.vhd
|
1
|
1061
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture model of RAMB16_S9_S18 is
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
shared variable mem : t_byte_array(0 to 2047) := (others => X"00");
begin
process(CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
DOA <= mem(to_integer(unsigned(ADDRA)));
if WEA = '1' then
mem(to_integer(unsigned(ADDRA))) := DIA;
end if;
end if;
end if;
end process;
process(CLKB)
variable addr : natural;
begin
if rising_edge(CLKB) then
if ENB = '1' then
addr := 2 * to_integer(unsigned(ADDRB));
DOB <= mem(addr + 1) & mem(addr);
if WEB = '1' then
mem(addr) := DIB(7 downto 0);
mem(addr + 1) := DIB(15 downto 8);
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/signal10.vhd
|
5
|
748
|
entity signal10 is
end entity;
architecture test of signal10 is
signal x, y, z : bit;
signal u : bit_vector(1 to 3);
signal v : bit_vector(2 downto 0);
begin
process is
begin
(x, y, z) <= bit_vector'("011");
wait for 1 ns;
assert x = '0';
assert y = '1';
assert z = '1';
u <= bit_vector'("011");
wait for 1 ns;
(x, y, z) <= u;
wait for 1 ns;
assert x = '0';
assert y = '1';
assert z = '1';
v <= bit_vector'("011");
wait for 1 ns;
(x, y, z) <= v;
wait for 1 ns;
assert x = '0';
assert y = '1';
assert z = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4.vhd
|
5
|
9586
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (no burst)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4 is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v4;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v4 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"0220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(req.tag'range);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack : std_logic;
signal rack : std_logic;
signal rack_tag : std_logic_vector(req.tag'range);
signal dack_tag : std_logic_vector(req.tag'range);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
attribute iob of SDRAM_CKE : signal is "false";
begin
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_i;
resp.rack <= rack;
resp.rack_tag <= rack_tag;
resp.dack_tag <= dack_tag;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
sram_d_t <= '0'; --not req.read_writen;
sram_d_o <= req.data;
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
dout_sel <= '0';
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
SDRAM_CSn <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= not rwn_i; -- enable for writes
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 2;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
if rwn_i = '1' then -- read
dack <= '1';
dack_tag <= tag;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sram_d_t <= '0';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/assign2.vhd
|
5
|
353
|
entity assign2 is
end entity;
architecture test of assign2 is
begin
process is
variable x : bit_vector(7 downto 0) := (1 => '1', others => '0');
begin
assert x(0) = '0';
assert x(1) = '1';
assert x(4) = x(5);
x(2) := '1';
assert x(2) = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/attr6.vhd
|
4
|
895
|
entity attr6 is
end entity;
architecture test of attr6 is
signal x : integer := 5;
signal y : bit_vector(0 to 3);
begin
process is
begin
assert x'last_event = time'high;
x <= 0;
assert x'last_value = x;
assert x'last_value = 5;
wait for 1 ns;
assert x'last_value = 5;
assert x'last_event = 1 ns;
x <= 2;
wait for 1 ns;
assert x = 2;
assert x'last_value = 0;
assert x'last_event = 1 ns;
assert y'last_value = y;
y <= ( '0', '1', '0', '1' );
wait for 1 ns;
assert y'last_value = ( '0', '0', '0', '0' );
y(1) <= '1';
wait for 1 ns;
assert y'last_value = ( '0', '0', '0', '0' );
y(1) <= '0';
wait for 1 ns;
assert y'last_value = ( '0', '1', '0', '0' );
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/memory/vhdl_source/dpram.vhd
|
5
|
3149
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first_a : boolean := false;
g_read_first_b : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
a_clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
a_en : in std_logic := '1';
a_we : in std_logic := '0';
b_clock : in std_logic := '0';
b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0');
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram : entity is "yes";
end entity;
architecture xilinx of dpram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
-----------------------------------------------------------------------
-- PORT A
-----------------------------------------------------------------------
p_port_a: process(a_clock)
begin
if rising_edge(a_clock) then
if a_en = '1' then
if g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
if a_we = '1' then
ram(to_integer(a_address)) := a_wdata;
end if;
if not g_read_first_a then
a_rdata <= ram(to_integer(a_address));
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- PORT B
-----------------------------------------------------------------------
p_port_b: process(b_clock)
begin
if rising_edge(b_clock) then
if b_en = '1' then
if g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
end if;
if not g_read_first_b then
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
target/simulation/packages/vhdl_source/tl_sctb_pkg.vhd
|
2
|
23924
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL
-- | ======= I == I =
-- | I I I I
-- | I === === I === I === === I I I ==== I === I ===
-- | I / \ I I/ I I/ I I I I I I I I I I I/ I
-- | I ===== I I I I I I I I I I I I I I I I
-- | I \ I I I I I I I I I /I \ I I I I I
-- | I === === I I I I === === === I == I === I I
-- | +---------------------------------------------------+
-- +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++|
-- | | ++++++++++++++++++++++++++++++++++++++|
-- +------------+ +++++++++++++++++++++++++|
-- ++++++++++++++|
-- A U T O M A T I O N T E C H N O L O G Y +++++|
--
-------------------------------------------------------------------------------
-- Title : Support package for self-checking testbenches
-- Author : Jonathan Hofman ([email protected])
-- Author : Ard Wiersma ([email protected])
-- Author : Edwin Hakkennes ([email protected])
-------------------------------------------------------------------------------
-- Description: Support package for self-checking testbenches
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_string_util_pkg.all;
package tl_sctb_pkg is
---------------------------------------------------------------------------
-- constants for the log-level
---------------------------------------------------------------------------
constant c_log_level_error : integer := 0;
constant c_log_level_warning : integer := 1;
constant c_log_level_trace : integer := 2;
---------------------------------------------------------------------------
-- procedures to open and close the simulation
---------------------------------------------------------------------------
procedure sctb_open_simulation(testcase_name : string;
output_file_name : string;
log_level : integer := c_log_level_error);
procedure sctb_close_simulation(force: boolean := false);
---------------------------------------------------------------------------
-- procedures to open and close a region within a simulation
---------------------------------------------------------------------------
procedure sctb_open_region(region_name : string;
expected_errors : integer := 0);
procedure sctb_open_region(region_name : string;
msg : string;
expected_errors : integer := 0);
procedure sctb_close_region;
---------------------------------------------------------------------------
-- procedures to test conditions and report strings
---------------------------------------------------------------------------
procedure sctb_assert(condition : boolean;
msg : string);
procedure sctb_error(msg : string);
procedure sctb_warning(msg : string);
procedure sctb_trace(msg : string);
---------------------------------------------------------------------------
-- procedures to check correctness
---------------------------------------------------------------------------
procedure sctb_check (
data_a : in std_logic_vector;
data_b : in std_logic_vector;
msg : in string);
procedure sctb_check (
data_a : in unsigned;
data_b : in unsigned;
msg : in string);
procedure sctb_check (
data_a : in signed;
data_b : in signed;
msg : in string);
procedure sctb_check (
data_a : in std_logic;
data_b : in std_logic;
msg : in string);
procedure sctb_check (
data_a : in integer;
data_b : in integer;
msg : in string);
procedure sctb_check (
data_a : in boolean;
data_b : in boolean;
msg : in string);
---------------------------------------------------------------------------
-- procedures to expect expected value correctness
---------------------------------------------------------------------------
procedure sctb_expect (
expect : in std_logic_vector;
got : in std_logic_vector;
msg : in string);
procedure sctb_expect (
expect : in unsigned;
got : in unsigned;
msg : in string);
procedure sctb_expect (
expect : in signed;
got : in signed;
msg : in string);
procedure sctb_expect (
expect : in std_logic;
got : in std_logic;
msg : in string);
procedure sctb_expect (
expect : in integer;
got : in integer;
msg : in string);
procedure sctb_expect (
expect : in boolean;
got : in boolean;
msg : in string);
---------------------------------------------------------------------------
-- procedures to control the output
---------------------------------------------------------------------------
procedure sctb_set_log_level(log_level : integer);
procedure sctb_log_to_console(input : boolean := true);
---------------------------------------------------------------------------
-- signals
---------------------------------------------------------------------------
shared variable v_current_region: string(1 to 32);
end package;
package body tl_sctb_pkg is
---------------------------------------------------------------------------
-- private types, variables and constants
---------------------------------------------------------------------------
type t_string_ptr is access string;
type t_error_simulation is
record
output_file : t_string_ptr;
testcase_name : t_string_ptr;
region_active : boolean;
nr_of_regions : integer;
nr_of_failed_regions : integer;
nr_of_succeded_regions : integer;
log_level : integer;
end record;
shared variable c_error_simulation_rst : t_error_simulation := (
output_file => null,
testcase_name => null,
region_active => false,
nr_of_regions => 0,
nr_of_failed_regions => 0,
nr_of_succeded_regions => 0,
log_level => c_log_level_error);
shared variable error_simulation : t_error_simulation := c_error_simulation_rst;
type t_error_region is
record
name : t_string_ptr;
error_count : integer;
expected_errors : integer;
end record;
shared variable c_error_region_rst : t_error_region := (
name => null,
error_count => 0,
expected_errors => 0);
shared variable error_region : t_error_region;
file output_file : text;
shared variable v_log_to_console : boolean := true;
---------------------------------------------------------------------------
-- private procedures
---------------------------------------------------------------------------
-- purpose: write a line to the error log only, intended for pretty-printing
procedure write_line_log(str : string) is
variable v_line : line;
begin
if error_simulation.output_file = null then
print("[SCTB]" & str);
else
write(v_line, str);
writeline(output_file, v_line);
end if;
end procedure;
-- purpose: write a line to the error log and the console, conditionally
procedure write_line_cond (
str : string) is
begin -- write_line
if v_log_to_console then
print("[SCTB]"& str);
end if;
write_line_log(str);
end write_line_cond;
-- purpose: write a line to the error log and the console, unconditionally
procedure write_line (
str : string) is
begin -- write_line
print("[SCTB] " & time'image(now) & ": " & str);
write_line_log(str);
end write_line;
procedure write_line_of_stars is
begin -- write_line_of_stars
write_line_cond("*******************************************************************************");
end write_line_of_stars;
procedure print_header is
begin -- print_header
write_line_log("*******************************************************************************");
write_line_log("** **");
write_line_log("** (C) COPYRIGHT 2006 TECHNOLUTION BV, GOUDA NL **");
write_line_log("** | ======= I == I = **");
write_line_log("** | I I I I **");
write_line_log("** | I === === I === I === === I I I ==== I === I === **");
write_line_log("** | I / \ I I/ I I/ I I I I I I I I I I I/ I **");
write_line_log("** | I ===== I I I I I I I I I I I I I I I I **");
write_line_log("** | I \ I I I I I I I I I /I \ I I I I I **");
write_line_log("** | I === === I I I I === === === I == I === I I **");
write_line_log("** | +---------------------------------------------------+ **");
write_line_log("** +----+ | +++++++++++++++++++++++++++++++++++++++++++++++++| **");
write_line_log("** | | ++++++++++++++++++++++++++++++++++++++| **");
write_line_log("** +------------+ +++++++++++++++++++++++++| **");
write_line_log("** ++++++++++++++| **");
write_line_log("** A U T O M A T I O N T E C H N O L O G Y +++++| **");
write_line_log("** **");
write_line_log("*******************************************************************************");
end print_header;
---------------------------------------------------------------------------
-- procedures to open and close the simulation
---------------------------------------------------------------------------
procedure sctb_open_simulation(
testcase_name : string;
output_file_name : string;
log_level : integer := c_log_level_error) is
variable testcase_name_int : string(1 to 80);
variable testcase_name_length : natural := 0;
variable v_stat : file_open_status;
begin
l_name_format : for i in 1 to 80 loop
exit l_name_format when testcase_name(i+1) = ':';
testcase_name_int(i) := testcase_name(i+1);
testcase_name_length := i;
end loop l_name_format; -- i
error_simulation := c_error_simulation_rst;
error_simulation.output_file := new string'(output_file_name);
error_simulation.testcase_name :=
new string'(testcase_name_int(1 to testcase_name_length));
file_open(v_stat, output_file, output_file_name, write_mode);
assert (v_stat = open_ok)
report "tl_sctb_pkg: Could not open file " & output_file_name & " for writing."
severity failure;
print_header;
write_line_log("");
write_line_of_stars;
write_line_cond("** Opening simulation : " &
error_simulation.testcase_name.all);
write_line_of_stars;
sctb_set_log_level(log_level);
end procedure;
procedure sctb_close_simulation(force: boolean := false) is
begin
assert(error_simulation.region_active = false)
report "tl_sctb_pkg: close active region before closing simulation!!"&
"Please correct your testbench and run the test again."
severity failure;
write_line_log("");
write_line_of_stars;
if error_simulation.nr_of_failed_regions > 0 then
write_line_cond("** Closing simulation : "&
error_simulation.testcase_name.all);
write_line("** Simulation verdict : FAILURE - " &
integer'image(error_simulation.nr_of_failed_regions)
& " region(s) failed!");
write_line_of_stars;
file_close(output_file);
else
write_line_cond("** Closing simulation : "&
error_simulation.testcase_name.all);
write_line_cond("** Simulation verdict : SUCCESSFUL");
write_line_of_stars;
file_close(output_file);
end if;
if force then
report "simulation end forced using report failure (this does not imply a simulation error). " &
"See simulation verdict for actual simulation result!"
severity failure;
end if;
end procedure;
---------------------------------------------------------------------------
-- procedures to open and close a region within a simulation
---------------------------------------------------------------------------
procedure sctb_open_region(
region_name : string;
msg : string;
expected_errors : integer := 0) is
begin
assert(error_simulation.region_active = false)
report "tl_sctb_pkg: testbench failure - opening region """ & region_name
& """ without closing the last region first." &
"Please correct your testbench and run the test again."
severity failure;
write_line_log("");
write_line_of_stars;
if msg = "" then
write_line_cond("** Opening region : " & region_name);
else
write_line_cond("** Opening region : " & region_name & " - " & msg);
end if;
write_line_cond("** Expected errors : " & integer'image(expected_errors));
write_line_log("**");
if error_region.name /= null then
deallocate(error_region.name);
end if;
error_region := c_error_region_rst;
error_region.name := new string'(region_name);
v_current_region := resize(region_name, v_current_region'length);
error_region.expected_errors := expected_errors;
error_simulation.region_active := true;
end procedure;
procedure sctb_open_region(
region_name : string;
expected_errors : integer := 0) is
begin
sctb_open_region(region_name, "", expected_errors);
end procedure;
procedure sctb_close_region is
begin
assert(error_simulation.region_active = true)
report "tl_sctb_pkg: testbench failure - closing an inactive region." &
"Please correct your testbench and run the test again."
severity failure;
write_line_log("**");
write_line_cond("** Closing region : " & error_region.name.all);
write_line_cond("** Expected errors : " & integer'image(error_region.expected_errors));
write_line_cond("** Errors : " & integer'image(error_region.error_count));
if error_region.error_count /= error_region.expected_errors then
write_line_cond("** Test verdict : FAILED");
error_simulation.nr_of_failed_regions := error_simulation.nr_of_failed_regions + 1;
else
write_line_cond("** Test verdict : SUCCEEDED");
error_simulation.nr_of_succeded_regions := error_simulation.nr_of_succeded_regions + 1;
end if;
write_line_of_stars;
error_simulation.region_active := false;
v_current_region := resize("none", v_current_region'length);
end procedure;
---------------------------------------------------------------------------
-- procedures to test conditions and report strings
---------------------------------------------------------------------------
procedure sctb_assert(condition : boolean;
msg : string) is
begin
if not condition then
sctb_error(msg);
end if;
end procedure;
procedure sctb_error(msg : string) is
begin
assert (error_simulation.region_active)
report "tl_sctb_pkg: testbench failure - Reporting an error while no error region is active." &
"Please correct your testbench and run the test again."
severity failure;
error_region.error_count := error_region.error_count + 1;
if error_region.error_count <= error_region.expected_errors then
write_line("(ERROR): " & msg);
else
write_line("[ERROR]: " & msg);
end if;
end procedure;
procedure sctb_warning(msg : string) is
begin
if error_simulation.log_level >= c_log_level_warning then
write_line("(WARNING): " & msg);
end if;
end procedure;
procedure sctb_trace(msg : string) is
begin
if error_simulation.log_level >= c_log_level_trace then
write_line("(TRACE): " & msg);
end if;
end procedure;
---------------------------------------------------------------------------
-- procedures to check expected value
---------------------------------------------------------------------------
procedure sctb_expect (
expect : in std_logic_vector;
got : in std_logic_vector;
msg : in string) is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: 0x" & hstr(expect)
&" Got : 0x" & hstr(got));
end;
procedure sctb_expect (
expect : in unsigned;
got : in unsigned;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: 0x" & hstr(expect)
&" Got : 0x" & hstr(got));
end;
procedure sctb_expect (
expect : in signed;
got : in signed;
msg : in string)is
begin
sctb_expect(to_integer(expect),to_integer(got),msg);
end;
procedure sctb_expect (
expect : in std_logic;
got : in std_logic;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & std_logic'image(expect)
&" Got : " & std_logic'image(got));
end;
procedure sctb_expect (
expect : in integer;
got : in integer;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & integer'image(expect)
&" Got : " & integer'image(got));
end;
procedure sctb_expect (
expect : in boolean;
got : in boolean;
msg : in string)is
begin
sctb_assert (
condition => (expect = got),
msg => msg & " : Expected: " & boolean'image(expect)
&" Got : " & boolean'image(got));
end;
---------------------------------------------------------------------------
-- procedures to check correctness
---------------------------------------------------------------------------
procedure sctb_check (
data_a : in std_logic_vector;
data_b : in std_logic_vector;
msg : in string) is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(data_a)
&" not identical to data_b : 0x" & hstr(data_b));
end;
procedure sctb_check (
data_a : in unsigned;
data_b : in unsigned;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(data_a)
&" not identical to data_b : 0x" & hstr(data_b));
end;
procedure sctb_check (
data_a : in signed;
data_b : in signed;
msg : in string)is
begin
if data_a'length <= 32 then
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : " & str(to_integer(data_a)) & " (0x" & hstr(std_logic_vector(data_a))
&") not identical to data_b : " & str(to_integer(data_b)) & " (0x" & hstr(std_logic_vector(data_b)) & ")");
else
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : 0x" & hstr(std_logic_vector(data_a))
&" not identical to data_b : 0x" & hstr(std_logic_vector(data_b)));
end if;
end;
procedure sctb_check (
data_a : in std_logic;
data_b : in std_logic;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&std_logic'image(data_a)
&" not identical to data_b : "&std_logic'image(data_b));
end;
procedure sctb_check (
data_a : in integer;
data_b : in integer;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&integer'image(data_a)
&" not identical to data_b : "&integer'image(data_b));
end;
procedure sctb_check (
data_a : in boolean;
data_b : in boolean;
msg : in string)is
begin
sctb_assert (
condition => (data_a = data_b),
msg => msg & " data_a : "&boolean'image(data_a)
&" not identical to data_b : "&boolean'image(data_b));
end;
---------------------------------------------------------------------------
-- procedures to control the output
---------------------------------------------------------------------------
procedure sctb_set_log_level(log_level : integer) is
begin
error_simulation.log_level := log_level;
end procedure;
procedure sctb_log_to_console(input : boolean := true) is
begin
v_log_to_console := input;
end sctb_log_to_console;
end;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/issue140.vhd
|
5
|
991
|
package protected_type_pkg is
type protected_t is protected
procedure proc;
end protected;
end package;
package body protected_type_pkg is
type protected_t is protected body
procedure proc is
begin
end;
end protected body;
end package body;
-------------------------------------------------------------------------------
use work.protected_type_pkg.protected_t;
entity e is
end entity;
architecture a of e is
procedure proc(variable prot : inout protected_t) is
begin
prot.proc; -- Was undefined
end;
begin
end architecture;
-------------------------------------------------------------------------------
use work.protected_type_pkg.protected_t;
package protected_user_pkg is
procedure proc(variable prot : inout protected_t);
end package;
package body protected_user_pkg is
procedure proc(variable prot : inout protected_t) is
begin
prot.proc; -- Was undefined
end;
end package body;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/sampler/vhdl_source/sampler2.vhd
|
1
|
10239
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler is
generic (
g_clock_freq : natural := 50_000_000;
g_num_voices : positive := 8 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
irq : out std_logic;
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler is
function iif(c : boolean; t : natural; f : natural) return natural is
begin
if c then return t; else return f; end if;
end function iif;
-- At this point there are 3 systems:
-- Ultimate-II running at 50 MHz
-- Ultimate-II+ running at 62.5 MHz
-- Ultimate-64 running at 66.66 MHz
-- The ratios are: 1, 5/4 and 4/3, or 12/12, 15/12 and 16/12. So we should divide by this value
-- Or multiply by: 20/20, 16/20 and 15/20
constant c_prescale_numerator : natural := iif(g_clock_freq = 50_000_000, 1, iif(g_clock_freq = 62_500_000, 4, 3));
constant c_prescale_denominator : natural := iif(g_clock_freq = 50_000_000, 1, iif(g_clock_freq = 62_500_000, 5, 4));
signal voice_i : integer range 0 to g_num_voices-1;
signal voice_state : t_voice_state_array(0 to g_num_voices-1) := (others => c_voice_state_init);
signal voice_sample_reg_h : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_sample_reg_l : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal fetch_en : std_logic;
signal fetch_addr : unsigned(25 downto 0);
signal fetch_tag : std_logic_vector(7 downto 0);
signal interrupt : std_logic_vector(g_num_voices-1 downto 0);
signal interrupt_clr : std_logic_vector(g_num_voices-1 downto 0);
signal current_control : t_voice_control;
signal first_chan : std_logic;
signal cur_sam : signed(15 downto 0);
signal cur_vol : unsigned(5 downto 0);
signal cur_pan : unsigned(3 downto 0);
begin
i_regs: entity work.sampler_regs
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
rd_addr => voice_i,
control => current_control,
irq_status => interrupt,
irq_clear => interrupt_clr );
irq <= '1' when unsigned(interrupt) /= 0 else '0';
process(clock)
variable current_state : t_voice_state;
variable next_state : t_voice_state;
variable sample_reg : signed(15 downto 0);
variable v : integer range 0 to 15;
begin
if rising_edge(clock) then
if voice_i = g_num_voices-1 then
voice_i <= 0;
else
voice_i <= voice_i + 1;
end if;
for i in interrupt'range loop
if interrupt_clr(i)='1' then
interrupt(i) <= '0';
end if;
end loop;
fetch_en <= '0';
current_state := voice_state(0);
sample_reg := voice_sample_reg_h(voice_i) & voice_sample_reg_l(voice_i);
next_state := current_state;
case current_state.state is
when idle =>
if current_control.enable then -- and voice_i <= g_num_voices
next_state.state := fetch1;
next_state.position := (others => '0');
next_state.divider := current_control.rate;
next_state.sample_out := (others => '0');
end if;
when playing =>
if current_state.prescale + c_prescale_numerator >= c_prescale_denominator then
next_state.prescale := current_state.prescale + c_prescale_numerator - c_prescale_denominator;
if current_state.divider = 0 then
next_state.divider := current_control.rate;
next_state.sample_out := sample_reg;
next_state.state := fetch1;
if (current_state.position = current_control.repeat_b) then
if current_control.enable and current_control.repeat then
next_state.position := current_control.repeat_a;
end if;
elsif current_state.position = current_control.length then
next_state.state := finished;
if current_control.interrupt then
interrupt(voice_i) <= '1';
end if;
end if;
else
next_state.divider := current_state.divider - 1;
end if;
else
next_state.prescale := current_state.prescale + c_prescale_numerator;
end if;
if not current_control.enable and not current_control.repeat then
next_state.state := idle;
end if;
when finished =>
if not current_control.enable then
next_state.state := idle;
end if;
when fetch1 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
if current_control.mode = mono8 then
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 2; -- this and the next byte
else
next_state.position := current_state.position + 1; -- this byte only
end if;
else
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '0'; -- low
next_state.position := current_state.position + 1; -- go to the next byte
next_state.state := fetch2;
end if;
when fetch2 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 3; -- this and the two next bytes
else
next_state.position := current_state.position + 1; -- this byte only
end if;
when others =>
null;
end case;
cur_sam <= current_state.sample_out;
cur_vol <= current_control.volume;
cur_pan <= current_control.pan;
if voice_i=0 then
first_chan <= '1';
else
first_chan <= '0';
end if;
-- write port - state --
voice_state <= voice_state(1 to g_num_voices-1) & next_state;
-- write port - sample data --
if mem_resp.dack_tag(7 downto 5) = "110" then
v := to_integer(unsigned(mem_resp.dack_tag(4 downto 1)));
if mem_resp.dack_tag(0)='1' then
voice_sample_reg_h(v) <= signed(mem_resp.data);
else
voice_sample_reg_l(v) <= signed(mem_resp.data);
end if;
end if;
if reset='1' then
voice_i <= 0;
next_state.state := finished; -- shifted into the voice state vector automatically.
interrupt <= (others => '0');
end if;
end if;
end process;
b_mem_fifo: block
signal rack : std_logic;
signal fifo_din : std_logic_vector(33 downto 0);
signal fifo_dout : std_logic_vector(33 downto 0);
begin
fifo_din <= fetch_tag & std_logic_vector(fetch_addr);
i_fifo: entity work.srl_fifo
generic map (
Width => 34,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => fetch_en,
FlushFifo => '0',
DataIn => fifo_din,
DataOut => fifo_dout,
SpaceInFifo => open,
DataInFifo => mem_req.request );
mem_req.read_writen <= '1';
mem_req.address <= unsigned(fifo_dout(25 downto 0));
mem_req.tag <= fifo_dout(33 downto 26);
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time (can be optimized!)
rack <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(7 downto 5)="110") else '0';
end block;
i_accu: entity work.sampler_accu
port map (
clock => clock,
reset => reset,
first_chan => first_chan,
sample_in => cur_sam,
volume_in => cur_vol,
pan_in => cur_pan,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
end gideon;
|
gpl-3.0
|
keyru/hdl-make
|
tests/questa_uvm_sv/rtl/RTLTopModuleVHDL.vhdl
|
1
|
1934
|
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <[email protected]> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
component includeModuleVHDL is
end component;
signal probe : STD_LOGIC;
begin -- architectureecture Behavioral
probe <= '1';
include_module : includeModuleVHDL;
a : entity work.includeModuleAVHDL;
GEN : for i in 0 to 3 generate
B : entity work.includeModuleBVHDL;
end generate;
end architecture Behavioral;
|
gpl-3.0
|
chiggs/nvc
|
test/lower/issue134.vhd
|
5
|
231
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/alias7.vhd
|
5
|
649
|
entity alias7 is
end entity;
architecture test of alias7 is
signal x : bit_vector(7 downto 0);
alias top is x(7);
signal ctr : integer := 0;
begin
process (top) is
begin
if top = '1' then
ctr <= ctr + 1;
end if;
end process;
process is
begin
assert ctr = 0;
x <= X"3f";
wait for 1 ns;
assert ctr = 0;
x <= X"80";
wait for 1 ns;
assert ctr = 1;
x <= X"00";
wait for 1 ns;
assert ctr = 1;
x <= X"ff";
wait for 1 ns;
assert ctr = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/bounds10.vhd
|
5
|
334
|
entity bounds10 is
end entity;
architecture test of bounds10 is
begin
process is
variable n : integer;
variable a : bit_vector(3 downto 0);
variable b : bit_vector(7 downto 0);
begin
n := 7;
wait for 1 ns;
a := b(n downto 0);
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/comp1.vhd
|
5
|
707
|
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a, b : integer;
component comp1_bot is
port (
x : in integer;
y : out integer );
end component;
begin
c1: component comp1_bot
port map ( 1, a );
c2: comp1_bot
port map ( 2, b );
process is
begin
wait for 1 ns;
assert a = 2;
assert b = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
lib/synopsys/std_logic_textio.vhd
|
5
|
18668
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk); -- but also exit on a bad read
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
if (readOk = FALSE) then
good := FALSE;
else
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
variable readOk: BOOLEAN;
begin
loop -- skip white space
read(l,c,readOk);
exit when ((readOk = FALSE) or ((c /= ' ') and (c /= CR) and (c /= HT)));
end loop;
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s, readOk);
-- Bail out if there was a bad read
if (readOk = FALSE) then
good := FALSE;
return;
end if;
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out std_ulogic_vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'Z' => result(0) := 'Z'; result(1) := 'Z'; result(2) := 'Z'; result(3) := 'Z'; good := TRUE;
when 'X' => result(0) := 'X'; result(1) := 'X'; result(2) := 'X'; result(3) := 'X'; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: std_ulogic_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := To_X01Z(bv(4*i to 4*i+3));
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
when others =>
if (quad = "ZZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in std_ulogic_vector;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: std_ulogic_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: std_ulogic_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := To_X01Z(bv(3*i to 3*i+2));
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
when others =>
if (tri = "ZZZ") then
s(i+1) := 'Z';
else
s(i+1) := 'X';
end if;
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD:out BOOLEAN) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_BitVector(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable tmp: std_ulogic_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_BitVector(tmp);
end HREAD;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
gpl-3.0
|
jresendiz27/electronica
|
digitales/BoothsAlgorithm/BoothAlgorithm/main.vhd
|
2
|
1416
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity main is
port (
sal: inout std_logic_vector (7 downto 0);
CLK : in std_logic;
multiplicando : inout std_logic_vector(7 downto 0) := "00000111";
arreglo : inout std_logic_vector (7 downto 0):="00000000";
multiplicador : inout std_logic_vector(7 downto 0) := "00000011";
test : inout std_logic_vector(7 downto 0):="00000000");
end main;
architecture Behavioral of main is
signal I : natural := 0;
signal auxArray : std_logic_vector(7 downto 0) := "00000000";
function reverse_any_vector (a: in std_logic_vector)
return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_vector
begin
process(CLK)
begin
if CLK'event and CLK = '1' then
if I <= 7 then
if '1' = multiplicador(I) then
--arreglo <= reverse_any_vector(arreglo)(7 downto 0);
test <= multiplicando + arreglo;
arreglo <= test(7 downto 0);
end if;
--sal <= reverse_any_vector(sal)(7 downto 0);
--arreglo <= reverse_any_vector(arreglo)(7 downto 0);
sal <= sal(6 downto 0)&arreglo(0);
arreglo <= arreglo(6 downto 0) & '0';
end if;
I <= I + 1;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/func.vhd
|
4
|
6787
|
package func is
function sum(x, y, z : in integer) return integer;
function invalid(x : out integer) return integer; -- Error
type uenum is (A, B, C);
type uenum_vector is array (integer range <>) of uenum;
function resolved(v : uenum_vector) return uenum;
subtype enum is resolved uenum;
subtype enum_ab is resolved uenum range A to B;
function resolved2(v : uenum) return uenum;
subtype enum_bad1 is resolved2 uenum; -- Error
function resolved3(v : uenum; x : integer) return uenum;
subtype enum_bad2 is resolved3 uenum; -- Error
subtype enum_bad3 is uenum uenum; -- Error
function default(x : in uenum := 6) return uenum; -- Error
function foo return integer is -- Error
begin
return 4;
end function;
end package;
package body bad is -- Error
end package body;
package body func is
function sum(x, y, z : in integer) return integer is
begin
return x + y; -- OK
end function;
function test1(x : integer) return integer is
begin
return A; -- Wrong return type
end function;
function test2(x : out integer) return integer is -- Invalid mode
begin
return 0;
end function;
function test3(x : integer) return integer is
begin
null; -- Missing return statement
end function;
function foo(x, y, z : in integer) return integer;
function foo(x, y, z : in integer) return integer; -- Duplicate
function test4(x : uenum_vector) return uenum is
begin
return x(x'low);
end function;
function test5(x, y : uenum) return uenum is
type uenum2d is array (uenum, uenum) of uenum;
constant table : uenum2d :=
( ( A, A, A ),
( A, B, C ),
( A, C, B ) );
begin
return table(x, y);
end function;
function test6(x : uenum_vector) return uenum_vector is
variable tmp : uenum_vector(1 to x'length);
begin
for i in tmp'range loop
tmp(i) := A;
end loop;
return tmp;
end function;
function test7(x : uenum_vector) return uenum_vector is
subtype rtype is uenum_vector(x'length downto 0);
variable r : rtype;
begin
return r;
end function;
function test8(x : uenum) return uenum_vector is
begin
return test7((1 to 3 => x));
end function;
function default2(y : in integer := 6) return integer is
begin
return y * 2;
end function;
function test9 return integer is
begin
return default2;
end function;
function test10(k : in integer) return integer is
variable v : integer;
variable u : uenum;
begin
v := sum(x => 4, 1); -- Error
v := sum(1, x => 4, x => 4); -- Error
v := sum(1, y => k, z => 4); -- OK
u := resolved3(A, x => 4); -- OK
u := resolved3(x => 3, v => B); -- OK
return v;
end function;
function test11(constant c : in bit) return bit; -- OK
function test12(variable v : in bit) return bit; -- Error
type ft is file of bit;
function test13(file f : ft) return bit; -- OK
function test14(signal s : bit) return bit; -- OK
procedure modify(variable b : inout bit) is
begin
b := '1';
end procedure;
function test15(file f : ft) return bit is
variable b : bit;
begin
read(f, b); -- OK
return b;
end function;
function test16(x : in bit) return bit is
begin
modify(x); -- Error
return x;
end function;
impure function test17(x : in bit) return bit is
begin
if now = 10 ns then
return '1';
else
return '0';
end if;
end function;
function test18(x : in bit) return bit is
begin
return not test17(x); -- Error, test18 not impure
end function;
type int_ptr is access integer;
function test19(x : in int_ptr) return integer; -- Error
function recur(x : in integer) return integer is
begin
if x = 0 then
return 1;
else
return x * recur(x - 1);
end if;
end function;
function test20(x : integer := 5; y : real) return integer is
variable k : integer;
begin
k := test20(6.5); -- Error
k := test20(5); -- Error
k := test20(y => 7); -- Error
return k;
end function;
function test21a(x : string) return integer;
function test21a(x : bit_vector) return integer;
function test21 return integer is
begin
return test21a(';' & LF); -- OK
end function;
function test22a(x : integer) return integer is
begin
return x + 1;
end function;
function test22a(x : integer) return real is
begin
return real(x) + 1.0;
end function;
function test22 return integer is
begin
assert test22a(1) = 2;
assert test22a(1) = 2.0;
return 1;
end function;
impure function test23 return integer is
variable x : integer;
impure function sub(y : in integer) return integer is
begin
return x + y;
end function;
begin
x := 5;
return sub(2);
end function;
function test24f(x : integer; r : real := 1.0) return integer;
function test24f(y : integer; b : boolean := true) return integer;
function test24 return integer is
begin
return test24f(x => 1) + test24f(y => 2);
end function;
end package body;
package func2 is
procedure test25(constant x : integer);
end package;
package body func2 is
procedure test25(variable x : integer) is -- Error
begin
end procedure;
function test26(signal x : integer) return integer;
function test26(x : integer) return integer is -- Error
begin
return 1;
end function;
end package body;
package func3 is
end package;
package body func3 is
-- default class should be treated identically to constant class
-- (ie, this should not produce an error)
function issue182(bitv : bit_vector) return integer is
function nested_fun return integer is
begin
return bitv'length;
end function;
begin
return nested_fun;
end function;
function issue123(signal x : integer) return integer is
function nested return integer is
begin
return x + 1; -- Error
end function;
begin
return nested;
end function;
end package body;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/func13.vhd
|
5
|
885
|
entity func13 is
end entity;
architecture test of func13 is
signal five : integer := 5;
signal zero : integer := 0;
begin
process is
variable x : integer;
variable y : bit_vector(7 downto 0);
impure function add_to_x(y : integer) return integer is
impure function do_it return integer is
begin
report integer'image(x) & " + " & integer'image(y);
return x + y;
end function;
begin
return do_it;
end function;
impure function get_bit(n : integer) return bit is
begin
return y(n);
end function;
begin
x := 2;
assert add_to_x(five) = 7;
x := 3;
assert add_to_x(five) = 8;
y := X"00";
assert get_bit(zero) = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/cpu_unit/mblite/hw/core/decode.vhd
|
1
|
20338
|
----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_SUPPORT_SPR: boolean := true;
g_USE_PCMP : boolean := true;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
architecture arch of decode is
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
block_interrupt : std_logic;
end record;
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_o.int_ack <= r.int_ack;
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.inst_valid,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
v.int_ack := '0';
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
wb_dat_d <= mem_result;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
if decode_i.inst_valid = '0' then
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
-- not a hazard, just a nop
elsif (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
else
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
end if;
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if decode_i.interrupt_enable = '1' and decode_i.interrupt = '1' and reg.block_interrupt = '0' then
v_reg.interrupt := '1';
end if;
if decode_i.interrupt_enable = '0' then
v_reg.block_interrupt := '0';
end if;
end if;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := "00";
v.ctrl_ex.compare_op := '0';
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_ex.msr_op := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
if G_INTERRUPT = true and (reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.interrupt := '0';
v_reg.block_interrupt := '1'; -- because interrupt enable is cleared in exec, we block here any new interrupts until MSR_I bit is cleared.
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.int_ack := '1';
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110"; -- link register is r14
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.msr_op := MSR_CLR_I;
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA; -- will read 0 because reg_a = 0
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Pass modifier for CMP and CMPU
if (compare(opcode, "000101") = '1') then
v.ctrl_ex.compare_op := '1';
v.ctrl_ex.operation := instruction(1 downto 0);
end if;
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode(5 downto 2), "1000") = '1' then
-- OR, AND, XOR, ANDN
-- PCMPEQ, PCMPNE
if G_USE_PCMP and instruction(10) = '1' then -- Pattern Compare
v.ctrl_ex.alu_op := ALU_PEQ;
v.ctrl_ex.operation(0) := opcode(0);
else
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
end if;
if compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode(5 downto 2), "1010") = '1' then
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
if compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.delay := instruction(20);
-- Link: WRITE THE CURRENT PC TO REGISTER D. In the MEM stage, a multiplexer decides that PC is being written in case of a branch.
if instruction(18) = '1' then
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
end if;
if instruction(19) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.reg_a := (others => '0'); -- select register 0 to emulate 0.
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
elsif compare(opcode, "101101") = '1' then
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v.ctrl_ex.msr_op := MSR_SET_I;
end if;
v_reg.delay_interrupt := '1';
end if;
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.carry := CARRY_ZERO;
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := '1';
end if;
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
v.ctrl_ex.delay := '0';
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
v.ctrl_ex.alu_op := ALU_MUL;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
v.ctrl_ex.alu_op := ALU_BS;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_SUPPORT_SPR and opcode = "100101" then
if instruction(15 downto 14) = "11" then -- MTS, SPR[Sd] := Ra
v.ctrl_ex.msr_op := LOAD_MSR; -- Ra will be written to the status bits
elsif instruction(15 downto 14) = "10" then -- MFS, Rd := SPR[Sd]
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
else -- 00 (MSRSET/MSRCLR) and 01 -> illegal
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
v.ctrl_wrb.reg_write := '1';
if instruction(16)='0' then -- SET
v.ctrl_ex.msr_op := MSR_SET;
else -- CLR
v.ctrl_ex.msr_op := MSR_CLR;
end if;
end if;
else
-- UNKNOWN OPCODE
null;
end if;
rin <= v;
regin <= v_reg;
end process;
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= "00";
r.ctrl_ex.compare_op <= '0';
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
reg.block_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/elab21.vhd
|
4
|
997
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/mem_ctrl/vhdl_sim/fpga_mem_test_v5_tb.vhd
|
2
|
1679
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: fpga_mem_test_v5_tb
-- Date:2015-01-02
-- Author: Gideon
-- Description: Testbench for FPGA mem tester
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpga_mem_test_v5_tb is
end entity;
architecture arch of fpga_mem_test_v5_tb is
signal CLOCK_50 : std_logic := '0';
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
signal MOTOR_LEDn : std_logic;
signal DISK_ACTn : std_logic;
begin
CLOCK_50 <= not CLOCK_50 after 10 ns;
fpga: entity work.fpga_mem_test_v5
port map (
CLOCK_50 => CLOCK_50,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA,
SDRAM_DQ => SDRAM_DQ,
MOTOR_LEDn => MOTOR_LEDn,
DISK_ACTn => DISK_ACTn );
end arch;
|
gpl-3.0
|
fpgaddicted/5bit-shift-register-structural-
|
prescaler_clock.vhd
|
1
|
769
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prescaler is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end prescaler;
architecture Behavioral of prescaler is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 5000000 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 100000) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/alias3.vhd
|
5
|
763
|
entity alias3 is
end entity;
architecture test of alias3 is
type int_array is array (integer range <>) of integer;
function cut(x : int_array; low, high: integer) return int_array is
alias a : int_array(1 to x'length) is x;
begin
return a(low to high);
end function;
signal s : int_array(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable x : int_array(1 to 5) := (1, 2, 3, 4, 5);
variable y : int_array(4 downto 0) := (4, 3, 2, 1, 0);
alias sa : int_array(4 downto 0) is x;
begin
assert x(2 to 4) = (2, 3, 4);
assert sa(3 downto 1) = (2, 3, 4);
assert cut(x, 2, 3) = (2, 3);
assert cut(y, 1, 2) = (4, 3);
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/cart_slot/vhdl_source/old/action_logic.vhd
|
5
|
6483
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity action_logic is
generic (
rom_base : std_logic_vector(27 downto 0) := X"1040000";
ram_base : std_logic_vector(27 downto 0) := X"0052000" );
port (
clock : in std_logic;
reset : in std_logic;
RSTn_in : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
io_write : in std_logic;
io_addr : in std_logic_vector(8 downto 0);
io_data : in std_logic_vector(7 downto 0);
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
slot_addr : in std_logic_vector(15 downto 0);
mem_addr : out std_logic_vector(25 downto 0);
-- debug
cart_mode : out std_logic_vector(7 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end action_logic;
architecture gideon of action_logic is
signal reset_in : std_logic;
signal cart_ctrl : std_logic_vector(7 downto 0);
signal freeze_act_d : std_logic;
signal mode : std_logic_vector(2 downto 0);
signal cart_en : std_logic;
constant c_serve_rom : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io2 : std_logic_vector(0 to 7) := "10101111";
begin
unfreeze <= cart_ctrl(6);
serve_enable <= cart_en;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or not RSTn_in;
freeze_act_d <= freeze_act;
-- control register
if reset_in='1' or (freeze_act='1' and freeze_act_d='0') then -- either reset or freeze
cart_ctrl <= (others => '0');
elsif io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- IO1
cart_ctrl <= io_data;
end if;
-- Generate the cartridge mode
-- determine whether to serve io requests
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_io2 <= '0';
serve_rom <= '1';
else
game_n <= not mode(0);
exrom_n <= mode(1);
serve_io2 <= c_serve_io2(conv_integer(mode));
serve_rom <= c_serve_rom(conv_integer(mode));
end if;
if cart_kill='1' then
cart_ctrl(2) <= '1';
end if;
end if;
end process;
mode <= cart_ctrl(5) & cart_ctrl(1) & cart_ctrl(0);
cart_en <= not cart_ctrl(2);
CART_LEDn <= cart_ctrl(2);
irq_n <= not (freeze_trig or freeze_act);
nmi_n <= not (freeze_trig or freeze_act);
-- determine address
process(slot_addr, mode, cart_ctrl)
begin
allow_write <= '0';
if mode(2)='1' then
if slot_addr(13)='0' then
mem_addr <= ram_base(25 downto 13) & slot_addr(12 downto 0);
else
mem_addr <= rom_base(25 downto 15) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
end if;
if slot_addr(15 downto 13)="100" or slot_addr(15 downto 8)=X"DF" then
allow_write <= '1';
end if;
else
mem_addr <= rom_base(25 downto 15) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
end if;
end process;
cart_mode <= cart_ctrl;
serve_vic <= '0';
serve_io1 <= '0';
end gideon;
--Freeze:
--Always use ROM address, and respond to ROML/ROMH, but not to IO2n
--
--Non-freeze:
--
--Mode 0: Always use ROM address, let ROMLn and IO2n control the output
--Mode 1: Always use ROM address, let ROMLn (ROMhn?) but not IO2n control the output
--Mode 2: Always use ROM address, and let only IO2n control the output
--Mode 3: Always use ROM address, and let ROMLn / ROMHn, but not IO2n control the output
--
--Mode 4: Always use RAM address, and let ROMLn and IO2n control the output
--Mode 5: Use A13 to select between ROM/RAM (0=RAM, 1=ROM), let ROMLn/ROMHn and IO2n control the output (or write)
--Mode 6: Always use RAM address, let IO2n and ROMLn control the output
--Mode 7: Use A13 to select between ROM/RAM (0=RAM, 1=ROM), let ROMLn/ROMHn and IO2n control the output (or write)
--
--$0000-$1FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$2000-$3FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$4000-$5FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$6000-$7FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$8000-$9FFF: ROM --- 8K ROM|--- --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- ram 8K ROM|--- ram 16K ROM|--- ram ----- |--- ram UltiMax|
--$A000-$BFFF: --- --- 8K ROM|ROM --- 16K ROM|--- --- ----- |--- --- UltiMax|--- --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|
--$C000-$DFFF: --- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$E000-$FFFF: --- --- 8K ROM|--- --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |ROM --- UltiMax|
--
--$DF00-$DFFF: ROM --- 8K ROM|--- --- 16K ROM|ROM --- ----- |--- --- UltiMax|--- ram 8K ROM|--- ram 16K ROM|--- ram ----- |--- ram UltiMax|
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/nios_c5/nios/synthesis/nios_rst_controller_002.vhd
|
1
|
9037
|
-- nios_rst_controller_002.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_rst_controller_002 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_rst_controller_002;
architecture rtl of nios_rst_controller_002 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_002 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_rst_controller_002
|
gpl-3.0
|
chiggs/nvc
|
test/regress/issue122.vhd
|
5
|
732
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural := nested_function;
begin
result := bar;
end;
end package body;
-------------------------------------------------------------------------------
entity issue122 is
end entity;
use work.nested_function_bug.all;
architecture test of issue122 is
begin
process is
variable r : integer;
begin
proc(5, r);
assert r = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/elab14.vhd
|
5
|
1086
|
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
architecture test of elab14 is
signal a : bit_vector(1 downto 0);
signal b : bit_vector(5 downto 0);
signal c : bit_vector(5 downto 2);
signal d : bit_vector(3 downto 0);
begin
sub_i: entity work.sub
port map (
i(1 downto 0) => a,
i(7 downto 2) => b,
o(3 downto 0) => c,
o(7 downto 4) => d );
process is
begin
assert c = "0000";
assert d = "0000";
wait for 2 ns;
assert c = "1111";
assert d = "1111";
a <= "11";
wait for 2 ns;
assert c = "1100";
assert d = "1111";
b <= "011110";
wait for 2 ns;
assert c = "0100";
assert d = "1000";
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/zpu/vhdl_source/zpu_compare.vhd
|
5
|
2270
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- oper input can have the following values, producing the following results
-- 000 => false
-- 001 => a = b
-- 010 => false
-- 011 => a = b
-- 100 => a < b
-- 101 => a <= b
-- 110 => a < b (unsigned)
-- 111 => a <= b (unsigned)
entity zpu_compare is
port (
a : in unsigned(31 downto 0);
b : in unsigned(31 downto 0);
oper : in std_logic_vector(2 downto 0);
y : out boolean );
end zpu_compare;
architecture gideon of zpu_compare is
signal result : boolean;
signal equal : boolean;
signal ext_a : signed(32 downto 0);
signal ext_b : signed(32 downto 0);
begin
equal <= (a = b);
ext_a(32) <= not oper(1) and a(31); -- if oper(1) is 1, then we'll do an unsigned compare = signed compare with '0' in front.
ext_b(32) <= not oper(1) and b(31); -- if oper(1) is 0, when we'll do a signed compare = extended signed with sign bit.
ext_a(31 downto 0) <= signed(a);
ext_b(31 downto 0) <= signed(b);
result <= (ext_a < ext_b);
process(oper, result, equal)
variable r : boolean;
begin
r := false;
if oper(0)='1' then
r := r or equal;
end if;
if oper(2)='1' then
r := r or result;
end if;
y <= r;
end process;
end gideon;
-- constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6); -- 100100
-- constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6); -- 100101
-- constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6); -- 100110
-- constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6); -- 100111
-- Note, the mapping is such, that for the opcodes above, the lower three bits of the opcode can be fed directly
-- into the compare unit.
-- constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6); -- 101110
-- constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6); -- 101111
-- For these operations, the decoder must do extra work.
-- TODO: make a smarter mapping to support EQ and NEQ without external decoding.
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/altera/mem_io.vhd
|
1
|
16820
|
--------------------------------------------------------------------------------
-- Entity: mem_io
-- Date:2016-07-16
-- Author: Gideon
--
-- Description: All Altera specific I/O stuff for DDR(2)
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity mem_io is
generic (
g_data_width : natural := 4;
g_addr_cmd_width : natural := 8 );
port (
ref_clock : in std_logic;
ref_reset : in std_logic;
sys_clock : out std_logic;
sys_reset : out std_logic;
user_clock_1 : out std_logic := '0';
user_clock_2 : out std_logic := '0';
user_clock_3 : out std_logic := '0';
phasecounterselect : in std_logic_vector(2 downto 0);
phasestep : in std_logic;
phaseupdown : in std_logic;
phasedone : out std_logic;
mode : in std_logic_vector(1 downto 0) := "00";
addr_first : in std_logic_vector(g_addr_cmd_width-1 downto 0);
addr_second : in std_logic_vector(g_addr_cmd_width-1 downto 0);
wdata : in std_logic_vector(4*g_data_width-1 downto 0);
wdata_oe : in std_logic := '0';
rdata : out std_logic_vector(4*g_data_width-1 downto 0);
mem_clk_p : inout std_logic := 'Z';
mem_clk_n : inout std_logic := 'Z';
mem_addr : out std_logic_vector(g_addr_cmd_width-1 downto 0);
mem_dqs : inout std_logic := 'Z';
mem_dq : inout std_logic_vector(g_data_width-1 downto 0)
);
end entity;
architecture arch of mem_io is
signal sys_clock_pll : std_logic;
signal sys_clock_i : std_logic;
signal sys_reset_pipe : std_logic_vector(3 downto 0);
signal pll_locked : std_logic;
signal mem_sys_clock : std_logic;
signal mem_addr_clock : std_logic;
signal mem_write_clock : std_logic;
signal mem_read_clock : std_logic;
signal not_sys_clock : std_logic;
signal not_addr_clock : std_logic;
signal wdata_r : std_logic_vector(4*g_data_width-1 downto 0);
signal wdata_oe_r : std_logic;
signal wdata_oe_r2 : std_logic;
signal mode_r : std_logic_vector(1 downto 0);
signal wdata_half : std_logic_vector(2*g_data_width-1 downto 0);
signal wdata_mux : std_logic;
signal mux_reset : std_logic;
signal rdata_h : std_logic_vector(g_data_width-1 downto 0);
signal rdata_l : std_logic_vector(g_data_width-1 downto 0);
signal rdata_l1 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_l2 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_h1 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_h2 : std_logic_vector(g_data_width-1 downto 0);
signal rdata_32 : std_logic_vector(4*g_data_width-1 downto 0);
signal dqs_oe : std_logic;
signal dqs_in_h : std_logic;
signal dqs_in_l : std_logic;
signal dqs_in_h1 : std_logic;
signal dqs_in_l1 : std_logic;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
clk4_divide_by : NATURAL;
clk4_duty_cycle : NATURAL;
clk4_multiply_by : NATURAL;
clk4_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
vco_frequency_control : STRING;
vco_phase_shift_step : NATURAL;
width_clock : NATURAL;
width_phasecounterselect : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
phasecounterselect : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
phasestep : IN STD_LOGIC ;
phaseupdown : IN STD_LOGIC ;
scanclk : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC ;
phasedone : OUT STD_LOGIC
);
END COMPONENT;
begin
i_pll : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 4,
clk0_duty_cycle => 50,
clk0_multiply_by => 5,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 5,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "2000",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 5,
clk3_phase_shift => "3400",
clk4_divide_by => 4,
clk4_duty_cycle => 50,
clk4_multiply_by => 5,
clk4_phase_shift => "0",
compensate_clock => "CLK1",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_USED",
port_phasedone => "PORT_USED",
port_phasestep => "PORT_USED",
port_phaseupdown => "PORT_USED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_USED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_USED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
vco_frequency_control => "MANUAL_PHASE",
vco_phase_shift_step => 80,
width_clock => 5,
width_phasecounterselect => 3
)
port map (
areset => ref_reset,
inclk(1) => '0',
inclk(0) => ref_clock,
phasecounterselect => phasecounterselect,
phasestep => phasestep,
phaseupdown => phaseupdown,
scanclk => sys_clock_i,
clk(0) => sys_clock_pll,
clk(1) => mem_addr_clock,
clk(2) => mem_write_clock,
clk(3) => mem_read_clock,
clk(4) => mem_sys_clock,
locked => pll_locked,
phasedone => phasedone
);
sys_clock <= sys_clock_pll;
sys_clock_i <= sys_clock_pll;
process(sys_clock_i, pll_locked)
begin
if pll_locked = '0' then
sys_reset_pipe <= (others => '1');
elsif rising_edge(sys_clock_i) then
sys_reset_pipe <= '0' & sys_reset_pipe(sys_reset_pipe'high downto 1);
end if;
end process;
sys_reset <= sys_reset_pipe(0);
i_clk_p: altddio_bidir
generic map (
extend_oe_disable => "UNUSED",
implement_input_in_lcell => "UNUSED",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 1
) port map (
padio(0) => mem_clk_p,
outclock => mem_addr_clock,
inclock => mem_read_clock, -- was measure clock
oe => '1',
datain_h => "0",
datain_l => "1",
dataout_h => open,
dataout_l => open,
combout => open,
dqsundelayedout => open,
outclocken => '1',
sclr => '0',
sset => '0'
);
i_clk_n: altddio_bidir
generic map (
extend_oe_disable => "UNUSED",
implement_input_in_lcell => "UNUSED",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "UNUSED",
power_up_high => "OFF",
width => 1
) port map (
padio(0) => mem_clk_n,
outclock => mem_addr_clock,
inclock => mem_read_clock, -- was measure clock
oe => '1',
datain_h => "1",
datain_l => "0",
dataout_h => open,
dataout_l => open,
combout => open,
dqsundelayedout => open,
outclocken => '1',
sclr => '0',
sset => '0'
);
not_sys_clock <= not sys_clock_i;
i_addr: altddio_out
generic map (
extend_oe_disable => "UNUSED",
intended_device_family => "Cyclone IV E",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNUSED",
power_up_high => "ON",
width => mem_addr'length
) port map (
aset => sys_reset_pipe(0),
datain_h => addr_first,
datain_l => addr_second,
dataout => mem_addr,
oe => '1',
outclock => not_sys_clock,
outclocken => '1'
);
process(mem_write_clock)
begin
if rising_edge(mem_write_clock) then
wdata_mux <= not wdata_mux and not mux_reset;
end if;
if falling_edge(mem_write_clock) then
mux_reset <= sys_reset_pipe(0);
wdata_r <= wdata;
wdata_oe_r <= wdata_oe;
end if;
if rising_edge(mem_write_clock) then
wdata_oe_r2 <= wdata_oe_r;
end if;
end process;
wdata_half <= wdata_r(2*g_data_width-1 downto 0) when wdata_mux='0' else
wdata_r(4*g_data_width-1 downto 2*g_data_width);
i_data: altddio_bidir
generic map (
extend_oe_disable => "OFF",
implement_input_in_lcell => "UNUSED",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_type => "altddio_bidir",
oe_reg => "REGISTERED",
power_up_high => "OFF",
width => g_data_width
) port map (
padio => mem_dq,
outclock => mem_write_clock,
inclock => mem_read_clock,
oe => wdata_oe_r,
datain_h => wdata_half(g_data_width-1 downto 0),
datain_l => wdata_half(2*g_data_width-1 downto g_data_width),
dataout_h => rdata_h,
dataout_l => rdata_l,
outclocken => '1',
sclr => '0',
sset => '0'
);
dqs_oe <= wdata_oe or wdata_oe_r;
i_dqs: altddio_bidir
generic map (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
lpm_hint => "UNUSED",
lpm_type => "altddio_bidir",
invert_output => "OFF",
oe_reg => "REGISTERED",
power_up_high => "OFF",
width => 1
) port map (
-- aset => sys_reset_pipe(0),
datain_h(0) => wdata_oe_r,
datain_l(0) => '0',
padio(0) => mem_dqs,
oe => dqs_oe,
outclock => not_addr_clock,
outclocken => '1',
inclock => mem_read_clock,
dataout_h(0) => dqs_in_h,
dataout_l(0) => dqs_in_l,
sclr => '0',
sset => '0'
);
not_addr_clock <= not mem_addr_clock;
process(mem_read_clock)
begin
if rising_edge(mem_read_clock) then
rdata_h1 <= rdata_h;
rdata_l1 <= rdata_l;
rdata_h2 <= rdata_h1;
rdata_l2 <= rdata_l1;
dqs_in_h1 <= dqs_in_h;
dqs_in_l1 <= dqs_in_l;
end if;
end process;
process(mem_read_clock)
begin
if falling_edge(mem_read_clock) then
if dqs_in_h1 = '0' and dqs_in_l1 = '1' then
rdata_32 <= rdata_h & rdata_l & rdata_h1 & rdata_l1;
else
rdata_32 <= rdata_l & rdata_h1 & rdata_l1 & rdata_h2;
end if;
end if;
end process;
--
-- process(dqs_in_h1, dqs_in_l1, rdata_h, rdata_l, rdata_h1, rdata_l1, rdata_h2)
-- begin
-- if dqs_in_h1 = '0' and dqs_in_l1 = '1' then
-- rdata_32 <= rdata_h & rdata_l & rdata_h1 & rdata_l1;
-- else
-- rdata_32 <= rdata_l & rdata_h1 & rdata_l1 & rdata_h2;
-- end if;
-- end process;
-- process(mem_sys_clock)
-- begin
-- if rising_edge(mem_sys_clock) then
-- mode_r <= mode;
-- case mode_r is
-- when "00" =>
-- rdata <= rdata_r1 & rdata_r2;
-- when "01" =>
-- rdata <= rdata_f1 & rdata_f2;
-- when "10" =>
-- rdata <= rdata_r2 & rdata_r3;
-- when "11" =>
-- rdata <= rdata_f2 & rdata_f3;
-- when others =>
-- rdata <= (others => '0');
-- end case;
-- end if;
-- end process;
process(sys_clock_i)
begin
if rising_edge(sys_clock_i) then
rdata <= rdata_32;
end if;
end process;
end architecture;
|
gpl-3.0
|
fpgaddicted/5bit-shift-register-structural-
|
debounce.vhd
|
1
|
1785
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:54 04/11/2017
-- Design Name:
-- Module Name: debounce - logic
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 20); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_v6_tb.vhd
|
5
|
7362
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v6_tb is
end ext_mem_test_v6_tb;
architecture tb of ext_mem_test_v6_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp : t_mem_burst_16_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_v6
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => okay );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
|
gpl-3.0
|
chiggs/nvc
|
test/lower/issue167.vhd
|
5
|
417
|
package pkg is
type p1 is protected
end protected;
end package;
package body pkg is
type p1 is protected body
end protected body;
end package body;
entity e is
end entity;
use work.pkg.all;
architecture a of e is
type p2 is protected
end protected;
type p2 is protected body
end protected body;
shared variable t : p1;
shared variable s : p2;
begin
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v4.vhd
|
5
|
14070
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
entity harness_v4 is
end harness_v4;
architecture tb of harness_v4 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal LB_ADDR : std_logic_vector(14 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal MEM_WEn : std_logic;
signal MEM_OEn : std_logic;
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal sys_shifted : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
-- shared variable rom : h_mem_object;
-- shared variable bram : h_mem_object;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
begin
mut: entity work.ultimate_logic
generic map (
g_simulation => true )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- io bus for simulation
sim_io_req => io_req,
sim_io_resp => io_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_CLOCK => ULPI_CLOCK,
ULPI_RESET => ULPI_RESET,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Buttons
BUTTON => BUTTON );
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
sys_shifted <= transport sys_clock after 3 ns;
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_ulpi_phy: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 100000 )
port map (
clock => ULPI_CLOCK,
reset => ULPI_RESET,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
-- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome
-- process. It would work with a good model of the serial spi flash, but since it is not included in the public
-- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram:
load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"D400";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
-- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
-- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
-- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
-- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
-- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
-- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
-- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
-- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
-- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
-- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
-- constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
-- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
-- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
|
gpl-3.0
|
chiggs/nvc
|
test/parse/empty.vhd
|
12226531
|
0
|
gpl-3.0
|
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Register/Lab04/Lab04/ipcore_dir/VGA_BUFFER_RAM/example_design/VGA_BUFFER_RAM_exdes.vhd
|
8
|
5187
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY VGA_BUFFER_RAM_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END VGA_BUFFER_RAM_exdes;
ARCHITECTURE xilinx OF VGA_BUFFER_RAM_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT VGA_BUFFER_RAM IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : VGA_BUFFER_RAM
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/REG_CTL.vhd
|
8
|
2756
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:44 03/25/2016
-- Design Name:
-- Module Name: REG_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity REG_CTL is
Port ( CLK : in STD_LOGIC;
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OPC4 : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end REG_CTL;
architecture Dataflow of REG_CTL is
begin
with OPC select RD_EN <=
'1' when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
'0' when OTHERS;
with OPC4 select WR_EN <=
'1' when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001",
'0' when OTHERS;
end Dataflow;
--architecture Behavioral of REG_CTL is
--
--begin
-- process(CLK)
-- begin
-- if (rising_edge(CLK)) then
-- case OPC is
-- when "0000" => RD_EN <= '1';
-- when "0001" => RD_EN <= '1';
-- when "0010" => RD_EN <= '1';
-- when "0011" => RD_EN <= '1';
-- when "0100" => RD_EN <= '1';
-- when "0101" => RD_EN <= '1';
-- when "0110" => RD_EN <= '1';
-- when "0111" => RD_EN <= '1';
-- when "1000" => RD_EN <= '1';
-- when "1001" => RD_EN <= '1';
-- when others => RD_EN <= '0';
-- end case;
-- end if;
--
---- if (OPC = "1001") then
---- RD_EN <= '0';
---- else
---- RD_EN <= '1';
---- end if;
-- if (falling_edge(CLK)) then
-- case OPC4 is
-- when "0000" => WR_EN <= '1';
-- when "0001" => WR_EN <= '1';
-- when "0010" => WR_EN <= '1';
-- when "0011" => WR_EN <= '1';
-- when "0100" => WR_EN <= '1';
-- when "0101" => WR_EN <= '1';
-- when "0110" => WR_EN <= '1';
-- when "0111" => WR_EN <= '1';
-- when "1000" => WR_EN <= '1';
-- when "1010" => WR_EN <= '1';
-- when others => WR_EN <= '0';
-- end case;
--
---- if (OPC4 = "1010") then
---- WR_EN <= '0';
---- else
---- WR_EN <= '1';
---- end if;
-- end if;
-- end process;
--
--end Behavioral;
--
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ADR_LATCH.vhd
|
3
|
1246
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:14 04/23/2016
-- Design Name:
-- Module Name: ADR_LATCH - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADR_LATCH is
generic(PCWIDTH: integer := 5);
Port (CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADRIN : in STD_LOGIC_VECTOR (PCWIDTH-1 downto 0);
ADOUT : out STD_LOGIC_VECTOR (PCWIDTH-1 downto 0));
end ADR_LATCH;
architecture Behavioral of ADR_LATCH is
begin
process(CLK,RST)
begin
if RST = '1' then
ADOUT <= (OTHERS => '0');
elsif (CLK'Event and CLK = '1') then
ADOUT <= ADRIN;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/PipelineRegisters.vhd
|
9
|
1655
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PipelineRegisters is
generic(dataWidth:integer:=16);
Port ( Clk : in STD_LOGIC; -- Clock
Ena : in STD_LOGIC; -- Enable
Rst : in STD_LOGIC; -- Reset line
Din : in STD_LOGIC_VECTOR (dataWidth-1 downto 0); -- Data in
Dout : out STD_LOGIC_VECTOR (dataWidth-1 downto 0)); -- Data out
end PipelineRegisters;
architecture Behavioral of PipelineRegisters is
signal DataOutSignal : STD_LOGIC_VECTOR(dataWidth-1 DOWNTO 0) := (others=>'1'); -- Use a signal that always begins at 0 to ensure safe states
begin
BehavioralProcess: process(Clk, Rst)
begin
if(rising_edge(Clk) and Ena = '1') then
DataOutSignal <= Din; -- Read data in
end if;
if(falling_edge(Clk) and Ena = '1') then
Dout <= DataOutSignal; -- Write data out
end if;
if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out.
DataOutSignal <= (others=>'1'); -- Set data out to all zeroes
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Register/Lab04/PipelineRegisters.vhd
|
9
|
1655
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PipelineRegisters is
generic(dataWidth:integer:=16);
Port ( Clk : in STD_LOGIC; -- Clock
Ena : in STD_LOGIC; -- Enable
Rst : in STD_LOGIC; -- Reset line
Din : in STD_LOGIC_VECTOR (dataWidth-1 downto 0); -- Data in
Dout : out STD_LOGIC_VECTOR (dataWidth-1 downto 0)); -- Data out
end PipelineRegisters;
architecture Behavioral of PipelineRegisters is
signal DataOutSignal : STD_LOGIC_VECTOR(dataWidth-1 DOWNTO 0) := (others=>'1'); -- Use a signal that always begins at 0 to ensure safe states
begin
BehavioralProcess: process(Clk, Rst)
begin
if(rising_edge(Clk) and Ena = '1') then
DataOutSignal <= Din; -- Read data in
end if;
if(falling_edge(Clk) and Ena = '1') then
Dout <= DataOutSignal; -- Write data out
end if;
if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out.
DataOutSignal <= (others=>'1'); -- Set data out to all zeroes
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/ipcore_dir/VGA_BUFFER_RAM/example_design/VGA_BUFFER_RAM_prod.vhd
|
8
|
10573
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : VGA_BUFFER_RAM.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 20
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY VGA_BUFFER_RAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END VGA_BUFFER_RAM_prod;
ARCHITECTURE xilinx OF VGA_BUFFER_RAM_prod IS
COMPONENT VGA_BUFFER_RAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : VGA_BUFFER_RAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/REG_CTL.vhd
|
1
|
2790
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:44 03/25/2016
-- Design Name:
-- Module Name: REG_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity REG_CTL is
Port ( CLK : in STD_LOGIC;
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OPC4 : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end REG_CTL;
architecture Dataflow of REG_CTL is
begin
with OPC select RD_EN <=
'1' when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
'1' when OTHERS; -- always enable reading
with OPC4 select WR_EN <=
'1' when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1011",
'0' when OTHERS;
end Dataflow;
--architecture Behavioral of REG_CTL is
--
--begin
-- process(CLK)
-- begin
-- if (rising_edge(CLK)) then
-- case OPC is
-- when "0000" => RD_EN <= '1';
-- when "0001" => RD_EN <= '1';
-- when "0010" => RD_EN <= '1';
-- when "0011" => RD_EN <= '1';
-- when "0100" => RD_EN <= '1';
-- when "0101" => RD_EN <= '1';
-- when "0110" => RD_EN <= '1';
-- when "0111" => RD_EN <= '1';
-- when "1000" => RD_EN <= '1';
-- when "1001" => RD_EN <= '1';
-- when others => RD_EN <= '0';
-- end case;
-- end if;
--
---- if (OPC = "1001") then
---- RD_EN <= '0';
---- else
---- RD_EN <= '1';
---- end if;
-- if (falling_edge(CLK)) then
-- case OPC4 is
-- when "0000" => WR_EN <= '1';
-- when "0001" => WR_EN <= '1';
-- when "0010" => WR_EN <= '1';
-- when "0011" => WR_EN <= '1';
-- when "0100" => WR_EN <= '1';
-- when "0101" => WR_EN <= '1';
-- when "0110" => WR_EN <= '1';
-- when "0111" => WR_EN <= '1';
-- when "1000" => WR_EN <= '1';
-- when "1010" => WR_EN <= '1';
-- when others => WR_EN <= '0';
-- end case;
--
---- if (OPC4 = "1010") then
---- WR_EN <= '0';
---- else
---- WR_EN <= '1';
---- end if;
-- end if;
-- end process;
--
--end Behavioral;
--
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Shadow_Register/Lab04/Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/random.vhd
|
30
|
4220
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/ipcore_dir/DEBUG_RAM/simulation/random.vhd
|
30
|
4220
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/ipcore_dir/blk_mem_gen_v7_3/simulation/random.vhd
|
30
|
4220
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
JumpUnit/ECE368_Project_Lab1_Team5/ipcore_dir/Instr_Mem/example_design/Instr_Mem_exdes.vhd
|
6
|
4617
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Instr_Mem_exdes;
ARCHITECTURE xilinx OF Instr_Mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instr_Mem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Instr_Mem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/ProgramCounter/ProgramCounter/ipcore_dir/Instr_Mem/example_design/Instr_Mem_exdes.vhd
|
6
|
4617
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instr_Mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Instr_Mem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Instr_Mem_exdes;
ARCHITECTURE xilinx OF Instr_Mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Instr_Mem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Instr_Mem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/DATA_CTL.vhd
|
9
|
1373
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/mux8to1.vhd
|
12
|
1166
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Mux 8 to 1
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Select one bit from a byte
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX8to1 is
Port ( SEL : in STD_LOGIC_VECTOR (2 downto 0);
DATA : in STD_LOGIC_VECTOR (7 downto 0);
OUTPUT : out STD_LOGIC);
end MUX8to1;
architecture Behavioral of MUX8to1 is
signal SEL1 : STD_LOGIC_VECTOR (2 downto 0);
begin
SEL1<=SEL-2;
with SEL1 SELect
OUTPUT<= DATA(7) when "000" ,
DATA(6) when "001" ,
DATA(5) when "010" ,
DATA(4) when "011" ,
DATA(3) when "100" ,
DATA(2) when "101" ,
DATA(1) when "110" ,
DATA(0) when "111" ,
'0' when others;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
JumpUnit/ECE368_Project_Lab1_Team5/TopLevel_tb.vhd
|
4
|
3502
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:39 03/31/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/TopLevel_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ProjLab01
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TopLevel_tb IS
END TopLevel_tb;
ARCHITECTURE behavior OF TopLevel_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ProjLab01
PORT(
CLK : IN std_logic;
RST : IN std_logic;
--instruction : IN std_logic_vector(15 downto 0);
ALU_OUT : OUT std_logic_vector(15 downto 0);
DST_ADR : OUT std_logic_vector(15 downto 0);
STORE_DATA : OUT std_logic_vector(15 downto 0);
CCR : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--signal instruction : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal ALU_OUT : std_logic_vector(15 downto 0);
signal DST_ADR : std_logic_vector(15 downto 0);
signal STORE_DATA : std_logic_vector(15 downto 0);
signal CCR : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 1 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ProjLab01 PORT MAP (
CLK => CLK,
RST => RST,
-- instruction => instruction,
ALU_OUT => ALU_OUT,
DST_ADR => DST_ADR,
STORE_DATA => STORE_DATA,
CCR => CCR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
RST <= '1';
wait for CLK_period*2;
wait for CLK_period/2;
RST <= '0';
wait for CLK_period*10;
-- instruction <= X"5002";
--
-- wait for CLK_period;
--
-- instruction <= X"5101";
--
-- wait for CLK_period;
--
-- instruction <= X"A10F";
--
-- wait for CLK_period;
--
-- instruction <= X"950F";
--
-- wait for CLK_period;
--
-- instruction <= X"0050";
--
-- wait for CLK_period;
--
-- instruction <= X"2010";
--
-- wait for CLK_period;
--
-- instruction <= X"3010";
--
-- wait for CLK_period;
--
-- instruction <= X"0010";
--
-- wait for CLK_period;
--
-- instruction <= X"4A10";
--
-- wait for CLK_period;
--
-- instruction <= X"7A03";
wait for CLK_period;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
DataTest/DataContentionTest/DC_CTL.vhd
|
1
|
2331
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
-- RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
-- OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0));
-- OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Combinational of DC_CTL is
signal OP1 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
OP1_SEL <= OP1;
-- with OPC select OP1_SEL <=
-- "00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
-- OP1 when OTHERS;
-- with OPC select OP2_SEL <=
-- "00" when "0101" | "0110" | "0111" | "1000" | "1001" | "1010",
-- OP2 when OTHERS;
--
-- OP1 <= "00";
process(RA, RA0, RA1, RA2)
begin
-- if(CLK'event) then
if (RA = RA0) then
OP1 <= "01";
elsif (RA = RA1) then
OP1 <= "10";
elsif (RA = RA2) then
OP1 <= "11";
else
OP1 <= "00";
end if;
-- if (RB = RA0) then
-- OP2 <= "01";
-- elsif (RB = RA1) then
-- OP2 <= "10";
-- elsif (RB = RA2) then
-- OP2 <= "11";
-- else
-- OP2 <= "00";
-- end if;
-- end if;
-- OP1_SEL <= OP1;
end process;
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
Lab04/ipcore_dir/VGA_BUFFER_RAM.vhd
|
8
|
5991
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file VGA_BUFFER_RAM.vhd when simulating
-- the core, VGA_BUFFER_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY VGA_BUFFER_RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END VGA_BUFFER_RAM;
ARCHITECTURE VGA_BUFFER_RAM_a OF VGA_BUFFER_RAM IS
-- synthesis translate_off
COMPONENT wrapped_VGA_BUFFER_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_VGA_BUFFER_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "20",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "VGA_BUFFER_RAM.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_VGA_BUFFER_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END VGA_BUFFER_RAM_a;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/HardwareTestPart1/Lab04/alu_mux.vhd
|
12
|
2229
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/alu_mux.vhd
|
12
|
2229
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/alu_logic_unit.vhd
|
12
|
1560
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined[old]/DC_CTL.vhd
|
1
|
2240
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:59 03/25/2016
-- Design Name:
-- Module Name: DC_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DC_CTL is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (3 downto 0);
RB : in STD_LOGIC_VECTOR (3 downto 0);
RA0 : in STD_LOGIC_VECTOR (3 downto 0);
RA1 : in STD_LOGIC_VECTOR (3 downto 0);
RA2 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB0 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB1 : in STD_LOGIC_VECTOR (3 downto 0);
-- RB2 : in STD_LOGIC_VECTOR (3 downto 0);
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OP1_SEL : out STD_LOGIC_VECTOR (1 downto 0);
OP2_SEL : out STD_LOGIC_VECTOR (1 downto 0));
end DC_CTL;
architecture Mixed of DC_CTL is
signal OP1, OP2 : STD_LOGIC_VECTOR (1 downto 0) := (OTHERS => '0');
begin
process(RA, RB, RA0, RA1, RA2)
begin
-- if (rising_edge(CLK)) then
if (RA = RA0) then
OP1 <= "01";
-- OP1_SEL <= OP1;
elsif (RA = RA1) then
OP1 <= "10";
-- OP1_SEL <= OP1;
elsif (RA = RA2) then
OP1 <= "11";
-- OP1_SEL <= OP1;
else
OP1 <= "00";
-- OP1_SEL <= OP1;
end if;
-- OP1_SEL <= OP1;
if (RB = RA0) then
OP2 <= "01";
elsif (RB = RA1) then
OP2 <= "10";
elsif (RB = RA2) then
OP2 <= "11";
else
OP2 <= "00";
end if;
-- end if;
end process;
OP1_SEL <= OP1;
with OPC select OP2_SEL <=
OP2 when "0000" | "0001" | "0010" | "0011" | "0100",
"00" when OTHERS;
end Mixed;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/HardwareDebugDemo/button_controller.vhd
|
2
|
1582
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Switch Controller
-- Maintain input from the four buttons on Nexys
-- Built in debouncer for buttons
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity buttoncontrol is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end buttoncontrol;
architecture Structural of buttoncontrol is
begin
----- Structural Components: -----
BTN_0: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => BTN(0),
OUTPUT => LED(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => BTN(1),
OUTPUT => LED(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => BTN(2),
OUTPUT => LED(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
EN => EN,
INPUT => BTN(3),
OUTPUT => LED(3));
----- End Structural Components -----
end Structural;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/ipcore_dir/DEBUG_RAM/simulation/bmg_stim_gen.vhd
|
1
|
12278
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SDP Configuration
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(51 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(51 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL DO_READ_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0');
SIGNAL PORTA_WR : STD_LOGIC:='0';
SIGNAL COUNT : INTEGER :=0;
SIGNAL INCR_WR_CNT : STD_LOGIC:='0';
SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD : STD_LOGIC:='0';
SIGNAL COUNT_RD : INTEGER :=0;
SIGNAL INCR_RD_CNT : STD_LOGIC:='0';
SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTA_WR_L1 :STD_LOGIC := '0';
SIGNAL PORTA_WR_L2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R2 :STD_LOGIC := '0';
SIGNAL PORTB_RD_R1 :STD_LOGIC := '0';
SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0';
SIGNAL PORTB_RD_L1 : STD_LOGIC := '0';
SIGNAL PORTB_RD_L2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R2 : STD_LOGIC := '0';
SIGNAL PORTA_WR_R1 : STD_LOGIC := '0';
CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8;
CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((4 <= 4),WR_RD_DEEP_COUNT,
((52/52)*WR_RD_DEEP_COUNT));
CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((4 <= 4),WR_RD_DEEP_COUNT,
((52/52)*WR_RD_DEEP_COUNT));
BEGIN
ADDRA <= WRITE_ADDR(3 DOWNTO 0) ;
DINA <= DINA_INT ;
ADDRB <= READ_ADDR(3 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0');
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 52,
DOUT_WIDTH => 52 ,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
PORTA_WR_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR<='1';
ELSE
PORTA_WR<=PORTB_RD_COMPLETE;
END IF;
END IF;
END PROCESS;
PORTB_RD_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_RD<='0';
ELSE
PORTB_RD<=PORTA_WR_L2;
END IF;
END IF;
END PROCESS;
PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
ELSIF(PORTB_RD_COMPLETE='1') THEN
LATCH_PORTB_RD_COMPLETE <='1';
ELSIF(PORTA_WR_HAPPENED='1') THEN
LATCH_PORTB_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_L1 <='0';
PORTB_RD_L2 <='0';
ELSE
PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE;
PORTB_RD_L2 <= PORTB_RD_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_R1 <='0';
PORTA_WR_R2 <='0';
ELSE
PORTA_WR_R1 <= PORTA_WR;
PORTA_WR_R2 <= PORTA_WR_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_HAPPENED <= PORTA_WR_R2;
PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_COMPLETE<='0';
ELSIF(PORTA_WR_COMPLETE='1') THEN
LATCH_PORTA_WR_COMPLETE <='1';
--ELSIF(PORTB_RD_HAPPENED='1') THEN
ELSE
LATCH_PORTA_WR_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_L1 <='0';
PORTA_WR_L2 <='0';
ELSE
PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE;
PORTA_WR_L2 <= PORTA_WR_L1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_RD_R1 <='0';
PORTB_RD_R2 <='0';
ELSE
PORTB_RD_R1 <= PORTB_RD;
PORTB_RD_R2 <= PORTB_RD_R1;
END IF;
END IF;
END PROCESS;
PORTB_RD_HAPPENED <= PORTB_RD_R2;
PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0';
start_rd_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
incr_rd_cnt <= '0';
elsif(portb_rd ='1') then
incr_rd_cnt <='1';
elsif(portb_rd_complete='1') then
incr_rd_cnt <='0';
end if;
end if;
end process;
RD_COUNTER: process(clkb)
begin
if(rising_edge(clkb)) then
if(tb_rst='1') then
count_rd <= 0;
elsif(incr_rd_cnt='1') then
count_rd<=count_rd+1;
end if;
--if(count_rd=(wr_rd_deep_count)) then
if(count_rd=(RD_DEEP_COUNT)) then
count_rd<=0;
end if;
end if;
end process;
DO_READ<='1' when (count_rd <RD_DEEP_COUNT and incr_rd_cnt='1') else '0';
PORTA_WR_COMPLETE <= '1' when (count=WR_DEEP_COUNT) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
incr_wr_cnt <= '0';
elsif(porta_wr ='1') then
incr_wr_cnt <='1';
elsif(porta_wr_complete='1') then
incr_wr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(tb_rst='1') then
count <= 0;
elsif(incr_wr_cnt='1') then
count<=count+1;
end if;
if(count=(WR_DEEP_COUNT)) then
count<=0;
end if;
end if;
end process;
DO_WRITE<='1' when (count <WR_DEEP_COUNT and incr_wr_cnt='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 5 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLKB,
RST => TB_RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLKB,
RST =>TB_RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
REGCE_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_R <= '0';
ELSE
DO_READ_R <= DO_READ;
END IF;
END IF;
END PROCESS;
WEA(0) <= DO_WRITE ;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/NewCombined/programCounter.vhd
|
3
|
1104
|
-- Company: Team 5
-- Engineer:
--
-- Create Date: 15:15:57 03/11/2016
-- Design Name:
-- Module Name: programCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity programCounter is
generic(PCWIDTH:integer:=16);
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
RST : in STD_LOGIC;
INSADR : out STD_LOGIC_VECTOR (PCWIDTH-1 downto 0));
end programCounter;
architecture Behavioral of programCounter is
signal COUNTER : std_logic_vector(PCWIDTH-1 downto 0) := (OTHERS => '0');
begin
INSADR <= COUNTER;
process(CLK, RST)
begin
if(RST = '1')then
COUNTER <= (OTHERS => '0');
elsif(CLK'event and CLK = '1')then
if(EN = '1')then
COUNTER <= unsigned(COUNTER) + 1;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/ipcore_dir/instruction_memory/simulation/random.vhd
|
101
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/Combined/Shadow_IMM_Add.vhd
|
2
|
1309
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:06:07 04/13/2016
-- Design Name:
-- Module Name: Shadow_IMM_Add - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; --Using Unsigned for output
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Shadow_IMM_Add is
Port ( SHADOW : in STD_LOGIC_VECTOR (15 downto 0);
IMM : in STD_LOGIC_VECTOR (3 downto 0);
EX_ADDR : out STD_LOGIC_VECTOR (13 downto 0));
end Shadow_IMM_Add;
architecture Behavioral of Shadow_IMM_Add is
signal RESULT : STD_LOGIC_VECTOR(13 downto 0) := (OTHERS => '0');
begin
RESULT <= SHADOW(13 downto 0) + IMM;
EX_ADDR <= RESULT;
end Behavioral;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab1/VGA_Debug_Unit/Lab04/ipcore_dir/VGA_BUFFER_RAM/simulation/addr_gen.vhd
|
30
|
4526
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
FlatTargetInk/UMD_RISC-16G5
|
ProjectLab2/NewCombined/ipcore_dir/blk_mem_gen_v7_3/simulation/addr_gen.vhd
|
30
|
4526
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
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