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GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/iface.vhd
|
1
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24212
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: iface
-- File: iface.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Package with type declarations for module interconnections
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
package iface is
subtype clk_type is std_logic;
------------------------------------------------------------------------------
-- Add I/Os for custom peripherals in the records below
------------------------------------------------------------------------------
-- peripheral inputs
type io_in_type is record
piol : std_logic_vector(15 downto 0); -- I/O port inputs
pci_arb_req_n : std_logic_vector(0 to 3);
end record;
-- peripheral outputs
type io_out_type is record
piol : std_logic_vector(15 downto 0); -- I/O port outputs
piodir : std_logic_vector(15 downto 0); -- I/O port direction
errorn : std_logic; -- CPU in error mode
wdog : std_logic; -- watchdog output
pci_arb_gnt_n : std_logic_vector(0 to 3);
end record;
------------------------------------------------------------------------------
-- IU register file signals
type rf_in_type is record
rd1addr : std_logic_vector(RABITS-1 downto 0); -- read address 1
rd2addr : std_logic_vector(RABITS-1 downto 0); -- read address 2
wraddr : std_logic_vector(RABITS-1 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- co-processor register file signals
type rf_cp_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_cp_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- instruction cache diagnostic access inputs
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_logic;
read : std_logic;
tag : std_logic;
flush : std_logic;
end record;
-- data cache controller inputs
type dcache_in_type is record
asi : std_logic_vector(7 downto 0); -- ASI for load/store
maddress : std_logic_vector(31 downto 0); -- memory stage address
eaddress : std_logic_vector(31 downto 0); -- execute stage address
edata : std_logic_vector(31 downto 0); -- execute stage data
size : std_logic_vector(1 downto 0);
signed : std_logic;
enaddr : std_logic;
eenaddr : std_logic;
nullify : std_logic;
lock : std_logic;
read : std_logic;
write : std_logic;
flush : std_logic;
dsuen : std_logic;
end record;
-- data cache controller outputs
type dcache_out_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
mexc : std_logic; -- memory exception
hold : std_logic;
mds : std_logic;
werr : std_logic; -- memory write error
icdiag : icdiag_in_type;
dsudata : std_logic_vector(31 downto 0);
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto PCLOW); -- raw address (npc)
fpc : std_logic_vector(31 downto PCLOW); -- latched address (fpc)
dpc : std_logic_vector(31 downto PCLOW); -- latched address (dpc)
rbranch : std_logic; -- Instruction branch
fbranch : std_logic; -- Instruction branch
nullify : std_logic; -- instruction nullify
su : std_logic; -- super-user
flush : std_logic; -- flush icache
end record;
type icache_out_type is record
data : std_logic_vector(31 downto 0);
exception : std_logic;
hold : std_logic;
flush : std_logic; -- flush in progress
diagrdy : std_logic; -- diagnostic access ready
diagdata : std_logic_vector(31 downto 0); -- diagnostic data
mds : std_logic; -- memory data strobe
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_logic; -- burst request
req : std_logic; -- memory cycle request
su : std_logic; -- supervisor address space
flush : std_logic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
burst : std_logic; -- memory burst enable
ics : std_logic_vector(1 downto 0); -- icache state (from CCR)
cache : std_logic; -- cacheable data
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
flush : std_logic; -- flush in progress
lock : std_logic;
su : std_logic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
dcs : std_logic_vector(1 downto 0);
iflush : std_logic; -- flush icache (from CCR)
dflush : std_logic; -- flush dcache (from CCR)
cache : std_logic; -- cacheable data
dsnoop : std_logic; -- snoop enable
ba : std_logic; -- bus active (used for snooping)
bg : std_logic; -- bus grant (used for snooping)
end record;
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
end record;
type memory_out_type is record
address : std_logic_vector(27 downto 0);
data : std_logic_vector(31 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
iosn : std_logic;
romsn : std_logic_vector(1 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
read : std_logic;
end record;
type pio_in_type is record
piol : std_logic_vector(15 downto 0);
pioh : std_logic_vector(15 downto 0);
end record;
type pio_out_type is record
irq : std_logic_vector(3 downto 0);
piol : std_logic_vector(31 downto 0);
piodir : std_logic_vector(17 downto 0);
io8lsb : std_logic_vector(7 downto 0);
rxd : std_logic_vector(1 downto 0);
ctsn : std_logic_vector(1 downto 0);
wrio : std_logic;
end record;
type wprot_out_type is record
wprothit : std_logic;
end record;
type ahbstat_out_type is record
ahberr : std_logic;
end record;
type mctrl_out_type is record
pioh : std_logic_vector(15 downto 0);
end record;
type itram_in_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE - 1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type itram_out_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE -1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
end record;
type idram_in_type is record
address : std_logic_vector((IOFFSET_BITS + ILINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type idram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type dtram_in_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE - 1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type dtram_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
end record;
type dtramsn_in_type is record
enable : std_logic;
write : std_logic;
address : std_logic_vector((DOFFSET_BITS-1) downto 0);
end record;
type dtramsn_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
end record;
type ddram_in_type is record
address : std_logic_vector((DOFFSET_BITS + DLINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type ddram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type icram_in_type is record
itramin : itram_in_type;
idramin : idram_in_type;
end record;
type icram_out_type is record
itramout : itram_out_type;
idramout : idram_out_type;
end record;
type dcram_in_type is record
dtramin : dtram_in_type;
ddramin : ddram_in_type;
dtraminsn : dtramsn_in_type;
end record;
type dcram_out_type is record
dtramout : dtram_out_type;
ddramout : ddram_out_type;
dtramoutsn : dtramsn_out_type;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramout : icram_out_type;
dcramout : dcram_out_type;
end record;
type irq_in_type is record
irq : std_logic_vector(15 downto 1);
intack : std_logic;
irl : std_logic_vector(3 downto 0);
end record;
type irq_out_type is record
irl : std_logic_vector(3 downto 0);
end record;
type irq2_in_type is record
irq : std_logic_vector(31 downto 0);
end record;
type irq2_out_type is record
irq : std_logic;
end record;
type timers_out_type is record
irq : std_logic_vector(1 downto 0);
tick : std_logic;
wdog : std_logic;
end record;
type uart_in_type is record
rxd : std_logic;
ctsn : std_logic;
scaler : std_logic_vector(7 downto 0);
end record;
type uart_out_type is record
rxen : std_logic;
txen : std_logic;
flow : std_logic;
irq : std_logic;
rtsn : std_logic;
txd : std_logic;
end record;
type clkgen_in_type is record
iholdn : std_logic; -- Instruction hold
imdsn : std_logic; -- Instruction memory data strobe
dholdn : std_logic; -- Data hold
dmdsn : std_logic; -- Data memory data strobe
fpuholdn : std_logic; -- FPU/CP busy
end record;
type clkgen_out_type is record
clk : clk_type; -- Common clock
clkn : clk_type; -- inverted clock
iuclk : clk_type; -- Processor clock
dclk : clk_type; -- Data latch clock
iclk : clk_type; -- Instruction latch clock
pciclk : clk_type; -- PCI config-block clock
holdn : std_logic; -- Instruction latch clock
end record;
-- iu pipeline control type (defined here to be visible to debug and coprocessor)
type pipeline_control_type is record
inst : std_logic_vector(31 downto 0); -- instruction word
pc : std_logic_vector(31 downto PCLOW); -- program counter
annul : std_logic; -- instruction annul
cnt : std_logic_vector(1 downto 0); -- cycle number (multi-cycle inst)
ld : std_logic; -- load cycle
pv : std_logic; -- PC valid
rett : std_logic; -- RETT indicator
trap : std_logic; -- trap pending flag
tt : std_logic_vector(5 downto 0); -- trap type
rd : std_logic_vector(RABITS-1 downto 0); -- destination register address
end record;
-- Stucture for FPU/CP control
type cp_in_type is record
flush : std_logic; -- pipeline flush
exack : std_logic; -- CP exception acknowledge
dannul : std_logic; -- decode stage annul
dtrap : std_logic; -- decode stage trap
dcnt : std_logic_vector(1 downto 0); -- decode stage cycle counter
dinst : std_logic_vector(31 downto 0); -- decode stage instruction
ex : pipeline_control_type; -- iu pipeline ctrl (ex)
me : pipeline_control_type; -- iu pipeline ctrl (me)
wr : pipeline_control_type; -- iu pipeline ctrl (wr)
lddata : std_logic_vector(31 downto 0); -- load data
end record;
type cp_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- CP exception
cc : std_logic_vector(1 downto 0); -- CP condition codes
ccv : std_logic; -- CP condition codes valid
holdn : std_logic; -- CP pipeline hold
ldlock : std_logic; -- CP load/store interlock
end record;
-- iu debug port
type iu_debug_in_type is record
dsuen : std_logic; -- DSU enable
dbreak : std_logic; -- debug break-in
btrapa : std_logic; -- break on IU trap
btrape : std_logic; -- break on IU trap
berror : std_logic; -- break on IU error mode
bwatch : std_logic; -- break on IU watchpoint
bsoft : std_logic; -- break on software breakpoint (TA 1)
rerror : std_logic; -- reset processor error mode
step : std_logic; -- single step
denable : std_logic; -- diagnostic register access enable
dwrite : std_logic; -- read/write
daddr : std_logic_vector(20 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_debug_out_type is record
clk : std_logic;
rst : std_logic;
holdn : std_logic;
ex : pipeline_control_type;
me : pipeline_control_type;
wr : pipeline_control_type;
write_reg : std_logic;
mresult : std_logic_vector(31 downto 0);
result : std_logic_vector(31 downto 0);
trap : std_logic;
error : std_logic;
dmode : std_logic;
dmode2 : std_logic;
vdmode : std_logic;
dbreak : std_logic;
tt : std_logic_vector(7 downto 0);
psrtt : std_logic_vector(7 downto 0);
psrpil : std_logic_vector(3 downto 0);
diagrdy : std_logic;
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_in_type is record
irl : std_logic_vector(3 downto 0); -- interrupt request level
debug : iu_debug_in_type;
end record;
type iu_out_type is record
error : std_logic;
intack : std_logic;
irqvec : std_logic_vector(3 downto 0);
ipend : std_logic;
debug : iu_debug_out_type;
end record;
-- Meiko FPU interface
type fpu_in_type is record
FpInst : std_logic_vector(9 downto 0);
FpOp : std_logic;
FpLd : std_logic;
Reset : std_logic;
fprf_dout1 : std_logic_vector(63 downto 0);
fprf_dout2 : std_logic_vector(63 downto 0);
RoundingMode : std_logic_vector(1 downto 0);
ss_scan_mode : std_logic;
fp_ctl_scan_in : std_logic;
fpuholdn : std_logic;
end record;
type fpu_out_type is record
FpBusy : std_logic;
FracResult : std_logic_vector(54 downto 3);
ExpResult : std_logic_vector(10 downto 0);
SignResult : std_logic;
SNnotDB : std_logic;
Excep : std_logic_vector(5 downto 0);
ConditionCodes : std_logic_vector(1 downto 0);
fp_ctl_scan_out : std_logic;
end record;
type cp_unit_in_type is record -- coprocessor execution unit input
op1 : std_logic_vector (63 downto 0); -- operand 1
op2 : std_logic_vector (63 downto 0); -- operand 2
opcode : std_logic_vector (9 downto 0); -- opcode
start : std_logic; -- start
load : std_logic; -- load operands
flush : std_logic; -- cancel operation
end record;
type cp_unit_out_type is record -- coprocessor execution unit output
res : std_logic_vector (63 downto 0); -- result
cc : std_logic_vector (1 downto 0); -- condition codes
exc : std_logic_vector (5 downto 0); -- exception
busy : std_logic; -- eu busy
end record;
type rst_type is record
syncrst : std_logic; -- synchronous reset
rawrst : std_logic; -- asynchronous reset
end record;
-- pci_[in|out]_type groups all EXTERNAL pci ports in unidirectional form
-- as well as the required enable signals for the pads
type pci_in_type is record
pci_rst_in_n : std_logic;
pci_clk_in : std_logic;
pci_gnt_in_n : std_logic;
pci_idsel_in : std_logic;
pci_adin : std_logic_vector(31 downto 0);
pci_cbein_n : std_logic_vector(3 downto 0);
pci_frame_in_n : std_logic;
pci_irdy_in_n : std_logic;
pci_trdy_in_n : std_logic;
pci_devsel_in_n : std_logic;
pci_stop_in_n : std_logic;
pci_lock_in_n : std_logic;
pci_perr_in_n : std_logic;
pci_serr_in_n : std_logic;
pci_par_in : std_logic;
pci_host : std_logic;
pci_66 : std_logic;
pme_status : std_logic;
end record;
type pci_out_type is record
pci_aden_n : std_logic_vector(31 downto 0);
pci_cbe0_en_n : std_logic;
pci_cbe1_en_n : std_logic;
pci_cbe2_en_n : std_logic;
pci_cbe3_en_n : std_logic;
pci_frame_en_n : std_logic;
pci_irdy_en_n : std_logic;
pci_ctrl_en_n : std_logic;
pci_perr_en_n : std_logic;
pci_par_en_n : std_logic;
pci_req_en_n : std_logic;
pci_lock_en_n : std_logic;
pci_serr_en_n : std_logic;
pci_int_en_n : std_logic;
pci_req_out_n : std_logic;
pci_adout : std_logic_vector(31 downto 0);
pci_cbeout_n : std_logic_vector(3 downto 0);
pci_frame_out_n : std_logic;
pci_irdy_out_n : std_logic;
pci_trdy_out_n : std_logic;
pci_devsel_out_n : std_logic;
pci_stop_out_n : std_logic;
pci_perr_out_n : std_logic;
pci_serr_out_n : std_logic;
pci_par_out : std_logic;
pci_lock_out_n : std_logic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_logic;
pme_clear : std_logic;
pci_int_out_n : std_logic;
end record;
type div_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_logic;
burst : std_logic;
write : std_logic;
size : std_logic_vector(1 downto 0);
end record;
type ahb_dma_out_type is record
start : std_logic;
active : std_logic;
ready : std_logic;
retry : std_logic;
mexc : std_logic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
type actpci_be_in_type is record
mem_ad_int : std_logic_vector(31 downto 0);
mem_data : std_logic_vector(31 downto 0);
dp_done : std_logic;
dp_start : std_logic;
rd_be_now : std_logic;
rd_cyc : std_logic;
wr_be_now : std_logic_vector(3 downto 0);
wr_cyc : std_logic;
bar0_mem_cyc : std_logic;
busy : std_logic_vector(3 downto 0);
master_active : std_logic;
be_gnt : std_logic;
end record;
type actpci_be_out_type is record
rd_be_rdy : std_logic;
wr_be_rdy : std_logic;
error : std_logic;
busy : std_logic;
mem_data : std_logic_vector(31 downto 0);
cs_controln : std_logic;
rd_controln : std_logic;
wr_controln : std_logic;
control_add : std_logic_vector(1 downto 0);
ext_intn : std_logic;
be_req : std_logic;
end record;
type dsu_in_type is record
dsuen : std_logic;
dsubre : std_logic;
end record;
type dsu_out_type is record
dsuact : std_logic;
ntrace : std_logic;
freezetime : std_logic;
lresp : std_logic;
dresp : std_logic;
dsuen : std_logic;
dsubre : std_logic;
end record;
type dcom_in_type is record
dsurx : std_logic;
end record;
type dcom_out_type is record
dsutx : std_logic;
end record;
type dsuif_in_type is record
dsui : dsu_in_type;
dcomi : dcom_in_type;
end record;
type dsuif_out_type is record
dsuo : dsu_out_type;
dcomo : dcom_out_type;
end record;
type dcom_uart_in_type is record
rxd : std_logic;
read : std_logic;
write : std_logic;
data : std_logic_vector(7 downto 0);
dsuen : std_logic;
end record;
type dcom_uart_out_type is record
txd : std_logic;
dready : std_logic;
tsempty : std_logic;
thempty : std_logic;
lock : std_logic;
enable : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type dsumem_in_type is record
pbufi : tracebuf_in_type;
abufi : tracebuf_in_type;
end record;
type dsumem_out_type is record
pbufo : tracebuf_out_type;
abufo : tracebuf_out_type;
end record;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/tech_fs90.vhd
|
3
|
26522
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: tech_fs90
-- File: tech_fs90.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains UMC (Farraday Technology) FS90A/B specific pads and
-- ram generators
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_fs90 is
-- sync ram generator
component fs90_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
-- regfile generator
component fs90_regfile
generic ( abits : integer := 8; dbits : integer := 32; words : integer := 128);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
-- pads
component fs90_inpad
port (pad : in std_logic; q : out std_logic); end component;
component fs90_smpad
port (pad : in std_logic; q : out std_logic);
end component;
component fs90_outpad
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end component;
component fs90_toutpadu
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end component;
component fs90_iopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component fs90_smiopad
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component fs90_iopadu
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component fs90_iodpad
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component fs90_odpad
generic (drive : integer := 1);
port ( d : in std_logic; pad : out std_logic);
end component;
end;
------------------------------------------------------------------
-- behavioural pad models --------------------------------------------
------------------------------------------------------------------
-- Only needed for simulation, not synthesis.
-- pragma translate_off
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
entity uyfaa is port (
o : out std_logic;
i : in std_logic;
pu : in std_logic;
pd : in std_logic;
smt : in std_logic);
end;
architecture rtl of uyfaa is
signal inode : std_logic;
begin
inode <= to_x01(i) after 1 ns;
inode <= 'H' when pu = '1' else 'L' when pd = '1' else 'Z';
o <= to_x01(inode);
end;
-- output pad
library IEEE;
use IEEE.std_logic_1164.all;
entity vyfa2gsa is port (
o : out std_logic;
i : in std_logic;
e : in std_logic;
e2 : in std_logic;
e4 : in std_logic;
e8 : in std_logic;
sr : in std_logic);
end;
architecture rtl of vyfa2gsa is begin
o <= to_x01(i) after 2 ns when e = '1' else 'Z' after 2 ns;
end;
-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
entity wyfa2gsa is port (
o : out std_logic;
i : in std_logic;
io : inout std_logic;
e : in std_logic;
e2 : in std_logic;
e4 : in std_logic;
e8 : in std_logic;
sr : in std_logic;
pu : in std_logic;
pd : in std_logic;
smt : in std_logic);
end;
architecture rtl of wyfa2gsa is begin
io <= to_x01(i) after 2 ns when e = '1' else 'Z' after 2 ns;
io <= 'H' when pu = '1' else 'L' when pd = '1' else 'Z';
o <= to_x01(io);
end;
------------------------------------------------------------------
-- behavioural ram models ----------------------------------------
------------------------------------------------------------------
-- synchronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.iface.all;
entity fs90_syncram_sim is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
cselect : in std_logic;
oenable : in std_logic;
write : in std_logic
);
end;
architecture behavioral of fs90_syncram_sim is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
begin
main : process(clk, memarr)
variable do : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) then
do := (others => 'X');
if cselect = '1' then
if (write = '0') and not is_x(address) then
memarr(conv_integer(unsigned(address))) <= datain;
end if;
if (write = '1') and not is_x(address) then
do := memarr(conv_integer(unsigned(address)));
end if;
end if;
if oenable = '1' then dataout <= do; else dataout <= (others => 'Z'); end if;
end if;
end process;
end;
-- 2-port ram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity fs90_dpram_ss is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
data: in std_logic_vector (dbits -1 downto 0);
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
wren : in std_logic;
clka, clkb : in std_logic;
sela, selb : in std_logic;
oe : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of fs90_dpram_ss is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
begin
main : process(clka, clkb, memarr)
variable do : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) then
do := (others => 'X');
if sela = '1' then
if ((wren = '1') or (rdaddress /= wraddress)) and not is_x(rdaddress)
then do := memarr(conv_integer(unsigned(rdaddress))); end if;
end if;
if oe = '1' then q <= do; else q <= (others => 'Z'); end if;
end if;
if rising_edge(clkb) then
if (selb = '1') and (wren = '0') and not is_x(wraddress) then
memarr(conv_integer(unsigned(wraddress))) <= data;
end if;
end if;
end process;
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_fs90_sim is
component fs90_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
cselect : in std_logic;
oenable : in std_logic;
write : in std_logic
);
end component;
component fs90_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
data: in std_logic_vector (dbits -1 downto 0);
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
wren : in std_logic;
clka, clkb : in std_logic;
sela, selb : in std_logic;
oe : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
end;
-- Syncronous SRAM
-- Address, control and data signals latched on rising CK.
-- Write enable (WEB) active low.
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_fs90_sim.all;
entity SA108019 is -- 128x25
port (A0, A1, A2, A3, A4, A5, A6, DI0, DI1, DI2, DI3, DI4, DI5,
DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, CK, CS, OE,
WEB : in std_logic;
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
DO22, DO23, DO24: out std_logic
);
end;
architecture behavioral of SA108019 is
signal din, dout : std_logic_vector(24 downto 0);
signal addr : std_logic_vector(6 downto 0);
begin
addr <= a6&a5&a4&a3&a2&a1&a0;
din <= di24&di23&di22&di21&di20&di19&di18&di17&di16&di15&di14&di13&di12&
di11&di10&di9&di8&di7&di6&di5&di4&di3&di2&di1&di0;
do24 <= dout(24); do23 <= dout(23); do22 <= dout(22); do21 <= dout(21);
do20 <= dout(20); do19 <= dout(19); do18 <= dout(18); do17 <= dout(17);
do16 <= dout(16); do15 <= dout(15); do14 <= dout(14); do13 <= dout(13);
do12 <= dout(12); do11 <= dout(11); do10 <= dout(10); do9 <= dout(9);
do8 <= dout(8); do7 <= dout(7); do6 <= dout(6); do5 <= dout(5);
do4 <= dout(4); do3 <= dout(3); do2 <= dout(2); do1 <= dout(1);
do0 <= dout(0);
syncram0 : fs90_syncram_sim generic map ( abits => 7, dbits => 25)
port map ( addr, ck, din, dout, cs, oe, web);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_fs90_sim.all;
entity SU004020 is -- 512x32
port (A0, A1, A2, A3, A4, A5, A6, A7, A8, DI0, DI1, DI2, DI3, DI4, DI5,
DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26, DI27,
DI28, DI29, DI30, DI31, CK, CS, OE, WEB : in std_logic;
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
);
end;
architecture behavioral of SU004020 is
signal din, dout : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(8 downto 0);
begin
addr <= a8&a7&a6&a5&a4&a3&a2&a1&a0;
din <= di31&di30&di29&di28&di27&di26&di25&di24&di23&di22&di21&di20&di19&
di18&di17&di16&di15&di14&di13&di12&di11&di10&di9&di8&di7&di6&di5&
di4&di3&di2&di1&di0;
do31 <= dout(31); do30 <= dout(30); do29 <= dout(29); do28 <= dout(28);
do27 <= dout(27); do26 <= dout(26); do25 <= dout(25); do24 <= dout(24);
do23 <= dout(23); do22 <= dout(22); do21 <= dout(21); do20 <= dout(20);
do19 <= dout(19); do18 <= dout(18); do17 <= dout(17); do16 <= dout(16);
do15 <= dout(15); do14 <= dout(14); do13 <= dout(13); do12 <= dout(12);
do11 <= dout(11); do10 <= dout(10); do9 <= dout(9); do8 <= dout(8);
do7 <= dout(7); do6 <= dout(6); do5 <= dout(5); do4 <= dout(4);
do3 <= dout(3); do2 <= dout(2); do1 <= dout(1); do0 <= dout(0);
syncram0 : fs90_syncram_sim generic map ( abits => 9, dbits => 32)
port map ( addr, ck, din, dout, cs, oe, web);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_fs90_sim.all;
entity SW204420 is
port (A0, A1, A2, A3, A4, A5, A6, A7, B0, B1, B2, B3, B4, B5, B6,
B7, DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10,
DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20, DI21,
DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31,
CKA, CKB, CSA, CSB, OE,
WEB : in std_logic;
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
);
end;
architecture behavioral of SW204420 is
signal din, dout : std_logic_vector(31 downto 0);
signal addra, addrb : std_logic_vector(7 downto 0);
begin
addra <= a7&a6&a5&a4&a3&a2&a1&a0;
addrb <= b7&b6&b5&b4&b3&b2&b1&b0;
din <= di31&di30&di29&di28&di27&di26&di25&di24&di23&di22&di21&di20&di19&
di18&di17&di16&di15&di14&di13&di12&di11&di10&di9&di8&di7&di6&di5&
di4&di3&di2&di1&di0;
do31 <= dout(31); do30 <= dout(30); do29 <= dout(29); do28 <= dout(28);
do27 <= dout(27); do26 <= dout(26); do25 <= dout(25); do24 <= dout(24);
do23 <= dout(23); do22 <= dout(22); do21 <= dout(21); do20 <= dout(20);
do19 <= dout(19); do18 <= dout(18); do17 <= dout(17); do16 <= dout(16);
do15 <= dout(15); do14 <= dout(14); do13 <= dout(13); do12 <= dout(12);
do11 <= dout(11); do10 <= dout(10); do9 <= dout(9); do8 <= dout(8);
do7 <= dout(7); do6 <= dout(6); do5 <= dout(5); do4 <= dout(4);
do3 <= dout(3); do2 <= dout(2); do1 <= dout(1); do0 <= dout(0);
dpram0 : fs90_dpram_ss generic map ( abits => 8, dbits => 32)
port map ( din, addra, addrb, web, cka, ckb, csa, csb, oe, dout);
end;
-- pragma translate_on
-- component declarations from true tech library
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_fs90_syn is
-- 128x25 sync ram
component SA108019
port (A0, A1, A2, A3, A4, A5, A6, DI0, DI1, DI2, DI3, DI4, DI5,
DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, CK, CS, OE,
WEB : in std_logic;
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
DO22, DO23, DO24: out std_logic
);
end component;
-- 512x32 sync ram
component SU004020
port (A0, A1, A2, A3, A4, A5, A6, A7, A8, DI0, DI1, DI2, DI3, DI4, DI5,
DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26, DI27,
DI28, DI29, DI30, DI31, CK, CS, OE, WEB : in std_logic;
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
);
end component;
-- 2-port sync ram
component SW204420
port (A0, A1, A2, A3, A4, A5, A6, A7, B0, B1, B2, B3, B4, B5, B6,
B7, DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10,
DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20, DI21,
DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31,
CKA, CKB, CSA, CSB, OE,
WEB : in std_logic;
DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
);
end component;
-- in-pad
component uyfaa port (
o : out std_logic;
i : in std_logic;
pu : in std_logic;
pd : in std_logic;
smt : in std_logic);
end component;
-- out-pad
component vyfa2gsa port (
o : out std_logic;
i : in std_logic;
e : in std_logic;
e2 : in std_logic;
e4 : in std_logic;
e8 : in std_logic;
sr : in std_logic);
end component;
-- io-pad
component wyfa2gsa port (
o : out std_logic;
i : in std_logic;
io : inout std_logic;
e : in std_logic;
e2 : in std_logic;
e4 : in std_logic;
e8 : in std_logic;
sr : in std_logic;
pu : in std_logic;
pd : in std_logic;
smt : in std_logic);
end component;
end;
------------------------------------------------------------------
-- sync ram generator --------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in std_logic;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture rtl of fs90_syncram is
signal wr : std_logic;
signal a : std_logic_vector(19 downto 0);
signal d, o : std_logic_vector(34 downto 0);
constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
signal we, vcc : std_logic;
begin
vcc <= '1';
wr <= not write;
a(abits -1 downto 0) <= address;
a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
d(dbits -1 downto 0) <= datain;
d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
dataout <= o(dbits -1 downto 0);
a7d25 : if (abits <= 7) and (dbits <= 25) generate
id0 : SA108019 port map (
a(0), a(1), a(2), a(3), a(4), a(5), a(6),
d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
clk, enable, vcc, wr,
o(0), o(1), o(2), o(3), o(4), o(5), o(6), o(7), o(8),
o(9), o(10), o(11), o(12), o(13), o(14), o(15), o(16),
o(17), o(18), o(19), o(20), o(21), o(22), o(23), o(24));
end generate;
a9d32 : if (abits = 9) and (dbits = 32) generate
id0 : SU004020 port map (
a(0), a(1), a(2), a(3), a(4), a(5), a(6), a(7), a(8),
d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
d(25), d(26), d(27), d(28), d(29), d(30), d(31),
clk, enable, vcc, wr,
o(0), o(1), o(2), o(3), o(4), o(5), o(6), o(7), o(8),
o(9), o(10), o(11), o(12), o(13), o(14), o(15), o(16),
o(17), o(18), o(19), o(20), o(21), o(22), o(23), o(24),
o(25), o(26), o(27), o(28), o(29), o(30), o(31));
end generate;
end rtl;
------------------------------------------------------------------
-- regfile generator --------------------------------------------
------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;
use work.iface.all;
use work.tech_fs90_syn.all;
entity fs90_regfile is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 128
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of fs90_regfile is
signal d, q1, q2 : std_logic_vector(39 downto 0);
signal vcc, wen : std_logic;
signal ra1, ra2, wa : std_logic_vector(12 downto 0);
begin
wen <= not rfi.wren; vcc <= '1';
ra1(abits-1 downto 0) <= rfi.rd1addr;
ra1(12 downto abits) <= (others => '0');
ra2(abits-1 downto 0) <= rfi.rd2addr;
ra2(12 downto abits) <= (others => '0');
wa(abits-1 downto 0) <= rfi.wraddr;
wa(12 downto abits) <= (others => '0');
rfo.data1 <= q1(dbits-1 downto 0);
rfo.data2 <= q2(dbits-1 downto 0);
d(RDBITS-1 downto 0) <= rfi.wrdata;
dp136x32 : if (words = 136) and (dbits = 32) generate
u0: SW204420 port map (
ra1(0), ra1(1), ra1(2), ra1(3), ra1(4), ra1(5), ra1(6), ra1(7),
wa(0), wa(1), wa(2), wa(3), wa(4), wa(5), wa(6), wa(7),
d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
d(25), d(26), d(27), d(28), d(29), d(30), d(31),
clkn, clkn, rfi.ren1, rfi.wren, vcc, wen,
q1(0), q1(1), q1(2), q1(3), q1(4), q1(5), q1(6), q1(7), q1(8),
q1(9), q1(10), q1(11), q1(12), q1(13), q1(14), q1(15), q1(16),
q1(17), q1(18), q1(19), q1(20), q1(21), q1(22), q1(23), q1(24),
q1(25), q1(26), q1(27), q1(28), q1(29), q1(30), q1(31));
u1: SW204420 port map (
ra2(0), ra2(1), ra2(2), ra2(3), ra2(4), ra2(5), ra2(6), ra2(7),
wa(0), wa(1), wa(2), wa(3), wa(4), wa(5), wa(6), wa(7),
d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
d(25), d(26), d(27), d(28), d(29), d(30), d(31),
clkn, clkn, rfi.ren2, rfi.wren, vcc, wen,
q2(0), q2(1), q2(2), q2(3), q2(4), q2(5), q2(6), q2(7), q2(8),
q2(9), q2(10), q2(11), q2(12), q2(13), q2(14), q2(15), q2(16),
q2(17), q2(18), q2(19), q2(20), q2(21), q2(22), q2(23), q2(24),
q2(25), q2(26), q2(27), q2(28), q2(29), q2(30), q2(31));
end generate;
end;
------------------------------------------------------------------
-- mapping generic pads on tech pads ---------------------------------
------------------------------------------------------------------
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_inpad is
port (pad : in std_logic; q : out std_logic);
end;
architecture syn of fs90_inpad is
signal gnd : std_logic;
begin
gnd <= '0';
i0 : uyfaa port map (q, pad, gnd, gnd, gnd);
end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_smpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of fs90_smpad is
signal gnd, vcc : std_logic;
begin
gnd <= '0'; vcc <= '1';
i0 : uyfaa port map (q, pad, gnd, gnd, vcc);
end;
-- output pads
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_outpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of fs90_outpad is
signal gnd, vcc : std_logic;
begin
gnd <= '0'; vcc <= '1';
d1 : if drive = 1 generate
u0 : vyfa2gsa port map (pad, d, vcc, vcc, gnd, gnd, gnd);
end generate;
d2 : if drive = 2 generate
u0 : vyfa2gsa port map (pad, d, vcc, gnd, vcc, gnd, gnd);
end generate;
d3 : if drive = 3 generate
u0 : vyfa2gsa port map (pad, d, vcc, gnd, gnd, vcc, gnd);
end generate;
d4 : if drive > 3 generate
u0 : vyfa2gsa port map (pad, d, vcc, gnd, vcc, vcc, gnd);
end generate;
end;
-- tri-state output pads with pull-up
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_toutpadu is
generic (drive : integer := 1);
port (d, en : in std_logic; pad : out std_logic);
end;
architecture syn of fs90_toutpadu is
signal gnd, vcc, q, ipad, eni : std_logic;
begin
gnd <= '0'; vcc <= '1'; pad <= ipad; eni <= not en;
d1 : if drive = 1 generate
u0 : wyfa2gsa port map (q, d, ipad, eni, vcc, gnd, gnd, gnd, vcc, gnd, gnd);
end generate;
d2 : if drive = 2 generate
u0 : wyfa2gsa port map (q, d, ipad, eni, gnd, vcc, gnd, gnd, vcc, gnd, gnd);
end generate;
d3 : if drive = 3 generate
u0 : wyfa2gsa port map (q, d, ipad, eni, gnd, gnd, vcc, gnd, vcc, gnd, gnd);
end generate;
d4 : if drive > 3 generate
u0 : wyfa2gsa port map (q, d, ipad, eni, gnd, vcc, vcc, gnd, vcc, gnd, gnd);
end generate;
end;
-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_iopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of fs90_iopad is
signal gnd, vcc, eni : std_logic;
begin
gnd <= '0'; vcc <= '1'; eni <= not en;
d1 : if drive = 1 generate
u0 : wyfa2gsa port map (q, d, pad, eni, vcc, gnd, gnd, gnd, gnd, gnd, gnd);
end generate;
d2 : if drive = 2 generate
u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, gnd, gnd, gnd, gnd, gnd);
end generate;
d3 : if drive = 3 generate
u0 : wyfa2gsa port map (q, d, pad, eni, gnd, gnd, vcc, gnd, gnd, gnd, gnd);
end generate;
d4 : if drive > 3 generate
u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, vcc, gnd, gnd, gnd, gnd);
end generate;
end;
-- bidirectional schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_smiopad is
generic (drive : integer := 1);
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of fs90_smiopad is
signal gnd, vcc, eni : std_logic;
begin
gnd <= '0'; vcc <= '1'; eni <= not en;
d1 : if drive = 1 generate
u0 : wyfa2gsa port map (q, d, pad, eni, vcc, gnd, gnd, gnd, gnd, gnd, vcc);
end generate;
d2 : if drive = 2 generate
u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, gnd, gnd, gnd, gnd, vcc);
end generate;
d3 : if drive = 3 generate
u0 : wyfa2gsa port map (q, d, pad, eni, gnd, gnd, vcc, gnd, gnd, gnd, vcc);
end generate;
d4 : if drive > 3 generate
u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, vcc, gnd, gnd, gnd, vcc);
end generate;
end;
-- bidirectional pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_iodpad is
generic (drive : integer := 1);
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture syn of fs90_iodpad is
signal gnd, vcc, eni : std_logic;
begin
gnd <= '0'; vcc <= '1'; eni <= not d;
d1 : if drive = 1 generate
u0 : wyfa2gsa port map (q, gnd, pad, eni, vcc, gnd, gnd, gnd, gnd, gnd, gnd);
end generate;
d2 : if drive = 2 generate
u0 : wyfa2gsa port map (q, gnd, pad, eni, gnd, vcc, gnd, gnd, gnd, gnd, gnd);
end generate;
d3 : if drive = 3 generate
u0 : wyfa2gsa port map (q, gnd, pad, eni, gnd, gnd, vcc, gnd, gnd, gnd, gnd);
end generate;
d4 : if drive > 3 generate
u0 : wyfa2gsa port map (q, gnd, pad, eni, gnd, vcc, vcc, gnd, gnd, gnd, gnd);
end generate;
end;
-- output pad with open-drain
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_fs90_syn.all;
entity fs90_odpad is
generic (drive : integer := 1);
port (d : in std_logic; pad : out std_logic);
end;
architecture syn of fs90_odpad is
signal gnd, vcc, eni : std_logic;
begin
gnd <= '0'; vcc <= '1'; eni <= not d;
d1 : if drive = 1 generate
u0 : vyfa2gsa port map (pad, gnd, eni, vcc, gnd, gnd, gnd);
end generate;
d2 : if drive = 2 generate
u0 : vyfa2gsa port map (pad, gnd, eni, gnd, vcc, gnd, gnd);
end generate;
d3 : if drive = 3 generate
u0 : vyfa2gsa port map (pad, gnd, eni, gnd, gnd, vcc, gnd);
end generate;
d4 : if drive > 3 generate
u0 : vyfa2gsa port map (pad, gnd, eni, gnd, vcc, vcc, gnd);
end generate;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/fp.vhd
|
3
|
32126
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fp
-- File: fp.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Parallel floating-point co-processor interface
-- The interface allows any number of parallel execution unit
-- As an example, two Meiko FPUs and two FMOVE units have been attached
------------------------------------------------------------------------------
-- FPU support unit - performs FMOVS, FNEGS, FABSS
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.iface.all;
entity fpaux is
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end;
architecture rtl of fpaux is
type reg_type is record
op : std_logic_vector (31 downto 0); -- operand
ins : std_logic_vector (1 downto 0); -- operand
end record;
signal r, rin : reg_type;
begin
comb: process(rst, eui, r)
variable rv : reg_type;
variable ready : std_logic;
variable sign : std_logic;
begin
rv := r;
if eui.start = '1' then rv.ins := eui.opcode(3 downto 2); end if;
if eui.load = '1' then rv.op := eui.op2(63 downto 32); end if;
case r.ins is
when "00" => sign := r.op(31); -- fmovs
when "01" => sign := not r.op(31); -- fnegs
when others => sign := '0'; -- fabss
end case;
euo.res(63 downto 29) <= sign & "000" & r.op(30 downto 0);
euo.res(28 downto 0) <= (others => '0');
euo.busy <= '0';
euo.exc <= (others => '0');
euo.cc <= (others => '0');
rin <= rv;
end process;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.ramlib.all;
use work.fpulib.all;
-- pragma translate_off
library MMS;
use MMS.stdioimp.all;
use STD.TEXTIO.all;
use work.debug.all;
-- pragma translate_on
entity fp is
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
xholdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end;
architecture rtl of fp is
constant EUTYPES : integer := 1; -- number of execution unit types
--constant EUTYPES : integer := 1; -- number of execution unit types
constant EU1NUM : integer := 2; -- number of execution unit 1 types
constant EU2NUM : integer := 1; -- number of execution unit 2 types
constant EUMAX : integer := 2; -- maximum number of any execution unit
--constant EUTOT : integer := 2; -- total number of execution units
constant EUTOT : integer := 2; -- total number of execution units
subtype euindex is integer range 0 to EUMAX-1;
subtype eumindex is integer range 0 to EUTOT-1;
subtype eutindex is integer range 0 to EUTYPES-1;
-- array to define how many execution units of each type
type euconf_arr is array (0 to 2) of euindex; -- one more than necessay to avoid modeltech bug
constant euconf : euconf_arr := (EU1NUM-1, EU2NUM-1,0);
--constant euconf : euconf_arr := (EU1NUM,1);
type eu_fifo_arr is array (0 to EUTOT-1) of eutindex;
type eu_fifo_type is record
first : eumindex;
last : eumindex;
fifo : eu_fifo_arr;
end record;
type euq_type is record
first : euindex;
last : euindex;
end record;
type euq_arr is array (0 to EUTYPES-1) of euq_type;
type rfi_type is record
raddr1 : std_logic_vector (3 downto 0);
raddr2 : std_logic_vector (3 downto 0);
waddr : std_logic_vector (3 downto 0);
wdata : std_logic_vector (63 downto 0);
wren : std_logic_vector(1 downto 0);
end record;
type rfo_type is record
rdata1 : std_logic_vector (63 downto 0);
rdata2 : std_logic_vector (63 downto 0);
end record;
type cpins_type is (none, cpop, load, store);
type pl_ctrl is record -- pipeline control record
cpins : cpins_type; -- CP instruction
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wrcc : std_logic; -- write CP condition codes
acsr : std_logic; -- access CP control register
first : euindex;
end record;
type unit_status_type is (exception, free, started, ready);
type unit_ctrl is record -- execution unit control record
status : unit_status_type; -- unit status
rs1 : std_logic_vector (4 downto 0); -- destination register
rs2 : std_logic_vector (4 downto 0); -- destination register
rd : std_logic_vector (4 downto 0); -- destination register
rreg1 : std_logic; -- using rs1
rreg2 : std_logic; -- using rs1
rs1d : std_logic; -- rs1 is double (64-bit)
rs2d : std_logic; -- rs2 is double (64-bit)
wreg : std_logic; -- will write CP regfile
rdd : std_logic; -- rd is double (64-bit)
wb : std_logic; -- result being written back
wrcc : std_logic; -- will write CP condition codes
rst : std_logic; -- reset register
pc : std_logic_vector (31 downto PCLOW); -- program counter
inst : std_logic_vector (31 downto 0); -- instruction
end record;
type csr_type is record -- CP status register
cc : std_logic_vector (1 downto 0); -- condition codes
aexc : std_logic_vector (4 downto 0); -- exception codes
cexc : std_logic_vector (4 downto 0); -- exception codes
tem : std_logic_vector (4 downto 0); -- trap enable mask
rd : std_logic_vector (1 downto 0); -- rounding mode
tt : std_logic_vector (2 downto 0); -- trap type
end record;
type execstate is (nominal, excpend, exception);
type reg_type is record -- registers clocked with pipeline
eufirst : euindex;
eulast : euindex;
sdep : std_logic; -- data dependency ex/me/wr
eut : integer range 0 to EUTYPES-1; -- type EU to start
eui : integer range 0 to EUMAX-1; -- index EU to start
start : std_logic; -- start EU
weut : integer range 0 to EUTYPES-1; -- write stage eut
weui : integer range 0 to EUMAX-1; -- write stage eui
end record;
type regx_type is record -- registers clocked continuously
res : std_logic_vector (63 downto 0); -- write stage result
waddr : std_logic_vector (3 downto 0); -- write stage dest
wren : std_logic_vector (1 downto 0); -- write stage regfile write enable
csr : csr_type; -- co-processor status register
start : std_logic; -- start EU
starty : std_logic; -- start EU
startx : std_logic; -- start EU
holdn : std_logic;
state : execstate; -- using rs1
end record;
type unit_ctrl_arr is array (0 to EUMAX-1) of unit_ctrl;
type unit_ctrl_arr_arr is array (0 to EUTYPES-1) of unit_ctrl_arr;
type eui_arr is array (0 to EUMAX-1) of cp_unit_in_type;
type euo_arr is array (0 to EUMAX-1) of cp_unit_out_type;
type eui_arr_arr is array (0 to EUTYPES) of eui_arr;
type euo_arr_arr is array (0 to EUTYPES) of euo_arr;
signal vcc, gnd : std_logic;
signal rfi : rfi_type;
signal rfo : rfo_type;
signal ex, exin, me, mein, wr, wrin : pl_ctrl;
signal r, rin : reg_type;
signal rx, rxin : regx_type;
signal eui : eui_arr_arr;
signal euo : euo_arr_arr;
signal eu, euin : unit_ctrl_arr_arr;
signal euq, euqin : euq_arr;
signal euf, eufin : eu_fifo_type;
component fpaux
port (
rst : in std_logic; -- Reset
clk : in std_logic; -- clock
eui : in cp_unit_in_type; -- inputs
euo : out cp_unit_out_type -- outputs
);
end component;
function ldcheck (rdin : std_logic_vector; ldd : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) or
((eu.rreg1 = '1') and (rd = eu.rs1)) or
((eu.rreg2 = '1') and (rd = eu.rs2))
then lock := '1'; end if;
if (ldd = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd)) or
((eu.rreg1 = '1') and ((rd(4 downto 1) & '1') = eu.rs1)) or
((eu.rreg2 = '1') and ((rd(4 downto 1) & '1') = eu.rs2))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function stcheck (rdin : std_logic_vector; std : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rd : std_logic_vector(4 downto 0);
begin
lock := '0'; rd := rdin;
if (eu.status > free) then
if (eu.rdd = '0') then
if ((eu.wreg = '1') and (rd = eu.rd)) then lock := '1'; end if;
if (std = '1') then
if ((eu.wreg = '1') and ((rd(4 downto 1) & '1') = eu.rd))
then lock := '1'; end if;
end if;
else
if ((eu.wreg = '1') and (rd(4 downto 1) = eu.rd(4 downto 1))) or
((eu.rreg1 = '1') and (rd(4 downto 1) = eu.rs1(4 downto 1))) or
((eu.rreg2 = '1') and (rd(4 downto 1) = eu.rs2(4 downto 1)))
then lock := '1'; end if;
end if;
end if;
return(lock);
end;
function srccheck (rsin : std_logic_vector; dbl : std_logic; eu : unit_ctrl)
return std_logic is
variable lock : std_logic;
variable rs : std_logic_vector(4 downto 0);
begin
lock := '0'; rs := rsin;
if (eu.wreg = '1') and (rs(4 downto 1) = eu.rd(4 downto 1)) then
if ((dbl or eu.rdd) = '1') or (rs(0) = eu.rd(0)) then lock := '1'; end if;
end if;
return(lock);
end;
function ddepcheck (rs1, rs2 : std_logic_vector;
rreg1, rreg2, rs1d, rs2d : std_logic; eu : unit_ctrl_arr_arr;
euo : euo_arr_arr) return std_logic is
variable ddep : std_logic;
variable r1, r2 : std_logic_vector(4 downto 0);
begin
ddep := '0'; r1 := rs1; r2 := rs2;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if (eu(i)(j).status = started) or (eu(i)(j).status = ready) then
if rreg1 = '1' then ddep := ddep or srccheck(r1, rs1d, eu(i)(j)); end if;
if rreg2 = '1' then ddep := ddep or srccheck(r2, rs2d, eu(i)(j)); end if;
end if;
end loop;
end loop;
return(ddep);
end;
begin
vcc <= '1'; gnd <= '1';
-- instruction decoding
pipeline : process(cpi, ex, me, wr, eu, euin, r, rx, rfi, rfo, holdn, xholdn,
euo, euf, euq, rst)
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opc : std_logic_vector(8 downto 0);
variable stdata : std_logic_vector(31 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable ctrl : pl_ctrl;
variable ldlock : std_logic;
variable wren : std_logic_vector(1 downto 0);
variable waddr : std_logic_vector(3 downto 0);
variable rtaddr : std_logic_vector(3 downto 0);
variable wrdata : std_logic_vector(63 downto 0);
variable rtdata : std_logic_vector(63 downto 0);
variable rv : reg_type;
variable rxv : regx_type;
variable euv : unit_ctrl_arr_arr;
variable euqv : euq_arr;
variable euiv : eui_arr_arr;
variable eufv : eu_fifo_type;
variable euti : eumindex;
variable euqi : euindex;
variable ddep : std_logic;
variable cpexc : std_logic;
variable fpill : std_logic;
variable ccv : std_logic;
variable qne : std_logic;
variable op1 : std_logic_vector (63 downto 0); -- operand1
variable op2 : std_logic_vector (63 downto 0); -- operand2
variable opcode : std_logic_vector (9 downto 0); -- FP opcode
begin
-------------------------------------------------------------
-- decode stage
-------------------------------------------------------------
op := cpi.dinst(31 downto 30);
op3 := cpi.dinst(24 downto 19);
opc := cpi.dinst(13 downto 5);
rs1 := cpi.dinst(18 downto 14);
rs2 := cpi.dinst(4 downto 0);
rd := cpi.dinst(29 downto 25);
rv := r; rxv := rx; ctrl.first := ex.first;
ctrl.cpins := none; ctrl.wreg := '0'; ctrl.rdd := '0';
ctrl.wrcc := '0'; ctrl.acsr := '0'; ldlock := '0';
ctrl.rreg1 := '0'; ctrl.rreg2 := '0';
ctrl.rs1d := '0'; ctrl.rs2d := '0'; fpill := '0';
stdata := (others => '-'); wren := "00"; cpexc := '0';
ccv := '0'; rv.start := '0';
rv.weut := r.eut; rv.weui := r.eui;
rxv.start := '0'; rv.eut := 0; rv.eui := 0; rv.sdep := '0';
euv := eu; euqv := euq; eufv := euf;
euti := euf.fifo(euf.last); euqi := euq(euti).last;
if (euf.last /= euf.first) or (eu(euti)(euqi).status = exception)
then qne := '1'; else qne := '0'; end if;
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).opcode := cpi.ex.inst(19) & cpi.ex.inst(13 downto 5);
euiv(i)(j).start := '0'; euiv(i)(j).load := '0';
euiv(i)(j).flush := eu(i)(j).rst or euin(i)(j).rst;
euv(i)(j).wb := '0';
euv(i)(j).rst := not rst;
if (eu(i)(j).status = started) and (euo(i)(j).busy = '0') then
euv(i)(j).status := ready;
end if;
if (eu(i)(j).status > free) then
ccv := ccv or eu(i)(j).wrcc;
end if;
end loop;
end loop;
-- decode CP instructions
case op is
when FMT3 =>
case op3 is
when FPOP1 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wreg := '1';
case opc is
when FMOVS | FABSS | FNEGS => ctrl.rreg2 := '1';
when FITOS | FSTOI => ctrl.rreg2 := '1';
when FITOD | FSTOD => ctrl.rreg2 := '1'; ctrl.rdd := '1';
when FDTOI | FDTOS => ctrl.rreg2 := '1'; ctrl.rs2d := '1';
when FSQRTS => ctrl.rreg2 := '1';
when FSQRTD => ctrl.rreg2 := '1'; ctrl.rs2d := '1'; ctrl.rdd := '1';
when FADDS | FSUBS | FMULS | FDIVS =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
when FADDD | FSUBD | FMULD | FDIVD =>
ctrl.rreg1 := '1'; ctrl.rreg2 := '1'; ctrl.rs1d := '1';
ctrl.rs2d := '1'; ctrl.rdd := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when FPOP2 =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.cpins := cpop; ctrl.wrcc := '1';
ctrl.rreg1 := '1'; ctrl.rreg2 := '1';
case opc is
when FCMPD | FCMPED =>
ctrl.rs1d := '1'; ctrl.rs2d := '1';
when others => fpill := '1'; -- illegal instuction
end case;
end if;
when others => null;
end case;
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(ex.wreg = '1')
then
if (ctrl.rreg1 = '1') and
(rs1(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs1d or ex.rdd) = '1') or (rs1(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
if (ctrl.rreg2 = '1') and
(rs2(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(((ctrl.rs2d or ex.rdd) = '1') or (rs2(0) = cpi.ex.inst(25)))
then ldlock := '1'; end if;
end if;
when LDST =>
case op3 is
when LDF | LDDF =>
if rx.state = exception then rxv.state := excpend; rxv.csr.tt := "100";
elsif rx.state = nominal then
ctrl.rdd := op3(1) and op3(0);
ctrl.cpins := load; ctrl.wreg := '1';
for i in 0 to EUTYPES-1 loop -- dst interlock
for j in 0 to euconf(i) loop
ldlock := ldlock or ldcheck(rd, ctrl.rdd, euin(i)(j));
end loop;
end loop;
end if;
when STF | STDF =>
-- check for CP register dependencies
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and
((rd = cpi.ex.inst(29 downto 25)) or
((rd(4 downto 1) = cpi.ex.inst(29 downto 26)) and
(ex.rdd = '1')))
then ldlock := '1'; end if;
if rx.state = nominal then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
ldlock := ldlock or stcheck(rd, (op3(1) and op3(0)), euin(i)(j));
end loop;
end loop;
end if;
if (ldlock = '0') then ctrl.cpins := store; end if;
when STFSR | LDFSR =>
if (rx.state = exception) and (op3 = LDFSR) then
rxv.state := excpend; rxv.csr.tt := "100";
else
if (ex.cpins = load) and ((cpi.ex.annul or cpi.ex.trap) = '0') and
(cpi.ex.cnt = "00") and (op3 = STFSR) and (ex.acsr = '1')
then ldlock := '1'; end if;
if (rx.state = nominal) then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
if eu(i)(j).status > free then ldlock := '1'; end if;
end loop;
end loop;
end if;
end if;
-- FIX ME - add check for not yet commited cpins in pipeline
if (ldlock = '0') then
ctrl.acsr := '1';
if op3 = STFSR then ctrl.cpins := store;
else ctrl.cpins := load; end if;
end if;
when STDFQ =>
if (rx.state = nominal) then
rxv.state := excpend; rxv.csr.tt := "100";
else ctrl.cpins := store; end if;
when others => null;
end case;
when others => null;
end case;
if ((cpi.flush or cpi.dtrap or cpi.dannul) = '1') then
ctrl.cpins := none;
rxv.state := rx.state; rxv.csr.tt := rx.csr.tt;
end if;
-------------------------------------------------------------
-- execute stage
-------------------------------------------------------------
-- generate regfile addresses
if holdn = '0' then
op := cpi.me.inst(31 downto 30);
rd := cpi.me.inst(29 downto 25);
op3 := cpi.me.inst(24 downto 19);
rs1 := cpi.me.inst(18 downto 14);
rs2 := cpi.me.inst(4 downto 0);
else
op := cpi.ex.inst(31 downto 30);
rd := cpi.ex.inst(29 downto 25);
op3 := cpi.ex.inst(24 downto 19);
rs1 := cpi.ex.inst(18 downto 14);
rs2 := cpi.ex.inst(4 downto 0);
end if;
if (op = LDST) and (op3(2) = '1') then rs1 := rd; end if;
rfi.raddr1 <= rs1(4 downto 1); rfi.raddr2 <= rs2(4 downto 1);
cpo.ldlock <= ldlock;
op1 := rfo.rdata1; op2 := rfo.rdata2;
-- generate store data
if (cpi.ex.inst(20 downto 19) = "10") then -- STDFQ
if (cpi.ex.cnt /= "10") then stdata := eu(euti)(euqi).pc;
else stdata := eu(euti)(euqi).inst; end if;
elsif ((cpi.ex.inst(25) = '0') and (cpi.ex.cnt /= "10")) then -- STF/STDF
stdata := op1(63 downto 32);
else stdata := op1(31 downto 0); end if;
if (ex.cpins = store) and (ex.acsr = '1') then -- STFSR
stdata := rx.csr.rd & "00" & rx.csr.tem & "000" & FPUVER &
rx.csr.tt & qne & '0' & rx.csr.cc & rx.csr.aexc & rx.csr.cexc;
end if;
cpo.data <= stdata;
-- check for source operand dependency with scheduled instructions
if (ex.cpins = cpop) then
rv.sdep := ddepcheck(cpi.ex.inst(18 downto 14), cpi.ex.inst(4 downto 0),
ex.rreg1, ex.rreg2, ex.rs1d, ex.rs2d, eu, euo);
end if;
-- select execution unit type
if (cpi.ex.inst(12 downto 9) = "0000") and (EUTYPES > 1) then
rv.eut := EUTYPES-1; -- use exection unit 1
else
rv.eut := 0; -- use exection unit 0
end if;
-- check if an execution unit is available
if (ex.cpins = cpop) and (holdn = '1') and (cpi.flush = '0') then
rv.eui := euq(rv.eut).first;
ccv := ccv or ex.wrcc;
if (rv.sdep = '0') and (eu(rv.eut)(euq(rv.eut).first).status = free)
then
rxv.start := '1';
euiv(rv.eut)(rv.eui).start := '1';
euv(rv.eut)(rv.eui).status := started;
euv(rv.eut)(rv.eui).rd := cpi.ex.inst(29 downto 25);
euv(rv.eut)(rv.eui).rs1 := cpi.ex.inst(18 downto 14);
euv(rv.eut)(rv.eui).rs2 := cpi.ex.inst(4 downto 0);
euv(rv.eut)(rv.eui).wreg := ex.wreg;
euv(rv.eut)(rv.eui).rreg1 := ex.rreg1;
euv(rv.eut)(rv.eui).rreg2 := ex.rreg2;
euv(rv.eut)(rv.eui).rs1d := ex.rs1d;
euv(rv.eut)(rv.eui).rs2d := ex.rs2d;
euv(rv.eut)(rv.eui).rdd := ex.rdd;
euv(rv.eut)(rv.eui).wrcc := ex.wrcc;
else rxv.holdn := '0'; rv.start := '1'; end if;
ctrl.first := euf.first;
eufv.fifo(euf.first) := rv.eut;
if euq(rv.eut).first = euconf(rv.eut) then euqv(rv.eut).first := 0;
else euqv(rv.eut).first := euqv(rv.eut).first + 1; end if;
if euf.first = (EUTOT-1) then eufv.first := 0;
else eufv.first := eufv.first + 1; end if;
end if;
-------------------------------------------------------------
-- memory stage
-------------------------------------------------------------
ddep := ddepcheck(cpi.me.inst(18 downto 14), cpi.me.inst(4 downto 0),
me.rreg1, me.rreg2, me.rs1d, me.rs2d, eu, euo);
euiv(r.eut)(r.eui).load := rx.start or rx.starty;
if (rx.holdn = '0') and (xholdn = '1') and (cpi.flush = '0') and
((r.sdep and ddep) = '0') and (euo(r.eut)(euq(r.eut).first).busy = '0')
then
euiv(r.eut)(r.eui).start := not rx.startx;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
end if;
if (rx.holdn = '0') and (cpi.flush = '0') and
(not ((r.sdep = '1') and (ddep = '1'))) and
((eu(r.eut)(r.eui).status <= free) or
(euin(r.eut)(r.eui).wb = '1'))
then
euiv(r.eut)(r.eui).load := rx.starty;
euiv(r.eut)(r.eui).start := not (rx.starty or rx.startx);
if eu(r.eut)(r.eui).status /= exception then
euv(r.eut)(r.eui).status := started;
end if;
euv(r.eut)(r.eui).rs1 := cpi.me.inst(18 downto 14);
euv(r.eut)(r.eui).rs2 := cpi.me.inst(4 downto 0);
euv(r.eut)(r.eui).rd := cpi.me.inst(29 downto 25);
euv(r.eut)(r.eui).wreg := me.wreg;
euv(r.eut)(r.eui).rreg1 := me.rreg1;
euv(r.eut)(r.eui).rreg2 := me.rreg2;
euv(r.eut)(r.eui).rs1d := me.rs1d;
euv(r.eut)(r.eui).rs2d := me.rs2d;
euv(r.eut)(r.eui).rdd := me.rdd;
euv(r.eut)(r.eui).wrcc := me.wrcc;
euiv(r.eut)(r.eui).opcode := cpi.me.inst(19) & cpi.me.inst(13 downto 5);
rxv.holdn := '1';
end if;
rxv.starty := euiv(r.eut)(r.eui).start;
rxv.startx := (rx.startx or euiv(r.eut)(r.eui).start) and not holdn;
ccv := ccv or me.wrcc;
if cpi.flush = '1' then rxv.holdn := '1'; end if;
-- regfile bypass
if (rx.waddr = cpi.me.inst(18 downto 15)) then
if (rx.wren(0) = '1') then op1(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op1(31 downto 0) := rx.res(31 downto 0); end if;
end if;
if (rx.waddr = cpi.me.inst(4 downto 1)) then
if (rx.wren(0) = '1') then op2(63 downto 32) := rx.res(63 downto 32); end if;
if (rx.wren(1) = '1') then op2(31 downto 0) := rx.res(31 downto 0); end if;
end if;
-- optionally forward data from write stage
if rfi.wren(0) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(63 downto 32) := rfi.wdata(63 downto 32);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(63 downto 32) := rfi.wdata(63 downto 32);
end if;
end if;
if rfi.wren(1) = '1' then
if cpi.me.inst(18 downto 15) = rfi.waddr then
op1(31 downto 0) := rfi.wdata(31 downto 0);
end if;
if cpi.me.inst(4 downto 1) = rfi.waddr then
op2(31 downto 0) := rfi.wdata(31 downto 0);
end if;
end if;
-- align single operands
if me.rs1d = '0' then
if cpi.me.inst(14) = '0' then op1 := op1(63 downto 32) & op1(63 downto 32);
else op1 := op1(31 downto 0) & op1(31 downto 0); end if;
end if;
if me.rs2d = '0' then
if cpi.me.inst(0) = '0' then op2 := op2(63 downto 32) & op2(63 downto 32);
else op2 := op2(31 downto 0) & op2(31 downto 0); end if;
end if;
-- drive EU operand inputs
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop
euiv(i)(j).op1 := op1; euiv(i)(j).op2 := op2;
end loop;
end loop;
cpo.holdn <= rx.holdn;
-------------------------------------------------------------
-- write stage
-------------------------------------------------------------
wrdata := cpi.lddata & cpi.lddata;
if cpi.flush = '0' then
case wr.cpins is
when load =>
if (wr.wreg = '1') then
if cpi.wr.cnt = "00" then
wren(0) := not cpi.wr.inst(25);
wren(1) := cpi.wr.inst(25);
else wren(1) := '1'; end if;
end if;
if (wr.acsr and holdn) = '1' then
rxv.csr.cexc := cpi.lddata(4 downto 0);
rxv.csr.aexc := cpi.lddata(9 downto 5);
rxv.csr.cc := cpi.lddata(11 downto 10);
rxv.csr.tem := cpi.lddata(27 downto 23);
rxv.csr.rd := cpi.lddata(31 downto 30);
end if;
when store =>
if wr.acsr = '1' then rxv.csr.tt := (others => '0'); end if;
if (cpi.wr.inst(20 downto 19) = "10") then -- STDFQ
if qne = '1'then
euv(euti)(euqi).status := free;
euv(euti)(euqi).rst := '1';
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if (euf.last /= euf.first) then
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
end if;
else
rxv.state := nominal;
end if;
end if;
when cpop =>
-- dont assign PC and inst until here in case previous cpop trapped
euv(r.weut)(r.weui).inst := cpi.wr.inst;
euv(r.weut)(r.weui).pc := cpi.wr.pc;
when others => null;
end case;
end if;
-- flush EU if trap was taken
if ((holdn and cpi.flush) = '1') and (EUTOT > 1) then
case wr.cpins is
when cpop =>
if eu(r.weut)(r.weui).status /= exception then
euv(r.weut)(r.weui).rst := '1';
euv(r.weut)(r.weui).status := free;
end if;
eufv.first := wr.first;
euqv(r.eut).first := r.eut;
euqv(r.weut).first := r.weut;
when others => null;
end case;
end if;
waddr := cpi.wr.inst(29 downto 26);
-------------------------------------------------------------
-- retire stage
-------------------------------------------------------------
rtaddr := eu(euti)(euqi).rd(4 downto 1);
if eu(euti)(euqi).rdd = '1' then rtdata := euo(euti)(euqi).res;
else
rtdata(63 downto 32) := euo(euti)(euqi).res(63) &
euo(euti)(euqi).res(59 downto 29);
rtdata(31 downto 0) := rtdata(63 downto 32);
end if;
wren := wren and (holdn & holdn);
if ((euo(euti)(euqi).exc(4 downto 0) and rx.csr.tem) /= "00000") or
(euo(euti)(euqi).exc(5) = '1')
then
cpexc := '1';
end if;
if (wren = "00") and (eu(euti)(euqi).status = ready) and
(rx.state = nominal)
then
waddr := rtaddr; wrdata := rtdata;
if cpexc = '0' then
if (eu(euti)(euqi).wreg) = '1' then
if (eu(euti)(euqi).rdd) = '1' then wren := "11";
else
wren(0) := not eu(euti)(euqi).rd(0);
wren(1) := eu(euti)(euqi).rd(0);
end if;
end if;
if eu(euti)(euqi).wrcc = '1' then
rxv.csr.cc := euo(euti)(euqi).cc;
end if;
rxv.csr.aexc := rx.csr.aexc or euo(euti)(euqi).exc(4 downto 0);
if euv(euti)(euqi).status = ready then
euv(euti)(euqi).status := free;
end if;
euv(euti)(euqi).wb := '1';
rxv.csr.cexc := euo(euti)(euqi).exc(4 downto 0);
if euq(euti).last = euconf(euti) then euqv(euti).last := 0;
else euqv(euti).last := euqv(euti).last + 1; end if;
if euf.last = (EUTOT-1) then eufv.last := 0;
else eufv.last := eufv.last + 1; end if;
else
euv(euti)(euqi).status := exception;
rxv.state := excpend;
if (euo(euti)(euqi).exc(5) = '1') then rxv.csr.tt := "011";
else rxv.csr.tt := "001"; end if;
end if;
end if;
if cpi.exack = '1' then rxv.state := exception; end if;
if rxv.state = excpend then cpo.exc <= '1'; else cpo.exc <= '0'; end if;
cpo.ccv <= not ccv;
cpo.cc <= rx.csr.cc;
rxv.res := wrdata;
rxv.waddr := waddr;
rxv.wren := wren;
rfi.waddr <= waddr;
rfi.wren <= wren;
rfi.wdata <= wrdata;
-- reset
if rst = '0' then
for i in 0 to EUTYPES-1 loop
for j in 0 to euconf(i) loop euv(i)(j).status := free; end loop;
euqv(i).first := 0; euqv(i).last := 0;
end loop;
eufv.first := 0; eufv.last := 0; rxv.holdn := '1'; rv.start := '0';
rxv.state := nominal; rxv.csr.tt := (others => '0');
rxv.startx := '0';
ctrl.first := 0;
end if;
euin <= euv;
eui <= euiv;
eufin <= eufv;
euqin <= euqv;
exin <= ctrl;
rin <= rv;
rxin <= rxv;
end process;
-- registers
regs : process(clk)
variable pc : std_logic_vector(31 downto 0);
begin
if rising_edge(clk(0)) then
if holdn = '1' then
ex <= exin; me <= ex; wr <= me; r <= rin;
end if;
euq <= euqin; euf <= eufin;
rx <= rxin; eu <= euin;
-- pragma translate_off
if DEBUGFPU then
if euin(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).wb = '1' then
pc := eu(euf.fifo(euf.last))(euq(euf.fifo(euf.last)).last).pc;
else pc := cpi.wr.pc; end if;
if (rfi.wren(0) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '0') &
" = " & tost(rfi.wdata(63 downto 32)));
end if;
if (rfi.wren(1) = '1') then
print(tost(pc) & ": %f" & tost("000" & rfi.waddr & '1') &
" = " & tost(rfi.wdata(31 downto 0)));
end if;
end if;
-- pragma translate_on
end if;
end process;
-- simple 3-port register file made up of 4 parallel dprams
dp00: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr1, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata1(63 downto 32));
dp01: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr1, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata1(31 downto 0));
dp10: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(63 downto 32), rfi.raddr2, rfi.waddr, vcc, rfi.wren(0),
clk(0), vcc, rfo.rdata2(63 downto 32));
dp11: dpram_synp_ss generic map (4, 32, 16)
port map (rfi.wdata(31 downto 0), rfi.raddr2, rfi.waddr, vcc, rfi.wren(1),
clk(0), vcc, rfo.rdata2(31 downto 0));
gl0 : for i in 0 to euconf(0) generate
fpu0 : fpu port map (
ss_clock => clk(0),
FpInst => eui(0)(i).opcode,
FpOp => eui(0)(i).start,
FpLd => eui(0)(i).load,
Reset => eui(0)(i).flush,
fprf_dout1 => eui(0)(i).op1,
fprf_dout2 => eui(0)(i).op2,
RoundingMode => rx.csr.rd,
FpBusy => euo(0)(i).busy,
FracResult => euo(0)(i).res(51 downto 0),
ExpResult => euo(0)(i).res(62 downto 52),
SignResult => euo(0)(i).res(63),
SNnotDB => open,
Excep => euo(0)(i).exc,
ConditionCodes => euo(0)(i).cc,
ss_scan_mode => gnd,
fp_ctl_scan_in => gnd,
fp_ctl_scan_out => open);
end generate;
fpauxgen : if EUTYPES > 1 generate
gl1 : for i in 0 to euconf(1) generate
eu1 : fpaux port map (rst, clk(0), eui(1)(i), euo(1)(i));
end generate;
end generate;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/cachemem.vhd
|
1
|
5349
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.tech_map.all;
entity cachemem is
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end;
architecture rtl of cachemem is
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant ITWIDTH : natural := ITAG_BITS;
constant DTWIDTH : natural := DTAG_BITS;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal itdatain : std_logic_vector(ITAG_BITS -1 downto 0);
signal itdataout : std_logic_vector(ITAG_BITS -1 downto 0);
signal iddatain : std_logic_vector(32 -1 downto 0);
signal iddataout : std_logic_vector(32 -1 downto 0);
signal itenable : std_logic;
signal idenable : std_logic;
signal itwrite : std_logic;
signal idwrite : std_logic;
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal dtdatain : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdatain2 : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout2: std_logic_vector(DTAG_BITS -1 downto 0);
signal dddatain : std_logic_vector(32 -1 downto 0);
signal dddataout : std_logic_vector(32 -1 downto 0);
signal dtenable : std_logic;
signal dtenable2 : std_logic;
signal ddenable : std_logic;
signal dtwrite : std_logic;
signal dtwrite2 : std_logic;
signal ddwrite : std_logic;
signal vcc, gnd : std_logic;
begin
vcc <= '1'; gnd <= '0'; dtdatain2 <= (others => '0');
itaddr <= crami.icramin.idramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.idramin.address;
itinsel : process(crami)
begin
itdatain(ITAG_BITS - 1 downto 0) <= crami.icramin.itramin.tag &
crami.icramin.itramin.valid;
iddatain(31 downto 0) <= crami.icramin.idramin.data;
dtdatain(DTAG_BITS - 1 downto 0) <= crami.dcramin.dtramin.tag &
crami.dcramin.dtramin.valid;
dddatain(32 - 1 downto 0) <= crami.dcramin.ddramin.data;
end process;
itwrite <= crami.icramin.itramin.write;
idwrite <= crami.icramin.idramin.write;
itenable <= crami.icramin.itramin.enable;
idenable <= crami.icramin.idramin.enable;
dtaddr <= crami.dcramin.ddramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.dtraminsn.address;
ddaddr <= crami.dcramin.ddramin.address;
dtwrite <= crami.dcramin.dtramin.write;
dtwrite2 <= crami.dcramin.dtraminsn.write;
ddwrite <= crami.dcramin.ddramin.write;
dtenable <= crami.dcramin.dtramin.enable;
dtenable2 <= crami.dcramin.dtraminsn.enable;
ddenable <= crami.dcramin.ddramin.enable;
itags0 : syncram
generic map ( dbits => ITAG_BITS, abits => IOFFSET_BITS)
port map ( itaddr, clk, itdatain, itdataout, itenable, itwrite);
dtags0 : if not DSNOOP generate
dtags0 : syncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite);
end generate;
dtags1 : if DSNOOP generate
dtags0 : dpsyncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite,
dtaddr2, dtdatain2, dtdataout2, dtenable2, dtwrite2);
end generate;
idata0 : syncram
generic map ( dbits => 32, abits => IOFFSET_BITS+ILINE_BITS)
port map ( idaddr, clk, iddatain, iddataout, idenable, idwrite);
ddata0 : syncram
generic map ( dbits => 32, abits => DOFFSET_BITS+DLINE_BITS)
port map ( ddaddr, clk, dddatain, dddataout, ddenable, ddwrite);
cramo.icramout.itramout.valid <= itdataout(ILINE_SIZE -1 downto 0);
cramo.icramout.itramout.tag <= itdataout(ITAG_BITS-1 downto ILINE_SIZE);
cramo.icramout.idramout.data <= iddataout(31 downto 0);
cramo.dcramout.dtramout.valid <= dtdataout(DLINE_SIZE -1 downto 0);
cramo.dcramout.dtramout.tag <= dtdataout(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.dtramoutsn.tag <= dtdataout2(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.ddramout.data <= dddataout(31 downto 0);
end ;
|
gpl-3.0
|
mirdej/sk611delay
|
vhdl/Slow_Clock.vhd
|
1
|
2105
|
---------------------------------------------------------------------------------------------
-- VIDEO DELAY - Slow Clock
--
-- Part of the Synkie Project: www.synkie.net
--
-- © 2013 Michael Egger, Licensed under GNU GPLv3
--
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Slow_Clock is
port
(
Clk : in std_logic;
ResetN : in std_logic;
Ms1 : out std_logic; -- 1 ms clock cycle / 1000 Hz
Ms40 : out std_logic; -- 40 ms clock cycle / 25 Hz
Ms500 : out std_logic -- 2 hz
);
end entity;
--------------------------------------------------------------------------------------------
-- ARCHITECTURE
architecture Slow_Clock_Arch of Slow_Clock is
-- uncomment for real world
constant FCLK : positive := 156250000; -- clock cycles / second
constant CYC_P_MS : natural := FCLK / 2000;
-- for testing -> speed up
-- constant CYC_P_MS : natural := 10;
signal clk_int : std_logic;
signal clk2_int : std_logic;
signal clk3_int : std_logic;
begin
process(Clk, ResetN)
variable count : integer range 0 to CYC_P_MS := 0;
begin
if(ResetN = '0') then
count := 0;
elsif((Clk'event) and (Clk = '1')) then
if (count = CYC_P_MS - 1) then
count := 0;
clk_int <= not clk_int;
else
count := count + 1;
end if;
end if;
end process;
a40msclock: process(clk_int)
variable count : integer range 0 to 40 := 0;
begin
if((clk_int'event) and (clk_int = '1')) then
if (count = 39) then
count := 0;
clk2_int <= not clk2_int;
else
count := count + 1;
end if;
end if;
end process;
a500_ms_clock: process(clk_int)
variable count : integer range 0 to 500 := 0;
begin
if((clk_int'event) and (clk_int = '1')) then
if (count = 499) then
count := 0;
clk3_int <= not clk3_int;
else
count := count + 1;
end if;
end if;
end process;
Ms1 <= clk_int;
Ms40 <= clk2_int;
Ms500 <= clk3_int;
end Slow_Clock_Arch;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/dcache.vhd
|
2
|
17354
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dcache
-- File: dcache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements the data cache controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.sparcv8.all; -- ASI declarations
use work.iface.all;
use work.macro.all; -- xorv()
entity dcache is
port (
rst : in std_logic;
clk : in clk_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ico : in icache_out_type;
mcdi : out memory_dc_in_type;
mcdo : in memory_dc_out_type;
dcrami : out dcram_in_type;
dcramo : in dcram_out_type;
fpuholdn : in std_logic
);
end;
architecture rtl of dcache is
constant TAG_HIGH : integer := DTAG_HIGH;
constant TAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := DLINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
type rdatatype is (dtag, ddata, icache, memory); -- sources during cache read
type vmasktype is (clearone, clearall, merge, tnew); -- valid bits operation
type write_buffer_type is record -- write buffer
addr, data1, data2 : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(3 downto 0);
read : std_logic;
lock : std_logic;
end record;
type dcache_control_type is record -- all registers
read : std_logic; -- access direction
signed : std_logic; -- signed/unsigned read
asi : std_logic_vector(3 downto 0); -- asi
size : std_logic_vector(1 downto 0); -- access size
req, burst, holdn, nomds, stpend : std_logic;
xaddress : std_logic_vector(31 downto 0); -- common address buffer
faddr : std_logic_vector(DOFFSET_BITS - 1 downto 0); -- flush address
valid : std_logic_vector(DLINE_SIZE - 1 downto 0); -- registered valid bits
dstate : std_logic_vector(2 downto 0); -- FSM vector
hit : std_logic;
flush : std_logic; -- flush in progress
mexc : std_logic; -- latched mexc
wb : write_buffer_type; -- write buffer
icenable : std_logic; -- icache diag access
end record;
signal r, c : dcache_control_type; -- r is registers, c is combinational
begin
dctrl : process(rst, r, dci, mcdo, ico, dcramo, fpuholdn)
variable rdatasel : rdatatype;
variable maddress : std_logic_vector(31 downto 0);
variable maddrlow : std_logic_vector(1 downto 0);
variable edata : std_logic_vector(31 downto 0);
variable size : std_logic_vector(1 downto 0);
variable read : std_logic;
variable twrite, tdiagwrite, ddiagwrite, dwrite : std_logic;
variable taddr : std_logic_vector(OFFSET_HIGH downto LINE_LOW); -- tag address
variable newtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- new tag
variable align_data : std_logic_vector(31 downto 0); -- aligned data
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((DLINE_SIZE -1) downto 0);
variable vmaskdbl : std_logic_vector((DLINE_SIZE/2 -1) downto 0);
variable enable : std_logic;
variable mds : std_logic;
variable mexc : std_logic;
variable hit, valid, validraw, forcemiss : std_logic;
variable signed : std_logic;
variable flush : std_logic;
variable iflush : std_logic;
variable v : dcache_control_type;
variable eholdn : std_logic; -- external hold
variable tparerr : std_logic;
variable dparerr : std_logic;
begin
-- init local variables
v := r;
mds := '1'; v.req := '0'; dwrite := '0'; twrite := '0';
ddiagwrite := '0'; tdiagwrite := '0'; v.holdn := '1'; mexc := '0';
flush := '0'; v.icenable := '0'; iflush := '0';
eholdn := ico.hold and fpuholdn;
tparerr := '0'; dparerr := '0';
enable := '1';
rdatasel := ddata; -- read data from cache as default
-- generate access parameters during pipeline stall
if (r.holdn) = '0' then
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
elsif ((dci.enaddr and not dci.read) = '1') or (eholdn = '0')
then
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
else
taddr := dci.eaddress(OFFSET_HIGH downto LINE_LOW);
end if;
if (dci.write or not r.holdn) = '1' then
maddress := r.xaddress(31 downto 0); signed := r.signed;
read := r.read; size := r.size; edata := dci.maddress;
else
maddress := dci.maddress(31 downto 0); signed := dci.signed;
read := dci.read; size := dci.size; edata := dci.edata;
end if;
newtag := dci.maddress(TAG_HIGH downto TAG_LOW);
-- generate cache hit and valid bits
forcemiss := not dci.asi(3);
if (dcramo.dtramout.tag = dci.maddress(TAG_HIGH downto TAG_LOW)) then
hit := (not r.flush) and not tparerr;
else
hit := '0';
end if;
validraw := genmux(dci.maddress(LINE_HIGH downto LINE_LOW),
dcramo.dtramout.valid);
valid := validraw and not dparerr;
if ((r.holdn and dci.enaddr) = '1') and (r.dstate = "000") then
v.hit := hit; v.xaddress := dci.maddress;
v.read := dci.read; v.asi := dci.asi(3 downto 0); v.size := dci.size;
v.signed := dci.signed;
end if;
-- Store buffer
wdata := r.wb.data1;
if r.stpend = '1' then
v.req := r.burst or (r.req and not mcdo.grant);
if mcdo.ready = '1' then
v.req := '0'; v.stpend := r.burst; v.burst := '0';
v.wb.addr(2) := '1'; v.wb.data1 := r.wb.data2;
end if;
end if;
if mcdo.ready = '1' then v.wb.addr(2) := '1'; end if;
-- main Dcache state machine
case r.dstate is
when "000" => -- Idle state
v.nomds := r.nomds and not eholdn; v.valid := dcramo.dtramout.valid;
if (dci.enaddr and eholdn and (not r.nomds) and not dci.nullify) = '1' then
case dci.asi(3 downto 0) is
when ASI_ITAG | ASI_IDATA => -- Read/write Icache tags
if ico.flush = '1' then mexc := '1';
else v.dstate := "101"; v.holdn := '0'; end if;
when ASI_IFLUSH => -- flush instruction cache
if dci.read = '0' then iflush := '1'; end if;
when ASI_DFLUSH => -- flush data cache
if dci.read = '0' then flush := '1'; end if;
when ASI_DDATA => -- Read/write Dcache data
if (dci.size /= "10") or (r.flush = '1') then -- only word access is allowed
mexc := '1';
elsif (dci.read = '0') then
dwrite := '1'; ddiagwrite := '1';
end if;
when ASI_DTAG => -- Read/write Dcache tags
rdatasel := dtag;
if (dci.size /= "10") or (r.flush = '1') then -- allow only word access
mexc := '1';
elsif (dci.read = '0') then
twrite := '1'; tdiagwrite := '1';
end if;
when others =>
if (r.stpend = '0') or ((mcdo.ready and not r.burst)= '1') then -- wait for store queue
v.wb.addr := dci.maddress; v.wb.size := dci.size;
v.wb.asi := dci.asi(3 downto 0); v.wb.read := dci.read;
v.wb.data1 := dci.edata; v.wb.lock := dci.lock;
end if;
if dci.read = '1' then -- read access
if (not ((mcdo.dcs(0) = '1')
and ((hit and valid and not forcemiss) = '1')))
then -- read miss
v.holdn := '0'; v.dstate := "001";
if ((r.stpend = '0') or ((mcdo.ready and not r.burst) = '1'))
then -- wait for store queue
v.req := '1';
v.burst := dci.size(1) and dci.size(0) and not dci.maddress(2);
end if;
end if;
else -- write access
if (r.stpend = '0') or ((mcdo.ready and not r.burst)= '1') then -- wait for store queue
v.req := '1'; v.stpend := '1';
v.burst := dci.size(1) and dci.size(0);
if (dci.size = "11") then v.dstate := "100"; end if; -- double store
else -- wait for store queue
v.dstate := "110"; v.holdn := '0';
end if;
if (mcdo.dcs(0) = '1') and ((hit and (dci.size(1) or valid)) = '1')
then -- write hit
twrite := '1'; dwrite := '1';
end if;
if (dci.size = "11") then v.xaddress(2) := '1'; end if;
end if;
end case;
end if;
when "001" => -- read miss, wait for memory data
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
newtag := r.xaddress(TAG_HIGH downto TAG_LOW);
v.nomds := r.nomds and not eholdn;
v.holdn := v.nomds; rdatasel := memory;
if r.stpend = '0' then
v.req := r.req; v.burst := r.req and r.burst;-- and not r.xaddress(2);
if mcdo.grant = '1' then v.req := v.burst; end if;
if mcdo.ready = '1' then
mds := r.holdn or r.nomds; v.xaddress(2) := '1'; v.holdn := '1';
if (mcdo.dcs = "01") then twrite := mcdo.cache and r.hit;
elsif (mcdo.dcs(1) = '1') then twrite := mcdo.cache; end if;
dwrite := twrite; rdatasel := memory;
mexc := mcdo.mexc;
if r.burst = '0' then
if (((dci.enaddr and not mds) = '1') or
((dci.eenaddr and mds and eholdn) = '1')) and (mcdo.dcs(0) = '1') then
v.dstate := "011"; v.holdn := '0';
else v.dstate := "000"; end if;
else v.nomds := '1'; end if;
v.burst := '0'; v.req := '0';
end if;
v.mexc := mcdo.mexc; v.wb.data2 := mcdo.data;
else
if ((mcdo.ready and not r.burst) = '1') then -- wait for store queue
v.burst := r.size(1) and r.size(0) and not r.xaddress(2);
v.wb.addr := r.xaddress; v.wb.size := r.size; v.wb.asi := r.asi(3 downto 0);
v.wb.read := r.read; v.wb.data1 := dci.maddress; v.req := '1';
v.wb.lock := dci.lock;
end if;
end if;
when "011" => -- return from read miss with load pending
taddr := dci.maddress(OFFSET_HIGH downto LINE_LOW);
v.dstate := "000";
when "100" => -- second part of double store cycle
v.dstate := "000"; v.wb.data2 := dci.edata;
edata := dci.edata; -- needed for STD store hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW);
if (mcdo.dcs(0) = '1') and (r.hit = '1') then dwrite := '1'; end if;
when "101" => -- icache diag access
rdatasel := icache; v.icenable := '1'; v.holdn := '0';
if ico.diagrdy = '1' then
v.dstate := "011"; v.icenable := '0'; mds := not r.read;
end if;
when "110" => -- wait for store buffer to empty (store access)
edata := dci.edata; -- needed for STD store hit
if ((mcdo.ready and not r.burst) = '1') then -- store queue emptied
if (mcdo.dcs(0) = '1') and (r.hit = '1') and (r.size = "11") then -- write hit
taddr := r.xaddress(OFFSET_HIGH downto LINE_LOW); dwrite := '1';
end if;
v.dstate := "000";
v.req := '1'; v.burst := r.size(1) and r.size(0); v.stpend := '1';
v.wb.addr := r.xaddress; v.wb.size := r.size;
v.wb.asi := r.asi(3 downto 0);
v.wb.read := r.read; v.wb.data1 := dci.maddress;
v.wb.lock := dci.lock;
v.wb.data2 := dci.edata;
if r.size = "11" then v.wb.addr(2) := '0'; end if;
else -- hold cpu until buffer empty
v.holdn := '0';
end if;
when others => v.dstate := "000";
end case;
-- select data to return on read access
-- align if byte/half word read from cache or memory.
rdata := (others => '0');
align_data := (others => '0');
maddrlow := maddress(1 downto 0); -- stupid Synopsys VSS bug ...
case rdatasel is
when dtag =>
rdata(TAG_HIGH downto TAG_LOW) := dcramo.dtramout.tag;
rdata(DLINE_SIZE -1 downto 0) := dcramo.dtramout.valid;
when icache => rdata := ico.diagdata;
when ddata | memory =>
if rdatasel = ddata then align_data := dcramo.ddramout.data;
else align_data := mcdo.data; end if;
case size is
when "00" => -- byte read
case maddrlow is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if maddress(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
end case;
-- select which data to update the data cache with
case size is -- merge data during partial write
when "00" =>
case maddrlow is
when "00" =>
ddatain := edata(7 downto 0) & dcramo.ddramout.data(23 downto 0);
when "01" =>
ddatain := dcramo.ddramout.data(31 downto 24) & edata(7 downto 0) &
dcramo.ddramout.data(15 downto 0);
when "10" =>
ddatain := dcramo.ddramout.data(31 downto 16) & edata(7 downto 0) &
dcramo.ddramout.data(7 downto 0);
when others =>
ddatain := dcramo.ddramout.data(31 downto 8) & edata(7 downto 0);
end case;
when "01" =>
if maddress(1) = '0' then
ddatain := edata(15 downto 0) & dcramo.ddramout.data(15 downto 0);
else
ddatain := dcramo.ddramout.data(31 downto 16) & edata(15 downto 0);
end if;
when others =>
ddatain := edata;
end case;
-- handle double load with pipeline hold
if (r.dstate = "000") and (r.nomds = '1') then
rdata := r.wb.data2; mexc := r.mexc;
end if;
-- Handle AHB retry
v.req := v.req or mcdo.retry;
-- Generate new valid bits
vmaskdbl := decode(maddress(LINE_HIGH downto LINE_LOW+1));
if (size = "11") and (read = '0') then
for i in 0 to (DLINE_SIZE - 1) loop vmaskraw(i) := vmaskdbl(i/2); end loop;
else
vmaskraw := decode(maddress(LINE_HIGH downto LINE_LOW));
end if;
vmask := vmaskraw;
if r.hit = '1' then vmask := r.valid or vmaskraw; end if;
if r.dstate = "000" then
vmask := dcramo.dtramout.valid or vmaskraw;
end if;
if (mcdo.mexc or r.flush) = '1' then
twrite := '0'; dwrite := '0';
end if;
if twrite = '1' then
v.valid := vmask; if (r.dstate = "001") then v.hit := mcdo.cache; end if;
end if;
if tdiagwrite = '1' then -- diagnostic tag write
vmask := dci.edata(DLINE_SIZE - 1 downto 0);
end if;
-- cache flush
if (dci.flush or flush) = '1' then
v.flush := '1'; v.faddr := (others => '0');
end if;
if r.flush = '1' then
twrite := '1'; vmask := (others => '0'); v.faddr := r.faddr +1;
newtag(TAG_HIGH downto TAG_LOW) := (others => '0');
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
-- taddr(OFFSET_LOW-1 downto LINE_LOW) := (others => '0');
if (r.faddr(DOFFSET_BITS -1) and not v.faddr(DOFFSET_BITS -1)) = '1' then
v.flush := '0';
end if;
end if;
-- update cache with memory data during read miss
if read = '1' then ddatain := mcdo.data; end if;
-- reset
if rst = '0' then
v.dstate := "000"; v.stpend := '0'; v.req := '0'; v.burst := '0';
v.read := '0'; v.flush := '0'; v.nomds := '0';
end if;
-- Drive signals
c <= v; -- register inputs
-- tag ram inputs
dcrami.dtramin.valid <= vmask;
dcrami.dtramin.tag <= newtag(TAG_HIGH downto TAG_LOW);
dcrami.dtramin.enable <= enable;
dcrami.dtramin.write <= twrite;
-- data ram inputs
dcrami.ddramin.enable <= enable;
dcrami.ddramin.address <= taddr;
dcrami.ddramin.data <= ddatain;
dcrami.ddramin.write <= dwrite;
-- memory controller inputs
mcdi.address <= r.wb.addr;
mcdi.data <= r.wb.data1;
mcdi.asi <= r.wb.asi;
mcdi.burst <= r.burst;
mcdi.size <= r.wb.size;
mcdi.read <= r.wb.read;
mcdi.lock <= r.wb.lock;
mcdi.req <= r.req;
mcdi.flush <= r.flush;
-- diagnostic instruction cache
dco.icdiag.flush <= iflush;
dco.icdiag.read <= read;
dco.icdiag.tag <= not r.asi(0);
dco.icdiag.addr <= r.xaddress;
dco.icdiag.enable <= r.icenable;
-- IU data cache inputs
dco.data <= rdata;
dco.mexc <= mexc;
dco.hold <= r.holdn;
dco.mds <= mds;
dco.werr <= mcdo.werr;
end process;
-- Local registers
dlat : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
end ;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/dct/serout.vhd
|
1
|
1100
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY dctslowout IS
PORT(
clk : IN std_logic ;
doutput : IN std_logic_vector (15 DOWNTO 0) ;
read : IN std_logic ;
reset : IN std_logic ;
dout : OUT std_logic ;
start : OUT std_logic
);
-- Declarations
END dctslowout ;
--
--
ARCHITECTURE beh3 OF dctslowout IS
signal inreg : std_logic_vector(15 downto 0);
signal start_int : std_logic;
BEGIN
process(reset,clk)
variable done : std_logic;
begin
if rising_edge(clk) then
if reset = '1' then
inreg <= "0000000000000000";
start_int <= '0';
start <= '0';
done := '0';
else
start <= start_int;
if read = '1' then
if done = '0' then
done := '1';
start_int <= '1';
else
start_int <= '0';
end if;
else
done := '0';
end if;
if start_int = '0' then
inreg <= '0'&inreg(15 downto 1);
else
inreg <= doutput;
end if;
end if;
end if;
end process;
dout <= inreg(0);
END beh3;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/pci.vhd
|
1
|
3211
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Reserch
-- Description: Module containing all possible PCI cores
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.ambacomp.all;
entity pci is
port (
resetn : in std_logic;
clk : in clk_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi1 : in ahb_mst_in_type;
ahbmo1 : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
irq : out std_logic
;clk_out: out std_logic
);
end;
architecture rtl of pci is
signal gnd4 : std_logic_vector(3 downto 0);
begin
-- InSilicon PCI core
pci_is0 : if PCICORE = insilicon generate
pci0 : pci_is
port map (
rst_n =>resetn, app_clk => clk, pci_clk => pcii.pci_clk_in,
pbi => apbi, pbo => apbo, irq => irq,
TargetMasterOut => ahbmo1, TargetMasterIn => ahbmi1,
pci_in => pcii, pci_out => pcio,
InitSlaveOut => ahbso, InitSlaveIn => ahbsi,
InitMasterOut => ahbmo2, InitMasterIn => ahbmi2
);
end generate;
pci_actel0 : if PCICORE = actel generate
-- pci0 : pci_actel
-- generic map (
-- USER_DEVICE_ID => PCI_DEVICE_ID, USER_VENDOR_ID => PCI_VENDOR_ID,
-- USER_REVISION_ID => PCI_REVISION_ID, USER_SUBSYSTEM_ID => PCI_SUBSYS_ID,
-- USER_BASE_CLASS => PCI_CLASS_CODE)
-- port map (
-- rst => resetn, clk => pcii.pci_clk_in, clk_out => clk_out, pcii => pcii, pcio => pcio,
-- ahbmi => ahbmi1, ahbmo => ahbmo1, ahbsi => ahbsi, ahbso => ahbso
-- );
--
-- ahbmo2.hbusreq <= '0';
-- ahbmo2.hlock <= '0';
-- ahbmo2.htrans <= HTRANS_IDLE;
-- ahbmo2.haddr <= (others => '0');
-- ahbmo2.hwrite <= '0';
-- ahbmo2.hburst <= HBURST_SINGLE;
-- ahbmo2.hprot <= (others => '0');
-- ahbmo2.hwdata <= (others => '0');
-- irq <= '0';
end generate;
-- Optional ESA PCI core
-- pci_esa0 : if PCICORE = esa generate
-- pci0 : pci_esa
-- port map (
-- resetn => rst.syncrst, app_clk => clko.clk,
-- pci_in => pcii, pci_out => pcio,
-- ahbmasterin => ahbmi(1), ahbmasterout => ahbmo(1),
-- ahbslavein => ahbsi(2), ahbslaveout => ahbso(2),
-- apbslavein => apbi(10), apbslaveout => apbo(10), irq => pciirq
-- );
-- pciresetn <= pcii.pci_rst_in_n;
-- end generate;
end ;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/VFLOAT_2015/General Modules/shift_adjust/shift_adjust.vhd
|
1
|
4526
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Shift/Adjust Module --
----------------------------------------------------------
entity shift_adjust is
generic
(
exp_bits : integer := 8;
man_bits : integer := 23
);
port
(
--inputs
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
READY : in std_logic;
FILL : in std_logic;
EXP_DIFF : in std_logic_vector(exp_bits-1 downto 0);
F_IN : in std_logic_vector(man_bits+1 downto 0);
--outputs
F_OUT : out std_logic_vector(man_bits+1 downto 0);
DONE : out std_logic
);
end shift_adjust;
architecture shift_adjust_arch of shift_adjust is
--SIGNALS
signal man_in : std_logic_vector(man_bits+1 downto 0);
signal man_out : std_logic_vector(man_bits+1 downto 0);
begin
man_in <= ((not F_IN) + '1') when (fill = '1') else F_IN;
pars : parameterized_shifter
generic map
(
bits => man_bits+2,
shift_bits => exp_bits,
direction => '0'
)
port map
(
I => man_in,
S => exp_diff,
FILL => fill,
O => man_out
);
--SYNCHRONOUS
main: process (CLK,RESET,STALL) is
begin
if (RESET = '1') then
DONE <= '0';
F_OUT <= (others=>'0');
elsif(rising_edge(CLK) and STALL = '0') then
DONE <= READY;
F_OUT <= man_out;
end if;--CLK
end process main;--main
end shift_adjust_arch; --end of architecture
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/device.vhd
|
1
|
2498
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: device
-- File: device.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: package to select current device configuration
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
package device is
----------------------------------------------------------------------
-- This is the current device configuration
----------------------------------------------------------------------
-- constant conf : config_type := fpga_4k4k_v8_fpu; -- debug enabled for simulation in target.vhd
-- constant conf : config_type := virtex_2k2k_25M_fpu;
constant conf : config_type := fpga_2k2k;
-- constant conf : config_type := fpga_2k2k_fpu_bprom_25M; -- bprom version
-- constant conf : config_type := fpga_2k2k_33M;
-- constant conf : config_type := fpga_2k2k; -- debug enabled
-- constant conf : config_type := fpga_2k2k_v8;
-- constant conf : config_type := fpga_2k2k_irq2;
-- constant conf : config_type := fpga_2k2k_softprom;
-- constant conf : config_type := fpga_2k2k_v8_softprom;
-- constant conf : config_type := fpga_4k4k_v8_fpu;
-- constant conf : config_type := fpga_4k4k_v8_fpu_softprom;
-- constant conf : config_type := fpga_2k2k_v8_mac_softprom;
-- constant conf : config_type := virtex_2k2k_blockprom;
-- constant conf : config_type := virtex_2k1k_rdbmon;
-- constant conf : config_type := virtex_2k2k_v8_fpu_blockprom;
-- constant conf : config_type := gen_atc25;
-- constant conf : config_type := gen_atc25_meiko;
-- constant conf : config_type := gen_atc25_fpc;
-- constant conf : config_type := gen_atc25_insilicon_pci;
-- constant conf : config_type := gen_atc35;
-- constant conf : config_type := systel_fpga;
-- constant conf : config_type := systel_asic;
-- constant conf : config_type := gen_fs90;
-- constant conf : config_type := gen_umc18;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/leon-ooac.vhd
|
2
|
7681
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leon
-- File: leon.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Complete processor
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity leon is
port (
resetn : in std_logic; -- system signals
clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0); -- memory bus
---
datain : in std_logic_vector(31 downto 0); -- 32 bits conversion LA
dataout : out std_logic_vector(31 downto 0);
datasel : out std_logic_vector(3 downto 0);
---
ramsn : out std_logic_vector(4 downto 0);
ramoen : out std_logic_vector(4 downto 0);
rwen : inout std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : inout std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
---
pioo : out std_logic_vector(15 downto 0); -- I/O port 32 bits LA
pioi : in std_logic_vector(15 downto 0);
piod : out std_logic_vector(15 downto 0);
buttons : in std_logic_vector(3 downto 0); -- ddm ports
audioin : in std_logic;
digit0 : out std_logic_vector(6 downto 0);
digit1 : out std_logic_vector(6 downto 0);
audioout : out std_logic;
lr_out : out std_logic;
shift_clk : out std_logic;
mclk : out std_logic;
dispen : out std_logic;
---
wdogn : out std_logic; -- watchdog output
--
dsuen : in std_logic;
dsutx : out std_logic;
dsurx : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
--
test : in std_logic
);
end;
architecture rtl of leon is
component mcore
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
--
ddmi : in ddm_in_type; -- DDM signals LA
ddmo : out ddm_out_type;
--
dsi : in dsuif_in_type;
dso : out dsuif_out_type;
test : in std_logic
);
end component;
signal gnd, clko, resetno : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal dsi : dsuif_in_type;
signal dso : dsuif_out_type;
--
signal ddmi : ddm_in_type; -- DDM signals LA
signal ddmo : ddm_out_type;
--
begin
gnd <= '0';
-- main processor core
mcore0 : mcore
port map (
resetn => resetno, clk => clko,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
-- pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, test => test
pcii => pcii, pcio => pcio, ddmi => ddmi, ddmo => ddmo,dsi => dsi, dso => dso, test => test -- DDM LA
);
-- pads
-- clk_pad : inpad port map (clk, clko); -- clock
clko <= clk; -- avoid buffering during synthesis
reset_pad : smpad port map (resetn, resetno); -- reset
brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
--DDM lines
inpad4 : inpad port map (audioin, ddmi.audioin);
inpad5 : inpad port map (buttons(0),ddmi.button0);
inpad6 : inpad port map (buttons(1),ddmi.button1);
inpad7 : inpad port map (buttons(2),ddmi.button2);
inpad8 : inpad port map (buttons(3),ddmi.button3);
-- d_pads: for i in 0 to 31 generate -- data bus
-- d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
-- end generate;
--
dataout <= memo.data; -- databus DDM LA
memi.data <= datain;
datasel <= memo.bdrive;
-- pio_pads : for i in 0 to 15 generate -- parallel I/O port
-- pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
-- end generate;
--
pioo <= ioo.piol; -- parallel I/O port DDM
ioi.piol <= pioi;
piod <= ioo.piodir;
rwen(0) <= memo.wrn(0);
memi.wrn(0) <= memo.wrn(0);
rwen(1) <= memo.wrn(1);
memi.wrn(1) <= memo.wrn(1);
rwen(2) <= memo.wrn(2);
memi.wrn(2) <= memo.wrn(2);
rwen(3) <= memo.wrn(3);
memi.wrn(3) <= memo.wrn(3);
-- rwen_pads : for i in 0 to 3 generate -- ram write strobe
-- rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
-- end generate;
--
-- -- I/O write strobe
-- writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
--
writen <= memo.writen; -- DDM LA
memi.writen <= memo.writen;
a_pads: for i in 0 to 27 generate -- memory address
a_pad : outpad generic map (3) port map (memo.address(i), address(i));
end generate;
ramsn_pads : for i in 0 to 4 generate -- ram oen/rasn
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
end generate;
ramoen_pads : for i in 0 to 4 generate -- ram chip select
eamoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
end generate;
romsn_pads : for i in 0 to 1 generate -- rom chip select
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
end generate;
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
--
outpadb7: outpad port map (ddmo.shift_clk, shift_clk); -- DDM
outpadb8: outpad port map (ddmo.lr_out, lr_out);
outpadb9: outpad port map (ddmo.audioout, audioout);
outpadb10: for i in 0 to 6 generate
outpad101: outpad port map(ddmo.digit0(i), digit0(i));
end generate;
outpadb11: for i in 0 to 6 generate
outpad111: outpad port map(ddmo.digit1(i), digit1(i));
end generate;
outpadb12: outpad port map (ddmo.mclk, mclk);
dispen <= ddmo.dispen;
--
wd : if WDOGEN generate
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
end generate;
ds : if DEBUG_UNIT generate
dsuen_pad : inpad port map (dsuen, dsi.dsui.dsuen); -- DSU enable
dsutx_pad : outpad generic map (1) port map (dso.dcomo.dsutx, dsutx);
dsurx_pad : inpad port map (dsurx, dsi.dcomi.dsurx); -- DSU receive data
dsubre_pad : inpad port map (dsubre, dsi.dsui.dsubre); -- DSU break
dsuact_pad : outpad generic map (1) port map (dso.dsuo.dsuact, dsuact);
end generate;
end ;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/VFLOAT_2015/General Modules/parameterized modules/parameterized_variable_shifter/parameterized_variable_shifter.vhd
|
2
|
5157
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized variable shifter --
----------------------------------------------------------
entity parameterized_variable_shifter is
generic
(
bits : integer := 12;
select_bits : integer := 4;
direction : std_logic := '0' --0=right,1=left
);
port
(
--inputs
I : in std_logic_vector(bits-1 downto 0);
S : in std_logic_vector(select_bits-1 downto 0);
CLEAR : in std_logic;
--outputs
O : out std_logic_vector(bits-1 downto 0)
);
end parameterized_variable_shifter;
----------------------------------------------------------
-- Parameterized variable shifter --
----------------------------------------------------------
architecture parameterized_variable_shifter_arch of parameterized_variable_shifter is
--CONSTANTS
constant rows : integer := ceil_log2(bits);
--TYPES
type pipe is
array (0 to rows) of
std_logic_vector(bits-1 downto 0);
--SIGNALS
signal im : pipe; --intermediate signals
signal zeros : std_logic_vector(bits-1 downto 0) := (others=>'0');
begin
--connect input
im(0) <= I;
--defective module
defective : if(rows/=select_bits) generate
O <= (others=>'0'); --output zero if instantiated wrongly
end generate;--defective unit
--correctly instantiated
correct : if(rows=select_bits) generate
over_rows : for x in 0 to rows-1 generate --iterate over rows
row : parameterized_variable_shifter_row
generic map
(
bits => bits,
row_number => x,
direction => direction
)
port map
(
--inputs
I => im(x),
S => S(x),
FILL => '0',
--outputs
O => im(x+1)
);
end generate;--rows
output_mux : parameterized_mux
generic map
(
bits => bits
)
port map
(
--inputs
A => zeros,
B => im(rows),
S => CLEAR,
--outputs
O => O
);
end generate;--correctly instantiated
end parameterized_variable_shifter_arch; -- end of architecture
|
gpl-3.0
|
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/vga_res_sel.vhd
|
1
|
1505
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.vga_mouse_pkg.all;
entity vga_res_sel is
port (
resolution : in std_logic;
HS_640_60 : in std_logic;
VS_640_60 : in std_logic;
HS_800_60 : in std_logic;
VS_800_60 : in std_logic;
red_25 : in std_logic_vector(2 downto 0);
green_25 : in std_logic_vector(2 downto 0);
blue_25 : in std_logic_vector(2 downto 1);
red_40 : in std_logic_vector(2 downto 0);
green_40 : in std_logic_vector(2 downto 0);
blue_40 : in std_logic_vector(2 downto 1);
hs : out std_logic; -- Horizontal sync
vs : out std_logic; -- Vertical sync
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end vga_res_sel;
architecture behavioral of vga_res_sel is
begin
-- select horizontal synch pulse signal depending on the
-- resolution used
hs <= HS_800_60 when resolution = '1' else HS_640_60;
-- select vertical synch pulse signal depending on the
-- resolution used
vs <= VS_800_60 when resolution = '1' else VS_640_60;
red <= red_25 when resolution = '0' else red_40;
green <= green_25 when resolution = '0' else green_40;
blue <= blue_25 when resolution = '0' else blue_40;
end behavioral;
|
gpl-3.0
|
tejainece/VHDLExperiments
|
GoldschmidtDivider/Counter4_2.vhd
|
4
|
1489
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:15:39 12/15/2013
-- Design Name:
-- Module Name: Counter4_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
end Counter4_2;
architecture Behavioral of Counter4_2 is
COMPONENT FAdder
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
signal sINT1: STD_LOGIC;
begin
fa1: FAdder port map(
c => a,
a => b,
b => c,
s => sINT1,
co => tout
);
fa2: FAdder port map(
c => tin,
a => sINT1,
b => d,
s => s,
co => co
);
end Behavioral;
|
gpl-3.0
|
tejainece/VHDLExperiments
|
FloatingPointMul23/Counter4_2.vhd
|
4
|
1489
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:15:39 12/15/2013
-- Design Name:
-- Module Name: Counter4_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
end Counter4_2;
architecture Behavioral of Counter4_2 is
COMPONENT FAdder
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
signal sINT1: STD_LOGIC;
begin
fa1: FAdder port map(
c => a,
a => b,
b => c,
s => sINT1,
co => tout
);
fa2: FAdder port map(
c => tin,
a => sINT1,
b => d,
s => s,
co => co
);
end Behavioral;
|
gpl-3.0
|
tejainece/VHDLExperiments
|
Multiply16Booth4/FAdder.vhd
|
4
|
1094
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:06:21 11/13/2013
-- Design Name:
-- Module Name: FAdder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end FAdder;
architecture Behavioral of FAdder is
begin
s <= a xor b xor c;
co <= (a and b) or ((a xor b) and c);
end Behavioral;
|
gpl-3.0
|
johnmurrayvi/vhdl-projects
|
CPU/cpuout.vhd
|
1
|
509974
|
-- cpu (EPF10K10TC144-3)
--
-- Copyright (C) 1991-1997 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- MAX+plus II Version 7.2 RC2 2/14/97
-- Mon Dec 22 16:11:31 1997
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
LIBRARY alt_vtl;
USE alt_vtl.VCOMPONENTS.all;
ENTITY cpu IS
PORT (
addr : OUT std_logic_vector(15 downto 0);
data : INOUT std_logic_vector(15 downto 0);
clock : IN std_logic;
ready : IN std_logic;
reset : IN std_logic;
rw : OUT std_logic;
vma : OUT std_logic);
END cpu;
ARCHITECTURE EPF10K10TC144_a3 OF cpu IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL
ix1553_aOE, n_174, a_as_or3_aix1786_a_a32_aOUT, n_176, n_177, n_178, n_179,
n_180, O_dup_827_aOUT, n_182, ix1551_aOE, n_184, n_185, n_186, n_187,
n_188, n_189, O_dup_820_aOUT, n_191, ix1549_aOE, n_193, n_194, n_195,
n_196, n_197, n_198, O_dup_817_aOUT, n_200, ix1547_aOE, n_202, n_203,
n_204, n_205, n_206, n_207, O_dup_814_aOUT, n_209, ix1545_aOE, n_211,
n_212, n_213, n_214, n_215, n_216, O_dup_811_aOUT, n_218, ix1543_aOE,
n_220, n_221, n_222, n_223, n_224, n_225, O_dup_808_aOUT, n_227,
ix1541_aOE, n_229, n_230, n_231, n_232, n_233, n_234, O_dup_805_aOUT,
n_236, ix1539_aOE, n_238, n_239, n_240, n_241, n_242, n_243, O_dup_802_aOUT,
n_245, ix1537_aOE, n_247, n_248, n_249, n_250, n_251, n_252, O_dup_799_aOUT,
n_254, ix1535_aOE, n_256, n_257, n_258, n_259, n_260, n_261, O_dup_796_aOUT,
n_263, ix1533_aOE, n_265, n_266, n_267, n_268, n_269, n_270, O_dup_793_aOUT,
n_272, ix1531_aOE, n_274, n_275, n_276, n_277, n_278, n_279, O_dup_790_aOUT,
n_281, ix1529_aOE, n_283, n_284, n_285, n_286, n_287, n_288, O_dup_787_aOUT,
n_290, ix1527_aOE, n_292, n_293, n_294, n_295, n_296, n_297, O_dup_784_aOUT,
n_299, ix1525_aOE, n_301, n_302, n_303, n_304, n_305, n_306, O_dup_781_aOUT,
n_308, ix1523_aOE, n_310, n_311, n_312, n_313, n_314, n_315, O_dup_778_aOUT,
n_317, n_318, n_319, n_320, n_321, n_322, O_aOUT, n_324, n_325,
n_326, n_327, n_328, n_329, rw_dup0_Q, n_331, n_332, n_333, n_334,
n_335, n_336, addr_dup00_Q, n_338, n_339, n_340, n_341, n_342, n_343,
addr_dup01_Q, n_345, n_346, n_347, n_348, n_349, n_350, addr_dup02_Q,
n_352, n_353, n_354, n_355, n_356, n_357, addr_dup03_Q, n_359, n_360,
n_361, n_362, n_363, n_364, addr_dup04_Q, n_366, n_367, n_368, n_369,
n_370, n_371, addr_dup05_Q, n_373, n_374, n_375, n_376, n_377, n_378,
addr_dup06_Q, n_380, n_381, n_382, n_383, n_384, n_385, addr_dup07_Q,
n_387, n_388, n_389, n_390, n_391, n_392, addr_dup08_Q, n_394, n_395,
n_396, n_397, n_398, n_399, addr_dup09_Q, n_401, n_402, n_403, n_404,
n_405, n_406, addr_dup010_Q, n_408, n_409, n_410, n_411, n_412,
n_413, addr_dup011_Q, n_415, n_416, n_417, n_418, n_419, n_420,
addr_dup012_Q, n_422, n_423, n_424, n_425, n_426, n_427, addr_dup013_Q,
n_429, n_430, n_431, n_432, n_433, n_434, addr_dup014_Q, n_436,
n_437, n_438, n_439, n_440, n_441, addr_dup015_Q, n_443, O_dup_876_aOUT,
O_dup_876_aIN, n_446, n_447, n_448, I2_dup_823_aOUT, n_450, ix484_nx43_aOUT,
n_452, ix484_nx40_aOUT, ix484_nx40_aIN, n_455, n_456, n_457, I1_dup_755_aOUT,
n_459, regsel0_aOUT, n_461, I2_dup_756_aOUT, n_463, O_dup_885_aOUT,
O_dup_885_aIN, n_466, n_467, n_468, n_469, n_470, I1_dup_767_aOUT,
I1_dup_767_aIN, n_473, n_474, n_475, O_dup_1034_aOUT, n_477, n_478,
ix484_nx44_aOUT, ix484_nx44_aIN, n_481, n_482, n_483, I0_dup_770_aOUT,
n_485, n_486, O_dup_882_aOUT, O_dup_882_aIN, n_489, n_490, n_491,
n_492, n_493, ix484_nx39_aOUT, ix484_nx39_aIN, n_496, n_497, n_498,
n_499, n_500, n_501, O_dup_891_aOUT, O_dup_891_aIN, n_504, n_505,
n_506, n_507, n_508, ix484_nx42_aOUT, ix484_nx42_aIN, n_511, n_512,
n_513, I0_dup_766_aOUT, n_515, n_516, O_dup_888_aOUT, O_dup_888_aIN,
n_519, n_520, n_521, n_522, n_523, I0_dup_1373_aOUT, I0_dup_1373_aIN,
n_526, n_527, n_528, n_529, n_530, n_531, ix484_a3_dup_619_Q, n_533,
n_534, n_535, ix484_a6_dup_616_Q, n_537, n_538, n_539, n_540, n_541,
O_dup_1375_aOUT, O_dup_1375_aIN, n_544, n_545, n_546, n_547, n_548,
n_549, ix484_a1_dup_621_Q, n_551, n_552, n_553, ix484_a5_dup_617_Q,
n_555, n_556, n_557, n_558, n_559, O_dup_1697_aOUT, O_dup_1697_aIN,
n_562, n_563, n_564, outregrd_aOUT, n_566, n3_aOUT, n_568, n_569,
outreg_val4_Q, n_571, progcntr_val4_Q, n_573, n_574, n_575, n_576,
n_577, n_578, n_579, I1_dup_810_aOUT, I1_dup_810_aIN, n_582, n_583,
n_584, n_585, O_dup_879_aOUT, n_587, n_588, ix484_a2_dup_620_Q,
n_590, n_591, n_592, ix484_a7_dup_615_Q, n_594, n_595, n_596, n_597,
n_598, O_dup_811_aIN1, n_600, n_601, n_602, O_dup_870_aOUT, n_604,
O_dup_873_aOUT, n_606, n_607, ix484_a4_dup_618_Q, n_609, n_610,
n_611, ix484_a0_dup_622_Q, n_613, n_614, n_615, n_616, n_617, instrregout4_Q,
instrregout4_aD, n_624, n_625, n_626, n_627, n_628, n_629, a_as_or3_aix1644_a_a32_aOUT,
instrregout4_aCLK, I0_dup_1401_aOUT, I0_dup_1401_aIN, n_634, n_635,
n_636, n_637, n_638, n_639, ix484_a3_dup_627_Q, n_641, n_642, n_643,
ix484_a6_dup_624_Q, n_645, n_646, n_647, n_648, n_649, O_dup_1403_aOUT,
O_dup_1403_aIN, n_652, n_653, n_654, n_655, n_656, n_657, ix484_a1_dup_629_Q,
n_659, n_660, n_661, ix484_a5_dup_625_Q, n_663, n_664, n_665, n_666,
n_667, O_dup_1705_aOUT, O_dup_1705_aIN, n_670, n_671, n_672, n_673,
n_674, n_675, outreg_val3_Q, n_677, progcntr_val3_Q, n_679, n_680,
n_681, n_682, n_683, n_684, n_685, I1_dup_813_aOUT, I1_dup_813_aIN,
n_688, n_689, n_690, n_691, n_692, n_693, ix484_a2_dup_628_Q, n_695,
n_696, n_697, ix484_a7_dup_623_Q, n_699, n_700, n_701, n_702, n_703,
O_dup_814_aIN1, n_705, n_706, n_707, n_708, n_709, n_710, ix484_a4_dup_626_Q,
n_712, n_713, n_714, ix484_a0_dup_630_Q, n_716, n_717, n_718, n_719,
n_720, instrregout3_Q, instrregout3_aD, n_727, n_728, n_729, n_730,
n_731, n_732, instrregout3_aCLK, I0_dup_1429_aOUT, I0_dup_1429_aIN,
n_736, n_737, n_738, n_739, n_740, n_741, ix484_a3_dup_635_Q, n_743,
n_744, n_745, ix484_a6_dup_632_Q, n_747, n_748, n_749, n_750, n_751,
O_dup_1431_aOUT, O_dup_1431_aIN, n_754, n_755, n_756, n_757, n_758,
n_759, ix484_a1_dup_637_Q, n_761, n_762, n_763, ix484_a5_dup_633_Q,
n_765, n_766, n_767, n_768, n_769, O_dup_1713_aOUT, O_dup_1713_aIN,
n_772, n_773, n_774, n_775, n_776, n_777, outreg_val2_Q, n_779,
progcntr_val2_Q, n_781, n_782, n_783, n_784, n_785, n_786, n_787,
I1_dup_816_aOUT, I1_dup_816_aIN, n_790, n_791, n_792, n_793, n_794,
n_795, ix484_a2_dup_636_Q, n_797, n_798, n_799, ix484_a7_dup_631_Q,
n_801, n_802, n_803, n_804, n_805, O_dup_817_aIN1, n_807, n_808,
n_809, n_810, n_811, n_812, ix484_a4_dup_634_Q, n_814, n_815, n_816,
ix484_a0_dup_638_Q, n_818, n_819, n_820, n_821, n_822, instrregout2_Q,
instrregout2_aD, n_829, n_830, n_831, n_832, n_833, n_834, instrregout2_aCLK,
I0_dup_1345_aOUT, I0_dup_1345_aIN, n_838, n_839, n_840, n_841, n_842,
n_843, ix484_a3_dup_611_Q, n_845, n_846, n_847, ix484_a6_dup_608_Q,
n_849, n_850, n_851, n_852, n_853, O_dup_1347_aOUT, O_dup_1347_aIN,
n_856, n_857, n_858, n_859, n_860, n_861, ix484_a1_dup_613_Q, n_863,
n_864, n_865, ix484_a5_dup_609_Q, n_867, n_868, n_869, n_870, n_871,
O_dup_1689_aOUT, O_dup_1689_aIN, n_874, n_875, n_876, n_877, n_878,
n_879, outreg_val5_Q, n_881, progcntr_val5_Q, n_883, n_884, n_885,
n_886, n_887, n_888, n_889, I1_dup_807_aOUT, I1_dup_807_aIN, n_892,
n_893, n_894, n_895, n_896, n_897, ix484_a2_dup_612_Q, n_899, n_900,
n_901, ix484_a7_dup_607_Q, n_903, n_904, n_905, n_906, n_907, O_dup_808_aIN1,
n_909, n_910, n_911, n_912, n_913, n_914, ix484_a4_dup_610_Q, n_916,
n_917, n_918, ix484_a0_dup_614_Q, n_920, n_921, n_922, n_923, n_924,
instrregout5_Q, instrregout5_aD, n_931, n_932, n_933, n_934, n_935,
n_936, instrregout5_aCLK, con1_current_state31_Q, con1_current_state31_aCLRN,
con1_current_state31_aD, n_946, n_947, n_948, opregwr_Q, n_950,
con1_current_state31_aCLK, con1_current_state32_Q, con1_current_state32_aCLRN,
con1_current_state32_aD, n_960, n_961, n_962, n_963, con1_current_state32_aCLK,
con1_modgen_63_nx10_aOUT, con1_modgen_63_nx10_aIN, n_967, n_968,
n_969, instrregout12_Q, n_971, n_972, instrregout11_Q, n_974, con1_current_state17_Q,
con1_current_state17_aCLRN, con1_current_state17_aD, n_982, n_983,
n_984, instrregout15_Q, n_986, n_987, con1_modgen_61_nx12_aOUT,
n_989, con1_current_state6_Q, n_991, con1_current_state17_aCLK,
I0_dup_1457_aOUT, I0_dup_1457_aIN, n_995, n_996, n_997, n_998, n_999,
n_1000, ix484_a3_dup_643_Q, n_1002, n_1003, n_1004, ix484_a6_dup_640_Q,
n_1006, n_1007, n_1008, n_1009, n_1010, O_dup_1459_aOUT, O_dup_1459_aIN,
n_1013, n_1014, n_1015, n_1016, n_1017, n_1018, ix484_a1_dup_645_Q,
n_1020, n_1021, n_1022, ix484_a5_dup_641_Q, n_1024, n_1025, n_1026,
n_1027, n_1028, O_dup_1721_aOUT, O_dup_1721_aIN, n_1031, n_1032,
n_1033, n_1034, n_1035, n_1036, outreg_val1_Q, n_1038, progcntr_val1_Q,
n_1040, n_1041, n_1042, n_1043, n_1044, n_1045, n_1046, I1_dup_819_aOUT,
I1_dup_819_aIN, n_1049, n_1050, n_1051, n_1052, n_1053, n_1054,
ix484_a2_dup_644_Q, n_1056, n_1057, n_1058, ix484_a7_dup_639_Q,
n_1060, n_1061, n_1062, n_1063, n_1064, O_dup_820_aIN1, n_1066,
n_1067, n_1068, n_1069, n_1070, n_1071, ix484_a4_dup_642_Q, n_1073,
n_1074, n_1075, ix484_a0_dup_646_Q, n_1077, n_1078, n_1079, n_1080,
n_1081, instrregout1_Q, instrregout1_aD, n_1088, n_1089, n_1090,
n_1091, n_1092, n_1093, instrregout1_aCLK, I0_dup_1485_aOUT, I0_dup_1485_aIN,
n_1097, n_1098, n_1099, n_1100, n_1101, n_1102, ix484_a3_dup_651_Q,
n_1104, n_1105, n_1106, ix484_a6_dup_648_Q, n_1108, n_1109, n_1110,
n_1111, n_1112, O_dup_1487_aOUT, O_dup_1487_aIN, n_1115, n_1116,
n_1117, n_1118, n_1119, n_1120, ix484_a1_dup_653_Q, n_1122, n_1123,
n_1124, ix484_a5_dup_649_Q, n_1126, n_1127, n_1128, n_1129, n_1130,
O_dup_1729_aOUT, O_dup_1729_aIN, n_1133, n_1134, n_1135, n_1136,
n_1137, n_1138, outreg_val0_Q, n_1140, progcntr_val0_Q, n_1142,
n_1143, n_1144, n_1145, n_1146, n_1147, n_1148, I1_dup_826_aOUT,
I1_dup_826_aIN, n_1151, n_1152, n_1153, n_1154, n_1155, n_1156,
ix484_a2_dup_652_Q, n_1158, n_1159, n_1160, ix484_a7_dup_647_Q,
n_1162, n_1163, n_1164, n_1165, n_1166, O_dup_827_aIN1, n_1168,
n_1169, n_1170, n_1171, n_1172, n_1173, ix484_a4_dup_650_Q, n_1175,
n_1176, n_1177, ix484_a0_dup_654_Q, n_1179, n_1180, n_1181, n_1182,
n_1183, instrregout0_Q, instrregout0_aD, n_1190, n_1191, n_1192,
n_1193, n_1194, n_1195, instrregout0_aCLK, I3_dup_673_aOUT, I3_dup_673_aIN,
n_1199, n_1200, n_1201, con1_current_state51_Q, n_1203, n_1204,
con1_current_state19_Q, n_1206, a_as_or3_aix1635_a_a32_aOUT, a_as_or3_aix1635_a_a32_aIN1,
n_1209, n_1210, n_1211, con1_current_state13_Q, n_1213, n_1214,
n_1215, n_1216, n_1218, con1_current_state48_Q, n_1220, ix484_a3_dup_651_aD,
n_1227, n_1228, n_1229, n_1230, n_1231, n_1232, ix484_a3_dup_651_aCLK,
ix484_a3_dup_651_aENA, n_1235, ix484_a6_dup_648_aD, n_1242, n_1243,
n_1244, n_1245, n_1246, n_1247, ix484_a6_dup_648_aCLK, ix484_a6_dup_648_aENA,
n_1250, ix484_a3_dup_643_aD, n_1257, n_1258, n_1259, n_1260, n_1261,
n_1262, ix484_a3_dup_643_aCLK, ix484_a3_dup_643_aENA, n_1265, ix484_a6_dup_640_aD,
n_1272, n_1273, n_1274, n_1275, n_1276, n_1277, ix484_a6_dup_640_aCLK,
ix484_a6_dup_640_aENA, n_1280, ix484_a3_dup_635_aD, n_1287, n_1288,
n_1289, n_1290, n_1291, n_1292, ix484_a3_dup_635_aCLK, ix484_a3_dup_635_aENA,
n_1295, ix484_a6_dup_632_aD, n_1302, n_1303, n_1304, n_1305, n_1306,
n_1307, ix484_a6_dup_632_aCLK, ix484_a6_dup_632_aENA, n_1310, ix484_a3_dup_627_aD,
n_1317, n_1318, n_1319, n_1320, n_1321, n_1322, ix484_a3_dup_627_aCLK,
ix484_a3_dup_627_aENA, n_1325, ix484_a6_dup_624_aD, n_1332, n_1333,
n_1334, n_1335, n_1336, n_1337, ix484_a6_dup_624_aCLK, ix484_a6_dup_624_aENA,
n_1340, ix484_a3_dup_619_aD, n_1347, n_1348, n_1349, n_1350, n_1351,
n_1352, ix484_a3_dup_619_aCLK, ix484_a3_dup_619_aENA, n_1355, ix484_a6_dup_616_aD,
n_1362, n_1363, n_1364, n_1365, n_1366, n_1367, ix484_a6_dup_616_aCLK,
ix484_a6_dup_616_aENA, n_1370, ix484_a3_dup_611_aD, n_1377, n_1378,
n_1379, n_1380, n_1381, n_1382, ix484_a3_dup_611_aCLK, ix484_a3_dup_611_aENA,
n_1385, ix484_a6_dup_608_aD, n_1392, n_1393, n_1394, n_1395, n_1396,
n_1397, ix484_a6_dup_608_aCLK, ix484_a6_dup_608_aENA, n_1400, I0_dup_1317_aOUT,
I0_dup_1317_aIN, n_1403, n_1404, n_1405, n_1406, n_1407, n_1408,
ix484_a3_dup_603_Q, n_1410, n_1411, n_1412, ix484_a6_dup_600_Q,
n_1414, n_1415, n_1416, n_1417, n_1418, O_dup_1319_aOUT, O_dup_1319_aIN,
n_1421, n_1422, n_1423, n_1424, n_1425, n_1426, ix484_a1_dup_605_Q,
n_1428, n_1429, n_1430, ix484_a5_dup_601_Q, n_1432, n_1433, n_1434,
n_1435, n_1436, O_dup_1681_aOUT, O_dup_1681_aIN, n_1439, n_1440,
n_1441, n_1442, n_1443, n_1444, outreg_val6_Q, n_1446, progcntr_val6_Q,
n_1448, n_1449, n_1450, n_1451, n_1452, n_1453, n_1454, I1_dup_804_aOUT,
I1_dup_804_aIN, n_1457, n_1458, n_1459, n_1460, n_1461, n_1462,
ix484_a2_dup_604_Q, n_1464, n_1465, n_1466, ix484_a7_dup_599_Q,
n_1468, n_1469, n_1470, n_1471, n_1472, O_dup_805_aIN1, n_1474,
n_1475, n_1476, n_1477, n_1478, n_1479, ix484_a4_dup_602_Q, n_1481,
n_1482, n_1483, ix484_a0_dup_606_Q, n_1485, n_1486, n_1487, n_1488,
n_1489, ix484_a3_dup_603_aD, n_1496, n_1497, n_1498, n_1499, n_1500,
n_1501, ix484_a3_dup_603_aCLK, ix484_a3_dup_603_aENA, n_1504, ix484_a6_dup_600_aD,
n_1511, n_1512, n_1513, n_1514, n_1515, n_1516, ix484_a6_dup_600_aCLK,
ix484_a6_dup_600_aENA, n_1519, I0_dup_1289_aOUT, I0_dup_1289_aIN,
n_1522, n_1523, n_1524, n_1525, n_1526, n_1527, ix484_a3_dup_595_Q,
n_1529, n_1530, n_1531, ix484_a6_dup_592_Q, n_1533, n_1534, n_1535,
n_1536, n_1537, O_dup_1291_aOUT, O_dup_1291_aIN, n_1540, n_1541,
n_1542, n_1543, n_1544, n_1545, ix484_a1_dup_597_Q, n_1547, n_1548,
n_1549, ix484_a5_dup_593_Q, n_1551, n_1552, n_1553, n_1554, n_1555,
O_dup_1673_aOUT, O_dup_1673_aIN, n_1558, n_1559, n_1560, n_1561,
n_1562, n_1563, outreg_val7_Q, n_1565, progcntr_val7_Q, n_1567,
n_1568, n_1569, n_1570, n_1571, n_1572, n_1573, I1_dup_801_aOUT,
I1_dup_801_aIN, n_1576, n_1577, n_1578, n_1579, n_1580, n_1581,
ix484_a2_dup_596_Q, n_1583, n_1584, n_1585, ix484_a7_dup_591_Q,
n_1587, n_1588, n_1589, n_1590, n_1591, O_dup_802_aIN1, n_1593,
n_1594, n_1595, n_1596, n_1597, n_1598, ix484_a4_dup_594_Q, n_1600,
n_1601, n_1602, ix484_a0_dup_598_Q, n_1604, n_1605, n_1606, n_1607,
n_1608, ix484_a3_dup_595_aD, n_1615, n_1616, n_1617, n_1618, n_1619,
n_1620, ix484_a3_dup_595_aCLK, ix484_a3_dup_595_aENA, n_1623, ix484_a6_dup_592_aD,
n_1630, n_1631, n_1632, n_1633, n_1634, n_1635, ix484_a6_dup_592_aCLK,
ix484_a6_dup_592_aENA, n_1638, I0_dup_1261_aOUT, I0_dup_1261_aIN,
n_1641, n_1642, n_1643, n_1644, n_1645, n_1646, ix484_a3_dup_587_Q,
n_1648, n_1649, n_1650, ix484_a6_dup_584_Q, n_1652, n_1653, n_1654,
n_1655, n_1656, O_dup_1263_aOUT, O_dup_1263_aIN, n_1659, n_1660,
n_1661, n_1662, n_1663, n_1664, ix484_a1_dup_589_Q, n_1666, n_1667,
n_1668, ix484_a5_dup_585_Q, n_1670, n_1671, n_1672, n_1673, n_1674,
O_dup_1665_aOUT, O_dup_1665_aIN, n_1677, n_1678, n_1679, n_1680,
n_1681, n_1682, outreg_val8_Q, n_1684, progcntr_val8_Q, n_1686,
n_1687, n_1688, n_1689, n_1690, n_1691, n_1692, I1_dup_798_aOUT,
I1_dup_798_aIN, n_1695, n_1696, n_1697, n_1698, n_1699, n_1700,
ix484_a2_dup_588_Q, n_1702, n_1703, n_1704, ix484_a7_dup_583_Q,
n_1706, n_1707, n_1708, n_1709, n_1710, O_dup_799_aIN1, n_1712,
n_1713, n_1714, n_1715, n_1716, n_1717, ix484_a4_dup_586_Q, n_1719,
n_1720, n_1721, ix484_a0_dup_590_Q, n_1723, n_1724, n_1725, n_1726,
n_1727, ix484_a3_dup_587_aD, n_1734, n_1735, n_1736, n_1737, n_1738,
n_1739, ix484_a3_dup_587_aCLK, ix484_a3_dup_587_aENA, n_1742, ix484_a6_dup_584_aD,
n_1749, n_1750, n_1751, n_1752, n_1753, n_1754, ix484_a6_dup_584_aCLK,
ix484_a6_dup_584_aENA, n_1757, I0_dup_1233_aOUT, I0_dup_1233_aIN,
n_1760, n_1761, n_1762, n_1763, n_1764, n_1765, ix484_a3_dup_579_Q,
n_1767, n_1768, n_1769, ix484_a6_dup_576_Q, n_1771, n_1772, n_1773,
n_1774, n_1775, O_dup_1235_aOUT, O_dup_1235_aIN, n_1778, n_1779,
n_1780, n_1781, n_1782, n_1783, ix484_a1_dup_581_Q, n_1785, n_1786,
n_1787, ix484_a5_dup_577_Q, n_1789, n_1790, n_1791, n_1792, n_1793,
O_dup_1657_aOUT, O_dup_1657_aIN, n_1796, n_1797, n_1798, n_1799,
n_1800, n_1801, outreg_val9_Q, n_1803, progcntr_val9_Q, n_1805,
n_1806, n_1807, n_1808, n_1809, n_1810, n_1811, I1_dup_795_aOUT,
I1_dup_795_aIN, n_1814, n_1815, n_1816, n_1817, n_1818, n_1819,
ix484_a2_dup_580_Q, n_1821, n_1822, n_1823, ix484_a7_dup_575_Q,
n_1825, n_1826, n_1827, n_1828, n_1829, O_dup_796_aIN1, n_1831,
n_1832, n_1833, n_1834, n_1835, n_1836, ix484_a4_dup_578_Q, n_1838,
n_1839, n_1840, ix484_a0_dup_582_Q, n_1842, n_1843, n_1844, n_1845,
n_1846, ix484_a3_dup_579_aD, n_1853, n_1854, n_1855, n_1856, n_1857,
n_1858, ix484_a3_dup_579_aCLK, ix484_a3_dup_579_aENA, n_1861, ix484_a6_dup_576_aD,
n_1868, n_1869, n_1870, n_1871, n_1872, n_1873, ix484_a6_dup_576_aCLK,
ix484_a6_dup_576_aENA, n_1876, I0_dup_1205_aOUT, I0_dup_1205_aIN,
n_1879, n_1880, n_1881, n_1882, n_1883, n_1884, ix484_a3_dup_571_Q,
n_1886, n_1887, n_1888, ix484_a6_dup_568_Q, n_1890, n_1891, n_1892,
n_1893, n_1894, O_dup_1207_aOUT, O_dup_1207_aIN, n_1897, n_1898,
n_1899, n_1900, n_1901, n_1902, ix484_a1_dup_573_Q, n_1904, n_1905,
n_1906, ix484_a5_dup_569_Q, n_1908, n_1909, n_1910, n_1911, n_1912,
O_dup_1649_aOUT, O_dup_1649_aIN, n_1915, n_1916, n_1917, n_1918,
n_1919, n_1920, outreg_val10_Q, n_1922, progcntr_val10_Q, n_1924,
n_1925, n_1926, n_1927, n_1928, n_1929, n_1930, I1_dup_792_aOUT,
I1_dup_792_aIN, n_1933, n_1934, n_1935, n_1936, n_1937, n_1938,
ix484_a2_dup_572_Q, n_1940, n_1941, n_1942, ix484_a7_dup_567_Q,
n_1944, n_1945, n_1946, n_1947, n_1948, O_dup_793_aIN1, n_1950,
n_1951, n_1952, n_1953, n_1954, n_1955, ix484_a4_dup_570_Q, n_1957,
n_1958, n_1959, ix484_a0_dup_574_Q, n_1961, n_1962, n_1963, n_1964,
n_1965, ix484_a3_dup_571_aD, n_1972, n_1973, n_1974, n_1975, n_1976,
n_1977, ix484_a3_dup_571_aCLK, ix484_a3_dup_571_aENA, n_1980, ix484_a6_dup_568_aD,
n_1987, n_1988, n_1989, n_1990, n_1991, n_1992, ix484_a6_dup_568_aCLK,
ix484_a6_dup_568_aENA, n_1995, I0_dup_1177_aOUT, I0_dup_1177_aIN,
n_1998, n_1999, n_2000, n_2001, n_2002, n_2003, ix484_a3_dup_563_Q,
n_2005, n_2006, n_2007, ix484_a6_dup_560_Q, n_2009, n_2010, n_2011,
n_2012, n_2013, O_dup_1179_aOUT, O_dup_1179_aIN, n_2016, n_2017,
n_2018, n_2019, n_2020, n_2021, ix484_a1_dup_565_Q, n_2023, n_2024,
n_2025, ix484_a5_dup_561_Q, n_2027, n_2028, n_2029, n_2030, n_2031,
O_dup_1641_aOUT, O_dup_1641_aIN, n_2034, n_2035, n_2036, n_2037,
n_2038, n_2039, outreg_val11_Q, n_2041, progcntr_val11_Q, n_2043,
n_2044, n_2045, n_2046, n_2047, n_2048, n_2049, I1_dup_789_aOUT,
I1_dup_789_aIN, n_2052, n_2053, n_2054, n_2055, n_2056, n_2057,
ix484_a2_dup_564_Q, n_2059, n_2060, n_2061, ix484_a7_dup_559_Q,
n_2063, n_2064, n_2065, n_2066, n_2067, O_dup_790_aIN1, n_2069,
n_2070, n_2071, n_2072, n_2073, n_2074, ix484_a4_dup_562_Q, n_2076,
n_2077, n_2078, ix484_a0_dup_566_Q, n_2080, n_2081, n_2082, n_2083,
n_2084, ix484_a3_dup_563_aD, n_2091, n_2092, n_2093, n_2094, n_2095,
n_2096, ix484_a3_dup_563_aCLK, ix484_a3_dup_563_aENA, n_2099, ix484_a6_dup_560_aD,
n_2106, n_2107, n_2108, n_2109, n_2110, n_2111, ix484_a6_dup_560_aCLK,
ix484_a6_dup_560_aENA, n_2114, I0_dup_1149_aOUT, I0_dup_1149_aIN,
n_2117, n_2118, n_2119, n_2120, n_2121, n_2122, ix484_a3_dup_555_Q,
n_2124, n_2125, n_2126, ix484_a6_dup_552_Q, n_2128, n_2129, n_2130,
n_2131, n_2132, O_dup_1151_aOUT, O_dup_1151_aIN, n_2135, n_2136,
n_2137, n_2138, n_2139, n_2140, ix484_a1_dup_557_Q, n_2142, n_2143,
n_2144, ix484_a5_dup_553_Q, n_2146, n_2147, n_2148, n_2149, n_2150,
O_dup_1633_aOUT, O_dup_1633_aIN, n_2153, n_2154, n_2155, n_2156,
n_2157, n_2158, outreg_val12_Q, n_2160, progcntr_val12_Q, n_2162,
n_2163, n_2164, n_2165, n_2166, n_2167, n_2168, I1_dup_786_aOUT,
I1_dup_786_aIN, n_2171, n_2172, n_2173, n_2174, n_2175, n_2176,
ix484_a2_dup_556_Q, n_2178, n_2179, n_2180, ix484_a7_dup_551_Q,
n_2182, n_2183, n_2184, n_2185, n_2186, O_dup_787_aIN1, n_2188,
n_2189, n_2190, n_2191, n_2192, n_2193, ix484_a4_dup_554_Q, n_2195,
n_2196, n_2197, ix484_a0_dup_558_Q, n_2199, n_2200, n_2201, n_2202,
n_2203, ix484_a3_dup_555_aD, n_2210, n_2211, n_2212, n_2213, n_2214,
n_2215, ix484_a3_dup_555_aCLK, ix484_a3_dup_555_aENA, n_2218, ix484_a6_dup_552_aD,
n_2225, n_2226, n_2227, n_2228, n_2229, n_2230, ix484_a6_dup_552_aCLK,
ix484_a6_dup_552_aENA, n_2233, I0_dup_1121_aOUT, I0_dup_1121_aIN,
n_2236, n_2237, n_2238, n_2239, n_2240, n_2241, ix484_a3_dup_547_Q,
n_2243, n_2244, n_2245, ix484_a6_dup_544_Q, n_2247, n_2248, n_2249,
n_2250, n_2251, O_dup_1123_aOUT, O_dup_1123_aIN, n_2254, n_2255,
n_2256, n_2257, n_2258, n_2259, ix484_a1_dup_549_Q, n_2261, n_2262,
n_2263, ix484_a5_dup_545_Q, n_2265, n_2266, n_2267, n_2268, n_2269,
O_dup_1625_aOUT, O_dup_1625_aIN, n_2272, n_2273, n_2274, n_2275,
n_2276, n_2277, outreg_val13_Q, n_2279, progcntr_val13_Q, n_2281,
n_2282, n_2283, n_2284, n_2285, n_2286, n_2287, I1_dup_783_aOUT,
I1_dup_783_aIN, n_2290, n_2291, n_2292, n_2293, n_2294, n_2295,
ix484_a2_dup_548_Q, n_2297, n_2298, n_2299, ix484_a7_dup_543_Q,
n_2301, n_2302, n_2303, n_2304, n_2305, O_dup_784_aIN1, n_2307,
n_2308, n_2309, n_2310, n_2311, n_2312, ix484_a4_dup_546_Q, n_2314,
n_2315, n_2316, ix484_a0_dup_550_Q, n_2318, n_2319, n_2320, n_2321,
n_2322, ix484_a3_dup_547_aD, n_2329, n_2330, n_2331, n_2332, n_2333,
n_2334, ix484_a3_dup_547_aCLK, ix484_a3_dup_547_aENA, n_2337, ix484_a6_dup_544_aD,
n_2344, n_2345, n_2346, n_2347, n_2348, n_2349, ix484_a6_dup_544_aCLK,
ix484_a6_dup_544_aENA, n_2352, I0_dup_1093_aOUT, I0_dup_1093_aIN,
n_2355, n_2356, n_2357, n_2358, n_2359, n_2360, ix484_a3_dup_539_Q,
n_2362, n_2363, n_2364, ix484_a6_dup_536_Q, n_2366, n_2367, n_2368,
n_2369, n_2370, O_dup_1095_aOUT, O_dup_1095_aIN, n_2373, n_2374,
n_2375, n_2376, n_2377, n_2378, ix484_a1_dup_541_Q, n_2380, n_2381,
n_2382, ix484_a5_dup_537_Q, n_2384, n_2385, n_2386, n_2387, n_2388,
O_dup_1617_aOUT, O_dup_1617_aIN, n_2391, n_2392, n_2393, n_2394,
n_2395, n_2396, outreg_val14_Q, n_2398, progcntr_val14_Q, n_2400,
n_2401, n_2402, n_2403, n_2404, n_2405, n_2406, I1_dup_780_aOUT,
I1_dup_780_aIN, n_2409, n_2410, n_2411, n_2412, n_2413, n_2414,
ix484_a2_dup_540_Q, n_2416, n_2417, n_2418, ix484_a7_dup_535_Q,
n_2420, n_2421, n_2422, n_2423, n_2424, O_dup_781_aIN1, n_2426,
n_2427, n_2428, n_2429, n_2430, n_2431, ix484_a4_dup_538_Q, n_2433,
n_2434, n_2435, ix484_a0_dup_542_Q, n_2437, n_2438, n_2439, n_2440,
n_2441, ix484_a3_dup_539_aD, n_2448, n_2449, n_2450, n_2451, n_2452,
n_2453, ix484_a3_dup_539_aCLK, ix484_a3_dup_539_aENA, n_2456, ix484_a6_dup_536_aD,
n_2463, n_2464, n_2465, n_2466, n_2467, n_2468, ix484_a6_dup_536_aCLK,
ix484_a6_dup_536_aENA, n_2471, instrregout13_Q, instrregout13_aD,
n_2478, n_2479, n_2480, n_2481, n_2482, n_2483, instrregout13_aCLK,
instrregout14_Q, instrregout14_aD, n_2491, n_2492, n_2493, n_2494,
n_2495, n_2496, instrregout14_aCLK, con1_current_state18_Q, con1_current_state18_aCLRN,
con1_current_state18_aD, n_2505, n_2506, n_2507, n_2508, con1_current_state18_aCLK,
I0_dup_1065_aOUT, I0_dup_1065_aIN, n_2512, n_2513, n_2514, n_2515,
n_2516, n_2517, ix484_a3_Q, n_2519, n_2520, n_2521, ix484_a6_Q,
n_2523, n_2524, n_2525, n_2526, n_2527, O_dup_1067_aOUT, O_dup_1067_aIN,
n_2530, n_2531, n_2532, n_2533, n_2534, n_2535, ix484_a1_dup_533_Q,
n_2537, n_2538, n_2539, ix484_a5_Q, n_2541, n_2542, n_2543, n_2544,
n_2545, O_dup_1609_aOUT, O_dup_1609_aIN, n_2548, n_2549, n_2550,
n_2551, n_2552, n_2553, outreg_val15_Q, n_2555, progcntr_val15_Q,
n_2557, n_2558, n_2559, n_2560, n_2561, n_2562, n_2563, I1_dup_777_aOUT,
I1_dup_777_aIN, n_2566, n_2567, n_2568, n_2569, n_2570, n_2571,
ix484_a2_dup_532_Q, n_2573, n_2574, n_2575, ix484_a7_Q, n_2577,
n_2578, n_2579, n_2580, n_2581, O_dup_778_aIN1, n_2583, n_2584,
n_2585, n_2586, n_2587, n_2588, ix484_a4_Q, n_2590, n_2591, n_2592,
ix484_a0_dup_534_Q, n_2594, n_2595, n_2596, n_2597, n_2598, ix484_a3_aD,
n_2605, n_2606, n_2607, n_2608, n_2609, n_2610, ix484_a3_aCLK, ix484_a3_aENA,
n_2613, ix484_a6_aD, n_2620, n_2621, n_2622, n_2623, n_2624, n_2625,
ix484_a6_aCLK, ix484_a6_aENA, n_2628, opreg_val0_Q, opreg_val0_aD,
n_2635, n_2636, n_2637, n_2638, n_2639, n_2640, opreg_val0_aCLK,
comp1_modgen_56_l1_l0_c_int1_aOUT, comp1_modgen_56_l1_l0_c_int1_aIN,
n_2644, n_2645, n_2646, n_2647, n_2648, n_2649, opreg_val1_Q, opreg_val1_aD,
n_2656, n_2657, n_2658, n_2659, n_2660, n_2661, opreg_val1_aCLK,
comp1_modgen_56_l1_l0_c_int2_aOUT, comp1_modgen_56_l1_l0_c_int2_aIN,
n_2665, n_2666, n_2667, n_2668, n_2669, n_2670, n_2671, n_2672,
n_2673, n_2674, n_2675, opreg_val2_Q, opreg_val2_aD, n_2682, n_2683,
n_2684, n_2685, n_2686, n_2687, opreg_val2_aCLK, comp1_modgen_56_l1_l0_c_int3_aOUT,
comp1_modgen_56_l1_l0_c_int3_aIN, n_2691, n_2692, n_2693, n_2694,
n_2695, n_2696, n_2697, n_2698, n_2699, n_2700, n_2701, opreg_val3_Q,
opreg_val3_aD, n_2708, n_2709, n_2710, n_2711, n_2712, n_2713, opreg_val3_aCLK,
comp1_modgen_56_l1_l0_c_int4_aOUT, comp1_modgen_56_l1_l0_c_int4_aIN,
n_2717, n_2718, n_2719, n_2720, n_2721, n_2722, n_2723, n_2724,
n_2725, n_2726, n_2727, opreg_val4_Q, opreg_val4_aD, n_2734, n_2735,
n_2736, n_2737, n_2738, n_2739, opreg_val4_aCLK, comp1_modgen_56_l1_l0_c_int5_aOUT,
comp1_modgen_56_l1_l0_c_int5_aIN, n_2743, n_2744, n_2745, n_2746,
n_2747, n_2748, n_2749, n_2750, n_2751, n_2752, n_2753, opreg_val5_Q,
opreg_val5_aD, n_2760, n_2761, n_2762, n_2763, n_2764, n_2765, opreg_val5_aCLK,
comp1_modgen_56_l1_l0_c_int6_aOUT, comp1_modgen_56_l1_l0_c_int6_aIN,
n_2769, n_2770, n_2771, n_2772, n_2773, n_2774, n_2775, n_2776,
n_2777, n_2778, n_2779, opreg_val6_Q, opreg_val6_aD, n_2786, n_2787,
n_2788, n_2789, n_2790, n_2791, opreg_val6_aCLK, comp1_modgen_56_l1_l0_c_int7_aOUT,
comp1_modgen_56_l1_l0_c_int7_aIN, n_2795, n_2796, n_2797, n_2798,
n_2799, n_2800, n_2801, n_2802, n_2803, n_2804, n_2805, opreg_val7_Q,
opreg_val7_aD, n_2812, n_2813, n_2814, n_2815, n_2816, n_2817, opreg_val7_aCLK,
comp1_modgen_56_l1_l0_c_int8_aOUT, comp1_modgen_56_l1_l0_c_int8_aIN,
n_2821, n_2822, n_2823, n_2824, n_2825, n_2826, n_2827, n_2828,
n_2829, n_2830, n_2831, opreg_val8_Q, opreg_val8_aD, n_2838, n_2839,
n_2840, n_2841, n_2842, n_2843, opreg_val8_aCLK, comp1_modgen_56_l1_l0_c_int9_aOUT,
comp1_modgen_56_l1_l0_c_int9_aIN, n_2847, n_2848, n_2849, n_2850,
n_2851, n_2852, n_2853, n_2854, n_2855, n_2856, n_2857, opreg_val9_Q,
opreg_val9_aD, n_2864, n_2865, n_2866, n_2867, n_2868, n_2869, opreg_val9_aCLK,
comp1_modgen_56_l1_l0_c_int10_aOUT, comp1_modgen_56_l1_l0_c_int10_aIN,
n_2873, n_2874, n_2875, n_2876, n_2877, n_2878, n_2879, n_2880,
n_2881, n_2882, n_2883, opreg_val10_Q, opreg_val10_aD, n_2890, n_2891,
n_2892, n_2893, n_2894, n_2895, opreg_val10_aCLK, comp1_modgen_56_l1_l0_c_int11_aOUT,
comp1_modgen_56_l1_l0_c_int11_aIN, n_2899, n_2900, n_2901, n_2902,
n_2903, n_2904, n_2905, n_2906, n_2907, n_2908, n_2909, opreg_val11_Q,
opreg_val11_aD, n_2916, n_2917, n_2918, n_2919, n_2920, n_2921,
opreg_val11_aCLK, comp1_modgen_56_l1_l0_c_int12_aOUT, comp1_modgen_56_l1_l0_c_int12_aIN,
n_2925, n_2926, n_2927, n_2928, n_2929, n_2930, n_2931, n_2932,
n_2933, n_2934, n_2935, opreg_val12_Q, opreg_val12_aD, n_2942, n_2943,
n_2944, n_2945, n_2946, n_2947, opreg_val12_aCLK, comp1_modgen_56_l1_l0_c_int13_aOUT,
comp1_modgen_56_l1_l0_c_int13_aIN, n_2951, n_2952, n_2953, n_2954,
n_2955, n_2956, n_2957, n_2958, n_2959, n_2960, n_2961, opreg_val13_Q,
opreg_val13_aD, n_2968, n_2969, n_2970, n_2971, n_2972, n_2973,
opreg_val13_aCLK, comp1_modgen_56_l1_l0_c_int14_aOUT, comp1_modgen_56_l1_l0_c_int14_aIN,
n_2977, n_2978, n_2979, n_2980, n_2981, n_2982, n_2983, n_2984,
n_2985, n_2986, n_2987, opreg_val14_Q, opreg_val14_aD, n_2994, n_2995,
n_2996, n_2997, n_2998, n_2999, opreg_val14_aCLK, comp1_modgen_56_l1_l0_c_int15_aOUT,
comp1_modgen_56_l1_l0_c_int15_aIN, n_3003, n_3004, n_3005, n_3006,
n_3007, n_3008, n_3009, n_3010, n_3011, n_3012, n_3013, opreg_val15_Q,
opreg_val15_aD, n_3020, n_3021, n_3022, n_3023, n_3024, n_3025,
opreg_val15_aCLK, a_as_or2_a77_a_a30_aOUT_aNOT, a_as_or2_a77_a_a30_aOUT,
n_3029, a_as_or2_a77_a_a30_aIN1, n_3031, n_3032, n_3033, n_3034,
n_3035, n_3036, n_3037, n_3038, n_3039, n_3040, n_3041, a_a289_aOUT,
a_a289_aIN, n_3044, n_3045, n_3046, n_3047, n_3048, n_3049, n_3050,
n_3051, n_3052, n_3053, n_3054, n_3055, n_3056, n_3057, n_3058,
n_3059, n_3060, n_3061, n_3062, n_3063, n_3064, n_3065, a_a290_aOUT,
a_a290_aIN, n_3068, n_3069, n_3070, n_3071, n_3072, n_3073, n_3074,
n_3075, n_3076, n_3077, n_3078, n_3079, n_3080, n_3081, n_3082,
n_3083, n_3084, n_3085, n_3086, n_3087, n_3088, n_3089, a_a291_aOUT,
a_a291_aIN, n_3092, n_3093, n_3094, n_3095, n_3096, n_3097, n_3098,
n_3099, n_3100, n_3101, n_3102, n_3103, n_3104, n_3105, n_3106,
n_3107, n_3108, n_3109, n_3110, n_3111, n_3112, n_3113, comp1_modgen_54_eqo1_aOUT,
comp1_modgen_54_eqo1_aIN1, n_3116, n_3117, n_3118, n_3119, n_3120,
n_3121, n_3122, n_3123, n_3124, n_3125, n_3126, n_3127, n_3128,
n_3129, n_3130, n_3131, n_3132, n_3133, n_3134, n_3135, n_3136,
n_3137, a_a286_aOUT, a_a286_aIN, n_3140, n_3141, n_3142, n_3143,
n_3144, n_3145, n_3146, n_3147, n_3148, n_3149, n_3150, n_3151,
n_3152, n_3153, n_3154, n_3155, n_3156, n_3157, n_3158, n_3159,
n_3160, n_3161, a_a287_aOUT, a_a287_aIN, n_3164, n_3165, n_3166,
n_3167, n_3168, n_3169, n_3170, n_3171, n_3172, n_3173, n_3174,
n_3175, n_3176, n_3177, n_3178, n_3179, n_3180, n_3181, n_3182,
n_3183, n_3184, n_3185, a_a288_aOUT, a_a288_aIN, n_3188, n_3189,
n_3190, n_3191, n_3192, n_3193, n_3194, n_3195, n_3196, n_3197,
n_3198, n_3199, n_3200, n_3201, n_3202, n_3203, n_3204, n_3205,
n_3206, n_3207, n_3208, n_3209, comp1_modgen_54_eqo0_aOUT, comp1_modgen_54_eqo0_aIN1,
n_3212, n_3213, n_3214, n_3215, n_3216, n_3217, n_3218, n_3219,
n_3220, n_3221, n_3222, n_3223, n_3224, n_3225, n_3226, n_3227,
n_3228, n_3229, n_3230, n_3231, n_3232, n_3233, comp1_nx38_aOUT,
comp1_nx38_aIN, n_3236, n_3237, n_3238, opregrd_aOUT, n_3240, n_3241,
n_3242, n_3243, n_3244, n_3245, con1_current_state33_Q, con1_current_state33_aCLRN,
con1_current_state33_aD, n_3253, n_3254, n_3255, n_3256, n_3257,
con1_current_state33_aCLK, ix484_a1_dup_653_aD, n_3265, n_3266,
n_3267, n_3268, n_3269, n_3270, ix484_a1_dup_653_aCLK, ix484_a1_dup_653_aENA,
n_3273, ix484_a5_dup_649_aD, n_3280, n_3281, n_3282, n_3283, n_3284,
n_3285, ix484_a5_dup_649_aCLK, ix484_a5_dup_649_aENA, n_3288, ix484_a1_dup_645_aD,
n_3295, n_3296, n_3297, n_3298, n_3299, n_3300, ix484_a1_dup_645_aCLK,
ix484_a1_dup_645_aENA, n_3303, ix484_a5_dup_641_aD, n_3310, n_3311,
n_3312, n_3313, n_3314, n_3315, ix484_a5_dup_641_aCLK, ix484_a5_dup_641_aENA,
n_3318, ix484_a1_dup_637_aD, n_3325, n_3326, n_3327, n_3328, n_3329,
n_3330, ix484_a1_dup_637_aCLK, ix484_a1_dup_637_aENA, n_3333, ix484_a5_dup_633_aD,
n_3340, n_3341, n_3342, n_3343, n_3344, n_3345, ix484_a5_dup_633_aCLK,
ix484_a5_dup_633_aENA, n_3348, ix484_a1_dup_629_aD, n_3355, n_3356,
n_3357, n_3358, n_3359, n_3360, ix484_a1_dup_629_aCLK, ix484_a1_dup_629_aENA,
n_3363, ix484_a5_dup_625_aD, n_3370, n_3371, n_3372, n_3373, n_3374,
n_3375, ix484_a5_dup_625_aCLK, ix484_a5_dup_625_aENA, n_3378, ix484_a1_dup_621_aD,
n_3385, n_3386, n_3387, n_3388, n_3389, n_3390, ix484_a1_dup_621_aCLK,
ix484_a1_dup_621_aENA, n_3393, ix484_a5_dup_617_aD, n_3400, n_3401,
n_3402, n_3403, n_3404, n_3405, ix484_a5_dup_617_aCLK, ix484_a5_dup_617_aENA,
n_3408, ix484_a1_dup_613_aD, n_3415, n_3416, n_3417, n_3418, n_3419,
n_3420, ix484_a1_dup_613_aCLK, ix484_a1_dup_613_aENA, n_3423, ix484_a5_dup_609_aD,
n_3430, n_3431, n_3432, n_3433, n_3434, n_3435, ix484_a5_dup_609_aCLK,
ix484_a5_dup_609_aENA, n_3438, ix484_a1_dup_605_aD, n_3445, n_3446,
n_3447, n_3448, n_3449, n_3450, ix484_a1_dup_605_aCLK, ix484_a1_dup_605_aENA,
n_3453, ix484_a5_dup_601_aD, n_3460, n_3461, n_3462, n_3463, n_3464,
n_3465, ix484_a5_dup_601_aCLK, ix484_a5_dup_601_aENA, n_3468, ix484_a1_dup_597_aD,
n_3475, n_3476, n_3477, n_3478, n_3479, n_3480, ix484_a1_dup_597_aCLK,
ix484_a1_dup_597_aENA, n_3483, ix484_a5_dup_593_aD, n_3490, n_3491,
n_3492, n_3493, n_3494, n_3495, ix484_a5_dup_593_aCLK, ix484_a5_dup_593_aENA,
n_3498, ix484_a1_dup_589_aD, n_3505, n_3506, n_3507, n_3508, n_3509,
n_3510, ix484_a1_dup_589_aCLK, ix484_a1_dup_589_aENA, n_3513, ix484_a5_dup_585_aD,
n_3520, n_3521, n_3522, n_3523, n_3524, n_3525, ix484_a5_dup_585_aCLK,
ix484_a5_dup_585_aENA, n_3528, ix484_a1_dup_581_aD, n_3535, n_3536,
n_3537, n_3538, n_3539, n_3540, ix484_a1_dup_581_aCLK, ix484_a1_dup_581_aENA,
n_3543, ix484_a5_dup_577_aD, n_3550, n_3551, n_3552, n_3553, n_3554,
n_3555, ix484_a5_dup_577_aCLK, ix484_a5_dup_577_aENA, n_3558, ix484_a1_dup_573_aD,
n_3565, n_3566, n_3567, n_3568, n_3569, n_3570, ix484_a1_dup_573_aCLK,
ix484_a1_dup_573_aENA, n_3573, ix484_a5_dup_569_aD, n_3580, n_3581,
n_3582, n_3583, n_3584, n_3585, ix484_a5_dup_569_aCLK, ix484_a5_dup_569_aENA,
n_3588, ix484_a1_dup_565_aD, n_3595, n_3596, n_3597, n_3598, n_3599,
n_3600, ix484_a1_dup_565_aCLK, ix484_a1_dup_565_aENA, n_3603, ix484_a5_dup_561_aD,
n_3610, n_3611, n_3612, n_3613, n_3614, n_3615, ix484_a5_dup_561_aCLK,
ix484_a5_dup_561_aENA, n_3618, ix484_a1_dup_557_aD, n_3625, n_3626,
n_3627, n_3628, n_3629, n_3630, ix484_a1_dup_557_aCLK, ix484_a1_dup_557_aENA,
n_3633, ix484_a5_dup_553_aD, n_3640, n_3641, n_3642, n_3643, n_3644,
n_3645, ix484_a5_dup_553_aCLK, ix484_a5_dup_553_aENA, n_3648, ix484_a1_dup_549_aD,
n_3655, n_3656, n_3657, n_3658, n_3659, n_3660, ix484_a1_dup_549_aCLK,
ix484_a1_dup_549_aENA, n_3663, ix484_a5_dup_545_aD, n_3670, n_3671,
n_3672, n_3673, n_3674, n_3675, ix484_a5_dup_545_aCLK, ix484_a5_dup_545_aENA,
n_3678, ix484_a1_dup_541_aD, n_3685, n_3686, n_3687, n_3688, n_3689,
n_3690, ix484_a1_dup_541_aCLK, ix484_a1_dup_541_aENA, n_3693, ix484_a5_dup_537_aD,
n_3700, n_3701, n_3702, n_3703, n_3704, n_3705, ix484_a5_dup_537_aCLK,
ix484_a5_dup_537_aENA, n_3708, con1_current_state49_Q, con1_current_state49_aCLRN,
con1_current_state49_aD, n_3716, n_3717, n_3718, I3_dup_732_aOUT,
n_3720, n_3721, n_3722, n_3723, con1_current_state49_aCLK, con1_current_state19_aCLRN,
con1_current_state19_aD, n_3731, n_3732, n_3733, n_3734, con1_current_state19_aCLK,
con1_current_state51_aCLRN, con1_current_state51_aD, n_3742, n_3743,
n_3744, con1_current_state50_Q, n_3746, con1_current_state51_aCLK,
ix484_a1_dup_533_aD, n_3754, n_3755, n_3756, n_3757, n_3758, n_3759,
ix484_a1_dup_533_aCLK, ix484_a1_dup_533_aENA, n_3762, ix484_a5_aD,
n_3769, n_3770, n_3771, n_3772, n_3773, n_3774, ix484_a5_aCLK, ix484_a5_aENA,
n_3777, instrregout11_aD, n_3783, n_3784, n_3785, n_3786, n_3787,
n_3788, instrregout11_aCLK, con1_current_state44_Q, con1_current_state44_aCLRN,
con1_current_state44_aD, n_3797, n_3798, n_3799, n_3800, n_3801,
n_3802, n_3803, con1_current_state44_aCLK, con1_current_state39_Q,
con1_current_state39_aCLRN, con1_current_state39_aD, n_3812, n_3813,
n_3814, n_3815, n_3816, n_3817, n_3818, con1_current_state39_aCLK,
con1_current_state34_Q, con1_current_state34_aCLRN, con1_current_state34_aD,
n_3827, n_3828, n_3829, n_3830, con1_current_state34_aCLK, I2_dup_689_aOUT,
I2_dup_689_aIN, n_3834, n_3835, n_3836, con1_current_state38_Q,
n_3838, n_3839, con1_current_state43_Q, n_3841, a_as_or3_aix1652_a_a32_aOUT,
a_as_or3_aix1652_a_a32_aIN1, n_3844, n_3845, n_3846, con1_current_state23_Q,
n_3848, n_3849, n_3850, n_3851, n_3852, I2_dup_681_aOUT, n_3854,
progcntr_val0_aD, n_3860, n_3861, n_3862, n_3863, n_3864, n_3865,
progcntr_val0_aCLK, O_dup_914_aOUT, O_dup_914_aIN, n_3869, n_3870,
n_3871, con1_current_state21_Q, n_3873, n_3874, n_3875, I2_dup_679_aOUT,
I2_dup_679_aIN, n_3878, n_3879, n_3880, con1_current_state1_Q, n_3882,
n_3883, n_3884, n_3885, n_3886, n_3887, n_3888, a_as_or3_aix1642_a_a32_aOUT,
a_as_or3_aix1642_a_a32_aIN1, n_3891, n_3892, n_3893, n_3894, n_3895,
n_3896, n_3897, n_3898, alu1_nx191_aOUT, alu1_nx191_aIN, n_3901,
n_3902, n_3903, n_3904, n4_aOUT, n4_aIN, n_3907, n_3908, n_3909,
n_3910, n_3911, n_3912, n_3913, n_3914, n_3915, alusel2_aOUT, alusel2_aIN,
n_3918, n_3919, n_3920, n_3921, n_3922, n_3923, n_3924, I3_dup_696_aOUT,
n_3926, n_3927, n_3928, O_dup_867_aOUT, O_dup_867_aIN, n_3931, n_3932,
n_3933, n_3934, n_3935, con1_current_state0_aQ_aNOT, n_3937, I1_dup_669_aOUT,
I1_dup_669_aIN, n_3940, n_3941, n_3942, n_3943, n_3944, alusel0_aOUT,
alusel0_aIN, n_3947, n_3948, n_3949, n_3950, n_3951, n_3952, n_3953,
n_3954, outreg_val0_aD, n_3960, n_3961, n_3962, n_3963, n_3964,
n_3965, n_3966, n_3967, n_3968, outreg_val0_aCLK, progcntr_val1_aD,
n_3975, n_3976, n_3977, n_3978, n_3979, n_3980, progcntr_val1_aCLK,
alu1_nx190_aOUT, alu1_nx190_aIN, n_3984, n_3985, n_3986, n_3987,
n_3988, n_3989, n_3990, n_3991, I1_dup_668_aOUT, I1_dup_668_aIN,
n_3994, n_3995, n_3996, n_3997, n_3998, outreg_val1_aD, n_4004,
n_4005, n_4006, n_4007, n_4008, n_4009, n_4010, n_4011, n_4012,
outreg_val1_aCLK, progcntr_val2_aD, n_4019, n_4020, n_4021, n_4022,
n_4023, n_4024, progcntr_val2_aCLK, alu1_modgen_34_l1_l0_c_int2_aOUT,
alu1_modgen_34_l1_l0_c_int2_aIN, n_4028, n_4029, n_4030, n_4031,
n_4032, alu1_nx189_aOUT, alu1_nx189_aIN, n_4035, n_4036, n_4037,
n_4038, n_4039, n_4040, n_4041, n_4042, I1_dup_667_aOUT, I1_dup_667_aIN,
n_4045, n_4046, n_4047, n_4048, n_4049, outreg_val2_aD, n_4055,
n_4056, n_4057, n_4058, n_4059, n_4060, n_4061, n_4062, n_4063,
outreg_val2_aCLK, progcntr_val3_aD, n_4070, n_4071, n_4072, n_4073,
n_4074, n_4075, progcntr_val3_aCLK, alu1_modgen_34_l1_l0_c_int3_aOUT,
alu1_modgen_34_l1_l0_c_int3_aIN, n_4079, n_4080, n_4081, n_4082,
n_4083, alu1_nx188_aOUT, alu1_nx188_aIN, n_4086, n_4087, n_4088,
n_4089, n_4090, n_4091, n_4092, n_4093, I1_dup_666_aOUT, I1_dup_666_aIN,
n_4096, n_4097, n_4098, n_4099, n_4100, outreg_val3_aD, n_4106,
n_4107, n_4108, n_4109, n_4110, n_4111, n_4112, n_4113, n_4114,
outreg_val3_aCLK, progcntr_val4_aD, n_4121, n_4122, n_4123, n_4124,
n_4125, n_4126, progcntr_val4_aCLK, alu1_modgen_34_l1_l0_c_int4_aOUT,
alu1_modgen_34_l1_l0_c_int4_aIN, n_4130, n_4131, n_4132, n_4133,
n_4134, alu1_nx187_aOUT, alu1_nx187_aIN, n_4137, n_4138, n_4139,
n_4140, n_4141, n_4142, n_4143, n_4144, I1_dup_665_aOUT, I1_dup_665_aIN,
n_4147, n_4148, n_4149, n_4150, n_4151, outreg_val4_aD, n_4157,
n_4158, n_4159, n_4160, n_4161, n_4162, n_4163, n_4164, n_4165,
outreg_val4_aCLK, progcntr_val5_aD, n_4172, n_4173, n_4174, n_4175,
n_4176, n_4177, progcntr_val5_aCLK, alu1_modgen_34_l1_l0_c_int5_aOUT,
alu1_modgen_34_l1_l0_c_int5_aIN, n_4181, n_4182, n_4183, n_4184,
n_4185, alu1_nx186_aOUT, alu1_nx186_aIN, n_4188, n_4189, n_4190,
n_4191, n_4192, n_4193, n_4194, n_4195, I1_dup_664_aOUT, I1_dup_664_aIN,
n_4198, n_4199, n_4200, n_4201, n_4202, outreg_val5_aD, n_4208,
n_4209, n_4210, n_4211, n_4212, n_4213, n_4214, n_4215, n_4216,
outreg_val5_aCLK, progcntr_val6_aD, n_4223, n_4224, n_4225, n_4226,
n_4227, n_4228, progcntr_val6_aCLK, alu1_modgen_34_l1_l0_c_int6_aOUT,
alu1_modgen_34_l1_l0_c_int6_aIN, n_4232, n_4233, n_4234, n_4235,
n_4236, alu1_nx185_aOUT, alu1_nx185_aIN, n_4239, n_4240, n_4241,
n_4242, n_4243, n_4244, n_4245, n_4246, I1_dup_663_aOUT, I1_dup_663_aIN,
n_4249, n_4250, n_4251, n_4252, n_4253, outreg_val6_aD, n_4259,
n_4260, n_4261, n_4262, n_4263, n_4264, n_4265, n_4266, n_4267,
outreg_val6_aCLK, progcntr_val7_aD, n_4274, n_4275, n_4276, n_4277,
n_4278, n_4279, progcntr_val7_aCLK, alu1_modgen_34_l1_l0_c_int7_aOUT,
alu1_modgen_34_l1_l0_c_int7_aIN, n_4283, n_4284, n_4285, n_4286,
n_4287, alu1_nx184_aOUT, alu1_nx184_aIN, n_4290, n_4291, n_4292,
n_4293, n_4294, n_4295, n_4296, n_4297, I1_dup_662_aOUT, I1_dup_662_aIN,
n_4300, n_4301, n_4302, n_4303, n_4304, outreg_val7_aD, n_4310,
n_4311, n_4312, n_4313, n_4314, n_4315, n_4316, n_4317, n_4318,
outreg_val7_aCLK, progcntr_val8_aD, n_4325, n_4326, n_4327, n_4328,
n_4329, n_4330, progcntr_val8_aCLK, alu1_modgen_34_l1_l0_c_int8_aOUT,
alu1_modgen_34_l1_l0_c_int8_aIN, n_4334, n_4335, n_4336, n_4337,
n_4338, alu1_nx183_aOUT, alu1_nx183_aIN, n_4341, n_4342, n_4343,
n_4344, n_4345, n_4346, n_4347, n_4348, I1_dup_661_aOUT, I1_dup_661_aIN,
n_4351, n_4352, n_4353, n_4354, n_4355, outreg_val8_aD, n_4361,
n_4362, n_4363, n_4364, n_4365, n_4366, n_4367, n_4368, n_4369,
outreg_val8_aCLK, progcntr_val9_aD, n_4376, n_4377, n_4378, n_4379,
n_4380, n_4381, progcntr_val9_aCLK, alu1_modgen_34_l1_l0_c_int9_aOUT,
alu1_modgen_34_l1_l0_c_int9_aIN, n_4385, n_4386, n_4387, n_4388,
n_4389, alu1_nx182_aOUT, alu1_nx182_aIN, n_4392, n_4393, n_4394,
n_4395, n_4396, n_4397, n_4398, n_4399, I1_dup_660_aOUT, I1_dup_660_aIN,
n_4402, n_4403, n_4404, n_4405, n_4406, outreg_val9_aD, n_4412,
n_4413, n_4414, n_4415, n_4416, n_4417, n_4418, n_4419, n_4420,
outreg_val9_aCLK, progcntr_val10_aD, n_4427, n_4428, n_4429, n_4430,
n_4431, n_4432, progcntr_val10_aCLK, alu1_modgen_34_l1_l0_c_int10_aOUT,
alu1_modgen_34_l1_l0_c_int10_aIN, n_4436, n_4437, n_4438, n_4439,
n_4440, alu1_nx181_aOUT, alu1_nx181_aIN, n_4443, n_4444, n_4445,
n_4446, n_4447, n_4448, n_4449, n_4450, I1_dup_659_aOUT, I1_dup_659_aIN,
n_4453, n_4454, n_4455, n_4456, n_4457, outreg_val10_aD, n_4463,
n_4464, n_4465, n_4466, n_4467, n_4468, n_4469, n_4470, n_4471,
outreg_val10_aCLK, progcntr_val11_aD, n_4478, n_4479, n_4480, n_4481,
n_4482, n_4483, progcntr_val11_aCLK, alu1_modgen_34_l1_l0_c_int11_aOUT,
alu1_modgen_34_l1_l0_c_int11_aIN, n_4487, n_4488, n_4489, n_4490,
n_4491, alu1_nx180_aOUT, alu1_nx180_aIN, n_4494, n_4495, n_4496,
n_4497, n_4498, n_4499, n_4500, n_4501, I1_dup_658_aOUT, I1_dup_658_aIN,
n_4504, n_4505, n_4506, n_4507, n_4508, outreg_val11_aD, n_4514,
n_4515, n_4516, n_4517, n_4518, n_4519, n_4520, n_4521, n_4522,
outreg_val11_aCLK, progcntr_val12_aD, n_4529, n_4530, n_4531, n_4532,
n_4533, n_4534, progcntr_val12_aCLK, alu1_modgen_34_l1_l0_c_int12_aOUT,
alu1_modgen_34_l1_l0_c_int12_aIN, n_4538, n_4539, n_4540, n_4541,
n_4542, alu1_nx179_aOUT, alu1_nx179_aIN, n_4545, n_4546, n_4547,
n_4548, n_4549, n_4550, n_4551, n_4552, I1_dup_657_aOUT, I1_dup_657_aIN,
n_4555, n_4556, n_4557, n_4558, n_4559, outreg_val12_aD, n_4565,
n_4566, n_4567, n_4568, n_4569, n_4570, n_4571, n_4572, n_4573,
outreg_val12_aCLK, progcntr_val13_aD, n_4580, n_4581, n_4582, n_4583,
n_4584, n_4585, progcntr_val13_aCLK, alu1_modgen_34_l1_l0_c_int13_aOUT,
alu1_modgen_34_l1_l0_c_int13_aIN, n_4589, n_4590, n_4591, n_4592,
n_4593, alu1_nx178_aOUT, alu1_nx178_aIN, n_4596, n_4597, n_4598,
n_4599, n_4600, n_4601, n_4602, n_4603, I1_dup_656_aOUT, I1_dup_656_aIN,
n_4606, n_4607, n_4608, n_4609, n_4610, outreg_val13_aD, n_4616,
n_4617, n_4618, n_4619, n_4620, n_4621, n_4622, n_4623, n_4624,
outreg_val13_aCLK, progcntr_val14_aD, n_4631, n_4632, n_4633, n_4634,
n_4635, n_4636, progcntr_val14_aCLK, alu1_modgen_34_l1_l0_c_int14_aOUT,
alu1_modgen_34_l1_l0_c_int14_aIN, n_4640, n_4641, n_4642, n_4643,
n_4644, alu1_nx177_aOUT, alu1_nx177_aIN, n_4647, n_4648, n_4649,
n_4650, n_4651, n_4652, n_4653, n_4654, I1_dup_655_aOUT, I1_dup_655_aIN,
n_4657, n_4658, n_4659, n_4660, n_4661, outreg_val14_aD, n_4667,
n_4668, n_4669, n_4670, n_4671, n_4672, n_4673, n_4674, n_4675,
outreg_val14_aCLK, con1_current_state50_aCLRN, con1_current_state50_aD,
n_4683, n_4684, n_4685, n_4686, con1_current_state50_aCLK, progcntr_val15_aD,
n_4693, n_4694, n_4695, n_4696, n_4697, n_4698, progcntr_val15_aCLK,
alu1_modgen_34_l1_l0_c_int15_aOUT, alu1_modgen_34_l1_l0_c_int15_aIN,
n_4702, n_4703, n_4704, n_4705, n_4706, alu1_nx176_aOUT, alu1_nx176_aIN,
n_4709, n_4710, n_4711, n_4712, n_4713, n_4714, n_4715, n_4716,
I1_aOUT, I1_aIN, n_4719, n_4720, n_4721, n_4722, n_4723, outreg_val15_aD,
n_4729, n_4730, n_4731, n_4732, n_4733, n_4734, n_4735, n_4736,
n_4737, outreg_val15_aCLK, instrregout15_aD, n_4744, n_4745, n_4746,
n_4747, n_4748, n_4749, instrregout15_aCLK, con1_current_state45_Q,
con1_current_state45_aCLRN, con1_current_state45_aD, n_4758, n_4759,
n_4760, n_4761, con1_current_state45_aCLK, con1_current_state40_Q,
con1_current_state40_aCLRN, con1_current_state40_aD, n_4770, n_4771,
n_4772, n_4773, con1_current_state40_aCLK, con1_current_state35_Q,
con1_current_state35_aCLRN, con1_current_state35_aD, n_4782, n_4783,
n_4784, n_4785, con1_current_state35_aCLK, ix484_a2_dup_652_aD,
n_4793, n_4794, n_4795, n_4796, n_4797, n_4798, ix484_a2_dup_652_aCLK,
ix484_a2_dup_652_aENA, n_4801, ix484_a7_dup_647_aD, n_4808, n_4809,
n_4810, n_4811, n_4812, n_4813, ix484_a7_dup_647_aCLK, ix484_a7_dup_647_aENA,
n_4816, ix484_nx38_aOUT, ix484_a2_dup_644_aD, n_4824, n_4825, n_4826,
n_4827, n_4828, n_4829, ix484_a2_dup_644_aCLK, ix484_a2_dup_644_aENA,
n_4832, ix484_a7_dup_639_aD, n_4839, n_4840, n_4841, n_4842, n_4843,
n_4844, ix484_a7_dup_639_aCLK, ix484_a7_dup_639_aENA, n_4847, ix484_a2_dup_636_aD,
n_4854, n_4855, n_4856, n_4857, n_4858, n_4859, ix484_a2_dup_636_aCLK,
ix484_a2_dup_636_aENA, n_4862, ix484_a7_dup_631_aD, n_4869, n_4870,
n_4871, n_4872, n_4873, n_4874, ix484_a7_dup_631_aCLK, ix484_a7_dup_631_aENA,
n_4877, ix484_a2_dup_628_aD, n_4884, n_4885, n_4886, n_4887, n_4888,
n_4889, ix484_a2_dup_628_aCLK, ix484_a2_dup_628_aENA, n_4892, ix484_a7_dup_623_aD,
n_4899, n_4900, n_4901, n_4902, n_4903, n_4904, ix484_a7_dup_623_aCLK,
ix484_a7_dup_623_aENA, n_4907, ix484_a2_dup_620_aD, n_4914, n_4915,
n_4916, n_4917, n_4918, n_4919, ix484_a2_dup_620_aCLK, ix484_a2_dup_620_aENA,
n_4922, ix484_a7_dup_615_aD, n_4929, n_4930, n_4931, n_4932, n_4933,
n_4934, ix484_a7_dup_615_aCLK, ix484_a7_dup_615_aENA, n_4937, ix484_a2_dup_612_aD,
n_4944, n_4945, n_4946, n_4947, n_4948, n_4949, ix484_a2_dup_612_aCLK,
ix484_a2_dup_612_aENA, n_4952, ix484_a7_dup_607_aD, n_4959, n_4960,
n_4961, n_4962, n_4963, n_4964, ix484_a7_dup_607_aCLK, ix484_a7_dup_607_aENA,
n_4967, ix484_a2_dup_604_aD, n_4974, n_4975, n_4976, n_4977, n_4978,
n_4979, ix484_a2_dup_604_aCLK, ix484_a2_dup_604_aENA, n_4982, ix484_a7_dup_599_aD,
n_4989, n_4990, n_4991, n_4992, n_4993, n_4994, ix484_a7_dup_599_aCLK,
ix484_a7_dup_599_aENA, n_4997, ix484_a2_dup_596_aD, n_5004, n_5005,
n_5006, n_5007, n_5008, n_5009, ix484_a2_dup_596_aCLK, ix484_a2_dup_596_aENA,
n_5012, ix484_a7_dup_591_aD, n_5019, n_5020, n_5021, n_5022, n_5023,
n_5024, ix484_a7_dup_591_aCLK, ix484_a7_dup_591_aENA, n_5027, ix484_a2_dup_588_aD,
n_5034, n_5035, n_5036, n_5037, n_5038, n_5039, ix484_a2_dup_588_aCLK,
ix484_a2_dup_588_aENA, n_5042, ix484_a7_dup_583_aD, n_5049, n_5050,
n_5051, n_5052, n_5053, n_5054, ix484_a7_dup_583_aCLK, ix484_a7_dup_583_aENA,
n_5057, ix484_a2_dup_580_aD, n_5064, n_5065, n_5066, n_5067, n_5068,
n_5069, ix484_a2_dup_580_aCLK, ix484_a2_dup_580_aENA, n_5072, ix484_a7_dup_575_aD,
n_5079, n_5080, n_5081, n_5082, n_5083, n_5084, ix484_a7_dup_575_aCLK,
ix484_a7_dup_575_aENA, n_5087, ix484_a2_dup_572_aD, n_5094, n_5095,
n_5096, n_5097, n_5098, n_5099, ix484_a2_dup_572_aCLK, ix484_a2_dup_572_aENA,
n_5102, ix484_a7_dup_567_aD, n_5109, n_5110, n_5111, n_5112, n_5113,
n_5114, ix484_a7_dup_567_aCLK, ix484_a7_dup_567_aENA, n_5117, ix484_a2_dup_564_aD,
n_5124, n_5125, n_5126, n_5127, n_5128, n_5129, ix484_a2_dup_564_aCLK,
ix484_a2_dup_564_aENA, n_5132, ix484_a7_dup_559_aD, n_5139, n_5140,
n_5141, n_5142, n_5143, n_5144, ix484_a7_dup_559_aCLK, ix484_a7_dup_559_aENA,
n_5147, ix484_a2_dup_556_aD, n_5154, n_5155, n_5156, n_5157, n_5158,
n_5159, ix484_a2_dup_556_aCLK, ix484_a2_dup_556_aENA, n_5162, ix484_a7_dup_551_aD,
n_5169, n_5170, n_5171, n_5172, n_5173, n_5174, ix484_a7_dup_551_aCLK,
ix484_a7_dup_551_aENA, n_5177, ix484_a2_dup_548_aD, n_5184, n_5185,
n_5186, n_5187, n_5188, n_5189, ix484_a2_dup_548_aCLK, ix484_a2_dup_548_aENA,
n_5192, ix484_a7_dup_543_aD, n_5199, n_5200, n_5201, n_5202, n_5203,
n_5204, ix484_a7_dup_543_aCLK, ix484_a7_dup_543_aENA, n_5207, ix484_a2_dup_540_aD,
n_5214, n_5215, n_5216, n_5217, n_5218, n_5219, ix484_a2_dup_540_aCLK,
ix484_a2_dup_540_aENA, n_5222, ix484_a7_dup_535_aD, n_5229, n_5230,
n_5231, n_5232, n_5233, n_5234, ix484_a7_dup_535_aCLK, ix484_a7_dup_535_aENA,
n_5237, instrregout12_aD, n_5243, n_5244, n_5245, n_5246, n_5247,
n_5248, instrregout12_aCLK, ix484_a2_dup_532_aD, n_5256, n_5257,
n_5258, n_5259, n_5260, n_5261, ix484_a2_dup_532_aCLK, ix484_a2_dup_532_aENA,
n_5264, ix484_a7_aD, n_5271, n_5272, n_5273, n_5274, n_5275, n_5276,
ix484_a7_aCLK, ix484_a7_aENA, n_5279, con1_current_state0_Q, con1_current_state0_aPRN,
n_5286, con1_current_state0_aD, n_5288, n_5289, n_5290, con1_current_state0_aCLK,
I1_dup_708_aOUT, I1_dup_708_aIN, n_5294, n_5295, n_5296, n_5297,
n_5298, n_5299, n_5300, n_5301, n_5302, O_dup_926_aOUT, O_dup_926_aIN,
n_5305, n_5306, n_5307, n_5308, n_5309, n_5310, I3_dup_710_aOUT,
I3_dup_710_aIN, n_5313, n_5314, n_5315, I3_dup_900_aOUT, n_5317,
I2_dup_1023_aOUT, n_5319, n_5320, I3_dup_1028_aOUT, I3_dup_1028_aIN,
n_5323, n_5324, n_5325, con1_current_state25_Q, n_5327, n_5328,
n_5329, con1_current_state29_Q, n_5331, alusel3_aOUT, alusel3_aIN,
n_5334, n_5335, n_5336, n_5337, n_5338, n_5339, I3_dup_682_aOUT,
I3_dup_682_aIN, n_5342, n_5343, n_5344, con1_current_state14_Q,
n_5346, n_5347, con1_current_state11_Q, n_5349, a_as_or4_aix1643_a_a34_aOUT_aNOT,
a_as_or4_aix1643_a_a34_aOUT, n_5352, a_as_or4_aix1643_a_a34_aIN1,
n_5354, n_5355, n_5356, n_5357, con1_current_state27_Q, n_5359,
n_5360, n_5361, O_dup_1005_aOUT, O_dup_1005_aIN, n_5364, n_5365,
n_5366, con1_current_state42_Q, n_5368, con1_current_state37_Q,
n_5370, n_5371, n_5372, O_dup_1572_aOUT, O_dup_1572_aIN, n_5375,
n_5376, n_5377, con1_current_state26_Q, n_5379, con1_current_state24_Q,
n_5381, con1_current_state28_Q, n_5383, n_5384, I1_dup_989_aOUT,
I1_dup_989_aIN, n_5387, n_5388, n_5389, n_5390, n_5391, n_5392,
n_5393, O_dup_990_aOUT, O_dup_990_aIN, n_5396, n_5397, n_5398, n_5399,
con1_current_state47_Q, n_5401, n_5402, n_5403, O_dup_1589_aOUT,
O_dup_1589_aIN, n_5406, n_5407, n_5408, con1_current_state15_Q,
n_5410, con1_current_state22_Q, n_5412, n_5413, n_5414, I1_dup_986_aOUT,
I1_dup_986_aIN, n_5417, n_5418, n_5419, con1_current_state4_Q, n_5421,
con1_current_state2_Q, n_5423, con1_current_state5_Q, n_5425, con1_current_state12_Q,
n_5427, I2_dup_709_aOUT, I2_dup_709_aIN1, n_5430, n_5431, n_5432,
n_5433, n_5434, n_5435, n_5436, con1_current_state20_Q, con1_current_state20_aCLRN,
con1_current_state20_aD, n_5444, n_5445, n_5446, n_5447, n_5448,
n_5449, n_5450, n_5451, n_5452, n_5453, con1_current_state20_aCLK,
con1_current_state46_Q, con1_current_state46_aCLRN, con1_current_state46_aD,
n_5462, n_5463, n_5464, n_5465, con1_current_state46_aCLK, con1_current_state41_Q,
con1_current_state41_aCLRN, con1_current_state41_aD, n_5474, n_5475,
n_5476, n_5477, con1_current_state41_aCLK, con1_current_state36_Q,
con1_current_state36_aCLRN, con1_current_state36_aD, n_5486, n_5487,
n_5488, n_5489, con1_current_state36_aCLK, con1_current_state37_aCLRN,
con1_current_state37_aD, n_5497, n_5498, n_5499, n_5500, con1_current_state37_aCLK,
con1_current_state42_aCLRN, con1_current_state42_aD, n_5508, n_5509,
n_5510, n_5511, con1_current_state42_aCLK, con1_current_state28_aCLRN,
con1_current_state28_aD, n_5519, n_5520, n_5521, n_5522, con1_current_state28_aCLK,
con1_modgen_61_nx10_aOUT, con1_modgen_61_nx10_aIN, n_5526, n_5527,
n_5528, n_5529, n_5530, n_5531, con1_current_state11_aCLRN, con1_current_state11_aD,
n_5538, n_5539, n_5540, n_5541, n_5542, n_5543, n_5544, con1_current_state11_aCLK,
con1_current_state47_aCLRN, con1_current_state47_aD, n_5552, n_5553,
n_5554, n_5555, con1_current_state47_aCLK, con1_current_state1_aCLRN,
con1_current_state1_aD, n_5563, n_5564, n_5565, n_5566, con1_current_state1_aCLK,
con1_current_state6_aCLRN, con1_current_state6_aD, n_5574, n_5575,
n_5576, n_5577, n_5578, n_5579, n_5580, n_5581, n_5582, n_5583,
n_5584, con1_current_state6_aCLK, con1_current_state21_aCLRN, con1_current_state21_aD,
n_5592, n_5593, n_5594, n_5595, con1_current_state21_aCLK, ix484_a4_dup_650_aD,
n_5603, n_5604, n_5605, n_5606, n_5607, n_5608, ix484_a4_dup_650_aCLK,
ix484_a4_dup_650_aENA, n_5611, ix484_nx41_aOUT, ix484_a0_dup_654_aD,
n_5619, n_5620, n_5621, n_5622, n_5623, n_5624, ix484_a0_dup_654_aCLK,
ix484_a0_dup_654_aENA, n_5627, ix484_nx45_aOUT, ix484_a4_dup_642_aD,
n_5635, n_5636, n_5637, n_5638, n_5639, n_5640, ix484_a4_dup_642_aCLK,
ix484_a4_dup_642_aENA, n_5643, ix484_a0_dup_646_aD, n_5650, n_5651,
n_5652, n_5653, n_5654, n_5655, ix484_a0_dup_646_aCLK, ix484_a0_dup_646_aENA,
n_5658, ix484_a4_dup_634_aD, n_5665, n_5666, n_5667, n_5668, n_5669,
n_5670, ix484_a4_dup_634_aCLK, ix484_a4_dup_634_aENA, n_5673, ix484_a0_dup_638_aD,
n_5680, n_5681, n_5682, n_5683, n_5684, n_5685, ix484_a0_dup_638_aCLK,
ix484_a0_dup_638_aENA, n_5688, ix484_a4_dup_626_aD, n_5695, n_5696,
n_5697, n_5698, n_5699, n_5700, ix484_a4_dup_626_aCLK, ix484_a4_dup_626_aENA,
n_5703, ix484_a0_dup_630_aD, n_5710, n_5711, n_5712, n_5713, n_5714,
n_5715, ix484_a0_dup_630_aCLK, ix484_a0_dup_630_aENA, n_5718, ix484_a4_dup_618_aD,
n_5725, n_5726, n_5727, n_5728, n_5729, n_5730, ix484_a4_dup_618_aCLK,
ix484_a4_dup_618_aENA, n_5733, ix484_a0_dup_622_aD, n_5740, n_5741,
n_5742, n_5743, n_5744, n_5745, ix484_a0_dup_622_aCLK, ix484_a0_dup_622_aENA,
n_5748, ix484_a4_dup_610_aD, n_5755, n_5756, n_5757, n_5758, n_5759,
n_5760, ix484_a4_dup_610_aCLK, ix484_a4_dup_610_aENA, n_5763, ix484_a0_dup_614_aD,
n_5770, n_5771, n_5772, n_5773, n_5774, n_5775, ix484_a0_dup_614_aCLK,
ix484_a0_dup_614_aENA, n_5778, ix484_a4_dup_602_aD, n_5785, n_5786,
n_5787, n_5788, n_5789, n_5790, ix484_a4_dup_602_aCLK, ix484_a4_dup_602_aENA,
n_5793, ix484_a0_dup_606_aD, n_5800, n_5801, n_5802, n_5803, n_5804,
n_5805, ix484_a0_dup_606_aCLK, ix484_a0_dup_606_aENA, n_5808, ix484_a4_dup_594_aD,
n_5815, n_5816, n_5817, n_5818, n_5819, n_5820, ix484_a4_dup_594_aCLK,
ix484_a4_dup_594_aENA, n_5823, ix484_a0_dup_598_aD, n_5830, n_5831,
n_5832, n_5833, n_5834, n_5835, ix484_a0_dup_598_aCLK, ix484_a0_dup_598_aENA,
n_5838, ix484_a4_dup_586_aD, n_5845, n_5846, n_5847, n_5848, n_5849,
n_5850, ix484_a4_dup_586_aCLK, ix484_a4_dup_586_aENA, n_5853, ix484_a0_dup_590_aD,
n_5860, n_5861, n_5862, n_5863, n_5864, n_5865, ix484_a0_dup_590_aCLK,
ix484_a0_dup_590_aENA, n_5868, ix484_a4_dup_578_aD, n_5875, n_5876,
n_5877, n_5878, n_5879, n_5880, ix484_a4_dup_578_aCLK, ix484_a4_dup_578_aENA,
n_5883, ix484_a0_dup_582_aD, n_5890, n_5891, n_5892, n_5893, n_5894,
n_5895, ix484_a0_dup_582_aCLK, ix484_a0_dup_582_aENA, n_5898, ix484_a4_dup_570_aD,
n_5905, n_5906, n_5907, n_5908, n_5909, n_5910, ix484_a4_dup_570_aCLK,
ix484_a4_dup_570_aENA, n_5913, ix484_a0_dup_574_aD, n_5920, n_5921,
n_5922, n_5923, n_5924, n_5925, ix484_a0_dup_574_aCLK, ix484_a0_dup_574_aENA,
n_5928, ix484_a4_dup_562_aD, n_5935, n_5936, n_5937, n_5938, n_5939,
n_5940, ix484_a4_dup_562_aCLK, ix484_a4_dup_562_aENA, n_5943, ix484_a0_dup_566_aD,
n_5950, n_5951, n_5952, n_5953, n_5954, n_5955, ix484_a0_dup_566_aCLK,
ix484_a0_dup_566_aENA, n_5958, ix484_a4_dup_554_aD, n_5965, n_5966,
n_5967, n_5968, n_5969, n_5970, ix484_a4_dup_554_aCLK, ix484_a4_dup_554_aENA,
n_5973, ix484_a0_dup_558_aD, n_5980, n_5981, n_5982, n_5983, n_5984,
n_5985, ix484_a0_dup_558_aCLK, ix484_a0_dup_558_aENA, n_5988, ix484_a4_dup_546_aD,
n_5995, n_5996, n_5997, n_5998, n_5999, n_6000, ix484_a4_dup_546_aCLK,
ix484_a4_dup_546_aENA, n_6003, ix484_a0_dup_550_aD, n_6010, n_6011,
n_6012, n_6013, n_6014, n_6015, ix484_a0_dup_550_aCLK, ix484_a0_dup_550_aENA,
n_6018, ix484_a4_dup_538_aD, n_6025, n_6026, n_6027, n_6028, n_6029,
n_6030, ix484_a4_dup_538_aCLK, ix484_a4_dup_538_aENA, n_6033, ix484_a0_dup_542_aD,
n_6040, n_6041, n_6042, n_6043, n_6044, n_6045, ix484_a0_dup_542_aCLK,
ix484_a0_dup_542_aENA, n_6048, ix484_a4_aD, n_6055, n_6056, n_6057,
n_6058, n_6059, n_6060, ix484_a4_aCLK, ix484_a4_aENA, n_6063, ix484_a0_dup_534_aD,
n_6070, n_6071, n_6072, n_6073, n_6074, n_6075, ix484_a0_dup_534_aCLK,
ix484_a0_dup_534_aENA, n_6078, con1_current_state13_aCLRN, con1_current_state13_aD,
n_6085, n_6086, n_6087, n_6088, con1_current_state13_aCLK, con1_current_state24_aCLRN,
con1_current_state24_aD, n_6096, n_6097, n_6098, n_6099, con1_current_state24_aCLK,
con1_current_state12_aCLRN, con1_current_state12_aD, n_6107, n_6108,
n_6109, n_6110, con1_current_state12_aCLK, con1_current_state5_aCLRN,
con1_current_state5_aD, n_6118, n_6119, n_6120, n_6121, n_6122,
n_6123, n_6124, con1_current_state5_aCLK, con1_current_state2_aCLRN,
con1_current_state2_aD, n_6132, n_6133, n_6134, n_6135, con1_current_state2_aCLK,
con1_current_state29_aCLRN, con1_current_state29_aD, n_6143, n_6144,
n_6145, n_6146, n_6147, n_6148, n_6149, con1_current_state29_aCLK,
con1_current_state43_aCLRN, con1_current_state43_aD, n_6157, n_6158,
n_6159, n_6160, n_6161, n_6162, n_6163, con1_current_state43_aCLK,
con1_current_state38_aCLRN, con1_current_state38_aD, n_6171, n_6172,
n_6173, n_6174, n_6175, n_6176, n_6177, con1_current_state38_aCLK,
con1_current_state25_aCLRN, con1_current_state25_aD, n_6185, n_6186,
n_6187, n_6188, n_6189, n_6190, n_6191, con1_current_state25_aCLK,
con1_current_state26_aCLRN, con1_current_state26_aD, n_6199, n_6200,
n_6201, n_6202, n_6203, n_6204, n_6205, n_6206, con1_current_state26_aCLK,
con1_current_state22_aCLRN, con1_current_state22_aD, n_6214, n_6215,
n_6216, n_6217, con1_current_state22_aCLK, con1_current_state3_Q,
con1_current_state3_aCLRN, con1_current_state3_aD, n_6226, n_6227,
n_6228, n_6229, con1_current_state3_aCLK, con1_current_state14_aCLRN,
con1_current_state14_aD, n_6237, n_6238, n_6239, con1_modgen_62_nx16_aOUT,
n_6241, n_6242, con1_current_state14_aCLK, con1_current_state27_aCLRN,
con1_current_state27_aD, n_6250, n_6251, n_6252, n_6253, con1_current_state27_aCLK,
con1_current_state23_aCLRN, con1_current_state23_aD, n_6261, n_6262,
n_6263, n_6264, con1_current_state23_aCLK, con1_current_state48_aCLRN,
con1_current_state48_aD, n_6272, n_6273, n_6274, n_6275, n_6276,
n_6277, n_6278, con1_current_state48_aCLK, con1_current_state4_aCLRN,
con1_current_state4_aD, n_6286, n_6287, n_6288, n_6289, con1_current_state4_aCLK,
con1_current_state15_aCLRN, con1_current_state15_aD, n_6297, n_6298,
n_6299, n_6300, con1_current_state15_aCLK, rw_dup0_aCLRN, rw_dup0_aD,
n_6308, n_6309, n_6310, n_6311, rw_dup0_aCLK, O_dup_1039_aOUT, O_dup_1039_aIN,
n_6315, n_6316, n_6317, n_6318, n_6319, n_6320, n_6321, I0_dup_774_aOUT,
I0_dup_774_aIN, n_6324, n_6325, n_6326, n_6327, n_6328, n_6329,
n_6330, O_aIN1, n_6332, n_6333, n_6334, n_6335, n_6336, n_6337,
n_6338, addr_dup00_aD, n_6344, n_6345, n_6346, n_6347, n_6348, n_6349,
addr_dup00_aCLK, addr_dup01_aD, n_6356, n_6357, n_6358, n_6359,
n_6360, n_6361, addr_dup01_aCLK, addr_dup02_aD, n_6368, n_6369,
n_6370, n_6371, n_6372, n_6373, addr_dup02_aCLK, addr_dup03_aD,
n_6380, n_6381, n_6382, n_6383, n_6384, n_6385, addr_dup03_aCLK,
addr_dup04_aD, n_6392, n_6393, n_6394, n_6395, n_6396, n_6397, addr_dup04_aCLK,
addr_dup05_aD, n_6404, n_6405, n_6406, n_6407, n_6408, n_6409, addr_dup05_aCLK,
addr_dup06_aD, n_6416, n_6417, n_6418, n_6419, n_6420, n_6421, addr_dup06_aCLK,
addr_dup07_aD, n_6428, n_6429, n_6430, n_6431, n_6432, n_6433, addr_dup07_aCLK,
addr_dup08_aD, n_6440, n_6441, n_6442, n_6443, n_6444, n_6445, addr_dup08_aCLK,
addr_dup09_aD, n_6452, n_6453, n_6454, n_6455, n_6456, n_6457, addr_dup09_aCLK,
addr_dup010_aD, n_6464, n_6465, n_6466, n_6467, n_6468, n_6469,
addr_dup010_aCLK, addr_dup011_aD, n_6476, n_6477, n_6478, n_6479,
n_6480, n_6481, addr_dup011_aCLK, addr_dup012_aD, n_6488, n_6489,
n_6490, n_6491, n_6492, n_6493, addr_dup012_aCLK, addr_dup013_aD,
n_6500, n_6501, n_6502, n_6503, n_6504, n_6505, addr_dup013_aCLK,
addr_dup014_aD, n_6512, n_6513, n_6514, n_6515, n_6516, n_6517,
addr_dup014_aCLK, addr_dup015_aD, n_6524, n_6525, n_6526, n_6527,
n_6528, n_6529, addr_dup015_aCLK, a_as_or3_aix1644_a_a32_aIN1, n_6532,
n_6533, n_6534, n_6535, n_6536, n_6537, n_6538, n_6539, n_6540,
n_6541, n_6542, I3_dup_732_aIN, n_6544, n_6545, n_6546, n_6547,
n_6548, n_6549, n_6550, n_6551, I3_dup_918_aOUT, I3_dup_918_aIN,
n_6554, n_6555, n_6556, n_6557, n_6558, n_6559, I3_dup_696_aIN,
n_6561, n_6562, n_6563, n_6564, n_6565, n_6566, n_6567, n_6568,
n_6569, n_6570, I1_dup_686_aOUT, I1_dup_686_aIN, n_6573, n_6574,
n_6575, n_6576, n_6577, n_6578, n_6579, n3_aIN1, n_6581, n_6582,
n_6583, n_6584, n_6585, n_6586, n_6587, n_6588, con1_modgen_61_nx12_aIN,
n_6590, n_6591, n_6592, n_6593, n_6594, n_6595, con1_modgen_62_nx16_aIN,
n_6597, n_6598, n_6599, n_6600, n_6601, n_6602, n_6603, n_6604,
n_6605, n_6606, I2_dup_1023_aIN, n_6608, n_6609, n_6610, n_6611,
n_6612, n_6613, n_6614, n_6615, I3_dup_900_aIN, n_6617, n_6618,
n_6619, n_6620, n_6621, n_6622, opregwr_aCLRN, opregwr_aD, n_6629,
n_6630, n_6631, n_6632, n_6633, n_6634, n_6635, opregwr_aCLK, I3_dup_736_aOUT,
I3_dup_736_aIN, n_6639, n_6640, n_6641, n_6642, n_6643, con1_nx3498_aOUT,
con1_nx3498_aIN, n_6646, n_6647, n_6648, n_6649, n_6650, n_6651,
n_6652, n_6653, n_6654, n_6655, opregrd_aIN, n_6657, n_6658, n_6659,
n_6660, n_6661, n_6662, con1_nx3626_aOUT, con1_nx3626_aIN, n_6665,
n_6666, n_6667, n_6668, n_6669, n_6670, n_6671, n_6672, n_6673,
n_6674, I2_dup_823_aIN, n_6676, n_6677, n_6678, n_6679, n_6680,
n_6681, n_6682, n_6683, n_6684, n_6685, I2_dup_681_aIN, n_6687,
n_6688, n_6689, n_6690, n_6691, n_6692, n_6693, n_6694, n_6695,
n_6696, O_dup_1049_aOUT, O_dup_1049_aIN, n_6699, n_6700, n_6701,
n_6702, n_6703, n_6704, n_6705, I3_dup_677_aOUT, I3_dup_677_aIN1,
n_6708, n_6709, n_6710, n_6711, n_6712, n_6713, n_6714, outregrd_aIN,
n_6716, n_6717, n_6718, n_6719, n_6720, n_6721, n_6722, n_6723,
n_6724, n_6725, a_as_or3_aix1786_a_a32_aIN1, n_6727, n_6728, n_6729,
n_6730, n_6731, n_6732, n_6733, n_6734, con1_modgen_66_nx16_aOUT,
con1_modgen_66_nx16_aIN, n_6737, n_6738, n_6739, n_6740, n_6741,
n_6742, n_6743, n_6744, O_dup_901_aOUT, O_dup_901_aIN, n_6747, n_6748,
n_6749, n_6750, n_6751, n_6752, n_6753, n_6754, n_6755, n_6756,
I3_dup_1509_aOUT, I3_dup_1509_aIN, n_6759, n_6760, n_6761, n_6762,
n_6763, con1_next_state14_aOUT, con1_next_state14_aIN1, n_6766,
n_6767, n_6768, n_6769, n_6770, con1_next_state49_aOUT, con1_next_state49_aIN1,
n_6773, n_6774, n_6775, n_6776, n_6777, n_6778, n_6779, I1_dup_670_aOUT,
I1_dup_670_aIN, n_6782, n_6783, n_6784, n_6785, n_6786, n_6787,
n_6788, n_6789, n_6790, I3_dup_1546_aOUT, I3_dup_1546_aIN, n_6793,
n_6794, n_6795, n_6796, n_6797, n_6798, n_6799, n_6800, I2_aOUT,
I2_aIN, n_6803, n_6804, n_6805, n_6806, n_6807, n_6808, n_6809,
I1_dup_755_aIN, n_6811, n_6812, n_6813, n_6814, n_6815, n_6816,
n_6817, n_6818, n_6819, n_6820, O_dup_1505_aOUT, O_dup_1505_aIN,
n_6823, n_6824, n_6825, n_6826, n_6827, n_6828, I0_dup_770_aIN,
n_6830, n_6831, n_6832, n_6833, n_6834, I3_aOUT, I3_aIN, n_6837,
n_6838, n_6839, n_6840, n_6841, regsel0_aIN, n_6843, n_6844, n_6845,
n_6846, n_6847, n_6848, n_6849, n_6850, n_6851, n_6852, O_dup_1034_aIN,
n_6854, n_6855, n_6856, n_6857, n_6858, n_6859, n_6860, n_6861,
I0_dup_768_aOUT, I0_dup_768_aIN, n_6864, n_6865, n_6866, n_6867,
n_6868, ix484_nx45_aIN, n_6870, n_6871, n_6872, n_6873, n_6874,
O_dup_873_aIN, n_6876, n_6877, n_6878, n_6879, n_6880, I2_dup_756_aIN,
n_6882, n_6883, n_6884, n_6885, n_6886, n_6887, ix484_nx41_aIN,
n_6889, n_6890, n_6891, n_6892, n_6893, n_6894, O_dup_870_aIN, n_6896,
n_6897, n_6898, n_6899, n_6900, ix484_nx38_aIN, n_6902, n_6903,
n_6904, n_6905, n_6906, n_6907, O_dup_879_aIN, n_6909, n_6910, n_6911,
n_6912, n_6913, I0_dup_766_aIN, n_6915, n_6916, n_6917, n_6918,
n_6919, ix484_nx43_aIN, n_6921, n_6922, n_6923, n_6924, n_6925 : std_logic;
BEGIN
tribuf_2: TRIBUF
PORT MAP (IN1 => n_176, OE => ix1553_aOE, Y => data(0));
tribuf_4: TRIBUF
PORT MAP (IN1 => n_185, OE => ix1551_aOE, Y => data(1));
tribuf_6: TRIBUF
PORT MAP (IN1 => n_194, OE => ix1549_aOE, Y => data(2));
tribuf_8: TRIBUF
PORT MAP (IN1 => n_203, OE => ix1547_aOE, Y => data(3));
tribuf_10: TRIBUF
PORT MAP (IN1 => n_212, OE => ix1545_aOE, Y => data(4));
tribuf_12: TRIBUF
PORT MAP (IN1 => n_221, OE => ix1543_aOE, Y => data(5));
tribuf_14: TRIBUF
PORT MAP (IN1 => n_230, OE => ix1541_aOE, Y => data(6));
tribuf_16: TRIBUF
PORT MAP (IN1 => n_239, OE => ix1539_aOE, Y => data(7));
tribuf_18: TRIBUF
PORT MAP (IN1 => n_248, OE => ix1537_aOE, Y => data(8));
tribuf_20: TRIBUF
PORT MAP (IN1 => n_257, OE => ix1535_aOE, Y => data(9));
tribuf_22: TRIBUF
PORT MAP (IN1 => n_266, OE => ix1533_aOE, Y => data(10));
tribuf_24: TRIBUF
PORT MAP (IN1 => n_275, OE => ix1531_aOE, Y => data(11));
tribuf_26: TRIBUF
PORT MAP (IN1 => n_284, OE => ix1529_aOE, Y => data(12));
tribuf_28: TRIBUF
PORT MAP (IN1 => n_293, OE => ix1527_aOE, Y => data(13));
tribuf_30: TRIBUF
PORT MAP (IN1 => n_302, OE => ix1525_aOE, Y => data(14));
tribuf_32: TRIBUF
PORT MAP (IN1 => n_311, OE => ix1523_aOE, Y => data(15));
tribuf_34: TRIBUF
PORT MAP (IN1 => n_318, OE => vcc, Y => vma);
tribuf_36: TRIBUF
PORT MAP (IN1 => n_325, OE => vcc, Y => rw);
tribuf_38: TRIBUF
PORT MAP (IN1 => n_332, OE => vcc, Y => addr(0));
tribuf_40: TRIBUF
PORT MAP (IN1 => n_339, OE => vcc, Y => addr(1));
tribuf_42: TRIBUF
PORT MAP (IN1 => n_346, OE => vcc, Y => addr(2));
tribuf_44: TRIBUF
PORT MAP (IN1 => n_353, OE => vcc, Y => addr(3));
tribuf_46: TRIBUF
PORT MAP (IN1 => n_360, OE => vcc, Y => addr(4));
tribuf_48: TRIBUF
PORT MAP (IN1 => n_367, OE => vcc, Y => addr(5));
tribuf_50: TRIBUF
PORT MAP (IN1 => n_374, OE => vcc, Y => addr(6));
tribuf_52: TRIBUF
PORT MAP (IN1 => n_381, OE => vcc, Y => addr(7));
tribuf_54: TRIBUF
PORT MAP (IN1 => n_388, OE => vcc, Y => addr(8));
tribuf_56: TRIBUF
PORT MAP (IN1 => n_395, OE => vcc, Y => addr(9));
tribuf_58: TRIBUF
PORT MAP (IN1 => n_402, OE => vcc, Y => addr(10));
tribuf_60: TRIBUF
PORT MAP (IN1 => n_409, OE => vcc, Y => addr(11));
tribuf_62: TRIBUF
PORT MAP (IN1 => n_416, OE => vcc, Y => addr(12));
tribuf_64: TRIBUF
PORT MAP (IN1 => n_423, OE => vcc, Y => addr(13));
tribuf_66: TRIBUF
PORT MAP (IN1 => n_430, OE => vcc, Y => addr(14));
tribuf_68: TRIBUF
PORT MAP (IN1 => n_437, OE => vcc, Y => addr(15));
and1_69: AND1
PORT MAP ( Y => ix1553_aOE, IN1 => n_174);
delay_70: DELAY
PORT MAP ( Y => n_174, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_71: DELAY
PORT MAP ( Y => n_176, IN1 => n_177);
xor2_72: XOR2
PORT MAP ( Y => n_177, IN1 => n_178, IN2 => n_182);
or1_73: OR1
PORT MAP ( Y => n_178, IN1 => n_179);
and1_74: AND1
PORT MAP ( Y => n_179, IN1 => n_180);
inv_75: INV
PORT MAP ( Y => n_180, IN1 => O_dup_827_aOUT);
and1_76: AND1
PORT MAP ( Y => n_182, IN1 => gnd);
and1_77: AND1
PORT MAP ( Y => ix1551_aOE, IN1 => n_184);
delay_78: DELAY
PORT MAP ( Y => n_184, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_79: DELAY
PORT MAP ( Y => n_185, IN1 => n_186);
xor2_80: XOR2
PORT MAP ( Y => n_186, IN1 => n_187, IN2 => n_191);
or1_81: OR1
PORT MAP ( Y => n_187, IN1 => n_188);
and1_82: AND1
PORT MAP ( Y => n_188, IN1 => n_189);
inv_83: INV
PORT MAP ( Y => n_189, IN1 => O_dup_820_aOUT);
and1_84: AND1
PORT MAP ( Y => n_191, IN1 => gnd);
and1_85: AND1
PORT MAP ( Y => ix1549_aOE, IN1 => n_193);
delay_86: DELAY
PORT MAP ( Y => n_193, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_87: DELAY
PORT MAP ( Y => n_194, IN1 => n_195);
xor2_88: XOR2
PORT MAP ( Y => n_195, IN1 => n_196, IN2 => n_200);
or1_89: OR1
PORT MAP ( Y => n_196, IN1 => n_197);
and1_90: AND1
PORT MAP ( Y => n_197, IN1 => n_198);
inv_91: INV
PORT MAP ( Y => n_198, IN1 => O_dup_817_aOUT);
and1_92: AND1
PORT MAP ( Y => n_200, IN1 => gnd);
and1_93: AND1
PORT MAP ( Y => ix1547_aOE, IN1 => n_202);
delay_94: DELAY
PORT MAP ( Y => n_202, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_95: DELAY
PORT MAP ( Y => n_203, IN1 => n_204);
xor2_96: XOR2
PORT MAP ( Y => n_204, IN1 => n_205, IN2 => n_209);
or1_97: OR1
PORT MAP ( Y => n_205, IN1 => n_206);
and1_98: AND1
PORT MAP ( Y => n_206, IN1 => n_207);
inv_99: INV
PORT MAP ( Y => n_207, IN1 => O_dup_814_aOUT);
and1_100: AND1
PORT MAP ( Y => n_209, IN1 => gnd);
and1_101: AND1
PORT MAP ( Y => ix1545_aOE, IN1 => n_211);
delay_102: DELAY
PORT MAP ( Y => n_211, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_103: DELAY
PORT MAP ( Y => n_212, IN1 => n_213);
xor2_104: XOR2
PORT MAP ( Y => n_213, IN1 => n_214, IN2 => n_218);
or1_105: OR1
PORT MAP ( Y => n_214, IN1 => n_215);
and1_106: AND1
PORT MAP ( Y => n_215, IN1 => n_216);
inv_107: INV
PORT MAP ( Y => n_216, IN1 => O_dup_811_aOUT);
and1_108: AND1
PORT MAP ( Y => n_218, IN1 => gnd);
and1_109: AND1
PORT MAP ( Y => ix1543_aOE, IN1 => n_220);
delay_110: DELAY
PORT MAP ( Y => n_220, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_111: DELAY
PORT MAP ( Y => n_221, IN1 => n_222);
xor2_112: XOR2
PORT MAP ( Y => n_222, IN1 => n_223, IN2 => n_227);
or1_113: OR1
PORT MAP ( Y => n_223, IN1 => n_224);
and1_114: AND1
PORT MAP ( Y => n_224, IN1 => n_225);
inv_115: INV
PORT MAP ( Y => n_225, IN1 => O_dup_808_aOUT);
and1_116: AND1
PORT MAP ( Y => n_227, IN1 => gnd);
and1_117: AND1
PORT MAP ( Y => ix1541_aOE, IN1 => n_229);
delay_118: DELAY
PORT MAP ( Y => n_229, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_119: DELAY
PORT MAP ( Y => n_230, IN1 => n_231);
xor2_120: XOR2
PORT MAP ( Y => n_231, IN1 => n_232, IN2 => n_236);
or1_121: OR1
PORT MAP ( Y => n_232, IN1 => n_233);
and1_122: AND1
PORT MAP ( Y => n_233, IN1 => n_234);
inv_123: INV
PORT MAP ( Y => n_234, IN1 => O_dup_805_aOUT);
and1_124: AND1
PORT MAP ( Y => n_236, IN1 => gnd);
and1_125: AND1
PORT MAP ( Y => ix1539_aOE, IN1 => n_238);
delay_126: DELAY
PORT MAP ( Y => n_238, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_127: DELAY
PORT MAP ( Y => n_239, IN1 => n_240);
xor2_128: XOR2
PORT MAP ( Y => n_240, IN1 => n_241, IN2 => n_245);
or1_129: OR1
PORT MAP ( Y => n_241, IN1 => n_242);
and1_130: AND1
PORT MAP ( Y => n_242, IN1 => n_243);
inv_131: INV
PORT MAP ( Y => n_243, IN1 => O_dup_802_aOUT);
and1_132: AND1
PORT MAP ( Y => n_245, IN1 => gnd);
and1_133: AND1
PORT MAP ( Y => ix1537_aOE, IN1 => n_247);
delay_134: DELAY
PORT MAP ( Y => n_247, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_135: DELAY
PORT MAP ( Y => n_248, IN1 => n_249);
xor2_136: XOR2
PORT MAP ( Y => n_249, IN1 => n_250, IN2 => n_254);
or1_137: OR1
PORT MAP ( Y => n_250, IN1 => n_251);
and1_138: AND1
PORT MAP ( Y => n_251, IN1 => n_252);
inv_139: INV
PORT MAP ( Y => n_252, IN1 => O_dup_799_aOUT);
and1_140: AND1
PORT MAP ( Y => n_254, IN1 => gnd);
and1_141: AND1
PORT MAP ( Y => ix1535_aOE, IN1 => n_256);
delay_142: DELAY
PORT MAP ( Y => n_256, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_143: DELAY
PORT MAP ( Y => n_257, IN1 => n_258);
xor2_144: XOR2
PORT MAP ( Y => n_258, IN1 => n_259, IN2 => n_263);
or1_145: OR1
PORT MAP ( Y => n_259, IN1 => n_260);
and1_146: AND1
PORT MAP ( Y => n_260, IN1 => n_261);
inv_147: INV
PORT MAP ( Y => n_261, IN1 => O_dup_796_aOUT);
and1_148: AND1
PORT MAP ( Y => n_263, IN1 => gnd);
and1_149: AND1
PORT MAP ( Y => ix1533_aOE, IN1 => n_265);
delay_150: DELAY
PORT MAP ( Y => n_265, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_151: DELAY
PORT MAP ( Y => n_266, IN1 => n_267);
xor2_152: XOR2
PORT MAP ( Y => n_267, IN1 => n_268, IN2 => n_272);
or1_153: OR1
PORT MAP ( Y => n_268, IN1 => n_269);
and1_154: AND1
PORT MAP ( Y => n_269, IN1 => n_270);
inv_155: INV
PORT MAP ( Y => n_270, IN1 => O_dup_793_aOUT);
and1_156: AND1
PORT MAP ( Y => n_272, IN1 => gnd);
and1_157: AND1
PORT MAP ( Y => ix1531_aOE, IN1 => n_274);
delay_158: DELAY
PORT MAP ( Y => n_274, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_159: DELAY
PORT MAP ( Y => n_275, IN1 => n_276);
xor2_160: XOR2
PORT MAP ( Y => n_276, IN1 => n_277, IN2 => n_281);
or1_161: OR1
PORT MAP ( Y => n_277, IN1 => n_278);
and1_162: AND1
PORT MAP ( Y => n_278, IN1 => n_279);
inv_163: INV
PORT MAP ( Y => n_279, IN1 => O_dup_790_aOUT);
and1_164: AND1
PORT MAP ( Y => n_281, IN1 => gnd);
and1_165: AND1
PORT MAP ( Y => ix1529_aOE, IN1 => n_283);
delay_166: DELAY
PORT MAP ( Y => n_283, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_167: DELAY
PORT MAP ( Y => n_284, IN1 => n_285);
xor2_168: XOR2
PORT MAP ( Y => n_285, IN1 => n_286, IN2 => n_290);
or1_169: OR1
PORT MAP ( Y => n_286, IN1 => n_287);
and1_170: AND1
PORT MAP ( Y => n_287, IN1 => n_288);
inv_171: INV
PORT MAP ( Y => n_288, IN1 => O_dup_787_aOUT);
and1_172: AND1
PORT MAP ( Y => n_290, IN1 => gnd);
and1_173: AND1
PORT MAP ( Y => ix1527_aOE, IN1 => n_292);
delay_174: DELAY
PORT MAP ( Y => n_292, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_175: DELAY
PORT MAP ( Y => n_293, IN1 => n_294);
xor2_176: XOR2
PORT MAP ( Y => n_294, IN1 => n_295, IN2 => n_299);
or1_177: OR1
PORT MAP ( Y => n_295, IN1 => n_296);
and1_178: AND1
PORT MAP ( Y => n_296, IN1 => n_297);
inv_179: INV
PORT MAP ( Y => n_297, IN1 => O_dup_784_aOUT);
and1_180: AND1
PORT MAP ( Y => n_299, IN1 => gnd);
and1_181: AND1
PORT MAP ( Y => ix1525_aOE, IN1 => n_301);
delay_182: DELAY
PORT MAP ( Y => n_301, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_183: DELAY
PORT MAP ( Y => n_302, IN1 => n_303);
xor2_184: XOR2
PORT MAP ( Y => n_303, IN1 => n_304, IN2 => n_308);
or1_185: OR1
PORT MAP ( Y => n_304, IN1 => n_305);
and1_186: AND1
PORT MAP ( Y => n_305, IN1 => n_306);
inv_187: INV
PORT MAP ( Y => n_306, IN1 => O_dup_781_aOUT);
and1_188: AND1
PORT MAP ( Y => n_308, IN1 => gnd);
and1_189: AND1
PORT MAP ( Y => ix1523_aOE, IN1 => n_310);
delay_190: DELAY
PORT MAP ( Y => n_310, IN1 => a_as_or3_aix1786_a_a32_aOUT);
delay_191: DELAY
PORT MAP ( Y => n_311, IN1 => n_312);
xor2_192: XOR2
PORT MAP ( Y => n_312, IN1 => n_313, IN2 => n_317);
or1_193: OR1
PORT MAP ( Y => n_313, IN1 => n_314);
and1_194: AND1
PORT MAP ( Y => n_314, IN1 => n_315);
inv_195: INV
PORT MAP ( Y => n_315, IN1 => O_dup_778_aOUT);
and1_196: AND1
PORT MAP ( Y => n_317, IN1 => gnd);
delay_197: DELAY
PORT MAP ( Y => n_318, IN1 => n_319);
xor2_198: XOR2
PORT MAP ( Y => n_319, IN1 => n_320, IN2 => n_324);
or1_199: OR1
PORT MAP ( Y => n_320, IN1 => n_321);
and1_200: AND1
PORT MAP ( Y => n_321, IN1 => n_322);
inv_201: INV
PORT MAP ( Y => n_322, IN1 => O_aOUT);
and1_202: AND1
PORT MAP ( Y => n_324, IN1 => gnd);
delay_203: DELAY
PORT MAP ( Y => n_325, IN1 => n_326);
xor2_204: XOR2
PORT MAP ( Y => n_326, IN1 => n_327, IN2 => n_331);
or1_205: OR1
PORT MAP ( Y => n_327, IN1 => n_328);
and1_206: AND1
PORT MAP ( Y => n_328, IN1 => n_329);
delay_207: DELAY
PORT MAP ( Y => n_329, IN1 => rw_dup0_Q);
and1_208: AND1
PORT MAP ( Y => n_331, IN1 => gnd);
delay_209: DELAY
PORT MAP ( Y => n_332, IN1 => n_333);
xor2_210: XOR2
PORT MAP ( Y => n_333, IN1 => n_334, IN2 => n_338);
or1_211: OR1
PORT MAP ( Y => n_334, IN1 => n_335);
and1_212: AND1
PORT MAP ( Y => n_335, IN1 => n_336);
delay_213: DELAY
PORT MAP ( Y => n_336, IN1 => addr_dup00_Q);
and1_214: AND1
PORT MAP ( Y => n_338, IN1 => gnd);
delay_215: DELAY
PORT MAP ( Y => n_339, IN1 => n_340);
xor2_216: XOR2
PORT MAP ( Y => n_340, IN1 => n_341, IN2 => n_345);
or1_217: OR1
PORT MAP ( Y => n_341, IN1 => n_342);
and1_218: AND1
PORT MAP ( Y => n_342, IN1 => n_343);
delay_219: DELAY
PORT MAP ( Y => n_343, IN1 => addr_dup01_Q);
and1_220: AND1
PORT MAP ( Y => n_345, IN1 => gnd);
delay_221: DELAY
PORT MAP ( Y => n_346, IN1 => n_347);
xor2_222: XOR2
PORT MAP ( Y => n_347, IN1 => n_348, IN2 => n_352);
or1_223: OR1
PORT MAP ( Y => n_348, IN1 => n_349);
and1_224: AND1
PORT MAP ( Y => n_349, IN1 => n_350);
delay_225: DELAY
PORT MAP ( Y => n_350, IN1 => addr_dup02_Q);
and1_226: AND1
PORT MAP ( Y => n_352, IN1 => gnd);
delay_227: DELAY
PORT MAP ( Y => n_353, IN1 => n_354);
xor2_228: XOR2
PORT MAP ( Y => n_354, IN1 => n_355, IN2 => n_359);
or1_229: OR1
PORT MAP ( Y => n_355, IN1 => n_356);
and1_230: AND1
PORT MAP ( Y => n_356, IN1 => n_357);
delay_231: DELAY
PORT MAP ( Y => n_357, IN1 => addr_dup03_Q);
and1_232: AND1
PORT MAP ( Y => n_359, IN1 => gnd);
delay_233: DELAY
PORT MAP ( Y => n_360, IN1 => n_361);
xor2_234: XOR2
PORT MAP ( Y => n_361, IN1 => n_362, IN2 => n_366);
or1_235: OR1
PORT MAP ( Y => n_362, IN1 => n_363);
and1_236: AND1
PORT MAP ( Y => n_363, IN1 => n_364);
delay_237: DELAY
PORT MAP ( Y => n_364, IN1 => addr_dup04_Q);
and1_238: AND1
PORT MAP ( Y => n_366, IN1 => gnd);
delay_239: DELAY
PORT MAP ( Y => n_367, IN1 => n_368);
xor2_240: XOR2
PORT MAP ( Y => n_368, IN1 => n_369, IN2 => n_373);
or1_241: OR1
PORT MAP ( Y => n_369, IN1 => n_370);
and1_242: AND1
PORT MAP ( Y => n_370, IN1 => n_371);
delay_243: DELAY
PORT MAP ( Y => n_371, IN1 => addr_dup05_Q);
and1_244: AND1
PORT MAP ( Y => n_373, IN1 => gnd);
delay_245: DELAY
PORT MAP ( Y => n_374, IN1 => n_375);
xor2_246: XOR2
PORT MAP ( Y => n_375, IN1 => n_376, IN2 => n_380);
or1_247: OR1
PORT MAP ( Y => n_376, IN1 => n_377);
and1_248: AND1
PORT MAP ( Y => n_377, IN1 => n_378);
delay_249: DELAY
PORT MAP ( Y => n_378, IN1 => addr_dup06_Q);
and1_250: AND1
PORT MAP ( Y => n_380, IN1 => gnd);
delay_251: DELAY
PORT MAP ( Y => n_381, IN1 => n_382);
xor2_252: XOR2
PORT MAP ( Y => n_382, IN1 => n_383, IN2 => n_387);
or1_253: OR1
PORT MAP ( Y => n_383, IN1 => n_384);
and1_254: AND1
PORT MAP ( Y => n_384, IN1 => n_385);
delay_255: DELAY
PORT MAP ( Y => n_385, IN1 => addr_dup07_Q);
and1_256: AND1
PORT MAP ( Y => n_387, IN1 => gnd);
delay_257: DELAY
PORT MAP ( Y => n_388, IN1 => n_389);
xor2_258: XOR2
PORT MAP ( Y => n_389, IN1 => n_390, IN2 => n_394);
or1_259: OR1
PORT MAP ( Y => n_390, IN1 => n_391);
and1_260: AND1
PORT MAP ( Y => n_391, IN1 => n_392);
delay_261: DELAY
PORT MAP ( Y => n_392, IN1 => addr_dup08_Q);
and1_262: AND1
PORT MAP ( Y => n_394, IN1 => gnd);
delay_263: DELAY
PORT MAP ( Y => n_395, IN1 => n_396);
xor2_264: XOR2
PORT MAP ( Y => n_396, IN1 => n_397, IN2 => n_401);
or1_265: OR1
PORT MAP ( Y => n_397, IN1 => n_398);
and1_266: AND1
PORT MAP ( Y => n_398, IN1 => n_399);
delay_267: DELAY
PORT MAP ( Y => n_399, IN1 => addr_dup09_Q);
and1_268: AND1
PORT MAP ( Y => n_401, IN1 => gnd);
delay_269: DELAY
PORT MAP ( Y => n_402, IN1 => n_403);
xor2_270: XOR2
PORT MAP ( Y => n_403, IN1 => n_404, IN2 => n_408);
or1_271: OR1
PORT MAP ( Y => n_404, IN1 => n_405);
and1_272: AND1
PORT MAP ( Y => n_405, IN1 => n_406);
delay_273: DELAY
PORT MAP ( Y => n_406, IN1 => addr_dup010_Q);
and1_274: AND1
PORT MAP ( Y => n_408, IN1 => gnd);
delay_275: DELAY
PORT MAP ( Y => n_409, IN1 => n_410);
xor2_276: XOR2
PORT MAP ( Y => n_410, IN1 => n_411, IN2 => n_415);
or1_277: OR1
PORT MAP ( Y => n_411, IN1 => n_412);
and1_278: AND1
PORT MAP ( Y => n_412, IN1 => n_413);
delay_279: DELAY
PORT MAP ( Y => n_413, IN1 => addr_dup011_Q);
and1_280: AND1
PORT MAP ( Y => n_415, IN1 => gnd);
delay_281: DELAY
PORT MAP ( Y => n_416, IN1 => n_417);
xor2_282: XOR2
PORT MAP ( Y => n_417, IN1 => n_418, IN2 => n_422);
or1_283: OR1
PORT MAP ( Y => n_418, IN1 => n_419);
and1_284: AND1
PORT MAP ( Y => n_419, IN1 => n_420);
delay_285: DELAY
PORT MAP ( Y => n_420, IN1 => addr_dup012_Q);
and1_286: AND1
PORT MAP ( Y => n_422, IN1 => gnd);
delay_287: DELAY
PORT MAP ( Y => n_423, IN1 => n_424);
xor2_288: XOR2
PORT MAP ( Y => n_424, IN1 => n_425, IN2 => n_429);
or1_289: OR1
PORT MAP ( Y => n_425, IN1 => n_426);
and1_290: AND1
PORT MAP ( Y => n_426, IN1 => n_427);
delay_291: DELAY
PORT MAP ( Y => n_427, IN1 => addr_dup013_Q);
and1_292: AND1
PORT MAP ( Y => n_429, IN1 => gnd);
delay_293: DELAY
PORT MAP ( Y => n_430, IN1 => n_431);
xor2_294: XOR2
PORT MAP ( Y => n_431, IN1 => n_432, IN2 => n_436);
or1_295: OR1
PORT MAP ( Y => n_432, IN1 => n_433);
and1_296: AND1
PORT MAP ( Y => n_433, IN1 => n_434);
delay_297: DELAY
PORT MAP ( Y => n_434, IN1 => addr_dup014_Q);
and1_298: AND1
PORT MAP ( Y => n_436, IN1 => gnd);
delay_299: DELAY
PORT MAP ( Y => n_437, IN1 => n_438);
xor2_300: XOR2
PORT MAP ( Y => n_438, IN1 => n_439, IN2 => n_443);
or1_301: OR1
PORT MAP ( Y => n_439, IN1 => n_440);
and1_302: AND1
PORT MAP ( Y => n_440, IN1 => n_441);
delay_303: DELAY
PORT MAP ( Y => n_441, IN1 => addr_dup015_Q);
and1_304: AND1
PORT MAP ( Y => n_443, IN1 => gnd);
delay_305: DELAY
PORT MAP ( Y => O_dup_876_aOUT, IN1 => O_dup_876_aIN);
xor2_306: XOR2
PORT MAP ( Y => O_dup_876_aIN, IN1 => n_446, IN2 => n_452);
or1_307: OR1
PORT MAP ( Y => n_446, IN1 => n_447);
and2_308: AND2
PORT MAP ( Y => n_447, IN1 => n_448, IN2 => n_450);
delay_309: DELAY
PORT MAP ( Y => n_448, IN1 => I2_dup_823_aOUT);
delay_310: DELAY
PORT MAP ( Y => n_450, IN1 => ix484_nx43_aOUT);
and1_311: AND1
PORT MAP ( Y => n_452, IN1 => gnd);
delay_312: DELAY
PORT MAP ( Y => ix484_nx40_aOUT, IN1 => ix484_nx40_aIN);
xor2_313: XOR2
PORT MAP ( Y => ix484_nx40_aIN, IN1 => n_455, IN2 => n_463);
or1_314: OR1
PORT MAP ( Y => n_455, IN1 => n_456);
and3_315: AND3
PORT MAP ( Y => n_456, IN1 => n_457, IN2 => n_459, IN3 => n_461);
inv_316: INV
PORT MAP ( Y => n_457, IN1 => I1_dup_755_aOUT);
delay_317: DELAY
PORT MAP ( Y => n_459, IN1 => regsel0_aOUT);
delay_318: DELAY
PORT MAP ( Y => n_461, IN1 => I2_dup_756_aOUT);
and1_319: AND1
PORT MAP ( Y => n_463, IN1 => gnd);
delay_320: DELAY
PORT MAP ( Y => O_dup_885_aOUT, IN1 => O_dup_885_aIN);
xor2_321: XOR2
PORT MAP ( Y => O_dup_885_aIN, IN1 => n_466, IN2 => n_470);
or1_322: OR1
PORT MAP ( Y => n_466, IN1 => n_467);
and2_323: AND2
PORT MAP ( Y => n_467, IN1 => n_468, IN2 => n_469);
delay_324: DELAY
PORT MAP ( Y => n_468, IN1 => I2_dup_823_aOUT);
delay_325: DELAY
PORT MAP ( Y => n_469, IN1 => ix484_nx40_aOUT);
and1_326: AND1
PORT MAP ( Y => n_470, IN1 => gnd);
delay_327: DELAY
PORT MAP ( Y => I1_dup_767_aOUT, IN1 => I1_dup_767_aIN);
xor2_328: XOR2
PORT MAP ( Y => I1_dup_767_aIN, IN1 => n_473, IN2 => n_478);
or1_329: OR1
PORT MAP ( Y => n_473, IN1 => n_474);
and2_330: AND2
PORT MAP ( Y => n_474, IN1 => n_475, IN2 => n_477);
inv_331: INV
PORT MAP ( Y => n_475, IN1 => O_dup_1034_aOUT);
delay_332: DELAY
PORT MAP ( Y => n_477, IN1 => regsel0_aOUT);
and1_333: AND1
PORT MAP ( Y => n_478, IN1 => gnd);
delay_334: DELAY
PORT MAP ( Y => ix484_nx44_aOUT, IN1 => ix484_nx44_aIN);
xor2_335: XOR2
PORT MAP ( Y => ix484_nx44_aIN, IN1 => n_481, IN2 => n_486);
or1_336: OR1
PORT MAP ( Y => n_481, IN1 => n_482);
and2_337: AND2
PORT MAP ( Y => n_482, IN1 => n_483, IN2 => n_485);
delay_338: DELAY
PORT MAP ( Y => n_483, IN1 => I0_dup_770_aOUT);
delay_339: DELAY
PORT MAP ( Y => n_485, IN1 => I1_dup_767_aOUT);
and1_340: AND1
PORT MAP ( Y => n_486, IN1 => gnd);
delay_341: DELAY
PORT MAP ( Y => O_dup_882_aOUT, IN1 => O_dup_882_aIN);
xor2_342: XOR2
PORT MAP ( Y => O_dup_882_aIN, IN1 => n_489, IN2 => n_493);
or1_343: OR1
PORT MAP ( Y => n_489, IN1 => n_490);
and2_344: AND2
PORT MAP ( Y => n_490, IN1 => n_491, IN2 => n_492);
delay_345: DELAY
PORT MAP ( Y => n_491, IN1 => I2_dup_823_aOUT);
delay_346: DELAY
PORT MAP ( Y => n_492, IN1 => ix484_nx44_aOUT);
and1_347: AND1
PORT MAP ( Y => n_493, IN1 => gnd);
delay_348: DELAY
PORT MAP ( Y => ix484_nx39_aOUT, IN1 => ix484_nx39_aIN);
xor2_349: XOR2
PORT MAP ( Y => ix484_nx39_aIN, IN1 => n_496, IN2 => n_501);
or1_350: OR1
PORT MAP ( Y => n_496, IN1 => n_497);
and3_351: AND3
PORT MAP ( Y => n_497, IN1 => n_498, IN2 => n_499, IN3 => n_500);
inv_352: INV
PORT MAP ( Y => n_498, IN1 => regsel0_aOUT);
delay_353: DELAY
PORT MAP ( Y => n_499, IN1 => I1_dup_755_aOUT);
delay_354: DELAY
PORT MAP ( Y => n_500, IN1 => I2_dup_756_aOUT);
and1_355: AND1
PORT MAP ( Y => n_501, IN1 => gnd);
delay_356: DELAY
PORT MAP ( Y => O_dup_891_aOUT, IN1 => O_dup_891_aIN);
xor2_357: XOR2
PORT MAP ( Y => O_dup_891_aIN, IN1 => n_504, IN2 => n_508);
or1_358: OR1
PORT MAP ( Y => n_504, IN1 => n_505);
and2_359: AND2
PORT MAP ( Y => n_505, IN1 => n_506, IN2 => n_507);
delay_360: DELAY
PORT MAP ( Y => n_506, IN1 => I2_dup_823_aOUT);
delay_361: DELAY
PORT MAP ( Y => n_507, IN1 => ix484_nx39_aOUT);
and1_362: AND1
PORT MAP ( Y => n_508, IN1 => gnd);
delay_363: DELAY
PORT MAP ( Y => ix484_nx42_aOUT, IN1 => ix484_nx42_aIN);
xor2_364: XOR2
PORT MAP ( Y => ix484_nx42_aIN, IN1 => n_511, IN2 => n_516);
or1_365: OR1
PORT MAP ( Y => n_511, IN1 => n_512);
and2_366: AND2
PORT MAP ( Y => n_512, IN1 => n_513, IN2 => n_515);
delay_367: DELAY
PORT MAP ( Y => n_513, IN1 => I0_dup_766_aOUT);
delay_368: DELAY
PORT MAP ( Y => n_515, IN1 => I1_dup_767_aOUT);
and1_369: AND1
PORT MAP ( Y => n_516, IN1 => gnd);
delay_370: DELAY
PORT MAP ( Y => O_dup_888_aOUT, IN1 => O_dup_888_aIN);
xor2_371: XOR2
PORT MAP ( Y => O_dup_888_aIN, IN1 => n_519, IN2 => n_523);
or1_372: OR1
PORT MAP ( Y => n_519, IN1 => n_520);
and2_373: AND2
PORT MAP ( Y => n_520, IN1 => n_521, IN2 => n_522);
delay_374: DELAY
PORT MAP ( Y => n_521, IN1 => I2_dup_823_aOUT);
delay_375: DELAY
PORT MAP ( Y => n_522, IN1 => ix484_nx42_aOUT);
and1_376: AND1
PORT MAP ( Y => n_523, IN1 => gnd);
delay_377: DELAY
PORT MAP ( Y => I0_dup_1373_aOUT, IN1 => I0_dup_1373_aIN);
xor2_378: XOR2
PORT MAP ( Y => I0_dup_1373_aIN, IN1 => n_526, IN2 => n_541);
or4_379: OR4
PORT MAP ( Y => n_526, IN1 => n_527, IN2 => n_530, IN3 => n_534, IN4 => n_538);
and2_380: AND2
PORT MAP ( Y => n_527, IN1 => n_528, IN2 => n_529);
inv_381: INV
PORT MAP ( Y => n_528, IN1 => O_dup_888_aOUT);
inv_382: INV
PORT MAP ( Y => n_529, IN1 => O_dup_891_aOUT);
and2_383: AND2
PORT MAP ( Y => n_530, IN1 => n_531, IN2 => n_533);
inv_384: INV
PORT MAP ( Y => n_531, IN1 => ix484_a3_dup_619_Q);
inv_385: INV
PORT MAP ( Y => n_533, IN1 => O_dup_891_aOUT);
and2_386: AND2
PORT MAP ( Y => n_534, IN1 => n_535, IN2 => n_537);
inv_387: INV
PORT MAP ( Y => n_535, IN1 => ix484_a6_dup_616_Q);
inv_388: INV
PORT MAP ( Y => n_537, IN1 => ix484_a3_dup_619_Q);
and2_389: AND2
PORT MAP ( Y => n_538, IN1 => n_539, IN2 => n_540);
inv_390: INV
PORT MAP ( Y => n_539, IN1 => ix484_a6_dup_616_Q);
inv_391: INV
PORT MAP ( Y => n_540, IN1 => O_dup_888_aOUT);
and1_392: AND1
PORT MAP ( Y => n_541, IN1 => gnd);
delay_393: DELAY
PORT MAP ( Y => O_dup_1375_aOUT, IN1 => O_dup_1375_aIN);
and2_394: AND2
PORT MAP ( Y => O_dup_1375_aIN, IN1 => n_544, IN2 => n_559);
or4_395: OR4
PORT MAP ( Y => n_544, IN1 => n_545, IN2 => n_548, IN3 => n_552, IN4 => n_556);
and2_396: AND2
PORT MAP ( Y => n_545, IN1 => n_546, IN2 => n_547);
inv_397: INV
PORT MAP ( Y => n_546, IN1 => O_dup_882_aOUT);
inv_398: INV
PORT MAP ( Y => n_547, IN1 => O_dup_885_aOUT);
and2_399: AND2
PORT MAP ( Y => n_548, IN1 => n_549, IN2 => n_551);
inv_400: INV
PORT MAP ( Y => n_549, IN1 => ix484_a1_dup_621_Q);
inv_401: INV
PORT MAP ( Y => n_551, IN1 => O_dup_885_aOUT);
and2_402: AND2
PORT MAP ( Y => n_552, IN1 => n_553, IN2 => n_555);
inv_403: INV
PORT MAP ( Y => n_553, IN1 => ix484_a5_dup_617_Q);
inv_404: INV
PORT MAP ( Y => n_555, IN1 => ix484_a1_dup_621_Q);
and2_405: AND2
PORT MAP ( Y => n_556, IN1 => n_557, IN2 => n_558);
inv_406: INV
PORT MAP ( Y => n_557, IN1 => ix484_a5_dup_617_Q);
inv_407: INV
PORT MAP ( Y => n_558, IN1 => O_dup_882_aOUT);
delay_408: DELAY
PORT MAP ( Y => n_559, IN1 => I0_dup_1373_aIN);
delay_409: DELAY
PORT MAP ( Y => O_dup_1697_aOUT, IN1 => O_dup_1697_aIN);
and2_410: AND2
PORT MAP ( Y => O_dup_1697_aIN, IN1 => n_562, IN2 => n_579);
or4_411: OR4
PORT MAP ( Y => n_562, IN1 => n_563, IN2 => n_568, IN3 => n_573, IN4 => n_576);
and2_412: AND2
PORT MAP ( Y => n_563, IN1 => n_564, IN2 => n_566);
inv_413: INV
PORT MAP ( Y => n_564, IN1 => outregrd_aOUT);
delay_414: DELAY
PORT MAP ( Y => n_566, IN1 => n3_aOUT);
and2_415: AND2
PORT MAP ( Y => n_568, IN1 => n_569, IN2 => n_571);
inv_416: INV
PORT MAP ( Y => n_569, IN1 => outreg_val4_Q);
inv_417: INV
PORT MAP ( Y => n_571, IN1 => progcntr_val4_Q);
and2_418: AND2
PORT MAP ( Y => n_573, IN1 => n_574, IN2 => n_575);
inv_419: INV
PORT MAP ( Y => n_574, IN1 => progcntr_val4_Q);
inv_420: INV
PORT MAP ( Y => n_575, IN1 => outregrd_aOUT);
and2_421: AND2
PORT MAP ( Y => n_576, IN1 => n_577, IN2 => n_578);
inv_422: INV
PORT MAP ( Y => n_577, IN1 => outreg_val4_Q);
delay_423: DELAY
PORT MAP ( Y => n_578, IN1 => n3_aOUT);
delay_424: DELAY
PORT MAP ( Y => n_579, IN1 => O_dup_1375_aIN);
delay_425: DELAY
PORT MAP ( Y => I1_dup_810_aOUT, IN1 => I1_dup_810_aIN);
and2_426: AND2
PORT MAP ( Y => I1_dup_810_aIN, IN1 => n_582, IN2 => n_598);
or4_427: OR4
PORT MAP ( Y => n_582, IN1 => n_583, IN2 => n_587, IN3 => n_591, IN4 => n_595);
and2_428: AND2
PORT MAP ( Y => n_583, IN1 => n_584, IN2 => n_585);
inv_429: INV
PORT MAP ( Y => n_584, IN1 => O_dup_876_aOUT);
inv_430: INV
PORT MAP ( Y => n_585, IN1 => O_dup_879_aOUT);
and2_431: AND2
PORT MAP ( Y => n_587, IN1 => n_588, IN2 => n_590);
inv_432: INV
PORT MAP ( Y => n_588, IN1 => ix484_a2_dup_620_Q);
inv_433: INV
PORT MAP ( Y => n_590, IN1 => O_dup_879_aOUT);
and2_434: AND2
PORT MAP ( Y => n_591, IN1 => n_592, IN2 => n_594);
inv_435: INV
PORT MAP ( Y => n_592, IN1 => ix484_a7_dup_615_Q);
inv_436: INV
PORT MAP ( Y => n_594, IN1 => ix484_a2_dup_620_Q);
and2_437: AND2
PORT MAP ( Y => n_595, IN1 => n_596, IN2 => n_597);
inv_438: INV
PORT MAP ( Y => n_596, IN1 => ix484_a7_dup_615_Q);
inv_439: INV
PORT MAP ( Y => n_597, IN1 => O_dup_876_aOUT);
delay_440: DELAY
PORT MAP ( Y => n_598, IN1 => O_dup_1697_aIN);
delay_441: DELAY
PORT MAP ( Y => O_dup_811_aOUT, IN1 => O_dup_811_aIN1);
and2_442: AND2
PORT MAP ( Y => O_dup_811_aIN1, IN1 => n_600, IN2 => n_617);
or4_443: OR4
PORT MAP ( Y => n_600, IN1 => n_601, IN2 => n_606, IN3 => n_610, IN4 => n_614);
and2_444: AND2
PORT MAP ( Y => n_601, IN1 => n_602, IN2 => n_604);
inv_445: INV
PORT MAP ( Y => n_602, IN1 => O_dup_870_aOUT);
inv_446: INV
PORT MAP ( Y => n_604, IN1 => O_dup_873_aOUT);
and2_447: AND2
PORT MAP ( Y => n_606, IN1 => n_607, IN2 => n_609);
inv_448: INV
PORT MAP ( Y => n_607, IN1 => ix484_a4_dup_618_Q);
inv_449: INV
PORT MAP ( Y => n_609, IN1 => O_dup_873_aOUT);
and2_450: AND2
PORT MAP ( Y => n_610, IN1 => n_611, IN2 => n_613);
inv_451: INV
PORT MAP ( Y => n_611, IN1 => ix484_a0_dup_622_Q);
inv_452: INV
PORT MAP ( Y => n_613, IN1 => ix484_a4_dup_618_Q);
and2_453: AND2
PORT MAP ( Y => n_614, IN1 => n_615, IN2 => n_616);
inv_454: INV
PORT MAP ( Y => n_615, IN1 => ix484_a0_dup_622_Q);
inv_455: INV
PORT MAP ( Y => n_616, IN1 => O_dup_870_aOUT);
delay_456: DELAY
PORT MAP ( Y => n_617, IN1 => I1_dup_810_aIN);
dff_457: DFF
PORT MAP ( D => instrregout4_aD, CLK => instrregout4_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout4_Q);
xor2_458: XOR2
PORT MAP ( Y => instrregout4_aD, IN1 => n_624, IN2 => n_627);
or1_459: OR1
PORT MAP ( Y => n_624, IN1 => n_625);
and1_460: AND1
PORT MAP ( Y => n_625, IN1 => n_626);
delay_461: DELAY
PORT MAP ( Y => n_626, IN1 => data(4));
and1_462: AND1
PORT MAP ( Y => n_627, IN1 => gnd);
and1_463: AND1
PORT MAP ( Y => n_628, IN1 => n_629);
delay_464: DELAY
PORT MAP ( Y => n_629, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_465: DELAY
PORT MAP ( Y => instrregout4_aCLK, IN1 => n_628);
delay_466: DELAY
PORT MAP ( Y => I0_dup_1401_aOUT, IN1 => I0_dup_1401_aIN);
xor2_467: XOR2
PORT MAP ( Y => I0_dup_1401_aIN, IN1 => n_634, IN2 => n_649);
or4_468: OR4
PORT MAP ( Y => n_634, IN1 => n_635, IN2 => n_638, IN3 => n_642, IN4 => n_646);
and2_469: AND2
PORT MAP ( Y => n_635, IN1 => n_636, IN2 => n_637);
inv_470: INV
PORT MAP ( Y => n_636, IN1 => O_dup_888_aOUT);
inv_471: INV
PORT MAP ( Y => n_637, IN1 => O_dup_891_aOUT);
and2_472: AND2
PORT MAP ( Y => n_638, IN1 => n_639, IN2 => n_641);
inv_473: INV
PORT MAP ( Y => n_639, IN1 => ix484_a3_dup_627_Q);
inv_474: INV
PORT MAP ( Y => n_641, IN1 => O_dup_891_aOUT);
and2_475: AND2
PORT MAP ( Y => n_642, IN1 => n_643, IN2 => n_645);
inv_476: INV
PORT MAP ( Y => n_643, IN1 => ix484_a6_dup_624_Q);
inv_477: INV
PORT MAP ( Y => n_645, IN1 => ix484_a3_dup_627_Q);
and2_478: AND2
PORT MAP ( Y => n_646, IN1 => n_647, IN2 => n_648);
inv_479: INV
PORT MAP ( Y => n_647, IN1 => ix484_a6_dup_624_Q);
inv_480: INV
PORT MAP ( Y => n_648, IN1 => O_dup_888_aOUT);
and1_481: AND1
PORT MAP ( Y => n_649, IN1 => gnd);
delay_482: DELAY
PORT MAP ( Y => O_dup_1403_aOUT, IN1 => O_dup_1403_aIN);
and2_483: AND2
PORT MAP ( Y => O_dup_1403_aIN, IN1 => n_652, IN2 => n_667);
or4_484: OR4
PORT MAP ( Y => n_652, IN1 => n_653, IN2 => n_656, IN3 => n_660, IN4 => n_664);
and2_485: AND2
PORT MAP ( Y => n_653, IN1 => n_654, IN2 => n_655);
inv_486: INV
PORT MAP ( Y => n_654, IN1 => O_dup_882_aOUT);
inv_487: INV
PORT MAP ( Y => n_655, IN1 => O_dup_885_aOUT);
and2_488: AND2
PORT MAP ( Y => n_656, IN1 => n_657, IN2 => n_659);
inv_489: INV
PORT MAP ( Y => n_657, IN1 => ix484_a1_dup_629_Q);
inv_490: INV
PORT MAP ( Y => n_659, IN1 => O_dup_885_aOUT);
and2_491: AND2
PORT MAP ( Y => n_660, IN1 => n_661, IN2 => n_663);
inv_492: INV
PORT MAP ( Y => n_661, IN1 => ix484_a5_dup_625_Q);
inv_493: INV
PORT MAP ( Y => n_663, IN1 => ix484_a1_dup_629_Q);
and2_494: AND2
PORT MAP ( Y => n_664, IN1 => n_665, IN2 => n_666);
inv_495: INV
PORT MAP ( Y => n_665, IN1 => ix484_a5_dup_625_Q);
inv_496: INV
PORT MAP ( Y => n_666, IN1 => O_dup_882_aOUT);
delay_497: DELAY
PORT MAP ( Y => n_667, IN1 => I0_dup_1401_aIN);
delay_498: DELAY
PORT MAP ( Y => O_dup_1705_aOUT, IN1 => O_dup_1705_aIN);
and2_499: AND2
PORT MAP ( Y => O_dup_1705_aIN, IN1 => n_670, IN2 => n_685);
or4_500: OR4
PORT MAP ( Y => n_670, IN1 => n_671, IN2 => n_674, IN3 => n_679, IN4 => n_682);
and2_501: AND2
PORT MAP ( Y => n_671, IN1 => n_672, IN2 => n_673);
inv_502: INV
PORT MAP ( Y => n_672, IN1 => outregrd_aOUT);
delay_503: DELAY
PORT MAP ( Y => n_673, IN1 => n3_aOUT);
and2_504: AND2
PORT MAP ( Y => n_674, IN1 => n_675, IN2 => n_677);
inv_505: INV
PORT MAP ( Y => n_675, IN1 => outreg_val3_Q);
inv_506: INV
PORT MAP ( Y => n_677, IN1 => progcntr_val3_Q);
and2_507: AND2
PORT MAP ( Y => n_679, IN1 => n_680, IN2 => n_681);
inv_508: INV
PORT MAP ( Y => n_680, IN1 => progcntr_val3_Q);
inv_509: INV
PORT MAP ( Y => n_681, IN1 => outregrd_aOUT);
and2_510: AND2
PORT MAP ( Y => n_682, IN1 => n_683, IN2 => n_684);
inv_511: INV
PORT MAP ( Y => n_683, IN1 => outreg_val3_Q);
delay_512: DELAY
PORT MAP ( Y => n_684, IN1 => n3_aOUT);
delay_513: DELAY
PORT MAP ( Y => n_685, IN1 => O_dup_1403_aIN);
delay_514: DELAY
PORT MAP ( Y => I1_dup_813_aOUT, IN1 => I1_dup_813_aIN);
and2_515: AND2
PORT MAP ( Y => I1_dup_813_aIN, IN1 => n_688, IN2 => n_703);
or4_516: OR4
PORT MAP ( Y => n_688, IN1 => n_689, IN2 => n_692, IN3 => n_696, IN4 => n_700);
and2_517: AND2
PORT MAP ( Y => n_689, IN1 => n_690, IN2 => n_691);
inv_518: INV
PORT MAP ( Y => n_690, IN1 => O_dup_876_aOUT);
inv_519: INV
PORT MAP ( Y => n_691, IN1 => O_dup_879_aOUT);
and2_520: AND2
PORT MAP ( Y => n_692, IN1 => n_693, IN2 => n_695);
inv_521: INV
PORT MAP ( Y => n_693, IN1 => ix484_a2_dup_628_Q);
inv_522: INV
PORT MAP ( Y => n_695, IN1 => O_dup_879_aOUT);
and2_523: AND2
PORT MAP ( Y => n_696, IN1 => n_697, IN2 => n_699);
inv_524: INV
PORT MAP ( Y => n_697, IN1 => ix484_a7_dup_623_Q);
inv_525: INV
PORT MAP ( Y => n_699, IN1 => ix484_a2_dup_628_Q);
and2_526: AND2
PORT MAP ( Y => n_700, IN1 => n_701, IN2 => n_702);
inv_527: INV
PORT MAP ( Y => n_701, IN1 => ix484_a7_dup_623_Q);
inv_528: INV
PORT MAP ( Y => n_702, IN1 => O_dup_876_aOUT);
delay_529: DELAY
PORT MAP ( Y => n_703, IN1 => O_dup_1705_aIN);
delay_530: DELAY
PORT MAP ( Y => O_dup_814_aOUT, IN1 => O_dup_814_aIN1);
and2_531: AND2
PORT MAP ( Y => O_dup_814_aIN1, IN1 => n_705, IN2 => n_720);
or4_532: OR4
PORT MAP ( Y => n_705, IN1 => n_706, IN2 => n_709, IN3 => n_713, IN4 => n_717);
and2_533: AND2
PORT MAP ( Y => n_706, IN1 => n_707, IN2 => n_708);
inv_534: INV
PORT MAP ( Y => n_707, IN1 => O_dup_870_aOUT);
inv_535: INV
PORT MAP ( Y => n_708, IN1 => O_dup_873_aOUT);
and2_536: AND2
PORT MAP ( Y => n_709, IN1 => n_710, IN2 => n_712);
inv_537: INV
PORT MAP ( Y => n_710, IN1 => ix484_a4_dup_626_Q);
inv_538: INV
PORT MAP ( Y => n_712, IN1 => O_dup_873_aOUT);
and2_539: AND2
PORT MAP ( Y => n_713, IN1 => n_714, IN2 => n_716);
inv_540: INV
PORT MAP ( Y => n_714, IN1 => ix484_a0_dup_630_Q);
inv_541: INV
PORT MAP ( Y => n_716, IN1 => ix484_a4_dup_626_Q);
and2_542: AND2
PORT MAP ( Y => n_717, IN1 => n_718, IN2 => n_719);
inv_543: INV
PORT MAP ( Y => n_718, IN1 => ix484_a0_dup_630_Q);
inv_544: INV
PORT MAP ( Y => n_719, IN1 => O_dup_870_aOUT);
delay_545: DELAY
PORT MAP ( Y => n_720, IN1 => I1_dup_813_aIN);
dff_546: DFF
PORT MAP ( D => instrregout3_aD, CLK => instrregout3_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout3_Q);
xor2_547: XOR2
PORT MAP ( Y => instrregout3_aD, IN1 => n_727, IN2 => n_730);
or1_548: OR1
PORT MAP ( Y => n_727, IN1 => n_728);
and1_549: AND1
PORT MAP ( Y => n_728, IN1 => n_729);
delay_550: DELAY
PORT MAP ( Y => n_729, IN1 => data(3));
and1_551: AND1
PORT MAP ( Y => n_730, IN1 => gnd);
and1_552: AND1
PORT MAP ( Y => n_731, IN1 => n_732);
delay_553: DELAY
PORT MAP ( Y => n_732, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_554: DELAY
PORT MAP ( Y => instrregout3_aCLK, IN1 => n_731);
delay_555: DELAY
PORT MAP ( Y => I0_dup_1429_aOUT, IN1 => I0_dup_1429_aIN);
xor2_556: XOR2
PORT MAP ( Y => I0_dup_1429_aIN, IN1 => n_736, IN2 => n_751);
or4_557: OR4
PORT MAP ( Y => n_736, IN1 => n_737, IN2 => n_740, IN3 => n_744, IN4 => n_748);
and2_558: AND2
PORT MAP ( Y => n_737, IN1 => n_738, IN2 => n_739);
inv_559: INV
PORT MAP ( Y => n_738, IN1 => O_dup_888_aOUT);
inv_560: INV
PORT MAP ( Y => n_739, IN1 => O_dup_891_aOUT);
and2_561: AND2
PORT MAP ( Y => n_740, IN1 => n_741, IN2 => n_743);
inv_562: INV
PORT MAP ( Y => n_741, IN1 => ix484_a3_dup_635_Q);
inv_563: INV
PORT MAP ( Y => n_743, IN1 => O_dup_891_aOUT);
and2_564: AND2
PORT MAP ( Y => n_744, IN1 => n_745, IN2 => n_747);
inv_565: INV
PORT MAP ( Y => n_745, IN1 => ix484_a6_dup_632_Q);
inv_566: INV
PORT MAP ( Y => n_747, IN1 => ix484_a3_dup_635_Q);
and2_567: AND2
PORT MAP ( Y => n_748, IN1 => n_749, IN2 => n_750);
inv_568: INV
PORT MAP ( Y => n_749, IN1 => ix484_a6_dup_632_Q);
inv_569: INV
PORT MAP ( Y => n_750, IN1 => O_dup_888_aOUT);
and1_570: AND1
PORT MAP ( Y => n_751, IN1 => gnd);
delay_571: DELAY
PORT MAP ( Y => O_dup_1431_aOUT, IN1 => O_dup_1431_aIN);
and2_572: AND2
PORT MAP ( Y => O_dup_1431_aIN, IN1 => n_754, IN2 => n_769);
or4_573: OR4
PORT MAP ( Y => n_754, IN1 => n_755, IN2 => n_758, IN3 => n_762, IN4 => n_766);
and2_574: AND2
PORT MAP ( Y => n_755, IN1 => n_756, IN2 => n_757);
inv_575: INV
PORT MAP ( Y => n_756, IN1 => O_dup_882_aOUT);
inv_576: INV
PORT MAP ( Y => n_757, IN1 => O_dup_885_aOUT);
and2_577: AND2
PORT MAP ( Y => n_758, IN1 => n_759, IN2 => n_761);
inv_578: INV
PORT MAP ( Y => n_759, IN1 => ix484_a1_dup_637_Q);
inv_579: INV
PORT MAP ( Y => n_761, IN1 => O_dup_885_aOUT);
and2_580: AND2
PORT MAP ( Y => n_762, IN1 => n_763, IN2 => n_765);
inv_581: INV
PORT MAP ( Y => n_763, IN1 => ix484_a5_dup_633_Q);
inv_582: INV
PORT MAP ( Y => n_765, IN1 => ix484_a1_dup_637_Q);
and2_583: AND2
PORT MAP ( Y => n_766, IN1 => n_767, IN2 => n_768);
inv_584: INV
PORT MAP ( Y => n_767, IN1 => ix484_a5_dup_633_Q);
inv_585: INV
PORT MAP ( Y => n_768, IN1 => O_dup_882_aOUT);
delay_586: DELAY
PORT MAP ( Y => n_769, IN1 => I0_dup_1429_aIN);
delay_587: DELAY
PORT MAP ( Y => O_dup_1713_aOUT, IN1 => O_dup_1713_aIN);
and2_588: AND2
PORT MAP ( Y => O_dup_1713_aIN, IN1 => n_772, IN2 => n_787);
or4_589: OR4
PORT MAP ( Y => n_772, IN1 => n_773, IN2 => n_776, IN3 => n_781, IN4 => n_784);
and2_590: AND2
PORT MAP ( Y => n_773, IN1 => n_774, IN2 => n_775);
inv_591: INV
PORT MAP ( Y => n_774, IN1 => outregrd_aOUT);
delay_592: DELAY
PORT MAP ( Y => n_775, IN1 => n3_aOUT);
and2_593: AND2
PORT MAP ( Y => n_776, IN1 => n_777, IN2 => n_779);
inv_594: INV
PORT MAP ( Y => n_777, IN1 => outreg_val2_Q);
inv_595: INV
PORT MAP ( Y => n_779, IN1 => progcntr_val2_Q);
and2_596: AND2
PORT MAP ( Y => n_781, IN1 => n_782, IN2 => n_783);
inv_597: INV
PORT MAP ( Y => n_782, IN1 => progcntr_val2_Q);
inv_598: INV
PORT MAP ( Y => n_783, IN1 => outregrd_aOUT);
and2_599: AND2
PORT MAP ( Y => n_784, IN1 => n_785, IN2 => n_786);
inv_600: INV
PORT MAP ( Y => n_785, IN1 => outreg_val2_Q);
delay_601: DELAY
PORT MAP ( Y => n_786, IN1 => n3_aOUT);
delay_602: DELAY
PORT MAP ( Y => n_787, IN1 => O_dup_1431_aIN);
delay_603: DELAY
PORT MAP ( Y => I1_dup_816_aOUT, IN1 => I1_dup_816_aIN);
and2_604: AND2
PORT MAP ( Y => I1_dup_816_aIN, IN1 => n_790, IN2 => n_805);
or4_605: OR4
PORT MAP ( Y => n_790, IN1 => n_791, IN2 => n_794, IN3 => n_798, IN4 => n_802);
and2_606: AND2
PORT MAP ( Y => n_791, IN1 => n_792, IN2 => n_793);
inv_607: INV
PORT MAP ( Y => n_792, IN1 => O_dup_876_aOUT);
inv_608: INV
PORT MAP ( Y => n_793, IN1 => O_dup_879_aOUT);
and2_609: AND2
PORT MAP ( Y => n_794, IN1 => n_795, IN2 => n_797);
inv_610: INV
PORT MAP ( Y => n_795, IN1 => ix484_a2_dup_636_Q);
inv_611: INV
PORT MAP ( Y => n_797, IN1 => O_dup_879_aOUT);
and2_612: AND2
PORT MAP ( Y => n_798, IN1 => n_799, IN2 => n_801);
inv_613: INV
PORT MAP ( Y => n_799, IN1 => ix484_a7_dup_631_Q);
inv_614: INV
PORT MAP ( Y => n_801, IN1 => ix484_a2_dup_636_Q);
and2_615: AND2
PORT MAP ( Y => n_802, IN1 => n_803, IN2 => n_804);
inv_616: INV
PORT MAP ( Y => n_803, IN1 => ix484_a7_dup_631_Q);
inv_617: INV
PORT MAP ( Y => n_804, IN1 => O_dup_876_aOUT);
delay_618: DELAY
PORT MAP ( Y => n_805, IN1 => O_dup_1713_aIN);
delay_619: DELAY
PORT MAP ( Y => O_dup_817_aOUT, IN1 => O_dup_817_aIN1);
and2_620: AND2
PORT MAP ( Y => O_dup_817_aIN1, IN1 => n_807, IN2 => n_822);
or4_621: OR4
PORT MAP ( Y => n_807, IN1 => n_808, IN2 => n_811, IN3 => n_815, IN4 => n_819);
and2_622: AND2
PORT MAP ( Y => n_808, IN1 => n_809, IN2 => n_810);
inv_623: INV
PORT MAP ( Y => n_809, IN1 => O_dup_870_aOUT);
inv_624: INV
PORT MAP ( Y => n_810, IN1 => O_dup_873_aOUT);
and2_625: AND2
PORT MAP ( Y => n_811, IN1 => n_812, IN2 => n_814);
inv_626: INV
PORT MAP ( Y => n_812, IN1 => ix484_a4_dup_634_Q);
inv_627: INV
PORT MAP ( Y => n_814, IN1 => O_dup_873_aOUT);
and2_628: AND2
PORT MAP ( Y => n_815, IN1 => n_816, IN2 => n_818);
inv_629: INV
PORT MAP ( Y => n_816, IN1 => ix484_a0_dup_638_Q);
inv_630: INV
PORT MAP ( Y => n_818, IN1 => ix484_a4_dup_634_Q);
and2_631: AND2
PORT MAP ( Y => n_819, IN1 => n_820, IN2 => n_821);
inv_632: INV
PORT MAP ( Y => n_820, IN1 => ix484_a0_dup_638_Q);
inv_633: INV
PORT MAP ( Y => n_821, IN1 => O_dup_870_aOUT);
delay_634: DELAY
PORT MAP ( Y => n_822, IN1 => I1_dup_816_aIN);
dff_635: DFF
PORT MAP ( D => instrregout2_aD, CLK => instrregout2_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout2_Q);
xor2_636: XOR2
PORT MAP ( Y => instrregout2_aD, IN1 => n_829, IN2 => n_832);
or1_637: OR1
PORT MAP ( Y => n_829, IN1 => n_830);
and1_638: AND1
PORT MAP ( Y => n_830, IN1 => n_831);
delay_639: DELAY
PORT MAP ( Y => n_831, IN1 => data(2));
and1_640: AND1
PORT MAP ( Y => n_832, IN1 => gnd);
and1_641: AND1
PORT MAP ( Y => n_833, IN1 => n_834);
delay_642: DELAY
PORT MAP ( Y => n_834, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_643: DELAY
PORT MAP ( Y => instrregout2_aCLK, IN1 => n_833);
delay_644: DELAY
PORT MAP ( Y => I0_dup_1345_aOUT, IN1 => I0_dup_1345_aIN);
xor2_645: XOR2
PORT MAP ( Y => I0_dup_1345_aIN, IN1 => n_838, IN2 => n_853);
or4_646: OR4
PORT MAP ( Y => n_838, IN1 => n_839, IN2 => n_842, IN3 => n_846, IN4 => n_850);
and2_647: AND2
PORT MAP ( Y => n_839, IN1 => n_840, IN2 => n_841);
inv_648: INV
PORT MAP ( Y => n_840, IN1 => O_dup_888_aOUT);
inv_649: INV
PORT MAP ( Y => n_841, IN1 => O_dup_891_aOUT);
and2_650: AND2
PORT MAP ( Y => n_842, IN1 => n_843, IN2 => n_845);
inv_651: INV
PORT MAP ( Y => n_843, IN1 => ix484_a3_dup_611_Q);
inv_652: INV
PORT MAP ( Y => n_845, IN1 => O_dup_891_aOUT);
and2_653: AND2
PORT MAP ( Y => n_846, IN1 => n_847, IN2 => n_849);
inv_654: INV
PORT MAP ( Y => n_847, IN1 => ix484_a6_dup_608_Q);
inv_655: INV
PORT MAP ( Y => n_849, IN1 => ix484_a3_dup_611_Q);
and2_656: AND2
PORT MAP ( Y => n_850, IN1 => n_851, IN2 => n_852);
inv_657: INV
PORT MAP ( Y => n_851, IN1 => ix484_a6_dup_608_Q);
inv_658: INV
PORT MAP ( Y => n_852, IN1 => O_dup_888_aOUT);
and1_659: AND1
PORT MAP ( Y => n_853, IN1 => gnd);
delay_660: DELAY
PORT MAP ( Y => O_dup_1347_aOUT, IN1 => O_dup_1347_aIN);
and2_661: AND2
PORT MAP ( Y => O_dup_1347_aIN, IN1 => n_856, IN2 => n_871);
or4_662: OR4
PORT MAP ( Y => n_856, IN1 => n_857, IN2 => n_860, IN3 => n_864, IN4 => n_868);
and2_663: AND2
PORT MAP ( Y => n_857, IN1 => n_858, IN2 => n_859);
inv_664: INV
PORT MAP ( Y => n_858, IN1 => O_dup_882_aOUT);
inv_665: INV
PORT MAP ( Y => n_859, IN1 => O_dup_885_aOUT);
and2_666: AND2
PORT MAP ( Y => n_860, IN1 => n_861, IN2 => n_863);
inv_667: INV
PORT MAP ( Y => n_861, IN1 => ix484_a1_dup_613_Q);
inv_668: INV
PORT MAP ( Y => n_863, IN1 => O_dup_885_aOUT);
and2_669: AND2
PORT MAP ( Y => n_864, IN1 => n_865, IN2 => n_867);
inv_670: INV
PORT MAP ( Y => n_865, IN1 => ix484_a5_dup_609_Q);
inv_671: INV
PORT MAP ( Y => n_867, IN1 => ix484_a1_dup_613_Q);
and2_672: AND2
PORT MAP ( Y => n_868, IN1 => n_869, IN2 => n_870);
inv_673: INV
PORT MAP ( Y => n_869, IN1 => ix484_a5_dup_609_Q);
inv_674: INV
PORT MAP ( Y => n_870, IN1 => O_dup_882_aOUT);
delay_675: DELAY
PORT MAP ( Y => n_871, IN1 => I0_dup_1345_aIN);
delay_676: DELAY
PORT MAP ( Y => O_dup_1689_aOUT, IN1 => O_dup_1689_aIN);
and2_677: AND2
PORT MAP ( Y => O_dup_1689_aIN, IN1 => n_874, IN2 => n_889);
or4_678: OR4
PORT MAP ( Y => n_874, IN1 => n_875, IN2 => n_878, IN3 => n_883, IN4 => n_886);
and2_679: AND2
PORT MAP ( Y => n_875, IN1 => n_876, IN2 => n_877);
inv_680: INV
PORT MAP ( Y => n_876, IN1 => outregrd_aOUT);
delay_681: DELAY
PORT MAP ( Y => n_877, IN1 => n3_aOUT);
and2_682: AND2
PORT MAP ( Y => n_878, IN1 => n_879, IN2 => n_881);
inv_683: INV
PORT MAP ( Y => n_879, IN1 => outreg_val5_Q);
inv_684: INV
PORT MAP ( Y => n_881, IN1 => progcntr_val5_Q);
and2_685: AND2
PORT MAP ( Y => n_883, IN1 => n_884, IN2 => n_885);
inv_686: INV
PORT MAP ( Y => n_884, IN1 => progcntr_val5_Q);
inv_687: INV
PORT MAP ( Y => n_885, IN1 => outregrd_aOUT);
and2_688: AND2
PORT MAP ( Y => n_886, IN1 => n_887, IN2 => n_888);
inv_689: INV
PORT MAP ( Y => n_887, IN1 => outreg_val5_Q);
delay_690: DELAY
PORT MAP ( Y => n_888, IN1 => n3_aOUT);
delay_691: DELAY
PORT MAP ( Y => n_889, IN1 => O_dup_1347_aIN);
delay_692: DELAY
PORT MAP ( Y => I1_dup_807_aOUT, IN1 => I1_dup_807_aIN);
and2_693: AND2
PORT MAP ( Y => I1_dup_807_aIN, IN1 => n_892, IN2 => n_907);
or4_694: OR4
PORT MAP ( Y => n_892, IN1 => n_893, IN2 => n_896, IN3 => n_900, IN4 => n_904);
and2_695: AND2
PORT MAP ( Y => n_893, IN1 => n_894, IN2 => n_895);
inv_696: INV
PORT MAP ( Y => n_894, IN1 => O_dup_876_aOUT);
inv_697: INV
PORT MAP ( Y => n_895, IN1 => O_dup_879_aOUT);
and2_698: AND2
PORT MAP ( Y => n_896, IN1 => n_897, IN2 => n_899);
inv_699: INV
PORT MAP ( Y => n_897, IN1 => ix484_a2_dup_612_Q);
inv_700: INV
PORT MAP ( Y => n_899, IN1 => O_dup_879_aOUT);
and2_701: AND2
PORT MAP ( Y => n_900, IN1 => n_901, IN2 => n_903);
inv_702: INV
PORT MAP ( Y => n_901, IN1 => ix484_a7_dup_607_Q);
inv_703: INV
PORT MAP ( Y => n_903, IN1 => ix484_a2_dup_612_Q);
and2_704: AND2
PORT MAP ( Y => n_904, IN1 => n_905, IN2 => n_906);
inv_705: INV
PORT MAP ( Y => n_905, IN1 => ix484_a7_dup_607_Q);
inv_706: INV
PORT MAP ( Y => n_906, IN1 => O_dup_876_aOUT);
delay_707: DELAY
PORT MAP ( Y => n_907, IN1 => O_dup_1689_aIN);
delay_708: DELAY
PORT MAP ( Y => O_dup_808_aOUT, IN1 => O_dup_808_aIN1);
and2_709: AND2
PORT MAP ( Y => O_dup_808_aIN1, IN1 => n_909, IN2 => n_924);
or4_710: OR4
PORT MAP ( Y => n_909, IN1 => n_910, IN2 => n_913, IN3 => n_917, IN4 => n_921);
and2_711: AND2
PORT MAP ( Y => n_910, IN1 => n_911, IN2 => n_912);
inv_712: INV
PORT MAP ( Y => n_911, IN1 => O_dup_870_aOUT);
inv_713: INV
PORT MAP ( Y => n_912, IN1 => O_dup_873_aOUT);
and2_714: AND2
PORT MAP ( Y => n_913, IN1 => n_914, IN2 => n_916);
inv_715: INV
PORT MAP ( Y => n_914, IN1 => ix484_a4_dup_610_Q);
inv_716: INV
PORT MAP ( Y => n_916, IN1 => O_dup_873_aOUT);
and2_717: AND2
PORT MAP ( Y => n_917, IN1 => n_918, IN2 => n_920);
inv_718: INV
PORT MAP ( Y => n_918, IN1 => ix484_a0_dup_614_Q);
inv_719: INV
PORT MAP ( Y => n_920, IN1 => ix484_a4_dup_610_Q);
and2_720: AND2
PORT MAP ( Y => n_921, IN1 => n_922, IN2 => n_923);
inv_721: INV
PORT MAP ( Y => n_922, IN1 => ix484_a0_dup_614_Q);
inv_722: INV
PORT MAP ( Y => n_923, IN1 => O_dup_870_aOUT);
delay_723: DELAY
PORT MAP ( Y => n_924, IN1 => I1_dup_807_aIN);
dff_724: DFF
PORT MAP ( D => instrregout5_aD, CLK => instrregout5_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout5_Q);
xor2_725: XOR2
PORT MAP ( Y => instrregout5_aD, IN1 => n_931, IN2 => n_934);
or1_726: OR1
PORT MAP ( Y => n_931, IN1 => n_932);
and1_727: AND1
PORT MAP ( Y => n_932, IN1 => n_933);
delay_728: DELAY
PORT MAP ( Y => n_933, IN1 => data(5));
and1_729: AND1
PORT MAP ( Y => n_934, IN1 => gnd);
and1_730: AND1
PORT MAP ( Y => n_935, IN1 => n_936);
delay_731: DELAY
PORT MAP ( Y => n_936, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_732: DELAY
PORT MAP ( Y => instrregout5_aCLK, IN1 => n_935);
dff_733: DFF
PORT MAP ( D => con1_current_state31_aD, CLK => con1_current_state31_aCLK,
CLRN => con1_current_state31_aCLRN, PRN => vcc, Q => con1_current_state31_Q);
inv_734: INV
PORT MAP ( Y => con1_current_state31_aCLRN, IN1 => reset);
xor2_735: XOR2
PORT MAP ( Y => con1_current_state31_aD, IN1 => n_946, IN2 => n_950);
or1_736: OR1
PORT MAP ( Y => n_946, IN1 => n_947);
and1_737: AND1
PORT MAP ( Y => n_947, IN1 => n_948);
delay_738: DELAY
PORT MAP ( Y => n_948, IN1 => opregwr_Q);
and1_739: AND1
PORT MAP ( Y => n_950, IN1 => gnd);
delay_740: DELAY
PORT MAP ( Y => con1_current_state31_aCLK, IN1 => clock);
dff_741: DFF
PORT MAP ( D => con1_current_state32_aD, CLK => con1_current_state32_aCLK,
CLRN => con1_current_state32_aCLRN, PRN => vcc, Q => con1_current_state32_Q);
inv_742: INV
PORT MAP ( Y => con1_current_state32_aCLRN, IN1 => reset);
xor2_743: XOR2
PORT MAP ( Y => con1_current_state32_aD, IN1 => n_960, IN2 => n_963);
or1_744: OR1
PORT MAP ( Y => n_960, IN1 => n_961);
and1_745: AND1
PORT MAP ( Y => n_961, IN1 => n_962);
delay_746: DELAY
PORT MAP ( Y => n_962, IN1 => con1_current_state31_Q);
and1_747: AND1
PORT MAP ( Y => n_963, IN1 => gnd);
delay_748: DELAY
PORT MAP ( Y => con1_current_state32_aCLK, IN1 => clock);
delay_749: DELAY
PORT MAP ( Y => con1_modgen_63_nx10_aOUT, IN1 => con1_modgen_63_nx10_aIN);
xor2_750: XOR2
PORT MAP ( Y => con1_modgen_63_nx10_aIN, IN1 => n_967, IN2 => n_974);
or2_751: OR2
PORT MAP ( Y => n_967, IN1 => n_968, IN2 => n_971);
and1_752: AND1
PORT MAP ( Y => n_968, IN1 => n_969);
inv_753: INV
PORT MAP ( Y => n_969, IN1 => instrregout12_Q);
and1_754: AND1
PORT MAP ( Y => n_971, IN1 => n_972);
inv_755: INV
PORT MAP ( Y => n_972, IN1 => instrregout11_Q);
and1_756: AND1
PORT MAP ( Y => n_974, IN1 => gnd);
dff_757: DFF
PORT MAP ( D => con1_current_state17_aD, CLK => con1_current_state17_aCLK,
CLRN => con1_current_state17_aCLRN, PRN => vcc, Q => con1_current_state17_Q);
inv_758: INV
PORT MAP ( Y => con1_current_state17_aCLRN, IN1 => reset);
xor2_759: XOR2
PORT MAP ( Y => con1_current_state17_aD, IN1 => n_982, IN2 => n_991);
or1_760: OR1
PORT MAP ( Y => n_982, IN1 => n_983);
and4_761: AND4
PORT MAP ( Y => n_983, IN1 => n_984, IN2 => n_986, IN3 => n_987, IN4 => n_989);
inv_762: INV
PORT MAP ( Y => n_984, IN1 => instrregout15_Q);
inv_763: INV
PORT MAP ( Y => n_986, IN1 => con1_modgen_63_nx10_aOUT);
inv_764: INV
PORT MAP ( Y => n_987, IN1 => con1_modgen_61_nx12_aOUT);
delay_765: DELAY
PORT MAP ( Y => n_989, IN1 => con1_current_state6_Q);
and1_766: AND1
PORT MAP ( Y => n_991, IN1 => gnd);
delay_767: DELAY
PORT MAP ( Y => con1_current_state17_aCLK, IN1 => clock);
delay_768: DELAY
PORT MAP ( Y => I0_dup_1457_aOUT, IN1 => I0_dup_1457_aIN);
xor2_769: XOR2
PORT MAP ( Y => I0_dup_1457_aIN, IN1 => n_995, IN2 => n_1010);
or4_770: OR4
PORT MAP ( Y => n_995, IN1 => n_996, IN2 => n_999, IN3 => n_1003, IN4 => n_1007);
and2_771: AND2
PORT MAP ( Y => n_996, IN1 => n_997, IN2 => n_998);
inv_772: INV
PORT MAP ( Y => n_997, IN1 => O_dup_888_aOUT);
inv_773: INV
PORT MAP ( Y => n_998, IN1 => O_dup_891_aOUT);
and2_774: AND2
PORT MAP ( Y => n_999, IN1 => n_1000, IN2 => n_1002);
inv_775: INV
PORT MAP ( Y => n_1000, IN1 => ix484_a3_dup_643_Q);
inv_776: INV
PORT MAP ( Y => n_1002, IN1 => O_dup_891_aOUT);
and2_777: AND2
PORT MAP ( Y => n_1003, IN1 => n_1004, IN2 => n_1006);
inv_778: INV
PORT MAP ( Y => n_1004, IN1 => ix484_a6_dup_640_Q);
inv_779: INV
PORT MAP ( Y => n_1006, IN1 => ix484_a3_dup_643_Q);
and2_780: AND2
PORT MAP ( Y => n_1007, IN1 => n_1008, IN2 => n_1009);
inv_781: INV
PORT MAP ( Y => n_1008, IN1 => ix484_a6_dup_640_Q);
inv_782: INV
PORT MAP ( Y => n_1009, IN1 => O_dup_888_aOUT);
and1_783: AND1
PORT MAP ( Y => n_1010, IN1 => gnd);
delay_784: DELAY
PORT MAP ( Y => O_dup_1459_aOUT, IN1 => O_dup_1459_aIN);
and2_785: AND2
PORT MAP ( Y => O_dup_1459_aIN, IN1 => n_1013, IN2 => n_1028);
or4_786: OR4
PORT MAP ( Y => n_1013, IN1 => n_1014, IN2 => n_1017, IN3 => n_1021, IN4 => n_1025);
and2_787: AND2
PORT MAP ( Y => n_1014, IN1 => n_1015, IN2 => n_1016);
inv_788: INV
PORT MAP ( Y => n_1015, IN1 => O_dup_882_aOUT);
inv_789: INV
PORT MAP ( Y => n_1016, IN1 => O_dup_885_aOUT);
and2_790: AND2
PORT MAP ( Y => n_1017, IN1 => n_1018, IN2 => n_1020);
inv_791: INV
PORT MAP ( Y => n_1018, IN1 => ix484_a1_dup_645_Q);
inv_792: INV
PORT MAP ( Y => n_1020, IN1 => O_dup_885_aOUT);
and2_793: AND2
PORT MAP ( Y => n_1021, IN1 => n_1022, IN2 => n_1024);
inv_794: INV
PORT MAP ( Y => n_1022, IN1 => ix484_a5_dup_641_Q);
inv_795: INV
PORT MAP ( Y => n_1024, IN1 => ix484_a1_dup_645_Q);
and2_796: AND2
PORT MAP ( Y => n_1025, IN1 => n_1026, IN2 => n_1027);
inv_797: INV
PORT MAP ( Y => n_1026, IN1 => ix484_a5_dup_641_Q);
inv_798: INV
PORT MAP ( Y => n_1027, IN1 => O_dup_882_aOUT);
delay_799: DELAY
PORT MAP ( Y => n_1028, IN1 => I0_dup_1457_aIN);
delay_800: DELAY
PORT MAP ( Y => O_dup_1721_aOUT, IN1 => O_dup_1721_aIN);
and2_801: AND2
PORT MAP ( Y => O_dup_1721_aIN, IN1 => n_1031, IN2 => n_1046);
or4_802: OR4
PORT MAP ( Y => n_1031, IN1 => n_1032, IN2 => n_1035, IN3 => n_1040, IN4 => n_1043);
and2_803: AND2
PORT MAP ( Y => n_1032, IN1 => n_1033, IN2 => n_1034);
inv_804: INV
PORT MAP ( Y => n_1033, IN1 => outregrd_aOUT);
delay_805: DELAY
PORT MAP ( Y => n_1034, IN1 => n3_aOUT);
and2_806: AND2
PORT MAP ( Y => n_1035, IN1 => n_1036, IN2 => n_1038);
inv_807: INV
PORT MAP ( Y => n_1036, IN1 => outreg_val1_Q);
inv_808: INV
PORT MAP ( Y => n_1038, IN1 => progcntr_val1_Q);
and2_809: AND2
PORT MAP ( Y => n_1040, IN1 => n_1041, IN2 => n_1042);
inv_810: INV
PORT MAP ( Y => n_1041, IN1 => progcntr_val1_Q);
inv_811: INV
PORT MAP ( Y => n_1042, IN1 => outregrd_aOUT);
and2_812: AND2
PORT MAP ( Y => n_1043, IN1 => n_1044, IN2 => n_1045);
inv_813: INV
PORT MAP ( Y => n_1044, IN1 => outreg_val1_Q);
delay_814: DELAY
PORT MAP ( Y => n_1045, IN1 => n3_aOUT);
delay_815: DELAY
PORT MAP ( Y => n_1046, IN1 => O_dup_1459_aIN);
delay_816: DELAY
PORT MAP ( Y => I1_dup_819_aOUT, IN1 => I1_dup_819_aIN);
and2_817: AND2
PORT MAP ( Y => I1_dup_819_aIN, IN1 => n_1049, IN2 => n_1064);
or4_818: OR4
PORT MAP ( Y => n_1049, IN1 => n_1050, IN2 => n_1053, IN3 => n_1057, IN4 => n_1061);
and2_819: AND2
PORT MAP ( Y => n_1050, IN1 => n_1051, IN2 => n_1052);
inv_820: INV
PORT MAP ( Y => n_1051, IN1 => O_dup_876_aOUT);
inv_821: INV
PORT MAP ( Y => n_1052, IN1 => O_dup_879_aOUT);
and2_822: AND2
PORT MAP ( Y => n_1053, IN1 => n_1054, IN2 => n_1056);
inv_823: INV
PORT MAP ( Y => n_1054, IN1 => ix484_a2_dup_644_Q);
inv_824: INV
PORT MAP ( Y => n_1056, IN1 => O_dup_879_aOUT);
and2_825: AND2
PORT MAP ( Y => n_1057, IN1 => n_1058, IN2 => n_1060);
inv_826: INV
PORT MAP ( Y => n_1058, IN1 => ix484_a7_dup_639_Q);
inv_827: INV
PORT MAP ( Y => n_1060, IN1 => ix484_a2_dup_644_Q);
and2_828: AND2
PORT MAP ( Y => n_1061, IN1 => n_1062, IN2 => n_1063);
inv_829: INV
PORT MAP ( Y => n_1062, IN1 => ix484_a7_dup_639_Q);
inv_830: INV
PORT MAP ( Y => n_1063, IN1 => O_dup_876_aOUT);
delay_831: DELAY
PORT MAP ( Y => n_1064, IN1 => O_dup_1721_aIN);
delay_832: DELAY
PORT MAP ( Y => O_dup_820_aOUT, IN1 => O_dup_820_aIN1);
and2_833: AND2
PORT MAP ( Y => O_dup_820_aIN1, IN1 => n_1066, IN2 => n_1081);
or4_834: OR4
PORT MAP ( Y => n_1066, IN1 => n_1067, IN2 => n_1070, IN3 => n_1074, IN4 => n_1078);
and2_835: AND2
PORT MAP ( Y => n_1067, IN1 => n_1068, IN2 => n_1069);
inv_836: INV
PORT MAP ( Y => n_1068, IN1 => O_dup_870_aOUT);
inv_837: INV
PORT MAP ( Y => n_1069, IN1 => O_dup_873_aOUT);
and2_838: AND2
PORT MAP ( Y => n_1070, IN1 => n_1071, IN2 => n_1073);
inv_839: INV
PORT MAP ( Y => n_1071, IN1 => ix484_a4_dup_642_Q);
inv_840: INV
PORT MAP ( Y => n_1073, IN1 => O_dup_873_aOUT);
and2_841: AND2
PORT MAP ( Y => n_1074, IN1 => n_1075, IN2 => n_1077);
inv_842: INV
PORT MAP ( Y => n_1075, IN1 => ix484_a0_dup_646_Q);
inv_843: INV
PORT MAP ( Y => n_1077, IN1 => ix484_a4_dup_642_Q);
and2_844: AND2
PORT MAP ( Y => n_1078, IN1 => n_1079, IN2 => n_1080);
inv_845: INV
PORT MAP ( Y => n_1079, IN1 => ix484_a0_dup_646_Q);
inv_846: INV
PORT MAP ( Y => n_1080, IN1 => O_dup_870_aOUT);
delay_847: DELAY
PORT MAP ( Y => n_1081, IN1 => I1_dup_819_aIN);
dff_848: DFF
PORT MAP ( D => instrregout1_aD, CLK => instrregout1_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout1_Q);
xor2_849: XOR2
PORT MAP ( Y => instrregout1_aD, IN1 => n_1088, IN2 => n_1091);
or1_850: OR1
PORT MAP ( Y => n_1088, IN1 => n_1089);
and1_851: AND1
PORT MAP ( Y => n_1089, IN1 => n_1090);
delay_852: DELAY
PORT MAP ( Y => n_1090, IN1 => data(1));
and1_853: AND1
PORT MAP ( Y => n_1091, IN1 => gnd);
and1_854: AND1
PORT MAP ( Y => n_1092, IN1 => n_1093);
delay_855: DELAY
PORT MAP ( Y => n_1093, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_856: DELAY
PORT MAP ( Y => instrregout1_aCLK, IN1 => n_1092);
delay_857: DELAY
PORT MAP ( Y => I0_dup_1485_aOUT, IN1 => I0_dup_1485_aIN);
xor2_858: XOR2
PORT MAP ( Y => I0_dup_1485_aIN, IN1 => n_1097, IN2 => n_1112);
or4_859: OR4
PORT MAP ( Y => n_1097, IN1 => n_1098, IN2 => n_1101, IN3 => n_1105, IN4 => n_1109);
and2_860: AND2
PORT MAP ( Y => n_1098, IN1 => n_1099, IN2 => n_1100);
inv_861: INV
PORT MAP ( Y => n_1099, IN1 => O_dup_888_aOUT);
inv_862: INV
PORT MAP ( Y => n_1100, IN1 => O_dup_891_aOUT);
and2_863: AND2
PORT MAP ( Y => n_1101, IN1 => n_1102, IN2 => n_1104);
inv_864: INV
PORT MAP ( Y => n_1102, IN1 => ix484_a3_dup_651_Q);
inv_865: INV
PORT MAP ( Y => n_1104, IN1 => O_dup_891_aOUT);
and2_866: AND2
PORT MAP ( Y => n_1105, IN1 => n_1106, IN2 => n_1108);
inv_867: INV
PORT MAP ( Y => n_1106, IN1 => ix484_a6_dup_648_Q);
inv_868: INV
PORT MAP ( Y => n_1108, IN1 => ix484_a3_dup_651_Q);
and2_869: AND2
PORT MAP ( Y => n_1109, IN1 => n_1110, IN2 => n_1111);
inv_870: INV
PORT MAP ( Y => n_1110, IN1 => ix484_a6_dup_648_Q);
inv_871: INV
PORT MAP ( Y => n_1111, IN1 => O_dup_888_aOUT);
and1_872: AND1
PORT MAP ( Y => n_1112, IN1 => gnd);
delay_873: DELAY
PORT MAP ( Y => O_dup_1487_aOUT, IN1 => O_dup_1487_aIN);
and2_874: AND2
PORT MAP ( Y => O_dup_1487_aIN, IN1 => n_1115, IN2 => n_1130);
or4_875: OR4
PORT MAP ( Y => n_1115, IN1 => n_1116, IN2 => n_1119, IN3 => n_1123, IN4 => n_1127);
and2_876: AND2
PORT MAP ( Y => n_1116, IN1 => n_1117, IN2 => n_1118);
inv_877: INV
PORT MAP ( Y => n_1117, IN1 => O_dup_882_aOUT);
inv_878: INV
PORT MAP ( Y => n_1118, IN1 => O_dup_885_aOUT);
and2_879: AND2
PORT MAP ( Y => n_1119, IN1 => n_1120, IN2 => n_1122);
inv_880: INV
PORT MAP ( Y => n_1120, IN1 => ix484_a1_dup_653_Q);
inv_881: INV
PORT MAP ( Y => n_1122, IN1 => O_dup_885_aOUT);
and2_882: AND2
PORT MAP ( Y => n_1123, IN1 => n_1124, IN2 => n_1126);
inv_883: INV
PORT MAP ( Y => n_1124, IN1 => ix484_a5_dup_649_Q);
inv_884: INV
PORT MAP ( Y => n_1126, IN1 => ix484_a1_dup_653_Q);
and2_885: AND2
PORT MAP ( Y => n_1127, IN1 => n_1128, IN2 => n_1129);
inv_886: INV
PORT MAP ( Y => n_1128, IN1 => ix484_a5_dup_649_Q);
inv_887: INV
PORT MAP ( Y => n_1129, IN1 => O_dup_882_aOUT);
delay_888: DELAY
PORT MAP ( Y => n_1130, IN1 => I0_dup_1485_aIN);
delay_889: DELAY
PORT MAP ( Y => O_dup_1729_aOUT, IN1 => O_dup_1729_aIN);
and2_890: AND2
PORT MAP ( Y => O_dup_1729_aIN, IN1 => n_1133, IN2 => n_1148);
or4_891: OR4
PORT MAP ( Y => n_1133, IN1 => n_1134, IN2 => n_1137, IN3 => n_1142, IN4 => n_1145);
and2_892: AND2
PORT MAP ( Y => n_1134, IN1 => n_1135, IN2 => n_1136);
inv_893: INV
PORT MAP ( Y => n_1135, IN1 => outregrd_aOUT);
delay_894: DELAY
PORT MAP ( Y => n_1136, IN1 => n3_aOUT);
and2_895: AND2
PORT MAP ( Y => n_1137, IN1 => n_1138, IN2 => n_1140);
inv_896: INV
PORT MAP ( Y => n_1138, IN1 => outreg_val0_Q);
inv_897: INV
PORT MAP ( Y => n_1140, IN1 => progcntr_val0_Q);
and2_898: AND2
PORT MAP ( Y => n_1142, IN1 => n_1143, IN2 => n_1144);
inv_899: INV
PORT MAP ( Y => n_1143, IN1 => progcntr_val0_Q);
inv_900: INV
PORT MAP ( Y => n_1144, IN1 => outregrd_aOUT);
and2_901: AND2
PORT MAP ( Y => n_1145, IN1 => n_1146, IN2 => n_1147);
inv_902: INV
PORT MAP ( Y => n_1146, IN1 => outreg_val0_Q);
delay_903: DELAY
PORT MAP ( Y => n_1147, IN1 => n3_aOUT);
delay_904: DELAY
PORT MAP ( Y => n_1148, IN1 => O_dup_1487_aIN);
delay_905: DELAY
PORT MAP ( Y => I1_dup_826_aOUT, IN1 => I1_dup_826_aIN);
and2_906: AND2
PORT MAP ( Y => I1_dup_826_aIN, IN1 => n_1151, IN2 => n_1166);
or4_907: OR4
PORT MAP ( Y => n_1151, IN1 => n_1152, IN2 => n_1155, IN3 => n_1159, IN4 => n_1163);
and2_908: AND2
PORT MAP ( Y => n_1152, IN1 => n_1153, IN2 => n_1154);
inv_909: INV
PORT MAP ( Y => n_1153, IN1 => O_dup_876_aOUT);
inv_910: INV
PORT MAP ( Y => n_1154, IN1 => O_dup_879_aOUT);
and2_911: AND2
PORT MAP ( Y => n_1155, IN1 => n_1156, IN2 => n_1158);
inv_912: INV
PORT MAP ( Y => n_1156, IN1 => ix484_a2_dup_652_Q);
inv_913: INV
PORT MAP ( Y => n_1158, IN1 => O_dup_879_aOUT);
and2_914: AND2
PORT MAP ( Y => n_1159, IN1 => n_1160, IN2 => n_1162);
inv_915: INV
PORT MAP ( Y => n_1160, IN1 => ix484_a7_dup_647_Q);
inv_916: INV
PORT MAP ( Y => n_1162, IN1 => ix484_a2_dup_652_Q);
and2_917: AND2
PORT MAP ( Y => n_1163, IN1 => n_1164, IN2 => n_1165);
inv_918: INV
PORT MAP ( Y => n_1164, IN1 => ix484_a7_dup_647_Q);
inv_919: INV
PORT MAP ( Y => n_1165, IN1 => O_dup_876_aOUT);
delay_920: DELAY
PORT MAP ( Y => n_1166, IN1 => O_dup_1729_aIN);
delay_921: DELAY
PORT MAP ( Y => O_dup_827_aOUT, IN1 => O_dup_827_aIN1);
and2_922: AND2
PORT MAP ( Y => O_dup_827_aIN1, IN1 => n_1168, IN2 => n_1183);
or4_923: OR4
PORT MAP ( Y => n_1168, IN1 => n_1169, IN2 => n_1172, IN3 => n_1176, IN4 => n_1180);
and2_924: AND2
PORT MAP ( Y => n_1169, IN1 => n_1170, IN2 => n_1171);
inv_925: INV
PORT MAP ( Y => n_1170, IN1 => O_dup_870_aOUT);
inv_926: INV
PORT MAP ( Y => n_1171, IN1 => O_dup_873_aOUT);
and2_927: AND2
PORT MAP ( Y => n_1172, IN1 => n_1173, IN2 => n_1175);
inv_928: INV
PORT MAP ( Y => n_1173, IN1 => ix484_a4_dup_650_Q);
inv_929: INV
PORT MAP ( Y => n_1175, IN1 => O_dup_873_aOUT);
and2_930: AND2
PORT MAP ( Y => n_1176, IN1 => n_1177, IN2 => n_1179);
inv_931: INV
PORT MAP ( Y => n_1177, IN1 => ix484_a0_dup_654_Q);
inv_932: INV
PORT MAP ( Y => n_1179, IN1 => ix484_a4_dup_650_Q);
and2_933: AND2
PORT MAP ( Y => n_1180, IN1 => n_1181, IN2 => n_1182);
inv_934: INV
PORT MAP ( Y => n_1181, IN1 => ix484_a0_dup_654_Q);
inv_935: INV
PORT MAP ( Y => n_1182, IN1 => O_dup_870_aOUT);
delay_936: DELAY
PORT MAP ( Y => n_1183, IN1 => I1_dup_826_aIN);
dff_937: DFF
PORT MAP ( D => instrregout0_aD, CLK => instrregout0_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout0_Q);
xor2_938: XOR2
PORT MAP ( Y => instrregout0_aD, IN1 => n_1190, IN2 => n_1193);
or1_939: OR1
PORT MAP ( Y => n_1190, IN1 => n_1191);
and1_940: AND1
PORT MAP ( Y => n_1191, IN1 => n_1192);
delay_941: DELAY
PORT MAP ( Y => n_1192, IN1 => data(0));
and1_942: AND1
PORT MAP ( Y => n_1193, IN1 => gnd);
and1_943: AND1
PORT MAP ( Y => n_1194, IN1 => n_1195);
delay_944: DELAY
PORT MAP ( Y => n_1195, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_945: DELAY
PORT MAP ( Y => instrregout0_aCLK, IN1 => n_1194);
delay_946: DELAY
PORT MAP ( Y => I3_dup_673_aOUT, IN1 => I3_dup_673_aIN);
xor2_947: XOR2
PORT MAP ( Y => I3_dup_673_aIN, IN1 => n_1199, IN2 => n_1206);
or2_948: OR2
PORT MAP ( Y => n_1199, IN1 => n_1200, IN2 => n_1203);
and1_949: AND1
PORT MAP ( Y => n_1200, IN1 => n_1201);
delay_950: DELAY
PORT MAP ( Y => n_1201, IN1 => con1_current_state51_Q);
and1_951: AND1
PORT MAP ( Y => n_1203, IN1 => n_1204);
delay_952: DELAY
PORT MAP ( Y => n_1204, IN1 => con1_current_state19_Q);
and1_953: AND1
PORT MAP ( Y => n_1206, IN1 => gnd);
delay_954: DELAY
PORT MAP ( Y => a_as_or3_aix1635_a_a32_aOUT, IN1 => a_as_or3_aix1635_a_a32_aIN1);
xor2_955: XOR2
PORT MAP ( Y => a_as_or3_aix1635_a_a32_aIN1, IN1 => n_1209, IN2 => n_1220);
or3_956: OR3
PORT MAP ( Y => n_1209, IN1 => n_1210, IN2 => n_1213, IN3 => n_1215);
and1_957: AND1
PORT MAP ( Y => n_1210, IN1 => n_1211);
delay_958: DELAY
PORT MAP ( Y => n_1211, IN1 => con1_current_state13_Q);
and1_959: AND1
PORT MAP ( Y => n_1213, IN1 => n_1214);
delay_960: DELAY
PORT MAP ( Y => n_1214, IN1 => I3_dup_673_aOUT);
and2_961: AND2
PORT MAP ( Y => n_1215, IN1 => n_1216, IN2 => n_1218);
delay_962: DELAY
PORT MAP ( Y => n_1216, IN1 => ready);
delay_963: DELAY
PORT MAP ( Y => n_1218, IN1 => con1_current_state48_Q);
and1_964: AND1
PORT MAP ( Y => n_1220, IN1 => gnd);
dffe_965: DFFE
PORT MAP ( D => ix484_a3_dup_651_aD, CLK => ix484_a3_dup_651_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_651_aENA, Q => ix484_a3_dup_651_Q);
xor2_966: XOR2
PORT MAP ( Y => ix484_a3_dup_651_aD, IN1 => n_1227, IN2 => n_1230);
or1_967: OR1
PORT MAP ( Y => n_1227, IN1 => n_1228);
and1_968: AND1
PORT MAP ( Y => n_1228, IN1 => n_1229);
delay_969: DELAY
PORT MAP ( Y => n_1229, IN1 => data(0));
and1_970: AND1
PORT MAP ( Y => n_1230, IN1 => gnd);
and1_971: AND1
PORT MAP ( Y => n_1231, IN1 => n_1232);
delay_972: DELAY
PORT MAP ( Y => n_1232, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_973: DELAY
PORT MAP ( Y => ix484_a3_dup_651_aCLK, IN1 => n_1231);
and1_974: AND1
PORT MAP ( Y => ix484_a3_dup_651_aENA, IN1 => n_1235);
delay_975: DELAY
PORT MAP ( Y => n_1235, IN1 => ix484_nx42_aOUT);
dffe_976: DFFE
PORT MAP ( D => ix484_a6_dup_648_aD, CLK => ix484_a6_dup_648_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_648_aENA, Q => ix484_a6_dup_648_Q);
xor2_977: XOR2
PORT MAP ( Y => ix484_a6_dup_648_aD, IN1 => n_1242, IN2 => n_1245);
or1_978: OR1
PORT MAP ( Y => n_1242, IN1 => n_1243);
and1_979: AND1
PORT MAP ( Y => n_1243, IN1 => n_1244);
delay_980: DELAY
PORT MAP ( Y => n_1244, IN1 => data(0));
and1_981: AND1
PORT MAP ( Y => n_1245, IN1 => gnd);
and1_982: AND1
PORT MAP ( Y => n_1246, IN1 => n_1247);
delay_983: DELAY
PORT MAP ( Y => n_1247, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_984: DELAY
PORT MAP ( Y => ix484_a6_dup_648_aCLK, IN1 => n_1246);
and1_985: AND1
PORT MAP ( Y => ix484_a6_dup_648_aENA, IN1 => n_1250);
delay_986: DELAY
PORT MAP ( Y => n_1250, IN1 => ix484_nx39_aOUT);
dffe_987: DFFE
PORT MAP ( D => ix484_a3_dup_643_aD, CLK => ix484_a3_dup_643_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_643_aENA, Q => ix484_a3_dup_643_Q);
xor2_988: XOR2
PORT MAP ( Y => ix484_a3_dup_643_aD, IN1 => n_1257, IN2 => n_1260);
or1_989: OR1
PORT MAP ( Y => n_1257, IN1 => n_1258);
and1_990: AND1
PORT MAP ( Y => n_1258, IN1 => n_1259);
delay_991: DELAY
PORT MAP ( Y => n_1259, IN1 => data(1));
and1_992: AND1
PORT MAP ( Y => n_1260, IN1 => gnd);
and1_993: AND1
PORT MAP ( Y => n_1261, IN1 => n_1262);
delay_994: DELAY
PORT MAP ( Y => n_1262, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_995: DELAY
PORT MAP ( Y => ix484_a3_dup_643_aCLK, IN1 => n_1261);
and1_996: AND1
PORT MAP ( Y => ix484_a3_dup_643_aENA, IN1 => n_1265);
delay_997: DELAY
PORT MAP ( Y => n_1265, IN1 => ix484_nx42_aOUT);
dffe_998: DFFE
PORT MAP ( D => ix484_a6_dup_640_aD, CLK => ix484_a6_dup_640_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_640_aENA, Q => ix484_a6_dup_640_Q);
xor2_999: XOR2
PORT MAP ( Y => ix484_a6_dup_640_aD, IN1 => n_1272, IN2 => n_1275);
or1_1000: OR1
PORT MAP ( Y => n_1272, IN1 => n_1273);
and1_1001: AND1
PORT MAP ( Y => n_1273, IN1 => n_1274);
delay_1002: DELAY
PORT MAP ( Y => n_1274, IN1 => data(1));
and1_1003: AND1
PORT MAP ( Y => n_1275, IN1 => gnd);
and1_1004: AND1
PORT MAP ( Y => n_1276, IN1 => n_1277);
delay_1005: DELAY
PORT MAP ( Y => n_1277, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1006: DELAY
PORT MAP ( Y => ix484_a6_dup_640_aCLK, IN1 => n_1276);
and1_1007: AND1
PORT MAP ( Y => ix484_a6_dup_640_aENA, IN1 => n_1280);
delay_1008: DELAY
PORT MAP ( Y => n_1280, IN1 => ix484_nx39_aOUT);
dffe_1009: DFFE
PORT MAP ( D => ix484_a3_dup_635_aD, CLK => ix484_a3_dup_635_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_635_aENA, Q => ix484_a3_dup_635_Q);
xor2_1010: XOR2
PORT MAP ( Y => ix484_a3_dup_635_aD, IN1 => n_1287, IN2 => n_1290);
or1_1011: OR1
PORT MAP ( Y => n_1287, IN1 => n_1288);
and1_1012: AND1
PORT MAP ( Y => n_1288, IN1 => n_1289);
delay_1013: DELAY
PORT MAP ( Y => n_1289, IN1 => data(2));
and1_1014: AND1
PORT MAP ( Y => n_1290, IN1 => gnd);
and1_1015: AND1
PORT MAP ( Y => n_1291, IN1 => n_1292);
delay_1016: DELAY
PORT MAP ( Y => n_1292, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1017: DELAY
PORT MAP ( Y => ix484_a3_dup_635_aCLK, IN1 => n_1291);
and1_1018: AND1
PORT MAP ( Y => ix484_a3_dup_635_aENA, IN1 => n_1295);
delay_1019: DELAY
PORT MAP ( Y => n_1295, IN1 => ix484_nx42_aOUT);
dffe_1020: DFFE
PORT MAP ( D => ix484_a6_dup_632_aD, CLK => ix484_a6_dup_632_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_632_aENA, Q => ix484_a6_dup_632_Q);
xor2_1021: XOR2
PORT MAP ( Y => ix484_a6_dup_632_aD, IN1 => n_1302, IN2 => n_1305);
or1_1022: OR1
PORT MAP ( Y => n_1302, IN1 => n_1303);
and1_1023: AND1
PORT MAP ( Y => n_1303, IN1 => n_1304);
delay_1024: DELAY
PORT MAP ( Y => n_1304, IN1 => data(2));
and1_1025: AND1
PORT MAP ( Y => n_1305, IN1 => gnd);
and1_1026: AND1
PORT MAP ( Y => n_1306, IN1 => n_1307);
delay_1027: DELAY
PORT MAP ( Y => n_1307, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1028: DELAY
PORT MAP ( Y => ix484_a6_dup_632_aCLK, IN1 => n_1306);
and1_1029: AND1
PORT MAP ( Y => ix484_a6_dup_632_aENA, IN1 => n_1310);
delay_1030: DELAY
PORT MAP ( Y => n_1310, IN1 => ix484_nx39_aOUT);
dffe_1031: DFFE
PORT MAP ( D => ix484_a3_dup_627_aD, CLK => ix484_a3_dup_627_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_627_aENA, Q => ix484_a3_dup_627_Q);
xor2_1032: XOR2
PORT MAP ( Y => ix484_a3_dup_627_aD, IN1 => n_1317, IN2 => n_1320);
or1_1033: OR1
PORT MAP ( Y => n_1317, IN1 => n_1318);
and1_1034: AND1
PORT MAP ( Y => n_1318, IN1 => n_1319);
delay_1035: DELAY
PORT MAP ( Y => n_1319, IN1 => data(3));
and1_1036: AND1
PORT MAP ( Y => n_1320, IN1 => gnd);
and1_1037: AND1
PORT MAP ( Y => n_1321, IN1 => n_1322);
delay_1038: DELAY
PORT MAP ( Y => n_1322, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1039: DELAY
PORT MAP ( Y => ix484_a3_dup_627_aCLK, IN1 => n_1321);
and1_1040: AND1
PORT MAP ( Y => ix484_a3_dup_627_aENA, IN1 => n_1325);
delay_1041: DELAY
PORT MAP ( Y => n_1325, IN1 => ix484_nx42_aOUT);
dffe_1042: DFFE
PORT MAP ( D => ix484_a6_dup_624_aD, CLK => ix484_a6_dup_624_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_624_aENA, Q => ix484_a6_dup_624_Q);
xor2_1043: XOR2
PORT MAP ( Y => ix484_a6_dup_624_aD, IN1 => n_1332, IN2 => n_1335);
or1_1044: OR1
PORT MAP ( Y => n_1332, IN1 => n_1333);
and1_1045: AND1
PORT MAP ( Y => n_1333, IN1 => n_1334);
delay_1046: DELAY
PORT MAP ( Y => n_1334, IN1 => data(3));
and1_1047: AND1
PORT MAP ( Y => n_1335, IN1 => gnd);
and1_1048: AND1
PORT MAP ( Y => n_1336, IN1 => n_1337);
delay_1049: DELAY
PORT MAP ( Y => n_1337, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1050: DELAY
PORT MAP ( Y => ix484_a6_dup_624_aCLK, IN1 => n_1336);
and1_1051: AND1
PORT MAP ( Y => ix484_a6_dup_624_aENA, IN1 => n_1340);
delay_1052: DELAY
PORT MAP ( Y => n_1340, IN1 => ix484_nx39_aOUT);
dffe_1053: DFFE
PORT MAP ( D => ix484_a3_dup_619_aD, CLK => ix484_a3_dup_619_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_619_aENA, Q => ix484_a3_dup_619_Q);
xor2_1054: XOR2
PORT MAP ( Y => ix484_a3_dup_619_aD, IN1 => n_1347, IN2 => n_1350);
or1_1055: OR1
PORT MAP ( Y => n_1347, IN1 => n_1348);
and1_1056: AND1
PORT MAP ( Y => n_1348, IN1 => n_1349);
delay_1057: DELAY
PORT MAP ( Y => n_1349, IN1 => data(4));
and1_1058: AND1
PORT MAP ( Y => n_1350, IN1 => gnd);
and1_1059: AND1
PORT MAP ( Y => n_1351, IN1 => n_1352);
delay_1060: DELAY
PORT MAP ( Y => n_1352, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1061: DELAY
PORT MAP ( Y => ix484_a3_dup_619_aCLK, IN1 => n_1351);
and1_1062: AND1
PORT MAP ( Y => ix484_a3_dup_619_aENA, IN1 => n_1355);
delay_1063: DELAY
PORT MAP ( Y => n_1355, IN1 => ix484_nx42_aOUT);
dffe_1064: DFFE
PORT MAP ( D => ix484_a6_dup_616_aD, CLK => ix484_a6_dup_616_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_616_aENA, Q => ix484_a6_dup_616_Q);
xor2_1065: XOR2
PORT MAP ( Y => ix484_a6_dup_616_aD, IN1 => n_1362, IN2 => n_1365);
or1_1066: OR1
PORT MAP ( Y => n_1362, IN1 => n_1363);
and1_1067: AND1
PORT MAP ( Y => n_1363, IN1 => n_1364);
delay_1068: DELAY
PORT MAP ( Y => n_1364, IN1 => data(4));
and1_1069: AND1
PORT MAP ( Y => n_1365, IN1 => gnd);
and1_1070: AND1
PORT MAP ( Y => n_1366, IN1 => n_1367);
delay_1071: DELAY
PORT MAP ( Y => n_1367, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1072: DELAY
PORT MAP ( Y => ix484_a6_dup_616_aCLK, IN1 => n_1366);
and1_1073: AND1
PORT MAP ( Y => ix484_a6_dup_616_aENA, IN1 => n_1370);
delay_1074: DELAY
PORT MAP ( Y => n_1370, IN1 => ix484_nx39_aOUT);
dffe_1075: DFFE
PORT MAP ( D => ix484_a3_dup_611_aD, CLK => ix484_a3_dup_611_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_611_aENA, Q => ix484_a3_dup_611_Q);
xor2_1076: XOR2
PORT MAP ( Y => ix484_a3_dup_611_aD, IN1 => n_1377, IN2 => n_1380);
or1_1077: OR1
PORT MAP ( Y => n_1377, IN1 => n_1378);
and1_1078: AND1
PORT MAP ( Y => n_1378, IN1 => n_1379);
delay_1079: DELAY
PORT MAP ( Y => n_1379, IN1 => data(5));
and1_1080: AND1
PORT MAP ( Y => n_1380, IN1 => gnd);
and1_1081: AND1
PORT MAP ( Y => n_1381, IN1 => n_1382);
delay_1082: DELAY
PORT MAP ( Y => n_1382, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1083: DELAY
PORT MAP ( Y => ix484_a3_dup_611_aCLK, IN1 => n_1381);
and1_1084: AND1
PORT MAP ( Y => ix484_a3_dup_611_aENA, IN1 => n_1385);
delay_1085: DELAY
PORT MAP ( Y => n_1385, IN1 => ix484_nx42_aOUT);
dffe_1086: DFFE
PORT MAP ( D => ix484_a6_dup_608_aD, CLK => ix484_a6_dup_608_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_608_aENA, Q => ix484_a6_dup_608_Q);
xor2_1087: XOR2
PORT MAP ( Y => ix484_a6_dup_608_aD, IN1 => n_1392, IN2 => n_1395);
or1_1088: OR1
PORT MAP ( Y => n_1392, IN1 => n_1393);
and1_1089: AND1
PORT MAP ( Y => n_1393, IN1 => n_1394);
delay_1090: DELAY
PORT MAP ( Y => n_1394, IN1 => data(5));
and1_1091: AND1
PORT MAP ( Y => n_1395, IN1 => gnd);
and1_1092: AND1
PORT MAP ( Y => n_1396, IN1 => n_1397);
delay_1093: DELAY
PORT MAP ( Y => n_1397, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1094: DELAY
PORT MAP ( Y => ix484_a6_dup_608_aCLK, IN1 => n_1396);
and1_1095: AND1
PORT MAP ( Y => ix484_a6_dup_608_aENA, IN1 => n_1400);
delay_1096: DELAY
PORT MAP ( Y => n_1400, IN1 => ix484_nx39_aOUT);
delay_1097: DELAY
PORT MAP ( Y => I0_dup_1317_aOUT, IN1 => I0_dup_1317_aIN);
xor2_1098: XOR2
PORT MAP ( Y => I0_dup_1317_aIN, IN1 => n_1403, IN2 => n_1418);
or4_1099: OR4
PORT MAP ( Y => n_1403, IN1 => n_1404, IN2 => n_1407, IN3 => n_1411, IN4 => n_1415);
and2_1100: AND2
PORT MAP ( Y => n_1404, IN1 => n_1405, IN2 => n_1406);
inv_1101: INV
PORT MAP ( Y => n_1405, IN1 => O_dup_888_aOUT);
inv_1102: INV
PORT MAP ( Y => n_1406, IN1 => O_dup_891_aOUT);
and2_1103: AND2
PORT MAP ( Y => n_1407, IN1 => n_1408, IN2 => n_1410);
inv_1104: INV
PORT MAP ( Y => n_1408, IN1 => ix484_a3_dup_603_Q);
inv_1105: INV
PORT MAP ( Y => n_1410, IN1 => O_dup_891_aOUT);
and2_1106: AND2
PORT MAP ( Y => n_1411, IN1 => n_1412, IN2 => n_1414);
inv_1107: INV
PORT MAP ( Y => n_1412, IN1 => ix484_a6_dup_600_Q);
inv_1108: INV
PORT MAP ( Y => n_1414, IN1 => ix484_a3_dup_603_Q);
and2_1109: AND2
PORT MAP ( Y => n_1415, IN1 => n_1416, IN2 => n_1417);
inv_1110: INV
PORT MAP ( Y => n_1416, IN1 => ix484_a6_dup_600_Q);
inv_1111: INV
PORT MAP ( Y => n_1417, IN1 => O_dup_888_aOUT);
and1_1112: AND1
PORT MAP ( Y => n_1418, IN1 => gnd);
delay_1113: DELAY
PORT MAP ( Y => O_dup_1319_aOUT, IN1 => O_dup_1319_aIN);
and2_1114: AND2
PORT MAP ( Y => O_dup_1319_aIN, IN1 => n_1421, IN2 => n_1436);
or4_1115: OR4
PORT MAP ( Y => n_1421, IN1 => n_1422, IN2 => n_1425, IN3 => n_1429, IN4 => n_1433);
and2_1116: AND2
PORT MAP ( Y => n_1422, IN1 => n_1423, IN2 => n_1424);
inv_1117: INV
PORT MAP ( Y => n_1423, IN1 => O_dup_882_aOUT);
inv_1118: INV
PORT MAP ( Y => n_1424, IN1 => O_dup_885_aOUT);
and2_1119: AND2
PORT MAP ( Y => n_1425, IN1 => n_1426, IN2 => n_1428);
inv_1120: INV
PORT MAP ( Y => n_1426, IN1 => ix484_a1_dup_605_Q);
inv_1121: INV
PORT MAP ( Y => n_1428, IN1 => O_dup_885_aOUT);
and2_1122: AND2
PORT MAP ( Y => n_1429, IN1 => n_1430, IN2 => n_1432);
inv_1123: INV
PORT MAP ( Y => n_1430, IN1 => ix484_a5_dup_601_Q);
inv_1124: INV
PORT MAP ( Y => n_1432, IN1 => ix484_a1_dup_605_Q);
and2_1125: AND2
PORT MAP ( Y => n_1433, IN1 => n_1434, IN2 => n_1435);
inv_1126: INV
PORT MAP ( Y => n_1434, IN1 => ix484_a5_dup_601_Q);
inv_1127: INV
PORT MAP ( Y => n_1435, IN1 => O_dup_882_aOUT);
delay_1128: DELAY
PORT MAP ( Y => n_1436, IN1 => I0_dup_1317_aIN);
delay_1129: DELAY
PORT MAP ( Y => O_dup_1681_aOUT, IN1 => O_dup_1681_aIN);
and2_1130: AND2
PORT MAP ( Y => O_dup_1681_aIN, IN1 => n_1439, IN2 => n_1454);
or4_1131: OR4
PORT MAP ( Y => n_1439, IN1 => n_1440, IN2 => n_1443, IN3 => n_1448, IN4 => n_1451);
and2_1132: AND2
PORT MAP ( Y => n_1440, IN1 => n_1441, IN2 => n_1442);
inv_1133: INV
PORT MAP ( Y => n_1441, IN1 => outregrd_aOUT);
delay_1134: DELAY
PORT MAP ( Y => n_1442, IN1 => n3_aOUT);
and2_1135: AND2
PORT MAP ( Y => n_1443, IN1 => n_1444, IN2 => n_1446);
inv_1136: INV
PORT MAP ( Y => n_1444, IN1 => outreg_val6_Q);
inv_1137: INV
PORT MAP ( Y => n_1446, IN1 => progcntr_val6_Q);
and2_1138: AND2
PORT MAP ( Y => n_1448, IN1 => n_1449, IN2 => n_1450);
inv_1139: INV
PORT MAP ( Y => n_1449, IN1 => progcntr_val6_Q);
inv_1140: INV
PORT MAP ( Y => n_1450, IN1 => outregrd_aOUT);
and2_1141: AND2
PORT MAP ( Y => n_1451, IN1 => n_1452, IN2 => n_1453);
inv_1142: INV
PORT MAP ( Y => n_1452, IN1 => outreg_val6_Q);
delay_1143: DELAY
PORT MAP ( Y => n_1453, IN1 => n3_aOUT);
delay_1144: DELAY
PORT MAP ( Y => n_1454, IN1 => O_dup_1319_aIN);
delay_1145: DELAY
PORT MAP ( Y => I1_dup_804_aOUT, IN1 => I1_dup_804_aIN);
and2_1146: AND2
PORT MAP ( Y => I1_dup_804_aIN, IN1 => n_1457, IN2 => n_1472);
or4_1147: OR4
PORT MAP ( Y => n_1457, IN1 => n_1458, IN2 => n_1461, IN3 => n_1465, IN4 => n_1469);
and2_1148: AND2
PORT MAP ( Y => n_1458, IN1 => n_1459, IN2 => n_1460);
inv_1149: INV
PORT MAP ( Y => n_1459, IN1 => O_dup_876_aOUT);
inv_1150: INV
PORT MAP ( Y => n_1460, IN1 => O_dup_879_aOUT);
and2_1151: AND2
PORT MAP ( Y => n_1461, IN1 => n_1462, IN2 => n_1464);
inv_1152: INV
PORT MAP ( Y => n_1462, IN1 => ix484_a2_dup_604_Q);
inv_1153: INV
PORT MAP ( Y => n_1464, IN1 => O_dup_879_aOUT);
and2_1154: AND2
PORT MAP ( Y => n_1465, IN1 => n_1466, IN2 => n_1468);
inv_1155: INV
PORT MAP ( Y => n_1466, IN1 => ix484_a7_dup_599_Q);
inv_1156: INV
PORT MAP ( Y => n_1468, IN1 => ix484_a2_dup_604_Q);
and2_1157: AND2
PORT MAP ( Y => n_1469, IN1 => n_1470, IN2 => n_1471);
inv_1158: INV
PORT MAP ( Y => n_1470, IN1 => ix484_a7_dup_599_Q);
inv_1159: INV
PORT MAP ( Y => n_1471, IN1 => O_dup_876_aOUT);
delay_1160: DELAY
PORT MAP ( Y => n_1472, IN1 => O_dup_1681_aIN);
delay_1161: DELAY
PORT MAP ( Y => O_dup_805_aOUT, IN1 => O_dup_805_aIN1);
and2_1162: AND2
PORT MAP ( Y => O_dup_805_aIN1, IN1 => n_1474, IN2 => n_1489);
or4_1163: OR4
PORT MAP ( Y => n_1474, IN1 => n_1475, IN2 => n_1478, IN3 => n_1482, IN4 => n_1486);
and2_1164: AND2
PORT MAP ( Y => n_1475, IN1 => n_1476, IN2 => n_1477);
inv_1165: INV
PORT MAP ( Y => n_1476, IN1 => O_dup_870_aOUT);
inv_1166: INV
PORT MAP ( Y => n_1477, IN1 => O_dup_873_aOUT);
and2_1167: AND2
PORT MAP ( Y => n_1478, IN1 => n_1479, IN2 => n_1481);
inv_1168: INV
PORT MAP ( Y => n_1479, IN1 => ix484_a4_dup_602_Q);
inv_1169: INV
PORT MAP ( Y => n_1481, IN1 => O_dup_873_aOUT);
and2_1170: AND2
PORT MAP ( Y => n_1482, IN1 => n_1483, IN2 => n_1485);
inv_1171: INV
PORT MAP ( Y => n_1483, IN1 => ix484_a0_dup_606_Q);
inv_1172: INV
PORT MAP ( Y => n_1485, IN1 => ix484_a4_dup_602_Q);
and2_1173: AND2
PORT MAP ( Y => n_1486, IN1 => n_1487, IN2 => n_1488);
inv_1174: INV
PORT MAP ( Y => n_1487, IN1 => ix484_a0_dup_606_Q);
inv_1175: INV
PORT MAP ( Y => n_1488, IN1 => O_dup_870_aOUT);
delay_1176: DELAY
PORT MAP ( Y => n_1489, IN1 => I1_dup_804_aIN);
dffe_1177: DFFE
PORT MAP ( D => ix484_a3_dup_603_aD, CLK => ix484_a3_dup_603_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_603_aENA, Q => ix484_a3_dup_603_Q);
xor2_1178: XOR2
PORT MAP ( Y => ix484_a3_dup_603_aD, IN1 => n_1496, IN2 => n_1499);
or1_1179: OR1
PORT MAP ( Y => n_1496, IN1 => n_1497);
and1_1180: AND1
PORT MAP ( Y => n_1497, IN1 => n_1498);
delay_1181: DELAY
PORT MAP ( Y => n_1498, IN1 => data(6));
and1_1182: AND1
PORT MAP ( Y => n_1499, IN1 => gnd);
and1_1183: AND1
PORT MAP ( Y => n_1500, IN1 => n_1501);
delay_1184: DELAY
PORT MAP ( Y => n_1501, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1185: DELAY
PORT MAP ( Y => ix484_a3_dup_603_aCLK, IN1 => n_1500);
and1_1186: AND1
PORT MAP ( Y => ix484_a3_dup_603_aENA, IN1 => n_1504);
delay_1187: DELAY
PORT MAP ( Y => n_1504, IN1 => ix484_nx42_aOUT);
dffe_1188: DFFE
PORT MAP ( D => ix484_a6_dup_600_aD, CLK => ix484_a6_dup_600_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_600_aENA, Q => ix484_a6_dup_600_Q);
xor2_1189: XOR2
PORT MAP ( Y => ix484_a6_dup_600_aD, IN1 => n_1511, IN2 => n_1514);
or1_1190: OR1
PORT MAP ( Y => n_1511, IN1 => n_1512);
and1_1191: AND1
PORT MAP ( Y => n_1512, IN1 => n_1513);
delay_1192: DELAY
PORT MAP ( Y => n_1513, IN1 => data(6));
and1_1193: AND1
PORT MAP ( Y => n_1514, IN1 => gnd);
and1_1194: AND1
PORT MAP ( Y => n_1515, IN1 => n_1516);
delay_1195: DELAY
PORT MAP ( Y => n_1516, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1196: DELAY
PORT MAP ( Y => ix484_a6_dup_600_aCLK, IN1 => n_1515);
and1_1197: AND1
PORT MAP ( Y => ix484_a6_dup_600_aENA, IN1 => n_1519);
delay_1198: DELAY
PORT MAP ( Y => n_1519, IN1 => ix484_nx39_aOUT);
delay_1199: DELAY
PORT MAP ( Y => I0_dup_1289_aOUT, IN1 => I0_dup_1289_aIN);
xor2_1200: XOR2
PORT MAP ( Y => I0_dup_1289_aIN, IN1 => n_1522, IN2 => n_1537);
or4_1201: OR4
PORT MAP ( Y => n_1522, IN1 => n_1523, IN2 => n_1526, IN3 => n_1530, IN4 => n_1534);
and2_1202: AND2
PORT MAP ( Y => n_1523, IN1 => n_1524, IN2 => n_1525);
inv_1203: INV
PORT MAP ( Y => n_1524, IN1 => O_dup_888_aOUT);
inv_1204: INV
PORT MAP ( Y => n_1525, IN1 => O_dup_891_aOUT);
and2_1205: AND2
PORT MAP ( Y => n_1526, IN1 => n_1527, IN2 => n_1529);
inv_1206: INV
PORT MAP ( Y => n_1527, IN1 => ix484_a3_dup_595_Q);
inv_1207: INV
PORT MAP ( Y => n_1529, IN1 => O_dup_891_aOUT);
and2_1208: AND2
PORT MAP ( Y => n_1530, IN1 => n_1531, IN2 => n_1533);
inv_1209: INV
PORT MAP ( Y => n_1531, IN1 => ix484_a6_dup_592_Q);
inv_1210: INV
PORT MAP ( Y => n_1533, IN1 => ix484_a3_dup_595_Q);
and2_1211: AND2
PORT MAP ( Y => n_1534, IN1 => n_1535, IN2 => n_1536);
inv_1212: INV
PORT MAP ( Y => n_1535, IN1 => ix484_a6_dup_592_Q);
inv_1213: INV
PORT MAP ( Y => n_1536, IN1 => O_dup_888_aOUT);
and1_1214: AND1
PORT MAP ( Y => n_1537, IN1 => gnd);
delay_1215: DELAY
PORT MAP ( Y => O_dup_1291_aOUT, IN1 => O_dup_1291_aIN);
and2_1216: AND2
PORT MAP ( Y => O_dup_1291_aIN, IN1 => n_1540, IN2 => n_1555);
or4_1217: OR4
PORT MAP ( Y => n_1540, IN1 => n_1541, IN2 => n_1544, IN3 => n_1548, IN4 => n_1552);
and2_1218: AND2
PORT MAP ( Y => n_1541, IN1 => n_1542, IN2 => n_1543);
inv_1219: INV
PORT MAP ( Y => n_1542, IN1 => O_dup_882_aOUT);
inv_1220: INV
PORT MAP ( Y => n_1543, IN1 => O_dup_885_aOUT);
and2_1221: AND2
PORT MAP ( Y => n_1544, IN1 => n_1545, IN2 => n_1547);
inv_1222: INV
PORT MAP ( Y => n_1545, IN1 => ix484_a1_dup_597_Q);
inv_1223: INV
PORT MAP ( Y => n_1547, IN1 => O_dup_885_aOUT);
and2_1224: AND2
PORT MAP ( Y => n_1548, IN1 => n_1549, IN2 => n_1551);
inv_1225: INV
PORT MAP ( Y => n_1549, IN1 => ix484_a5_dup_593_Q);
inv_1226: INV
PORT MAP ( Y => n_1551, IN1 => ix484_a1_dup_597_Q);
and2_1227: AND2
PORT MAP ( Y => n_1552, IN1 => n_1553, IN2 => n_1554);
inv_1228: INV
PORT MAP ( Y => n_1553, IN1 => ix484_a5_dup_593_Q);
inv_1229: INV
PORT MAP ( Y => n_1554, IN1 => O_dup_882_aOUT);
delay_1230: DELAY
PORT MAP ( Y => n_1555, IN1 => I0_dup_1289_aIN);
delay_1231: DELAY
PORT MAP ( Y => O_dup_1673_aOUT, IN1 => O_dup_1673_aIN);
and2_1232: AND2
PORT MAP ( Y => O_dup_1673_aIN, IN1 => n_1558, IN2 => n_1573);
or4_1233: OR4
PORT MAP ( Y => n_1558, IN1 => n_1559, IN2 => n_1562, IN3 => n_1567, IN4 => n_1570);
and2_1234: AND2
PORT MAP ( Y => n_1559, IN1 => n_1560, IN2 => n_1561);
inv_1235: INV
PORT MAP ( Y => n_1560, IN1 => outregrd_aOUT);
delay_1236: DELAY
PORT MAP ( Y => n_1561, IN1 => n3_aOUT);
and2_1237: AND2
PORT MAP ( Y => n_1562, IN1 => n_1563, IN2 => n_1565);
inv_1238: INV
PORT MAP ( Y => n_1563, IN1 => outreg_val7_Q);
inv_1239: INV
PORT MAP ( Y => n_1565, IN1 => progcntr_val7_Q);
and2_1240: AND2
PORT MAP ( Y => n_1567, IN1 => n_1568, IN2 => n_1569);
inv_1241: INV
PORT MAP ( Y => n_1568, IN1 => progcntr_val7_Q);
inv_1242: INV
PORT MAP ( Y => n_1569, IN1 => outregrd_aOUT);
and2_1243: AND2
PORT MAP ( Y => n_1570, IN1 => n_1571, IN2 => n_1572);
inv_1244: INV
PORT MAP ( Y => n_1571, IN1 => outreg_val7_Q);
delay_1245: DELAY
PORT MAP ( Y => n_1572, IN1 => n3_aOUT);
delay_1246: DELAY
PORT MAP ( Y => n_1573, IN1 => O_dup_1291_aIN);
delay_1247: DELAY
PORT MAP ( Y => I1_dup_801_aOUT, IN1 => I1_dup_801_aIN);
and2_1248: AND2
PORT MAP ( Y => I1_dup_801_aIN, IN1 => n_1576, IN2 => n_1591);
or4_1249: OR4
PORT MAP ( Y => n_1576, IN1 => n_1577, IN2 => n_1580, IN3 => n_1584, IN4 => n_1588);
and2_1250: AND2
PORT MAP ( Y => n_1577, IN1 => n_1578, IN2 => n_1579);
inv_1251: INV
PORT MAP ( Y => n_1578, IN1 => O_dup_876_aOUT);
inv_1252: INV
PORT MAP ( Y => n_1579, IN1 => O_dup_879_aOUT);
and2_1253: AND2
PORT MAP ( Y => n_1580, IN1 => n_1581, IN2 => n_1583);
inv_1254: INV
PORT MAP ( Y => n_1581, IN1 => ix484_a2_dup_596_Q);
inv_1255: INV
PORT MAP ( Y => n_1583, IN1 => O_dup_879_aOUT);
and2_1256: AND2
PORT MAP ( Y => n_1584, IN1 => n_1585, IN2 => n_1587);
inv_1257: INV
PORT MAP ( Y => n_1585, IN1 => ix484_a7_dup_591_Q);
inv_1258: INV
PORT MAP ( Y => n_1587, IN1 => ix484_a2_dup_596_Q);
and2_1259: AND2
PORT MAP ( Y => n_1588, IN1 => n_1589, IN2 => n_1590);
inv_1260: INV
PORT MAP ( Y => n_1589, IN1 => ix484_a7_dup_591_Q);
inv_1261: INV
PORT MAP ( Y => n_1590, IN1 => O_dup_876_aOUT);
delay_1262: DELAY
PORT MAP ( Y => n_1591, IN1 => O_dup_1673_aIN);
delay_1263: DELAY
PORT MAP ( Y => O_dup_802_aOUT, IN1 => O_dup_802_aIN1);
and2_1264: AND2
PORT MAP ( Y => O_dup_802_aIN1, IN1 => n_1593, IN2 => n_1608);
or4_1265: OR4
PORT MAP ( Y => n_1593, IN1 => n_1594, IN2 => n_1597, IN3 => n_1601, IN4 => n_1605);
and2_1266: AND2
PORT MAP ( Y => n_1594, IN1 => n_1595, IN2 => n_1596);
inv_1267: INV
PORT MAP ( Y => n_1595, IN1 => O_dup_870_aOUT);
inv_1268: INV
PORT MAP ( Y => n_1596, IN1 => O_dup_873_aOUT);
and2_1269: AND2
PORT MAP ( Y => n_1597, IN1 => n_1598, IN2 => n_1600);
inv_1270: INV
PORT MAP ( Y => n_1598, IN1 => ix484_a4_dup_594_Q);
inv_1271: INV
PORT MAP ( Y => n_1600, IN1 => O_dup_873_aOUT);
and2_1272: AND2
PORT MAP ( Y => n_1601, IN1 => n_1602, IN2 => n_1604);
inv_1273: INV
PORT MAP ( Y => n_1602, IN1 => ix484_a0_dup_598_Q);
inv_1274: INV
PORT MAP ( Y => n_1604, IN1 => ix484_a4_dup_594_Q);
and2_1275: AND2
PORT MAP ( Y => n_1605, IN1 => n_1606, IN2 => n_1607);
inv_1276: INV
PORT MAP ( Y => n_1606, IN1 => ix484_a0_dup_598_Q);
inv_1277: INV
PORT MAP ( Y => n_1607, IN1 => O_dup_870_aOUT);
delay_1278: DELAY
PORT MAP ( Y => n_1608, IN1 => I1_dup_801_aIN);
dffe_1279: DFFE
PORT MAP ( D => ix484_a3_dup_595_aD, CLK => ix484_a3_dup_595_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_595_aENA, Q => ix484_a3_dup_595_Q);
xor2_1280: XOR2
PORT MAP ( Y => ix484_a3_dup_595_aD, IN1 => n_1615, IN2 => n_1618);
or1_1281: OR1
PORT MAP ( Y => n_1615, IN1 => n_1616);
and1_1282: AND1
PORT MAP ( Y => n_1616, IN1 => n_1617);
delay_1283: DELAY
PORT MAP ( Y => n_1617, IN1 => data(7));
and1_1284: AND1
PORT MAP ( Y => n_1618, IN1 => gnd);
and1_1285: AND1
PORT MAP ( Y => n_1619, IN1 => n_1620);
delay_1286: DELAY
PORT MAP ( Y => n_1620, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1287: DELAY
PORT MAP ( Y => ix484_a3_dup_595_aCLK, IN1 => n_1619);
and1_1288: AND1
PORT MAP ( Y => ix484_a3_dup_595_aENA, IN1 => n_1623);
delay_1289: DELAY
PORT MAP ( Y => n_1623, IN1 => ix484_nx42_aOUT);
dffe_1290: DFFE
PORT MAP ( D => ix484_a6_dup_592_aD, CLK => ix484_a6_dup_592_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_592_aENA, Q => ix484_a6_dup_592_Q);
xor2_1291: XOR2
PORT MAP ( Y => ix484_a6_dup_592_aD, IN1 => n_1630, IN2 => n_1633);
or1_1292: OR1
PORT MAP ( Y => n_1630, IN1 => n_1631);
and1_1293: AND1
PORT MAP ( Y => n_1631, IN1 => n_1632);
delay_1294: DELAY
PORT MAP ( Y => n_1632, IN1 => data(7));
and1_1295: AND1
PORT MAP ( Y => n_1633, IN1 => gnd);
and1_1296: AND1
PORT MAP ( Y => n_1634, IN1 => n_1635);
delay_1297: DELAY
PORT MAP ( Y => n_1635, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1298: DELAY
PORT MAP ( Y => ix484_a6_dup_592_aCLK, IN1 => n_1634);
and1_1299: AND1
PORT MAP ( Y => ix484_a6_dup_592_aENA, IN1 => n_1638);
delay_1300: DELAY
PORT MAP ( Y => n_1638, IN1 => ix484_nx39_aOUT);
delay_1301: DELAY
PORT MAP ( Y => I0_dup_1261_aOUT, IN1 => I0_dup_1261_aIN);
xor2_1302: XOR2
PORT MAP ( Y => I0_dup_1261_aIN, IN1 => n_1641, IN2 => n_1656);
or4_1303: OR4
PORT MAP ( Y => n_1641, IN1 => n_1642, IN2 => n_1645, IN3 => n_1649, IN4 => n_1653);
and2_1304: AND2
PORT MAP ( Y => n_1642, IN1 => n_1643, IN2 => n_1644);
inv_1305: INV
PORT MAP ( Y => n_1643, IN1 => O_dup_888_aOUT);
inv_1306: INV
PORT MAP ( Y => n_1644, IN1 => O_dup_891_aOUT);
and2_1307: AND2
PORT MAP ( Y => n_1645, IN1 => n_1646, IN2 => n_1648);
inv_1308: INV
PORT MAP ( Y => n_1646, IN1 => ix484_a3_dup_587_Q);
inv_1309: INV
PORT MAP ( Y => n_1648, IN1 => O_dup_891_aOUT);
and2_1310: AND2
PORT MAP ( Y => n_1649, IN1 => n_1650, IN2 => n_1652);
inv_1311: INV
PORT MAP ( Y => n_1650, IN1 => ix484_a6_dup_584_Q);
inv_1312: INV
PORT MAP ( Y => n_1652, IN1 => ix484_a3_dup_587_Q);
and2_1313: AND2
PORT MAP ( Y => n_1653, IN1 => n_1654, IN2 => n_1655);
inv_1314: INV
PORT MAP ( Y => n_1654, IN1 => ix484_a6_dup_584_Q);
inv_1315: INV
PORT MAP ( Y => n_1655, IN1 => O_dup_888_aOUT);
and1_1316: AND1
PORT MAP ( Y => n_1656, IN1 => gnd);
delay_1317: DELAY
PORT MAP ( Y => O_dup_1263_aOUT, IN1 => O_dup_1263_aIN);
and2_1318: AND2
PORT MAP ( Y => O_dup_1263_aIN, IN1 => n_1659, IN2 => n_1674);
or4_1319: OR4
PORT MAP ( Y => n_1659, IN1 => n_1660, IN2 => n_1663, IN3 => n_1667, IN4 => n_1671);
and2_1320: AND2
PORT MAP ( Y => n_1660, IN1 => n_1661, IN2 => n_1662);
inv_1321: INV
PORT MAP ( Y => n_1661, IN1 => O_dup_882_aOUT);
inv_1322: INV
PORT MAP ( Y => n_1662, IN1 => O_dup_885_aOUT);
and2_1323: AND2
PORT MAP ( Y => n_1663, IN1 => n_1664, IN2 => n_1666);
inv_1324: INV
PORT MAP ( Y => n_1664, IN1 => ix484_a1_dup_589_Q);
inv_1325: INV
PORT MAP ( Y => n_1666, IN1 => O_dup_885_aOUT);
and2_1326: AND2
PORT MAP ( Y => n_1667, IN1 => n_1668, IN2 => n_1670);
inv_1327: INV
PORT MAP ( Y => n_1668, IN1 => ix484_a5_dup_585_Q);
inv_1328: INV
PORT MAP ( Y => n_1670, IN1 => ix484_a1_dup_589_Q);
and2_1329: AND2
PORT MAP ( Y => n_1671, IN1 => n_1672, IN2 => n_1673);
inv_1330: INV
PORT MAP ( Y => n_1672, IN1 => ix484_a5_dup_585_Q);
inv_1331: INV
PORT MAP ( Y => n_1673, IN1 => O_dup_882_aOUT);
delay_1332: DELAY
PORT MAP ( Y => n_1674, IN1 => I0_dup_1261_aIN);
delay_1333: DELAY
PORT MAP ( Y => O_dup_1665_aOUT, IN1 => O_dup_1665_aIN);
and2_1334: AND2
PORT MAP ( Y => O_dup_1665_aIN, IN1 => n_1677, IN2 => n_1692);
or4_1335: OR4
PORT MAP ( Y => n_1677, IN1 => n_1678, IN2 => n_1681, IN3 => n_1686, IN4 => n_1689);
and2_1336: AND2
PORT MAP ( Y => n_1678, IN1 => n_1679, IN2 => n_1680);
inv_1337: INV
PORT MAP ( Y => n_1679, IN1 => outregrd_aOUT);
delay_1338: DELAY
PORT MAP ( Y => n_1680, IN1 => n3_aOUT);
and2_1339: AND2
PORT MAP ( Y => n_1681, IN1 => n_1682, IN2 => n_1684);
inv_1340: INV
PORT MAP ( Y => n_1682, IN1 => outreg_val8_Q);
inv_1341: INV
PORT MAP ( Y => n_1684, IN1 => progcntr_val8_Q);
and2_1342: AND2
PORT MAP ( Y => n_1686, IN1 => n_1687, IN2 => n_1688);
inv_1343: INV
PORT MAP ( Y => n_1687, IN1 => progcntr_val8_Q);
inv_1344: INV
PORT MAP ( Y => n_1688, IN1 => outregrd_aOUT);
and2_1345: AND2
PORT MAP ( Y => n_1689, IN1 => n_1690, IN2 => n_1691);
inv_1346: INV
PORT MAP ( Y => n_1690, IN1 => outreg_val8_Q);
delay_1347: DELAY
PORT MAP ( Y => n_1691, IN1 => n3_aOUT);
delay_1348: DELAY
PORT MAP ( Y => n_1692, IN1 => O_dup_1263_aIN);
delay_1349: DELAY
PORT MAP ( Y => I1_dup_798_aOUT, IN1 => I1_dup_798_aIN);
and2_1350: AND2
PORT MAP ( Y => I1_dup_798_aIN, IN1 => n_1695, IN2 => n_1710);
or4_1351: OR4
PORT MAP ( Y => n_1695, IN1 => n_1696, IN2 => n_1699, IN3 => n_1703, IN4 => n_1707);
and2_1352: AND2
PORT MAP ( Y => n_1696, IN1 => n_1697, IN2 => n_1698);
inv_1353: INV
PORT MAP ( Y => n_1697, IN1 => O_dup_876_aOUT);
inv_1354: INV
PORT MAP ( Y => n_1698, IN1 => O_dup_879_aOUT);
and2_1355: AND2
PORT MAP ( Y => n_1699, IN1 => n_1700, IN2 => n_1702);
inv_1356: INV
PORT MAP ( Y => n_1700, IN1 => ix484_a2_dup_588_Q);
inv_1357: INV
PORT MAP ( Y => n_1702, IN1 => O_dup_879_aOUT);
and2_1358: AND2
PORT MAP ( Y => n_1703, IN1 => n_1704, IN2 => n_1706);
inv_1359: INV
PORT MAP ( Y => n_1704, IN1 => ix484_a7_dup_583_Q);
inv_1360: INV
PORT MAP ( Y => n_1706, IN1 => ix484_a2_dup_588_Q);
and2_1361: AND2
PORT MAP ( Y => n_1707, IN1 => n_1708, IN2 => n_1709);
inv_1362: INV
PORT MAP ( Y => n_1708, IN1 => ix484_a7_dup_583_Q);
inv_1363: INV
PORT MAP ( Y => n_1709, IN1 => O_dup_876_aOUT);
delay_1364: DELAY
PORT MAP ( Y => n_1710, IN1 => O_dup_1665_aIN);
delay_1365: DELAY
PORT MAP ( Y => O_dup_799_aOUT, IN1 => O_dup_799_aIN1);
and2_1366: AND2
PORT MAP ( Y => O_dup_799_aIN1, IN1 => n_1712, IN2 => n_1727);
or4_1367: OR4
PORT MAP ( Y => n_1712, IN1 => n_1713, IN2 => n_1716, IN3 => n_1720, IN4 => n_1724);
and2_1368: AND2
PORT MAP ( Y => n_1713, IN1 => n_1714, IN2 => n_1715);
inv_1369: INV
PORT MAP ( Y => n_1714, IN1 => O_dup_870_aOUT);
inv_1370: INV
PORT MAP ( Y => n_1715, IN1 => O_dup_873_aOUT);
and2_1371: AND2
PORT MAP ( Y => n_1716, IN1 => n_1717, IN2 => n_1719);
inv_1372: INV
PORT MAP ( Y => n_1717, IN1 => ix484_a4_dup_586_Q);
inv_1373: INV
PORT MAP ( Y => n_1719, IN1 => O_dup_873_aOUT);
and2_1374: AND2
PORT MAP ( Y => n_1720, IN1 => n_1721, IN2 => n_1723);
inv_1375: INV
PORT MAP ( Y => n_1721, IN1 => ix484_a0_dup_590_Q);
inv_1376: INV
PORT MAP ( Y => n_1723, IN1 => ix484_a4_dup_586_Q);
and2_1377: AND2
PORT MAP ( Y => n_1724, IN1 => n_1725, IN2 => n_1726);
inv_1378: INV
PORT MAP ( Y => n_1725, IN1 => ix484_a0_dup_590_Q);
inv_1379: INV
PORT MAP ( Y => n_1726, IN1 => O_dup_870_aOUT);
delay_1380: DELAY
PORT MAP ( Y => n_1727, IN1 => I1_dup_798_aIN);
dffe_1381: DFFE
PORT MAP ( D => ix484_a3_dup_587_aD, CLK => ix484_a3_dup_587_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_587_aENA, Q => ix484_a3_dup_587_Q);
xor2_1382: XOR2
PORT MAP ( Y => ix484_a3_dup_587_aD, IN1 => n_1734, IN2 => n_1737);
or1_1383: OR1
PORT MAP ( Y => n_1734, IN1 => n_1735);
and1_1384: AND1
PORT MAP ( Y => n_1735, IN1 => n_1736);
delay_1385: DELAY
PORT MAP ( Y => n_1736, IN1 => data(8));
and1_1386: AND1
PORT MAP ( Y => n_1737, IN1 => gnd);
and1_1387: AND1
PORT MAP ( Y => n_1738, IN1 => n_1739);
delay_1388: DELAY
PORT MAP ( Y => n_1739, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1389: DELAY
PORT MAP ( Y => ix484_a3_dup_587_aCLK, IN1 => n_1738);
and1_1390: AND1
PORT MAP ( Y => ix484_a3_dup_587_aENA, IN1 => n_1742);
delay_1391: DELAY
PORT MAP ( Y => n_1742, IN1 => ix484_nx42_aOUT);
dffe_1392: DFFE
PORT MAP ( D => ix484_a6_dup_584_aD, CLK => ix484_a6_dup_584_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_584_aENA, Q => ix484_a6_dup_584_Q);
xor2_1393: XOR2
PORT MAP ( Y => ix484_a6_dup_584_aD, IN1 => n_1749, IN2 => n_1752);
or1_1394: OR1
PORT MAP ( Y => n_1749, IN1 => n_1750);
and1_1395: AND1
PORT MAP ( Y => n_1750, IN1 => n_1751);
delay_1396: DELAY
PORT MAP ( Y => n_1751, IN1 => data(8));
and1_1397: AND1
PORT MAP ( Y => n_1752, IN1 => gnd);
and1_1398: AND1
PORT MAP ( Y => n_1753, IN1 => n_1754);
delay_1399: DELAY
PORT MAP ( Y => n_1754, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1400: DELAY
PORT MAP ( Y => ix484_a6_dup_584_aCLK, IN1 => n_1753);
and1_1401: AND1
PORT MAP ( Y => ix484_a6_dup_584_aENA, IN1 => n_1757);
delay_1402: DELAY
PORT MAP ( Y => n_1757, IN1 => ix484_nx39_aOUT);
delay_1403: DELAY
PORT MAP ( Y => I0_dup_1233_aOUT, IN1 => I0_dup_1233_aIN);
xor2_1404: XOR2
PORT MAP ( Y => I0_dup_1233_aIN, IN1 => n_1760, IN2 => n_1775);
or4_1405: OR4
PORT MAP ( Y => n_1760, IN1 => n_1761, IN2 => n_1764, IN3 => n_1768, IN4 => n_1772);
and2_1406: AND2
PORT MAP ( Y => n_1761, IN1 => n_1762, IN2 => n_1763);
inv_1407: INV
PORT MAP ( Y => n_1762, IN1 => O_dup_888_aOUT);
inv_1408: INV
PORT MAP ( Y => n_1763, IN1 => O_dup_891_aOUT);
and2_1409: AND2
PORT MAP ( Y => n_1764, IN1 => n_1765, IN2 => n_1767);
inv_1410: INV
PORT MAP ( Y => n_1765, IN1 => ix484_a3_dup_579_Q);
inv_1411: INV
PORT MAP ( Y => n_1767, IN1 => O_dup_891_aOUT);
and2_1412: AND2
PORT MAP ( Y => n_1768, IN1 => n_1769, IN2 => n_1771);
inv_1413: INV
PORT MAP ( Y => n_1769, IN1 => ix484_a6_dup_576_Q);
inv_1414: INV
PORT MAP ( Y => n_1771, IN1 => ix484_a3_dup_579_Q);
and2_1415: AND2
PORT MAP ( Y => n_1772, IN1 => n_1773, IN2 => n_1774);
inv_1416: INV
PORT MAP ( Y => n_1773, IN1 => ix484_a6_dup_576_Q);
inv_1417: INV
PORT MAP ( Y => n_1774, IN1 => O_dup_888_aOUT);
and1_1418: AND1
PORT MAP ( Y => n_1775, IN1 => gnd);
delay_1419: DELAY
PORT MAP ( Y => O_dup_1235_aOUT, IN1 => O_dup_1235_aIN);
and2_1420: AND2
PORT MAP ( Y => O_dup_1235_aIN, IN1 => n_1778, IN2 => n_1793);
or4_1421: OR4
PORT MAP ( Y => n_1778, IN1 => n_1779, IN2 => n_1782, IN3 => n_1786, IN4 => n_1790);
and2_1422: AND2
PORT MAP ( Y => n_1779, IN1 => n_1780, IN2 => n_1781);
inv_1423: INV
PORT MAP ( Y => n_1780, IN1 => O_dup_882_aOUT);
inv_1424: INV
PORT MAP ( Y => n_1781, IN1 => O_dup_885_aOUT);
and2_1425: AND2
PORT MAP ( Y => n_1782, IN1 => n_1783, IN2 => n_1785);
inv_1426: INV
PORT MAP ( Y => n_1783, IN1 => ix484_a1_dup_581_Q);
inv_1427: INV
PORT MAP ( Y => n_1785, IN1 => O_dup_885_aOUT);
and2_1428: AND2
PORT MAP ( Y => n_1786, IN1 => n_1787, IN2 => n_1789);
inv_1429: INV
PORT MAP ( Y => n_1787, IN1 => ix484_a5_dup_577_Q);
inv_1430: INV
PORT MAP ( Y => n_1789, IN1 => ix484_a1_dup_581_Q);
and2_1431: AND2
PORT MAP ( Y => n_1790, IN1 => n_1791, IN2 => n_1792);
inv_1432: INV
PORT MAP ( Y => n_1791, IN1 => ix484_a5_dup_577_Q);
inv_1433: INV
PORT MAP ( Y => n_1792, IN1 => O_dup_882_aOUT);
delay_1434: DELAY
PORT MAP ( Y => n_1793, IN1 => I0_dup_1233_aIN);
delay_1435: DELAY
PORT MAP ( Y => O_dup_1657_aOUT, IN1 => O_dup_1657_aIN);
and2_1436: AND2
PORT MAP ( Y => O_dup_1657_aIN, IN1 => n_1796, IN2 => n_1811);
or4_1437: OR4
PORT MAP ( Y => n_1796, IN1 => n_1797, IN2 => n_1800, IN3 => n_1805, IN4 => n_1808);
and2_1438: AND2
PORT MAP ( Y => n_1797, IN1 => n_1798, IN2 => n_1799);
inv_1439: INV
PORT MAP ( Y => n_1798, IN1 => outregrd_aOUT);
delay_1440: DELAY
PORT MAP ( Y => n_1799, IN1 => n3_aOUT);
and2_1441: AND2
PORT MAP ( Y => n_1800, IN1 => n_1801, IN2 => n_1803);
inv_1442: INV
PORT MAP ( Y => n_1801, IN1 => outreg_val9_Q);
inv_1443: INV
PORT MAP ( Y => n_1803, IN1 => progcntr_val9_Q);
and2_1444: AND2
PORT MAP ( Y => n_1805, IN1 => n_1806, IN2 => n_1807);
inv_1445: INV
PORT MAP ( Y => n_1806, IN1 => progcntr_val9_Q);
inv_1446: INV
PORT MAP ( Y => n_1807, IN1 => outregrd_aOUT);
and2_1447: AND2
PORT MAP ( Y => n_1808, IN1 => n_1809, IN2 => n_1810);
inv_1448: INV
PORT MAP ( Y => n_1809, IN1 => outreg_val9_Q);
delay_1449: DELAY
PORT MAP ( Y => n_1810, IN1 => n3_aOUT);
delay_1450: DELAY
PORT MAP ( Y => n_1811, IN1 => O_dup_1235_aIN);
delay_1451: DELAY
PORT MAP ( Y => I1_dup_795_aOUT, IN1 => I1_dup_795_aIN);
and2_1452: AND2
PORT MAP ( Y => I1_dup_795_aIN, IN1 => n_1814, IN2 => n_1829);
or4_1453: OR4
PORT MAP ( Y => n_1814, IN1 => n_1815, IN2 => n_1818, IN3 => n_1822, IN4 => n_1826);
and2_1454: AND2
PORT MAP ( Y => n_1815, IN1 => n_1816, IN2 => n_1817);
inv_1455: INV
PORT MAP ( Y => n_1816, IN1 => O_dup_876_aOUT);
inv_1456: INV
PORT MAP ( Y => n_1817, IN1 => O_dup_879_aOUT);
and2_1457: AND2
PORT MAP ( Y => n_1818, IN1 => n_1819, IN2 => n_1821);
inv_1458: INV
PORT MAP ( Y => n_1819, IN1 => ix484_a2_dup_580_Q);
inv_1459: INV
PORT MAP ( Y => n_1821, IN1 => O_dup_879_aOUT);
and2_1460: AND2
PORT MAP ( Y => n_1822, IN1 => n_1823, IN2 => n_1825);
inv_1461: INV
PORT MAP ( Y => n_1823, IN1 => ix484_a7_dup_575_Q);
inv_1462: INV
PORT MAP ( Y => n_1825, IN1 => ix484_a2_dup_580_Q);
and2_1463: AND2
PORT MAP ( Y => n_1826, IN1 => n_1827, IN2 => n_1828);
inv_1464: INV
PORT MAP ( Y => n_1827, IN1 => ix484_a7_dup_575_Q);
inv_1465: INV
PORT MAP ( Y => n_1828, IN1 => O_dup_876_aOUT);
delay_1466: DELAY
PORT MAP ( Y => n_1829, IN1 => O_dup_1657_aIN);
delay_1467: DELAY
PORT MAP ( Y => O_dup_796_aOUT, IN1 => O_dup_796_aIN1);
and2_1468: AND2
PORT MAP ( Y => O_dup_796_aIN1, IN1 => n_1831, IN2 => n_1846);
or4_1469: OR4
PORT MAP ( Y => n_1831, IN1 => n_1832, IN2 => n_1835, IN3 => n_1839, IN4 => n_1843);
and2_1470: AND2
PORT MAP ( Y => n_1832, IN1 => n_1833, IN2 => n_1834);
inv_1471: INV
PORT MAP ( Y => n_1833, IN1 => O_dup_870_aOUT);
inv_1472: INV
PORT MAP ( Y => n_1834, IN1 => O_dup_873_aOUT);
and2_1473: AND2
PORT MAP ( Y => n_1835, IN1 => n_1836, IN2 => n_1838);
inv_1474: INV
PORT MAP ( Y => n_1836, IN1 => ix484_a4_dup_578_Q);
inv_1475: INV
PORT MAP ( Y => n_1838, IN1 => O_dup_873_aOUT);
and2_1476: AND2
PORT MAP ( Y => n_1839, IN1 => n_1840, IN2 => n_1842);
inv_1477: INV
PORT MAP ( Y => n_1840, IN1 => ix484_a0_dup_582_Q);
inv_1478: INV
PORT MAP ( Y => n_1842, IN1 => ix484_a4_dup_578_Q);
and2_1479: AND2
PORT MAP ( Y => n_1843, IN1 => n_1844, IN2 => n_1845);
inv_1480: INV
PORT MAP ( Y => n_1844, IN1 => ix484_a0_dup_582_Q);
inv_1481: INV
PORT MAP ( Y => n_1845, IN1 => O_dup_870_aOUT);
delay_1482: DELAY
PORT MAP ( Y => n_1846, IN1 => I1_dup_795_aIN);
dffe_1483: DFFE
PORT MAP ( D => ix484_a3_dup_579_aD, CLK => ix484_a3_dup_579_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_579_aENA, Q => ix484_a3_dup_579_Q);
xor2_1484: XOR2
PORT MAP ( Y => ix484_a3_dup_579_aD, IN1 => n_1853, IN2 => n_1856);
or1_1485: OR1
PORT MAP ( Y => n_1853, IN1 => n_1854);
and1_1486: AND1
PORT MAP ( Y => n_1854, IN1 => n_1855);
delay_1487: DELAY
PORT MAP ( Y => n_1855, IN1 => data(9));
and1_1488: AND1
PORT MAP ( Y => n_1856, IN1 => gnd);
and1_1489: AND1
PORT MAP ( Y => n_1857, IN1 => n_1858);
delay_1490: DELAY
PORT MAP ( Y => n_1858, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1491: DELAY
PORT MAP ( Y => ix484_a3_dup_579_aCLK, IN1 => n_1857);
and1_1492: AND1
PORT MAP ( Y => ix484_a3_dup_579_aENA, IN1 => n_1861);
delay_1493: DELAY
PORT MAP ( Y => n_1861, IN1 => ix484_nx42_aOUT);
dffe_1494: DFFE
PORT MAP ( D => ix484_a6_dup_576_aD, CLK => ix484_a6_dup_576_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_576_aENA, Q => ix484_a6_dup_576_Q);
xor2_1495: XOR2
PORT MAP ( Y => ix484_a6_dup_576_aD, IN1 => n_1868, IN2 => n_1871);
or1_1496: OR1
PORT MAP ( Y => n_1868, IN1 => n_1869);
and1_1497: AND1
PORT MAP ( Y => n_1869, IN1 => n_1870);
delay_1498: DELAY
PORT MAP ( Y => n_1870, IN1 => data(9));
and1_1499: AND1
PORT MAP ( Y => n_1871, IN1 => gnd);
and1_1500: AND1
PORT MAP ( Y => n_1872, IN1 => n_1873);
delay_1501: DELAY
PORT MAP ( Y => n_1873, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1502: DELAY
PORT MAP ( Y => ix484_a6_dup_576_aCLK, IN1 => n_1872);
and1_1503: AND1
PORT MAP ( Y => ix484_a6_dup_576_aENA, IN1 => n_1876);
delay_1504: DELAY
PORT MAP ( Y => n_1876, IN1 => ix484_nx39_aOUT);
delay_1505: DELAY
PORT MAP ( Y => I0_dup_1205_aOUT, IN1 => I0_dup_1205_aIN);
xor2_1506: XOR2
PORT MAP ( Y => I0_dup_1205_aIN, IN1 => n_1879, IN2 => n_1894);
or4_1507: OR4
PORT MAP ( Y => n_1879, IN1 => n_1880, IN2 => n_1883, IN3 => n_1887, IN4 => n_1891);
and2_1508: AND2
PORT MAP ( Y => n_1880, IN1 => n_1881, IN2 => n_1882);
inv_1509: INV
PORT MAP ( Y => n_1881, IN1 => O_dup_888_aOUT);
inv_1510: INV
PORT MAP ( Y => n_1882, IN1 => O_dup_891_aOUT);
and2_1511: AND2
PORT MAP ( Y => n_1883, IN1 => n_1884, IN2 => n_1886);
inv_1512: INV
PORT MAP ( Y => n_1884, IN1 => ix484_a3_dup_571_Q);
inv_1513: INV
PORT MAP ( Y => n_1886, IN1 => O_dup_891_aOUT);
and2_1514: AND2
PORT MAP ( Y => n_1887, IN1 => n_1888, IN2 => n_1890);
inv_1515: INV
PORT MAP ( Y => n_1888, IN1 => ix484_a6_dup_568_Q);
inv_1516: INV
PORT MAP ( Y => n_1890, IN1 => ix484_a3_dup_571_Q);
and2_1517: AND2
PORT MAP ( Y => n_1891, IN1 => n_1892, IN2 => n_1893);
inv_1518: INV
PORT MAP ( Y => n_1892, IN1 => ix484_a6_dup_568_Q);
inv_1519: INV
PORT MAP ( Y => n_1893, IN1 => O_dup_888_aOUT);
and1_1520: AND1
PORT MAP ( Y => n_1894, IN1 => gnd);
delay_1521: DELAY
PORT MAP ( Y => O_dup_1207_aOUT, IN1 => O_dup_1207_aIN);
and2_1522: AND2
PORT MAP ( Y => O_dup_1207_aIN, IN1 => n_1897, IN2 => n_1912);
or4_1523: OR4
PORT MAP ( Y => n_1897, IN1 => n_1898, IN2 => n_1901, IN3 => n_1905, IN4 => n_1909);
and2_1524: AND2
PORT MAP ( Y => n_1898, IN1 => n_1899, IN2 => n_1900);
inv_1525: INV
PORT MAP ( Y => n_1899, IN1 => O_dup_882_aOUT);
inv_1526: INV
PORT MAP ( Y => n_1900, IN1 => O_dup_885_aOUT);
and2_1527: AND2
PORT MAP ( Y => n_1901, IN1 => n_1902, IN2 => n_1904);
inv_1528: INV
PORT MAP ( Y => n_1902, IN1 => ix484_a1_dup_573_Q);
inv_1529: INV
PORT MAP ( Y => n_1904, IN1 => O_dup_885_aOUT);
and2_1530: AND2
PORT MAP ( Y => n_1905, IN1 => n_1906, IN2 => n_1908);
inv_1531: INV
PORT MAP ( Y => n_1906, IN1 => ix484_a5_dup_569_Q);
inv_1532: INV
PORT MAP ( Y => n_1908, IN1 => ix484_a1_dup_573_Q);
and2_1533: AND2
PORT MAP ( Y => n_1909, IN1 => n_1910, IN2 => n_1911);
inv_1534: INV
PORT MAP ( Y => n_1910, IN1 => ix484_a5_dup_569_Q);
inv_1535: INV
PORT MAP ( Y => n_1911, IN1 => O_dup_882_aOUT);
delay_1536: DELAY
PORT MAP ( Y => n_1912, IN1 => I0_dup_1205_aIN);
delay_1537: DELAY
PORT MAP ( Y => O_dup_1649_aOUT, IN1 => O_dup_1649_aIN);
and2_1538: AND2
PORT MAP ( Y => O_dup_1649_aIN, IN1 => n_1915, IN2 => n_1930);
or4_1539: OR4
PORT MAP ( Y => n_1915, IN1 => n_1916, IN2 => n_1919, IN3 => n_1924, IN4 => n_1927);
and2_1540: AND2
PORT MAP ( Y => n_1916, IN1 => n_1917, IN2 => n_1918);
inv_1541: INV
PORT MAP ( Y => n_1917, IN1 => outregrd_aOUT);
delay_1542: DELAY
PORT MAP ( Y => n_1918, IN1 => n3_aOUT);
and2_1543: AND2
PORT MAP ( Y => n_1919, IN1 => n_1920, IN2 => n_1922);
inv_1544: INV
PORT MAP ( Y => n_1920, IN1 => outreg_val10_Q);
inv_1545: INV
PORT MAP ( Y => n_1922, IN1 => progcntr_val10_Q);
and2_1546: AND2
PORT MAP ( Y => n_1924, IN1 => n_1925, IN2 => n_1926);
inv_1547: INV
PORT MAP ( Y => n_1925, IN1 => progcntr_val10_Q);
inv_1548: INV
PORT MAP ( Y => n_1926, IN1 => outregrd_aOUT);
and2_1549: AND2
PORT MAP ( Y => n_1927, IN1 => n_1928, IN2 => n_1929);
inv_1550: INV
PORT MAP ( Y => n_1928, IN1 => outreg_val10_Q);
delay_1551: DELAY
PORT MAP ( Y => n_1929, IN1 => n3_aOUT);
delay_1552: DELAY
PORT MAP ( Y => n_1930, IN1 => O_dup_1207_aIN);
delay_1553: DELAY
PORT MAP ( Y => I1_dup_792_aOUT, IN1 => I1_dup_792_aIN);
and2_1554: AND2
PORT MAP ( Y => I1_dup_792_aIN, IN1 => n_1933, IN2 => n_1948);
or4_1555: OR4
PORT MAP ( Y => n_1933, IN1 => n_1934, IN2 => n_1937, IN3 => n_1941, IN4 => n_1945);
and2_1556: AND2
PORT MAP ( Y => n_1934, IN1 => n_1935, IN2 => n_1936);
inv_1557: INV
PORT MAP ( Y => n_1935, IN1 => O_dup_876_aOUT);
inv_1558: INV
PORT MAP ( Y => n_1936, IN1 => O_dup_879_aOUT);
and2_1559: AND2
PORT MAP ( Y => n_1937, IN1 => n_1938, IN2 => n_1940);
inv_1560: INV
PORT MAP ( Y => n_1938, IN1 => ix484_a2_dup_572_Q);
inv_1561: INV
PORT MAP ( Y => n_1940, IN1 => O_dup_879_aOUT);
and2_1562: AND2
PORT MAP ( Y => n_1941, IN1 => n_1942, IN2 => n_1944);
inv_1563: INV
PORT MAP ( Y => n_1942, IN1 => ix484_a7_dup_567_Q);
inv_1564: INV
PORT MAP ( Y => n_1944, IN1 => ix484_a2_dup_572_Q);
and2_1565: AND2
PORT MAP ( Y => n_1945, IN1 => n_1946, IN2 => n_1947);
inv_1566: INV
PORT MAP ( Y => n_1946, IN1 => ix484_a7_dup_567_Q);
inv_1567: INV
PORT MAP ( Y => n_1947, IN1 => O_dup_876_aOUT);
delay_1568: DELAY
PORT MAP ( Y => n_1948, IN1 => O_dup_1649_aIN);
delay_1569: DELAY
PORT MAP ( Y => O_dup_793_aOUT, IN1 => O_dup_793_aIN1);
and2_1570: AND2
PORT MAP ( Y => O_dup_793_aIN1, IN1 => n_1950, IN2 => n_1965);
or4_1571: OR4
PORT MAP ( Y => n_1950, IN1 => n_1951, IN2 => n_1954, IN3 => n_1958, IN4 => n_1962);
and2_1572: AND2
PORT MAP ( Y => n_1951, IN1 => n_1952, IN2 => n_1953);
inv_1573: INV
PORT MAP ( Y => n_1952, IN1 => O_dup_870_aOUT);
inv_1574: INV
PORT MAP ( Y => n_1953, IN1 => O_dup_873_aOUT);
and2_1575: AND2
PORT MAP ( Y => n_1954, IN1 => n_1955, IN2 => n_1957);
inv_1576: INV
PORT MAP ( Y => n_1955, IN1 => ix484_a4_dup_570_Q);
inv_1577: INV
PORT MAP ( Y => n_1957, IN1 => O_dup_873_aOUT);
and2_1578: AND2
PORT MAP ( Y => n_1958, IN1 => n_1959, IN2 => n_1961);
inv_1579: INV
PORT MAP ( Y => n_1959, IN1 => ix484_a0_dup_574_Q);
inv_1580: INV
PORT MAP ( Y => n_1961, IN1 => ix484_a4_dup_570_Q);
and2_1581: AND2
PORT MAP ( Y => n_1962, IN1 => n_1963, IN2 => n_1964);
inv_1582: INV
PORT MAP ( Y => n_1963, IN1 => ix484_a0_dup_574_Q);
inv_1583: INV
PORT MAP ( Y => n_1964, IN1 => O_dup_870_aOUT);
delay_1584: DELAY
PORT MAP ( Y => n_1965, IN1 => I1_dup_792_aIN);
dffe_1585: DFFE
PORT MAP ( D => ix484_a3_dup_571_aD, CLK => ix484_a3_dup_571_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_571_aENA, Q => ix484_a3_dup_571_Q);
xor2_1586: XOR2
PORT MAP ( Y => ix484_a3_dup_571_aD, IN1 => n_1972, IN2 => n_1975);
or1_1587: OR1
PORT MAP ( Y => n_1972, IN1 => n_1973);
and1_1588: AND1
PORT MAP ( Y => n_1973, IN1 => n_1974);
delay_1589: DELAY
PORT MAP ( Y => n_1974, IN1 => data(10));
and1_1590: AND1
PORT MAP ( Y => n_1975, IN1 => gnd);
and1_1591: AND1
PORT MAP ( Y => n_1976, IN1 => n_1977);
delay_1592: DELAY
PORT MAP ( Y => n_1977, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1593: DELAY
PORT MAP ( Y => ix484_a3_dup_571_aCLK, IN1 => n_1976);
and1_1594: AND1
PORT MAP ( Y => ix484_a3_dup_571_aENA, IN1 => n_1980);
delay_1595: DELAY
PORT MAP ( Y => n_1980, IN1 => ix484_nx42_aOUT);
dffe_1596: DFFE
PORT MAP ( D => ix484_a6_dup_568_aD, CLK => ix484_a6_dup_568_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_568_aENA, Q => ix484_a6_dup_568_Q);
xor2_1597: XOR2
PORT MAP ( Y => ix484_a6_dup_568_aD, IN1 => n_1987, IN2 => n_1990);
or1_1598: OR1
PORT MAP ( Y => n_1987, IN1 => n_1988);
and1_1599: AND1
PORT MAP ( Y => n_1988, IN1 => n_1989);
delay_1600: DELAY
PORT MAP ( Y => n_1989, IN1 => data(10));
and1_1601: AND1
PORT MAP ( Y => n_1990, IN1 => gnd);
and1_1602: AND1
PORT MAP ( Y => n_1991, IN1 => n_1992);
delay_1603: DELAY
PORT MAP ( Y => n_1992, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1604: DELAY
PORT MAP ( Y => ix484_a6_dup_568_aCLK, IN1 => n_1991);
and1_1605: AND1
PORT MAP ( Y => ix484_a6_dup_568_aENA, IN1 => n_1995);
delay_1606: DELAY
PORT MAP ( Y => n_1995, IN1 => ix484_nx39_aOUT);
delay_1607: DELAY
PORT MAP ( Y => I0_dup_1177_aOUT, IN1 => I0_dup_1177_aIN);
xor2_1608: XOR2
PORT MAP ( Y => I0_dup_1177_aIN, IN1 => n_1998, IN2 => n_2013);
or4_1609: OR4
PORT MAP ( Y => n_1998, IN1 => n_1999, IN2 => n_2002, IN3 => n_2006, IN4 => n_2010);
and2_1610: AND2
PORT MAP ( Y => n_1999, IN1 => n_2000, IN2 => n_2001);
inv_1611: INV
PORT MAP ( Y => n_2000, IN1 => O_dup_888_aOUT);
inv_1612: INV
PORT MAP ( Y => n_2001, IN1 => O_dup_891_aOUT);
and2_1613: AND2
PORT MAP ( Y => n_2002, IN1 => n_2003, IN2 => n_2005);
inv_1614: INV
PORT MAP ( Y => n_2003, IN1 => ix484_a3_dup_563_Q);
inv_1615: INV
PORT MAP ( Y => n_2005, IN1 => O_dup_891_aOUT);
and2_1616: AND2
PORT MAP ( Y => n_2006, IN1 => n_2007, IN2 => n_2009);
inv_1617: INV
PORT MAP ( Y => n_2007, IN1 => ix484_a6_dup_560_Q);
inv_1618: INV
PORT MAP ( Y => n_2009, IN1 => ix484_a3_dup_563_Q);
and2_1619: AND2
PORT MAP ( Y => n_2010, IN1 => n_2011, IN2 => n_2012);
inv_1620: INV
PORT MAP ( Y => n_2011, IN1 => ix484_a6_dup_560_Q);
inv_1621: INV
PORT MAP ( Y => n_2012, IN1 => O_dup_888_aOUT);
and1_1622: AND1
PORT MAP ( Y => n_2013, IN1 => gnd);
delay_1623: DELAY
PORT MAP ( Y => O_dup_1179_aOUT, IN1 => O_dup_1179_aIN);
and2_1624: AND2
PORT MAP ( Y => O_dup_1179_aIN, IN1 => n_2016, IN2 => n_2031);
or4_1625: OR4
PORT MAP ( Y => n_2016, IN1 => n_2017, IN2 => n_2020, IN3 => n_2024, IN4 => n_2028);
and2_1626: AND2
PORT MAP ( Y => n_2017, IN1 => n_2018, IN2 => n_2019);
inv_1627: INV
PORT MAP ( Y => n_2018, IN1 => O_dup_882_aOUT);
inv_1628: INV
PORT MAP ( Y => n_2019, IN1 => O_dup_885_aOUT);
and2_1629: AND2
PORT MAP ( Y => n_2020, IN1 => n_2021, IN2 => n_2023);
inv_1630: INV
PORT MAP ( Y => n_2021, IN1 => ix484_a1_dup_565_Q);
inv_1631: INV
PORT MAP ( Y => n_2023, IN1 => O_dup_885_aOUT);
and2_1632: AND2
PORT MAP ( Y => n_2024, IN1 => n_2025, IN2 => n_2027);
inv_1633: INV
PORT MAP ( Y => n_2025, IN1 => ix484_a5_dup_561_Q);
inv_1634: INV
PORT MAP ( Y => n_2027, IN1 => ix484_a1_dup_565_Q);
and2_1635: AND2
PORT MAP ( Y => n_2028, IN1 => n_2029, IN2 => n_2030);
inv_1636: INV
PORT MAP ( Y => n_2029, IN1 => ix484_a5_dup_561_Q);
inv_1637: INV
PORT MAP ( Y => n_2030, IN1 => O_dup_882_aOUT);
delay_1638: DELAY
PORT MAP ( Y => n_2031, IN1 => I0_dup_1177_aIN);
delay_1639: DELAY
PORT MAP ( Y => O_dup_1641_aOUT, IN1 => O_dup_1641_aIN);
and2_1640: AND2
PORT MAP ( Y => O_dup_1641_aIN, IN1 => n_2034, IN2 => n_2049);
or4_1641: OR4
PORT MAP ( Y => n_2034, IN1 => n_2035, IN2 => n_2038, IN3 => n_2043, IN4 => n_2046);
and2_1642: AND2
PORT MAP ( Y => n_2035, IN1 => n_2036, IN2 => n_2037);
inv_1643: INV
PORT MAP ( Y => n_2036, IN1 => outregrd_aOUT);
delay_1644: DELAY
PORT MAP ( Y => n_2037, IN1 => n3_aOUT);
and2_1645: AND2
PORT MAP ( Y => n_2038, IN1 => n_2039, IN2 => n_2041);
inv_1646: INV
PORT MAP ( Y => n_2039, IN1 => outreg_val11_Q);
inv_1647: INV
PORT MAP ( Y => n_2041, IN1 => progcntr_val11_Q);
and2_1648: AND2
PORT MAP ( Y => n_2043, IN1 => n_2044, IN2 => n_2045);
inv_1649: INV
PORT MAP ( Y => n_2044, IN1 => progcntr_val11_Q);
inv_1650: INV
PORT MAP ( Y => n_2045, IN1 => outregrd_aOUT);
and2_1651: AND2
PORT MAP ( Y => n_2046, IN1 => n_2047, IN2 => n_2048);
inv_1652: INV
PORT MAP ( Y => n_2047, IN1 => outreg_val11_Q);
delay_1653: DELAY
PORT MAP ( Y => n_2048, IN1 => n3_aOUT);
delay_1654: DELAY
PORT MAP ( Y => n_2049, IN1 => O_dup_1179_aIN);
delay_1655: DELAY
PORT MAP ( Y => I1_dup_789_aOUT, IN1 => I1_dup_789_aIN);
and2_1656: AND2
PORT MAP ( Y => I1_dup_789_aIN, IN1 => n_2052, IN2 => n_2067);
or4_1657: OR4
PORT MAP ( Y => n_2052, IN1 => n_2053, IN2 => n_2056, IN3 => n_2060, IN4 => n_2064);
and2_1658: AND2
PORT MAP ( Y => n_2053, IN1 => n_2054, IN2 => n_2055);
inv_1659: INV
PORT MAP ( Y => n_2054, IN1 => O_dup_876_aOUT);
inv_1660: INV
PORT MAP ( Y => n_2055, IN1 => O_dup_879_aOUT);
and2_1661: AND2
PORT MAP ( Y => n_2056, IN1 => n_2057, IN2 => n_2059);
inv_1662: INV
PORT MAP ( Y => n_2057, IN1 => ix484_a2_dup_564_Q);
inv_1663: INV
PORT MAP ( Y => n_2059, IN1 => O_dup_879_aOUT);
and2_1664: AND2
PORT MAP ( Y => n_2060, IN1 => n_2061, IN2 => n_2063);
inv_1665: INV
PORT MAP ( Y => n_2061, IN1 => ix484_a7_dup_559_Q);
inv_1666: INV
PORT MAP ( Y => n_2063, IN1 => ix484_a2_dup_564_Q);
and2_1667: AND2
PORT MAP ( Y => n_2064, IN1 => n_2065, IN2 => n_2066);
inv_1668: INV
PORT MAP ( Y => n_2065, IN1 => ix484_a7_dup_559_Q);
inv_1669: INV
PORT MAP ( Y => n_2066, IN1 => O_dup_876_aOUT);
delay_1670: DELAY
PORT MAP ( Y => n_2067, IN1 => O_dup_1641_aIN);
delay_1671: DELAY
PORT MAP ( Y => O_dup_790_aOUT, IN1 => O_dup_790_aIN1);
and2_1672: AND2
PORT MAP ( Y => O_dup_790_aIN1, IN1 => n_2069, IN2 => n_2084);
or4_1673: OR4
PORT MAP ( Y => n_2069, IN1 => n_2070, IN2 => n_2073, IN3 => n_2077, IN4 => n_2081);
and2_1674: AND2
PORT MAP ( Y => n_2070, IN1 => n_2071, IN2 => n_2072);
inv_1675: INV
PORT MAP ( Y => n_2071, IN1 => O_dup_870_aOUT);
inv_1676: INV
PORT MAP ( Y => n_2072, IN1 => O_dup_873_aOUT);
and2_1677: AND2
PORT MAP ( Y => n_2073, IN1 => n_2074, IN2 => n_2076);
inv_1678: INV
PORT MAP ( Y => n_2074, IN1 => ix484_a4_dup_562_Q);
inv_1679: INV
PORT MAP ( Y => n_2076, IN1 => O_dup_873_aOUT);
and2_1680: AND2
PORT MAP ( Y => n_2077, IN1 => n_2078, IN2 => n_2080);
inv_1681: INV
PORT MAP ( Y => n_2078, IN1 => ix484_a0_dup_566_Q);
inv_1682: INV
PORT MAP ( Y => n_2080, IN1 => ix484_a4_dup_562_Q);
and2_1683: AND2
PORT MAP ( Y => n_2081, IN1 => n_2082, IN2 => n_2083);
inv_1684: INV
PORT MAP ( Y => n_2082, IN1 => ix484_a0_dup_566_Q);
inv_1685: INV
PORT MAP ( Y => n_2083, IN1 => O_dup_870_aOUT);
delay_1686: DELAY
PORT MAP ( Y => n_2084, IN1 => I1_dup_789_aIN);
dffe_1687: DFFE
PORT MAP ( D => ix484_a3_dup_563_aD, CLK => ix484_a3_dup_563_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_563_aENA, Q => ix484_a3_dup_563_Q);
xor2_1688: XOR2
PORT MAP ( Y => ix484_a3_dup_563_aD, IN1 => n_2091, IN2 => n_2094);
or1_1689: OR1
PORT MAP ( Y => n_2091, IN1 => n_2092);
and1_1690: AND1
PORT MAP ( Y => n_2092, IN1 => n_2093);
delay_1691: DELAY
PORT MAP ( Y => n_2093, IN1 => data(11));
and1_1692: AND1
PORT MAP ( Y => n_2094, IN1 => gnd);
and1_1693: AND1
PORT MAP ( Y => n_2095, IN1 => n_2096);
delay_1694: DELAY
PORT MAP ( Y => n_2096, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1695: DELAY
PORT MAP ( Y => ix484_a3_dup_563_aCLK, IN1 => n_2095);
and1_1696: AND1
PORT MAP ( Y => ix484_a3_dup_563_aENA, IN1 => n_2099);
delay_1697: DELAY
PORT MAP ( Y => n_2099, IN1 => ix484_nx42_aOUT);
dffe_1698: DFFE
PORT MAP ( D => ix484_a6_dup_560_aD, CLK => ix484_a6_dup_560_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_560_aENA, Q => ix484_a6_dup_560_Q);
xor2_1699: XOR2
PORT MAP ( Y => ix484_a6_dup_560_aD, IN1 => n_2106, IN2 => n_2109);
or1_1700: OR1
PORT MAP ( Y => n_2106, IN1 => n_2107);
and1_1701: AND1
PORT MAP ( Y => n_2107, IN1 => n_2108);
delay_1702: DELAY
PORT MAP ( Y => n_2108, IN1 => data(11));
and1_1703: AND1
PORT MAP ( Y => n_2109, IN1 => gnd);
and1_1704: AND1
PORT MAP ( Y => n_2110, IN1 => n_2111);
delay_1705: DELAY
PORT MAP ( Y => n_2111, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1706: DELAY
PORT MAP ( Y => ix484_a6_dup_560_aCLK, IN1 => n_2110);
and1_1707: AND1
PORT MAP ( Y => ix484_a6_dup_560_aENA, IN1 => n_2114);
delay_1708: DELAY
PORT MAP ( Y => n_2114, IN1 => ix484_nx39_aOUT);
delay_1709: DELAY
PORT MAP ( Y => I0_dup_1149_aOUT, IN1 => I0_dup_1149_aIN);
xor2_1710: XOR2
PORT MAP ( Y => I0_dup_1149_aIN, IN1 => n_2117, IN2 => n_2132);
or4_1711: OR4
PORT MAP ( Y => n_2117, IN1 => n_2118, IN2 => n_2121, IN3 => n_2125, IN4 => n_2129);
and2_1712: AND2
PORT MAP ( Y => n_2118, IN1 => n_2119, IN2 => n_2120);
inv_1713: INV
PORT MAP ( Y => n_2119, IN1 => O_dup_888_aOUT);
inv_1714: INV
PORT MAP ( Y => n_2120, IN1 => O_dup_891_aOUT);
and2_1715: AND2
PORT MAP ( Y => n_2121, IN1 => n_2122, IN2 => n_2124);
inv_1716: INV
PORT MAP ( Y => n_2122, IN1 => ix484_a3_dup_555_Q);
inv_1717: INV
PORT MAP ( Y => n_2124, IN1 => O_dup_891_aOUT);
and2_1718: AND2
PORT MAP ( Y => n_2125, IN1 => n_2126, IN2 => n_2128);
inv_1719: INV
PORT MAP ( Y => n_2126, IN1 => ix484_a6_dup_552_Q);
inv_1720: INV
PORT MAP ( Y => n_2128, IN1 => ix484_a3_dup_555_Q);
and2_1721: AND2
PORT MAP ( Y => n_2129, IN1 => n_2130, IN2 => n_2131);
inv_1722: INV
PORT MAP ( Y => n_2130, IN1 => ix484_a6_dup_552_Q);
inv_1723: INV
PORT MAP ( Y => n_2131, IN1 => O_dup_888_aOUT);
and1_1724: AND1
PORT MAP ( Y => n_2132, IN1 => gnd);
delay_1725: DELAY
PORT MAP ( Y => O_dup_1151_aOUT, IN1 => O_dup_1151_aIN);
and2_1726: AND2
PORT MAP ( Y => O_dup_1151_aIN, IN1 => n_2135, IN2 => n_2150);
or4_1727: OR4
PORT MAP ( Y => n_2135, IN1 => n_2136, IN2 => n_2139, IN3 => n_2143, IN4 => n_2147);
and2_1728: AND2
PORT MAP ( Y => n_2136, IN1 => n_2137, IN2 => n_2138);
inv_1729: INV
PORT MAP ( Y => n_2137, IN1 => O_dup_882_aOUT);
inv_1730: INV
PORT MAP ( Y => n_2138, IN1 => O_dup_885_aOUT);
and2_1731: AND2
PORT MAP ( Y => n_2139, IN1 => n_2140, IN2 => n_2142);
inv_1732: INV
PORT MAP ( Y => n_2140, IN1 => ix484_a1_dup_557_Q);
inv_1733: INV
PORT MAP ( Y => n_2142, IN1 => O_dup_885_aOUT);
and2_1734: AND2
PORT MAP ( Y => n_2143, IN1 => n_2144, IN2 => n_2146);
inv_1735: INV
PORT MAP ( Y => n_2144, IN1 => ix484_a5_dup_553_Q);
inv_1736: INV
PORT MAP ( Y => n_2146, IN1 => ix484_a1_dup_557_Q);
and2_1737: AND2
PORT MAP ( Y => n_2147, IN1 => n_2148, IN2 => n_2149);
inv_1738: INV
PORT MAP ( Y => n_2148, IN1 => ix484_a5_dup_553_Q);
inv_1739: INV
PORT MAP ( Y => n_2149, IN1 => O_dup_882_aOUT);
delay_1740: DELAY
PORT MAP ( Y => n_2150, IN1 => I0_dup_1149_aIN);
delay_1741: DELAY
PORT MAP ( Y => O_dup_1633_aOUT, IN1 => O_dup_1633_aIN);
and2_1742: AND2
PORT MAP ( Y => O_dup_1633_aIN, IN1 => n_2153, IN2 => n_2168);
or4_1743: OR4
PORT MAP ( Y => n_2153, IN1 => n_2154, IN2 => n_2157, IN3 => n_2162, IN4 => n_2165);
and2_1744: AND2
PORT MAP ( Y => n_2154, IN1 => n_2155, IN2 => n_2156);
inv_1745: INV
PORT MAP ( Y => n_2155, IN1 => outregrd_aOUT);
delay_1746: DELAY
PORT MAP ( Y => n_2156, IN1 => n3_aOUT);
and2_1747: AND2
PORT MAP ( Y => n_2157, IN1 => n_2158, IN2 => n_2160);
inv_1748: INV
PORT MAP ( Y => n_2158, IN1 => outreg_val12_Q);
inv_1749: INV
PORT MAP ( Y => n_2160, IN1 => progcntr_val12_Q);
and2_1750: AND2
PORT MAP ( Y => n_2162, IN1 => n_2163, IN2 => n_2164);
inv_1751: INV
PORT MAP ( Y => n_2163, IN1 => progcntr_val12_Q);
inv_1752: INV
PORT MAP ( Y => n_2164, IN1 => outregrd_aOUT);
and2_1753: AND2
PORT MAP ( Y => n_2165, IN1 => n_2166, IN2 => n_2167);
inv_1754: INV
PORT MAP ( Y => n_2166, IN1 => outreg_val12_Q);
delay_1755: DELAY
PORT MAP ( Y => n_2167, IN1 => n3_aOUT);
delay_1756: DELAY
PORT MAP ( Y => n_2168, IN1 => O_dup_1151_aIN);
delay_1757: DELAY
PORT MAP ( Y => I1_dup_786_aOUT, IN1 => I1_dup_786_aIN);
and2_1758: AND2
PORT MAP ( Y => I1_dup_786_aIN, IN1 => n_2171, IN2 => n_2186);
or4_1759: OR4
PORT MAP ( Y => n_2171, IN1 => n_2172, IN2 => n_2175, IN3 => n_2179, IN4 => n_2183);
and2_1760: AND2
PORT MAP ( Y => n_2172, IN1 => n_2173, IN2 => n_2174);
inv_1761: INV
PORT MAP ( Y => n_2173, IN1 => O_dup_876_aOUT);
inv_1762: INV
PORT MAP ( Y => n_2174, IN1 => O_dup_879_aOUT);
and2_1763: AND2
PORT MAP ( Y => n_2175, IN1 => n_2176, IN2 => n_2178);
inv_1764: INV
PORT MAP ( Y => n_2176, IN1 => ix484_a2_dup_556_Q);
inv_1765: INV
PORT MAP ( Y => n_2178, IN1 => O_dup_879_aOUT);
and2_1766: AND2
PORT MAP ( Y => n_2179, IN1 => n_2180, IN2 => n_2182);
inv_1767: INV
PORT MAP ( Y => n_2180, IN1 => ix484_a7_dup_551_Q);
inv_1768: INV
PORT MAP ( Y => n_2182, IN1 => ix484_a2_dup_556_Q);
and2_1769: AND2
PORT MAP ( Y => n_2183, IN1 => n_2184, IN2 => n_2185);
inv_1770: INV
PORT MAP ( Y => n_2184, IN1 => ix484_a7_dup_551_Q);
inv_1771: INV
PORT MAP ( Y => n_2185, IN1 => O_dup_876_aOUT);
delay_1772: DELAY
PORT MAP ( Y => n_2186, IN1 => O_dup_1633_aIN);
delay_1773: DELAY
PORT MAP ( Y => O_dup_787_aOUT, IN1 => O_dup_787_aIN1);
and2_1774: AND2
PORT MAP ( Y => O_dup_787_aIN1, IN1 => n_2188, IN2 => n_2203);
or4_1775: OR4
PORT MAP ( Y => n_2188, IN1 => n_2189, IN2 => n_2192, IN3 => n_2196, IN4 => n_2200);
and2_1776: AND2
PORT MAP ( Y => n_2189, IN1 => n_2190, IN2 => n_2191);
inv_1777: INV
PORT MAP ( Y => n_2190, IN1 => O_dup_870_aOUT);
inv_1778: INV
PORT MAP ( Y => n_2191, IN1 => O_dup_873_aOUT);
and2_1779: AND2
PORT MAP ( Y => n_2192, IN1 => n_2193, IN2 => n_2195);
inv_1780: INV
PORT MAP ( Y => n_2193, IN1 => ix484_a4_dup_554_Q);
inv_1781: INV
PORT MAP ( Y => n_2195, IN1 => O_dup_873_aOUT);
and2_1782: AND2
PORT MAP ( Y => n_2196, IN1 => n_2197, IN2 => n_2199);
inv_1783: INV
PORT MAP ( Y => n_2197, IN1 => ix484_a0_dup_558_Q);
inv_1784: INV
PORT MAP ( Y => n_2199, IN1 => ix484_a4_dup_554_Q);
and2_1785: AND2
PORT MAP ( Y => n_2200, IN1 => n_2201, IN2 => n_2202);
inv_1786: INV
PORT MAP ( Y => n_2201, IN1 => ix484_a0_dup_558_Q);
inv_1787: INV
PORT MAP ( Y => n_2202, IN1 => O_dup_870_aOUT);
delay_1788: DELAY
PORT MAP ( Y => n_2203, IN1 => I1_dup_786_aIN);
dffe_1789: DFFE
PORT MAP ( D => ix484_a3_dup_555_aD, CLK => ix484_a3_dup_555_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_555_aENA, Q => ix484_a3_dup_555_Q);
xor2_1790: XOR2
PORT MAP ( Y => ix484_a3_dup_555_aD, IN1 => n_2210, IN2 => n_2213);
or1_1791: OR1
PORT MAP ( Y => n_2210, IN1 => n_2211);
and1_1792: AND1
PORT MAP ( Y => n_2211, IN1 => n_2212);
delay_1793: DELAY
PORT MAP ( Y => n_2212, IN1 => data(12));
and1_1794: AND1
PORT MAP ( Y => n_2213, IN1 => gnd);
and1_1795: AND1
PORT MAP ( Y => n_2214, IN1 => n_2215);
delay_1796: DELAY
PORT MAP ( Y => n_2215, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1797: DELAY
PORT MAP ( Y => ix484_a3_dup_555_aCLK, IN1 => n_2214);
and1_1798: AND1
PORT MAP ( Y => ix484_a3_dup_555_aENA, IN1 => n_2218);
delay_1799: DELAY
PORT MAP ( Y => n_2218, IN1 => ix484_nx42_aOUT);
dffe_1800: DFFE
PORT MAP ( D => ix484_a6_dup_552_aD, CLK => ix484_a6_dup_552_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_552_aENA, Q => ix484_a6_dup_552_Q);
xor2_1801: XOR2
PORT MAP ( Y => ix484_a6_dup_552_aD, IN1 => n_2225, IN2 => n_2228);
or1_1802: OR1
PORT MAP ( Y => n_2225, IN1 => n_2226);
and1_1803: AND1
PORT MAP ( Y => n_2226, IN1 => n_2227);
delay_1804: DELAY
PORT MAP ( Y => n_2227, IN1 => data(12));
and1_1805: AND1
PORT MAP ( Y => n_2228, IN1 => gnd);
and1_1806: AND1
PORT MAP ( Y => n_2229, IN1 => n_2230);
delay_1807: DELAY
PORT MAP ( Y => n_2230, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1808: DELAY
PORT MAP ( Y => ix484_a6_dup_552_aCLK, IN1 => n_2229);
and1_1809: AND1
PORT MAP ( Y => ix484_a6_dup_552_aENA, IN1 => n_2233);
delay_1810: DELAY
PORT MAP ( Y => n_2233, IN1 => ix484_nx39_aOUT);
delay_1811: DELAY
PORT MAP ( Y => I0_dup_1121_aOUT, IN1 => I0_dup_1121_aIN);
xor2_1812: XOR2
PORT MAP ( Y => I0_dup_1121_aIN, IN1 => n_2236, IN2 => n_2251);
or4_1813: OR4
PORT MAP ( Y => n_2236, IN1 => n_2237, IN2 => n_2240, IN3 => n_2244, IN4 => n_2248);
and2_1814: AND2
PORT MAP ( Y => n_2237, IN1 => n_2238, IN2 => n_2239);
inv_1815: INV
PORT MAP ( Y => n_2238, IN1 => O_dup_888_aOUT);
inv_1816: INV
PORT MAP ( Y => n_2239, IN1 => O_dup_891_aOUT);
and2_1817: AND2
PORT MAP ( Y => n_2240, IN1 => n_2241, IN2 => n_2243);
inv_1818: INV
PORT MAP ( Y => n_2241, IN1 => ix484_a3_dup_547_Q);
inv_1819: INV
PORT MAP ( Y => n_2243, IN1 => O_dup_891_aOUT);
and2_1820: AND2
PORT MAP ( Y => n_2244, IN1 => n_2245, IN2 => n_2247);
inv_1821: INV
PORT MAP ( Y => n_2245, IN1 => ix484_a6_dup_544_Q);
inv_1822: INV
PORT MAP ( Y => n_2247, IN1 => ix484_a3_dup_547_Q);
and2_1823: AND2
PORT MAP ( Y => n_2248, IN1 => n_2249, IN2 => n_2250);
inv_1824: INV
PORT MAP ( Y => n_2249, IN1 => ix484_a6_dup_544_Q);
inv_1825: INV
PORT MAP ( Y => n_2250, IN1 => O_dup_888_aOUT);
and1_1826: AND1
PORT MAP ( Y => n_2251, IN1 => gnd);
delay_1827: DELAY
PORT MAP ( Y => O_dup_1123_aOUT, IN1 => O_dup_1123_aIN);
and2_1828: AND2
PORT MAP ( Y => O_dup_1123_aIN, IN1 => n_2254, IN2 => n_2269);
or4_1829: OR4
PORT MAP ( Y => n_2254, IN1 => n_2255, IN2 => n_2258, IN3 => n_2262, IN4 => n_2266);
and2_1830: AND2
PORT MAP ( Y => n_2255, IN1 => n_2256, IN2 => n_2257);
inv_1831: INV
PORT MAP ( Y => n_2256, IN1 => O_dup_882_aOUT);
inv_1832: INV
PORT MAP ( Y => n_2257, IN1 => O_dup_885_aOUT);
and2_1833: AND2
PORT MAP ( Y => n_2258, IN1 => n_2259, IN2 => n_2261);
inv_1834: INV
PORT MAP ( Y => n_2259, IN1 => ix484_a1_dup_549_Q);
inv_1835: INV
PORT MAP ( Y => n_2261, IN1 => O_dup_885_aOUT);
and2_1836: AND2
PORT MAP ( Y => n_2262, IN1 => n_2263, IN2 => n_2265);
inv_1837: INV
PORT MAP ( Y => n_2263, IN1 => ix484_a5_dup_545_Q);
inv_1838: INV
PORT MAP ( Y => n_2265, IN1 => ix484_a1_dup_549_Q);
and2_1839: AND2
PORT MAP ( Y => n_2266, IN1 => n_2267, IN2 => n_2268);
inv_1840: INV
PORT MAP ( Y => n_2267, IN1 => ix484_a5_dup_545_Q);
inv_1841: INV
PORT MAP ( Y => n_2268, IN1 => O_dup_882_aOUT);
delay_1842: DELAY
PORT MAP ( Y => n_2269, IN1 => I0_dup_1121_aIN);
delay_1843: DELAY
PORT MAP ( Y => O_dup_1625_aOUT, IN1 => O_dup_1625_aIN);
and2_1844: AND2
PORT MAP ( Y => O_dup_1625_aIN, IN1 => n_2272, IN2 => n_2287);
or4_1845: OR4
PORT MAP ( Y => n_2272, IN1 => n_2273, IN2 => n_2276, IN3 => n_2281, IN4 => n_2284);
and2_1846: AND2
PORT MAP ( Y => n_2273, IN1 => n_2274, IN2 => n_2275);
inv_1847: INV
PORT MAP ( Y => n_2274, IN1 => outregrd_aOUT);
delay_1848: DELAY
PORT MAP ( Y => n_2275, IN1 => n3_aOUT);
and2_1849: AND2
PORT MAP ( Y => n_2276, IN1 => n_2277, IN2 => n_2279);
inv_1850: INV
PORT MAP ( Y => n_2277, IN1 => outreg_val13_Q);
inv_1851: INV
PORT MAP ( Y => n_2279, IN1 => progcntr_val13_Q);
and2_1852: AND2
PORT MAP ( Y => n_2281, IN1 => n_2282, IN2 => n_2283);
inv_1853: INV
PORT MAP ( Y => n_2282, IN1 => progcntr_val13_Q);
inv_1854: INV
PORT MAP ( Y => n_2283, IN1 => outregrd_aOUT);
and2_1855: AND2
PORT MAP ( Y => n_2284, IN1 => n_2285, IN2 => n_2286);
inv_1856: INV
PORT MAP ( Y => n_2285, IN1 => outreg_val13_Q);
delay_1857: DELAY
PORT MAP ( Y => n_2286, IN1 => n3_aOUT);
delay_1858: DELAY
PORT MAP ( Y => n_2287, IN1 => O_dup_1123_aIN);
delay_1859: DELAY
PORT MAP ( Y => I1_dup_783_aOUT, IN1 => I1_dup_783_aIN);
and2_1860: AND2
PORT MAP ( Y => I1_dup_783_aIN, IN1 => n_2290, IN2 => n_2305);
or4_1861: OR4
PORT MAP ( Y => n_2290, IN1 => n_2291, IN2 => n_2294, IN3 => n_2298, IN4 => n_2302);
and2_1862: AND2
PORT MAP ( Y => n_2291, IN1 => n_2292, IN2 => n_2293);
inv_1863: INV
PORT MAP ( Y => n_2292, IN1 => O_dup_876_aOUT);
inv_1864: INV
PORT MAP ( Y => n_2293, IN1 => O_dup_879_aOUT);
and2_1865: AND2
PORT MAP ( Y => n_2294, IN1 => n_2295, IN2 => n_2297);
inv_1866: INV
PORT MAP ( Y => n_2295, IN1 => ix484_a2_dup_548_Q);
inv_1867: INV
PORT MAP ( Y => n_2297, IN1 => O_dup_879_aOUT);
and2_1868: AND2
PORT MAP ( Y => n_2298, IN1 => n_2299, IN2 => n_2301);
inv_1869: INV
PORT MAP ( Y => n_2299, IN1 => ix484_a7_dup_543_Q);
inv_1870: INV
PORT MAP ( Y => n_2301, IN1 => ix484_a2_dup_548_Q);
and2_1871: AND2
PORT MAP ( Y => n_2302, IN1 => n_2303, IN2 => n_2304);
inv_1872: INV
PORT MAP ( Y => n_2303, IN1 => ix484_a7_dup_543_Q);
inv_1873: INV
PORT MAP ( Y => n_2304, IN1 => O_dup_876_aOUT);
delay_1874: DELAY
PORT MAP ( Y => n_2305, IN1 => O_dup_1625_aIN);
delay_1875: DELAY
PORT MAP ( Y => O_dup_784_aOUT, IN1 => O_dup_784_aIN1);
and2_1876: AND2
PORT MAP ( Y => O_dup_784_aIN1, IN1 => n_2307, IN2 => n_2322);
or4_1877: OR4
PORT MAP ( Y => n_2307, IN1 => n_2308, IN2 => n_2311, IN3 => n_2315, IN4 => n_2319);
and2_1878: AND2
PORT MAP ( Y => n_2308, IN1 => n_2309, IN2 => n_2310);
inv_1879: INV
PORT MAP ( Y => n_2309, IN1 => O_dup_870_aOUT);
inv_1880: INV
PORT MAP ( Y => n_2310, IN1 => O_dup_873_aOUT);
and2_1881: AND2
PORT MAP ( Y => n_2311, IN1 => n_2312, IN2 => n_2314);
inv_1882: INV
PORT MAP ( Y => n_2312, IN1 => ix484_a4_dup_546_Q);
inv_1883: INV
PORT MAP ( Y => n_2314, IN1 => O_dup_873_aOUT);
and2_1884: AND2
PORT MAP ( Y => n_2315, IN1 => n_2316, IN2 => n_2318);
inv_1885: INV
PORT MAP ( Y => n_2316, IN1 => ix484_a0_dup_550_Q);
inv_1886: INV
PORT MAP ( Y => n_2318, IN1 => ix484_a4_dup_546_Q);
and2_1887: AND2
PORT MAP ( Y => n_2319, IN1 => n_2320, IN2 => n_2321);
inv_1888: INV
PORT MAP ( Y => n_2320, IN1 => ix484_a0_dup_550_Q);
inv_1889: INV
PORT MAP ( Y => n_2321, IN1 => O_dup_870_aOUT);
delay_1890: DELAY
PORT MAP ( Y => n_2322, IN1 => I1_dup_783_aIN);
dffe_1891: DFFE
PORT MAP ( D => ix484_a3_dup_547_aD, CLK => ix484_a3_dup_547_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_547_aENA, Q => ix484_a3_dup_547_Q);
xor2_1892: XOR2
PORT MAP ( Y => ix484_a3_dup_547_aD, IN1 => n_2329, IN2 => n_2332);
or1_1893: OR1
PORT MAP ( Y => n_2329, IN1 => n_2330);
and1_1894: AND1
PORT MAP ( Y => n_2330, IN1 => n_2331);
delay_1895: DELAY
PORT MAP ( Y => n_2331, IN1 => data(13));
and1_1896: AND1
PORT MAP ( Y => n_2332, IN1 => gnd);
and1_1897: AND1
PORT MAP ( Y => n_2333, IN1 => n_2334);
delay_1898: DELAY
PORT MAP ( Y => n_2334, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1899: DELAY
PORT MAP ( Y => ix484_a3_dup_547_aCLK, IN1 => n_2333);
and1_1900: AND1
PORT MAP ( Y => ix484_a3_dup_547_aENA, IN1 => n_2337);
delay_1901: DELAY
PORT MAP ( Y => n_2337, IN1 => ix484_nx42_aOUT);
dffe_1902: DFFE
PORT MAP ( D => ix484_a6_dup_544_aD, CLK => ix484_a6_dup_544_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_544_aENA, Q => ix484_a6_dup_544_Q);
xor2_1903: XOR2
PORT MAP ( Y => ix484_a6_dup_544_aD, IN1 => n_2344, IN2 => n_2347);
or1_1904: OR1
PORT MAP ( Y => n_2344, IN1 => n_2345);
and1_1905: AND1
PORT MAP ( Y => n_2345, IN1 => n_2346);
delay_1906: DELAY
PORT MAP ( Y => n_2346, IN1 => data(13));
and1_1907: AND1
PORT MAP ( Y => n_2347, IN1 => gnd);
and1_1908: AND1
PORT MAP ( Y => n_2348, IN1 => n_2349);
delay_1909: DELAY
PORT MAP ( Y => n_2349, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_1910: DELAY
PORT MAP ( Y => ix484_a6_dup_544_aCLK, IN1 => n_2348);
and1_1911: AND1
PORT MAP ( Y => ix484_a6_dup_544_aENA, IN1 => n_2352);
delay_1912: DELAY
PORT MAP ( Y => n_2352, IN1 => ix484_nx39_aOUT);
delay_1913: DELAY
PORT MAP ( Y => I0_dup_1093_aOUT, IN1 => I0_dup_1093_aIN);
xor2_1914: XOR2
PORT MAP ( Y => I0_dup_1093_aIN, IN1 => n_2355, IN2 => n_2370);
or4_1915: OR4
PORT MAP ( Y => n_2355, IN1 => n_2356, IN2 => n_2359, IN3 => n_2363, IN4 => n_2367);
and2_1916: AND2
PORT MAP ( Y => n_2356, IN1 => n_2357, IN2 => n_2358);
inv_1917: INV
PORT MAP ( Y => n_2357, IN1 => O_dup_888_aOUT);
inv_1918: INV
PORT MAP ( Y => n_2358, IN1 => O_dup_891_aOUT);
and2_1919: AND2
PORT MAP ( Y => n_2359, IN1 => n_2360, IN2 => n_2362);
inv_1920: INV
PORT MAP ( Y => n_2360, IN1 => ix484_a3_dup_539_Q);
inv_1921: INV
PORT MAP ( Y => n_2362, IN1 => O_dup_891_aOUT);
and2_1922: AND2
PORT MAP ( Y => n_2363, IN1 => n_2364, IN2 => n_2366);
inv_1923: INV
PORT MAP ( Y => n_2364, IN1 => ix484_a6_dup_536_Q);
inv_1924: INV
PORT MAP ( Y => n_2366, IN1 => ix484_a3_dup_539_Q);
and2_1925: AND2
PORT MAP ( Y => n_2367, IN1 => n_2368, IN2 => n_2369);
inv_1926: INV
PORT MAP ( Y => n_2368, IN1 => ix484_a6_dup_536_Q);
inv_1927: INV
PORT MAP ( Y => n_2369, IN1 => O_dup_888_aOUT);
and1_1928: AND1
PORT MAP ( Y => n_2370, IN1 => gnd);
delay_1929: DELAY
PORT MAP ( Y => O_dup_1095_aOUT, IN1 => O_dup_1095_aIN);
and2_1930: AND2
PORT MAP ( Y => O_dup_1095_aIN, IN1 => n_2373, IN2 => n_2388);
or4_1931: OR4
PORT MAP ( Y => n_2373, IN1 => n_2374, IN2 => n_2377, IN3 => n_2381, IN4 => n_2385);
and2_1932: AND2
PORT MAP ( Y => n_2374, IN1 => n_2375, IN2 => n_2376);
inv_1933: INV
PORT MAP ( Y => n_2375, IN1 => O_dup_882_aOUT);
inv_1934: INV
PORT MAP ( Y => n_2376, IN1 => O_dup_885_aOUT);
and2_1935: AND2
PORT MAP ( Y => n_2377, IN1 => n_2378, IN2 => n_2380);
inv_1936: INV
PORT MAP ( Y => n_2378, IN1 => ix484_a1_dup_541_Q);
inv_1937: INV
PORT MAP ( Y => n_2380, IN1 => O_dup_885_aOUT);
and2_1938: AND2
PORT MAP ( Y => n_2381, IN1 => n_2382, IN2 => n_2384);
inv_1939: INV
PORT MAP ( Y => n_2382, IN1 => ix484_a5_dup_537_Q);
inv_1940: INV
PORT MAP ( Y => n_2384, IN1 => ix484_a1_dup_541_Q);
and2_1941: AND2
PORT MAP ( Y => n_2385, IN1 => n_2386, IN2 => n_2387);
inv_1942: INV
PORT MAP ( Y => n_2386, IN1 => ix484_a5_dup_537_Q);
inv_1943: INV
PORT MAP ( Y => n_2387, IN1 => O_dup_882_aOUT);
delay_1944: DELAY
PORT MAP ( Y => n_2388, IN1 => I0_dup_1093_aIN);
delay_1945: DELAY
PORT MAP ( Y => O_dup_1617_aOUT, IN1 => O_dup_1617_aIN);
and2_1946: AND2
PORT MAP ( Y => O_dup_1617_aIN, IN1 => n_2391, IN2 => n_2406);
or4_1947: OR4
PORT MAP ( Y => n_2391, IN1 => n_2392, IN2 => n_2395, IN3 => n_2400, IN4 => n_2403);
and2_1948: AND2
PORT MAP ( Y => n_2392, IN1 => n_2393, IN2 => n_2394);
inv_1949: INV
PORT MAP ( Y => n_2393, IN1 => outregrd_aOUT);
delay_1950: DELAY
PORT MAP ( Y => n_2394, IN1 => n3_aOUT);
and2_1951: AND2
PORT MAP ( Y => n_2395, IN1 => n_2396, IN2 => n_2398);
inv_1952: INV
PORT MAP ( Y => n_2396, IN1 => outreg_val14_Q);
inv_1953: INV
PORT MAP ( Y => n_2398, IN1 => progcntr_val14_Q);
and2_1954: AND2
PORT MAP ( Y => n_2400, IN1 => n_2401, IN2 => n_2402);
inv_1955: INV
PORT MAP ( Y => n_2401, IN1 => progcntr_val14_Q);
inv_1956: INV
PORT MAP ( Y => n_2402, IN1 => outregrd_aOUT);
and2_1957: AND2
PORT MAP ( Y => n_2403, IN1 => n_2404, IN2 => n_2405);
inv_1958: INV
PORT MAP ( Y => n_2404, IN1 => outreg_val14_Q);
delay_1959: DELAY
PORT MAP ( Y => n_2405, IN1 => n3_aOUT);
delay_1960: DELAY
PORT MAP ( Y => n_2406, IN1 => O_dup_1095_aIN);
delay_1961: DELAY
PORT MAP ( Y => I1_dup_780_aOUT, IN1 => I1_dup_780_aIN);
and2_1962: AND2
PORT MAP ( Y => I1_dup_780_aIN, IN1 => n_2409, IN2 => n_2424);
or4_1963: OR4
PORT MAP ( Y => n_2409, IN1 => n_2410, IN2 => n_2413, IN3 => n_2417, IN4 => n_2421);
and2_1964: AND2
PORT MAP ( Y => n_2410, IN1 => n_2411, IN2 => n_2412);
inv_1965: INV
PORT MAP ( Y => n_2411, IN1 => O_dup_876_aOUT);
inv_1966: INV
PORT MAP ( Y => n_2412, IN1 => O_dup_879_aOUT);
and2_1967: AND2
PORT MAP ( Y => n_2413, IN1 => n_2414, IN2 => n_2416);
inv_1968: INV
PORT MAP ( Y => n_2414, IN1 => ix484_a2_dup_540_Q);
inv_1969: INV
PORT MAP ( Y => n_2416, IN1 => O_dup_879_aOUT);
and2_1970: AND2
PORT MAP ( Y => n_2417, IN1 => n_2418, IN2 => n_2420);
inv_1971: INV
PORT MAP ( Y => n_2418, IN1 => ix484_a7_dup_535_Q);
inv_1972: INV
PORT MAP ( Y => n_2420, IN1 => ix484_a2_dup_540_Q);
and2_1973: AND2
PORT MAP ( Y => n_2421, IN1 => n_2422, IN2 => n_2423);
inv_1974: INV
PORT MAP ( Y => n_2422, IN1 => ix484_a7_dup_535_Q);
inv_1975: INV
PORT MAP ( Y => n_2423, IN1 => O_dup_876_aOUT);
delay_1976: DELAY
PORT MAP ( Y => n_2424, IN1 => O_dup_1617_aIN);
delay_1977: DELAY
PORT MAP ( Y => O_dup_781_aOUT, IN1 => O_dup_781_aIN1);
and2_1978: AND2
PORT MAP ( Y => O_dup_781_aIN1, IN1 => n_2426, IN2 => n_2441);
or4_1979: OR4
PORT MAP ( Y => n_2426, IN1 => n_2427, IN2 => n_2430, IN3 => n_2434, IN4 => n_2438);
and2_1980: AND2
PORT MAP ( Y => n_2427, IN1 => n_2428, IN2 => n_2429);
inv_1981: INV
PORT MAP ( Y => n_2428, IN1 => O_dup_870_aOUT);
inv_1982: INV
PORT MAP ( Y => n_2429, IN1 => O_dup_873_aOUT);
and2_1983: AND2
PORT MAP ( Y => n_2430, IN1 => n_2431, IN2 => n_2433);
inv_1984: INV
PORT MAP ( Y => n_2431, IN1 => ix484_a4_dup_538_Q);
inv_1985: INV
PORT MAP ( Y => n_2433, IN1 => O_dup_873_aOUT);
and2_1986: AND2
PORT MAP ( Y => n_2434, IN1 => n_2435, IN2 => n_2437);
inv_1987: INV
PORT MAP ( Y => n_2435, IN1 => ix484_a0_dup_542_Q);
inv_1988: INV
PORT MAP ( Y => n_2437, IN1 => ix484_a4_dup_538_Q);
and2_1989: AND2
PORT MAP ( Y => n_2438, IN1 => n_2439, IN2 => n_2440);
inv_1990: INV
PORT MAP ( Y => n_2439, IN1 => ix484_a0_dup_542_Q);
inv_1991: INV
PORT MAP ( Y => n_2440, IN1 => O_dup_870_aOUT);
delay_1992: DELAY
PORT MAP ( Y => n_2441, IN1 => I1_dup_780_aIN);
dffe_1993: DFFE
PORT MAP ( D => ix484_a3_dup_539_aD, CLK => ix484_a3_dup_539_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a3_dup_539_aENA, Q => ix484_a3_dup_539_Q);
xor2_1994: XOR2
PORT MAP ( Y => ix484_a3_dup_539_aD, IN1 => n_2448, IN2 => n_2451);
or1_1995: OR1
PORT MAP ( Y => n_2448, IN1 => n_2449);
and1_1996: AND1
PORT MAP ( Y => n_2449, IN1 => n_2450);
delay_1997: DELAY
PORT MAP ( Y => n_2450, IN1 => data(14));
and1_1998: AND1
PORT MAP ( Y => n_2451, IN1 => gnd);
and1_1999: AND1
PORT MAP ( Y => n_2452, IN1 => n_2453);
delay_2000: DELAY
PORT MAP ( Y => n_2453, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2001: DELAY
PORT MAP ( Y => ix484_a3_dup_539_aCLK, IN1 => n_2452);
and1_2002: AND1
PORT MAP ( Y => ix484_a3_dup_539_aENA, IN1 => n_2456);
delay_2003: DELAY
PORT MAP ( Y => n_2456, IN1 => ix484_nx42_aOUT);
dffe_2004: DFFE
PORT MAP ( D => ix484_a6_dup_536_aD, CLK => ix484_a6_dup_536_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a6_dup_536_aENA, Q => ix484_a6_dup_536_Q);
xor2_2005: XOR2
PORT MAP ( Y => ix484_a6_dup_536_aD, IN1 => n_2463, IN2 => n_2466);
or1_2006: OR1
PORT MAP ( Y => n_2463, IN1 => n_2464);
and1_2007: AND1
PORT MAP ( Y => n_2464, IN1 => n_2465);
delay_2008: DELAY
PORT MAP ( Y => n_2465, IN1 => data(14));
and1_2009: AND1
PORT MAP ( Y => n_2466, IN1 => gnd);
and1_2010: AND1
PORT MAP ( Y => n_2467, IN1 => n_2468);
delay_2011: DELAY
PORT MAP ( Y => n_2468, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2012: DELAY
PORT MAP ( Y => ix484_a6_dup_536_aCLK, IN1 => n_2467);
and1_2013: AND1
PORT MAP ( Y => ix484_a6_dup_536_aENA, IN1 => n_2471);
delay_2014: DELAY
PORT MAP ( Y => n_2471, IN1 => ix484_nx39_aOUT);
dff_2015: DFF
PORT MAP ( D => instrregout13_aD, CLK => instrregout13_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout13_Q);
xor2_2016: XOR2
PORT MAP ( Y => instrregout13_aD, IN1 => n_2478, IN2 => n_2481);
or1_2017: OR1
PORT MAP ( Y => n_2478, IN1 => n_2479);
and1_2018: AND1
PORT MAP ( Y => n_2479, IN1 => n_2480);
delay_2019: DELAY
PORT MAP ( Y => n_2480, IN1 => data(13));
and1_2020: AND1
PORT MAP ( Y => n_2481, IN1 => gnd);
and1_2021: AND1
PORT MAP ( Y => n_2482, IN1 => n_2483);
delay_2022: DELAY
PORT MAP ( Y => n_2483, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_2023: DELAY
PORT MAP ( Y => instrregout13_aCLK, IN1 => n_2482);
dff_2024: DFF
PORT MAP ( D => instrregout14_aD, CLK => instrregout14_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout14_Q);
xor2_2025: XOR2
PORT MAP ( Y => instrregout14_aD, IN1 => n_2491, IN2 => n_2494);
or1_2026: OR1
PORT MAP ( Y => n_2491, IN1 => n_2492);
and1_2027: AND1
PORT MAP ( Y => n_2492, IN1 => n_2493);
delay_2028: DELAY
PORT MAP ( Y => n_2493, IN1 => data(14));
and1_2029: AND1
PORT MAP ( Y => n_2494, IN1 => gnd);
and1_2030: AND1
PORT MAP ( Y => n_2495, IN1 => n_2496);
delay_2031: DELAY
PORT MAP ( Y => n_2496, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_2032: DELAY
PORT MAP ( Y => instrregout14_aCLK, IN1 => n_2495);
dff_2033: DFF
PORT MAP ( D => con1_current_state18_aD, CLK => con1_current_state18_aCLK,
CLRN => con1_current_state18_aCLRN, PRN => vcc, Q => con1_current_state18_Q);
inv_2034: INV
PORT MAP ( Y => con1_current_state18_aCLRN, IN1 => reset);
xor2_2035: XOR2
PORT MAP ( Y => con1_current_state18_aD, IN1 => n_2505, IN2 => n_2508);
or1_2036: OR1
PORT MAP ( Y => n_2505, IN1 => n_2506);
and1_2037: AND1
PORT MAP ( Y => n_2506, IN1 => n_2507);
delay_2038: DELAY
PORT MAP ( Y => n_2507, IN1 => con1_current_state17_Q);
and1_2039: AND1
PORT MAP ( Y => n_2508, IN1 => gnd);
delay_2040: DELAY
PORT MAP ( Y => con1_current_state18_aCLK, IN1 => clock);
delay_2041: DELAY
PORT MAP ( Y => I0_dup_1065_aOUT, IN1 => I0_dup_1065_aIN);
xor2_2042: XOR2
PORT MAP ( Y => I0_dup_1065_aIN, IN1 => n_2512, IN2 => n_2527);
or4_2043: OR4
PORT MAP ( Y => n_2512, IN1 => n_2513, IN2 => n_2516, IN3 => n_2520, IN4 => n_2524);
and2_2044: AND2
PORT MAP ( Y => n_2513, IN1 => n_2514, IN2 => n_2515);
inv_2045: INV
PORT MAP ( Y => n_2514, IN1 => O_dup_888_aOUT);
inv_2046: INV
PORT MAP ( Y => n_2515, IN1 => O_dup_891_aOUT);
and2_2047: AND2
PORT MAP ( Y => n_2516, IN1 => n_2517, IN2 => n_2519);
inv_2048: INV
PORT MAP ( Y => n_2517, IN1 => ix484_a3_Q);
inv_2049: INV
PORT MAP ( Y => n_2519, IN1 => O_dup_891_aOUT);
and2_2050: AND2
PORT MAP ( Y => n_2520, IN1 => n_2521, IN2 => n_2523);
inv_2051: INV
PORT MAP ( Y => n_2521, IN1 => ix484_a6_Q);
inv_2052: INV
PORT MAP ( Y => n_2523, IN1 => ix484_a3_Q);
and2_2053: AND2
PORT MAP ( Y => n_2524, IN1 => n_2525, IN2 => n_2526);
inv_2054: INV
PORT MAP ( Y => n_2525, IN1 => ix484_a6_Q);
inv_2055: INV
PORT MAP ( Y => n_2526, IN1 => O_dup_888_aOUT);
and1_2056: AND1
PORT MAP ( Y => n_2527, IN1 => gnd);
delay_2057: DELAY
PORT MAP ( Y => O_dup_1067_aOUT, IN1 => O_dup_1067_aIN);
and2_2058: AND2
PORT MAP ( Y => O_dup_1067_aIN, IN1 => n_2530, IN2 => n_2545);
or4_2059: OR4
PORT MAP ( Y => n_2530, IN1 => n_2531, IN2 => n_2534, IN3 => n_2538, IN4 => n_2542);
and2_2060: AND2
PORT MAP ( Y => n_2531, IN1 => n_2532, IN2 => n_2533);
inv_2061: INV
PORT MAP ( Y => n_2532, IN1 => O_dup_882_aOUT);
inv_2062: INV
PORT MAP ( Y => n_2533, IN1 => O_dup_885_aOUT);
and2_2063: AND2
PORT MAP ( Y => n_2534, IN1 => n_2535, IN2 => n_2537);
inv_2064: INV
PORT MAP ( Y => n_2535, IN1 => ix484_a1_dup_533_Q);
inv_2065: INV
PORT MAP ( Y => n_2537, IN1 => O_dup_885_aOUT);
and2_2066: AND2
PORT MAP ( Y => n_2538, IN1 => n_2539, IN2 => n_2541);
inv_2067: INV
PORT MAP ( Y => n_2539, IN1 => ix484_a5_Q);
inv_2068: INV
PORT MAP ( Y => n_2541, IN1 => ix484_a1_dup_533_Q);
and2_2069: AND2
PORT MAP ( Y => n_2542, IN1 => n_2543, IN2 => n_2544);
inv_2070: INV
PORT MAP ( Y => n_2543, IN1 => ix484_a5_Q);
inv_2071: INV
PORT MAP ( Y => n_2544, IN1 => O_dup_882_aOUT);
delay_2072: DELAY
PORT MAP ( Y => n_2545, IN1 => I0_dup_1065_aIN);
delay_2073: DELAY
PORT MAP ( Y => O_dup_1609_aOUT, IN1 => O_dup_1609_aIN);
and2_2074: AND2
PORT MAP ( Y => O_dup_1609_aIN, IN1 => n_2548, IN2 => n_2563);
or4_2075: OR4
PORT MAP ( Y => n_2548, IN1 => n_2549, IN2 => n_2552, IN3 => n_2557, IN4 => n_2560);
and2_2076: AND2
PORT MAP ( Y => n_2549, IN1 => n_2550, IN2 => n_2551);
inv_2077: INV
PORT MAP ( Y => n_2550, IN1 => outregrd_aOUT);
delay_2078: DELAY
PORT MAP ( Y => n_2551, IN1 => n3_aOUT);
and2_2079: AND2
PORT MAP ( Y => n_2552, IN1 => n_2553, IN2 => n_2555);
inv_2080: INV
PORT MAP ( Y => n_2553, IN1 => outreg_val15_Q);
inv_2081: INV
PORT MAP ( Y => n_2555, IN1 => progcntr_val15_Q);
and2_2082: AND2
PORT MAP ( Y => n_2557, IN1 => n_2558, IN2 => n_2559);
inv_2083: INV
PORT MAP ( Y => n_2558, IN1 => progcntr_val15_Q);
inv_2084: INV
PORT MAP ( Y => n_2559, IN1 => outregrd_aOUT);
and2_2085: AND2
PORT MAP ( Y => n_2560, IN1 => n_2561, IN2 => n_2562);
inv_2086: INV
PORT MAP ( Y => n_2561, IN1 => outreg_val15_Q);
delay_2087: DELAY
PORT MAP ( Y => n_2562, IN1 => n3_aOUT);
delay_2088: DELAY
PORT MAP ( Y => n_2563, IN1 => O_dup_1067_aIN);
delay_2089: DELAY
PORT MAP ( Y => I1_dup_777_aOUT, IN1 => I1_dup_777_aIN);
and2_2090: AND2
PORT MAP ( Y => I1_dup_777_aIN, IN1 => n_2566, IN2 => n_2581);
or4_2091: OR4
PORT MAP ( Y => n_2566, IN1 => n_2567, IN2 => n_2570, IN3 => n_2574, IN4 => n_2578);
and2_2092: AND2
PORT MAP ( Y => n_2567, IN1 => n_2568, IN2 => n_2569);
inv_2093: INV
PORT MAP ( Y => n_2568, IN1 => O_dup_876_aOUT);
inv_2094: INV
PORT MAP ( Y => n_2569, IN1 => O_dup_879_aOUT);
and2_2095: AND2
PORT MAP ( Y => n_2570, IN1 => n_2571, IN2 => n_2573);
inv_2096: INV
PORT MAP ( Y => n_2571, IN1 => ix484_a2_dup_532_Q);
inv_2097: INV
PORT MAP ( Y => n_2573, IN1 => O_dup_879_aOUT);
and2_2098: AND2
PORT MAP ( Y => n_2574, IN1 => n_2575, IN2 => n_2577);
inv_2099: INV
PORT MAP ( Y => n_2575, IN1 => ix484_a7_Q);
inv_2100: INV
PORT MAP ( Y => n_2577, IN1 => ix484_a2_dup_532_Q);
and2_2101: AND2
PORT MAP ( Y => n_2578, IN1 => n_2579, IN2 => n_2580);
inv_2102: INV
PORT MAP ( Y => n_2579, IN1 => ix484_a7_Q);
inv_2103: INV
PORT MAP ( Y => n_2580, IN1 => O_dup_876_aOUT);
delay_2104: DELAY
PORT MAP ( Y => n_2581, IN1 => O_dup_1609_aIN);
delay_2105: DELAY
PORT MAP ( Y => O_dup_778_aOUT, IN1 => O_dup_778_aIN1);
and2_2106: AND2
PORT MAP ( Y => O_dup_778_aIN1, IN1 => n_2583, IN2 => n_2598);
or4_2107: OR4
PORT MAP ( Y => n_2583, IN1 => n_2584, IN2 => n_2587, IN3 => n_2591, IN4 => n_2595);
and2_2108: AND2
PORT MAP ( Y => n_2584, IN1 => n_2585, IN2 => n_2586);
inv_2109: INV
PORT MAP ( Y => n_2585, IN1 => O_dup_870_aOUT);
inv_2110: INV
PORT MAP ( Y => n_2586, IN1 => O_dup_873_aOUT);
and2_2111: AND2
PORT MAP ( Y => n_2587, IN1 => n_2588, IN2 => n_2590);
inv_2112: INV
PORT MAP ( Y => n_2588, IN1 => ix484_a4_Q);
inv_2113: INV
PORT MAP ( Y => n_2590, IN1 => O_dup_873_aOUT);
and2_2114: AND2
PORT MAP ( Y => n_2591, IN1 => n_2592, IN2 => n_2594);
inv_2115: INV
PORT MAP ( Y => n_2592, IN1 => ix484_a0_dup_534_Q);
inv_2116: INV
PORT MAP ( Y => n_2594, IN1 => ix484_a4_Q);
and2_2117: AND2
PORT MAP ( Y => n_2595, IN1 => n_2596, IN2 => n_2597);
inv_2118: INV
PORT MAP ( Y => n_2596, IN1 => ix484_a0_dup_534_Q);
inv_2119: INV
PORT MAP ( Y => n_2597, IN1 => O_dup_870_aOUT);
delay_2120: DELAY
PORT MAP ( Y => n_2598, IN1 => I1_dup_777_aIN);
dffe_2121: DFFE
PORT MAP ( D => ix484_a3_aD, CLK => ix484_a3_aCLK, CLRN => vcc, PRN => vcc,
ENA => ix484_a3_aENA, Q => ix484_a3_Q);
xor2_2122: XOR2
PORT MAP ( Y => ix484_a3_aD, IN1 => n_2605, IN2 => n_2608);
or1_2123: OR1
PORT MAP ( Y => n_2605, IN1 => n_2606);
and1_2124: AND1
PORT MAP ( Y => n_2606, IN1 => n_2607);
delay_2125: DELAY
PORT MAP ( Y => n_2607, IN1 => data(15));
and1_2126: AND1
PORT MAP ( Y => n_2608, IN1 => gnd);
and1_2127: AND1
PORT MAP ( Y => n_2609, IN1 => n_2610);
delay_2128: DELAY
PORT MAP ( Y => n_2610, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2129: DELAY
PORT MAP ( Y => ix484_a3_aCLK, IN1 => n_2609);
and1_2130: AND1
PORT MAP ( Y => ix484_a3_aENA, IN1 => n_2613);
delay_2131: DELAY
PORT MAP ( Y => n_2613, IN1 => ix484_nx42_aOUT);
dffe_2132: DFFE
PORT MAP ( D => ix484_a6_aD, CLK => ix484_a6_aCLK, CLRN => vcc, PRN => vcc,
ENA => ix484_a6_aENA, Q => ix484_a6_Q);
xor2_2133: XOR2
PORT MAP ( Y => ix484_a6_aD, IN1 => n_2620, IN2 => n_2623);
or1_2134: OR1
PORT MAP ( Y => n_2620, IN1 => n_2621);
and1_2135: AND1
PORT MAP ( Y => n_2621, IN1 => n_2622);
delay_2136: DELAY
PORT MAP ( Y => n_2622, IN1 => data(15));
and1_2137: AND1
PORT MAP ( Y => n_2623, IN1 => gnd);
and1_2138: AND1
PORT MAP ( Y => n_2624, IN1 => n_2625);
delay_2139: DELAY
PORT MAP ( Y => n_2625, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2140: DELAY
PORT MAP ( Y => ix484_a6_aCLK, IN1 => n_2624);
and1_2141: AND1
PORT MAP ( Y => ix484_a6_aENA, IN1 => n_2628);
delay_2142: DELAY
PORT MAP ( Y => n_2628, IN1 => ix484_nx39_aOUT);
dff_2143: DFF
PORT MAP ( D => opreg_val0_aD, CLK => opreg_val0_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val0_Q);
xor2_2144: XOR2
PORT MAP ( Y => opreg_val0_aD, IN1 => n_2635, IN2 => n_2638);
or1_2145: OR1
PORT MAP ( Y => n_2635, IN1 => n_2636);
and1_2146: AND1
PORT MAP ( Y => n_2636, IN1 => n_2637);
delay_2147: DELAY
PORT MAP ( Y => n_2637, IN1 => data(0));
and1_2148: AND1
PORT MAP ( Y => n_2638, IN1 => gnd);
and1_2149: AND1
PORT MAP ( Y => n_2639, IN1 => n_2640);
delay_2150: DELAY
PORT MAP ( Y => n_2640, IN1 => opregwr_Q);
delay_2151: DELAY
PORT MAP ( Y => opreg_val0_aCLK, IN1 => n_2639);
delay_2152: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int1_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int1_aIN);
xor2_2153: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int1_aIN, IN1 => n_2644, IN2 => n_2649);
or2_2154: OR2
PORT MAP ( Y => n_2644, IN1 => n_2645, IN2 => n_2647);
and1_2155: AND1
PORT MAP ( Y => n_2645, IN1 => n_2646);
inv_2156: INV
PORT MAP ( Y => n_2646, IN1 => opreg_val0_Q);
and1_2157: AND1
PORT MAP ( Y => n_2647, IN1 => n_2648);
delay_2158: DELAY
PORT MAP ( Y => n_2648, IN1 => data(0));
and1_2159: AND1
PORT MAP ( Y => n_2649, IN1 => gnd);
dff_2160: DFF
PORT MAP ( D => opreg_val1_aD, CLK => opreg_val1_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val1_Q);
xor2_2161: XOR2
PORT MAP ( Y => opreg_val1_aD, IN1 => n_2656, IN2 => n_2659);
or1_2162: OR1
PORT MAP ( Y => n_2656, IN1 => n_2657);
and1_2163: AND1
PORT MAP ( Y => n_2657, IN1 => n_2658);
delay_2164: DELAY
PORT MAP ( Y => n_2658, IN1 => data(1));
and1_2165: AND1
PORT MAP ( Y => n_2659, IN1 => gnd);
and1_2166: AND1
PORT MAP ( Y => n_2660, IN1 => n_2661);
delay_2167: DELAY
PORT MAP ( Y => n_2661, IN1 => opregwr_Q);
delay_2168: DELAY
PORT MAP ( Y => opreg_val1_aCLK, IN1 => n_2660);
delay_2169: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int2_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int2_aIN);
xor2_2170: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int2_aIN, IN1 => n_2665, IN2 => n_2675);
or3_2171: OR3
PORT MAP ( Y => n_2665, IN1 => n_2666, IN2 => n_2669, IN3 => n_2672);
and2_2172: AND2
PORT MAP ( Y => n_2666, IN1 => n_2667, IN2 => n_2668);
delay_2173: DELAY
PORT MAP ( Y => n_2667, IN1 => comp1_modgen_56_l1_l0_c_int1_aOUT);
delay_2174: DELAY
PORT MAP ( Y => n_2668, IN1 => data(1));
and2_2175: AND2
PORT MAP ( Y => n_2669, IN1 => n_2670, IN2 => n_2671);
inv_2176: INV
PORT MAP ( Y => n_2670, IN1 => opreg_val1_Q);
delay_2177: DELAY
PORT MAP ( Y => n_2671, IN1 => data(1));
and2_2178: AND2
PORT MAP ( Y => n_2672, IN1 => n_2673, IN2 => n_2674);
inv_2179: INV
PORT MAP ( Y => n_2673, IN1 => opreg_val1_Q);
delay_2180: DELAY
PORT MAP ( Y => n_2674, IN1 => comp1_modgen_56_l1_l0_c_int1_aOUT);
and1_2181: AND1
PORT MAP ( Y => n_2675, IN1 => gnd);
dff_2182: DFF
PORT MAP ( D => opreg_val2_aD, CLK => opreg_val2_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val2_Q);
xor2_2183: XOR2
PORT MAP ( Y => opreg_val2_aD, IN1 => n_2682, IN2 => n_2685);
or1_2184: OR1
PORT MAP ( Y => n_2682, IN1 => n_2683);
and1_2185: AND1
PORT MAP ( Y => n_2683, IN1 => n_2684);
delay_2186: DELAY
PORT MAP ( Y => n_2684, IN1 => data(2));
and1_2187: AND1
PORT MAP ( Y => n_2685, IN1 => gnd);
and1_2188: AND1
PORT MAP ( Y => n_2686, IN1 => n_2687);
delay_2189: DELAY
PORT MAP ( Y => n_2687, IN1 => opregwr_Q);
delay_2190: DELAY
PORT MAP ( Y => opreg_val2_aCLK, IN1 => n_2686);
delay_2191: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int3_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int3_aIN);
xor2_2192: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int3_aIN, IN1 => n_2691, IN2 => n_2701);
or3_2193: OR3
PORT MAP ( Y => n_2691, IN1 => n_2692, IN2 => n_2695, IN3 => n_2698);
and2_2194: AND2
PORT MAP ( Y => n_2692, IN1 => n_2693, IN2 => n_2694);
delay_2195: DELAY
PORT MAP ( Y => n_2693, IN1 => comp1_modgen_56_l1_l0_c_int2_aOUT);
delay_2196: DELAY
PORT MAP ( Y => n_2694, IN1 => data(2));
and2_2197: AND2
PORT MAP ( Y => n_2695, IN1 => n_2696, IN2 => n_2697);
inv_2198: INV
PORT MAP ( Y => n_2696, IN1 => opreg_val2_Q);
delay_2199: DELAY
PORT MAP ( Y => n_2697, IN1 => data(2));
and2_2200: AND2
PORT MAP ( Y => n_2698, IN1 => n_2699, IN2 => n_2700);
inv_2201: INV
PORT MAP ( Y => n_2699, IN1 => opreg_val2_Q);
delay_2202: DELAY
PORT MAP ( Y => n_2700, IN1 => comp1_modgen_56_l1_l0_c_int2_aOUT);
and1_2203: AND1
PORT MAP ( Y => n_2701, IN1 => gnd);
dff_2204: DFF
PORT MAP ( D => opreg_val3_aD, CLK => opreg_val3_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val3_Q);
xor2_2205: XOR2
PORT MAP ( Y => opreg_val3_aD, IN1 => n_2708, IN2 => n_2711);
or1_2206: OR1
PORT MAP ( Y => n_2708, IN1 => n_2709);
and1_2207: AND1
PORT MAP ( Y => n_2709, IN1 => n_2710);
delay_2208: DELAY
PORT MAP ( Y => n_2710, IN1 => data(3));
and1_2209: AND1
PORT MAP ( Y => n_2711, IN1 => gnd);
and1_2210: AND1
PORT MAP ( Y => n_2712, IN1 => n_2713);
delay_2211: DELAY
PORT MAP ( Y => n_2713, IN1 => opregwr_Q);
delay_2212: DELAY
PORT MAP ( Y => opreg_val3_aCLK, IN1 => n_2712);
delay_2213: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int4_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int4_aIN);
xor2_2214: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int4_aIN, IN1 => n_2717, IN2 => n_2727);
or3_2215: OR3
PORT MAP ( Y => n_2717, IN1 => n_2718, IN2 => n_2721, IN3 => n_2724);
and2_2216: AND2
PORT MAP ( Y => n_2718, IN1 => n_2719, IN2 => n_2720);
delay_2217: DELAY
PORT MAP ( Y => n_2719, IN1 => comp1_modgen_56_l1_l0_c_int3_aOUT);
delay_2218: DELAY
PORT MAP ( Y => n_2720, IN1 => data(3));
and2_2219: AND2
PORT MAP ( Y => n_2721, IN1 => n_2722, IN2 => n_2723);
inv_2220: INV
PORT MAP ( Y => n_2722, IN1 => opreg_val3_Q);
delay_2221: DELAY
PORT MAP ( Y => n_2723, IN1 => data(3));
and2_2222: AND2
PORT MAP ( Y => n_2724, IN1 => n_2725, IN2 => n_2726);
inv_2223: INV
PORT MAP ( Y => n_2725, IN1 => opreg_val3_Q);
delay_2224: DELAY
PORT MAP ( Y => n_2726, IN1 => comp1_modgen_56_l1_l0_c_int3_aOUT);
and1_2225: AND1
PORT MAP ( Y => n_2727, IN1 => gnd);
dff_2226: DFF
PORT MAP ( D => opreg_val4_aD, CLK => opreg_val4_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val4_Q);
xor2_2227: XOR2
PORT MAP ( Y => opreg_val4_aD, IN1 => n_2734, IN2 => n_2737);
or1_2228: OR1
PORT MAP ( Y => n_2734, IN1 => n_2735);
and1_2229: AND1
PORT MAP ( Y => n_2735, IN1 => n_2736);
delay_2230: DELAY
PORT MAP ( Y => n_2736, IN1 => data(4));
and1_2231: AND1
PORT MAP ( Y => n_2737, IN1 => gnd);
and1_2232: AND1
PORT MAP ( Y => n_2738, IN1 => n_2739);
delay_2233: DELAY
PORT MAP ( Y => n_2739, IN1 => opregwr_Q);
delay_2234: DELAY
PORT MAP ( Y => opreg_val4_aCLK, IN1 => n_2738);
delay_2235: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int5_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int5_aIN);
xor2_2236: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int5_aIN, IN1 => n_2743, IN2 => n_2753);
or3_2237: OR3
PORT MAP ( Y => n_2743, IN1 => n_2744, IN2 => n_2747, IN3 => n_2750);
and2_2238: AND2
PORT MAP ( Y => n_2744, IN1 => n_2745, IN2 => n_2746);
delay_2239: DELAY
PORT MAP ( Y => n_2745, IN1 => comp1_modgen_56_l1_l0_c_int4_aOUT);
delay_2240: DELAY
PORT MAP ( Y => n_2746, IN1 => data(4));
and2_2241: AND2
PORT MAP ( Y => n_2747, IN1 => n_2748, IN2 => n_2749);
inv_2242: INV
PORT MAP ( Y => n_2748, IN1 => opreg_val4_Q);
delay_2243: DELAY
PORT MAP ( Y => n_2749, IN1 => data(4));
and2_2244: AND2
PORT MAP ( Y => n_2750, IN1 => n_2751, IN2 => n_2752);
inv_2245: INV
PORT MAP ( Y => n_2751, IN1 => opreg_val4_Q);
delay_2246: DELAY
PORT MAP ( Y => n_2752, IN1 => comp1_modgen_56_l1_l0_c_int4_aOUT);
and1_2247: AND1
PORT MAP ( Y => n_2753, IN1 => gnd);
dff_2248: DFF
PORT MAP ( D => opreg_val5_aD, CLK => opreg_val5_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val5_Q);
xor2_2249: XOR2
PORT MAP ( Y => opreg_val5_aD, IN1 => n_2760, IN2 => n_2763);
or1_2250: OR1
PORT MAP ( Y => n_2760, IN1 => n_2761);
and1_2251: AND1
PORT MAP ( Y => n_2761, IN1 => n_2762);
delay_2252: DELAY
PORT MAP ( Y => n_2762, IN1 => data(5));
and1_2253: AND1
PORT MAP ( Y => n_2763, IN1 => gnd);
and1_2254: AND1
PORT MAP ( Y => n_2764, IN1 => n_2765);
delay_2255: DELAY
PORT MAP ( Y => n_2765, IN1 => opregwr_Q);
delay_2256: DELAY
PORT MAP ( Y => opreg_val5_aCLK, IN1 => n_2764);
delay_2257: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int6_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int6_aIN);
xor2_2258: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int6_aIN, IN1 => n_2769, IN2 => n_2779);
or3_2259: OR3
PORT MAP ( Y => n_2769, IN1 => n_2770, IN2 => n_2773, IN3 => n_2776);
and2_2260: AND2
PORT MAP ( Y => n_2770, IN1 => n_2771, IN2 => n_2772);
delay_2261: DELAY
PORT MAP ( Y => n_2771, IN1 => comp1_modgen_56_l1_l0_c_int5_aOUT);
delay_2262: DELAY
PORT MAP ( Y => n_2772, IN1 => data(5));
and2_2263: AND2
PORT MAP ( Y => n_2773, IN1 => n_2774, IN2 => n_2775);
inv_2264: INV
PORT MAP ( Y => n_2774, IN1 => opreg_val5_Q);
delay_2265: DELAY
PORT MAP ( Y => n_2775, IN1 => data(5));
and2_2266: AND2
PORT MAP ( Y => n_2776, IN1 => n_2777, IN2 => n_2778);
inv_2267: INV
PORT MAP ( Y => n_2777, IN1 => opreg_val5_Q);
delay_2268: DELAY
PORT MAP ( Y => n_2778, IN1 => comp1_modgen_56_l1_l0_c_int5_aOUT);
and1_2269: AND1
PORT MAP ( Y => n_2779, IN1 => gnd);
dff_2270: DFF
PORT MAP ( D => opreg_val6_aD, CLK => opreg_val6_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val6_Q);
xor2_2271: XOR2
PORT MAP ( Y => opreg_val6_aD, IN1 => n_2786, IN2 => n_2789);
or1_2272: OR1
PORT MAP ( Y => n_2786, IN1 => n_2787);
and1_2273: AND1
PORT MAP ( Y => n_2787, IN1 => n_2788);
delay_2274: DELAY
PORT MAP ( Y => n_2788, IN1 => data(6));
and1_2275: AND1
PORT MAP ( Y => n_2789, IN1 => gnd);
and1_2276: AND1
PORT MAP ( Y => n_2790, IN1 => n_2791);
delay_2277: DELAY
PORT MAP ( Y => n_2791, IN1 => opregwr_Q);
delay_2278: DELAY
PORT MAP ( Y => opreg_val6_aCLK, IN1 => n_2790);
delay_2279: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int7_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int7_aIN);
xor2_2280: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int7_aIN, IN1 => n_2795, IN2 => n_2805);
or3_2281: OR3
PORT MAP ( Y => n_2795, IN1 => n_2796, IN2 => n_2799, IN3 => n_2802);
and2_2282: AND2
PORT MAP ( Y => n_2796, IN1 => n_2797, IN2 => n_2798);
delay_2283: DELAY
PORT MAP ( Y => n_2797, IN1 => comp1_modgen_56_l1_l0_c_int6_aOUT);
delay_2284: DELAY
PORT MAP ( Y => n_2798, IN1 => data(6));
and2_2285: AND2
PORT MAP ( Y => n_2799, IN1 => n_2800, IN2 => n_2801);
inv_2286: INV
PORT MAP ( Y => n_2800, IN1 => opreg_val6_Q);
delay_2287: DELAY
PORT MAP ( Y => n_2801, IN1 => data(6));
and2_2288: AND2
PORT MAP ( Y => n_2802, IN1 => n_2803, IN2 => n_2804);
inv_2289: INV
PORT MAP ( Y => n_2803, IN1 => opreg_val6_Q);
delay_2290: DELAY
PORT MAP ( Y => n_2804, IN1 => comp1_modgen_56_l1_l0_c_int6_aOUT);
and1_2291: AND1
PORT MAP ( Y => n_2805, IN1 => gnd);
dff_2292: DFF
PORT MAP ( D => opreg_val7_aD, CLK => opreg_val7_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val7_Q);
xor2_2293: XOR2
PORT MAP ( Y => opreg_val7_aD, IN1 => n_2812, IN2 => n_2815);
or1_2294: OR1
PORT MAP ( Y => n_2812, IN1 => n_2813);
and1_2295: AND1
PORT MAP ( Y => n_2813, IN1 => n_2814);
delay_2296: DELAY
PORT MAP ( Y => n_2814, IN1 => data(7));
and1_2297: AND1
PORT MAP ( Y => n_2815, IN1 => gnd);
and1_2298: AND1
PORT MAP ( Y => n_2816, IN1 => n_2817);
delay_2299: DELAY
PORT MAP ( Y => n_2817, IN1 => opregwr_Q);
delay_2300: DELAY
PORT MAP ( Y => opreg_val7_aCLK, IN1 => n_2816);
delay_2301: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int8_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int8_aIN);
xor2_2302: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int8_aIN, IN1 => n_2821, IN2 => n_2831);
or3_2303: OR3
PORT MAP ( Y => n_2821, IN1 => n_2822, IN2 => n_2825, IN3 => n_2828);
and2_2304: AND2
PORT MAP ( Y => n_2822, IN1 => n_2823, IN2 => n_2824);
delay_2305: DELAY
PORT MAP ( Y => n_2823, IN1 => comp1_modgen_56_l1_l0_c_int7_aOUT);
delay_2306: DELAY
PORT MAP ( Y => n_2824, IN1 => data(7));
and2_2307: AND2
PORT MAP ( Y => n_2825, IN1 => n_2826, IN2 => n_2827);
inv_2308: INV
PORT MAP ( Y => n_2826, IN1 => opreg_val7_Q);
delay_2309: DELAY
PORT MAP ( Y => n_2827, IN1 => data(7));
and2_2310: AND2
PORT MAP ( Y => n_2828, IN1 => n_2829, IN2 => n_2830);
inv_2311: INV
PORT MAP ( Y => n_2829, IN1 => opreg_val7_Q);
delay_2312: DELAY
PORT MAP ( Y => n_2830, IN1 => comp1_modgen_56_l1_l0_c_int7_aOUT);
and1_2313: AND1
PORT MAP ( Y => n_2831, IN1 => gnd);
dff_2314: DFF
PORT MAP ( D => opreg_val8_aD, CLK => opreg_val8_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val8_Q);
xor2_2315: XOR2
PORT MAP ( Y => opreg_val8_aD, IN1 => n_2838, IN2 => n_2841);
or1_2316: OR1
PORT MAP ( Y => n_2838, IN1 => n_2839);
and1_2317: AND1
PORT MAP ( Y => n_2839, IN1 => n_2840);
delay_2318: DELAY
PORT MAP ( Y => n_2840, IN1 => data(8));
and1_2319: AND1
PORT MAP ( Y => n_2841, IN1 => gnd);
and1_2320: AND1
PORT MAP ( Y => n_2842, IN1 => n_2843);
delay_2321: DELAY
PORT MAP ( Y => n_2843, IN1 => opregwr_Q);
delay_2322: DELAY
PORT MAP ( Y => opreg_val8_aCLK, IN1 => n_2842);
delay_2323: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int9_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int9_aIN);
xor2_2324: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int9_aIN, IN1 => n_2847, IN2 => n_2857);
or3_2325: OR3
PORT MAP ( Y => n_2847, IN1 => n_2848, IN2 => n_2851, IN3 => n_2854);
and2_2326: AND2
PORT MAP ( Y => n_2848, IN1 => n_2849, IN2 => n_2850);
delay_2327: DELAY
PORT MAP ( Y => n_2849, IN1 => comp1_modgen_56_l1_l0_c_int8_aOUT);
delay_2328: DELAY
PORT MAP ( Y => n_2850, IN1 => data(8));
and2_2329: AND2
PORT MAP ( Y => n_2851, IN1 => n_2852, IN2 => n_2853);
inv_2330: INV
PORT MAP ( Y => n_2852, IN1 => opreg_val8_Q);
delay_2331: DELAY
PORT MAP ( Y => n_2853, IN1 => data(8));
and2_2332: AND2
PORT MAP ( Y => n_2854, IN1 => n_2855, IN2 => n_2856);
inv_2333: INV
PORT MAP ( Y => n_2855, IN1 => opreg_val8_Q);
delay_2334: DELAY
PORT MAP ( Y => n_2856, IN1 => comp1_modgen_56_l1_l0_c_int8_aOUT);
and1_2335: AND1
PORT MAP ( Y => n_2857, IN1 => gnd);
dff_2336: DFF
PORT MAP ( D => opreg_val9_aD, CLK => opreg_val9_aCLK, CLRN => vcc, PRN => vcc,
Q => opreg_val9_Q);
xor2_2337: XOR2
PORT MAP ( Y => opreg_val9_aD, IN1 => n_2864, IN2 => n_2867);
or1_2338: OR1
PORT MAP ( Y => n_2864, IN1 => n_2865);
and1_2339: AND1
PORT MAP ( Y => n_2865, IN1 => n_2866);
delay_2340: DELAY
PORT MAP ( Y => n_2866, IN1 => data(9));
and1_2341: AND1
PORT MAP ( Y => n_2867, IN1 => gnd);
and1_2342: AND1
PORT MAP ( Y => n_2868, IN1 => n_2869);
delay_2343: DELAY
PORT MAP ( Y => n_2869, IN1 => opregwr_Q);
delay_2344: DELAY
PORT MAP ( Y => opreg_val9_aCLK, IN1 => n_2868);
delay_2345: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int10_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int10_aIN);
xor2_2346: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int10_aIN, IN1 => n_2873, IN2 => n_2883);
or3_2347: OR3
PORT MAP ( Y => n_2873, IN1 => n_2874, IN2 => n_2877, IN3 => n_2880);
and2_2348: AND2
PORT MAP ( Y => n_2874, IN1 => n_2875, IN2 => n_2876);
delay_2349: DELAY
PORT MAP ( Y => n_2875, IN1 => comp1_modgen_56_l1_l0_c_int9_aOUT);
delay_2350: DELAY
PORT MAP ( Y => n_2876, IN1 => data(9));
and2_2351: AND2
PORT MAP ( Y => n_2877, IN1 => n_2878, IN2 => n_2879);
inv_2352: INV
PORT MAP ( Y => n_2878, IN1 => opreg_val9_Q);
delay_2353: DELAY
PORT MAP ( Y => n_2879, IN1 => data(9));
and2_2354: AND2
PORT MAP ( Y => n_2880, IN1 => n_2881, IN2 => n_2882);
inv_2355: INV
PORT MAP ( Y => n_2881, IN1 => opreg_val9_Q);
delay_2356: DELAY
PORT MAP ( Y => n_2882, IN1 => comp1_modgen_56_l1_l0_c_int9_aOUT);
and1_2357: AND1
PORT MAP ( Y => n_2883, IN1 => gnd);
dff_2358: DFF
PORT MAP ( D => opreg_val10_aD, CLK => opreg_val10_aCLK, CLRN => vcc,
PRN => vcc, Q => opreg_val10_Q);
xor2_2359: XOR2
PORT MAP ( Y => opreg_val10_aD, IN1 => n_2890, IN2 => n_2893);
or1_2360: OR1
PORT MAP ( Y => n_2890, IN1 => n_2891);
and1_2361: AND1
PORT MAP ( Y => n_2891, IN1 => n_2892);
delay_2362: DELAY
PORT MAP ( Y => n_2892, IN1 => data(10));
and1_2363: AND1
PORT MAP ( Y => n_2893, IN1 => gnd);
and1_2364: AND1
PORT MAP ( Y => n_2894, IN1 => n_2895);
delay_2365: DELAY
PORT MAP ( Y => n_2895, IN1 => opregwr_Q);
delay_2366: DELAY
PORT MAP ( Y => opreg_val10_aCLK, IN1 => n_2894);
delay_2367: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int11_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int11_aIN);
xor2_2368: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int11_aIN, IN1 => n_2899, IN2 => n_2909);
or3_2369: OR3
PORT MAP ( Y => n_2899, IN1 => n_2900, IN2 => n_2903, IN3 => n_2906);
and2_2370: AND2
PORT MAP ( Y => n_2900, IN1 => n_2901, IN2 => n_2902);
delay_2371: DELAY
PORT MAP ( Y => n_2901, IN1 => comp1_modgen_56_l1_l0_c_int10_aOUT);
delay_2372: DELAY
PORT MAP ( Y => n_2902, IN1 => data(10));
and2_2373: AND2
PORT MAP ( Y => n_2903, IN1 => n_2904, IN2 => n_2905);
inv_2374: INV
PORT MAP ( Y => n_2904, IN1 => opreg_val10_Q);
delay_2375: DELAY
PORT MAP ( Y => n_2905, IN1 => data(10));
and2_2376: AND2
PORT MAP ( Y => n_2906, IN1 => n_2907, IN2 => n_2908);
inv_2377: INV
PORT MAP ( Y => n_2907, IN1 => opreg_val10_Q);
delay_2378: DELAY
PORT MAP ( Y => n_2908, IN1 => comp1_modgen_56_l1_l0_c_int10_aOUT);
and1_2379: AND1
PORT MAP ( Y => n_2909, IN1 => gnd);
dff_2380: DFF
PORT MAP ( D => opreg_val11_aD, CLK => opreg_val11_aCLK, CLRN => vcc,
PRN => vcc, Q => opreg_val11_Q);
xor2_2381: XOR2
PORT MAP ( Y => opreg_val11_aD, IN1 => n_2916, IN2 => n_2919);
or1_2382: OR1
PORT MAP ( Y => n_2916, IN1 => n_2917);
and1_2383: AND1
PORT MAP ( Y => n_2917, IN1 => n_2918);
delay_2384: DELAY
PORT MAP ( Y => n_2918, IN1 => data(11));
and1_2385: AND1
PORT MAP ( Y => n_2919, IN1 => gnd);
and1_2386: AND1
PORT MAP ( Y => n_2920, IN1 => n_2921);
delay_2387: DELAY
PORT MAP ( Y => n_2921, IN1 => opregwr_Q);
delay_2388: DELAY
PORT MAP ( Y => opreg_val11_aCLK, IN1 => n_2920);
delay_2389: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int12_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int12_aIN);
xor2_2390: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int12_aIN, IN1 => n_2925, IN2 => n_2935);
or3_2391: OR3
PORT MAP ( Y => n_2925, IN1 => n_2926, IN2 => n_2929, IN3 => n_2932);
and2_2392: AND2
PORT MAP ( Y => n_2926, IN1 => n_2927, IN2 => n_2928);
delay_2393: DELAY
PORT MAP ( Y => n_2927, IN1 => comp1_modgen_56_l1_l0_c_int11_aOUT);
delay_2394: DELAY
PORT MAP ( Y => n_2928, IN1 => data(11));
and2_2395: AND2
PORT MAP ( Y => n_2929, IN1 => n_2930, IN2 => n_2931);
inv_2396: INV
PORT MAP ( Y => n_2930, IN1 => opreg_val11_Q);
delay_2397: DELAY
PORT MAP ( Y => n_2931, IN1 => data(11));
and2_2398: AND2
PORT MAP ( Y => n_2932, IN1 => n_2933, IN2 => n_2934);
inv_2399: INV
PORT MAP ( Y => n_2933, IN1 => opreg_val11_Q);
delay_2400: DELAY
PORT MAP ( Y => n_2934, IN1 => comp1_modgen_56_l1_l0_c_int11_aOUT);
and1_2401: AND1
PORT MAP ( Y => n_2935, IN1 => gnd);
dff_2402: DFF
PORT MAP ( D => opreg_val12_aD, CLK => opreg_val12_aCLK, CLRN => vcc,
PRN => vcc, Q => opreg_val12_Q);
xor2_2403: XOR2
PORT MAP ( Y => opreg_val12_aD, IN1 => n_2942, IN2 => n_2945);
or1_2404: OR1
PORT MAP ( Y => n_2942, IN1 => n_2943);
and1_2405: AND1
PORT MAP ( Y => n_2943, IN1 => n_2944);
delay_2406: DELAY
PORT MAP ( Y => n_2944, IN1 => data(12));
and1_2407: AND1
PORT MAP ( Y => n_2945, IN1 => gnd);
and1_2408: AND1
PORT MAP ( Y => n_2946, IN1 => n_2947);
delay_2409: DELAY
PORT MAP ( Y => n_2947, IN1 => opregwr_Q);
delay_2410: DELAY
PORT MAP ( Y => opreg_val12_aCLK, IN1 => n_2946);
delay_2411: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int13_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int13_aIN);
xor2_2412: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int13_aIN, IN1 => n_2951, IN2 => n_2961);
or3_2413: OR3
PORT MAP ( Y => n_2951, IN1 => n_2952, IN2 => n_2955, IN3 => n_2958);
and2_2414: AND2
PORT MAP ( Y => n_2952, IN1 => n_2953, IN2 => n_2954);
delay_2415: DELAY
PORT MAP ( Y => n_2953, IN1 => comp1_modgen_56_l1_l0_c_int12_aOUT);
delay_2416: DELAY
PORT MAP ( Y => n_2954, IN1 => data(12));
and2_2417: AND2
PORT MAP ( Y => n_2955, IN1 => n_2956, IN2 => n_2957);
inv_2418: INV
PORT MAP ( Y => n_2956, IN1 => opreg_val12_Q);
delay_2419: DELAY
PORT MAP ( Y => n_2957, IN1 => data(12));
and2_2420: AND2
PORT MAP ( Y => n_2958, IN1 => n_2959, IN2 => n_2960);
inv_2421: INV
PORT MAP ( Y => n_2959, IN1 => opreg_val12_Q);
delay_2422: DELAY
PORT MAP ( Y => n_2960, IN1 => comp1_modgen_56_l1_l0_c_int12_aOUT);
and1_2423: AND1
PORT MAP ( Y => n_2961, IN1 => gnd);
dff_2424: DFF
PORT MAP ( D => opreg_val13_aD, CLK => opreg_val13_aCLK, CLRN => vcc,
PRN => vcc, Q => opreg_val13_Q);
xor2_2425: XOR2
PORT MAP ( Y => opreg_val13_aD, IN1 => n_2968, IN2 => n_2971);
or1_2426: OR1
PORT MAP ( Y => n_2968, IN1 => n_2969);
and1_2427: AND1
PORT MAP ( Y => n_2969, IN1 => n_2970);
delay_2428: DELAY
PORT MAP ( Y => n_2970, IN1 => data(13));
and1_2429: AND1
PORT MAP ( Y => n_2971, IN1 => gnd);
and1_2430: AND1
PORT MAP ( Y => n_2972, IN1 => n_2973);
delay_2431: DELAY
PORT MAP ( Y => n_2973, IN1 => opregwr_Q);
delay_2432: DELAY
PORT MAP ( Y => opreg_val13_aCLK, IN1 => n_2972);
delay_2433: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int14_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int14_aIN);
xor2_2434: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int14_aIN, IN1 => n_2977, IN2 => n_2987);
or3_2435: OR3
PORT MAP ( Y => n_2977, IN1 => n_2978, IN2 => n_2981, IN3 => n_2984);
and2_2436: AND2
PORT MAP ( Y => n_2978, IN1 => n_2979, IN2 => n_2980);
delay_2437: DELAY
PORT MAP ( Y => n_2979, IN1 => comp1_modgen_56_l1_l0_c_int13_aOUT);
delay_2438: DELAY
PORT MAP ( Y => n_2980, IN1 => data(13));
and2_2439: AND2
PORT MAP ( Y => n_2981, IN1 => n_2982, IN2 => n_2983);
inv_2440: INV
PORT MAP ( Y => n_2982, IN1 => opreg_val13_Q);
delay_2441: DELAY
PORT MAP ( Y => n_2983, IN1 => data(13));
and2_2442: AND2
PORT MAP ( Y => n_2984, IN1 => n_2985, IN2 => n_2986);
inv_2443: INV
PORT MAP ( Y => n_2985, IN1 => opreg_val13_Q);
delay_2444: DELAY
PORT MAP ( Y => n_2986, IN1 => comp1_modgen_56_l1_l0_c_int13_aOUT);
and1_2445: AND1
PORT MAP ( Y => n_2987, IN1 => gnd);
dff_2446: DFF
PORT MAP ( D => opreg_val14_aD, CLK => opreg_val14_aCLK, CLRN => vcc,
PRN => vcc, Q => opreg_val14_Q);
xor2_2447: XOR2
PORT MAP ( Y => opreg_val14_aD, IN1 => n_2994, IN2 => n_2997);
or1_2448: OR1
PORT MAP ( Y => n_2994, IN1 => n_2995);
and1_2449: AND1
PORT MAP ( Y => n_2995, IN1 => n_2996);
delay_2450: DELAY
PORT MAP ( Y => n_2996, IN1 => data(14));
and1_2451: AND1
PORT MAP ( Y => n_2997, IN1 => gnd);
and1_2452: AND1
PORT MAP ( Y => n_2998, IN1 => n_2999);
delay_2453: DELAY
PORT MAP ( Y => n_2999, IN1 => opregwr_Q);
delay_2454: DELAY
PORT MAP ( Y => opreg_val14_aCLK, IN1 => n_2998);
delay_2455: DELAY
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int15_aOUT, IN1 => comp1_modgen_56_l1_l0_c_int15_aIN);
xor2_2456: XOR2
PORT MAP ( Y => comp1_modgen_56_l1_l0_c_int15_aIN, IN1 => n_3003, IN2 => n_3013);
or3_2457: OR3
PORT MAP ( Y => n_3003, IN1 => n_3004, IN2 => n_3007, IN3 => n_3010);
and2_2458: AND2
PORT MAP ( Y => n_3004, IN1 => n_3005, IN2 => n_3006);
delay_2459: DELAY
PORT MAP ( Y => n_3005, IN1 => comp1_modgen_56_l1_l0_c_int14_aOUT);
delay_2460: DELAY
PORT MAP ( Y => n_3006, IN1 => data(14));
and2_2461: AND2
PORT MAP ( Y => n_3007, IN1 => n_3008, IN2 => n_3009);
inv_2462: INV
PORT MAP ( Y => n_3008, IN1 => opreg_val14_Q);
delay_2463: DELAY
PORT MAP ( Y => n_3009, IN1 => data(14));
and2_2464: AND2
PORT MAP ( Y => n_3010, IN1 => n_3011, IN2 => n_3012);
inv_2465: INV
PORT MAP ( Y => n_3011, IN1 => opreg_val14_Q);
delay_2466: DELAY
PORT MAP ( Y => n_3012, IN1 => comp1_modgen_56_l1_l0_c_int14_aOUT);
and1_2467: AND1
PORT MAP ( Y => n_3013, IN1 => gnd);
dff_2468: DFF
PORT MAP ( D => opreg_val15_aD, CLK => opreg_val15_aCLK, CLRN => vcc,
PRN => vcc, Q => opreg_val15_Q);
xor2_2469: XOR2
PORT MAP ( Y => opreg_val15_aD, IN1 => n_3020, IN2 => n_3023);
or1_2470: OR1
PORT MAP ( Y => n_3020, IN1 => n_3021);
and1_2471: AND1
PORT MAP ( Y => n_3021, IN1 => n_3022);
delay_2472: DELAY
PORT MAP ( Y => n_3022, IN1 => data(15));
and1_2473: AND1
PORT MAP ( Y => n_3023, IN1 => gnd);
and1_2474: AND1
PORT MAP ( Y => n_3024, IN1 => n_3025);
delay_2475: DELAY
PORT MAP ( Y => n_3025, IN1 => opregwr_Q);
delay_2476: DELAY
PORT MAP ( Y => opreg_val15_aCLK, IN1 => n_3024);
inv_2477: INV
PORT MAP ( Y => a_as_or2_a77_a_a30_aOUT, IN1 => a_as_or2_a77_a_a30_aOUT_aNOT);
delay_2478: DELAY
PORT MAP ( Y => a_as_or2_a77_a_a30_aOUT_aNOT, IN1 => n_3029);
inv_2479: INV
PORT MAP ( Y => a_as_or2_a77_a_a30_aIN1, IN1 => n_3029);
xor2_2480: XOR2
PORT MAP ( Y => n_3029, IN1 => n_3031, IN2 => n_3041);
or3_2481: OR3
PORT MAP ( Y => n_3031, IN1 => n_3032, IN2 => n_3035, IN3 => n_3038);
and2_2482: AND2
PORT MAP ( Y => n_3032, IN1 => n_3033, IN2 => n_3034);
inv_2483: INV
PORT MAP ( Y => n_3033, IN1 => comp1_modgen_56_l1_l0_c_int15_aOUT);
delay_2484: DELAY
PORT MAP ( Y => n_3034, IN1 => opreg_val15_Q);
and2_2485: AND2
PORT MAP ( Y => n_3035, IN1 => n_3036, IN2 => n_3037);
inv_2486: INV
PORT MAP ( Y => n_3036, IN1 => data(15));
inv_2487: INV
PORT MAP ( Y => n_3037, IN1 => comp1_modgen_56_l1_l0_c_int15_aOUT);
and2_2488: AND2
PORT MAP ( Y => n_3038, IN1 => n_3039, IN2 => n_3040);
inv_2489: INV
PORT MAP ( Y => n_3039, IN1 => data(15));
delay_2490: DELAY
PORT MAP ( Y => n_3040, IN1 => opreg_val15_Q);
and1_2491: AND1
PORT MAP ( Y => n_3041, IN1 => gnd);
delay_2492: DELAY
PORT MAP ( Y => a_a289_aOUT, IN1 => a_a289_aIN);
xor2_2493: XOR2
PORT MAP ( Y => a_a289_aIN, IN1 => n_3044, IN2 => n_3065);
or4_2494: OR4
PORT MAP ( Y => n_3044, IN1 => n_3045, IN2 => n_3050, IN3 => n_3055, IN4 => n_3060);
and4_2495: AND4
PORT MAP ( Y => n_3045, IN1 => n_3046, IN2 => n_3047, IN3 => n_3048, IN4 => n_3049);
delay_2496: DELAY
PORT MAP ( Y => n_3046, IN1 => opreg_val8_Q);
delay_2497: DELAY
PORT MAP ( Y => n_3047, IN1 => opreg_val9_Q);
delay_2498: DELAY
PORT MAP ( Y => n_3048, IN1 => data(8));
delay_2499: DELAY
PORT MAP ( Y => n_3049, IN1 => data(9));
and4_2500: AND4
PORT MAP ( Y => n_3050, IN1 => n_3051, IN2 => n_3052, IN3 => n_3053, IN4 => n_3054);
inv_2501: INV
PORT MAP ( Y => n_3051, IN1 => data(8));
inv_2502: INV
PORT MAP ( Y => n_3052, IN1 => opreg_val8_Q);
delay_2503: DELAY
PORT MAP ( Y => n_3053, IN1 => opreg_val9_Q);
delay_2504: DELAY
PORT MAP ( Y => n_3054, IN1 => data(9));
and4_2505: AND4
PORT MAP ( Y => n_3055, IN1 => n_3056, IN2 => n_3057, IN3 => n_3058, IN4 => n_3059);
inv_2506: INV
PORT MAP ( Y => n_3056, IN1 => data(9));
inv_2507: INV
PORT MAP ( Y => n_3057, IN1 => opreg_val9_Q);
delay_2508: DELAY
PORT MAP ( Y => n_3058, IN1 => opreg_val8_Q);
delay_2509: DELAY
PORT MAP ( Y => n_3059, IN1 => data(8));
and4_2510: AND4
PORT MAP ( Y => n_3060, IN1 => n_3061, IN2 => n_3062, IN3 => n_3063, IN4 => n_3064);
inv_2511: INV
PORT MAP ( Y => n_3061, IN1 => data(9));
inv_2512: INV
PORT MAP ( Y => n_3062, IN1 => data(8));
inv_2513: INV
PORT MAP ( Y => n_3063, IN1 => opreg_val9_Q);
inv_2514: INV
PORT MAP ( Y => n_3064, IN1 => opreg_val8_Q);
and1_2515: AND1
PORT MAP ( Y => n_3065, IN1 => gnd);
delay_2516: DELAY
PORT MAP ( Y => a_a290_aOUT, IN1 => a_a290_aIN);
and2_2517: AND2
PORT MAP ( Y => a_a290_aIN, IN1 => n_3068, IN2 => n_3089);
or4_2518: OR4
PORT MAP ( Y => n_3068, IN1 => n_3069, IN2 => n_3074, IN3 => n_3079, IN4 => n_3084);
and4_2519: AND4
PORT MAP ( Y => n_3069, IN1 => n_3070, IN2 => n_3071, IN3 => n_3072, IN4 => n_3073);
delay_2520: DELAY
PORT MAP ( Y => n_3070, IN1 => opreg_val10_Q);
delay_2521: DELAY
PORT MAP ( Y => n_3071, IN1 => opreg_val11_Q);
delay_2522: DELAY
PORT MAP ( Y => n_3072, IN1 => data(10));
delay_2523: DELAY
PORT MAP ( Y => n_3073, IN1 => data(11));
and4_2524: AND4
PORT MAP ( Y => n_3074, IN1 => n_3075, IN2 => n_3076, IN3 => n_3077, IN4 => n_3078);
inv_2525: INV
PORT MAP ( Y => n_3075, IN1 => data(11));
inv_2526: INV
PORT MAP ( Y => n_3076, IN1 => opreg_val11_Q);
delay_2527: DELAY
PORT MAP ( Y => n_3077, IN1 => opreg_val10_Q);
delay_2528: DELAY
PORT MAP ( Y => n_3078, IN1 => data(10));
and4_2529: AND4
PORT MAP ( Y => n_3079, IN1 => n_3080, IN2 => n_3081, IN3 => n_3082, IN4 => n_3083);
inv_2530: INV
PORT MAP ( Y => n_3080, IN1 => data(10));
inv_2531: INV
PORT MAP ( Y => n_3081, IN1 => opreg_val10_Q);
delay_2532: DELAY
PORT MAP ( Y => n_3082, IN1 => opreg_val11_Q);
delay_2533: DELAY
PORT MAP ( Y => n_3083, IN1 => data(11));
and4_2534: AND4
PORT MAP ( Y => n_3084, IN1 => n_3085, IN2 => n_3086, IN3 => n_3087, IN4 => n_3088);
inv_2535: INV
PORT MAP ( Y => n_3085, IN1 => data(11));
inv_2536: INV
PORT MAP ( Y => n_3086, IN1 => data(10));
inv_2537: INV
PORT MAP ( Y => n_3087, IN1 => opreg_val11_Q);
inv_2538: INV
PORT MAP ( Y => n_3088, IN1 => opreg_val10_Q);
delay_2539: DELAY
PORT MAP ( Y => n_3089, IN1 => a_a289_aIN);
delay_2540: DELAY
PORT MAP ( Y => a_a291_aOUT, IN1 => a_a291_aIN);
and2_2541: AND2
PORT MAP ( Y => a_a291_aIN, IN1 => n_3092, IN2 => n_3113);
or4_2542: OR4
PORT MAP ( Y => n_3092, IN1 => n_3093, IN2 => n_3098, IN3 => n_3103, IN4 => n_3108);
and4_2543: AND4
PORT MAP ( Y => n_3093, IN1 => n_3094, IN2 => n_3095, IN3 => n_3096, IN4 => n_3097);
delay_2544: DELAY
PORT MAP ( Y => n_3094, IN1 => opreg_val12_Q);
delay_2545: DELAY
PORT MAP ( Y => n_3095, IN1 => opreg_val13_Q);
delay_2546: DELAY
PORT MAP ( Y => n_3096, IN1 => data(12));
delay_2547: DELAY
PORT MAP ( Y => n_3097, IN1 => data(13));
and4_2548: AND4
PORT MAP ( Y => n_3098, IN1 => n_3099, IN2 => n_3100, IN3 => n_3101, IN4 => n_3102);
inv_2549: INV
PORT MAP ( Y => n_3099, IN1 => data(12));
inv_2550: INV
PORT MAP ( Y => n_3100, IN1 => opreg_val12_Q);
delay_2551: DELAY
PORT MAP ( Y => n_3101, IN1 => opreg_val13_Q);
delay_2552: DELAY
PORT MAP ( Y => n_3102, IN1 => data(13));
and4_2553: AND4
PORT MAP ( Y => n_3103, IN1 => n_3104, IN2 => n_3105, IN3 => n_3106, IN4 => n_3107);
inv_2554: INV
PORT MAP ( Y => n_3104, IN1 => data(13));
inv_2555: INV
PORT MAP ( Y => n_3105, IN1 => opreg_val13_Q);
delay_2556: DELAY
PORT MAP ( Y => n_3106, IN1 => opreg_val12_Q);
delay_2557: DELAY
PORT MAP ( Y => n_3107, IN1 => data(12));
and4_2558: AND4
PORT MAP ( Y => n_3108, IN1 => n_3109, IN2 => n_3110, IN3 => n_3111, IN4 => n_3112);
inv_2559: INV
PORT MAP ( Y => n_3109, IN1 => data(13));
inv_2560: INV
PORT MAP ( Y => n_3110, IN1 => data(12));
inv_2561: INV
PORT MAP ( Y => n_3111, IN1 => opreg_val13_Q);
inv_2562: INV
PORT MAP ( Y => n_3112, IN1 => opreg_val12_Q);
delay_2563: DELAY
PORT MAP ( Y => n_3113, IN1 => a_a290_aIN);
delay_2564: DELAY
PORT MAP ( Y => comp1_modgen_54_eqo1_aOUT, IN1 => comp1_modgen_54_eqo1_aIN1);
and2_2565: AND2
PORT MAP ( Y => comp1_modgen_54_eqo1_aIN1, IN1 => n_3116, IN2 => n_3137);
or4_2566: OR4
PORT MAP ( Y => n_3116, IN1 => n_3117, IN2 => n_3122, IN3 => n_3127, IN4 => n_3132);
and4_2567: AND4
PORT MAP ( Y => n_3117, IN1 => n_3118, IN2 => n_3119, IN3 => n_3120, IN4 => n_3121);
delay_2568: DELAY
PORT MAP ( Y => n_3118, IN1 => opreg_val14_Q);
delay_2569: DELAY
PORT MAP ( Y => n_3119, IN1 => opreg_val15_Q);
delay_2570: DELAY
PORT MAP ( Y => n_3120, IN1 => data(14));
delay_2571: DELAY
PORT MAP ( Y => n_3121, IN1 => data(15));
and4_2572: AND4
PORT MAP ( Y => n_3122, IN1 => n_3123, IN2 => n_3124, IN3 => n_3125, IN4 => n_3126);
inv_2573: INV
PORT MAP ( Y => n_3123, IN1 => data(14));
inv_2574: INV
PORT MAP ( Y => n_3124, IN1 => opreg_val14_Q);
delay_2575: DELAY
PORT MAP ( Y => n_3125, IN1 => opreg_val15_Q);
delay_2576: DELAY
PORT MAP ( Y => n_3126, IN1 => data(15));
and4_2577: AND4
PORT MAP ( Y => n_3127, IN1 => n_3128, IN2 => n_3129, IN3 => n_3130, IN4 => n_3131);
inv_2578: INV
PORT MAP ( Y => n_3128, IN1 => data(15));
inv_2579: INV
PORT MAP ( Y => n_3129, IN1 => opreg_val15_Q);
delay_2580: DELAY
PORT MAP ( Y => n_3130, IN1 => opreg_val14_Q);
delay_2581: DELAY
PORT MAP ( Y => n_3131, IN1 => data(14));
and4_2582: AND4
PORT MAP ( Y => n_3132, IN1 => n_3133, IN2 => n_3134, IN3 => n_3135, IN4 => n_3136);
inv_2583: INV
PORT MAP ( Y => n_3133, IN1 => data(15));
inv_2584: INV
PORT MAP ( Y => n_3134, IN1 => data(14));
inv_2585: INV
PORT MAP ( Y => n_3135, IN1 => opreg_val15_Q);
inv_2586: INV
PORT MAP ( Y => n_3136, IN1 => opreg_val14_Q);
delay_2587: DELAY
PORT MAP ( Y => n_3137, IN1 => a_a291_aIN);
delay_2588: DELAY
PORT MAP ( Y => a_a286_aOUT, IN1 => a_a286_aIN);
xor2_2589: XOR2
PORT MAP ( Y => a_a286_aIN, IN1 => n_3140, IN2 => n_3161);
or4_2590: OR4
PORT MAP ( Y => n_3140, IN1 => n_3141, IN2 => n_3146, IN3 => n_3151, IN4 => n_3156);
and4_2591: AND4
PORT MAP ( Y => n_3141, IN1 => n_3142, IN2 => n_3143, IN3 => n_3144, IN4 => n_3145);
delay_2592: DELAY
PORT MAP ( Y => n_3142, IN1 => opreg_val0_Q);
delay_2593: DELAY
PORT MAP ( Y => n_3143, IN1 => opreg_val1_Q);
delay_2594: DELAY
PORT MAP ( Y => n_3144, IN1 => data(0));
delay_2595: DELAY
PORT MAP ( Y => n_3145, IN1 => data(1));
and4_2596: AND4
PORT MAP ( Y => n_3146, IN1 => n_3147, IN2 => n_3148, IN3 => n_3149, IN4 => n_3150);
inv_2597: INV
PORT MAP ( Y => n_3147, IN1 => data(1));
inv_2598: INV
PORT MAP ( Y => n_3148, IN1 => opreg_val1_Q);
delay_2599: DELAY
PORT MAP ( Y => n_3149, IN1 => opreg_val0_Q);
delay_2600: DELAY
PORT MAP ( Y => n_3150, IN1 => data(0));
and4_2601: AND4
PORT MAP ( Y => n_3151, IN1 => n_3152, IN2 => n_3153, IN3 => n_3154, IN4 => n_3155);
inv_2602: INV
PORT MAP ( Y => n_3152, IN1 => data(0));
inv_2603: INV
PORT MAP ( Y => n_3153, IN1 => opreg_val0_Q);
delay_2604: DELAY
PORT MAP ( Y => n_3154, IN1 => opreg_val1_Q);
delay_2605: DELAY
PORT MAP ( Y => n_3155, IN1 => data(1));
and4_2606: AND4
PORT MAP ( Y => n_3156, IN1 => n_3157, IN2 => n_3158, IN3 => n_3159, IN4 => n_3160);
inv_2607: INV
PORT MAP ( Y => n_3157, IN1 => data(1));
inv_2608: INV
PORT MAP ( Y => n_3158, IN1 => data(0));
inv_2609: INV
PORT MAP ( Y => n_3159, IN1 => opreg_val1_Q);
inv_2610: INV
PORT MAP ( Y => n_3160, IN1 => opreg_val0_Q);
and1_2611: AND1
PORT MAP ( Y => n_3161, IN1 => gnd);
delay_2612: DELAY
PORT MAP ( Y => a_a287_aOUT, IN1 => a_a287_aIN);
and2_2613: AND2
PORT MAP ( Y => a_a287_aIN, IN1 => n_3164, IN2 => n_3185);
or4_2614: OR4
PORT MAP ( Y => n_3164, IN1 => n_3165, IN2 => n_3170, IN3 => n_3175, IN4 => n_3180);
and4_2615: AND4
PORT MAP ( Y => n_3165, IN1 => n_3166, IN2 => n_3167, IN3 => n_3168, IN4 => n_3169);
delay_2616: DELAY
PORT MAP ( Y => n_3166, IN1 => opreg_val2_Q);
delay_2617: DELAY
PORT MAP ( Y => n_3167, IN1 => opreg_val3_Q);
delay_2618: DELAY
PORT MAP ( Y => n_3168, IN1 => data(2));
delay_2619: DELAY
PORT MAP ( Y => n_3169, IN1 => data(3));
and4_2620: AND4
PORT MAP ( Y => n_3170, IN1 => n_3171, IN2 => n_3172, IN3 => n_3173, IN4 => n_3174);
inv_2621: INV
PORT MAP ( Y => n_3171, IN1 => data(2));
inv_2622: INV
PORT MAP ( Y => n_3172, IN1 => opreg_val2_Q);
delay_2623: DELAY
PORT MAP ( Y => n_3173, IN1 => opreg_val3_Q);
delay_2624: DELAY
PORT MAP ( Y => n_3174, IN1 => data(3));
and4_2625: AND4
PORT MAP ( Y => n_3175, IN1 => n_3176, IN2 => n_3177, IN3 => n_3178, IN4 => n_3179);
inv_2626: INV
PORT MAP ( Y => n_3176, IN1 => data(3));
inv_2627: INV
PORT MAP ( Y => n_3177, IN1 => opreg_val3_Q);
delay_2628: DELAY
PORT MAP ( Y => n_3178, IN1 => opreg_val2_Q);
delay_2629: DELAY
PORT MAP ( Y => n_3179, IN1 => data(2));
and4_2630: AND4
PORT MAP ( Y => n_3180, IN1 => n_3181, IN2 => n_3182, IN3 => n_3183, IN4 => n_3184);
inv_2631: INV
PORT MAP ( Y => n_3181, IN1 => data(3));
inv_2632: INV
PORT MAP ( Y => n_3182, IN1 => data(2));
inv_2633: INV
PORT MAP ( Y => n_3183, IN1 => opreg_val3_Q);
inv_2634: INV
PORT MAP ( Y => n_3184, IN1 => opreg_val2_Q);
delay_2635: DELAY
PORT MAP ( Y => n_3185, IN1 => a_a286_aIN);
delay_2636: DELAY
PORT MAP ( Y => a_a288_aOUT, IN1 => a_a288_aIN);
and2_2637: AND2
PORT MAP ( Y => a_a288_aIN, IN1 => n_3188, IN2 => n_3209);
or4_2638: OR4
PORT MAP ( Y => n_3188, IN1 => n_3189, IN2 => n_3194, IN3 => n_3199, IN4 => n_3204);
and4_2639: AND4
PORT MAP ( Y => n_3189, IN1 => n_3190, IN2 => n_3191, IN3 => n_3192, IN4 => n_3193);
delay_2640: DELAY
PORT MAP ( Y => n_3190, IN1 => opreg_val4_Q);
delay_2641: DELAY
PORT MAP ( Y => n_3191, IN1 => opreg_val5_Q);
delay_2642: DELAY
PORT MAP ( Y => n_3192, IN1 => data(4));
delay_2643: DELAY
PORT MAP ( Y => n_3193, IN1 => data(5));
and4_2644: AND4
PORT MAP ( Y => n_3194, IN1 => n_3195, IN2 => n_3196, IN3 => n_3197, IN4 => n_3198);
inv_2645: INV
PORT MAP ( Y => n_3195, IN1 => data(4));
inv_2646: INV
PORT MAP ( Y => n_3196, IN1 => opreg_val4_Q);
delay_2647: DELAY
PORT MAP ( Y => n_3197, IN1 => opreg_val5_Q);
delay_2648: DELAY
PORT MAP ( Y => n_3198, IN1 => data(5));
and4_2649: AND4
PORT MAP ( Y => n_3199, IN1 => n_3200, IN2 => n_3201, IN3 => n_3202, IN4 => n_3203);
inv_2650: INV
PORT MAP ( Y => n_3200, IN1 => data(5));
inv_2651: INV
PORT MAP ( Y => n_3201, IN1 => opreg_val5_Q);
delay_2652: DELAY
PORT MAP ( Y => n_3202, IN1 => opreg_val4_Q);
delay_2653: DELAY
PORT MAP ( Y => n_3203, IN1 => data(4));
and4_2654: AND4
PORT MAP ( Y => n_3204, IN1 => n_3205, IN2 => n_3206, IN3 => n_3207, IN4 => n_3208);
inv_2655: INV
PORT MAP ( Y => n_3205, IN1 => data(5));
inv_2656: INV
PORT MAP ( Y => n_3206, IN1 => data(4));
inv_2657: INV
PORT MAP ( Y => n_3207, IN1 => opreg_val5_Q);
inv_2658: INV
PORT MAP ( Y => n_3208, IN1 => opreg_val4_Q);
delay_2659: DELAY
PORT MAP ( Y => n_3209, IN1 => a_a287_aIN);
delay_2660: DELAY
PORT MAP ( Y => comp1_modgen_54_eqo0_aOUT, IN1 => comp1_modgen_54_eqo0_aIN1);
and2_2661: AND2
PORT MAP ( Y => comp1_modgen_54_eqo0_aIN1, IN1 => n_3212, IN2 => n_3233);
or4_2662: OR4
PORT MAP ( Y => n_3212, IN1 => n_3213, IN2 => n_3218, IN3 => n_3223, IN4 => n_3228);
and4_2663: AND4
PORT MAP ( Y => n_3213, IN1 => n_3214, IN2 => n_3215, IN3 => n_3216, IN4 => n_3217);
delay_2664: DELAY
PORT MAP ( Y => n_3214, IN1 => opreg_val6_Q);
delay_2665: DELAY
PORT MAP ( Y => n_3215, IN1 => opreg_val7_Q);
delay_2666: DELAY
PORT MAP ( Y => n_3216, IN1 => data(6));
delay_2667: DELAY
PORT MAP ( Y => n_3217, IN1 => data(7));
and4_2668: AND4
PORT MAP ( Y => n_3218, IN1 => n_3219, IN2 => n_3220, IN3 => n_3221, IN4 => n_3222);
inv_2669: INV
PORT MAP ( Y => n_3219, IN1 => data(6));
inv_2670: INV
PORT MAP ( Y => n_3220, IN1 => opreg_val6_Q);
delay_2671: DELAY
PORT MAP ( Y => n_3221, IN1 => opreg_val7_Q);
delay_2672: DELAY
PORT MAP ( Y => n_3222, IN1 => data(7));
and4_2673: AND4
PORT MAP ( Y => n_3223, IN1 => n_3224, IN2 => n_3225, IN3 => n_3226, IN4 => n_3227);
inv_2674: INV
PORT MAP ( Y => n_3224, IN1 => data(7));
inv_2675: INV
PORT MAP ( Y => n_3225, IN1 => opreg_val7_Q);
delay_2676: DELAY
PORT MAP ( Y => n_3226, IN1 => opreg_val6_Q);
delay_2677: DELAY
PORT MAP ( Y => n_3227, IN1 => data(6));
and4_2678: AND4
PORT MAP ( Y => n_3228, IN1 => n_3229, IN2 => n_3230, IN3 => n_3231, IN4 => n_3232);
inv_2679: INV
PORT MAP ( Y => n_3229, IN1 => data(7));
inv_2680: INV
PORT MAP ( Y => n_3230, IN1 => data(6));
inv_2681: INV
PORT MAP ( Y => n_3231, IN1 => opreg_val7_Q);
inv_2682: INV
PORT MAP ( Y => n_3232, IN1 => opreg_val6_Q);
delay_2683: DELAY
PORT MAP ( Y => n_3233, IN1 => a_a288_aIN);
delay_2684: DELAY
PORT MAP ( Y => comp1_nx38_aOUT, IN1 => comp1_nx38_aIN);
xor2_2685: XOR2
PORT MAP ( Y => comp1_nx38_aIN, IN1 => n_3236, IN2 => n_3245);
or2_2686: OR2
PORT MAP ( Y => n_3236, IN1 => n_3237, IN2 => n_3241);
and2_2687: AND2
PORT MAP ( Y => n_3237, IN1 => n_3238, IN2 => n_3240);
delay_2688: DELAY
PORT MAP ( Y => n_3238, IN1 => opregrd_aOUT);
delay_2689: DELAY
PORT MAP ( Y => n_3240, IN1 => a_as_or2_a77_a_a30_aOUT_aNOT);
and3_2690: AND3
PORT MAP ( Y => n_3241, IN1 => n_3242, IN2 => n_3243, IN3 => n_3244);
inv_2691: INV
PORT MAP ( Y => n_3242, IN1 => opregrd_aOUT);
delay_2692: DELAY
PORT MAP ( Y => n_3243, IN1 => comp1_modgen_54_eqo1_aOUT);
delay_2693: DELAY
PORT MAP ( Y => n_3244, IN1 => comp1_modgen_54_eqo0_aOUT);
and1_2694: AND1
PORT MAP ( Y => n_3245, IN1 => gnd);
dff_2695: DFF
PORT MAP ( D => con1_current_state33_aD, CLK => con1_current_state33_aCLK,
CLRN => con1_current_state33_aCLRN, PRN => vcc, Q => con1_current_state33_Q);
inv_2696: INV
PORT MAP ( Y => con1_current_state33_aCLRN, IN1 => reset);
xor2_2697: XOR2
PORT MAP ( Y => con1_current_state33_aD, IN1 => n_3253, IN2 => n_3257);
or1_2698: OR1
PORT MAP ( Y => n_3253, IN1 => n_3254);
and2_2699: AND2
PORT MAP ( Y => n_3254, IN1 => n_3255, IN2 => n_3256);
delay_2700: DELAY
PORT MAP ( Y => n_3255, IN1 => con1_current_state32_Q);
delay_2701: DELAY
PORT MAP ( Y => n_3256, IN1 => comp1_nx38_aOUT);
and1_2702: AND1
PORT MAP ( Y => n_3257, IN1 => gnd);
delay_2703: DELAY
PORT MAP ( Y => con1_current_state33_aCLK, IN1 => clock);
dffe_2704: DFFE
PORT MAP ( D => ix484_a1_dup_653_aD, CLK => ix484_a1_dup_653_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_653_aENA, Q => ix484_a1_dup_653_Q);
xor2_2705: XOR2
PORT MAP ( Y => ix484_a1_dup_653_aD, IN1 => n_3265, IN2 => n_3268);
or1_2706: OR1
PORT MAP ( Y => n_3265, IN1 => n_3266);
and1_2707: AND1
PORT MAP ( Y => n_3266, IN1 => n_3267);
delay_2708: DELAY
PORT MAP ( Y => n_3267, IN1 => data(0));
and1_2709: AND1
PORT MAP ( Y => n_3268, IN1 => gnd);
and1_2710: AND1
PORT MAP ( Y => n_3269, IN1 => n_3270);
delay_2711: DELAY
PORT MAP ( Y => n_3270, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2712: DELAY
PORT MAP ( Y => ix484_a1_dup_653_aCLK, IN1 => n_3269);
and1_2713: AND1
PORT MAP ( Y => ix484_a1_dup_653_aENA, IN1 => n_3273);
delay_2714: DELAY
PORT MAP ( Y => n_3273, IN1 => ix484_nx44_aOUT);
dffe_2715: DFFE
PORT MAP ( D => ix484_a5_dup_649_aD, CLK => ix484_a5_dup_649_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_649_aENA, Q => ix484_a5_dup_649_Q);
xor2_2716: XOR2
PORT MAP ( Y => ix484_a5_dup_649_aD, IN1 => n_3280, IN2 => n_3283);
or1_2717: OR1
PORT MAP ( Y => n_3280, IN1 => n_3281);
and1_2718: AND1
PORT MAP ( Y => n_3281, IN1 => n_3282);
delay_2719: DELAY
PORT MAP ( Y => n_3282, IN1 => data(0));
and1_2720: AND1
PORT MAP ( Y => n_3283, IN1 => gnd);
and1_2721: AND1
PORT MAP ( Y => n_3284, IN1 => n_3285);
delay_2722: DELAY
PORT MAP ( Y => n_3285, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2723: DELAY
PORT MAP ( Y => ix484_a5_dup_649_aCLK, IN1 => n_3284);
and1_2724: AND1
PORT MAP ( Y => ix484_a5_dup_649_aENA, IN1 => n_3288);
delay_2725: DELAY
PORT MAP ( Y => n_3288, IN1 => ix484_nx40_aOUT);
dffe_2726: DFFE
PORT MAP ( D => ix484_a1_dup_645_aD, CLK => ix484_a1_dup_645_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_645_aENA, Q => ix484_a1_dup_645_Q);
xor2_2727: XOR2
PORT MAP ( Y => ix484_a1_dup_645_aD, IN1 => n_3295, IN2 => n_3298);
or1_2728: OR1
PORT MAP ( Y => n_3295, IN1 => n_3296);
and1_2729: AND1
PORT MAP ( Y => n_3296, IN1 => n_3297);
delay_2730: DELAY
PORT MAP ( Y => n_3297, IN1 => data(1));
and1_2731: AND1
PORT MAP ( Y => n_3298, IN1 => gnd);
and1_2732: AND1
PORT MAP ( Y => n_3299, IN1 => n_3300);
delay_2733: DELAY
PORT MAP ( Y => n_3300, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2734: DELAY
PORT MAP ( Y => ix484_a1_dup_645_aCLK, IN1 => n_3299);
and1_2735: AND1
PORT MAP ( Y => ix484_a1_dup_645_aENA, IN1 => n_3303);
delay_2736: DELAY
PORT MAP ( Y => n_3303, IN1 => ix484_nx44_aOUT);
dffe_2737: DFFE
PORT MAP ( D => ix484_a5_dup_641_aD, CLK => ix484_a5_dup_641_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_641_aENA, Q => ix484_a5_dup_641_Q);
xor2_2738: XOR2
PORT MAP ( Y => ix484_a5_dup_641_aD, IN1 => n_3310, IN2 => n_3313);
or1_2739: OR1
PORT MAP ( Y => n_3310, IN1 => n_3311);
and1_2740: AND1
PORT MAP ( Y => n_3311, IN1 => n_3312);
delay_2741: DELAY
PORT MAP ( Y => n_3312, IN1 => data(1));
and1_2742: AND1
PORT MAP ( Y => n_3313, IN1 => gnd);
and1_2743: AND1
PORT MAP ( Y => n_3314, IN1 => n_3315);
delay_2744: DELAY
PORT MAP ( Y => n_3315, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2745: DELAY
PORT MAP ( Y => ix484_a5_dup_641_aCLK, IN1 => n_3314);
and1_2746: AND1
PORT MAP ( Y => ix484_a5_dup_641_aENA, IN1 => n_3318);
delay_2747: DELAY
PORT MAP ( Y => n_3318, IN1 => ix484_nx40_aOUT);
dffe_2748: DFFE
PORT MAP ( D => ix484_a1_dup_637_aD, CLK => ix484_a1_dup_637_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_637_aENA, Q => ix484_a1_dup_637_Q);
xor2_2749: XOR2
PORT MAP ( Y => ix484_a1_dup_637_aD, IN1 => n_3325, IN2 => n_3328);
or1_2750: OR1
PORT MAP ( Y => n_3325, IN1 => n_3326);
and1_2751: AND1
PORT MAP ( Y => n_3326, IN1 => n_3327);
delay_2752: DELAY
PORT MAP ( Y => n_3327, IN1 => data(2));
and1_2753: AND1
PORT MAP ( Y => n_3328, IN1 => gnd);
and1_2754: AND1
PORT MAP ( Y => n_3329, IN1 => n_3330);
delay_2755: DELAY
PORT MAP ( Y => n_3330, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2756: DELAY
PORT MAP ( Y => ix484_a1_dup_637_aCLK, IN1 => n_3329);
and1_2757: AND1
PORT MAP ( Y => ix484_a1_dup_637_aENA, IN1 => n_3333);
delay_2758: DELAY
PORT MAP ( Y => n_3333, IN1 => ix484_nx44_aOUT);
dffe_2759: DFFE
PORT MAP ( D => ix484_a5_dup_633_aD, CLK => ix484_a5_dup_633_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_633_aENA, Q => ix484_a5_dup_633_Q);
xor2_2760: XOR2
PORT MAP ( Y => ix484_a5_dup_633_aD, IN1 => n_3340, IN2 => n_3343);
or1_2761: OR1
PORT MAP ( Y => n_3340, IN1 => n_3341);
and1_2762: AND1
PORT MAP ( Y => n_3341, IN1 => n_3342);
delay_2763: DELAY
PORT MAP ( Y => n_3342, IN1 => data(2));
and1_2764: AND1
PORT MAP ( Y => n_3343, IN1 => gnd);
and1_2765: AND1
PORT MAP ( Y => n_3344, IN1 => n_3345);
delay_2766: DELAY
PORT MAP ( Y => n_3345, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2767: DELAY
PORT MAP ( Y => ix484_a5_dup_633_aCLK, IN1 => n_3344);
and1_2768: AND1
PORT MAP ( Y => ix484_a5_dup_633_aENA, IN1 => n_3348);
delay_2769: DELAY
PORT MAP ( Y => n_3348, IN1 => ix484_nx40_aOUT);
dffe_2770: DFFE
PORT MAP ( D => ix484_a1_dup_629_aD, CLK => ix484_a1_dup_629_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_629_aENA, Q => ix484_a1_dup_629_Q);
xor2_2771: XOR2
PORT MAP ( Y => ix484_a1_dup_629_aD, IN1 => n_3355, IN2 => n_3358);
or1_2772: OR1
PORT MAP ( Y => n_3355, IN1 => n_3356);
and1_2773: AND1
PORT MAP ( Y => n_3356, IN1 => n_3357);
delay_2774: DELAY
PORT MAP ( Y => n_3357, IN1 => data(3));
and1_2775: AND1
PORT MAP ( Y => n_3358, IN1 => gnd);
and1_2776: AND1
PORT MAP ( Y => n_3359, IN1 => n_3360);
delay_2777: DELAY
PORT MAP ( Y => n_3360, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2778: DELAY
PORT MAP ( Y => ix484_a1_dup_629_aCLK, IN1 => n_3359);
and1_2779: AND1
PORT MAP ( Y => ix484_a1_dup_629_aENA, IN1 => n_3363);
delay_2780: DELAY
PORT MAP ( Y => n_3363, IN1 => ix484_nx44_aOUT);
dffe_2781: DFFE
PORT MAP ( D => ix484_a5_dup_625_aD, CLK => ix484_a5_dup_625_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_625_aENA, Q => ix484_a5_dup_625_Q);
xor2_2782: XOR2
PORT MAP ( Y => ix484_a5_dup_625_aD, IN1 => n_3370, IN2 => n_3373);
or1_2783: OR1
PORT MAP ( Y => n_3370, IN1 => n_3371);
and1_2784: AND1
PORT MAP ( Y => n_3371, IN1 => n_3372);
delay_2785: DELAY
PORT MAP ( Y => n_3372, IN1 => data(3));
and1_2786: AND1
PORT MAP ( Y => n_3373, IN1 => gnd);
and1_2787: AND1
PORT MAP ( Y => n_3374, IN1 => n_3375);
delay_2788: DELAY
PORT MAP ( Y => n_3375, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2789: DELAY
PORT MAP ( Y => ix484_a5_dup_625_aCLK, IN1 => n_3374);
and1_2790: AND1
PORT MAP ( Y => ix484_a5_dup_625_aENA, IN1 => n_3378);
delay_2791: DELAY
PORT MAP ( Y => n_3378, IN1 => ix484_nx40_aOUT);
dffe_2792: DFFE
PORT MAP ( D => ix484_a1_dup_621_aD, CLK => ix484_a1_dup_621_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_621_aENA, Q => ix484_a1_dup_621_Q);
xor2_2793: XOR2
PORT MAP ( Y => ix484_a1_dup_621_aD, IN1 => n_3385, IN2 => n_3388);
or1_2794: OR1
PORT MAP ( Y => n_3385, IN1 => n_3386);
and1_2795: AND1
PORT MAP ( Y => n_3386, IN1 => n_3387);
delay_2796: DELAY
PORT MAP ( Y => n_3387, IN1 => data(4));
and1_2797: AND1
PORT MAP ( Y => n_3388, IN1 => gnd);
and1_2798: AND1
PORT MAP ( Y => n_3389, IN1 => n_3390);
delay_2799: DELAY
PORT MAP ( Y => n_3390, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2800: DELAY
PORT MAP ( Y => ix484_a1_dup_621_aCLK, IN1 => n_3389);
and1_2801: AND1
PORT MAP ( Y => ix484_a1_dup_621_aENA, IN1 => n_3393);
delay_2802: DELAY
PORT MAP ( Y => n_3393, IN1 => ix484_nx44_aOUT);
dffe_2803: DFFE
PORT MAP ( D => ix484_a5_dup_617_aD, CLK => ix484_a5_dup_617_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_617_aENA, Q => ix484_a5_dup_617_Q);
xor2_2804: XOR2
PORT MAP ( Y => ix484_a5_dup_617_aD, IN1 => n_3400, IN2 => n_3403);
or1_2805: OR1
PORT MAP ( Y => n_3400, IN1 => n_3401);
and1_2806: AND1
PORT MAP ( Y => n_3401, IN1 => n_3402);
delay_2807: DELAY
PORT MAP ( Y => n_3402, IN1 => data(4));
and1_2808: AND1
PORT MAP ( Y => n_3403, IN1 => gnd);
and1_2809: AND1
PORT MAP ( Y => n_3404, IN1 => n_3405);
delay_2810: DELAY
PORT MAP ( Y => n_3405, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2811: DELAY
PORT MAP ( Y => ix484_a5_dup_617_aCLK, IN1 => n_3404);
and1_2812: AND1
PORT MAP ( Y => ix484_a5_dup_617_aENA, IN1 => n_3408);
delay_2813: DELAY
PORT MAP ( Y => n_3408, IN1 => ix484_nx40_aOUT);
dffe_2814: DFFE
PORT MAP ( D => ix484_a1_dup_613_aD, CLK => ix484_a1_dup_613_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_613_aENA, Q => ix484_a1_dup_613_Q);
xor2_2815: XOR2
PORT MAP ( Y => ix484_a1_dup_613_aD, IN1 => n_3415, IN2 => n_3418);
or1_2816: OR1
PORT MAP ( Y => n_3415, IN1 => n_3416);
and1_2817: AND1
PORT MAP ( Y => n_3416, IN1 => n_3417);
delay_2818: DELAY
PORT MAP ( Y => n_3417, IN1 => data(5));
and1_2819: AND1
PORT MAP ( Y => n_3418, IN1 => gnd);
and1_2820: AND1
PORT MAP ( Y => n_3419, IN1 => n_3420);
delay_2821: DELAY
PORT MAP ( Y => n_3420, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2822: DELAY
PORT MAP ( Y => ix484_a1_dup_613_aCLK, IN1 => n_3419);
and1_2823: AND1
PORT MAP ( Y => ix484_a1_dup_613_aENA, IN1 => n_3423);
delay_2824: DELAY
PORT MAP ( Y => n_3423, IN1 => ix484_nx44_aOUT);
dffe_2825: DFFE
PORT MAP ( D => ix484_a5_dup_609_aD, CLK => ix484_a5_dup_609_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_609_aENA, Q => ix484_a5_dup_609_Q);
xor2_2826: XOR2
PORT MAP ( Y => ix484_a5_dup_609_aD, IN1 => n_3430, IN2 => n_3433);
or1_2827: OR1
PORT MAP ( Y => n_3430, IN1 => n_3431);
and1_2828: AND1
PORT MAP ( Y => n_3431, IN1 => n_3432);
delay_2829: DELAY
PORT MAP ( Y => n_3432, IN1 => data(5));
and1_2830: AND1
PORT MAP ( Y => n_3433, IN1 => gnd);
and1_2831: AND1
PORT MAP ( Y => n_3434, IN1 => n_3435);
delay_2832: DELAY
PORT MAP ( Y => n_3435, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2833: DELAY
PORT MAP ( Y => ix484_a5_dup_609_aCLK, IN1 => n_3434);
and1_2834: AND1
PORT MAP ( Y => ix484_a5_dup_609_aENA, IN1 => n_3438);
delay_2835: DELAY
PORT MAP ( Y => n_3438, IN1 => ix484_nx40_aOUT);
dffe_2836: DFFE
PORT MAP ( D => ix484_a1_dup_605_aD, CLK => ix484_a1_dup_605_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_605_aENA, Q => ix484_a1_dup_605_Q);
xor2_2837: XOR2
PORT MAP ( Y => ix484_a1_dup_605_aD, IN1 => n_3445, IN2 => n_3448);
or1_2838: OR1
PORT MAP ( Y => n_3445, IN1 => n_3446);
and1_2839: AND1
PORT MAP ( Y => n_3446, IN1 => n_3447);
delay_2840: DELAY
PORT MAP ( Y => n_3447, IN1 => data(6));
and1_2841: AND1
PORT MAP ( Y => n_3448, IN1 => gnd);
and1_2842: AND1
PORT MAP ( Y => n_3449, IN1 => n_3450);
delay_2843: DELAY
PORT MAP ( Y => n_3450, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2844: DELAY
PORT MAP ( Y => ix484_a1_dup_605_aCLK, IN1 => n_3449);
and1_2845: AND1
PORT MAP ( Y => ix484_a1_dup_605_aENA, IN1 => n_3453);
delay_2846: DELAY
PORT MAP ( Y => n_3453, IN1 => ix484_nx44_aOUT);
dffe_2847: DFFE
PORT MAP ( D => ix484_a5_dup_601_aD, CLK => ix484_a5_dup_601_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_601_aENA, Q => ix484_a5_dup_601_Q);
xor2_2848: XOR2
PORT MAP ( Y => ix484_a5_dup_601_aD, IN1 => n_3460, IN2 => n_3463);
or1_2849: OR1
PORT MAP ( Y => n_3460, IN1 => n_3461);
and1_2850: AND1
PORT MAP ( Y => n_3461, IN1 => n_3462);
delay_2851: DELAY
PORT MAP ( Y => n_3462, IN1 => data(6));
and1_2852: AND1
PORT MAP ( Y => n_3463, IN1 => gnd);
and1_2853: AND1
PORT MAP ( Y => n_3464, IN1 => n_3465);
delay_2854: DELAY
PORT MAP ( Y => n_3465, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2855: DELAY
PORT MAP ( Y => ix484_a5_dup_601_aCLK, IN1 => n_3464);
and1_2856: AND1
PORT MAP ( Y => ix484_a5_dup_601_aENA, IN1 => n_3468);
delay_2857: DELAY
PORT MAP ( Y => n_3468, IN1 => ix484_nx40_aOUT);
dffe_2858: DFFE
PORT MAP ( D => ix484_a1_dup_597_aD, CLK => ix484_a1_dup_597_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_597_aENA, Q => ix484_a1_dup_597_Q);
xor2_2859: XOR2
PORT MAP ( Y => ix484_a1_dup_597_aD, IN1 => n_3475, IN2 => n_3478);
or1_2860: OR1
PORT MAP ( Y => n_3475, IN1 => n_3476);
and1_2861: AND1
PORT MAP ( Y => n_3476, IN1 => n_3477);
delay_2862: DELAY
PORT MAP ( Y => n_3477, IN1 => data(7));
and1_2863: AND1
PORT MAP ( Y => n_3478, IN1 => gnd);
and1_2864: AND1
PORT MAP ( Y => n_3479, IN1 => n_3480);
delay_2865: DELAY
PORT MAP ( Y => n_3480, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2866: DELAY
PORT MAP ( Y => ix484_a1_dup_597_aCLK, IN1 => n_3479);
and1_2867: AND1
PORT MAP ( Y => ix484_a1_dup_597_aENA, IN1 => n_3483);
delay_2868: DELAY
PORT MAP ( Y => n_3483, IN1 => ix484_nx44_aOUT);
dffe_2869: DFFE
PORT MAP ( D => ix484_a5_dup_593_aD, CLK => ix484_a5_dup_593_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_593_aENA, Q => ix484_a5_dup_593_Q);
xor2_2870: XOR2
PORT MAP ( Y => ix484_a5_dup_593_aD, IN1 => n_3490, IN2 => n_3493);
or1_2871: OR1
PORT MAP ( Y => n_3490, IN1 => n_3491);
and1_2872: AND1
PORT MAP ( Y => n_3491, IN1 => n_3492);
delay_2873: DELAY
PORT MAP ( Y => n_3492, IN1 => data(7));
and1_2874: AND1
PORT MAP ( Y => n_3493, IN1 => gnd);
and1_2875: AND1
PORT MAP ( Y => n_3494, IN1 => n_3495);
delay_2876: DELAY
PORT MAP ( Y => n_3495, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2877: DELAY
PORT MAP ( Y => ix484_a5_dup_593_aCLK, IN1 => n_3494);
and1_2878: AND1
PORT MAP ( Y => ix484_a5_dup_593_aENA, IN1 => n_3498);
delay_2879: DELAY
PORT MAP ( Y => n_3498, IN1 => ix484_nx40_aOUT);
dffe_2880: DFFE
PORT MAP ( D => ix484_a1_dup_589_aD, CLK => ix484_a1_dup_589_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_589_aENA, Q => ix484_a1_dup_589_Q);
xor2_2881: XOR2
PORT MAP ( Y => ix484_a1_dup_589_aD, IN1 => n_3505, IN2 => n_3508);
or1_2882: OR1
PORT MAP ( Y => n_3505, IN1 => n_3506);
and1_2883: AND1
PORT MAP ( Y => n_3506, IN1 => n_3507);
delay_2884: DELAY
PORT MAP ( Y => n_3507, IN1 => data(8));
and1_2885: AND1
PORT MAP ( Y => n_3508, IN1 => gnd);
and1_2886: AND1
PORT MAP ( Y => n_3509, IN1 => n_3510);
delay_2887: DELAY
PORT MAP ( Y => n_3510, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2888: DELAY
PORT MAP ( Y => ix484_a1_dup_589_aCLK, IN1 => n_3509);
and1_2889: AND1
PORT MAP ( Y => ix484_a1_dup_589_aENA, IN1 => n_3513);
delay_2890: DELAY
PORT MAP ( Y => n_3513, IN1 => ix484_nx44_aOUT);
dffe_2891: DFFE
PORT MAP ( D => ix484_a5_dup_585_aD, CLK => ix484_a5_dup_585_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_585_aENA, Q => ix484_a5_dup_585_Q);
xor2_2892: XOR2
PORT MAP ( Y => ix484_a5_dup_585_aD, IN1 => n_3520, IN2 => n_3523);
or1_2893: OR1
PORT MAP ( Y => n_3520, IN1 => n_3521);
and1_2894: AND1
PORT MAP ( Y => n_3521, IN1 => n_3522);
delay_2895: DELAY
PORT MAP ( Y => n_3522, IN1 => data(8));
and1_2896: AND1
PORT MAP ( Y => n_3523, IN1 => gnd);
and1_2897: AND1
PORT MAP ( Y => n_3524, IN1 => n_3525);
delay_2898: DELAY
PORT MAP ( Y => n_3525, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2899: DELAY
PORT MAP ( Y => ix484_a5_dup_585_aCLK, IN1 => n_3524);
and1_2900: AND1
PORT MAP ( Y => ix484_a5_dup_585_aENA, IN1 => n_3528);
delay_2901: DELAY
PORT MAP ( Y => n_3528, IN1 => ix484_nx40_aOUT);
dffe_2902: DFFE
PORT MAP ( D => ix484_a1_dup_581_aD, CLK => ix484_a1_dup_581_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_581_aENA, Q => ix484_a1_dup_581_Q);
xor2_2903: XOR2
PORT MAP ( Y => ix484_a1_dup_581_aD, IN1 => n_3535, IN2 => n_3538);
or1_2904: OR1
PORT MAP ( Y => n_3535, IN1 => n_3536);
and1_2905: AND1
PORT MAP ( Y => n_3536, IN1 => n_3537);
delay_2906: DELAY
PORT MAP ( Y => n_3537, IN1 => data(9));
and1_2907: AND1
PORT MAP ( Y => n_3538, IN1 => gnd);
and1_2908: AND1
PORT MAP ( Y => n_3539, IN1 => n_3540);
delay_2909: DELAY
PORT MAP ( Y => n_3540, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2910: DELAY
PORT MAP ( Y => ix484_a1_dup_581_aCLK, IN1 => n_3539);
and1_2911: AND1
PORT MAP ( Y => ix484_a1_dup_581_aENA, IN1 => n_3543);
delay_2912: DELAY
PORT MAP ( Y => n_3543, IN1 => ix484_nx44_aOUT);
dffe_2913: DFFE
PORT MAP ( D => ix484_a5_dup_577_aD, CLK => ix484_a5_dup_577_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_577_aENA, Q => ix484_a5_dup_577_Q);
xor2_2914: XOR2
PORT MAP ( Y => ix484_a5_dup_577_aD, IN1 => n_3550, IN2 => n_3553);
or1_2915: OR1
PORT MAP ( Y => n_3550, IN1 => n_3551);
and1_2916: AND1
PORT MAP ( Y => n_3551, IN1 => n_3552);
delay_2917: DELAY
PORT MAP ( Y => n_3552, IN1 => data(9));
and1_2918: AND1
PORT MAP ( Y => n_3553, IN1 => gnd);
and1_2919: AND1
PORT MAP ( Y => n_3554, IN1 => n_3555);
delay_2920: DELAY
PORT MAP ( Y => n_3555, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2921: DELAY
PORT MAP ( Y => ix484_a5_dup_577_aCLK, IN1 => n_3554);
and1_2922: AND1
PORT MAP ( Y => ix484_a5_dup_577_aENA, IN1 => n_3558);
delay_2923: DELAY
PORT MAP ( Y => n_3558, IN1 => ix484_nx40_aOUT);
dffe_2924: DFFE
PORT MAP ( D => ix484_a1_dup_573_aD, CLK => ix484_a1_dup_573_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_573_aENA, Q => ix484_a1_dup_573_Q);
xor2_2925: XOR2
PORT MAP ( Y => ix484_a1_dup_573_aD, IN1 => n_3565, IN2 => n_3568);
or1_2926: OR1
PORT MAP ( Y => n_3565, IN1 => n_3566);
and1_2927: AND1
PORT MAP ( Y => n_3566, IN1 => n_3567);
delay_2928: DELAY
PORT MAP ( Y => n_3567, IN1 => data(10));
and1_2929: AND1
PORT MAP ( Y => n_3568, IN1 => gnd);
and1_2930: AND1
PORT MAP ( Y => n_3569, IN1 => n_3570);
delay_2931: DELAY
PORT MAP ( Y => n_3570, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2932: DELAY
PORT MAP ( Y => ix484_a1_dup_573_aCLK, IN1 => n_3569);
and1_2933: AND1
PORT MAP ( Y => ix484_a1_dup_573_aENA, IN1 => n_3573);
delay_2934: DELAY
PORT MAP ( Y => n_3573, IN1 => ix484_nx44_aOUT);
dffe_2935: DFFE
PORT MAP ( D => ix484_a5_dup_569_aD, CLK => ix484_a5_dup_569_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_569_aENA, Q => ix484_a5_dup_569_Q);
xor2_2936: XOR2
PORT MAP ( Y => ix484_a5_dup_569_aD, IN1 => n_3580, IN2 => n_3583);
or1_2937: OR1
PORT MAP ( Y => n_3580, IN1 => n_3581);
and1_2938: AND1
PORT MAP ( Y => n_3581, IN1 => n_3582);
delay_2939: DELAY
PORT MAP ( Y => n_3582, IN1 => data(10));
and1_2940: AND1
PORT MAP ( Y => n_3583, IN1 => gnd);
and1_2941: AND1
PORT MAP ( Y => n_3584, IN1 => n_3585);
delay_2942: DELAY
PORT MAP ( Y => n_3585, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2943: DELAY
PORT MAP ( Y => ix484_a5_dup_569_aCLK, IN1 => n_3584);
and1_2944: AND1
PORT MAP ( Y => ix484_a5_dup_569_aENA, IN1 => n_3588);
delay_2945: DELAY
PORT MAP ( Y => n_3588, IN1 => ix484_nx40_aOUT);
dffe_2946: DFFE
PORT MAP ( D => ix484_a1_dup_565_aD, CLK => ix484_a1_dup_565_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_565_aENA, Q => ix484_a1_dup_565_Q);
xor2_2947: XOR2
PORT MAP ( Y => ix484_a1_dup_565_aD, IN1 => n_3595, IN2 => n_3598);
or1_2948: OR1
PORT MAP ( Y => n_3595, IN1 => n_3596);
and1_2949: AND1
PORT MAP ( Y => n_3596, IN1 => n_3597);
delay_2950: DELAY
PORT MAP ( Y => n_3597, IN1 => data(11));
and1_2951: AND1
PORT MAP ( Y => n_3598, IN1 => gnd);
and1_2952: AND1
PORT MAP ( Y => n_3599, IN1 => n_3600);
delay_2953: DELAY
PORT MAP ( Y => n_3600, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2954: DELAY
PORT MAP ( Y => ix484_a1_dup_565_aCLK, IN1 => n_3599);
and1_2955: AND1
PORT MAP ( Y => ix484_a1_dup_565_aENA, IN1 => n_3603);
delay_2956: DELAY
PORT MAP ( Y => n_3603, IN1 => ix484_nx44_aOUT);
dffe_2957: DFFE
PORT MAP ( D => ix484_a5_dup_561_aD, CLK => ix484_a5_dup_561_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_561_aENA, Q => ix484_a5_dup_561_Q);
xor2_2958: XOR2
PORT MAP ( Y => ix484_a5_dup_561_aD, IN1 => n_3610, IN2 => n_3613);
or1_2959: OR1
PORT MAP ( Y => n_3610, IN1 => n_3611);
and1_2960: AND1
PORT MAP ( Y => n_3611, IN1 => n_3612);
delay_2961: DELAY
PORT MAP ( Y => n_3612, IN1 => data(11));
and1_2962: AND1
PORT MAP ( Y => n_3613, IN1 => gnd);
and1_2963: AND1
PORT MAP ( Y => n_3614, IN1 => n_3615);
delay_2964: DELAY
PORT MAP ( Y => n_3615, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2965: DELAY
PORT MAP ( Y => ix484_a5_dup_561_aCLK, IN1 => n_3614);
and1_2966: AND1
PORT MAP ( Y => ix484_a5_dup_561_aENA, IN1 => n_3618);
delay_2967: DELAY
PORT MAP ( Y => n_3618, IN1 => ix484_nx40_aOUT);
dffe_2968: DFFE
PORT MAP ( D => ix484_a1_dup_557_aD, CLK => ix484_a1_dup_557_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_557_aENA, Q => ix484_a1_dup_557_Q);
xor2_2969: XOR2
PORT MAP ( Y => ix484_a1_dup_557_aD, IN1 => n_3625, IN2 => n_3628);
or1_2970: OR1
PORT MAP ( Y => n_3625, IN1 => n_3626);
and1_2971: AND1
PORT MAP ( Y => n_3626, IN1 => n_3627);
delay_2972: DELAY
PORT MAP ( Y => n_3627, IN1 => data(12));
and1_2973: AND1
PORT MAP ( Y => n_3628, IN1 => gnd);
and1_2974: AND1
PORT MAP ( Y => n_3629, IN1 => n_3630);
delay_2975: DELAY
PORT MAP ( Y => n_3630, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2976: DELAY
PORT MAP ( Y => ix484_a1_dup_557_aCLK, IN1 => n_3629);
and1_2977: AND1
PORT MAP ( Y => ix484_a1_dup_557_aENA, IN1 => n_3633);
delay_2978: DELAY
PORT MAP ( Y => n_3633, IN1 => ix484_nx44_aOUT);
dffe_2979: DFFE
PORT MAP ( D => ix484_a5_dup_553_aD, CLK => ix484_a5_dup_553_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_553_aENA, Q => ix484_a5_dup_553_Q);
xor2_2980: XOR2
PORT MAP ( Y => ix484_a5_dup_553_aD, IN1 => n_3640, IN2 => n_3643);
or1_2981: OR1
PORT MAP ( Y => n_3640, IN1 => n_3641);
and1_2982: AND1
PORT MAP ( Y => n_3641, IN1 => n_3642);
delay_2983: DELAY
PORT MAP ( Y => n_3642, IN1 => data(12));
and1_2984: AND1
PORT MAP ( Y => n_3643, IN1 => gnd);
and1_2985: AND1
PORT MAP ( Y => n_3644, IN1 => n_3645);
delay_2986: DELAY
PORT MAP ( Y => n_3645, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2987: DELAY
PORT MAP ( Y => ix484_a5_dup_553_aCLK, IN1 => n_3644);
and1_2988: AND1
PORT MAP ( Y => ix484_a5_dup_553_aENA, IN1 => n_3648);
delay_2989: DELAY
PORT MAP ( Y => n_3648, IN1 => ix484_nx40_aOUT);
dffe_2990: DFFE
PORT MAP ( D => ix484_a1_dup_549_aD, CLK => ix484_a1_dup_549_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_549_aENA, Q => ix484_a1_dup_549_Q);
xor2_2991: XOR2
PORT MAP ( Y => ix484_a1_dup_549_aD, IN1 => n_3655, IN2 => n_3658);
or1_2992: OR1
PORT MAP ( Y => n_3655, IN1 => n_3656);
and1_2993: AND1
PORT MAP ( Y => n_3656, IN1 => n_3657);
delay_2994: DELAY
PORT MAP ( Y => n_3657, IN1 => data(13));
and1_2995: AND1
PORT MAP ( Y => n_3658, IN1 => gnd);
and1_2996: AND1
PORT MAP ( Y => n_3659, IN1 => n_3660);
delay_2997: DELAY
PORT MAP ( Y => n_3660, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_2998: DELAY
PORT MAP ( Y => ix484_a1_dup_549_aCLK, IN1 => n_3659);
and1_2999: AND1
PORT MAP ( Y => ix484_a1_dup_549_aENA, IN1 => n_3663);
delay_3000: DELAY
PORT MAP ( Y => n_3663, IN1 => ix484_nx44_aOUT);
dffe_3001: DFFE
PORT MAP ( D => ix484_a5_dup_545_aD, CLK => ix484_a5_dup_545_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_545_aENA, Q => ix484_a5_dup_545_Q);
xor2_3002: XOR2
PORT MAP ( Y => ix484_a5_dup_545_aD, IN1 => n_3670, IN2 => n_3673);
or1_3003: OR1
PORT MAP ( Y => n_3670, IN1 => n_3671);
and1_3004: AND1
PORT MAP ( Y => n_3671, IN1 => n_3672);
delay_3005: DELAY
PORT MAP ( Y => n_3672, IN1 => data(13));
and1_3006: AND1
PORT MAP ( Y => n_3673, IN1 => gnd);
and1_3007: AND1
PORT MAP ( Y => n_3674, IN1 => n_3675);
delay_3008: DELAY
PORT MAP ( Y => n_3675, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3009: DELAY
PORT MAP ( Y => ix484_a5_dup_545_aCLK, IN1 => n_3674);
and1_3010: AND1
PORT MAP ( Y => ix484_a5_dup_545_aENA, IN1 => n_3678);
delay_3011: DELAY
PORT MAP ( Y => n_3678, IN1 => ix484_nx40_aOUT);
dffe_3012: DFFE
PORT MAP ( D => ix484_a1_dup_541_aD, CLK => ix484_a1_dup_541_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_541_aENA, Q => ix484_a1_dup_541_Q);
xor2_3013: XOR2
PORT MAP ( Y => ix484_a1_dup_541_aD, IN1 => n_3685, IN2 => n_3688);
or1_3014: OR1
PORT MAP ( Y => n_3685, IN1 => n_3686);
and1_3015: AND1
PORT MAP ( Y => n_3686, IN1 => n_3687);
delay_3016: DELAY
PORT MAP ( Y => n_3687, IN1 => data(14));
and1_3017: AND1
PORT MAP ( Y => n_3688, IN1 => gnd);
and1_3018: AND1
PORT MAP ( Y => n_3689, IN1 => n_3690);
delay_3019: DELAY
PORT MAP ( Y => n_3690, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3020: DELAY
PORT MAP ( Y => ix484_a1_dup_541_aCLK, IN1 => n_3689);
and1_3021: AND1
PORT MAP ( Y => ix484_a1_dup_541_aENA, IN1 => n_3693);
delay_3022: DELAY
PORT MAP ( Y => n_3693, IN1 => ix484_nx44_aOUT);
dffe_3023: DFFE
PORT MAP ( D => ix484_a5_dup_537_aD, CLK => ix484_a5_dup_537_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a5_dup_537_aENA, Q => ix484_a5_dup_537_Q);
xor2_3024: XOR2
PORT MAP ( Y => ix484_a5_dup_537_aD, IN1 => n_3700, IN2 => n_3703);
or1_3025: OR1
PORT MAP ( Y => n_3700, IN1 => n_3701);
and1_3026: AND1
PORT MAP ( Y => n_3701, IN1 => n_3702);
delay_3027: DELAY
PORT MAP ( Y => n_3702, IN1 => data(14));
and1_3028: AND1
PORT MAP ( Y => n_3703, IN1 => gnd);
and1_3029: AND1
PORT MAP ( Y => n_3704, IN1 => n_3705);
delay_3030: DELAY
PORT MAP ( Y => n_3705, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3031: DELAY
PORT MAP ( Y => ix484_a5_dup_537_aCLK, IN1 => n_3704);
and1_3032: AND1
PORT MAP ( Y => ix484_a5_dup_537_aENA, IN1 => n_3708);
delay_3033: DELAY
PORT MAP ( Y => n_3708, IN1 => ix484_nx40_aOUT);
dff_3034: DFF
PORT MAP ( D => con1_current_state49_aD, CLK => con1_current_state49_aCLK,
CLRN => con1_current_state49_aCLRN, PRN => vcc, Q => con1_current_state49_Q);
inv_3035: INV
PORT MAP ( Y => con1_current_state49_aCLRN, IN1 => reset);
xor2_3036: XOR2
PORT MAP ( Y => con1_current_state49_aD, IN1 => n_3716, IN2 => n_3723);
or1_3037: OR1
PORT MAP ( Y => n_3716, IN1 => n_3717);
and4_3038: AND4
PORT MAP ( Y => n_3717, IN1 => n_3718, IN2 => n_3720, IN3 => n_3721, IN4 => n_3722);
inv_3039: INV
PORT MAP ( Y => n_3718, IN1 => I3_dup_732_aOUT);
delay_3040: DELAY
PORT MAP ( Y => n_3720, IN1 => instrregout11_Q);
delay_3041: DELAY
PORT MAP ( Y => n_3721, IN1 => instrregout12_Q);
delay_3042: DELAY
PORT MAP ( Y => n_3722, IN1 => con1_current_state6_Q);
and1_3043: AND1
PORT MAP ( Y => n_3723, IN1 => gnd);
delay_3044: DELAY
PORT MAP ( Y => con1_current_state49_aCLK, IN1 => clock);
dff_3045: DFF
PORT MAP ( D => con1_current_state19_aD, CLK => con1_current_state19_aCLK,
CLRN => con1_current_state19_aCLRN, PRN => vcc, Q => con1_current_state19_Q);
inv_3046: INV
PORT MAP ( Y => con1_current_state19_aCLRN, IN1 => reset);
xor2_3047: XOR2
PORT MAP ( Y => con1_current_state19_aD, IN1 => n_3731, IN2 => n_3734);
or1_3048: OR1
PORT MAP ( Y => n_3731, IN1 => n_3732);
and1_3049: AND1
PORT MAP ( Y => n_3732, IN1 => n_3733);
delay_3050: DELAY
PORT MAP ( Y => n_3733, IN1 => con1_current_state18_Q);
and1_3051: AND1
PORT MAP ( Y => n_3734, IN1 => gnd);
delay_3052: DELAY
PORT MAP ( Y => con1_current_state19_aCLK, IN1 => clock);
dff_3053: DFF
PORT MAP ( D => con1_current_state51_aD, CLK => con1_current_state51_aCLK,
CLRN => con1_current_state51_aCLRN, PRN => vcc, Q => con1_current_state51_Q);
inv_3054: INV
PORT MAP ( Y => con1_current_state51_aCLRN, IN1 => reset);
xor2_3055: XOR2
PORT MAP ( Y => con1_current_state51_aD, IN1 => n_3742, IN2 => n_3746);
or1_3056: OR1
PORT MAP ( Y => n_3742, IN1 => n_3743);
and1_3057: AND1
PORT MAP ( Y => n_3743, IN1 => n_3744);
delay_3058: DELAY
PORT MAP ( Y => n_3744, IN1 => con1_current_state50_Q);
and1_3059: AND1
PORT MAP ( Y => n_3746, IN1 => gnd);
delay_3060: DELAY
PORT MAP ( Y => con1_current_state51_aCLK, IN1 => clock);
dffe_3061: DFFE
PORT MAP ( D => ix484_a1_dup_533_aD, CLK => ix484_a1_dup_533_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a1_dup_533_aENA, Q => ix484_a1_dup_533_Q);
xor2_3062: XOR2
PORT MAP ( Y => ix484_a1_dup_533_aD, IN1 => n_3754, IN2 => n_3757);
or1_3063: OR1
PORT MAP ( Y => n_3754, IN1 => n_3755);
and1_3064: AND1
PORT MAP ( Y => n_3755, IN1 => n_3756);
delay_3065: DELAY
PORT MAP ( Y => n_3756, IN1 => data(15));
and1_3066: AND1
PORT MAP ( Y => n_3757, IN1 => gnd);
and1_3067: AND1
PORT MAP ( Y => n_3758, IN1 => n_3759);
delay_3068: DELAY
PORT MAP ( Y => n_3759, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3069: DELAY
PORT MAP ( Y => ix484_a1_dup_533_aCLK, IN1 => n_3758);
and1_3070: AND1
PORT MAP ( Y => ix484_a1_dup_533_aENA, IN1 => n_3762);
delay_3071: DELAY
PORT MAP ( Y => n_3762, IN1 => ix484_nx44_aOUT);
dffe_3072: DFFE
PORT MAP ( D => ix484_a5_aD, CLK => ix484_a5_aCLK, CLRN => vcc, PRN => vcc,
ENA => ix484_a5_aENA, Q => ix484_a5_Q);
xor2_3073: XOR2
PORT MAP ( Y => ix484_a5_aD, IN1 => n_3769, IN2 => n_3772);
or1_3074: OR1
PORT MAP ( Y => n_3769, IN1 => n_3770);
and1_3075: AND1
PORT MAP ( Y => n_3770, IN1 => n_3771);
delay_3076: DELAY
PORT MAP ( Y => n_3771, IN1 => data(15));
and1_3077: AND1
PORT MAP ( Y => n_3772, IN1 => gnd);
and1_3078: AND1
PORT MAP ( Y => n_3773, IN1 => n_3774);
delay_3079: DELAY
PORT MAP ( Y => n_3774, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3080: DELAY
PORT MAP ( Y => ix484_a5_aCLK, IN1 => n_3773);
and1_3081: AND1
PORT MAP ( Y => ix484_a5_aENA, IN1 => n_3777);
delay_3082: DELAY
PORT MAP ( Y => n_3777, IN1 => ix484_nx40_aOUT);
dff_3083: DFF
PORT MAP ( D => instrregout11_aD, CLK => instrregout11_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout11_Q);
xor2_3084: XOR2
PORT MAP ( Y => instrregout11_aD, IN1 => n_3783, IN2 => n_3786);
or1_3085: OR1
PORT MAP ( Y => n_3783, IN1 => n_3784);
and1_3086: AND1
PORT MAP ( Y => n_3784, IN1 => n_3785);
delay_3087: DELAY
PORT MAP ( Y => n_3785, IN1 => data(11));
and1_3088: AND1
PORT MAP ( Y => n_3786, IN1 => gnd);
and1_3089: AND1
PORT MAP ( Y => n_3787, IN1 => n_3788);
delay_3090: DELAY
PORT MAP ( Y => n_3788, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_3091: DELAY
PORT MAP ( Y => instrregout11_aCLK, IN1 => n_3787);
dff_3092: DFF
PORT MAP ( D => con1_current_state44_aD, CLK => con1_current_state44_aCLK,
CLRN => con1_current_state44_aCLRN, PRN => vcc, Q => con1_current_state44_Q);
inv_3093: INV
PORT MAP ( Y => con1_current_state44_aCLRN, IN1 => reset);
xor2_3094: XOR2
PORT MAP ( Y => con1_current_state44_aD, IN1 => n_3797, IN2 => n_3803);
or1_3095: OR1
PORT MAP ( Y => n_3797, IN1 => n_3798);
and4_3096: AND4
PORT MAP ( Y => n_3798, IN1 => n_3799, IN2 => n_3800, IN3 => n_3801, IN4 => n_3802);
inv_3097: INV
PORT MAP ( Y => n_3799, IN1 => instrregout12_Q);
inv_3098: INV
PORT MAP ( Y => n_3800, IN1 => instrregout11_Q);
inv_3099: INV
PORT MAP ( Y => n_3801, IN1 => I3_dup_732_aOUT);
delay_3100: DELAY
PORT MAP ( Y => n_3802, IN1 => con1_current_state6_Q);
and1_3101: AND1
PORT MAP ( Y => n_3803, IN1 => gnd);
delay_3102: DELAY
PORT MAP ( Y => con1_current_state44_aCLK, IN1 => clock);
dff_3103: DFF
PORT MAP ( D => con1_current_state39_aD, CLK => con1_current_state39_aCLK,
CLRN => con1_current_state39_aCLRN, PRN => vcc, Q => con1_current_state39_Q);
inv_3104: INV
PORT MAP ( Y => con1_current_state39_aCLRN, IN1 => reset);
xor2_3105: XOR2
PORT MAP ( Y => con1_current_state39_aD, IN1 => n_3812, IN2 => n_3818);
or1_3106: OR1
PORT MAP ( Y => n_3812, IN1 => n_3813);
and4_3107: AND4
PORT MAP ( Y => n_3813, IN1 => n_3814, IN2 => n_3815, IN3 => n_3816, IN4 => n_3817);
inv_3108: INV
PORT MAP ( Y => n_3814, IN1 => instrregout12_Q);
inv_3109: INV
PORT MAP ( Y => n_3815, IN1 => I3_dup_732_aOUT);
delay_3110: DELAY
PORT MAP ( Y => n_3816, IN1 => instrregout11_Q);
delay_3111: DELAY
PORT MAP ( Y => n_3817, IN1 => con1_current_state6_Q);
and1_3112: AND1
PORT MAP ( Y => n_3818, IN1 => gnd);
delay_3113: DELAY
PORT MAP ( Y => con1_current_state39_aCLK, IN1 => clock);
dff_3114: DFF
PORT MAP ( D => con1_current_state34_aD, CLK => con1_current_state34_aCLK,
CLRN => con1_current_state34_aCLRN, PRN => vcc, Q => con1_current_state34_Q);
inv_3115: INV
PORT MAP ( Y => con1_current_state34_aCLRN, IN1 => reset);
xor2_3116: XOR2
PORT MAP ( Y => con1_current_state34_aD, IN1 => n_3827, IN2 => n_3830);
or1_3117: OR1
PORT MAP ( Y => n_3827, IN1 => n_3828);
and1_3118: AND1
PORT MAP ( Y => n_3828, IN1 => n_3829);
delay_3119: DELAY
PORT MAP ( Y => n_3829, IN1 => con1_current_state33_Q);
and1_3120: AND1
PORT MAP ( Y => n_3830, IN1 => gnd);
delay_3121: DELAY
PORT MAP ( Y => con1_current_state34_aCLK, IN1 => clock);
delay_3122: DELAY
PORT MAP ( Y => I2_dup_689_aOUT, IN1 => I2_dup_689_aIN);
xor2_3123: XOR2
PORT MAP ( Y => I2_dup_689_aIN, IN1 => n_3834, IN2 => n_3841);
or2_3124: OR2
PORT MAP ( Y => n_3834, IN1 => n_3835, IN2 => n_3838);
and1_3125: AND1
PORT MAP ( Y => n_3835, IN1 => n_3836);
delay_3126: DELAY
PORT MAP ( Y => n_3836, IN1 => con1_current_state38_Q);
and1_3127: AND1
PORT MAP ( Y => n_3838, IN1 => n_3839);
delay_3128: DELAY
PORT MAP ( Y => n_3839, IN1 => con1_current_state43_Q);
and1_3129: AND1
PORT MAP ( Y => n_3841, IN1 => gnd);
delay_3130: DELAY
PORT MAP ( Y => a_as_or3_aix1652_a_a32_aOUT, IN1 => a_as_or3_aix1652_a_a32_aIN1);
xor2_3131: XOR2
PORT MAP ( Y => a_as_or3_aix1652_a_a32_aIN1, IN1 => n_3844, IN2 => n_3854);
or3_3132: OR3
PORT MAP ( Y => n_3844, IN1 => n_3845, IN2 => n_3848, IN3 => n_3851);
and1_3133: AND1
PORT MAP ( Y => n_3845, IN1 => n_3846);
delay_3134: DELAY
PORT MAP ( Y => n_3846, IN1 => con1_current_state23_Q);
and2_3135: AND2
PORT MAP ( Y => n_3848, IN1 => n_3849, IN2 => n_3850);
delay_3136: DELAY
PORT MAP ( Y => n_3849, IN1 => I2_dup_689_aOUT);
delay_3137: DELAY
PORT MAP ( Y => n_3850, IN1 => ready);
and1_3138: AND1
PORT MAP ( Y => n_3851, IN1 => n_3852);
delay_3139: DELAY
PORT MAP ( Y => n_3852, IN1 => I2_dup_681_aOUT);
and1_3140: AND1
PORT MAP ( Y => n_3854, IN1 => gnd);
dff_3141: DFF
PORT MAP ( D => progcntr_val0_aD, CLK => progcntr_val0_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val0_Q);
xor2_3142: XOR2
PORT MAP ( Y => progcntr_val0_aD, IN1 => n_3860, IN2 => n_3863);
or1_3143: OR1
PORT MAP ( Y => n_3860, IN1 => n_3861);
and1_3144: AND1
PORT MAP ( Y => n_3861, IN1 => n_3862);
delay_3145: DELAY
PORT MAP ( Y => n_3862, IN1 => data(0));
and1_3146: AND1
PORT MAP ( Y => n_3863, IN1 => gnd);
and1_3147: AND1
PORT MAP ( Y => n_3864, IN1 => n_3865);
delay_3148: DELAY
PORT MAP ( Y => n_3865, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3149: DELAY
PORT MAP ( Y => progcntr_val0_aCLK, IN1 => n_3864);
delay_3150: DELAY
PORT MAP ( Y => O_dup_914_aOUT, IN1 => O_dup_914_aIN);
xor2_3151: XOR2
PORT MAP ( Y => O_dup_914_aIN, IN1 => n_3869, IN2 => n_3875);
or2_3152: OR2
PORT MAP ( Y => n_3869, IN1 => n_3870, IN2 => n_3873);
and1_3153: AND1
PORT MAP ( Y => n_3870, IN1 => n_3871);
delay_3154: DELAY
PORT MAP ( Y => n_3871, IN1 => con1_current_state21_Q);
and1_3155: AND1
PORT MAP ( Y => n_3873, IN1 => n_3874);
delay_3156: DELAY
PORT MAP ( Y => n_3874, IN1 => con1_current_state49_Q);
and1_3157: AND1
PORT MAP ( Y => n_3875, IN1 => gnd);
delay_3158: DELAY
PORT MAP ( Y => I2_dup_679_aOUT, IN1 => I2_dup_679_aIN);
xor2_3159: XOR2
PORT MAP ( Y => I2_dup_679_aIN, IN1 => n_3878, IN2 => n_3888);
or4_3160: OR4
PORT MAP ( Y => n_3878, IN1 => n_3879, IN2 => n_3882, IN3 => n_3884, IN4 => n_3886);
and1_3161: AND1
PORT MAP ( Y => n_3879, IN1 => n_3880);
delay_3162: DELAY
PORT MAP ( Y => n_3880, IN1 => con1_current_state1_Q);
and1_3163: AND1
PORT MAP ( Y => n_3882, IN1 => n_3883);
delay_3164: DELAY
PORT MAP ( Y => n_3883, IN1 => O_dup_914_aOUT);
and1_3165: AND1
PORT MAP ( Y => n_3884, IN1 => n_3885);
delay_3166: DELAY
PORT MAP ( Y => n_3885, IN1 => con1_current_state34_Q);
and1_3167: AND1
PORT MAP ( Y => n_3886, IN1 => n_3887);
delay_3168: DELAY
PORT MAP ( Y => n_3887, IN1 => con1_current_state17_Q);
and1_3169: AND1
PORT MAP ( Y => n_3888, IN1 => gnd);
delay_3170: DELAY
PORT MAP ( Y => a_as_or3_aix1642_a_a32_aOUT, IN1 => a_as_or3_aix1642_a_a32_aIN1);
xor2_3171: XOR2
PORT MAP ( Y => a_as_or3_aix1642_a_a32_aIN1, IN1 => n_3891, IN2 => n_3898);
or3_3172: OR3
PORT MAP ( Y => n_3891, IN1 => n_3892, IN2 => n_3894, IN3 => n_3896);
and1_3173: AND1
PORT MAP ( Y => n_3892, IN1 => n_3893);
delay_3174: DELAY
PORT MAP ( Y => n_3893, IN1 => I2_dup_679_aOUT);
and1_3175: AND1
PORT MAP ( Y => n_3894, IN1 => n_3895);
delay_3176: DELAY
PORT MAP ( Y => n_3895, IN1 => con1_current_state39_Q);
and1_3177: AND1
PORT MAP ( Y => n_3896, IN1 => n_3897);
delay_3178: DELAY
PORT MAP ( Y => n_3897, IN1 => con1_current_state44_Q);
and1_3179: AND1
PORT MAP ( Y => n_3898, IN1 => gnd);
delay_3180: DELAY
PORT MAP ( Y => alu1_nx191_aOUT, IN1 => alu1_nx191_aIN);
xor2_3181: XOR2
PORT MAP ( Y => alu1_nx191_aIN, IN1 => n_3901, IN2 => n_3904);
or1_3182: OR1
PORT MAP ( Y => n_3901, IN1 => n_3902);
and1_3183: AND1
PORT MAP ( Y => n_3902, IN1 => n_3903);
inv_3184: INV
PORT MAP ( Y => n_3903, IN1 => data(0));
and1_3185: AND1
PORT MAP ( Y => n_3904, IN1 => gnd);
delay_3186: DELAY
PORT MAP ( Y => n4_aOUT, IN1 => n4_aIN);
xor2_3187: XOR2
PORT MAP ( Y => n4_aIN, IN1 => n_3907, IN2 => n_3915);
or3_3188: OR3
PORT MAP ( Y => n_3907, IN1 => n_3908, IN2 => n_3910, IN3 => n_3913);
and1_3189: AND1
PORT MAP ( Y => n_3908, IN1 => n_3909);
inv_3190: INV
PORT MAP ( Y => n_3909, IN1 => con1_current_state6_Q);
and2_3191: AND2
PORT MAP ( Y => n_3910, IN1 => n_3911, IN2 => n_3912);
inv_3192: INV
PORT MAP ( Y => n_3911, IN1 => instrregout11_Q);
delay_3193: DELAY
PORT MAP ( Y => n_3912, IN1 => instrregout12_Q);
and1_3194: AND1
PORT MAP ( Y => n_3913, IN1 => n_3914);
delay_3195: DELAY
PORT MAP ( Y => n_3914, IN1 => I3_dup_732_aOUT);
and1_3196: AND1
PORT MAP ( Y => n_3915, IN1 => gnd);
delay_3197: DELAY
PORT MAP ( Y => alusel2_aOUT, IN1 => alusel2_aIN);
xor2_3198: XOR2
PORT MAP ( Y => alusel2_aIN, IN1 => n_3918, IN2 => n_3928);
or4_3199: OR4
PORT MAP ( Y => n_3918, IN1 => n_3919, IN2 => n_3921, IN3 => n_3923, IN4 => n_3926);
and1_3200: AND1
PORT MAP ( Y => n_3919, IN1 => n_3920);
delay_3201: DELAY
PORT MAP ( Y => n_3920, IN1 => con1_current_state21_Q);
and1_3202: AND1
PORT MAP ( Y => n_3921, IN1 => n_3922);
inv_3203: INV
PORT MAP ( Y => n_3922, IN1 => n4_aOUT);
and1_3204: AND1
PORT MAP ( Y => n_3923, IN1 => n_3924);
delay_3205: DELAY
PORT MAP ( Y => n_3924, IN1 => I3_dup_696_aOUT);
and1_3206: AND1
PORT MAP ( Y => n_3926, IN1 => n_3927);
delay_3207: DELAY
PORT MAP ( Y => n_3927, IN1 => con1_current_state49_Q);
and1_3208: AND1
PORT MAP ( Y => n_3928, IN1 => gnd);
delay_3209: DELAY
PORT MAP ( Y => O_dup_867_aOUT, IN1 => O_dup_867_aIN);
xor2_3210: XOR2
PORT MAP ( Y => O_dup_867_aIN, IN1 => n_3931, IN2 => n_3937);
or1_3211: OR1
PORT MAP ( Y => n_3931, IN1 => n_3932);
and3_3212: AND3
PORT MAP ( Y => n_3932, IN1 => n_3933, IN2 => n_3934, IN3 => n_3935);
inv_3213: INV
PORT MAP ( Y => n_3933, IN1 => con1_current_state1_Q);
delay_3214: DELAY
PORT MAP ( Y => n_3934, IN1 => alusel2_aOUT);
delay_3215: DELAY
PORT MAP ( Y => n_3935, IN1 => con1_current_state0_aQ_aNOT);
and1_3216: AND1
PORT MAP ( Y => n_3937, IN1 => gnd);
delay_3217: DELAY
PORT MAP ( Y => I1_dup_669_aOUT, IN1 => I1_dup_669_aIN);
xor2_3218: XOR2
PORT MAP ( Y => I1_dup_669_aIN, IN1 => n_3940, IN2 => n_3944);
or1_3219: OR1
PORT MAP ( Y => n_3940, IN1 => n_3941);
and2_3220: AND2
PORT MAP ( Y => n_3941, IN1 => n_3942, IN2 => n_3943);
delay_3221: DELAY
PORT MAP ( Y => n_3942, IN1 => alu1_nx191_aOUT);
delay_3222: DELAY
PORT MAP ( Y => n_3943, IN1 => O_dup_867_aOUT);
and1_3223: AND1
PORT MAP ( Y => n_3944, IN1 => gnd);
delay_3224: DELAY
PORT MAP ( Y => alusel0_aOUT, IN1 => alusel0_aIN);
xor2_3225: XOR2
PORT MAP ( Y => alusel0_aIN, IN1 => n_3947, IN2 => n_3954);
or3_3226: OR3
PORT MAP ( Y => n_3947, IN1 => n_3948, IN2 => n_3950, IN3 => n_3952);
and1_3227: AND1
PORT MAP ( Y => n_3948, IN1 => n_3949);
delay_3228: DELAY
PORT MAP ( Y => n_3949, IN1 => con1_current_state1_Q);
and1_3229: AND1
PORT MAP ( Y => n_3950, IN1 => n_3951);
inv_3230: INV
PORT MAP ( Y => n_3951, IN1 => con1_current_state0_aQ_aNOT);
and1_3231: AND1
PORT MAP ( Y => n_3952, IN1 => n_3953);
delay_3232: DELAY
PORT MAP ( Y => n_3953, IN1 => alusel2_aOUT);
and1_3233: AND1
PORT MAP ( Y => n_3954, IN1 => gnd);
dff_3234: DFF
PORT MAP ( D => outreg_val0_aD, CLK => outreg_val0_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val0_Q);
xor2_3235: XOR2
PORT MAP ( Y => outreg_val0_aD, IN1 => n_3960, IN2 => n_3966);
or2_3236: OR2
PORT MAP ( Y => n_3960, IN1 => n_3961, IN2 => n_3963);
and1_3237: AND1
PORT MAP ( Y => n_3961, IN1 => n_3962);
delay_3238: DELAY
PORT MAP ( Y => n_3962, IN1 => I1_dup_669_aOUT);
and2_3239: AND2
PORT MAP ( Y => n_3963, IN1 => n_3964, IN2 => n_3965);
inv_3240: INV
PORT MAP ( Y => n_3964, IN1 => alusel0_aOUT);
delay_3241: DELAY
PORT MAP ( Y => n_3965, IN1 => data(0));
and1_3242: AND1
PORT MAP ( Y => n_3966, IN1 => gnd);
and1_3243: AND1
PORT MAP ( Y => n_3967, IN1 => n_3968);
delay_3244: DELAY
PORT MAP ( Y => n_3968, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3245: DELAY
PORT MAP ( Y => outreg_val0_aCLK, IN1 => n_3967);
dff_3246: DFF
PORT MAP ( D => progcntr_val1_aD, CLK => progcntr_val1_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val1_Q);
xor2_3247: XOR2
PORT MAP ( Y => progcntr_val1_aD, IN1 => n_3975, IN2 => n_3978);
or1_3248: OR1
PORT MAP ( Y => n_3975, IN1 => n_3976);
and1_3249: AND1
PORT MAP ( Y => n_3976, IN1 => n_3977);
delay_3250: DELAY
PORT MAP ( Y => n_3977, IN1 => data(1));
and1_3251: AND1
PORT MAP ( Y => n_3978, IN1 => gnd);
and1_3252: AND1
PORT MAP ( Y => n_3979, IN1 => n_3980);
delay_3253: DELAY
PORT MAP ( Y => n_3980, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3254: DELAY
PORT MAP ( Y => progcntr_val1_aCLK, IN1 => n_3979);
delay_3255: DELAY
PORT MAP ( Y => alu1_nx190_aOUT, IN1 => alu1_nx190_aIN);
xor2_3256: XOR2
PORT MAP ( Y => alu1_nx190_aIN, IN1 => n_3984, IN2 => n_3991);
or2_3257: OR2
PORT MAP ( Y => n_3984, IN1 => n_3985, IN2 => n_3988);
and2_3258: AND2
PORT MAP ( Y => n_3985, IN1 => n_3986, IN2 => n_3987);
inv_3259: INV
PORT MAP ( Y => n_3986, IN1 => data(1));
delay_3260: DELAY
PORT MAP ( Y => n_3987, IN1 => data(0));
and2_3261: AND2
PORT MAP ( Y => n_3988, IN1 => n_3989, IN2 => n_3990);
inv_3262: INV
PORT MAP ( Y => n_3989, IN1 => data(0));
delay_3263: DELAY
PORT MAP ( Y => n_3990, IN1 => data(1));
and1_3264: AND1
PORT MAP ( Y => n_3991, IN1 => gnd);
delay_3265: DELAY
PORT MAP ( Y => I1_dup_668_aOUT, IN1 => I1_dup_668_aIN);
xor2_3266: XOR2
PORT MAP ( Y => I1_dup_668_aIN, IN1 => n_3994, IN2 => n_3998);
or1_3267: OR1
PORT MAP ( Y => n_3994, IN1 => n_3995);
and2_3268: AND2
PORT MAP ( Y => n_3995, IN1 => n_3996, IN2 => n_3997);
delay_3269: DELAY
PORT MAP ( Y => n_3996, IN1 => O_dup_867_aOUT);
delay_3270: DELAY
PORT MAP ( Y => n_3997, IN1 => alu1_nx190_aOUT);
and1_3271: AND1
PORT MAP ( Y => n_3998, IN1 => gnd);
dff_3272: DFF
PORT MAP ( D => outreg_val1_aD, CLK => outreg_val1_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val1_Q);
xor2_3273: XOR2
PORT MAP ( Y => outreg_val1_aD, IN1 => n_4004, IN2 => n_4010);
or2_3274: OR2
PORT MAP ( Y => n_4004, IN1 => n_4005, IN2 => n_4007);
and1_3275: AND1
PORT MAP ( Y => n_4005, IN1 => n_4006);
delay_3276: DELAY
PORT MAP ( Y => n_4006, IN1 => I1_dup_668_aOUT);
and2_3277: AND2
PORT MAP ( Y => n_4007, IN1 => n_4008, IN2 => n_4009);
inv_3278: INV
PORT MAP ( Y => n_4008, IN1 => alusel0_aOUT);
delay_3279: DELAY
PORT MAP ( Y => n_4009, IN1 => data(1));
and1_3280: AND1
PORT MAP ( Y => n_4010, IN1 => gnd);
and1_3281: AND1
PORT MAP ( Y => n_4011, IN1 => n_4012);
delay_3282: DELAY
PORT MAP ( Y => n_4012, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3283: DELAY
PORT MAP ( Y => outreg_val1_aCLK, IN1 => n_4011);
dff_3284: DFF
PORT MAP ( D => progcntr_val2_aD, CLK => progcntr_val2_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val2_Q);
xor2_3285: XOR2
PORT MAP ( Y => progcntr_val2_aD, IN1 => n_4019, IN2 => n_4022);
or1_3286: OR1
PORT MAP ( Y => n_4019, IN1 => n_4020);
and1_3287: AND1
PORT MAP ( Y => n_4020, IN1 => n_4021);
delay_3288: DELAY
PORT MAP ( Y => n_4021, IN1 => data(2));
and1_3289: AND1
PORT MAP ( Y => n_4022, IN1 => gnd);
and1_3290: AND1
PORT MAP ( Y => n_4023, IN1 => n_4024);
delay_3291: DELAY
PORT MAP ( Y => n_4024, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3292: DELAY
PORT MAP ( Y => progcntr_val2_aCLK, IN1 => n_4023);
delay_3293: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int2_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int2_aIN);
xor2_3294: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int2_aIN, IN1 => n_4028, IN2 => n_4032);
or1_3295: OR1
PORT MAP ( Y => n_4028, IN1 => n_4029);
and2_3296: AND2
PORT MAP ( Y => n_4029, IN1 => n_4030, IN2 => n_4031);
delay_3297: DELAY
PORT MAP ( Y => n_4030, IN1 => data(0));
delay_3298: DELAY
PORT MAP ( Y => n_4031, IN1 => data(1));
and1_3299: AND1
PORT MAP ( Y => n_4032, IN1 => gnd);
delay_3300: DELAY
PORT MAP ( Y => alu1_nx189_aOUT, IN1 => alu1_nx189_aIN);
xor2_3301: XOR2
PORT MAP ( Y => alu1_nx189_aIN, IN1 => n_4035, IN2 => n_4042);
or2_3302: OR2
PORT MAP ( Y => n_4035, IN1 => n_4036, IN2 => n_4039);
and2_3303: AND2
PORT MAP ( Y => n_4036, IN1 => n_4037, IN2 => n_4038);
inv_3304: INV
PORT MAP ( Y => n_4037, IN1 => data(2));
delay_3305: DELAY
PORT MAP ( Y => n_4038, IN1 => alu1_modgen_34_l1_l0_c_int2_aOUT);
and2_3306: AND2
PORT MAP ( Y => n_4039, IN1 => n_4040, IN2 => n_4041);
inv_3307: INV
PORT MAP ( Y => n_4040, IN1 => alu1_modgen_34_l1_l0_c_int2_aOUT);
delay_3308: DELAY
PORT MAP ( Y => n_4041, IN1 => data(2));
and1_3309: AND1
PORT MAP ( Y => n_4042, IN1 => gnd);
delay_3310: DELAY
PORT MAP ( Y => I1_dup_667_aOUT, IN1 => I1_dup_667_aIN);
xor2_3311: XOR2
PORT MAP ( Y => I1_dup_667_aIN, IN1 => n_4045, IN2 => n_4049);
or1_3312: OR1
PORT MAP ( Y => n_4045, IN1 => n_4046);
and2_3313: AND2
PORT MAP ( Y => n_4046, IN1 => n_4047, IN2 => n_4048);
delay_3314: DELAY
PORT MAP ( Y => n_4047, IN1 => O_dup_867_aOUT);
delay_3315: DELAY
PORT MAP ( Y => n_4048, IN1 => alu1_nx189_aOUT);
and1_3316: AND1
PORT MAP ( Y => n_4049, IN1 => gnd);
dff_3317: DFF
PORT MAP ( D => outreg_val2_aD, CLK => outreg_val2_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val2_Q);
xor2_3318: XOR2
PORT MAP ( Y => outreg_val2_aD, IN1 => n_4055, IN2 => n_4061);
or2_3319: OR2
PORT MAP ( Y => n_4055, IN1 => n_4056, IN2 => n_4058);
and1_3320: AND1
PORT MAP ( Y => n_4056, IN1 => n_4057);
delay_3321: DELAY
PORT MAP ( Y => n_4057, IN1 => I1_dup_667_aOUT);
and2_3322: AND2
PORT MAP ( Y => n_4058, IN1 => n_4059, IN2 => n_4060);
inv_3323: INV
PORT MAP ( Y => n_4059, IN1 => alusel0_aOUT);
delay_3324: DELAY
PORT MAP ( Y => n_4060, IN1 => data(2));
and1_3325: AND1
PORT MAP ( Y => n_4061, IN1 => gnd);
and1_3326: AND1
PORT MAP ( Y => n_4062, IN1 => n_4063);
delay_3327: DELAY
PORT MAP ( Y => n_4063, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3328: DELAY
PORT MAP ( Y => outreg_val2_aCLK, IN1 => n_4062);
dff_3329: DFF
PORT MAP ( D => progcntr_val3_aD, CLK => progcntr_val3_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val3_Q);
xor2_3330: XOR2
PORT MAP ( Y => progcntr_val3_aD, IN1 => n_4070, IN2 => n_4073);
or1_3331: OR1
PORT MAP ( Y => n_4070, IN1 => n_4071);
and1_3332: AND1
PORT MAP ( Y => n_4071, IN1 => n_4072);
delay_3333: DELAY
PORT MAP ( Y => n_4072, IN1 => data(3));
and1_3334: AND1
PORT MAP ( Y => n_4073, IN1 => gnd);
and1_3335: AND1
PORT MAP ( Y => n_4074, IN1 => n_4075);
delay_3336: DELAY
PORT MAP ( Y => n_4075, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3337: DELAY
PORT MAP ( Y => progcntr_val3_aCLK, IN1 => n_4074);
delay_3338: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int3_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int3_aIN);
xor2_3339: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int3_aIN, IN1 => n_4079, IN2 => n_4083);
or1_3340: OR1
PORT MAP ( Y => n_4079, IN1 => n_4080);
and2_3341: AND2
PORT MAP ( Y => n_4080, IN1 => n_4081, IN2 => n_4082);
delay_3342: DELAY
PORT MAP ( Y => n_4081, IN1 => alu1_modgen_34_l1_l0_c_int2_aOUT);
delay_3343: DELAY
PORT MAP ( Y => n_4082, IN1 => data(2));
and1_3344: AND1
PORT MAP ( Y => n_4083, IN1 => gnd);
delay_3345: DELAY
PORT MAP ( Y => alu1_nx188_aOUT, IN1 => alu1_nx188_aIN);
xor2_3346: XOR2
PORT MAP ( Y => alu1_nx188_aIN, IN1 => n_4086, IN2 => n_4093);
or2_3347: OR2
PORT MAP ( Y => n_4086, IN1 => n_4087, IN2 => n_4090);
and2_3348: AND2
PORT MAP ( Y => n_4087, IN1 => n_4088, IN2 => n_4089);
inv_3349: INV
PORT MAP ( Y => n_4088, IN1 => data(3));
delay_3350: DELAY
PORT MAP ( Y => n_4089, IN1 => alu1_modgen_34_l1_l0_c_int3_aOUT);
and2_3351: AND2
PORT MAP ( Y => n_4090, IN1 => n_4091, IN2 => n_4092);
inv_3352: INV
PORT MAP ( Y => n_4091, IN1 => alu1_modgen_34_l1_l0_c_int3_aOUT);
delay_3353: DELAY
PORT MAP ( Y => n_4092, IN1 => data(3));
and1_3354: AND1
PORT MAP ( Y => n_4093, IN1 => gnd);
delay_3355: DELAY
PORT MAP ( Y => I1_dup_666_aOUT, IN1 => I1_dup_666_aIN);
xor2_3356: XOR2
PORT MAP ( Y => I1_dup_666_aIN, IN1 => n_4096, IN2 => n_4100);
or1_3357: OR1
PORT MAP ( Y => n_4096, IN1 => n_4097);
and2_3358: AND2
PORT MAP ( Y => n_4097, IN1 => n_4098, IN2 => n_4099);
delay_3359: DELAY
PORT MAP ( Y => n_4098, IN1 => O_dup_867_aOUT);
delay_3360: DELAY
PORT MAP ( Y => n_4099, IN1 => alu1_nx188_aOUT);
and1_3361: AND1
PORT MAP ( Y => n_4100, IN1 => gnd);
dff_3362: DFF
PORT MAP ( D => outreg_val3_aD, CLK => outreg_val3_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val3_Q);
xor2_3363: XOR2
PORT MAP ( Y => outreg_val3_aD, IN1 => n_4106, IN2 => n_4112);
or2_3364: OR2
PORT MAP ( Y => n_4106, IN1 => n_4107, IN2 => n_4109);
and1_3365: AND1
PORT MAP ( Y => n_4107, IN1 => n_4108);
delay_3366: DELAY
PORT MAP ( Y => n_4108, IN1 => I1_dup_666_aOUT);
and2_3367: AND2
PORT MAP ( Y => n_4109, IN1 => n_4110, IN2 => n_4111);
inv_3368: INV
PORT MAP ( Y => n_4110, IN1 => alusel0_aOUT);
delay_3369: DELAY
PORT MAP ( Y => n_4111, IN1 => data(3));
and1_3370: AND1
PORT MAP ( Y => n_4112, IN1 => gnd);
and1_3371: AND1
PORT MAP ( Y => n_4113, IN1 => n_4114);
delay_3372: DELAY
PORT MAP ( Y => n_4114, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3373: DELAY
PORT MAP ( Y => outreg_val3_aCLK, IN1 => n_4113);
dff_3374: DFF
PORT MAP ( D => progcntr_val4_aD, CLK => progcntr_val4_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val4_Q);
xor2_3375: XOR2
PORT MAP ( Y => progcntr_val4_aD, IN1 => n_4121, IN2 => n_4124);
or1_3376: OR1
PORT MAP ( Y => n_4121, IN1 => n_4122);
and1_3377: AND1
PORT MAP ( Y => n_4122, IN1 => n_4123);
delay_3378: DELAY
PORT MAP ( Y => n_4123, IN1 => data(4));
and1_3379: AND1
PORT MAP ( Y => n_4124, IN1 => gnd);
and1_3380: AND1
PORT MAP ( Y => n_4125, IN1 => n_4126);
delay_3381: DELAY
PORT MAP ( Y => n_4126, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3382: DELAY
PORT MAP ( Y => progcntr_val4_aCLK, IN1 => n_4125);
delay_3383: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int4_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int4_aIN);
xor2_3384: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int4_aIN, IN1 => n_4130, IN2 => n_4134);
or1_3385: OR1
PORT MAP ( Y => n_4130, IN1 => n_4131);
and2_3386: AND2
PORT MAP ( Y => n_4131, IN1 => n_4132, IN2 => n_4133);
delay_3387: DELAY
PORT MAP ( Y => n_4132, IN1 => alu1_modgen_34_l1_l0_c_int3_aOUT);
delay_3388: DELAY
PORT MAP ( Y => n_4133, IN1 => data(3));
and1_3389: AND1
PORT MAP ( Y => n_4134, IN1 => gnd);
delay_3390: DELAY
PORT MAP ( Y => alu1_nx187_aOUT, IN1 => alu1_nx187_aIN);
xor2_3391: XOR2
PORT MAP ( Y => alu1_nx187_aIN, IN1 => n_4137, IN2 => n_4144);
or2_3392: OR2
PORT MAP ( Y => n_4137, IN1 => n_4138, IN2 => n_4141);
and2_3393: AND2
PORT MAP ( Y => n_4138, IN1 => n_4139, IN2 => n_4140);
inv_3394: INV
PORT MAP ( Y => n_4139, IN1 => data(4));
delay_3395: DELAY
PORT MAP ( Y => n_4140, IN1 => alu1_modgen_34_l1_l0_c_int4_aOUT);
and2_3396: AND2
PORT MAP ( Y => n_4141, IN1 => n_4142, IN2 => n_4143);
inv_3397: INV
PORT MAP ( Y => n_4142, IN1 => alu1_modgen_34_l1_l0_c_int4_aOUT);
delay_3398: DELAY
PORT MAP ( Y => n_4143, IN1 => data(4));
and1_3399: AND1
PORT MAP ( Y => n_4144, IN1 => gnd);
delay_3400: DELAY
PORT MAP ( Y => I1_dup_665_aOUT, IN1 => I1_dup_665_aIN);
xor2_3401: XOR2
PORT MAP ( Y => I1_dup_665_aIN, IN1 => n_4147, IN2 => n_4151);
or1_3402: OR1
PORT MAP ( Y => n_4147, IN1 => n_4148);
and2_3403: AND2
PORT MAP ( Y => n_4148, IN1 => n_4149, IN2 => n_4150);
delay_3404: DELAY
PORT MAP ( Y => n_4149, IN1 => O_dup_867_aOUT);
delay_3405: DELAY
PORT MAP ( Y => n_4150, IN1 => alu1_nx187_aOUT);
and1_3406: AND1
PORT MAP ( Y => n_4151, IN1 => gnd);
dff_3407: DFF
PORT MAP ( D => outreg_val4_aD, CLK => outreg_val4_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val4_Q);
xor2_3408: XOR2
PORT MAP ( Y => outreg_val4_aD, IN1 => n_4157, IN2 => n_4163);
or2_3409: OR2
PORT MAP ( Y => n_4157, IN1 => n_4158, IN2 => n_4160);
and1_3410: AND1
PORT MAP ( Y => n_4158, IN1 => n_4159);
delay_3411: DELAY
PORT MAP ( Y => n_4159, IN1 => I1_dup_665_aOUT);
and2_3412: AND2
PORT MAP ( Y => n_4160, IN1 => n_4161, IN2 => n_4162);
inv_3413: INV
PORT MAP ( Y => n_4161, IN1 => alusel0_aOUT);
delay_3414: DELAY
PORT MAP ( Y => n_4162, IN1 => data(4));
and1_3415: AND1
PORT MAP ( Y => n_4163, IN1 => gnd);
and1_3416: AND1
PORT MAP ( Y => n_4164, IN1 => n_4165);
delay_3417: DELAY
PORT MAP ( Y => n_4165, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3418: DELAY
PORT MAP ( Y => outreg_val4_aCLK, IN1 => n_4164);
dff_3419: DFF
PORT MAP ( D => progcntr_val5_aD, CLK => progcntr_val5_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val5_Q);
xor2_3420: XOR2
PORT MAP ( Y => progcntr_val5_aD, IN1 => n_4172, IN2 => n_4175);
or1_3421: OR1
PORT MAP ( Y => n_4172, IN1 => n_4173);
and1_3422: AND1
PORT MAP ( Y => n_4173, IN1 => n_4174);
delay_3423: DELAY
PORT MAP ( Y => n_4174, IN1 => data(5));
and1_3424: AND1
PORT MAP ( Y => n_4175, IN1 => gnd);
and1_3425: AND1
PORT MAP ( Y => n_4176, IN1 => n_4177);
delay_3426: DELAY
PORT MAP ( Y => n_4177, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3427: DELAY
PORT MAP ( Y => progcntr_val5_aCLK, IN1 => n_4176);
delay_3428: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int5_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int5_aIN);
xor2_3429: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int5_aIN, IN1 => n_4181, IN2 => n_4185);
or1_3430: OR1
PORT MAP ( Y => n_4181, IN1 => n_4182);
and2_3431: AND2
PORT MAP ( Y => n_4182, IN1 => n_4183, IN2 => n_4184);
delay_3432: DELAY
PORT MAP ( Y => n_4183, IN1 => alu1_modgen_34_l1_l0_c_int4_aOUT);
delay_3433: DELAY
PORT MAP ( Y => n_4184, IN1 => data(4));
and1_3434: AND1
PORT MAP ( Y => n_4185, IN1 => gnd);
delay_3435: DELAY
PORT MAP ( Y => alu1_nx186_aOUT, IN1 => alu1_nx186_aIN);
xor2_3436: XOR2
PORT MAP ( Y => alu1_nx186_aIN, IN1 => n_4188, IN2 => n_4195);
or2_3437: OR2
PORT MAP ( Y => n_4188, IN1 => n_4189, IN2 => n_4192);
and2_3438: AND2
PORT MAP ( Y => n_4189, IN1 => n_4190, IN2 => n_4191);
inv_3439: INV
PORT MAP ( Y => n_4190, IN1 => data(5));
delay_3440: DELAY
PORT MAP ( Y => n_4191, IN1 => alu1_modgen_34_l1_l0_c_int5_aOUT);
and2_3441: AND2
PORT MAP ( Y => n_4192, IN1 => n_4193, IN2 => n_4194);
inv_3442: INV
PORT MAP ( Y => n_4193, IN1 => alu1_modgen_34_l1_l0_c_int5_aOUT);
delay_3443: DELAY
PORT MAP ( Y => n_4194, IN1 => data(5));
and1_3444: AND1
PORT MAP ( Y => n_4195, IN1 => gnd);
delay_3445: DELAY
PORT MAP ( Y => I1_dup_664_aOUT, IN1 => I1_dup_664_aIN);
xor2_3446: XOR2
PORT MAP ( Y => I1_dup_664_aIN, IN1 => n_4198, IN2 => n_4202);
or1_3447: OR1
PORT MAP ( Y => n_4198, IN1 => n_4199);
and2_3448: AND2
PORT MAP ( Y => n_4199, IN1 => n_4200, IN2 => n_4201);
delay_3449: DELAY
PORT MAP ( Y => n_4200, IN1 => O_dup_867_aOUT);
delay_3450: DELAY
PORT MAP ( Y => n_4201, IN1 => alu1_nx186_aOUT);
and1_3451: AND1
PORT MAP ( Y => n_4202, IN1 => gnd);
dff_3452: DFF
PORT MAP ( D => outreg_val5_aD, CLK => outreg_val5_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val5_Q);
xor2_3453: XOR2
PORT MAP ( Y => outreg_val5_aD, IN1 => n_4208, IN2 => n_4214);
or2_3454: OR2
PORT MAP ( Y => n_4208, IN1 => n_4209, IN2 => n_4211);
and1_3455: AND1
PORT MAP ( Y => n_4209, IN1 => n_4210);
delay_3456: DELAY
PORT MAP ( Y => n_4210, IN1 => I1_dup_664_aOUT);
and2_3457: AND2
PORT MAP ( Y => n_4211, IN1 => n_4212, IN2 => n_4213);
inv_3458: INV
PORT MAP ( Y => n_4212, IN1 => alusel0_aOUT);
delay_3459: DELAY
PORT MAP ( Y => n_4213, IN1 => data(5));
and1_3460: AND1
PORT MAP ( Y => n_4214, IN1 => gnd);
and1_3461: AND1
PORT MAP ( Y => n_4215, IN1 => n_4216);
delay_3462: DELAY
PORT MAP ( Y => n_4216, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3463: DELAY
PORT MAP ( Y => outreg_val5_aCLK, IN1 => n_4215);
dff_3464: DFF
PORT MAP ( D => progcntr_val6_aD, CLK => progcntr_val6_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val6_Q);
xor2_3465: XOR2
PORT MAP ( Y => progcntr_val6_aD, IN1 => n_4223, IN2 => n_4226);
or1_3466: OR1
PORT MAP ( Y => n_4223, IN1 => n_4224);
and1_3467: AND1
PORT MAP ( Y => n_4224, IN1 => n_4225);
delay_3468: DELAY
PORT MAP ( Y => n_4225, IN1 => data(6));
and1_3469: AND1
PORT MAP ( Y => n_4226, IN1 => gnd);
and1_3470: AND1
PORT MAP ( Y => n_4227, IN1 => n_4228);
delay_3471: DELAY
PORT MAP ( Y => n_4228, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3472: DELAY
PORT MAP ( Y => progcntr_val6_aCLK, IN1 => n_4227);
delay_3473: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int6_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int6_aIN);
xor2_3474: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int6_aIN, IN1 => n_4232, IN2 => n_4236);
or1_3475: OR1
PORT MAP ( Y => n_4232, IN1 => n_4233);
and2_3476: AND2
PORT MAP ( Y => n_4233, IN1 => n_4234, IN2 => n_4235);
delay_3477: DELAY
PORT MAP ( Y => n_4234, IN1 => alu1_modgen_34_l1_l0_c_int5_aOUT);
delay_3478: DELAY
PORT MAP ( Y => n_4235, IN1 => data(5));
and1_3479: AND1
PORT MAP ( Y => n_4236, IN1 => gnd);
delay_3480: DELAY
PORT MAP ( Y => alu1_nx185_aOUT, IN1 => alu1_nx185_aIN);
xor2_3481: XOR2
PORT MAP ( Y => alu1_nx185_aIN, IN1 => n_4239, IN2 => n_4246);
or2_3482: OR2
PORT MAP ( Y => n_4239, IN1 => n_4240, IN2 => n_4243);
and2_3483: AND2
PORT MAP ( Y => n_4240, IN1 => n_4241, IN2 => n_4242);
inv_3484: INV
PORT MAP ( Y => n_4241, IN1 => data(6));
delay_3485: DELAY
PORT MAP ( Y => n_4242, IN1 => alu1_modgen_34_l1_l0_c_int6_aOUT);
and2_3486: AND2
PORT MAP ( Y => n_4243, IN1 => n_4244, IN2 => n_4245);
inv_3487: INV
PORT MAP ( Y => n_4244, IN1 => alu1_modgen_34_l1_l0_c_int6_aOUT);
delay_3488: DELAY
PORT MAP ( Y => n_4245, IN1 => data(6));
and1_3489: AND1
PORT MAP ( Y => n_4246, IN1 => gnd);
delay_3490: DELAY
PORT MAP ( Y => I1_dup_663_aOUT, IN1 => I1_dup_663_aIN);
xor2_3491: XOR2
PORT MAP ( Y => I1_dup_663_aIN, IN1 => n_4249, IN2 => n_4253);
or1_3492: OR1
PORT MAP ( Y => n_4249, IN1 => n_4250);
and2_3493: AND2
PORT MAP ( Y => n_4250, IN1 => n_4251, IN2 => n_4252);
delay_3494: DELAY
PORT MAP ( Y => n_4251, IN1 => O_dup_867_aOUT);
delay_3495: DELAY
PORT MAP ( Y => n_4252, IN1 => alu1_nx185_aOUT);
and1_3496: AND1
PORT MAP ( Y => n_4253, IN1 => gnd);
dff_3497: DFF
PORT MAP ( D => outreg_val6_aD, CLK => outreg_val6_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val6_Q);
xor2_3498: XOR2
PORT MAP ( Y => outreg_val6_aD, IN1 => n_4259, IN2 => n_4265);
or2_3499: OR2
PORT MAP ( Y => n_4259, IN1 => n_4260, IN2 => n_4262);
and1_3500: AND1
PORT MAP ( Y => n_4260, IN1 => n_4261);
delay_3501: DELAY
PORT MAP ( Y => n_4261, IN1 => I1_dup_663_aOUT);
and2_3502: AND2
PORT MAP ( Y => n_4262, IN1 => n_4263, IN2 => n_4264);
inv_3503: INV
PORT MAP ( Y => n_4263, IN1 => alusel0_aOUT);
delay_3504: DELAY
PORT MAP ( Y => n_4264, IN1 => data(6));
and1_3505: AND1
PORT MAP ( Y => n_4265, IN1 => gnd);
and1_3506: AND1
PORT MAP ( Y => n_4266, IN1 => n_4267);
delay_3507: DELAY
PORT MAP ( Y => n_4267, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3508: DELAY
PORT MAP ( Y => outreg_val6_aCLK, IN1 => n_4266);
dff_3509: DFF
PORT MAP ( D => progcntr_val7_aD, CLK => progcntr_val7_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val7_Q);
xor2_3510: XOR2
PORT MAP ( Y => progcntr_val7_aD, IN1 => n_4274, IN2 => n_4277);
or1_3511: OR1
PORT MAP ( Y => n_4274, IN1 => n_4275);
and1_3512: AND1
PORT MAP ( Y => n_4275, IN1 => n_4276);
delay_3513: DELAY
PORT MAP ( Y => n_4276, IN1 => data(7));
and1_3514: AND1
PORT MAP ( Y => n_4277, IN1 => gnd);
and1_3515: AND1
PORT MAP ( Y => n_4278, IN1 => n_4279);
delay_3516: DELAY
PORT MAP ( Y => n_4279, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3517: DELAY
PORT MAP ( Y => progcntr_val7_aCLK, IN1 => n_4278);
delay_3518: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int7_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int7_aIN);
xor2_3519: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int7_aIN, IN1 => n_4283, IN2 => n_4287);
or1_3520: OR1
PORT MAP ( Y => n_4283, IN1 => n_4284);
and2_3521: AND2
PORT MAP ( Y => n_4284, IN1 => n_4285, IN2 => n_4286);
delay_3522: DELAY
PORT MAP ( Y => n_4285, IN1 => alu1_modgen_34_l1_l0_c_int6_aOUT);
delay_3523: DELAY
PORT MAP ( Y => n_4286, IN1 => data(6));
and1_3524: AND1
PORT MAP ( Y => n_4287, IN1 => gnd);
delay_3525: DELAY
PORT MAP ( Y => alu1_nx184_aOUT, IN1 => alu1_nx184_aIN);
xor2_3526: XOR2
PORT MAP ( Y => alu1_nx184_aIN, IN1 => n_4290, IN2 => n_4297);
or2_3527: OR2
PORT MAP ( Y => n_4290, IN1 => n_4291, IN2 => n_4294);
and2_3528: AND2
PORT MAP ( Y => n_4291, IN1 => n_4292, IN2 => n_4293);
inv_3529: INV
PORT MAP ( Y => n_4292, IN1 => data(7));
delay_3530: DELAY
PORT MAP ( Y => n_4293, IN1 => alu1_modgen_34_l1_l0_c_int7_aOUT);
and2_3531: AND2
PORT MAP ( Y => n_4294, IN1 => n_4295, IN2 => n_4296);
inv_3532: INV
PORT MAP ( Y => n_4295, IN1 => alu1_modgen_34_l1_l0_c_int7_aOUT);
delay_3533: DELAY
PORT MAP ( Y => n_4296, IN1 => data(7));
and1_3534: AND1
PORT MAP ( Y => n_4297, IN1 => gnd);
delay_3535: DELAY
PORT MAP ( Y => I1_dup_662_aOUT, IN1 => I1_dup_662_aIN);
xor2_3536: XOR2
PORT MAP ( Y => I1_dup_662_aIN, IN1 => n_4300, IN2 => n_4304);
or1_3537: OR1
PORT MAP ( Y => n_4300, IN1 => n_4301);
and2_3538: AND2
PORT MAP ( Y => n_4301, IN1 => n_4302, IN2 => n_4303);
delay_3539: DELAY
PORT MAP ( Y => n_4302, IN1 => O_dup_867_aOUT);
delay_3540: DELAY
PORT MAP ( Y => n_4303, IN1 => alu1_nx184_aOUT);
and1_3541: AND1
PORT MAP ( Y => n_4304, IN1 => gnd);
dff_3542: DFF
PORT MAP ( D => outreg_val7_aD, CLK => outreg_val7_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val7_Q);
xor2_3543: XOR2
PORT MAP ( Y => outreg_val7_aD, IN1 => n_4310, IN2 => n_4316);
or2_3544: OR2
PORT MAP ( Y => n_4310, IN1 => n_4311, IN2 => n_4313);
and1_3545: AND1
PORT MAP ( Y => n_4311, IN1 => n_4312);
delay_3546: DELAY
PORT MAP ( Y => n_4312, IN1 => I1_dup_662_aOUT);
and2_3547: AND2
PORT MAP ( Y => n_4313, IN1 => n_4314, IN2 => n_4315);
inv_3548: INV
PORT MAP ( Y => n_4314, IN1 => alusel0_aOUT);
delay_3549: DELAY
PORT MAP ( Y => n_4315, IN1 => data(7));
and1_3550: AND1
PORT MAP ( Y => n_4316, IN1 => gnd);
and1_3551: AND1
PORT MAP ( Y => n_4317, IN1 => n_4318);
delay_3552: DELAY
PORT MAP ( Y => n_4318, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3553: DELAY
PORT MAP ( Y => outreg_val7_aCLK, IN1 => n_4317);
dff_3554: DFF
PORT MAP ( D => progcntr_val8_aD, CLK => progcntr_val8_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val8_Q);
xor2_3555: XOR2
PORT MAP ( Y => progcntr_val8_aD, IN1 => n_4325, IN2 => n_4328);
or1_3556: OR1
PORT MAP ( Y => n_4325, IN1 => n_4326);
and1_3557: AND1
PORT MAP ( Y => n_4326, IN1 => n_4327);
delay_3558: DELAY
PORT MAP ( Y => n_4327, IN1 => data(8));
and1_3559: AND1
PORT MAP ( Y => n_4328, IN1 => gnd);
and1_3560: AND1
PORT MAP ( Y => n_4329, IN1 => n_4330);
delay_3561: DELAY
PORT MAP ( Y => n_4330, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3562: DELAY
PORT MAP ( Y => progcntr_val8_aCLK, IN1 => n_4329);
delay_3563: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int8_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int8_aIN);
xor2_3564: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int8_aIN, IN1 => n_4334, IN2 => n_4338);
or1_3565: OR1
PORT MAP ( Y => n_4334, IN1 => n_4335);
and2_3566: AND2
PORT MAP ( Y => n_4335, IN1 => n_4336, IN2 => n_4337);
delay_3567: DELAY
PORT MAP ( Y => n_4336, IN1 => alu1_modgen_34_l1_l0_c_int7_aOUT);
delay_3568: DELAY
PORT MAP ( Y => n_4337, IN1 => data(7));
and1_3569: AND1
PORT MAP ( Y => n_4338, IN1 => gnd);
delay_3570: DELAY
PORT MAP ( Y => alu1_nx183_aOUT, IN1 => alu1_nx183_aIN);
xor2_3571: XOR2
PORT MAP ( Y => alu1_nx183_aIN, IN1 => n_4341, IN2 => n_4348);
or2_3572: OR2
PORT MAP ( Y => n_4341, IN1 => n_4342, IN2 => n_4345);
and2_3573: AND2
PORT MAP ( Y => n_4342, IN1 => n_4343, IN2 => n_4344);
inv_3574: INV
PORT MAP ( Y => n_4343, IN1 => data(8));
delay_3575: DELAY
PORT MAP ( Y => n_4344, IN1 => alu1_modgen_34_l1_l0_c_int8_aOUT);
and2_3576: AND2
PORT MAP ( Y => n_4345, IN1 => n_4346, IN2 => n_4347);
inv_3577: INV
PORT MAP ( Y => n_4346, IN1 => alu1_modgen_34_l1_l0_c_int8_aOUT);
delay_3578: DELAY
PORT MAP ( Y => n_4347, IN1 => data(8));
and1_3579: AND1
PORT MAP ( Y => n_4348, IN1 => gnd);
delay_3580: DELAY
PORT MAP ( Y => I1_dup_661_aOUT, IN1 => I1_dup_661_aIN);
xor2_3581: XOR2
PORT MAP ( Y => I1_dup_661_aIN, IN1 => n_4351, IN2 => n_4355);
or1_3582: OR1
PORT MAP ( Y => n_4351, IN1 => n_4352);
and2_3583: AND2
PORT MAP ( Y => n_4352, IN1 => n_4353, IN2 => n_4354);
delay_3584: DELAY
PORT MAP ( Y => n_4353, IN1 => O_dup_867_aOUT);
delay_3585: DELAY
PORT MAP ( Y => n_4354, IN1 => alu1_nx183_aOUT);
and1_3586: AND1
PORT MAP ( Y => n_4355, IN1 => gnd);
dff_3587: DFF
PORT MAP ( D => outreg_val8_aD, CLK => outreg_val8_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val8_Q);
xor2_3588: XOR2
PORT MAP ( Y => outreg_val8_aD, IN1 => n_4361, IN2 => n_4367);
or2_3589: OR2
PORT MAP ( Y => n_4361, IN1 => n_4362, IN2 => n_4364);
and1_3590: AND1
PORT MAP ( Y => n_4362, IN1 => n_4363);
delay_3591: DELAY
PORT MAP ( Y => n_4363, IN1 => I1_dup_661_aOUT);
and2_3592: AND2
PORT MAP ( Y => n_4364, IN1 => n_4365, IN2 => n_4366);
inv_3593: INV
PORT MAP ( Y => n_4365, IN1 => alusel0_aOUT);
delay_3594: DELAY
PORT MAP ( Y => n_4366, IN1 => data(8));
and1_3595: AND1
PORT MAP ( Y => n_4367, IN1 => gnd);
and1_3596: AND1
PORT MAP ( Y => n_4368, IN1 => n_4369);
delay_3597: DELAY
PORT MAP ( Y => n_4369, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3598: DELAY
PORT MAP ( Y => outreg_val8_aCLK, IN1 => n_4368);
dff_3599: DFF
PORT MAP ( D => progcntr_val9_aD, CLK => progcntr_val9_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val9_Q);
xor2_3600: XOR2
PORT MAP ( Y => progcntr_val9_aD, IN1 => n_4376, IN2 => n_4379);
or1_3601: OR1
PORT MAP ( Y => n_4376, IN1 => n_4377);
and1_3602: AND1
PORT MAP ( Y => n_4377, IN1 => n_4378);
delay_3603: DELAY
PORT MAP ( Y => n_4378, IN1 => data(9));
and1_3604: AND1
PORT MAP ( Y => n_4379, IN1 => gnd);
and1_3605: AND1
PORT MAP ( Y => n_4380, IN1 => n_4381);
delay_3606: DELAY
PORT MAP ( Y => n_4381, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3607: DELAY
PORT MAP ( Y => progcntr_val9_aCLK, IN1 => n_4380);
delay_3608: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int9_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int9_aIN);
xor2_3609: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int9_aIN, IN1 => n_4385, IN2 => n_4389);
or1_3610: OR1
PORT MAP ( Y => n_4385, IN1 => n_4386);
and2_3611: AND2
PORT MAP ( Y => n_4386, IN1 => n_4387, IN2 => n_4388);
delay_3612: DELAY
PORT MAP ( Y => n_4387, IN1 => alu1_modgen_34_l1_l0_c_int8_aOUT);
delay_3613: DELAY
PORT MAP ( Y => n_4388, IN1 => data(8));
and1_3614: AND1
PORT MAP ( Y => n_4389, IN1 => gnd);
delay_3615: DELAY
PORT MAP ( Y => alu1_nx182_aOUT, IN1 => alu1_nx182_aIN);
xor2_3616: XOR2
PORT MAP ( Y => alu1_nx182_aIN, IN1 => n_4392, IN2 => n_4399);
or2_3617: OR2
PORT MAP ( Y => n_4392, IN1 => n_4393, IN2 => n_4396);
and2_3618: AND2
PORT MAP ( Y => n_4393, IN1 => n_4394, IN2 => n_4395);
inv_3619: INV
PORT MAP ( Y => n_4394, IN1 => data(9));
delay_3620: DELAY
PORT MAP ( Y => n_4395, IN1 => alu1_modgen_34_l1_l0_c_int9_aOUT);
and2_3621: AND2
PORT MAP ( Y => n_4396, IN1 => n_4397, IN2 => n_4398);
inv_3622: INV
PORT MAP ( Y => n_4397, IN1 => alu1_modgen_34_l1_l0_c_int9_aOUT);
delay_3623: DELAY
PORT MAP ( Y => n_4398, IN1 => data(9));
and1_3624: AND1
PORT MAP ( Y => n_4399, IN1 => gnd);
delay_3625: DELAY
PORT MAP ( Y => I1_dup_660_aOUT, IN1 => I1_dup_660_aIN);
xor2_3626: XOR2
PORT MAP ( Y => I1_dup_660_aIN, IN1 => n_4402, IN2 => n_4406);
or1_3627: OR1
PORT MAP ( Y => n_4402, IN1 => n_4403);
and2_3628: AND2
PORT MAP ( Y => n_4403, IN1 => n_4404, IN2 => n_4405);
delay_3629: DELAY
PORT MAP ( Y => n_4404, IN1 => O_dup_867_aOUT);
delay_3630: DELAY
PORT MAP ( Y => n_4405, IN1 => alu1_nx182_aOUT);
and1_3631: AND1
PORT MAP ( Y => n_4406, IN1 => gnd);
dff_3632: DFF
PORT MAP ( D => outreg_val9_aD, CLK => outreg_val9_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val9_Q);
xor2_3633: XOR2
PORT MAP ( Y => outreg_val9_aD, IN1 => n_4412, IN2 => n_4418);
or2_3634: OR2
PORT MAP ( Y => n_4412, IN1 => n_4413, IN2 => n_4415);
and1_3635: AND1
PORT MAP ( Y => n_4413, IN1 => n_4414);
delay_3636: DELAY
PORT MAP ( Y => n_4414, IN1 => I1_dup_660_aOUT);
and2_3637: AND2
PORT MAP ( Y => n_4415, IN1 => n_4416, IN2 => n_4417);
inv_3638: INV
PORT MAP ( Y => n_4416, IN1 => alusel0_aOUT);
delay_3639: DELAY
PORT MAP ( Y => n_4417, IN1 => data(9));
and1_3640: AND1
PORT MAP ( Y => n_4418, IN1 => gnd);
and1_3641: AND1
PORT MAP ( Y => n_4419, IN1 => n_4420);
delay_3642: DELAY
PORT MAP ( Y => n_4420, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3643: DELAY
PORT MAP ( Y => outreg_val9_aCLK, IN1 => n_4419);
dff_3644: DFF
PORT MAP ( D => progcntr_val10_aD, CLK => progcntr_val10_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val10_Q);
xor2_3645: XOR2
PORT MAP ( Y => progcntr_val10_aD, IN1 => n_4427, IN2 => n_4430);
or1_3646: OR1
PORT MAP ( Y => n_4427, IN1 => n_4428);
and1_3647: AND1
PORT MAP ( Y => n_4428, IN1 => n_4429);
delay_3648: DELAY
PORT MAP ( Y => n_4429, IN1 => data(10));
and1_3649: AND1
PORT MAP ( Y => n_4430, IN1 => gnd);
and1_3650: AND1
PORT MAP ( Y => n_4431, IN1 => n_4432);
delay_3651: DELAY
PORT MAP ( Y => n_4432, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3652: DELAY
PORT MAP ( Y => progcntr_val10_aCLK, IN1 => n_4431);
delay_3653: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int10_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int10_aIN);
xor2_3654: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int10_aIN, IN1 => n_4436, IN2 => n_4440);
or1_3655: OR1
PORT MAP ( Y => n_4436, IN1 => n_4437);
and2_3656: AND2
PORT MAP ( Y => n_4437, IN1 => n_4438, IN2 => n_4439);
delay_3657: DELAY
PORT MAP ( Y => n_4438, IN1 => alu1_modgen_34_l1_l0_c_int9_aOUT);
delay_3658: DELAY
PORT MAP ( Y => n_4439, IN1 => data(9));
and1_3659: AND1
PORT MAP ( Y => n_4440, IN1 => gnd);
delay_3660: DELAY
PORT MAP ( Y => alu1_nx181_aOUT, IN1 => alu1_nx181_aIN);
xor2_3661: XOR2
PORT MAP ( Y => alu1_nx181_aIN, IN1 => n_4443, IN2 => n_4450);
or2_3662: OR2
PORT MAP ( Y => n_4443, IN1 => n_4444, IN2 => n_4447);
and2_3663: AND2
PORT MAP ( Y => n_4444, IN1 => n_4445, IN2 => n_4446);
inv_3664: INV
PORT MAP ( Y => n_4445, IN1 => data(10));
delay_3665: DELAY
PORT MAP ( Y => n_4446, IN1 => alu1_modgen_34_l1_l0_c_int10_aOUT);
and2_3666: AND2
PORT MAP ( Y => n_4447, IN1 => n_4448, IN2 => n_4449);
inv_3667: INV
PORT MAP ( Y => n_4448, IN1 => alu1_modgen_34_l1_l0_c_int10_aOUT);
delay_3668: DELAY
PORT MAP ( Y => n_4449, IN1 => data(10));
and1_3669: AND1
PORT MAP ( Y => n_4450, IN1 => gnd);
delay_3670: DELAY
PORT MAP ( Y => I1_dup_659_aOUT, IN1 => I1_dup_659_aIN);
xor2_3671: XOR2
PORT MAP ( Y => I1_dup_659_aIN, IN1 => n_4453, IN2 => n_4457);
or1_3672: OR1
PORT MAP ( Y => n_4453, IN1 => n_4454);
and2_3673: AND2
PORT MAP ( Y => n_4454, IN1 => n_4455, IN2 => n_4456);
delay_3674: DELAY
PORT MAP ( Y => n_4455, IN1 => O_dup_867_aOUT);
delay_3675: DELAY
PORT MAP ( Y => n_4456, IN1 => alu1_nx181_aOUT);
and1_3676: AND1
PORT MAP ( Y => n_4457, IN1 => gnd);
dff_3677: DFF
PORT MAP ( D => outreg_val10_aD, CLK => outreg_val10_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val10_Q);
xor2_3678: XOR2
PORT MAP ( Y => outreg_val10_aD, IN1 => n_4463, IN2 => n_4469);
or2_3679: OR2
PORT MAP ( Y => n_4463, IN1 => n_4464, IN2 => n_4466);
and1_3680: AND1
PORT MAP ( Y => n_4464, IN1 => n_4465);
delay_3681: DELAY
PORT MAP ( Y => n_4465, IN1 => I1_dup_659_aOUT);
and2_3682: AND2
PORT MAP ( Y => n_4466, IN1 => n_4467, IN2 => n_4468);
inv_3683: INV
PORT MAP ( Y => n_4467, IN1 => alusel0_aOUT);
delay_3684: DELAY
PORT MAP ( Y => n_4468, IN1 => data(10));
and1_3685: AND1
PORT MAP ( Y => n_4469, IN1 => gnd);
and1_3686: AND1
PORT MAP ( Y => n_4470, IN1 => n_4471);
delay_3687: DELAY
PORT MAP ( Y => n_4471, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3688: DELAY
PORT MAP ( Y => outreg_val10_aCLK, IN1 => n_4470);
dff_3689: DFF
PORT MAP ( D => progcntr_val11_aD, CLK => progcntr_val11_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val11_Q);
xor2_3690: XOR2
PORT MAP ( Y => progcntr_val11_aD, IN1 => n_4478, IN2 => n_4481);
or1_3691: OR1
PORT MAP ( Y => n_4478, IN1 => n_4479);
and1_3692: AND1
PORT MAP ( Y => n_4479, IN1 => n_4480);
delay_3693: DELAY
PORT MAP ( Y => n_4480, IN1 => data(11));
and1_3694: AND1
PORT MAP ( Y => n_4481, IN1 => gnd);
and1_3695: AND1
PORT MAP ( Y => n_4482, IN1 => n_4483);
delay_3696: DELAY
PORT MAP ( Y => n_4483, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3697: DELAY
PORT MAP ( Y => progcntr_val11_aCLK, IN1 => n_4482);
delay_3698: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int11_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int11_aIN);
xor2_3699: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int11_aIN, IN1 => n_4487, IN2 => n_4491);
or1_3700: OR1
PORT MAP ( Y => n_4487, IN1 => n_4488);
and2_3701: AND2
PORT MAP ( Y => n_4488, IN1 => n_4489, IN2 => n_4490);
delay_3702: DELAY
PORT MAP ( Y => n_4489, IN1 => alu1_modgen_34_l1_l0_c_int10_aOUT);
delay_3703: DELAY
PORT MAP ( Y => n_4490, IN1 => data(10));
and1_3704: AND1
PORT MAP ( Y => n_4491, IN1 => gnd);
delay_3705: DELAY
PORT MAP ( Y => alu1_nx180_aOUT, IN1 => alu1_nx180_aIN);
xor2_3706: XOR2
PORT MAP ( Y => alu1_nx180_aIN, IN1 => n_4494, IN2 => n_4501);
or2_3707: OR2
PORT MAP ( Y => n_4494, IN1 => n_4495, IN2 => n_4498);
and2_3708: AND2
PORT MAP ( Y => n_4495, IN1 => n_4496, IN2 => n_4497);
inv_3709: INV
PORT MAP ( Y => n_4496, IN1 => data(11));
delay_3710: DELAY
PORT MAP ( Y => n_4497, IN1 => alu1_modgen_34_l1_l0_c_int11_aOUT);
and2_3711: AND2
PORT MAP ( Y => n_4498, IN1 => n_4499, IN2 => n_4500);
inv_3712: INV
PORT MAP ( Y => n_4499, IN1 => alu1_modgen_34_l1_l0_c_int11_aOUT);
delay_3713: DELAY
PORT MAP ( Y => n_4500, IN1 => data(11));
and1_3714: AND1
PORT MAP ( Y => n_4501, IN1 => gnd);
delay_3715: DELAY
PORT MAP ( Y => I1_dup_658_aOUT, IN1 => I1_dup_658_aIN);
xor2_3716: XOR2
PORT MAP ( Y => I1_dup_658_aIN, IN1 => n_4504, IN2 => n_4508);
or1_3717: OR1
PORT MAP ( Y => n_4504, IN1 => n_4505);
and2_3718: AND2
PORT MAP ( Y => n_4505, IN1 => n_4506, IN2 => n_4507);
delay_3719: DELAY
PORT MAP ( Y => n_4506, IN1 => O_dup_867_aOUT);
delay_3720: DELAY
PORT MAP ( Y => n_4507, IN1 => alu1_nx180_aOUT);
and1_3721: AND1
PORT MAP ( Y => n_4508, IN1 => gnd);
dff_3722: DFF
PORT MAP ( D => outreg_val11_aD, CLK => outreg_val11_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val11_Q);
xor2_3723: XOR2
PORT MAP ( Y => outreg_val11_aD, IN1 => n_4514, IN2 => n_4520);
or2_3724: OR2
PORT MAP ( Y => n_4514, IN1 => n_4515, IN2 => n_4517);
and1_3725: AND1
PORT MAP ( Y => n_4515, IN1 => n_4516);
delay_3726: DELAY
PORT MAP ( Y => n_4516, IN1 => I1_dup_658_aOUT);
and2_3727: AND2
PORT MAP ( Y => n_4517, IN1 => n_4518, IN2 => n_4519);
inv_3728: INV
PORT MAP ( Y => n_4518, IN1 => alusel0_aOUT);
delay_3729: DELAY
PORT MAP ( Y => n_4519, IN1 => data(11));
and1_3730: AND1
PORT MAP ( Y => n_4520, IN1 => gnd);
and1_3731: AND1
PORT MAP ( Y => n_4521, IN1 => n_4522);
delay_3732: DELAY
PORT MAP ( Y => n_4522, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3733: DELAY
PORT MAP ( Y => outreg_val11_aCLK, IN1 => n_4521);
dff_3734: DFF
PORT MAP ( D => progcntr_val12_aD, CLK => progcntr_val12_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val12_Q);
xor2_3735: XOR2
PORT MAP ( Y => progcntr_val12_aD, IN1 => n_4529, IN2 => n_4532);
or1_3736: OR1
PORT MAP ( Y => n_4529, IN1 => n_4530);
and1_3737: AND1
PORT MAP ( Y => n_4530, IN1 => n_4531);
delay_3738: DELAY
PORT MAP ( Y => n_4531, IN1 => data(12));
and1_3739: AND1
PORT MAP ( Y => n_4532, IN1 => gnd);
and1_3740: AND1
PORT MAP ( Y => n_4533, IN1 => n_4534);
delay_3741: DELAY
PORT MAP ( Y => n_4534, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3742: DELAY
PORT MAP ( Y => progcntr_val12_aCLK, IN1 => n_4533);
delay_3743: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int12_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int12_aIN);
xor2_3744: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int12_aIN, IN1 => n_4538, IN2 => n_4542);
or1_3745: OR1
PORT MAP ( Y => n_4538, IN1 => n_4539);
and2_3746: AND2
PORT MAP ( Y => n_4539, IN1 => n_4540, IN2 => n_4541);
delay_3747: DELAY
PORT MAP ( Y => n_4540, IN1 => alu1_modgen_34_l1_l0_c_int11_aOUT);
delay_3748: DELAY
PORT MAP ( Y => n_4541, IN1 => data(11));
and1_3749: AND1
PORT MAP ( Y => n_4542, IN1 => gnd);
delay_3750: DELAY
PORT MAP ( Y => alu1_nx179_aOUT, IN1 => alu1_nx179_aIN);
xor2_3751: XOR2
PORT MAP ( Y => alu1_nx179_aIN, IN1 => n_4545, IN2 => n_4552);
or2_3752: OR2
PORT MAP ( Y => n_4545, IN1 => n_4546, IN2 => n_4549);
and2_3753: AND2
PORT MAP ( Y => n_4546, IN1 => n_4547, IN2 => n_4548);
inv_3754: INV
PORT MAP ( Y => n_4547, IN1 => data(12));
delay_3755: DELAY
PORT MAP ( Y => n_4548, IN1 => alu1_modgen_34_l1_l0_c_int12_aOUT);
and2_3756: AND2
PORT MAP ( Y => n_4549, IN1 => n_4550, IN2 => n_4551);
inv_3757: INV
PORT MAP ( Y => n_4550, IN1 => alu1_modgen_34_l1_l0_c_int12_aOUT);
delay_3758: DELAY
PORT MAP ( Y => n_4551, IN1 => data(12));
and1_3759: AND1
PORT MAP ( Y => n_4552, IN1 => gnd);
delay_3760: DELAY
PORT MAP ( Y => I1_dup_657_aOUT, IN1 => I1_dup_657_aIN);
xor2_3761: XOR2
PORT MAP ( Y => I1_dup_657_aIN, IN1 => n_4555, IN2 => n_4559);
or1_3762: OR1
PORT MAP ( Y => n_4555, IN1 => n_4556);
and2_3763: AND2
PORT MAP ( Y => n_4556, IN1 => n_4557, IN2 => n_4558);
delay_3764: DELAY
PORT MAP ( Y => n_4557, IN1 => O_dup_867_aOUT);
delay_3765: DELAY
PORT MAP ( Y => n_4558, IN1 => alu1_nx179_aOUT);
and1_3766: AND1
PORT MAP ( Y => n_4559, IN1 => gnd);
dff_3767: DFF
PORT MAP ( D => outreg_val12_aD, CLK => outreg_val12_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val12_Q);
xor2_3768: XOR2
PORT MAP ( Y => outreg_val12_aD, IN1 => n_4565, IN2 => n_4571);
or2_3769: OR2
PORT MAP ( Y => n_4565, IN1 => n_4566, IN2 => n_4568);
and1_3770: AND1
PORT MAP ( Y => n_4566, IN1 => n_4567);
delay_3771: DELAY
PORT MAP ( Y => n_4567, IN1 => I1_dup_657_aOUT);
and2_3772: AND2
PORT MAP ( Y => n_4568, IN1 => n_4569, IN2 => n_4570);
inv_3773: INV
PORT MAP ( Y => n_4569, IN1 => alusel0_aOUT);
delay_3774: DELAY
PORT MAP ( Y => n_4570, IN1 => data(12));
and1_3775: AND1
PORT MAP ( Y => n_4571, IN1 => gnd);
and1_3776: AND1
PORT MAP ( Y => n_4572, IN1 => n_4573);
delay_3777: DELAY
PORT MAP ( Y => n_4573, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3778: DELAY
PORT MAP ( Y => outreg_val12_aCLK, IN1 => n_4572);
dff_3779: DFF
PORT MAP ( D => progcntr_val13_aD, CLK => progcntr_val13_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val13_Q);
xor2_3780: XOR2
PORT MAP ( Y => progcntr_val13_aD, IN1 => n_4580, IN2 => n_4583);
or1_3781: OR1
PORT MAP ( Y => n_4580, IN1 => n_4581);
and1_3782: AND1
PORT MAP ( Y => n_4581, IN1 => n_4582);
delay_3783: DELAY
PORT MAP ( Y => n_4582, IN1 => data(13));
and1_3784: AND1
PORT MAP ( Y => n_4583, IN1 => gnd);
and1_3785: AND1
PORT MAP ( Y => n_4584, IN1 => n_4585);
delay_3786: DELAY
PORT MAP ( Y => n_4585, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3787: DELAY
PORT MAP ( Y => progcntr_val13_aCLK, IN1 => n_4584);
delay_3788: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int13_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int13_aIN);
xor2_3789: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int13_aIN, IN1 => n_4589, IN2 => n_4593);
or1_3790: OR1
PORT MAP ( Y => n_4589, IN1 => n_4590);
and2_3791: AND2
PORT MAP ( Y => n_4590, IN1 => n_4591, IN2 => n_4592);
delay_3792: DELAY
PORT MAP ( Y => n_4591, IN1 => alu1_modgen_34_l1_l0_c_int12_aOUT);
delay_3793: DELAY
PORT MAP ( Y => n_4592, IN1 => data(12));
and1_3794: AND1
PORT MAP ( Y => n_4593, IN1 => gnd);
delay_3795: DELAY
PORT MAP ( Y => alu1_nx178_aOUT, IN1 => alu1_nx178_aIN);
xor2_3796: XOR2
PORT MAP ( Y => alu1_nx178_aIN, IN1 => n_4596, IN2 => n_4603);
or2_3797: OR2
PORT MAP ( Y => n_4596, IN1 => n_4597, IN2 => n_4600);
and2_3798: AND2
PORT MAP ( Y => n_4597, IN1 => n_4598, IN2 => n_4599);
inv_3799: INV
PORT MAP ( Y => n_4598, IN1 => data(13));
delay_3800: DELAY
PORT MAP ( Y => n_4599, IN1 => alu1_modgen_34_l1_l0_c_int13_aOUT);
and2_3801: AND2
PORT MAP ( Y => n_4600, IN1 => n_4601, IN2 => n_4602);
inv_3802: INV
PORT MAP ( Y => n_4601, IN1 => alu1_modgen_34_l1_l0_c_int13_aOUT);
delay_3803: DELAY
PORT MAP ( Y => n_4602, IN1 => data(13));
and1_3804: AND1
PORT MAP ( Y => n_4603, IN1 => gnd);
delay_3805: DELAY
PORT MAP ( Y => I1_dup_656_aOUT, IN1 => I1_dup_656_aIN);
xor2_3806: XOR2
PORT MAP ( Y => I1_dup_656_aIN, IN1 => n_4606, IN2 => n_4610);
or1_3807: OR1
PORT MAP ( Y => n_4606, IN1 => n_4607);
and2_3808: AND2
PORT MAP ( Y => n_4607, IN1 => n_4608, IN2 => n_4609);
delay_3809: DELAY
PORT MAP ( Y => n_4608, IN1 => O_dup_867_aOUT);
delay_3810: DELAY
PORT MAP ( Y => n_4609, IN1 => alu1_nx178_aOUT);
and1_3811: AND1
PORT MAP ( Y => n_4610, IN1 => gnd);
dff_3812: DFF
PORT MAP ( D => outreg_val13_aD, CLK => outreg_val13_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val13_Q);
xor2_3813: XOR2
PORT MAP ( Y => outreg_val13_aD, IN1 => n_4616, IN2 => n_4622);
or2_3814: OR2
PORT MAP ( Y => n_4616, IN1 => n_4617, IN2 => n_4619);
and1_3815: AND1
PORT MAP ( Y => n_4617, IN1 => n_4618);
delay_3816: DELAY
PORT MAP ( Y => n_4618, IN1 => I1_dup_656_aOUT);
and2_3817: AND2
PORT MAP ( Y => n_4619, IN1 => n_4620, IN2 => n_4621);
inv_3818: INV
PORT MAP ( Y => n_4620, IN1 => alusel0_aOUT);
delay_3819: DELAY
PORT MAP ( Y => n_4621, IN1 => data(13));
and1_3820: AND1
PORT MAP ( Y => n_4622, IN1 => gnd);
and1_3821: AND1
PORT MAP ( Y => n_4623, IN1 => n_4624);
delay_3822: DELAY
PORT MAP ( Y => n_4624, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3823: DELAY
PORT MAP ( Y => outreg_val13_aCLK, IN1 => n_4623);
dff_3824: DFF
PORT MAP ( D => progcntr_val14_aD, CLK => progcntr_val14_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val14_Q);
xor2_3825: XOR2
PORT MAP ( Y => progcntr_val14_aD, IN1 => n_4631, IN2 => n_4634);
or1_3826: OR1
PORT MAP ( Y => n_4631, IN1 => n_4632);
and1_3827: AND1
PORT MAP ( Y => n_4632, IN1 => n_4633);
delay_3828: DELAY
PORT MAP ( Y => n_4633, IN1 => data(14));
and1_3829: AND1
PORT MAP ( Y => n_4634, IN1 => gnd);
and1_3830: AND1
PORT MAP ( Y => n_4635, IN1 => n_4636);
delay_3831: DELAY
PORT MAP ( Y => n_4636, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3832: DELAY
PORT MAP ( Y => progcntr_val14_aCLK, IN1 => n_4635);
delay_3833: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int14_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int14_aIN);
xor2_3834: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int14_aIN, IN1 => n_4640, IN2 => n_4644);
or1_3835: OR1
PORT MAP ( Y => n_4640, IN1 => n_4641);
and2_3836: AND2
PORT MAP ( Y => n_4641, IN1 => n_4642, IN2 => n_4643);
delay_3837: DELAY
PORT MAP ( Y => n_4642, IN1 => alu1_modgen_34_l1_l0_c_int13_aOUT);
delay_3838: DELAY
PORT MAP ( Y => n_4643, IN1 => data(13));
and1_3839: AND1
PORT MAP ( Y => n_4644, IN1 => gnd);
delay_3840: DELAY
PORT MAP ( Y => alu1_nx177_aOUT, IN1 => alu1_nx177_aIN);
xor2_3841: XOR2
PORT MAP ( Y => alu1_nx177_aIN, IN1 => n_4647, IN2 => n_4654);
or2_3842: OR2
PORT MAP ( Y => n_4647, IN1 => n_4648, IN2 => n_4651);
and2_3843: AND2
PORT MAP ( Y => n_4648, IN1 => n_4649, IN2 => n_4650);
inv_3844: INV
PORT MAP ( Y => n_4649, IN1 => data(14));
delay_3845: DELAY
PORT MAP ( Y => n_4650, IN1 => alu1_modgen_34_l1_l0_c_int14_aOUT);
and2_3846: AND2
PORT MAP ( Y => n_4651, IN1 => n_4652, IN2 => n_4653);
inv_3847: INV
PORT MAP ( Y => n_4652, IN1 => alu1_modgen_34_l1_l0_c_int14_aOUT);
delay_3848: DELAY
PORT MAP ( Y => n_4653, IN1 => data(14));
and1_3849: AND1
PORT MAP ( Y => n_4654, IN1 => gnd);
delay_3850: DELAY
PORT MAP ( Y => I1_dup_655_aOUT, IN1 => I1_dup_655_aIN);
xor2_3851: XOR2
PORT MAP ( Y => I1_dup_655_aIN, IN1 => n_4657, IN2 => n_4661);
or1_3852: OR1
PORT MAP ( Y => n_4657, IN1 => n_4658);
and2_3853: AND2
PORT MAP ( Y => n_4658, IN1 => n_4659, IN2 => n_4660);
delay_3854: DELAY
PORT MAP ( Y => n_4659, IN1 => O_dup_867_aOUT);
delay_3855: DELAY
PORT MAP ( Y => n_4660, IN1 => alu1_nx177_aOUT);
and1_3856: AND1
PORT MAP ( Y => n_4661, IN1 => gnd);
dff_3857: DFF
PORT MAP ( D => outreg_val14_aD, CLK => outreg_val14_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val14_Q);
xor2_3858: XOR2
PORT MAP ( Y => outreg_val14_aD, IN1 => n_4667, IN2 => n_4673);
or2_3859: OR2
PORT MAP ( Y => n_4667, IN1 => n_4668, IN2 => n_4670);
and1_3860: AND1
PORT MAP ( Y => n_4668, IN1 => n_4669);
delay_3861: DELAY
PORT MAP ( Y => n_4669, IN1 => I1_dup_655_aOUT);
and2_3862: AND2
PORT MAP ( Y => n_4670, IN1 => n_4671, IN2 => n_4672);
inv_3863: INV
PORT MAP ( Y => n_4671, IN1 => alusel0_aOUT);
delay_3864: DELAY
PORT MAP ( Y => n_4672, IN1 => data(14));
and1_3865: AND1
PORT MAP ( Y => n_4673, IN1 => gnd);
and1_3866: AND1
PORT MAP ( Y => n_4674, IN1 => n_4675);
delay_3867: DELAY
PORT MAP ( Y => n_4675, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3868: DELAY
PORT MAP ( Y => outreg_val14_aCLK, IN1 => n_4674);
dff_3869: DFF
PORT MAP ( D => con1_current_state50_aD, CLK => con1_current_state50_aCLK,
CLRN => con1_current_state50_aCLRN, PRN => vcc, Q => con1_current_state50_Q);
inv_3870: INV
PORT MAP ( Y => con1_current_state50_aCLRN, IN1 => reset);
xor2_3871: XOR2
PORT MAP ( Y => con1_current_state50_aD, IN1 => n_4683, IN2 => n_4686);
or1_3872: OR1
PORT MAP ( Y => n_4683, IN1 => n_4684);
and1_3873: AND1
PORT MAP ( Y => n_4684, IN1 => n_4685);
delay_3874: DELAY
PORT MAP ( Y => n_4685, IN1 => con1_current_state49_Q);
and1_3875: AND1
PORT MAP ( Y => n_4686, IN1 => gnd);
delay_3876: DELAY
PORT MAP ( Y => con1_current_state50_aCLK, IN1 => clock);
dff_3877: DFF
PORT MAP ( D => progcntr_val15_aD, CLK => progcntr_val15_aCLK, CLRN => vcc,
PRN => vcc, Q => progcntr_val15_Q);
xor2_3878: XOR2
PORT MAP ( Y => progcntr_val15_aD, IN1 => n_4693, IN2 => n_4696);
or1_3879: OR1
PORT MAP ( Y => n_4693, IN1 => n_4694);
and1_3880: AND1
PORT MAP ( Y => n_4694, IN1 => n_4695);
delay_3881: DELAY
PORT MAP ( Y => n_4695, IN1 => data(15));
and1_3882: AND1
PORT MAP ( Y => n_4696, IN1 => gnd);
and1_3883: AND1
PORT MAP ( Y => n_4697, IN1 => n_4698);
delay_3884: DELAY
PORT MAP ( Y => n_4698, IN1 => a_as_or3_aix1652_a_a32_aOUT);
delay_3885: DELAY
PORT MAP ( Y => progcntr_val15_aCLK, IN1 => n_4697);
delay_3886: DELAY
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int15_aOUT, IN1 => alu1_modgen_34_l1_l0_c_int15_aIN);
xor2_3887: XOR2
PORT MAP ( Y => alu1_modgen_34_l1_l0_c_int15_aIN, IN1 => n_4702, IN2 => n_4706);
or1_3888: OR1
PORT MAP ( Y => n_4702, IN1 => n_4703);
and2_3889: AND2
PORT MAP ( Y => n_4703, IN1 => n_4704, IN2 => n_4705);
delay_3890: DELAY
PORT MAP ( Y => n_4704, IN1 => alu1_modgen_34_l1_l0_c_int14_aOUT);
delay_3891: DELAY
PORT MAP ( Y => n_4705, IN1 => data(14));
and1_3892: AND1
PORT MAP ( Y => n_4706, IN1 => gnd);
delay_3893: DELAY
PORT MAP ( Y => alu1_nx176_aOUT, IN1 => alu1_nx176_aIN);
xor2_3894: XOR2
PORT MAP ( Y => alu1_nx176_aIN, IN1 => n_4709, IN2 => n_4716);
or2_3895: OR2
PORT MAP ( Y => n_4709, IN1 => n_4710, IN2 => n_4713);
and2_3896: AND2
PORT MAP ( Y => n_4710, IN1 => n_4711, IN2 => n_4712);
inv_3897: INV
PORT MAP ( Y => n_4711, IN1 => data(15));
delay_3898: DELAY
PORT MAP ( Y => n_4712, IN1 => alu1_modgen_34_l1_l0_c_int15_aOUT);
and2_3899: AND2
PORT MAP ( Y => n_4713, IN1 => n_4714, IN2 => n_4715);
inv_3900: INV
PORT MAP ( Y => n_4714, IN1 => alu1_modgen_34_l1_l0_c_int15_aOUT);
delay_3901: DELAY
PORT MAP ( Y => n_4715, IN1 => data(15));
and1_3902: AND1
PORT MAP ( Y => n_4716, IN1 => gnd);
delay_3903: DELAY
PORT MAP ( Y => I1_aOUT, IN1 => I1_aIN);
xor2_3904: XOR2
PORT MAP ( Y => I1_aIN, IN1 => n_4719, IN2 => n_4723);
or1_3905: OR1
PORT MAP ( Y => n_4719, IN1 => n_4720);
and2_3906: AND2
PORT MAP ( Y => n_4720, IN1 => n_4721, IN2 => n_4722);
delay_3907: DELAY
PORT MAP ( Y => n_4721, IN1 => O_dup_867_aOUT);
delay_3908: DELAY
PORT MAP ( Y => n_4722, IN1 => alu1_nx176_aOUT);
and1_3909: AND1
PORT MAP ( Y => n_4723, IN1 => gnd);
dff_3910: DFF
PORT MAP ( D => outreg_val15_aD, CLK => outreg_val15_aCLK, CLRN => vcc,
PRN => vcc, Q => outreg_val15_Q);
xor2_3911: XOR2
PORT MAP ( Y => outreg_val15_aD, IN1 => n_4729, IN2 => n_4735);
or2_3912: OR2
PORT MAP ( Y => n_4729, IN1 => n_4730, IN2 => n_4732);
and1_3913: AND1
PORT MAP ( Y => n_4730, IN1 => n_4731);
delay_3914: DELAY
PORT MAP ( Y => n_4731, IN1 => I1_aOUT);
and2_3915: AND2
PORT MAP ( Y => n_4732, IN1 => n_4733, IN2 => n_4734);
inv_3916: INV
PORT MAP ( Y => n_4733, IN1 => alusel0_aOUT);
delay_3917: DELAY
PORT MAP ( Y => n_4734, IN1 => data(15));
and1_3918: AND1
PORT MAP ( Y => n_4735, IN1 => gnd);
and1_3919: AND1
PORT MAP ( Y => n_4736, IN1 => n_4737);
delay_3920: DELAY
PORT MAP ( Y => n_4737, IN1 => a_as_or3_aix1642_a_a32_aOUT);
delay_3921: DELAY
PORT MAP ( Y => outreg_val15_aCLK, IN1 => n_4736);
dff_3922: DFF
PORT MAP ( D => instrregout15_aD, CLK => instrregout15_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout15_Q);
xor2_3923: XOR2
PORT MAP ( Y => instrregout15_aD, IN1 => n_4744, IN2 => n_4747);
or1_3924: OR1
PORT MAP ( Y => n_4744, IN1 => n_4745);
and1_3925: AND1
PORT MAP ( Y => n_4745, IN1 => n_4746);
delay_3926: DELAY
PORT MAP ( Y => n_4746, IN1 => data(15));
and1_3927: AND1
PORT MAP ( Y => n_4747, IN1 => gnd);
and1_3928: AND1
PORT MAP ( Y => n_4748, IN1 => n_4749);
delay_3929: DELAY
PORT MAP ( Y => n_4749, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_3930: DELAY
PORT MAP ( Y => instrregout15_aCLK, IN1 => n_4748);
dff_3931: DFF
PORT MAP ( D => con1_current_state45_aD, CLK => con1_current_state45_aCLK,
CLRN => con1_current_state45_aCLRN, PRN => vcc, Q => con1_current_state45_Q);
inv_3932: INV
PORT MAP ( Y => con1_current_state45_aCLRN, IN1 => reset);
xor2_3933: XOR2
PORT MAP ( Y => con1_current_state45_aD, IN1 => n_4758, IN2 => n_4761);
or1_3934: OR1
PORT MAP ( Y => n_4758, IN1 => n_4759);
and1_3935: AND1
PORT MAP ( Y => n_4759, IN1 => n_4760);
delay_3936: DELAY
PORT MAP ( Y => n_4760, IN1 => con1_current_state44_Q);
and1_3937: AND1
PORT MAP ( Y => n_4761, IN1 => gnd);
delay_3938: DELAY
PORT MAP ( Y => con1_current_state45_aCLK, IN1 => clock);
dff_3939: DFF
PORT MAP ( D => con1_current_state40_aD, CLK => con1_current_state40_aCLK,
CLRN => con1_current_state40_aCLRN, PRN => vcc, Q => con1_current_state40_Q);
inv_3940: INV
PORT MAP ( Y => con1_current_state40_aCLRN, IN1 => reset);
xor2_3941: XOR2
PORT MAP ( Y => con1_current_state40_aD, IN1 => n_4770, IN2 => n_4773);
or1_3942: OR1
PORT MAP ( Y => n_4770, IN1 => n_4771);
and1_3943: AND1
PORT MAP ( Y => n_4771, IN1 => n_4772);
delay_3944: DELAY
PORT MAP ( Y => n_4772, IN1 => con1_current_state39_Q);
and1_3945: AND1
PORT MAP ( Y => n_4773, IN1 => gnd);
delay_3946: DELAY
PORT MAP ( Y => con1_current_state40_aCLK, IN1 => clock);
dff_3947: DFF
PORT MAP ( D => con1_current_state35_aD, CLK => con1_current_state35_aCLK,
CLRN => con1_current_state35_aCLRN, PRN => vcc, Q => con1_current_state35_Q);
inv_3948: INV
PORT MAP ( Y => con1_current_state35_aCLRN, IN1 => reset);
xor2_3949: XOR2
PORT MAP ( Y => con1_current_state35_aD, IN1 => n_4782, IN2 => n_4785);
or1_3950: OR1
PORT MAP ( Y => n_4782, IN1 => n_4783);
and1_3951: AND1
PORT MAP ( Y => n_4783, IN1 => n_4784);
delay_3952: DELAY
PORT MAP ( Y => n_4784, IN1 => con1_current_state34_Q);
and1_3953: AND1
PORT MAP ( Y => n_4785, IN1 => gnd);
delay_3954: DELAY
PORT MAP ( Y => con1_current_state35_aCLK, IN1 => clock);
dffe_3955: DFFE
PORT MAP ( D => ix484_a2_dup_652_aD, CLK => ix484_a2_dup_652_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_652_aENA, Q => ix484_a2_dup_652_Q);
xor2_3956: XOR2
PORT MAP ( Y => ix484_a2_dup_652_aD, IN1 => n_4793, IN2 => n_4796);
or1_3957: OR1
PORT MAP ( Y => n_4793, IN1 => n_4794);
and1_3958: AND1
PORT MAP ( Y => n_4794, IN1 => n_4795);
delay_3959: DELAY
PORT MAP ( Y => n_4795, IN1 => data(0));
and1_3960: AND1
PORT MAP ( Y => n_4796, IN1 => gnd);
and1_3961: AND1
PORT MAP ( Y => n_4797, IN1 => n_4798);
delay_3962: DELAY
PORT MAP ( Y => n_4798, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3963: DELAY
PORT MAP ( Y => ix484_a2_dup_652_aCLK, IN1 => n_4797);
and1_3964: AND1
PORT MAP ( Y => ix484_a2_dup_652_aENA, IN1 => n_4801);
delay_3965: DELAY
PORT MAP ( Y => n_4801, IN1 => ix484_nx43_aOUT);
dffe_3966: DFFE
PORT MAP ( D => ix484_a7_dup_647_aD, CLK => ix484_a7_dup_647_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_647_aENA, Q => ix484_a7_dup_647_Q);
xor2_3967: XOR2
PORT MAP ( Y => ix484_a7_dup_647_aD, IN1 => n_4808, IN2 => n_4811);
or1_3968: OR1
PORT MAP ( Y => n_4808, IN1 => n_4809);
and1_3969: AND1
PORT MAP ( Y => n_4809, IN1 => n_4810);
delay_3970: DELAY
PORT MAP ( Y => n_4810, IN1 => data(0));
and1_3971: AND1
PORT MAP ( Y => n_4811, IN1 => gnd);
and1_3972: AND1
PORT MAP ( Y => n_4812, IN1 => n_4813);
delay_3973: DELAY
PORT MAP ( Y => n_4813, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3974: DELAY
PORT MAP ( Y => ix484_a7_dup_647_aCLK, IN1 => n_4812);
and1_3975: AND1
PORT MAP ( Y => ix484_a7_dup_647_aENA, IN1 => n_4816);
delay_3976: DELAY
PORT MAP ( Y => n_4816, IN1 => ix484_nx38_aOUT);
dffe_3977: DFFE
PORT MAP ( D => ix484_a2_dup_644_aD, CLK => ix484_a2_dup_644_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_644_aENA, Q => ix484_a2_dup_644_Q);
xor2_3978: XOR2
PORT MAP ( Y => ix484_a2_dup_644_aD, IN1 => n_4824, IN2 => n_4827);
or1_3979: OR1
PORT MAP ( Y => n_4824, IN1 => n_4825);
and1_3980: AND1
PORT MAP ( Y => n_4825, IN1 => n_4826);
delay_3981: DELAY
PORT MAP ( Y => n_4826, IN1 => data(1));
and1_3982: AND1
PORT MAP ( Y => n_4827, IN1 => gnd);
and1_3983: AND1
PORT MAP ( Y => n_4828, IN1 => n_4829);
delay_3984: DELAY
PORT MAP ( Y => n_4829, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3985: DELAY
PORT MAP ( Y => ix484_a2_dup_644_aCLK, IN1 => n_4828);
and1_3986: AND1
PORT MAP ( Y => ix484_a2_dup_644_aENA, IN1 => n_4832);
delay_3987: DELAY
PORT MAP ( Y => n_4832, IN1 => ix484_nx43_aOUT);
dffe_3988: DFFE
PORT MAP ( D => ix484_a7_dup_639_aD, CLK => ix484_a7_dup_639_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_639_aENA, Q => ix484_a7_dup_639_Q);
xor2_3989: XOR2
PORT MAP ( Y => ix484_a7_dup_639_aD, IN1 => n_4839, IN2 => n_4842);
or1_3990: OR1
PORT MAP ( Y => n_4839, IN1 => n_4840);
and1_3991: AND1
PORT MAP ( Y => n_4840, IN1 => n_4841);
delay_3992: DELAY
PORT MAP ( Y => n_4841, IN1 => data(1));
and1_3993: AND1
PORT MAP ( Y => n_4842, IN1 => gnd);
and1_3994: AND1
PORT MAP ( Y => n_4843, IN1 => n_4844);
delay_3995: DELAY
PORT MAP ( Y => n_4844, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_3996: DELAY
PORT MAP ( Y => ix484_a7_dup_639_aCLK, IN1 => n_4843);
and1_3997: AND1
PORT MAP ( Y => ix484_a7_dup_639_aENA, IN1 => n_4847);
delay_3998: DELAY
PORT MAP ( Y => n_4847, IN1 => ix484_nx38_aOUT);
dffe_3999: DFFE
PORT MAP ( D => ix484_a2_dup_636_aD, CLK => ix484_a2_dup_636_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_636_aENA, Q => ix484_a2_dup_636_Q);
xor2_4000: XOR2
PORT MAP ( Y => ix484_a2_dup_636_aD, IN1 => n_4854, IN2 => n_4857);
or1_4001: OR1
PORT MAP ( Y => n_4854, IN1 => n_4855);
and1_4002: AND1
PORT MAP ( Y => n_4855, IN1 => n_4856);
delay_4003: DELAY
PORT MAP ( Y => n_4856, IN1 => data(2));
and1_4004: AND1
PORT MAP ( Y => n_4857, IN1 => gnd);
and1_4005: AND1
PORT MAP ( Y => n_4858, IN1 => n_4859);
delay_4006: DELAY
PORT MAP ( Y => n_4859, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4007: DELAY
PORT MAP ( Y => ix484_a2_dup_636_aCLK, IN1 => n_4858);
and1_4008: AND1
PORT MAP ( Y => ix484_a2_dup_636_aENA, IN1 => n_4862);
delay_4009: DELAY
PORT MAP ( Y => n_4862, IN1 => ix484_nx43_aOUT);
dffe_4010: DFFE
PORT MAP ( D => ix484_a7_dup_631_aD, CLK => ix484_a7_dup_631_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_631_aENA, Q => ix484_a7_dup_631_Q);
xor2_4011: XOR2
PORT MAP ( Y => ix484_a7_dup_631_aD, IN1 => n_4869, IN2 => n_4872);
or1_4012: OR1
PORT MAP ( Y => n_4869, IN1 => n_4870);
and1_4013: AND1
PORT MAP ( Y => n_4870, IN1 => n_4871);
delay_4014: DELAY
PORT MAP ( Y => n_4871, IN1 => data(2));
and1_4015: AND1
PORT MAP ( Y => n_4872, IN1 => gnd);
and1_4016: AND1
PORT MAP ( Y => n_4873, IN1 => n_4874);
delay_4017: DELAY
PORT MAP ( Y => n_4874, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4018: DELAY
PORT MAP ( Y => ix484_a7_dup_631_aCLK, IN1 => n_4873);
and1_4019: AND1
PORT MAP ( Y => ix484_a7_dup_631_aENA, IN1 => n_4877);
delay_4020: DELAY
PORT MAP ( Y => n_4877, IN1 => ix484_nx38_aOUT);
dffe_4021: DFFE
PORT MAP ( D => ix484_a2_dup_628_aD, CLK => ix484_a2_dup_628_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_628_aENA, Q => ix484_a2_dup_628_Q);
xor2_4022: XOR2
PORT MAP ( Y => ix484_a2_dup_628_aD, IN1 => n_4884, IN2 => n_4887);
or1_4023: OR1
PORT MAP ( Y => n_4884, IN1 => n_4885);
and1_4024: AND1
PORT MAP ( Y => n_4885, IN1 => n_4886);
delay_4025: DELAY
PORT MAP ( Y => n_4886, IN1 => data(3));
and1_4026: AND1
PORT MAP ( Y => n_4887, IN1 => gnd);
and1_4027: AND1
PORT MAP ( Y => n_4888, IN1 => n_4889);
delay_4028: DELAY
PORT MAP ( Y => n_4889, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4029: DELAY
PORT MAP ( Y => ix484_a2_dup_628_aCLK, IN1 => n_4888);
and1_4030: AND1
PORT MAP ( Y => ix484_a2_dup_628_aENA, IN1 => n_4892);
delay_4031: DELAY
PORT MAP ( Y => n_4892, IN1 => ix484_nx43_aOUT);
dffe_4032: DFFE
PORT MAP ( D => ix484_a7_dup_623_aD, CLK => ix484_a7_dup_623_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_623_aENA, Q => ix484_a7_dup_623_Q);
xor2_4033: XOR2
PORT MAP ( Y => ix484_a7_dup_623_aD, IN1 => n_4899, IN2 => n_4902);
or1_4034: OR1
PORT MAP ( Y => n_4899, IN1 => n_4900);
and1_4035: AND1
PORT MAP ( Y => n_4900, IN1 => n_4901);
delay_4036: DELAY
PORT MAP ( Y => n_4901, IN1 => data(3));
and1_4037: AND1
PORT MAP ( Y => n_4902, IN1 => gnd);
and1_4038: AND1
PORT MAP ( Y => n_4903, IN1 => n_4904);
delay_4039: DELAY
PORT MAP ( Y => n_4904, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4040: DELAY
PORT MAP ( Y => ix484_a7_dup_623_aCLK, IN1 => n_4903);
and1_4041: AND1
PORT MAP ( Y => ix484_a7_dup_623_aENA, IN1 => n_4907);
delay_4042: DELAY
PORT MAP ( Y => n_4907, IN1 => ix484_nx38_aOUT);
dffe_4043: DFFE
PORT MAP ( D => ix484_a2_dup_620_aD, CLK => ix484_a2_dup_620_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_620_aENA, Q => ix484_a2_dup_620_Q);
xor2_4044: XOR2
PORT MAP ( Y => ix484_a2_dup_620_aD, IN1 => n_4914, IN2 => n_4917);
or1_4045: OR1
PORT MAP ( Y => n_4914, IN1 => n_4915);
and1_4046: AND1
PORT MAP ( Y => n_4915, IN1 => n_4916);
delay_4047: DELAY
PORT MAP ( Y => n_4916, IN1 => data(4));
and1_4048: AND1
PORT MAP ( Y => n_4917, IN1 => gnd);
and1_4049: AND1
PORT MAP ( Y => n_4918, IN1 => n_4919);
delay_4050: DELAY
PORT MAP ( Y => n_4919, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4051: DELAY
PORT MAP ( Y => ix484_a2_dup_620_aCLK, IN1 => n_4918);
and1_4052: AND1
PORT MAP ( Y => ix484_a2_dup_620_aENA, IN1 => n_4922);
delay_4053: DELAY
PORT MAP ( Y => n_4922, IN1 => ix484_nx43_aOUT);
dffe_4054: DFFE
PORT MAP ( D => ix484_a7_dup_615_aD, CLK => ix484_a7_dup_615_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_615_aENA, Q => ix484_a7_dup_615_Q);
xor2_4055: XOR2
PORT MAP ( Y => ix484_a7_dup_615_aD, IN1 => n_4929, IN2 => n_4932);
or1_4056: OR1
PORT MAP ( Y => n_4929, IN1 => n_4930);
and1_4057: AND1
PORT MAP ( Y => n_4930, IN1 => n_4931);
delay_4058: DELAY
PORT MAP ( Y => n_4931, IN1 => data(4));
and1_4059: AND1
PORT MAP ( Y => n_4932, IN1 => gnd);
and1_4060: AND1
PORT MAP ( Y => n_4933, IN1 => n_4934);
delay_4061: DELAY
PORT MAP ( Y => n_4934, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4062: DELAY
PORT MAP ( Y => ix484_a7_dup_615_aCLK, IN1 => n_4933);
and1_4063: AND1
PORT MAP ( Y => ix484_a7_dup_615_aENA, IN1 => n_4937);
delay_4064: DELAY
PORT MAP ( Y => n_4937, IN1 => ix484_nx38_aOUT);
dffe_4065: DFFE
PORT MAP ( D => ix484_a2_dup_612_aD, CLK => ix484_a2_dup_612_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_612_aENA, Q => ix484_a2_dup_612_Q);
xor2_4066: XOR2
PORT MAP ( Y => ix484_a2_dup_612_aD, IN1 => n_4944, IN2 => n_4947);
or1_4067: OR1
PORT MAP ( Y => n_4944, IN1 => n_4945);
and1_4068: AND1
PORT MAP ( Y => n_4945, IN1 => n_4946);
delay_4069: DELAY
PORT MAP ( Y => n_4946, IN1 => data(5));
and1_4070: AND1
PORT MAP ( Y => n_4947, IN1 => gnd);
and1_4071: AND1
PORT MAP ( Y => n_4948, IN1 => n_4949);
delay_4072: DELAY
PORT MAP ( Y => n_4949, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4073: DELAY
PORT MAP ( Y => ix484_a2_dup_612_aCLK, IN1 => n_4948);
and1_4074: AND1
PORT MAP ( Y => ix484_a2_dup_612_aENA, IN1 => n_4952);
delay_4075: DELAY
PORT MAP ( Y => n_4952, IN1 => ix484_nx43_aOUT);
dffe_4076: DFFE
PORT MAP ( D => ix484_a7_dup_607_aD, CLK => ix484_a7_dup_607_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_607_aENA, Q => ix484_a7_dup_607_Q);
xor2_4077: XOR2
PORT MAP ( Y => ix484_a7_dup_607_aD, IN1 => n_4959, IN2 => n_4962);
or1_4078: OR1
PORT MAP ( Y => n_4959, IN1 => n_4960);
and1_4079: AND1
PORT MAP ( Y => n_4960, IN1 => n_4961);
delay_4080: DELAY
PORT MAP ( Y => n_4961, IN1 => data(5));
and1_4081: AND1
PORT MAP ( Y => n_4962, IN1 => gnd);
and1_4082: AND1
PORT MAP ( Y => n_4963, IN1 => n_4964);
delay_4083: DELAY
PORT MAP ( Y => n_4964, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4084: DELAY
PORT MAP ( Y => ix484_a7_dup_607_aCLK, IN1 => n_4963);
and1_4085: AND1
PORT MAP ( Y => ix484_a7_dup_607_aENA, IN1 => n_4967);
delay_4086: DELAY
PORT MAP ( Y => n_4967, IN1 => ix484_nx38_aOUT);
dffe_4087: DFFE
PORT MAP ( D => ix484_a2_dup_604_aD, CLK => ix484_a2_dup_604_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_604_aENA, Q => ix484_a2_dup_604_Q);
xor2_4088: XOR2
PORT MAP ( Y => ix484_a2_dup_604_aD, IN1 => n_4974, IN2 => n_4977);
or1_4089: OR1
PORT MAP ( Y => n_4974, IN1 => n_4975);
and1_4090: AND1
PORT MAP ( Y => n_4975, IN1 => n_4976);
delay_4091: DELAY
PORT MAP ( Y => n_4976, IN1 => data(6));
and1_4092: AND1
PORT MAP ( Y => n_4977, IN1 => gnd);
and1_4093: AND1
PORT MAP ( Y => n_4978, IN1 => n_4979);
delay_4094: DELAY
PORT MAP ( Y => n_4979, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4095: DELAY
PORT MAP ( Y => ix484_a2_dup_604_aCLK, IN1 => n_4978);
and1_4096: AND1
PORT MAP ( Y => ix484_a2_dup_604_aENA, IN1 => n_4982);
delay_4097: DELAY
PORT MAP ( Y => n_4982, IN1 => ix484_nx43_aOUT);
dffe_4098: DFFE
PORT MAP ( D => ix484_a7_dup_599_aD, CLK => ix484_a7_dup_599_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_599_aENA, Q => ix484_a7_dup_599_Q);
xor2_4099: XOR2
PORT MAP ( Y => ix484_a7_dup_599_aD, IN1 => n_4989, IN2 => n_4992);
or1_4100: OR1
PORT MAP ( Y => n_4989, IN1 => n_4990);
and1_4101: AND1
PORT MAP ( Y => n_4990, IN1 => n_4991);
delay_4102: DELAY
PORT MAP ( Y => n_4991, IN1 => data(6));
and1_4103: AND1
PORT MAP ( Y => n_4992, IN1 => gnd);
and1_4104: AND1
PORT MAP ( Y => n_4993, IN1 => n_4994);
delay_4105: DELAY
PORT MAP ( Y => n_4994, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4106: DELAY
PORT MAP ( Y => ix484_a7_dup_599_aCLK, IN1 => n_4993);
and1_4107: AND1
PORT MAP ( Y => ix484_a7_dup_599_aENA, IN1 => n_4997);
delay_4108: DELAY
PORT MAP ( Y => n_4997, IN1 => ix484_nx38_aOUT);
dffe_4109: DFFE
PORT MAP ( D => ix484_a2_dup_596_aD, CLK => ix484_a2_dup_596_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_596_aENA, Q => ix484_a2_dup_596_Q);
xor2_4110: XOR2
PORT MAP ( Y => ix484_a2_dup_596_aD, IN1 => n_5004, IN2 => n_5007);
or1_4111: OR1
PORT MAP ( Y => n_5004, IN1 => n_5005);
and1_4112: AND1
PORT MAP ( Y => n_5005, IN1 => n_5006);
delay_4113: DELAY
PORT MAP ( Y => n_5006, IN1 => data(7));
and1_4114: AND1
PORT MAP ( Y => n_5007, IN1 => gnd);
and1_4115: AND1
PORT MAP ( Y => n_5008, IN1 => n_5009);
delay_4116: DELAY
PORT MAP ( Y => n_5009, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4117: DELAY
PORT MAP ( Y => ix484_a2_dup_596_aCLK, IN1 => n_5008);
and1_4118: AND1
PORT MAP ( Y => ix484_a2_dup_596_aENA, IN1 => n_5012);
delay_4119: DELAY
PORT MAP ( Y => n_5012, IN1 => ix484_nx43_aOUT);
dffe_4120: DFFE
PORT MAP ( D => ix484_a7_dup_591_aD, CLK => ix484_a7_dup_591_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_591_aENA, Q => ix484_a7_dup_591_Q);
xor2_4121: XOR2
PORT MAP ( Y => ix484_a7_dup_591_aD, IN1 => n_5019, IN2 => n_5022);
or1_4122: OR1
PORT MAP ( Y => n_5019, IN1 => n_5020);
and1_4123: AND1
PORT MAP ( Y => n_5020, IN1 => n_5021);
delay_4124: DELAY
PORT MAP ( Y => n_5021, IN1 => data(7));
and1_4125: AND1
PORT MAP ( Y => n_5022, IN1 => gnd);
and1_4126: AND1
PORT MAP ( Y => n_5023, IN1 => n_5024);
delay_4127: DELAY
PORT MAP ( Y => n_5024, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4128: DELAY
PORT MAP ( Y => ix484_a7_dup_591_aCLK, IN1 => n_5023);
and1_4129: AND1
PORT MAP ( Y => ix484_a7_dup_591_aENA, IN1 => n_5027);
delay_4130: DELAY
PORT MAP ( Y => n_5027, IN1 => ix484_nx38_aOUT);
dffe_4131: DFFE
PORT MAP ( D => ix484_a2_dup_588_aD, CLK => ix484_a2_dup_588_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_588_aENA, Q => ix484_a2_dup_588_Q);
xor2_4132: XOR2
PORT MAP ( Y => ix484_a2_dup_588_aD, IN1 => n_5034, IN2 => n_5037);
or1_4133: OR1
PORT MAP ( Y => n_5034, IN1 => n_5035);
and1_4134: AND1
PORT MAP ( Y => n_5035, IN1 => n_5036);
delay_4135: DELAY
PORT MAP ( Y => n_5036, IN1 => data(8));
and1_4136: AND1
PORT MAP ( Y => n_5037, IN1 => gnd);
and1_4137: AND1
PORT MAP ( Y => n_5038, IN1 => n_5039);
delay_4138: DELAY
PORT MAP ( Y => n_5039, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4139: DELAY
PORT MAP ( Y => ix484_a2_dup_588_aCLK, IN1 => n_5038);
and1_4140: AND1
PORT MAP ( Y => ix484_a2_dup_588_aENA, IN1 => n_5042);
delay_4141: DELAY
PORT MAP ( Y => n_5042, IN1 => ix484_nx43_aOUT);
dffe_4142: DFFE
PORT MAP ( D => ix484_a7_dup_583_aD, CLK => ix484_a7_dup_583_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_583_aENA, Q => ix484_a7_dup_583_Q);
xor2_4143: XOR2
PORT MAP ( Y => ix484_a7_dup_583_aD, IN1 => n_5049, IN2 => n_5052);
or1_4144: OR1
PORT MAP ( Y => n_5049, IN1 => n_5050);
and1_4145: AND1
PORT MAP ( Y => n_5050, IN1 => n_5051);
delay_4146: DELAY
PORT MAP ( Y => n_5051, IN1 => data(8));
and1_4147: AND1
PORT MAP ( Y => n_5052, IN1 => gnd);
and1_4148: AND1
PORT MAP ( Y => n_5053, IN1 => n_5054);
delay_4149: DELAY
PORT MAP ( Y => n_5054, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4150: DELAY
PORT MAP ( Y => ix484_a7_dup_583_aCLK, IN1 => n_5053);
and1_4151: AND1
PORT MAP ( Y => ix484_a7_dup_583_aENA, IN1 => n_5057);
delay_4152: DELAY
PORT MAP ( Y => n_5057, IN1 => ix484_nx38_aOUT);
dffe_4153: DFFE
PORT MAP ( D => ix484_a2_dup_580_aD, CLK => ix484_a2_dup_580_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_580_aENA, Q => ix484_a2_dup_580_Q);
xor2_4154: XOR2
PORT MAP ( Y => ix484_a2_dup_580_aD, IN1 => n_5064, IN2 => n_5067);
or1_4155: OR1
PORT MAP ( Y => n_5064, IN1 => n_5065);
and1_4156: AND1
PORT MAP ( Y => n_5065, IN1 => n_5066);
delay_4157: DELAY
PORT MAP ( Y => n_5066, IN1 => data(9));
and1_4158: AND1
PORT MAP ( Y => n_5067, IN1 => gnd);
and1_4159: AND1
PORT MAP ( Y => n_5068, IN1 => n_5069);
delay_4160: DELAY
PORT MAP ( Y => n_5069, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4161: DELAY
PORT MAP ( Y => ix484_a2_dup_580_aCLK, IN1 => n_5068);
and1_4162: AND1
PORT MAP ( Y => ix484_a2_dup_580_aENA, IN1 => n_5072);
delay_4163: DELAY
PORT MAP ( Y => n_5072, IN1 => ix484_nx43_aOUT);
dffe_4164: DFFE
PORT MAP ( D => ix484_a7_dup_575_aD, CLK => ix484_a7_dup_575_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_575_aENA, Q => ix484_a7_dup_575_Q);
xor2_4165: XOR2
PORT MAP ( Y => ix484_a7_dup_575_aD, IN1 => n_5079, IN2 => n_5082);
or1_4166: OR1
PORT MAP ( Y => n_5079, IN1 => n_5080);
and1_4167: AND1
PORT MAP ( Y => n_5080, IN1 => n_5081);
delay_4168: DELAY
PORT MAP ( Y => n_5081, IN1 => data(9));
and1_4169: AND1
PORT MAP ( Y => n_5082, IN1 => gnd);
and1_4170: AND1
PORT MAP ( Y => n_5083, IN1 => n_5084);
delay_4171: DELAY
PORT MAP ( Y => n_5084, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4172: DELAY
PORT MAP ( Y => ix484_a7_dup_575_aCLK, IN1 => n_5083);
and1_4173: AND1
PORT MAP ( Y => ix484_a7_dup_575_aENA, IN1 => n_5087);
delay_4174: DELAY
PORT MAP ( Y => n_5087, IN1 => ix484_nx38_aOUT);
dffe_4175: DFFE
PORT MAP ( D => ix484_a2_dup_572_aD, CLK => ix484_a2_dup_572_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_572_aENA, Q => ix484_a2_dup_572_Q);
xor2_4176: XOR2
PORT MAP ( Y => ix484_a2_dup_572_aD, IN1 => n_5094, IN2 => n_5097);
or1_4177: OR1
PORT MAP ( Y => n_5094, IN1 => n_5095);
and1_4178: AND1
PORT MAP ( Y => n_5095, IN1 => n_5096);
delay_4179: DELAY
PORT MAP ( Y => n_5096, IN1 => data(10));
and1_4180: AND1
PORT MAP ( Y => n_5097, IN1 => gnd);
and1_4181: AND1
PORT MAP ( Y => n_5098, IN1 => n_5099);
delay_4182: DELAY
PORT MAP ( Y => n_5099, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4183: DELAY
PORT MAP ( Y => ix484_a2_dup_572_aCLK, IN1 => n_5098);
and1_4184: AND1
PORT MAP ( Y => ix484_a2_dup_572_aENA, IN1 => n_5102);
delay_4185: DELAY
PORT MAP ( Y => n_5102, IN1 => ix484_nx43_aOUT);
dffe_4186: DFFE
PORT MAP ( D => ix484_a7_dup_567_aD, CLK => ix484_a7_dup_567_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_567_aENA, Q => ix484_a7_dup_567_Q);
xor2_4187: XOR2
PORT MAP ( Y => ix484_a7_dup_567_aD, IN1 => n_5109, IN2 => n_5112);
or1_4188: OR1
PORT MAP ( Y => n_5109, IN1 => n_5110);
and1_4189: AND1
PORT MAP ( Y => n_5110, IN1 => n_5111);
delay_4190: DELAY
PORT MAP ( Y => n_5111, IN1 => data(10));
and1_4191: AND1
PORT MAP ( Y => n_5112, IN1 => gnd);
and1_4192: AND1
PORT MAP ( Y => n_5113, IN1 => n_5114);
delay_4193: DELAY
PORT MAP ( Y => n_5114, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4194: DELAY
PORT MAP ( Y => ix484_a7_dup_567_aCLK, IN1 => n_5113);
and1_4195: AND1
PORT MAP ( Y => ix484_a7_dup_567_aENA, IN1 => n_5117);
delay_4196: DELAY
PORT MAP ( Y => n_5117, IN1 => ix484_nx38_aOUT);
dffe_4197: DFFE
PORT MAP ( D => ix484_a2_dup_564_aD, CLK => ix484_a2_dup_564_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_564_aENA, Q => ix484_a2_dup_564_Q);
xor2_4198: XOR2
PORT MAP ( Y => ix484_a2_dup_564_aD, IN1 => n_5124, IN2 => n_5127);
or1_4199: OR1
PORT MAP ( Y => n_5124, IN1 => n_5125);
and1_4200: AND1
PORT MAP ( Y => n_5125, IN1 => n_5126);
delay_4201: DELAY
PORT MAP ( Y => n_5126, IN1 => data(11));
and1_4202: AND1
PORT MAP ( Y => n_5127, IN1 => gnd);
and1_4203: AND1
PORT MAP ( Y => n_5128, IN1 => n_5129);
delay_4204: DELAY
PORT MAP ( Y => n_5129, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4205: DELAY
PORT MAP ( Y => ix484_a2_dup_564_aCLK, IN1 => n_5128);
and1_4206: AND1
PORT MAP ( Y => ix484_a2_dup_564_aENA, IN1 => n_5132);
delay_4207: DELAY
PORT MAP ( Y => n_5132, IN1 => ix484_nx43_aOUT);
dffe_4208: DFFE
PORT MAP ( D => ix484_a7_dup_559_aD, CLK => ix484_a7_dup_559_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_559_aENA, Q => ix484_a7_dup_559_Q);
xor2_4209: XOR2
PORT MAP ( Y => ix484_a7_dup_559_aD, IN1 => n_5139, IN2 => n_5142);
or1_4210: OR1
PORT MAP ( Y => n_5139, IN1 => n_5140);
and1_4211: AND1
PORT MAP ( Y => n_5140, IN1 => n_5141);
delay_4212: DELAY
PORT MAP ( Y => n_5141, IN1 => data(11));
and1_4213: AND1
PORT MAP ( Y => n_5142, IN1 => gnd);
and1_4214: AND1
PORT MAP ( Y => n_5143, IN1 => n_5144);
delay_4215: DELAY
PORT MAP ( Y => n_5144, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4216: DELAY
PORT MAP ( Y => ix484_a7_dup_559_aCLK, IN1 => n_5143);
and1_4217: AND1
PORT MAP ( Y => ix484_a7_dup_559_aENA, IN1 => n_5147);
delay_4218: DELAY
PORT MAP ( Y => n_5147, IN1 => ix484_nx38_aOUT);
dffe_4219: DFFE
PORT MAP ( D => ix484_a2_dup_556_aD, CLK => ix484_a2_dup_556_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_556_aENA, Q => ix484_a2_dup_556_Q);
xor2_4220: XOR2
PORT MAP ( Y => ix484_a2_dup_556_aD, IN1 => n_5154, IN2 => n_5157);
or1_4221: OR1
PORT MAP ( Y => n_5154, IN1 => n_5155);
and1_4222: AND1
PORT MAP ( Y => n_5155, IN1 => n_5156);
delay_4223: DELAY
PORT MAP ( Y => n_5156, IN1 => data(12));
and1_4224: AND1
PORT MAP ( Y => n_5157, IN1 => gnd);
and1_4225: AND1
PORT MAP ( Y => n_5158, IN1 => n_5159);
delay_4226: DELAY
PORT MAP ( Y => n_5159, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4227: DELAY
PORT MAP ( Y => ix484_a2_dup_556_aCLK, IN1 => n_5158);
and1_4228: AND1
PORT MAP ( Y => ix484_a2_dup_556_aENA, IN1 => n_5162);
delay_4229: DELAY
PORT MAP ( Y => n_5162, IN1 => ix484_nx43_aOUT);
dffe_4230: DFFE
PORT MAP ( D => ix484_a7_dup_551_aD, CLK => ix484_a7_dup_551_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_551_aENA, Q => ix484_a7_dup_551_Q);
xor2_4231: XOR2
PORT MAP ( Y => ix484_a7_dup_551_aD, IN1 => n_5169, IN2 => n_5172);
or1_4232: OR1
PORT MAP ( Y => n_5169, IN1 => n_5170);
and1_4233: AND1
PORT MAP ( Y => n_5170, IN1 => n_5171);
delay_4234: DELAY
PORT MAP ( Y => n_5171, IN1 => data(12));
and1_4235: AND1
PORT MAP ( Y => n_5172, IN1 => gnd);
and1_4236: AND1
PORT MAP ( Y => n_5173, IN1 => n_5174);
delay_4237: DELAY
PORT MAP ( Y => n_5174, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4238: DELAY
PORT MAP ( Y => ix484_a7_dup_551_aCLK, IN1 => n_5173);
and1_4239: AND1
PORT MAP ( Y => ix484_a7_dup_551_aENA, IN1 => n_5177);
delay_4240: DELAY
PORT MAP ( Y => n_5177, IN1 => ix484_nx38_aOUT);
dffe_4241: DFFE
PORT MAP ( D => ix484_a2_dup_548_aD, CLK => ix484_a2_dup_548_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_548_aENA, Q => ix484_a2_dup_548_Q);
xor2_4242: XOR2
PORT MAP ( Y => ix484_a2_dup_548_aD, IN1 => n_5184, IN2 => n_5187);
or1_4243: OR1
PORT MAP ( Y => n_5184, IN1 => n_5185);
and1_4244: AND1
PORT MAP ( Y => n_5185, IN1 => n_5186);
delay_4245: DELAY
PORT MAP ( Y => n_5186, IN1 => data(13));
and1_4246: AND1
PORT MAP ( Y => n_5187, IN1 => gnd);
and1_4247: AND1
PORT MAP ( Y => n_5188, IN1 => n_5189);
delay_4248: DELAY
PORT MAP ( Y => n_5189, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4249: DELAY
PORT MAP ( Y => ix484_a2_dup_548_aCLK, IN1 => n_5188);
and1_4250: AND1
PORT MAP ( Y => ix484_a2_dup_548_aENA, IN1 => n_5192);
delay_4251: DELAY
PORT MAP ( Y => n_5192, IN1 => ix484_nx43_aOUT);
dffe_4252: DFFE
PORT MAP ( D => ix484_a7_dup_543_aD, CLK => ix484_a7_dup_543_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_543_aENA, Q => ix484_a7_dup_543_Q);
xor2_4253: XOR2
PORT MAP ( Y => ix484_a7_dup_543_aD, IN1 => n_5199, IN2 => n_5202);
or1_4254: OR1
PORT MAP ( Y => n_5199, IN1 => n_5200);
and1_4255: AND1
PORT MAP ( Y => n_5200, IN1 => n_5201);
delay_4256: DELAY
PORT MAP ( Y => n_5201, IN1 => data(13));
and1_4257: AND1
PORT MAP ( Y => n_5202, IN1 => gnd);
and1_4258: AND1
PORT MAP ( Y => n_5203, IN1 => n_5204);
delay_4259: DELAY
PORT MAP ( Y => n_5204, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4260: DELAY
PORT MAP ( Y => ix484_a7_dup_543_aCLK, IN1 => n_5203);
and1_4261: AND1
PORT MAP ( Y => ix484_a7_dup_543_aENA, IN1 => n_5207);
delay_4262: DELAY
PORT MAP ( Y => n_5207, IN1 => ix484_nx38_aOUT);
dffe_4263: DFFE
PORT MAP ( D => ix484_a2_dup_540_aD, CLK => ix484_a2_dup_540_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_540_aENA, Q => ix484_a2_dup_540_Q);
xor2_4264: XOR2
PORT MAP ( Y => ix484_a2_dup_540_aD, IN1 => n_5214, IN2 => n_5217);
or1_4265: OR1
PORT MAP ( Y => n_5214, IN1 => n_5215);
and1_4266: AND1
PORT MAP ( Y => n_5215, IN1 => n_5216);
delay_4267: DELAY
PORT MAP ( Y => n_5216, IN1 => data(14));
and1_4268: AND1
PORT MAP ( Y => n_5217, IN1 => gnd);
and1_4269: AND1
PORT MAP ( Y => n_5218, IN1 => n_5219);
delay_4270: DELAY
PORT MAP ( Y => n_5219, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4271: DELAY
PORT MAP ( Y => ix484_a2_dup_540_aCLK, IN1 => n_5218);
and1_4272: AND1
PORT MAP ( Y => ix484_a2_dup_540_aENA, IN1 => n_5222);
delay_4273: DELAY
PORT MAP ( Y => n_5222, IN1 => ix484_nx43_aOUT);
dffe_4274: DFFE
PORT MAP ( D => ix484_a7_dup_535_aD, CLK => ix484_a7_dup_535_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a7_dup_535_aENA, Q => ix484_a7_dup_535_Q);
xor2_4275: XOR2
PORT MAP ( Y => ix484_a7_dup_535_aD, IN1 => n_5229, IN2 => n_5232);
or1_4276: OR1
PORT MAP ( Y => n_5229, IN1 => n_5230);
and1_4277: AND1
PORT MAP ( Y => n_5230, IN1 => n_5231);
delay_4278: DELAY
PORT MAP ( Y => n_5231, IN1 => data(14));
and1_4279: AND1
PORT MAP ( Y => n_5232, IN1 => gnd);
and1_4280: AND1
PORT MAP ( Y => n_5233, IN1 => n_5234);
delay_4281: DELAY
PORT MAP ( Y => n_5234, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4282: DELAY
PORT MAP ( Y => ix484_a7_dup_535_aCLK, IN1 => n_5233);
and1_4283: AND1
PORT MAP ( Y => ix484_a7_dup_535_aENA, IN1 => n_5237);
delay_4284: DELAY
PORT MAP ( Y => n_5237, IN1 => ix484_nx38_aOUT);
dff_4285: DFF
PORT MAP ( D => instrregout12_aD, CLK => instrregout12_aCLK, CLRN => vcc,
PRN => vcc, Q => instrregout12_Q);
xor2_4286: XOR2
PORT MAP ( Y => instrregout12_aD, IN1 => n_5243, IN2 => n_5246);
or1_4287: OR1
PORT MAP ( Y => n_5243, IN1 => n_5244);
and1_4288: AND1
PORT MAP ( Y => n_5244, IN1 => n_5245);
delay_4289: DELAY
PORT MAP ( Y => n_5245, IN1 => data(12));
and1_4290: AND1
PORT MAP ( Y => n_5246, IN1 => gnd);
and1_4291: AND1
PORT MAP ( Y => n_5247, IN1 => n_5248);
delay_4292: DELAY
PORT MAP ( Y => n_5248, IN1 => a_as_or3_aix1644_a_a32_aOUT);
delay_4293: DELAY
PORT MAP ( Y => instrregout12_aCLK, IN1 => n_5247);
dffe_4294: DFFE
PORT MAP ( D => ix484_a2_dup_532_aD, CLK => ix484_a2_dup_532_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a2_dup_532_aENA, Q => ix484_a2_dup_532_Q);
xor2_4295: XOR2
PORT MAP ( Y => ix484_a2_dup_532_aD, IN1 => n_5256, IN2 => n_5259);
or1_4296: OR1
PORT MAP ( Y => n_5256, IN1 => n_5257);
and1_4297: AND1
PORT MAP ( Y => n_5257, IN1 => n_5258);
delay_4298: DELAY
PORT MAP ( Y => n_5258, IN1 => data(15));
and1_4299: AND1
PORT MAP ( Y => n_5259, IN1 => gnd);
and1_4300: AND1
PORT MAP ( Y => n_5260, IN1 => n_5261);
delay_4301: DELAY
PORT MAP ( Y => n_5261, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4302: DELAY
PORT MAP ( Y => ix484_a2_dup_532_aCLK, IN1 => n_5260);
and1_4303: AND1
PORT MAP ( Y => ix484_a2_dup_532_aENA, IN1 => n_5264);
delay_4304: DELAY
PORT MAP ( Y => n_5264, IN1 => ix484_nx43_aOUT);
dffe_4305: DFFE
PORT MAP ( D => ix484_a7_aD, CLK => ix484_a7_aCLK, CLRN => vcc, PRN => vcc,
ENA => ix484_a7_aENA, Q => ix484_a7_Q);
xor2_4306: XOR2
PORT MAP ( Y => ix484_a7_aD, IN1 => n_5271, IN2 => n_5274);
or1_4307: OR1
PORT MAP ( Y => n_5271, IN1 => n_5272);
and1_4308: AND1
PORT MAP ( Y => n_5272, IN1 => n_5273);
delay_4309: DELAY
PORT MAP ( Y => n_5273, IN1 => data(15));
and1_4310: AND1
PORT MAP ( Y => n_5274, IN1 => gnd);
and1_4311: AND1
PORT MAP ( Y => n_5275, IN1 => n_5276);
delay_4312: DELAY
PORT MAP ( Y => n_5276, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4313: DELAY
PORT MAP ( Y => ix484_a7_aCLK, IN1 => n_5275);
and1_4314: AND1
PORT MAP ( Y => ix484_a7_aENA, IN1 => n_5279);
delay_4315: DELAY
PORT MAP ( Y => n_5279, IN1 => ix484_nx38_aOUT);
inv_4316: INV
PORT MAP ( Y => con1_current_state0_Q, IN1 => con1_current_state0_aQ_aNOT);
dff_4317: DFF
PORT MAP ( D => n_5286, CLK => con1_current_state0_aCLK, CLRN => con1_current_state0_aPRN,
PRN => vcc, Q => con1_current_state0_aQ_aNOT);
inv_4318: INV
PORT MAP ( Y => con1_current_state0_aPRN, IN1 => reset);
inv_4319: INV
PORT MAP ( Y => con1_current_state0_aD, IN1 => n_5286);
xor2_4320: XOR2
PORT MAP ( Y => n_5286, IN1 => n_5288, IN2 => n_5290);
or1_4321: OR1
PORT MAP ( Y => n_5288, IN1 => n_5289);
and1_4322: AND1
PORT MAP ( Y => n_5289, IN1 => vcc);
and1_4323: AND1
PORT MAP ( Y => n_5290, IN1 => gnd);
delay_4324: DELAY
PORT MAP ( Y => con1_current_state0_aCLK, IN1 => clock);
delay_4325: DELAY
PORT MAP ( Y => I1_dup_708_aOUT, IN1 => I1_dup_708_aIN);
xor2_4326: XOR2
PORT MAP ( Y => I1_dup_708_aIN, IN1 => n_5294, IN2 => n_5302);
or3_4327: OR3
PORT MAP ( Y => n_5294, IN1 => n_5295, IN2 => n_5297, IN3 => n_5300);
and1_4328: AND1
PORT MAP ( Y => n_5295, IN1 => n_5296);
delay_4329: DELAY
PORT MAP ( Y => n_5296, IN1 => rw_dup0_Q);
and2_4330: AND2
PORT MAP ( Y => n_5297, IN1 => n_5298, IN2 => n_5299);
inv_4331: INV
PORT MAP ( Y => n_5298, IN1 => comp1_nx38_aOUT);
delay_4332: DELAY
PORT MAP ( Y => n_5299, IN1 => con1_current_state32_Q);
and1_4333: AND1
PORT MAP ( Y => n_5300, IN1 => n_5301);
delay_4334: DELAY
PORT MAP ( Y => n_5301, IN1 => a_as_or3_aix1635_a_a32_aOUT);
and1_4335: AND1
PORT MAP ( Y => n_5302, IN1 => gnd);
delay_4336: DELAY
PORT MAP ( Y => O_dup_926_aOUT, IN1 => O_dup_926_aIN);
xor2_4337: XOR2
PORT MAP ( Y => O_dup_926_aIN, IN1 => n_5305, IN2 => n_5310);
or2_4338: OR2
PORT MAP ( Y => n_5305, IN1 => n_5306, IN2 => n_5308);
and1_4339: AND1
PORT MAP ( Y => n_5306, IN1 => n_5307);
delay_4340: DELAY
PORT MAP ( Y => n_5307, IN1 => instrregout12_Q);
and1_4341: AND1
PORT MAP ( Y => n_5308, IN1 => n_5309);
delay_4342: DELAY
PORT MAP ( Y => n_5309, IN1 => I3_dup_732_aOUT);
and1_4343: AND1
PORT MAP ( Y => n_5310, IN1 => gnd);
delay_4344: DELAY
PORT MAP ( Y => I3_dup_710_aOUT, IN1 => I3_dup_710_aIN);
xor2_4345: XOR2
PORT MAP ( Y => I3_dup_710_aIN, IN1 => n_5313, IN2 => n_5320);
or1_4346: OR1
PORT MAP ( Y => n_5313, IN1 => n_5314);
and3_4347: AND3
PORT MAP ( Y => n_5314, IN1 => n_5315, IN2 => n_5317, IN3 => n_5319);
inv_4348: INV
PORT MAP ( Y => n_5315, IN1 => I3_dup_900_aOUT);
delay_4349: DELAY
PORT MAP ( Y => n_5317, IN1 => I2_dup_1023_aOUT);
delay_4350: DELAY
PORT MAP ( Y => n_5319, IN1 => O_dup_926_aOUT);
and1_4351: AND1
PORT MAP ( Y => n_5320, IN1 => gnd);
delay_4352: DELAY
PORT MAP ( Y => I3_dup_1028_aOUT, IN1 => I3_dup_1028_aIN);
xor2_4353: XOR2
PORT MAP ( Y => I3_dup_1028_aIN, IN1 => n_5323, IN2 => n_5331);
or1_4354: OR1
PORT MAP ( Y => n_5323, IN1 => n_5324);
and4_4355: AND4
PORT MAP ( Y => n_5324, IN1 => n_5325, IN2 => n_5327, IN3 => n_5328, IN4 => n_5329);
inv_4356: INV
PORT MAP ( Y => n_5325, IN1 => con1_current_state25_Q);
inv_4357: INV
PORT MAP ( Y => n_5327, IN1 => con1_current_state38_Q);
inv_4358: INV
PORT MAP ( Y => n_5328, IN1 => con1_current_state43_Q);
inv_4359: INV
PORT MAP ( Y => n_5329, IN1 => con1_current_state29_Q);
and1_4360: AND1
PORT MAP ( Y => n_5331, IN1 => gnd);
delay_4361: DELAY
PORT MAP ( Y => alusel3_aOUT, IN1 => alusel3_aIN);
xor2_4362: XOR2
PORT MAP ( Y => alusel3_aIN, IN1 => n_5334, IN2 => n_5339);
or2_4363: OR2
PORT MAP ( Y => n_5334, IN1 => n_5335, IN2 => n_5337);
and1_4364: AND1
PORT MAP ( Y => n_5335, IN1 => n_5336);
delay_4365: DELAY
PORT MAP ( Y => n_5336, IN1 => con1_current_state1_Q);
and1_4366: AND1
PORT MAP ( Y => n_5337, IN1 => n_5338);
inv_4367: INV
PORT MAP ( Y => n_5338, IN1 => con1_current_state0_aQ_aNOT);
and1_4368: AND1
PORT MAP ( Y => n_5339, IN1 => gnd);
delay_4369: DELAY
PORT MAP ( Y => I3_dup_682_aOUT, IN1 => I3_dup_682_aIN);
xor2_4370: XOR2
PORT MAP ( Y => I3_dup_682_aIN, IN1 => n_5342, IN2 => n_5349);
or2_4371: OR2
PORT MAP ( Y => n_5342, IN1 => n_5343, IN2 => n_5346);
and1_4372: AND1
PORT MAP ( Y => n_5343, IN1 => n_5344);
delay_4373: DELAY
PORT MAP ( Y => n_5344, IN1 => con1_current_state14_Q);
and1_4374: AND1
PORT MAP ( Y => n_5346, IN1 => n_5347);
delay_4375: DELAY
PORT MAP ( Y => n_5347, IN1 => con1_current_state11_Q);
and1_4376: AND1
PORT MAP ( Y => n_5349, IN1 => gnd);
inv_4377: INV
PORT MAP ( Y => a_as_or4_aix1643_a_a34_aOUT, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_4378: DELAY
PORT MAP ( Y => a_as_or4_aix1643_a_a34_aOUT_aNOT, IN1 => n_5352);
inv_4379: INV
PORT MAP ( Y => a_as_or4_aix1643_a_a34_aIN1, IN1 => n_5352);
xor2_4380: XOR2
PORT MAP ( Y => n_5352, IN1 => n_5354, IN2 => n_5361);
or1_4381: OR1
PORT MAP ( Y => n_5354, IN1 => n_5355);
and4_4382: AND4
PORT MAP ( Y => n_5355, IN1 => n_5356, IN2 => n_5357, IN3 => n_5359, IN4 => n_5360);
inv_4383: INV
PORT MAP ( Y => n_5356, IN1 => con1_current_state23_Q);
inv_4384: INV
PORT MAP ( Y => n_5357, IN1 => con1_current_state27_Q);
inv_4385: INV
PORT MAP ( Y => n_5359, IN1 => I3_dup_682_aOUT);
inv_4386: INV
PORT MAP ( Y => n_5360, IN1 => I2_dup_681_aOUT);
and1_4387: AND1
PORT MAP ( Y => n_5361, IN1 => gnd);
delay_4388: DELAY
PORT MAP ( Y => O_dup_1005_aOUT, IN1 => O_dup_1005_aIN);
xor2_4389: XOR2
PORT MAP ( Y => O_dup_1005_aIN, IN1 => n_5364, IN2 => n_5372);
or1_4390: OR1
PORT MAP ( Y => n_5364, IN1 => n_5365);
and4_4391: AND4
PORT MAP ( Y => n_5365, IN1 => n_5366, IN2 => n_5368, IN3 => n_5370, IN4 => n_5371);
inv_4392: INV
PORT MAP ( Y => n_5366, IN1 => con1_current_state42_Q);
inv_4393: INV
PORT MAP ( Y => n_5368, IN1 => con1_current_state37_Q);
inv_4394: INV
PORT MAP ( Y => n_5370, IN1 => con1_current_state40_Q);
inv_4395: INV
PORT MAP ( Y => n_5371, IN1 => con1_current_state45_Q);
and1_4396: AND1
PORT MAP ( Y => n_5372, IN1 => gnd);
delay_4397: DELAY
PORT MAP ( Y => O_dup_1572_aOUT, IN1 => O_dup_1572_aIN);
and2_4398: AND2
PORT MAP ( Y => O_dup_1572_aIN, IN1 => n_5375, IN2 => n_5384);
or1_4399: OR1
PORT MAP ( Y => n_5375, IN1 => n_5376);
and4_4400: AND4
PORT MAP ( Y => n_5376, IN1 => n_5377, IN2 => n_5379, IN3 => n_5381, IN4 => n_5383);
inv_4401: INV
PORT MAP ( Y => n_5377, IN1 => con1_current_state26_Q);
inv_4402: INV
PORT MAP ( Y => n_5379, IN1 => con1_current_state24_Q);
inv_4403: INV
PORT MAP ( Y => n_5381, IN1 => con1_current_state28_Q);
inv_4404: INV
PORT MAP ( Y => n_5383, IN1 => con1_current_state35_Q);
delay_4405: DELAY
PORT MAP ( Y => n_5384, IN1 => O_dup_1005_aIN);
delay_4406: DELAY
PORT MAP ( Y => I1_dup_989_aOUT, IN1 => I1_dup_989_aIN);
and2_4407: AND2
PORT MAP ( Y => I1_dup_989_aIN, IN1 => n_5387, IN2 => n_5393);
or1_4408: OR1
PORT MAP ( Y => n_5387, IN1 => n_5388);
and4_4409: AND4
PORT MAP ( Y => n_5388, IN1 => n_5389, IN2 => n_5390, IN3 => n_5391, IN4 => n_5392);
inv_4410: INV
PORT MAP ( Y => n_5389, IN1 => con1_current_state32_Q);
inv_4411: INV
PORT MAP ( Y => n_5390, IN1 => con1_current_state31_Q);
inv_4412: INV
PORT MAP ( Y => n_5391, IN1 => opregwr_Q);
delay_4413: DELAY
PORT MAP ( Y => n_5392, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_4414: DELAY
PORT MAP ( Y => n_5393, IN1 => O_dup_1572_aIN);
delay_4415: DELAY
PORT MAP ( Y => O_dup_990_aOUT, IN1 => O_dup_990_aIN);
and2_4416: AND2
PORT MAP ( Y => O_dup_990_aIN, IN1 => n_5396, IN2 => n_5403);
or1_4417: OR1
PORT MAP ( Y => n_5396, IN1 => n_5397);
and4_4418: AND4
PORT MAP ( Y => n_5397, IN1 => n_5398, IN2 => n_5399, IN3 => n_5401, IN4 => n_5402);
inv_4419: INV
PORT MAP ( Y => n_5398, IN1 => con1_current_state48_Q);
inv_4420: INV
PORT MAP ( Y => n_5399, IN1 => con1_current_state47_Q);
inv_4421: INV
PORT MAP ( Y => n_5401, IN1 => alusel3_aOUT);
inv_4422: INV
PORT MAP ( Y => n_5402, IN1 => con1_current_state50_Q);
delay_4423: DELAY
PORT MAP ( Y => n_5403, IN1 => I1_dup_989_aIN);
delay_4424: DELAY
PORT MAP ( Y => O_dup_1589_aOUT, IN1 => O_dup_1589_aIN);
and2_4425: AND2
PORT MAP ( Y => O_dup_1589_aIN, IN1 => n_5406, IN2 => n_5414);
or1_4426: OR1
PORT MAP ( Y => n_5406, IN1 => n_5407);
and4_4427: AND4
PORT MAP ( Y => n_5407, IN1 => n_5408, IN2 => n_5410, IN3 => n_5412, IN4 => n_5413);
inv_4428: INV
PORT MAP ( Y => n_5408, IN1 => con1_current_state15_Q);
inv_4429: INV
PORT MAP ( Y => n_5410, IN1 => con1_current_state22_Q);
inv_4430: INV
PORT MAP ( Y => n_5412, IN1 => con1_current_state18_Q);
inv_4431: INV
PORT MAP ( Y => n_5413, IN1 => con1_current_state17_Q);
delay_4432: DELAY
PORT MAP ( Y => n_5414, IN1 => O_dup_990_aIN);
delay_4433: DELAY
PORT MAP ( Y => I1_dup_986_aOUT, IN1 => I1_dup_986_aIN);
and2_4434: AND2
PORT MAP ( Y => I1_dup_986_aIN, IN1 => n_5417, IN2 => n_5427);
or1_4435: OR1
PORT MAP ( Y => n_5417, IN1 => n_5418);
and4_4436: AND4
PORT MAP ( Y => n_5418, IN1 => n_5419, IN2 => n_5421, IN3 => n_5423, IN4 => n_5425);
inv_4437: INV
PORT MAP ( Y => n_5419, IN1 => con1_current_state4_Q);
inv_4438: INV
PORT MAP ( Y => n_5421, IN1 => con1_current_state2_Q);
inv_4439: INV
PORT MAP ( Y => n_5423, IN1 => con1_current_state5_Q);
inv_4440: INV
PORT MAP ( Y => n_5425, IN1 => con1_current_state12_Q);
delay_4441: DELAY
PORT MAP ( Y => n_5427, IN1 => O_dup_1589_aIN);
delay_4442: DELAY
PORT MAP ( Y => I2_dup_709_aOUT, IN1 => I2_dup_709_aIN1);
and2_4443: AND2
PORT MAP ( Y => I2_dup_709_aIN1, IN1 => n_5430, IN2 => n_5436);
or1_4444: OR1
PORT MAP ( Y => n_5430, IN1 => n_5431);
and4_4445: AND4
PORT MAP ( Y => n_5431, IN1 => n_5432, IN2 => n_5433, IN3 => n_5434, IN4 => n_5435);
inv_4446: INV
PORT MAP ( Y => n_5432, IN1 => con1_current_state21_Q);
inv_4447: INV
PORT MAP ( Y => n_5433, IN1 => con1_current_state49_Q);
inv_4448: INV
PORT MAP ( Y => n_5434, IN1 => I3_dup_696_aOUT);
delay_4449: DELAY
PORT MAP ( Y => n_5435, IN1 => I3_dup_1028_aOUT);
delay_4450: DELAY
PORT MAP ( Y => n_5436, IN1 => I1_dup_986_aIN);
dff_4451: DFF
PORT MAP ( D => con1_current_state20_aD, CLK => con1_current_state20_aCLK,
CLRN => con1_current_state20_aCLRN, PRN => vcc, Q => con1_current_state20_Q);
inv_4452: INV
PORT MAP ( Y => con1_current_state20_aCLRN, IN1 => reset);
xor2_4453: XOR2
PORT MAP ( Y => con1_current_state20_aD, IN1 => n_5444, IN2 => n_5453);
or3_4454: OR3
PORT MAP ( Y => n_5444, IN1 => n_5445, IN2 => n_5447, IN3 => n_5450);
and1_4455: AND1
PORT MAP ( Y => n_5445, IN1 => n_5446);
delay_4456: DELAY
PORT MAP ( Y => n_5446, IN1 => I1_dup_708_aOUT);
and2_4457: AND2
PORT MAP ( Y => n_5447, IN1 => n_5448, IN2 => n_5449);
delay_4458: DELAY
PORT MAP ( Y => n_5448, IN1 => I3_dup_710_aOUT);
delay_4459: DELAY
PORT MAP ( Y => n_5449, IN1 => con1_current_state6_Q);
and2_4460: AND2
PORT MAP ( Y => n_5450, IN1 => n_5451, IN2 => n_5452);
inv_4461: INV
PORT MAP ( Y => n_5451, IN1 => con1_current_state6_Q);
delay_4462: DELAY
PORT MAP ( Y => n_5452, IN1 => I2_dup_709_aOUT);
and1_4463: AND1
PORT MAP ( Y => n_5453, IN1 => gnd);
delay_4464: DELAY
PORT MAP ( Y => con1_current_state20_aCLK, IN1 => clock);
dff_4465: DFF
PORT MAP ( D => con1_current_state46_aD, CLK => con1_current_state46_aCLK,
CLRN => con1_current_state46_aCLRN, PRN => vcc, Q => con1_current_state46_Q);
inv_4466: INV
PORT MAP ( Y => con1_current_state46_aCLRN, IN1 => reset);
xor2_4467: XOR2
PORT MAP ( Y => con1_current_state46_aD, IN1 => n_5462, IN2 => n_5465);
or1_4468: OR1
PORT MAP ( Y => n_5462, IN1 => n_5463);
and1_4469: AND1
PORT MAP ( Y => n_5463, IN1 => n_5464);
delay_4470: DELAY
PORT MAP ( Y => n_5464, IN1 => con1_current_state45_Q);
and1_4471: AND1
PORT MAP ( Y => n_5465, IN1 => gnd);
delay_4472: DELAY
PORT MAP ( Y => con1_current_state46_aCLK, IN1 => clock);
dff_4473: DFF
PORT MAP ( D => con1_current_state41_aD, CLK => con1_current_state41_aCLK,
CLRN => con1_current_state41_aCLRN, PRN => vcc, Q => con1_current_state41_Q);
inv_4474: INV
PORT MAP ( Y => con1_current_state41_aCLRN, IN1 => reset);
xor2_4475: XOR2
PORT MAP ( Y => con1_current_state41_aD, IN1 => n_5474, IN2 => n_5477);
or1_4476: OR1
PORT MAP ( Y => n_5474, IN1 => n_5475);
and1_4477: AND1
PORT MAP ( Y => n_5475, IN1 => n_5476);
delay_4478: DELAY
PORT MAP ( Y => n_5476, IN1 => con1_current_state40_Q);
and1_4479: AND1
PORT MAP ( Y => n_5477, IN1 => gnd);
delay_4480: DELAY
PORT MAP ( Y => con1_current_state41_aCLK, IN1 => clock);
dff_4481: DFF
PORT MAP ( D => con1_current_state36_aD, CLK => con1_current_state36_aCLK,
CLRN => con1_current_state36_aCLRN, PRN => vcc, Q => con1_current_state36_Q);
inv_4482: INV
PORT MAP ( Y => con1_current_state36_aCLRN, IN1 => reset);
xor2_4483: XOR2
PORT MAP ( Y => con1_current_state36_aD, IN1 => n_5486, IN2 => n_5489);
or1_4484: OR1
PORT MAP ( Y => n_5486, IN1 => n_5487);
and1_4485: AND1
PORT MAP ( Y => n_5487, IN1 => n_5488);
delay_4486: DELAY
PORT MAP ( Y => n_5488, IN1 => con1_current_state35_Q);
and1_4487: AND1
PORT MAP ( Y => n_5489, IN1 => gnd);
delay_4488: DELAY
PORT MAP ( Y => con1_current_state36_aCLK, IN1 => clock);
dff_4489: DFF
PORT MAP ( D => con1_current_state37_aD, CLK => con1_current_state37_aCLK,
CLRN => con1_current_state37_aCLRN, PRN => vcc, Q => con1_current_state37_Q);
inv_4490: INV
PORT MAP ( Y => con1_current_state37_aCLRN, IN1 => reset);
xor2_4491: XOR2
PORT MAP ( Y => con1_current_state37_aD, IN1 => n_5497, IN2 => n_5500);
or1_4492: OR1
PORT MAP ( Y => n_5497, IN1 => n_5498);
and1_4493: AND1
PORT MAP ( Y => n_5498, IN1 => n_5499);
delay_4494: DELAY
PORT MAP ( Y => n_5499, IN1 => con1_current_state36_Q);
and1_4495: AND1
PORT MAP ( Y => n_5500, IN1 => gnd);
delay_4496: DELAY
PORT MAP ( Y => con1_current_state37_aCLK, IN1 => clock);
dff_4497: DFF
PORT MAP ( D => con1_current_state42_aD, CLK => con1_current_state42_aCLK,
CLRN => con1_current_state42_aCLRN, PRN => vcc, Q => con1_current_state42_Q);
inv_4498: INV
PORT MAP ( Y => con1_current_state42_aCLRN, IN1 => reset);
xor2_4499: XOR2
PORT MAP ( Y => con1_current_state42_aD, IN1 => n_5508, IN2 => n_5511);
or1_4500: OR1
PORT MAP ( Y => n_5508, IN1 => n_5509);
and1_4501: AND1
PORT MAP ( Y => n_5509, IN1 => n_5510);
delay_4502: DELAY
PORT MAP ( Y => n_5510, IN1 => con1_current_state41_Q);
and1_4503: AND1
PORT MAP ( Y => n_5511, IN1 => gnd);
delay_4504: DELAY
PORT MAP ( Y => con1_current_state42_aCLK, IN1 => clock);
dff_4505: DFF
PORT MAP ( D => con1_current_state28_aD, CLK => con1_current_state28_aCLK,
CLRN => con1_current_state28_aCLRN, PRN => vcc, Q => con1_current_state28_Q);
inv_4506: INV
PORT MAP ( Y => con1_current_state28_aCLRN, IN1 => reset);
xor2_4507: XOR2
PORT MAP ( Y => con1_current_state28_aD, IN1 => n_5519, IN2 => n_5522);
or1_4508: OR1
PORT MAP ( Y => n_5519, IN1 => n_5520);
and1_4509: AND1
PORT MAP ( Y => n_5520, IN1 => n_5521);
delay_4510: DELAY
PORT MAP ( Y => n_5521, IN1 => con1_current_state27_Q);
and1_4511: AND1
PORT MAP ( Y => n_5522, IN1 => gnd);
delay_4512: DELAY
PORT MAP ( Y => con1_current_state28_aCLK, IN1 => clock);
delay_4513: DELAY
PORT MAP ( Y => con1_modgen_61_nx10_aOUT, IN1 => con1_modgen_61_nx10_aIN);
xor2_4514: XOR2
PORT MAP ( Y => con1_modgen_61_nx10_aIN, IN1 => n_5526, IN2 => n_5531);
or2_4515: OR2
PORT MAP ( Y => n_5526, IN1 => n_5527, IN2 => n_5529);
and1_4516: AND1
PORT MAP ( Y => n_5527, IN1 => n_5528);
delay_4517: DELAY
PORT MAP ( Y => n_5528, IN1 => instrregout12_Q);
and1_4518: AND1
PORT MAP ( Y => n_5529, IN1 => n_5530);
inv_4519: INV
PORT MAP ( Y => n_5530, IN1 => instrregout11_Q);
and1_4520: AND1
PORT MAP ( Y => n_5531, IN1 => gnd);
dff_4521: DFF
PORT MAP ( D => con1_current_state11_aD, CLK => con1_current_state11_aCLK,
CLRN => con1_current_state11_aCLRN, PRN => vcc, Q => con1_current_state11_Q);
inv_4522: INV
PORT MAP ( Y => con1_current_state11_aCLRN, IN1 => reset);
xor2_4523: XOR2
PORT MAP ( Y => con1_current_state11_aD, IN1 => n_5538, IN2 => n_5544);
or1_4524: OR1
PORT MAP ( Y => n_5538, IN1 => n_5539);
and4_4525: AND4
PORT MAP ( Y => n_5539, IN1 => n_5540, IN2 => n_5541, IN3 => n_5542, IN4 => n_5543);
inv_4526: INV
PORT MAP ( Y => n_5540, IN1 => con1_modgen_61_nx10_aOUT);
inv_4527: INV
PORT MAP ( Y => n_5541, IN1 => instrregout15_Q);
inv_4528: INV
PORT MAP ( Y => n_5542, IN1 => con1_modgen_61_nx12_aOUT);
delay_4529: DELAY
PORT MAP ( Y => n_5543, IN1 => con1_current_state6_Q);
and1_4530: AND1
PORT MAP ( Y => n_5544, IN1 => gnd);
delay_4531: DELAY
PORT MAP ( Y => con1_current_state11_aCLK, IN1 => clock);
dff_4532: DFF
PORT MAP ( D => con1_current_state47_aD, CLK => con1_current_state47_aCLK,
CLRN => con1_current_state47_aCLRN, PRN => vcc, Q => con1_current_state47_Q);
inv_4533: INV
PORT MAP ( Y => con1_current_state47_aCLRN, IN1 => reset);
xor2_4534: XOR2
PORT MAP ( Y => con1_current_state47_aD, IN1 => n_5552, IN2 => n_5555);
or1_4535: OR1
PORT MAP ( Y => n_5552, IN1 => n_5553);
and1_4536: AND1
PORT MAP ( Y => n_5553, IN1 => n_5554);
delay_4537: DELAY
PORT MAP ( Y => n_5554, IN1 => con1_current_state46_Q);
and1_4538: AND1
PORT MAP ( Y => n_5555, IN1 => gnd);
delay_4539: DELAY
PORT MAP ( Y => con1_current_state47_aCLK, IN1 => clock);
dff_4540: DFF
PORT MAP ( D => con1_current_state1_aD, CLK => con1_current_state1_aCLK,
CLRN => con1_current_state1_aCLRN, PRN => vcc, Q => con1_current_state1_Q);
inv_4541: INV
PORT MAP ( Y => con1_current_state1_aCLRN, IN1 => reset);
xor2_4542: XOR2
PORT MAP ( Y => con1_current_state1_aD, IN1 => n_5563, IN2 => n_5566);
or1_4543: OR1
PORT MAP ( Y => n_5563, IN1 => n_5564);
and1_4544: AND1
PORT MAP ( Y => n_5564, IN1 => n_5565);
inv_4545: INV
PORT MAP ( Y => n_5565, IN1 => con1_current_state0_aQ_aNOT);
and1_4546: AND1
PORT MAP ( Y => n_5566, IN1 => gnd);
delay_4547: DELAY
PORT MAP ( Y => con1_current_state1_aCLK, IN1 => clock);
dff_4548: DFF
PORT MAP ( D => con1_current_state6_aD, CLK => con1_current_state6_aCLK,
CLRN => con1_current_state6_aCLRN, PRN => vcc, Q => con1_current_state6_Q);
inv_4549: INV
PORT MAP ( Y => con1_current_state6_aCLRN, IN1 => reset);
xor2_4550: XOR2
PORT MAP ( Y => con1_current_state6_aD, IN1 => n_5574, IN2 => n_5584);
or3_4551: OR3
PORT MAP ( Y => n_5574, IN1 => n_5575, IN2 => n_5578, IN3 => n_5581);
and2_4552: AND2
PORT MAP ( Y => n_5575, IN1 => n_5576, IN2 => n_5577);
delay_4553: DELAY
PORT MAP ( Y => n_5576, IN1 => ready);
delay_4554: DELAY
PORT MAP ( Y => n_5577, IN1 => con1_current_state5_Q);
and2_4555: AND2
PORT MAP ( Y => n_5578, IN1 => n_5579, IN2 => n_5580);
delay_4556: DELAY
PORT MAP ( Y => n_5579, IN1 => ready);
delay_4557: DELAY
PORT MAP ( Y => n_5580, IN1 => con1_current_state25_Q);
and2_4558: AND2
PORT MAP ( Y => n_5581, IN1 => n_5582, IN2 => n_5583);
delay_4559: DELAY
PORT MAP ( Y => n_5582, IN1 => ready);
delay_4560: DELAY
PORT MAP ( Y => n_5583, IN1 => con1_current_state29_Q);
and1_4561: AND1
PORT MAP ( Y => n_5584, IN1 => gnd);
delay_4562: DELAY
PORT MAP ( Y => con1_current_state6_aCLK, IN1 => clock);
dff_4563: DFF
PORT MAP ( D => con1_current_state21_aD, CLK => con1_current_state21_aCLK,
CLRN => con1_current_state21_aCLRN, PRN => vcc, Q => con1_current_state21_Q);
inv_4564: INV
PORT MAP ( Y => con1_current_state21_aCLRN, IN1 => reset);
xor2_4565: XOR2
PORT MAP ( Y => con1_current_state21_aD, IN1 => n_5592, IN2 => n_5595);
or1_4566: OR1
PORT MAP ( Y => n_5592, IN1 => n_5593);
and1_4567: AND1
PORT MAP ( Y => n_5593, IN1 => n_5594);
delay_4568: DELAY
PORT MAP ( Y => n_5594, IN1 => con1_current_state20_Q);
and1_4569: AND1
PORT MAP ( Y => n_5595, IN1 => gnd);
delay_4570: DELAY
PORT MAP ( Y => con1_current_state21_aCLK, IN1 => clock);
dffe_4571: DFFE
PORT MAP ( D => ix484_a4_dup_650_aD, CLK => ix484_a4_dup_650_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_650_aENA, Q => ix484_a4_dup_650_Q);
xor2_4572: XOR2
PORT MAP ( Y => ix484_a4_dup_650_aD, IN1 => n_5603, IN2 => n_5606);
or1_4573: OR1
PORT MAP ( Y => n_5603, IN1 => n_5604);
and1_4574: AND1
PORT MAP ( Y => n_5604, IN1 => n_5605);
delay_4575: DELAY
PORT MAP ( Y => n_5605, IN1 => data(0));
and1_4576: AND1
PORT MAP ( Y => n_5606, IN1 => gnd);
and1_4577: AND1
PORT MAP ( Y => n_5607, IN1 => n_5608);
delay_4578: DELAY
PORT MAP ( Y => n_5608, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4579: DELAY
PORT MAP ( Y => ix484_a4_dup_650_aCLK, IN1 => n_5607);
and1_4580: AND1
PORT MAP ( Y => ix484_a4_dup_650_aENA, IN1 => n_5611);
delay_4581: DELAY
PORT MAP ( Y => n_5611, IN1 => ix484_nx41_aOUT);
dffe_4582: DFFE
PORT MAP ( D => ix484_a0_dup_654_aD, CLK => ix484_a0_dup_654_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_654_aENA, Q => ix484_a0_dup_654_Q);
xor2_4583: XOR2
PORT MAP ( Y => ix484_a0_dup_654_aD, IN1 => n_5619, IN2 => n_5622);
or1_4584: OR1
PORT MAP ( Y => n_5619, IN1 => n_5620);
and1_4585: AND1
PORT MAP ( Y => n_5620, IN1 => n_5621);
delay_4586: DELAY
PORT MAP ( Y => n_5621, IN1 => data(0));
and1_4587: AND1
PORT MAP ( Y => n_5622, IN1 => gnd);
and1_4588: AND1
PORT MAP ( Y => n_5623, IN1 => n_5624);
delay_4589: DELAY
PORT MAP ( Y => n_5624, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4590: DELAY
PORT MAP ( Y => ix484_a0_dup_654_aCLK, IN1 => n_5623);
and1_4591: AND1
PORT MAP ( Y => ix484_a0_dup_654_aENA, IN1 => n_5627);
delay_4592: DELAY
PORT MAP ( Y => n_5627, IN1 => ix484_nx45_aOUT);
dffe_4593: DFFE
PORT MAP ( D => ix484_a4_dup_642_aD, CLK => ix484_a4_dup_642_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_642_aENA, Q => ix484_a4_dup_642_Q);
xor2_4594: XOR2
PORT MAP ( Y => ix484_a4_dup_642_aD, IN1 => n_5635, IN2 => n_5638);
or1_4595: OR1
PORT MAP ( Y => n_5635, IN1 => n_5636);
and1_4596: AND1
PORT MAP ( Y => n_5636, IN1 => n_5637);
delay_4597: DELAY
PORT MAP ( Y => n_5637, IN1 => data(1));
and1_4598: AND1
PORT MAP ( Y => n_5638, IN1 => gnd);
and1_4599: AND1
PORT MAP ( Y => n_5639, IN1 => n_5640);
delay_4600: DELAY
PORT MAP ( Y => n_5640, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4601: DELAY
PORT MAP ( Y => ix484_a4_dup_642_aCLK, IN1 => n_5639);
and1_4602: AND1
PORT MAP ( Y => ix484_a4_dup_642_aENA, IN1 => n_5643);
delay_4603: DELAY
PORT MAP ( Y => n_5643, IN1 => ix484_nx41_aOUT);
dffe_4604: DFFE
PORT MAP ( D => ix484_a0_dup_646_aD, CLK => ix484_a0_dup_646_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_646_aENA, Q => ix484_a0_dup_646_Q);
xor2_4605: XOR2
PORT MAP ( Y => ix484_a0_dup_646_aD, IN1 => n_5650, IN2 => n_5653);
or1_4606: OR1
PORT MAP ( Y => n_5650, IN1 => n_5651);
and1_4607: AND1
PORT MAP ( Y => n_5651, IN1 => n_5652);
delay_4608: DELAY
PORT MAP ( Y => n_5652, IN1 => data(1));
and1_4609: AND1
PORT MAP ( Y => n_5653, IN1 => gnd);
and1_4610: AND1
PORT MAP ( Y => n_5654, IN1 => n_5655);
delay_4611: DELAY
PORT MAP ( Y => n_5655, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4612: DELAY
PORT MAP ( Y => ix484_a0_dup_646_aCLK, IN1 => n_5654);
and1_4613: AND1
PORT MAP ( Y => ix484_a0_dup_646_aENA, IN1 => n_5658);
delay_4614: DELAY
PORT MAP ( Y => n_5658, IN1 => ix484_nx45_aOUT);
dffe_4615: DFFE
PORT MAP ( D => ix484_a4_dup_634_aD, CLK => ix484_a4_dup_634_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_634_aENA, Q => ix484_a4_dup_634_Q);
xor2_4616: XOR2
PORT MAP ( Y => ix484_a4_dup_634_aD, IN1 => n_5665, IN2 => n_5668);
or1_4617: OR1
PORT MAP ( Y => n_5665, IN1 => n_5666);
and1_4618: AND1
PORT MAP ( Y => n_5666, IN1 => n_5667);
delay_4619: DELAY
PORT MAP ( Y => n_5667, IN1 => data(2));
and1_4620: AND1
PORT MAP ( Y => n_5668, IN1 => gnd);
and1_4621: AND1
PORT MAP ( Y => n_5669, IN1 => n_5670);
delay_4622: DELAY
PORT MAP ( Y => n_5670, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4623: DELAY
PORT MAP ( Y => ix484_a4_dup_634_aCLK, IN1 => n_5669);
and1_4624: AND1
PORT MAP ( Y => ix484_a4_dup_634_aENA, IN1 => n_5673);
delay_4625: DELAY
PORT MAP ( Y => n_5673, IN1 => ix484_nx41_aOUT);
dffe_4626: DFFE
PORT MAP ( D => ix484_a0_dup_638_aD, CLK => ix484_a0_dup_638_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_638_aENA, Q => ix484_a0_dup_638_Q);
xor2_4627: XOR2
PORT MAP ( Y => ix484_a0_dup_638_aD, IN1 => n_5680, IN2 => n_5683);
or1_4628: OR1
PORT MAP ( Y => n_5680, IN1 => n_5681);
and1_4629: AND1
PORT MAP ( Y => n_5681, IN1 => n_5682);
delay_4630: DELAY
PORT MAP ( Y => n_5682, IN1 => data(2));
and1_4631: AND1
PORT MAP ( Y => n_5683, IN1 => gnd);
and1_4632: AND1
PORT MAP ( Y => n_5684, IN1 => n_5685);
delay_4633: DELAY
PORT MAP ( Y => n_5685, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4634: DELAY
PORT MAP ( Y => ix484_a0_dup_638_aCLK, IN1 => n_5684);
and1_4635: AND1
PORT MAP ( Y => ix484_a0_dup_638_aENA, IN1 => n_5688);
delay_4636: DELAY
PORT MAP ( Y => n_5688, IN1 => ix484_nx45_aOUT);
dffe_4637: DFFE
PORT MAP ( D => ix484_a4_dup_626_aD, CLK => ix484_a4_dup_626_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_626_aENA, Q => ix484_a4_dup_626_Q);
xor2_4638: XOR2
PORT MAP ( Y => ix484_a4_dup_626_aD, IN1 => n_5695, IN2 => n_5698);
or1_4639: OR1
PORT MAP ( Y => n_5695, IN1 => n_5696);
and1_4640: AND1
PORT MAP ( Y => n_5696, IN1 => n_5697);
delay_4641: DELAY
PORT MAP ( Y => n_5697, IN1 => data(3));
and1_4642: AND1
PORT MAP ( Y => n_5698, IN1 => gnd);
and1_4643: AND1
PORT MAP ( Y => n_5699, IN1 => n_5700);
delay_4644: DELAY
PORT MAP ( Y => n_5700, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4645: DELAY
PORT MAP ( Y => ix484_a4_dup_626_aCLK, IN1 => n_5699);
and1_4646: AND1
PORT MAP ( Y => ix484_a4_dup_626_aENA, IN1 => n_5703);
delay_4647: DELAY
PORT MAP ( Y => n_5703, IN1 => ix484_nx41_aOUT);
dffe_4648: DFFE
PORT MAP ( D => ix484_a0_dup_630_aD, CLK => ix484_a0_dup_630_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_630_aENA, Q => ix484_a0_dup_630_Q);
xor2_4649: XOR2
PORT MAP ( Y => ix484_a0_dup_630_aD, IN1 => n_5710, IN2 => n_5713);
or1_4650: OR1
PORT MAP ( Y => n_5710, IN1 => n_5711);
and1_4651: AND1
PORT MAP ( Y => n_5711, IN1 => n_5712);
delay_4652: DELAY
PORT MAP ( Y => n_5712, IN1 => data(3));
and1_4653: AND1
PORT MAP ( Y => n_5713, IN1 => gnd);
and1_4654: AND1
PORT MAP ( Y => n_5714, IN1 => n_5715);
delay_4655: DELAY
PORT MAP ( Y => n_5715, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4656: DELAY
PORT MAP ( Y => ix484_a0_dup_630_aCLK, IN1 => n_5714);
and1_4657: AND1
PORT MAP ( Y => ix484_a0_dup_630_aENA, IN1 => n_5718);
delay_4658: DELAY
PORT MAP ( Y => n_5718, IN1 => ix484_nx45_aOUT);
dffe_4659: DFFE
PORT MAP ( D => ix484_a4_dup_618_aD, CLK => ix484_a4_dup_618_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_618_aENA, Q => ix484_a4_dup_618_Q);
xor2_4660: XOR2
PORT MAP ( Y => ix484_a4_dup_618_aD, IN1 => n_5725, IN2 => n_5728);
or1_4661: OR1
PORT MAP ( Y => n_5725, IN1 => n_5726);
and1_4662: AND1
PORT MAP ( Y => n_5726, IN1 => n_5727);
delay_4663: DELAY
PORT MAP ( Y => n_5727, IN1 => data(4));
and1_4664: AND1
PORT MAP ( Y => n_5728, IN1 => gnd);
and1_4665: AND1
PORT MAP ( Y => n_5729, IN1 => n_5730);
delay_4666: DELAY
PORT MAP ( Y => n_5730, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4667: DELAY
PORT MAP ( Y => ix484_a4_dup_618_aCLK, IN1 => n_5729);
and1_4668: AND1
PORT MAP ( Y => ix484_a4_dup_618_aENA, IN1 => n_5733);
delay_4669: DELAY
PORT MAP ( Y => n_5733, IN1 => ix484_nx41_aOUT);
dffe_4670: DFFE
PORT MAP ( D => ix484_a0_dup_622_aD, CLK => ix484_a0_dup_622_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_622_aENA, Q => ix484_a0_dup_622_Q);
xor2_4671: XOR2
PORT MAP ( Y => ix484_a0_dup_622_aD, IN1 => n_5740, IN2 => n_5743);
or1_4672: OR1
PORT MAP ( Y => n_5740, IN1 => n_5741);
and1_4673: AND1
PORT MAP ( Y => n_5741, IN1 => n_5742);
delay_4674: DELAY
PORT MAP ( Y => n_5742, IN1 => data(4));
and1_4675: AND1
PORT MAP ( Y => n_5743, IN1 => gnd);
and1_4676: AND1
PORT MAP ( Y => n_5744, IN1 => n_5745);
delay_4677: DELAY
PORT MAP ( Y => n_5745, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4678: DELAY
PORT MAP ( Y => ix484_a0_dup_622_aCLK, IN1 => n_5744);
and1_4679: AND1
PORT MAP ( Y => ix484_a0_dup_622_aENA, IN1 => n_5748);
delay_4680: DELAY
PORT MAP ( Y => n_5748, IN1 => ix484_nx45_aOUT);
dffe_4681: DFFE
PORT MAP ( D => ix484_a4_dup_610_aD, CLK => ix484_a4_dup_610_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_610_aENA, Q => ix484_a4_dup_610_Q);
xor2_4682: XOR2
PORT MAP ( Y => ix484_a4_dup_610_aD, IN1 => n_5755, IN2 => n_5758);
or1_4683: OR1
PORT MAP ( Y => n_5755, IN1 => n_5756);
and1_4684: AND1
PORT MAP ( Y => n_5756, IN1 => n_5757);
delay_4685: DELAY
PORT MAP ( Y => n_5757, IN1 => data(5));
and1_4686: AND1
PORT MAP ( Y => n_5758, IN1 => gnd);
and1_4687: AND1
PORT MAP ( Y => n_5759, IN1 => n_5760);
delay_4688: DELAY
PORT MAP ( Y => n_5760, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4689: DELAY
PORT MAP ( Y => ix484_a4_dup_610_aCLK, IN1 => n_5759);
and1_4690: AND1
PORT MAP ( Y => ix484_a4_dup_610_aENA, IN1 => n_5763);
delay_4691: DELAY
PORT MAP ( Y => n_5763, IN1 => ix484_nx41_aOUT);
dffe_4692: DFFE
PORT MAP ( D => ix484_a0_dup_614_aD, CLK => ix484_a0_dup_614_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_614_aENA, Q => ix484_a0_dup_614_Q);
xor2_4693: XOR2
PORT MAP ( Y => ix484_a0_dup_614_aD, IN1 => n_5770, IN2 => n_5773);
or1_4694: OR1
PORT MAP ( Y => n_5770, IN1 => n_5771);
and1_4695: AND1
PORT MAP ( Y => n_5771, IN1 => n_5772);
delay_4696: DELAY
PORT MAP ( Y => n_5772, IN1 => data(5));
and1_4697: AND1
PORT MAP ( Y => n_5773, IN1 => gnd);
and1_4698: AND1
PORT MAP ( Y => n_5774, IN1 => n_5775);
delay_4699: DELAY
PORT MAP ( Y => n_5775, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4700: DELAY
PORT MAP ( Y => ix484_a0_dup_614_aCLK, IN1 => n_5774);
and1_4701: AND1
PORT MAP ( Y => ix484_a0_dup_614_aENA, IN1 => n_5778);
delay_4702: DELAY
PORT MAP ( Y => n_5778, IN1 => ix484_nx45_aOUT);
dffe_4703: DFFE
PORT MAP ( D => ix484_a4_dup_602_aD, CLK => ix484_a4_dup_602_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_602_aENA, Q => ix484_a4_dup_602_Q);
xor2_4704: XOR2
PORT MAP ( Y => ix484_a4_dup_602_aD, IN1 => n_5785, IN2 => n_5788);
or1_4705: OR1
PORT MAP ( Y => n_5785, IN1 => n_5786);
and1_4706: AND1
PORT MAP ( Y => n_5786, IN1 => n_5787);
delay_4707: DELAY
PORT MAP ( Y => n_5787, IN1 => data(6));
and1_4708: AND1
PORT MAP ( Y => n_5788, IN1 => gnd);
and1_4709: AND1
PORT MAP ( Y => n_5789, IN1 => n_5790);
delay_4710: DELAY
PORT MAP ( Y => n_5790, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4711: DELAY
PORT MAP ( Y => ix484_a4_dup_602_aCLK, IN1 => n_5789);
and1_4712: AND1
PORT MAP ( Y => ix484_a4_dup_602_aENA, IN1 => n_5793);
delay_4713: DELAY
PORT MAP ( Y => n_5793, IN1 => ix484_nx41_aOUT);
dffe_4714: DFFE
PORT MAP ( D => ix484_a0_dup_606_aD, CLK => ix484_a0_dup_606_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_606_aENA, Q => ix484_a0_dup_606_Q);
xor2_4715: XOR2
PORT MAP ( Y => ix484_a0_dup_606_aD, IN1 => n_5800, IN2 => n_5803);
or1_4716: OR1
PORT MAP ( Y => n_5800, IN1 => n_5801);
and1_4717: AND1
PORT MAP ( Y => n_5801, IN1 => n_5802);
delay_4718: DELAY
PORT MAP ( Y => n_5802, IN1 => data(6));
and1_4719: AND1
PORT MAP ( Y => n_5803, IN1 => gnd);
and1_4720: AND1
PORT MAP ( Y => n_5804, IN1 => n_5805);
delay_4721: DELAY
PORT MAP ( Y => n_5805, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4722: DELAY
PORT MAP ( Y => ix484_a0_dup_606_aCLK, IN1 => n_5804);
and1_4723: AND1
PORT MAP ( Y => ix484_a0_dup_606_aENA, IN1 => n_5808);
delay_4724: DELAY
PORT MAP ( Y => n_5808, IN1 => ix484_nx45_aOUT);
dffe_4725: DFFE
PORT MAP ( D => ix484_a4_dup_594_aD, CLK => ix484_a4_dup_594_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_594_aENA, Q => ix484_a4_dup_594_Q);
xor2_4726: XOR2
PORT MAP ( Y => ix484_a4_dup_594_aD, IN1 => n_5815, IN2 => n_5818);
or1_4727: OR1
PORT MAP ( Y => n_5815, IN1 => n_5816);
and1_4728: AND1
PORT MAP ( Y => n_5816, IN1 => n_5817);
delay_4729: DELAY
PORT MAP ( Y => n_5817, IN1 => data(7));
and1_4730: AND1
PORT MAP ( Y => n_5818, IN1 => gnd);
and1_4731: AND1
PORT MAP ( Y => n_5819, IN1 => n_5820);
delay_4732: DELAY
PORT MAP ( Y => n_5820, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4733: DELAY
PORT MAP ( Y => ix484_a4_dup_594_aCLK, IN1 => n_5819);
and1_4734: AND1
PORT MAP ( Y => ix484_a4_dup_594_aENA, IN1 => n_5823);
delay_4735: DELAY
PORT MAP ( Y => n_5823, IN1 => ix484_nx41_aOUT);
dffe_4736: DFFE
PORT MAP ( D => ix484_a0_dup_598_aD, CLK => ix484_a0_dup_598_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_598_aENA, Q => ix484_a0_dup_598_Q);
xor2_4737: XOR2
PORT MAP ( Y => ix484_a0_dup_598_aD, IN1 => n_5830, IN2 => n_5833);
or1_4738: OR1
PORT MAP ( Y => n_5830, IN1 => n_5831);
and1_4739: AND1
PORT MAP ( Y => n_5831, IN1 => n_5832);
delay_4740: DELAY
PORT MAP ( Y => n_5832, IN1 => data(7));
and1_4741: AND1
PORT MAP ( Y => n_5833, IN1 => gnd);
and1_4742: AND1
PORT MAP ( Y => n_5834, IN1 => n_5835);
delay_4743: DELAY
PORT MAP ( Y => n_5835, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4744: DELAY
PORT MAP ( Y => ix484_a0_dup_598_aCLK, IN1 => n_5834);
and1_4745: AND1
PORT MAP ( Y => ix484_a0_dup_598_aENA, IN1 => n_5838);
delay_4746: DELAY
PORT MAP ( Y => n_5838, IN1 => ix484_nx45_aOUT);
dffe_4747: DFFE
PORT MAP ( D => ix484_a4_dup_586_aD, CLK => ix484_a4_dup_586_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_586_aENA, Q => ix484_a4_dup_586_Q);
xor2_4748: XOR2
PORT MAP ( Y => ix484_a4_dup_586_aD, IN1 => n_5845, IN2 => n_5848);
or1_4749: OR1
PORT MAP ( Y => n_5845, IN1 => n_5846);
and1_4750: AND1
PORT MAP ( Y => n_5846, IN1 => n_5847);
delay_4751: DELAY
PORT MAP ( Y => n_5847, IN1 => data(8));
and1_4752: AND1
PORT MAP ( Y => n_5848, IN1 => gnd);
and1_4753: AND1
PORT MAP ( Y => n_5849, IN1 => n_5850);
delay_4754: DELAY
PORT MAP ( Y => n_5850, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4755: DELAY
PORT MAP ( Y => ix484_a4_dup_586_aCLK, IN1 => n_5849);
and1_4756: AND1
PORT MAP ( Y => ix484_a4_dup_586_aENA, IN1 => n_5853);
delay_4757: DELAY
PORT MAP ( Y => n_5853, IN1 => ix484_nx41_aOUT);
dffe_4758: DFFE
PORT MAP ( D => ix484_a0_dup_590_aD, CLK => ix484_a0_dup_590_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_590_aENA, Q => ix484_a0_dup_590_Q);
xor2_4759: XOR2
PORT MAP ( Y => ix484_a0_dup_590_aD, IN1 => n_5860, IN2 => n_5863);
or1_4760: OR1
PORT MAP ( Y => n_5860, IN1 => n_5861);
and1_4761: AND1
PORT MAP ( Y => n_5861, IN1 => n_5862);
delay_4762: DELAY
PORT MAP ( Y => n_5862, IN1 => data(8));
and1_4763: AND1
PORT MAP ( Y => n_5863, IN1 => gnd);
and1_4764: AND1
PORT MAP ( Y => n_5864, IN1 => n_5865);
delay_4765: DELAY
PORT MAP ( Y => n_5865, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4766: DELAY
PORT MAP ( Y => ix484_a0_dup_590_aCLK, IN1 => n_5864);
and1_4767: AND1
PORT MAP ( Y => ix484_a0_dup_590_aENA, IN1 => n_5868);
delay_4768: DELAY
PORT MAP ( Y => n_5868, IN1 => ix484_nx45_aOUT);
dffe_4769: DFFE
PORT MAP ( D => ix484_a4_dup_578_aD, CLK => ix484_a4_dup_578_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_578_aENA, Q => ix484_a4_dup_578_Q);
xor2_4770: XOR2
PORT MAP ( Y => ix484_a4_dup_578_aD, IN1 => n_5875, IN2 => n_5878);
or1_4771: OR1
PORT MAP ( Y => n_5875, IN1 => n_5876);
and1_4772: AND1
PORT MAP ( Y => n_5876, IN1 => n_5877);
delay_4773: DELAY
PORT MAP ( Y => n_5877, IN1 => data(9));
and1_4774: AND1
PORT MAP ( Y => n_5878, IN1 => gnd);
and1_4775: AND1
PORT MAP ( Y => n_5879, IN1 => n_5880);
delay_4776: DELAY
PORT MAP ( Y => n_5880, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4777: DELAY
PORT MAP ( Y => ix484_a4_dup_578_aCLK, IN1 => n_5879);
and1_4778: AND1
PORT MAP ( Y => ix484_a4_dup_578_aENA, IN1 => n_5883);
delay_4779: DELAY
PORT MAP ( Y => n_5883, IN1 => ix484_nx41_aOUT);
dffe_4780: DFFE
PORT MAP ( D => ix484_a0_dup_582_aD, CLK => ix484_a0_dup_582_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_582_aENA, Q => ix484_a0_dup_582_Q);
xor2_4781: XOR2
PORT MAP ( Y => ix484_a0_dup_582_aD, IN1 => n_5890, IN2 => n_5893);
or1_4782: OR1
PORT MAP ( Y => n_5890, IN1 => n_5891);
and1_4783: AND1
PORT MAP ( Y => n_5891, IN1 => n_5892);
delay_4784: DELAY
PORT MAP ( Y => n_5892, IN1 => data(9));
and1_4785: AND1
PORT MAP ( Y => n_5893, IN1 => gnd);
and1_4786: AND1
PORT MAP ( Y => n_5894, IN1 => n_5895);
delay_4787: DELAY
PORT MAP ( Y => n_5895, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4788: DELAY
PORT MAP ( Y => ix484_a0_dup_582_aCLK, IN1 => n_5894);
and1_4789: AND1
PORT MAP ( Y => ix484_a0_dup_582_aENA, IN1 => n_5898);
delay_4790: DELAY
PORT MAP ( Y => n_5898, IN1 => ix484_nx45_aOUT);
dffe_4791: DFFE
PORT MAP ( D => ix484_a4_dup_570_aD, CLK => ix484_a4_dup_570_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_570_aENA, Q => ix484_a4_dup_570_Q);
xor2_4792: XOR2
PORT MAP ( Y => ix484_a4_dup_570_aD, IN1 => n_5905, IN2 => n_5908);
or1_4793: OR1
PORT MAP ( Y => n_5905, IN1 => n_5906);
and1_4794: AND1
PORT MAP ( Y => n_5906, IN1 => n_5907);
delay_4795: DELAY
PORT MAP ( Y => n_5907, IN1 => data(10));
and1_4796: AND1
PORT MAP ( Y => n_5908, IN1 => gnd);
and1_4797: AND1
PORT MAP ( Y => n_5909, IN1 => n_5910);
delay_4798: DELAY
PORT MAP ( Y => n_5910, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4799: DELAY
PORT MAP ( Y => ix484_a4_dup_570_aCLK, IN1 => n_5909);
and1_4800: AND1
PORT MAP ( Y => ix484_a4_dup_570_aENA, IN1 => n_5913);
delay_4801: DELAY
PORT MAP ( Y => n_5913, IN1 => ix484_nx41_aOUT);
dffe_4802: DFFE
PORT MAP ( D => ix484_a0_dup_574_aD, CLK => ix484_a0_dup_574_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_574_aENA, Q => ix484_a0_dup_574_Q);
xor2_4803: XOR2
PORT MAP ( Y => ix484_a0_dup_574_aD, IN1 => n_5920, IN2 => n_5923);
or1_4804: OR1
PORT MAP ( Y => n_5920, IN1 => n_5921);
and1_4805: AND1
PORT MAP ( Y => n_5921, IN1 => n_5922);
delay_4806: DELAY
PORT MAP ( Y => n_5922, IN1 => data(10));
and1_4807: AND1
PORT MAP ( Y => n_5923, IN1 => gnd);
and1_4808: AND1
PORT MAP ( Y => n_5924, IN1 => n_5925);
delay_4809: DELAY
PORT MAP ( Y => n_5925, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4810: DELAY
PORT MAP ( Y => ix484_a0_dup_574_aCLK, IN1 => n_5924);
and1_4811: AND1
PORT MAP ( Y => ix484_a0_dup_574_aENA, IN1 => n_5928);
delay_4812: DELAY
PORT MAP ( Y => n_5928, IN1 => ix484_nx45_aOUT);
dffe_4813: DFFE
PORT MAP ( D => ix484_a4_dup_562_aD, CLK => ix484_a4_dup_562_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_562_aENA, Q => ix484_a4_dup_562_Q);
xor2_4814: XOR2
PORT MAP ( Y => ix484_a4_dup_562_aD, IN1 => n_5935, IN2 => n_5938);
or1_4815: OR1
PORT MAP ( Y => n_5935, IN1 => n_5936);
and1_4816: AND1
PORT MAP ( Y => n_5936, IN1 => n_5937);
delay_4817: DELAY
PORT MAP ( Y => n_5937, IN1 => data(11));
and1_4818: AND1
PORT MAP ( Y => n_5938, IN1 => gnd);
and1_4819: AND1
PORT MAP ( Y => n_5939, IN1 => n_5940);
delay_4820: DELAY
PORT MAP ( Y => n_5940, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4821: DELAY
PORT MAP ( Y => ix484_a4_dup_562_aCLK, IN1 => n_5939);
and1_4822: AND1
PORT MAP ( Y => ix484_a4_dup_562_aENA, IN1 => n_5943);
delay_4823: DELAY
PORT MAP ( Y => n_5943, IN1 => ix484_nx41_aOUT);
dffe_4824: DFFE
PORT MAP ( D => ix484_a0_dup_566_aD, CLK => ix484_a0_dup_566_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_566_aENA, Q => ix484_a0_dup_566_Q);
xor2_4825: XOR2
PORT MAP ( Y => ix484_a0_dup_566_aD, IN1 => n_5950, IN2 => n_5953);
or1_4826: OR1
PORT MAP ( Y => n_5950, IN1 => n_5951);
and1_4827: AND1
PORT MAP ( Y => n_5951, IN1 => n_5952);
delay_4828: DELAY
PORT MAP ( Y => n_5952, IN1 => data(11));
and1_4829: AND1
PORT MAP ( Y => n_5953, IN1 => gnd);
and1_4830: AND1
PORT MAP ( Y => n_5954, IN1 => n_5955);
delay_4831: DELAY
PORT MAP ( Y => n_5955, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4832: DELAY
PORT MAP ( Y => ix484_a0_dup_566_aCLK, IN1 => n_5954);
and1_4833: AND1
PORT MAP ( Y => ix484_a0_dup_566_aENA, IN1 => n_5958);
delay_4834: DELAY
PORT MAP ( Y => n_5958, IN1 => ix484_nx45_aOUT);
dffe_4835: DFFE
PORT MAP ( D => ix484_a4_dup_554_aD, CLK => ix484_a4_dup_554_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_554_aENA, Q => ix484_a4_dup_554_Q);
xor2_4836: XOR2
PORT MAP ( Y => ix484_a4_dup_554_aD, IN1 => n_5965, IN2 => n_5968);
or1_4837: OR1
PORT MAP ( Y => n_5965, IN1 => n_5966);
and1_4838: AND1
PORT MAP ( Y => n_5966, IN1 => n_5967);
delay_4839: DELAY
PORT MAP ( Y => n_5967, IN1 => data(12));
and1_4840: AND1
PORT MAP ( Y => n_5968, IN1 => gnd);
and1_4841: AND1
PORT MAP ( Y => n_5969, IN1 => n_5970);
delay_4842: DELAY
PORT MAP ( Y => n_5970, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4843: DELAY
PORT MAP ( Y => ix484_a4_dup_554_aCLK, IN1 => n_5969);
and1_4844: AND1
PORT MAP ( Y => ix484_a4_dup_554_aENA, IN1 => n_5973);
delay_4845: DELAY
PORT MAP ( Y => n_5973, IN1 => ix484_nx41_aOUT);
dffe_4846: DFFE
PORT MAP ( D => ix484_a0_dup_558_aD, CLK => ix484_a0_dup_558_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_558_aENA, Q => ix484_a0_dup_558_Q);
xor2_4847: XOR2
PORT MAP ( Y => ix484_a0_dup_558_aD, IN1 => n_5980, IN2 => n_5983);
or1_4848: OR1
PORT MAP ( Y => n_5980, IN1 => n_5981);
and1_4849: AND1
PORT MAP ( Y => n_5981, IN1 => n_5982);
delay_4850: DELAY
PORT MAP ( Y => n_5982, IN1 => data(12));
and1_4851: AND1
PORT MAP ( Y => n_5983, IN1 => gnd);
and1_4852: AND1
PORT MAP ( Y => n_5984, IN1 => n_5985);
delay_4853: DELAY
PORT MAP ( Y => n_5985, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4854: DELAY
PORT MAP ( Y => ix484_a0_dup_558_aCLK, IN1 => n_5984);
and1_4855: AND1
PORT MAP ( Y => ix484_a0_dup_558_aENA, IN1 => n_5988);
delay_4856: DELAY
PORT MAP ( Y => n_5988, IN1 => ix484_nx45_aOUT);
dffe_4857: DFFE
PORT MAP ( D => ix484_a4_dup_546_aD, CLK => ix484_a4_dup_546_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_546_aENA, Q => ix484_a4_dup_546_Q);
xor2_4858: XOR2
PORT MAP ( Y => ix484_a4_dup_546_aD, IN1 => n_5995, IN2 => n_5998);
or1_4859: OR1
PORT MAP ( Y => n_5995, IN1 => n_5996);
and1_4860: AND1
PORT MAP ( Y => n_5996, IN1 => n_5997);
delay_4861: DELAY
PORT MAP ( Y => n_5997, IN1 => data(13));
and1_4862: AND1
PORT MAP ( Y => n_5998, IN1 => gnd);
and1_4863: AND1
PORT MAP ( Y => n_5999, IN1 => n_6000);
delay_4864: DELAY
PORT MAP ( Y => n_6000, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4865: DELAY
PORT MAP ( Y => ix484_a4_dup_546_aCLK, IN1 => n_5999);
and1_4866: AND1
PORT MAP ( Y => ix484_a4_dup_546_aENA, IN1 => n_6003);
delay_4867: DELAY
PORT MAP ( Y => n_6003, IN1 => ix484_nx41_aOUT);
dffe_4868: DFFE
PORT MAP ( D => ix484_a0_dup_550_aD, CLK => ix484_a0_dup_550_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_550_aENA, Q => ix484_a0_dup_550_Q);
xor2_4869: XOR2
PORT MAP ( Y => ix484_a0_dup_550_aD, IN1 => n_6010, IN2 => n_6013);
or1_4870: OR1
PORT MAP ( Y => n_6010, IN1 => n_6011);
and1_4871: AND1
PORT MAP ( Y => n_6011, IN1 => n_6012);
delay_4872: DELAY
PORT MAP ( Y => n_6012, IN1 => data(13));
and1_4873: AND1
PORT MAP ( Y => n_6013, IN1 => gnd);
and1_4874: AND1
PORT MAP ( Y => n_6014, IN1 => n_6015);
delay_4875: DELAY
PORT MAP ( Y => n_6015, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4876: DELAY
PORT MAP ( Y => ix484_a0_dup_550_aCLK, IN1 => n_6014);
and1_4877: AND1
PORT MAP ( Y => ix484_a0_dup_550_aENA, IN1 => n_6018);
delay_4878: DELAY
PORT MAP ( Y => n_6018, IN1 => ix484_nx45_aOUT);
dffe_4879: DFFE
PORT MAP ( D => ix484_a4_dup_538_aD, CLK => ix484_a4_dup_538_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a4_dup_538_aENA, Q => ix484_a4_dup_538_Q);
xor2_4880: XOR2
PORT MAP ( Y => ix484_a4_dup_538_aD, IN1 => n_6025, IN2 => n_6028);
or1_4881: OR1
PORT MAP ( Y => n_6025, IN1 => n_6026);
and1_4882: AND1
PORT MAP ( Y => n_6026, IN1 => n_6027);
delay_4883: DELAY
PORT MAP ( Y => n_6027, IN1 => data(14));
and1_4884: AND1
PORT MAP ( Y => n_6028, IN1 => gnd);
and1_4885: AND1
PORT MAP ( Y => n_6029, IN1 => n_6030);
delay_4886: DELAY
PORT MAP ( Y => n_6030, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4887: DELAY
PORT MAP ( Y => ix484_a4_dup_538_aCLK, IN1 => n_6029);
and1_4888: AND1
PORT MAP ( Y => ix484_a4_dup_538_aENA, IN1 => n_6033);
delay_4889: DELAY
PORT MAP ( Y => n_6033, IN1 => ix484_nx41_aOUT);
dffe_4890: DFFE
PORT MAP ( D => ix484_a0_dup_542_aD, CLK => ix484_a0_dup_542_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_542_aENA, Q => ix484_a0_dup_542_Q);
xor2_4891: XOR2
PORT MAP ( Y => ix484_a0_dup_542_aD, IN1 => n_6040, IN2 => n_6043);
or1_4892: OR1
PORT MAP ( Y => n_6040, IN1 => n_6041);
and1_4893: AND1
PORT MAP ( Y => n_6041, IN1 => n_6042);
delay_4894: DELAY
PORT MAP ( Y => n_6042, IN1 => data(14));
and1_4895: AND1
PORT MAP ( Y => n_6043, IN1 => gnd);
and1_4896: AND1
PORT MAP ( Y => n_6044, IN1 => n_6045);
delay_4897: DELAY
PORT MAP ( Y => n_6045, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4898: DELAY
PORT MAP ( Y => ix484_a0_dup_542_aCLK, IN1 => n_6044);
and1_4899: AND1
PORT MAP ( Y => ix484_a0_dup_542_aENA, IN1 => n_6048);
delay_4900: DELAY
PORT MAP ( Y => n_6048, IN1 => ix484_nx45_aOUT);
dffe_4901: DFFE
PORT MAP ( D => ix484_a4_aD, CLK => ix484_a4_aCLK, CLRN => vcc, PRN => vcc,
ENA => ix484_a4_aENA, Q => ix484_a4_Q);
xor2_4902: XOR2
PORT MAP ( Y => ix484_a4_aD, IN1 => n_6055, IN2 => n_6058);
or1_4903: OR1
PORT MAP ( Y => n_6055, IN1 => n_6056);
and1_4904: AND1
PORT MAP ( Y => n_6056, IN1 => n_6057);
delay_4905: DELAY
PORT MAP ( Y => n_6057, IN1 => data(15));
and1_4906: AND1
PORT MAP ( Y => n_6058, IN1 => gnd);
and1_4907: AND1
PORT MAP ( Y => n_6059, IN1 => n_6060);
delay_4908: DELAY
PORT MAP ( Y => n_6060, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4909: DELAY
PORT MAP ( Y => ix484_a4_aCLK, IN1 => n_6059);
and1_4910: AND1
PORT MAP ( Y => ix484_a4_aENA, IN1 => n_6063);
delay_4911: DELAY
PORT MAP ( Y => n_6063, IN1 => ix484_nx41_aOUT);
dffe_4912: DFFE
PORT MAP ( D => ix484_a0_dup_534_aD, CLK => ix484_a0_dup_534_aCLK, CLRN => vcc,
PRN => vcc, ENA => ix484_a0_dup_534_aENA, Q => ix484_a0_dup_534_Q);
xor2_4913: XOR2
PORT MAP ( Y => ix484_a0_dup_534_aD, IN1 => n_6070, IN2 => n_6073);
or1_4914: OR1
PORT MAP ( Y => n_6070, IN1 => n_6071);
and1_4915: AND1
PORT MAP ( Y => n_6071, IN1 => n_6072);
delay_4916: DELAY
PORT MAP ( Y => n_6072, IN1 => data(15));
and1_4917: AND1
PORT MAP ( Y => n_6073, IN1 => gnd);
and1_4918: AND1
PORT MAP ( Y => n_6074, IN1 => n_6075);
delay_4919: DELAY
PORT MAP ( Y => n_6075, IN1 => a_as_or3_aix1635_a_a32_aOUT);
delay_4920: DELAY
PORT MAP ( Y => ix484_a0_dup_534_aCLK, IN1 => n_6074);
and1_4921: AND1
PORT MAP ( Y => ix484_a0_dup_534_aENA, IN1 => n_6078);
delay_4922: DELAY
PORT MAP ( Y => n_6078, IN1 => ix484_nx45_aOUT);
dff_4923: DFF
PORT MAP ( D => con1_current_state13_aD, CLK => con1_current_state13_aCLK,
CLRN => con1_current_state13_aCLRN, PRN => vcc, Q => con1_current_state13_Q);
inv_4924: INV
PORT MAP ( Y => con1_current_state13_aCLRN, IN1 => reset);
xor2_4925: XOR2
PORT MAP ( Y => con1_current_state13_aD, IN1 => n_6085, IN2 => n_6088);
or1_4926: OR1
PORT MAP ( Y => n_6085, IN1 => n_6086);
and1_4927: AND1
PORT MAP ( Y => n_6086, IN1 => n_6087);
delay_4928: DELAY
PORT MAP ( Y => n_6087, IN1 => con1_current_state12_Q);
and1_4929: AND1
PORT MAP ( Y => n_6088, IN1 => gnd);
delay_4930: DELAY
PORT MAP ( Y => con1_current_state13_aCLK, IN1 => clock);
dff_4931: DFF
PORT MAP ( D => con1_current_state24_aD, CLK => con1_current_state24_aCLK,
CLRN => con1_current_state24_aCLRN, PRN => vcc, Q => con1_current_state24_Q);
inv_4932: INV
PORT MAP ( Y => con1_current_state24_aCLRN, IN1 => reset);
xor2_4933: XOR2
PORT MAP ( Y => con1_current_state24_aD, IN1 => n_6096, IN2 => n_6099);
or1_4934: OR1
PORT MAP ( Y => n_6096, IN1 => n_6097);
and1_4935: AND1
PORT MAP ( Y => n_6097, IN1 => n_6098);
delay_4936: DELAY
PORT MAP ( Y => n_6098, IN1 => con1_current_state23_Q);
and1_4937: AND1
PORT MAP ( Y => n_6099, IN1 => gnd);
delay_4938: DELAY
PORT MAP ( Y => con1_current_state24_aCLK, IN1 => clock);
dff_4939: DFF
PORT MAP ( D => con1_current_state12_aD, CLK => con1_current_state12_aCLK,
CLRN => con1_current_state12_aCLRN, PRN => vcc, Q => con1_current_state12_Q);
inv_4940: INV
PORT MAP ( Y => con1_current_state12_aCLRN, IN1 => reset);
xor2_4941: XOR2
PORT MAP ( Y => con1_current_state12_aD, IN1 => n_6107, IN2 => n_6110);
or1_4942: OR1
PORT MAP ( Y => n_6107, IN1 => n_6108);
and1_4943: AND1
PORT MAP ( Y => n_6108, IN1 => n_6109);
delay_4944: DELAY
PORT MAP ( Y => n_6109, IN1 => con1_current_state11_Q);
and1_4945: AND1
PORT MAP ( Y => n_6110, IN1 => gnd);
delay_4946: DELAY
PORT MAP ( Y => con1_current_state12_aCLK, IN1 => clock);
dff_4947: DFF
PORT MAP ( D => con1_current_state5_aD, CLK => con1_current_state5_aCLK,
CLRN => con1_current_state5_aCLRN, PRN => vcc, Q => con1_current_state5_Q);
inv_4948: INV
PORT MAP ( Y => con1_current_state5_aCLRN, IN1 => reset);
xor2_4949: XOR2
PORT MAP ( Y => con1_current_state5_aD, IN1 => n_6118, IN2 => n_6124);
or2_4950: OR2
PORT MAP ( Y => n_6118, IN1 => n_6119, IN2 => n_6121);
and1_4951: AND1
PORT MAP ( Y => n_6119, IN1 => n_6120);
delay_4952: DELAY
PORT MAP ( Y => n_6120, IN1 => con1_current_state4_Q);
and2_4953: AND2
PORT MAP ( Y => n_6121, IN1 => n_6122, IN2 => n_6123);
inv_4954: INV
PORT MAP ( Y => n_6122, IN1 => ready);
delay_4955: DELAY
PORT MAP ( Y => n_6123, IN1 => con1_current_state5_Q);
and1_4956: AND1
PORT MAP ( Y => n_6124, IN1 => gnd);
delay_4957: DELAY
PORT MAP ( Y => con1_current_state5_aCLK, IN1 => clock);
dff_4958: DFF
PORT MAP ( D => con1_current_state2_aD, CLK => con1_current_state2_aCLK,
CLRN => con1_current_state2_aCLRN, PRN => vcc, Q => con1_current_state2_Q);
inv_4959: INV
PORT MAP ( Y => con1_current_state2_aCLRN, IN1 => reset);
xor2_4960: XOR2
PORT MAP ( Y => con1_current_state2_aD, IN1 => n_6132, IN2 => n_6135);
or1_4961: OR1
PORT MAP ( Y => n_6132, IN1 => n_6133);
and1_4962: AND1
PORT MAP ( Y => n_6133, IN1 => n_6134);
delay_4963: DELAY
PORT MAP ( Y => n_6134, IN1 => con1_current_state1_Q);
and1_4964: AND1
PORT MAP ( Y => n_6135, IN1 => gnd);
delay_4965: DELAY
PORT MAP ( Y => con1_current_state2_aCLK, IN1 => clock);
dff_4966: DFF
PORT MAP ( D => con1_current_state29_aD, CLK => con1_current_state29_aCLK,
CLRN => con1_current_state29_aCLRN, PRN => vcc, Q => con1_current_state29_Q);
inv_4967: INV
PORT MAP ( Y => con1_current_state29_aCLRN, IN1 => reset);
xor2_4968: XOR2
PORT MAP ( Y => con1_current_state29_aD, IN1 => n_6143, IN2 => n_6149);
or2_4969: OR2
PORT MAP ( Y => n_6143, IN1 => n_6144, IN2 => n_6146);
and1_4970: AND1
PORT MAP ( Y => n_6144, IN1 => n_6145);
delay_4971: DELAY
PORT MAP ( Y => n_6145, IN1 => con1_current_state28_Q);
and2_4972: AND2
PORT MAP ( Y => n_6146, IN1 => n_6147, IN2 => n_6148);
inv_4973: INV
PORT MAP ( Y => n_6147, IN1 => ready);
delay_4974: DELAY
PORT MAP ( Y => n_6148, IN1 => con1_current_state29_Q);
and1_4975: AND1
PORT MAP ( Y => n_6149, IN1 => gnd);
delay_4976: DELAY
PORT MAP ( Y => con1_current_state29_aCLK, IN1 => clock);
dff_4977: DFF
PORT MAP ( D => con1_current_state43_aD, CLK => con1_current_state43_aCLK,
CLRN => con1_current_state43_aCLRN, PRN => vcc, Q => con1_current_state43_Q);
inv_4978: INV
PORT MAP ( Y => con1_current_state43_aCLRN, IN1 => reset);
xor2_4979: XOR2
PORT MAP ( Y => con1_current_state43_aD, IN1 => n_6157, IN2 => n_6163);
or2_4980: OR2
PORT MAP ( Y => n_6157, IN1 => n_6158, IN2 => n_6160);
and1_4981: AND1
PORT MAP ( Y => n_6158, IN1 => n_6159);
delay_4982: DELAY
PORT MAP ( Y => n_6159, IN1 => con1_current_state42_Q);
and2_4983: AND2
PORT MAP ( Y => n_6160, IN1 => n_6161, IN2 => n_6162);
inv_4984: INV
PORT MAP ( Y => n_6161, IN1 => ready);
delay_4985: DELAY
PORT MAP ( Y => n_6162, IN1 => con1_current_state43_Q);
and1_4986: AND1
PORT MAP ( Y => n_6163, IN1 => gnd);
delay_4987: DELAY
PORT MAP ( Y => con1_current_state43_aCLK, IN1 => clock);
dff_4988: DFF
PORT MAP ( D => con1_current_state38_aD, CLK => con1_current_state38_aCLK,
CLRN => con1_current_state38_aCLRN, PRN => vcc, Q => con1_current_state38_Q);
inv_4989: INV
PORT MAP ( Y => con1_current_state38_aCLRN, IN1 => reset);
xor2_4990: XOR2
PORT MAP ( Y => con1_current_state38_aD, IN1 => n_6171, IN2 => n_6177);
or2_4991: OR2
PORT MAP ( Y => n_6171, IN1 => n_6172, IN2 => n_6174);
and1_4992: AND1
PORT MAP ( Y => n_6172, IN1 => n_6173);
delay_4993: DELAY
PORT MAP ( Y => n_6173, IN1 => con1_current_state37_Q);
and2_4994: AND2
PORT MAP ( Y => n_6174, IN1 => n_6175, IN2 => n_6176);
inv_4995: INV
PORT MAP ( Y => n_6175, IN1 => ready);
delay_4996: DELAY
PORT MAP ( Y => n_6176, IN1 => con1_current_state38_Q);
and1_4997: AND1
PORT MAP ( Y => n_6177, IN1 => gnd);
delay_4998: DELAY
PORT MAP ( Y => con1_current_state38_aCLK, IN1 => clock);
dff_4999: DFF
PORT MAP ( D => con1_current_state25_aD, CLK => con1_current_state25_aCLK,
CLRN => con1_current_state25_aCLRN, PRN => vcc, Q => con1_current_state25_Q);
inv_5000: INV
PORT MAP ( Y => con1_current_state25_aCLRN, IN1 => reset);
xor2_5001: XOR2
PORT MAP ( Y => con1_current_state25_aD, IN1 => n_6185, IN2 => n_6191);
or2_5002: OR2
PORT MAP ( Y => n_6185, IN1 => n_6186, IN2 => n_6188);
and1_5003: AND1
PORT MAP ( Y => n_6186, IN1 => n_6187);
delay_5004: DELAY
PORT MAP ( Y => n_6187, IN1 => con1_current_state24_Q);
and2_5005: AND2
PORT MAP ( Y => n_6188, IN1 => n_6189, IN2 => n_6190);
inv_5006: INV
PORT MAP ( Y => n_6189, IN1 => ready);
delay_5007: DELAY
PORT MAP ( Y => n_6190, IN1 => con1_current_state25_Q);
and1_5008: AND1
PORT MAP ( Y => n_6191, IN1 => gnd);
delay_5009: DELAY
PORT MAP ( Y => con1_current_state25_aCLK, IN1 => clock);
dff_5010: DFF
PORT MAP ( D => con1_current_state26_aD, CLK => con1_current_state26_aCLK,
CLRN => con1_current_state26_aCLRN, PRN => vcc, Q => con1_current_state26_Q);
inv_5011: INV
PORT MAP ( Y => con1_current_state26_aCLRN, IN1 => reset);
xor2_5012: XOR2
PORT MAP ( Y => con1_current_state26_aD, IN1 => n_6199, IN2 => n_6206);
or2_5013: OR2
PORT MAP ( Y => n_6199, IN1 => n_6200, IN2 => n_6203);
and2_5014: AND2
PORT MAP ( Y => n_6200, IN1 => n_6201, IN2 => n_6202);
delay_5015: DELAY
PORT MAP ( Y => n_6201, IN1 => ready);
delay_5016: DELAY
PORT MAP ( Y => n_6202, IN1 => con1_current_state38_Q);
and2_5017: AND2
PORT MAP ( Y => n_6203, IN1 => n_6204, IN2 => n_6205);
delay_5018: DELAY
PORT MAP ( Y => n_6204, IN1 => ready);
delay_5019: DELAY
PORT MAP ( Y => n_6205, IN1 => con1_current_state43_Q);
and1_5020: AND1
PORT MAP ( Y => n_6206, IN1 => gnd);
delay_5021: DELAY
PORT MAP ( Y => con1_current_state26_aCLK, IN1 => clock);
dff_5022: DFF
PORT MAP ( D => con1_current_state22_aD, CLK => con1_current_state22_aCLK,
CLRN => con1_current_state22_aCLRN, PRN => vcc, Q => con1_current_state22_Q);
inv_5023: INV
PORT MAP ( Y => con1_current_state22_aCLRN, IN1 => reset);
xor2_5024: XOR2
PORT MAP ( Y => con1_current_state22_aD, IN1 => n_6214, IN2 => n_6217);
or1_5025: OR1
PORT MAP ( Y => n_6214, IN1 => n_6215);
and1_5026: AND1
PORT MAP ( Y => n_6215, IN1 => n_6216);
delay_5027: DELAY
PORT MAP ( Y => n_6216, IN1 => con1_current_state21_Q);
and1_5028: AND1
PORT MAP ( Y => n_6217, IN1 => gnd);
delay_5029: DELAY
PORT MAP ( Y => con1_current_state22_aCLK, IN1 => clock);
dff_5030: DFF
PORT MAP ( D => con1_current_state3_aD, CLK => con1_current_state3_aCLK,
CLRN => con1_current_state3_aCLRN, PRN => vcc, Q => con1_current_state3_Q);
inv_5031: INV
PORT MAP ( Y => con1_current_state3_aCLRN, IN1 => reset);
xor2_5032: XOR2
PORT MAP ( Y => con1_current_state3_aD, IN1 => n_6226, IN2 => n_6229);
or1_5033: OR1
PORT MAP ( Y => n_6226, IN1 => n_6227);
and1_5034: AND1
PORT MAP ( Y => n_6227, IN1 => n_6228);
delay_5035: DELAY
PORT MAP ( Y => n_6228, IN1 => con1_current_state2_Q);
and1_5036: AND1
PORT MAP ( Y => n_6229, IN1 => gnd);
delay_5037: DELAY
PORT MAP ( Y => con1_current_state3_aCLK, IN1 => clock);
dff_5038: DFF
PORT MAP ( D => con1_current_state14_aD, CLK => con1_current_state14_aCLK,
CLRN => con1_current_state14_aCLRN, PRN => vcc, Q => con1_current_state14_Q);
inv_5039: INV
PORT MAP ( Y => con1_current_state14_aCLRN, IN1 => reset);
xor2_5040: XOR2
PORT MAP ( Y => con1_current_state14_aD, IN1 => n_6237, IN2 => n_6242);
or1_5041: OR1
PORT MAP ( Y => n_6237, IN1 => n_6238);
and2_5042: AND2
PORT MAP ( Y => n_6238, IN1 => n_6239, IN2 => n_6241);
inv_5043: INV
PORT MAP ( Y => n_6239, IN1 => con1_modgen_62_nx16_aOUT);
delay_5044: DELAY
PORT MAP ( Y => n_6241, IN1 => con1_current_state6_Q);
and1_5045: AND1
PORT MAP ( Y => n_6242, IN1 => gnd);
delay_5046: DELAY
PORT MAP ( Y => con1_current_state14_aCLK, IN1 => clock);
dff_5047: DFF
PORT MAP ( D => con1_current_state27_aD, CLK => con1_current_state27_aCLK,
CLRN => con1_current_state27_aCLRN, PRN => vcc, Q => con1_current_state27_Q);
inv_5048: INV
PORT MAP ( Y => con1_current_state27_aCLRN, IN1 => reset);
xor2_5049: XOR2
PORT MAP ( Y => con1_current_state27_aD, IN1 => n_6250, IN2 => n_6253);
or1_5050: OR1
PORT MAP ( Y => n_6250, IN1 => n_6251);
and1_5051: AND1
PORT MAP ( Y => n_6251, IN1 => n_6252);
delay_5052: DELAY
PORT MAP ( Y => n_6252, IN1 => con1_current_state26_Q);
and1_5053: AND1
PORT MAP ( Y => n_6253, IN1 => gnd);
delay_5054: DELAY
PORT MAP ( Y => con1_current_state27_aCLK, IN1 => clock);
dff_5055: DFF
PORT MAP ( D => con1_current_state23_aD, CLK => con1_current_state23_aCLK,
CLRN => con1_current_state23_aCLRN, PRN => vcc, Q => con1_current_state23_Q);
inv_5056: INV
PORT MAP ( Y => con1_current_state23_aCLRN, IN1 => reset);
xor2_5057: XOR2
PORT MAP ( Y => con1_current_state23_aD, IN1 => n_6261, IN2 => n_6264);
or1_5058: OR1
PORT MAP ( Y => n_6261, IN1 => n_6262);
and1_5059: AND1
PORT MAP ( Y => n_6262, IN1 => n_6263);
delay_5060: DELAY
PORT MAP ( Y => n_6263, IN1 => con1_current_state22_Q);
and1_5061: AND1
PORT MAP ( Y => n_6264, IN1 => gnd);
delay_5062: DELAY
PORT MAP ( Y => con1_current_state23_aCLK, IN1 => clock);
dff_5063: DFF
PORT MAP ( D => con1_current_state48_aD, CLK => con1_current_state48_aCLK,
CLRN => con1_current_state48_aCLRN, PRN => vcc, Q => con1_current_state48_Q);
inv_5064: INV
PORT MAP ( Y => con1_current_state48_aCLRN, IN1 => reset);
xor2_5065: XOR2
PORT MAP ( Y => con1_current_state48_aD, IN1 => n_6272, IN2 => n_6278);
or2_5066: OR2
PORT MAP ( Y => n_6272, IN1 => n_6273, IN2 => n_6276);
and2_5067: AND2
PORT MAP ( Y => n_6273, IN1 => n_6274, IN2 => n_6275);
inv_5068: INV
PORT MAP ( Y => n_6274, IN1 => ready);
delay_5069: DELAY
PORT MAP ( Y => n_6275, IN1 => con1_current_state48_Q);
and1_5070: AND1
PORT MAP ( Y => n_6276, IN1 => n_6277);
delay_5071: DELAY
PORT MAP ( Y => n_6277, IN1 => con1_current_state47_Q);
and1_5072: AND1
PORT MAP ( Y => n_6278, IN1 => gnd);
delay_5073: DELAY
PORT MAP ( Y => con1_current_state48_aCLK, IN1 => clock);
dff_5074: DFF
PORT MAP ( D => con1_current_state4_aD, CLK => con1_current_state4_aCLK,
CLRN => con1_current_state4_aCLRN, PRN => vcc, Q => con1_current_state4_Q);
inv_5075: INV
PORT MAP ( Y => con1_current_state4_aCLRN, IN1 => reset);
xor2_5076: XOR2
PORT MAP ( Y => con1_current_state4_aD, IN1 => n_6286, IN2 => n_6289);
or1_5077: OR1
PORT MAP ( Y => n_6286, IN1 => n_6287);
and1_5078: AND1
PORT MAP ( Y => n_6287, IN1 => n_6288);
delay_5079: DELAY
PORT MAP ( Y => n_6288, IN1 => con1_current_state3_Q);
and1_5080: AND1
PORT MAP ( Y => n_6289, IN1 => gnd);
delay_5081: DELAY
PORT MAP ( Y => con1_current_state4_aCLK, IN1 => clock);
dff_5082: DFF
PORT MAP ( D => con1_current_state15_aD, CLK => con1_current_state15_aCLK,
CLRN => con1_current_state15_aCLRN, PRN => vcc, Q => con1_current_state15_Q);
inv_5083: INV
PORT MAP ( Y => con1_current_state15_aCLRN, IN1 => reset);
xor2_5084: XOR2
PORT MAP ( Y => con1_current_state15_aD, IN1 => n_6297, IN2 => n_6300);
or1_5085: OR1
PORT MAP ( Y => n_6297, IN1 => n_6298);
and1_5086: AND1
PORT MAP ( Y => n_6298, IN1 => n_6299);
delay_5087: DELAY
PORT MAP ( Y => n_6299, IN1 => con1_current_state14_Q);
and1_5088: AND1
PORT MAP ( Y => n_6300, IN1 => gnd);
delay_5089: DELAY
PORT MAP ( Y => con1_current_state15_aCLK, IN1 => clock);
dff_5090: DFF
PORT MAP ( D => rw_dup0_aD, CLK => rw_dup0_aCLK, CLRN => rw_dup0_aCLRN,
PRN => vcc, Q => rw_dup0_Q);
inv_5091: INV
PORT MAP ( Y => rw_dup0_aCLRN, IN1 => reset);
xor2_5092: XOR2
PORT MAP ( Y => rw_dup0_aD, IN1 => n_6308, IN2 => n_6311);
or1_5093: OR1
PORT MAP ( Y => n_6308, IN1 => n_6309);
and1_5094: AND1
PORT MAP ( Y => n_6309, IN1 => n_6310);
delay_5095: DELAY
PORT MAP ( Y => n_6310, IN1 => con1_current_state15_Q);
and1_5096: AND1
PORT MAP ( Y => n_6311, IN1 => gnd);
delay_5097: DELAY
PORT MAP ( Y => rw_dup0_aCLK, IN1 => clock);
delay_5098: DELAY
PORT MAP ( Y => O_dup_1039_aOUT, IN1 => O_dup_1039_aIN);
xor2_5099: XOR2
PORT MAP ( Y => O_dup_1039_aIN, IN1 => n_6315, IN2 => n_6321);
or1_5100: OR1
PORT MAP ( Y => n_6315, IN1 => n_6316);
and4_5101: AND4
PORT MAP ( Y => n_6316, IN1 => n_6317, IN2 => n_6318, IN3 => n_6319, IN4 => n_6320);
inv_5102: INV
PORT MAP ( Y => n_6317, IN1 => con1_current_state47_Q);
inv_5103: INV
PORT MAP ( Y => n_6318, IN1 => con1_current_state28_Q);
inv_5104: INV
PORT MAP ( Y => n_6319, IN1 => con1_current_state42_Q);
inv_5105: INV
PORT MAP ( Y => n_6320, IN1 => con1_current_state37_Q);
and1_5106: AND1
PORT MAP ( Y => n_6321, IN1 => gnd);
delay_5107: DELAY
PORT MAP ( Y => I0_dup_774_aOUT, IN1 => I0_dup_774_aIN);
and2_5108: AND2
PORT MAP ( Y => I0_dup_774_aIN, IN1 => n_6324, IN2 => n_6330);
or1_5109: OR1
PORT MAP ( Y => n_6324, IN1 => n_6325);
and4_5110: AND4
PORT MAP ( Y => n_6325, IN1 => n_6326, IN2 => n_6327, IN3 => n_6328, IN4 => n_6329);
inv_5111: INV
PORT MAP ( Y => n_6326, IN1 => con1_current_state5_Q);
inv_5112: INV
PORT MAP ( Y => n_6327, IN1 => con1_current_state12_Q);
inv_5113: INV
PORT MAP ( Y => n_6328, IN1 => con1_current_state24_Q);
inv_5114: INV
PORT MAP ( Y => n_6329, IN1 => con1_current_state13_Q);
delay_5115: DELAY
PORT MAP ( Y => n_6330, IN1 => O_dup_1039_aIN);
delay_5116: DELAY
PORT MAP ( Y => O_aOUT, IN1 => O_aIN1);
and2_5117: AND2
PORT MAP ( Y => O_aIN1, IN1 => n_6332, IN2 => n_6338);
or1_5118: OR1
PORT MAP ( Y => n_6332, IN1 => n_6333);
and4_5119: AND4
PORT MAP ( Y => n_6333, IN1 => n_6334, IN2 => n_6335, IN3 => n_6336, IN4 => n_6337);
inv_5120: INV
PORT MAP ( Y => n_6334, IN1 => rw_dup0_Q);
inv_5121: INV
PORT MAP ( Y => n_6335, IN1 => con1_current_state4_Q);
inv_5122: INV
PORT MAP ( Y => n_6336, IN1 => con1_current_state48_Q);
delay_5123: DELAY
PORT MAP ( Y => n_6337, IN1 => I3_dup_1028_aOUT);
delay_5124: DELAY
PORT MAP ( Y => n_6338, IN1 => I0_dup_774_aIN);
dff_5125: DFF
PORT MAP ( D => addr_dup00_aD, CLK => addr_dup00_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup00_Q);
xor2_5126: XOR2
PORT MAP ( Y => addr_dup00_aD, IN1 => n_6344, IN2 => n_6347);
or1_5127: OR1
PORT MAP ( Y => n_6344, IN1 => n_6345);
and1_5128: AND1
PORT MAP ( Y => n_6345, IN1 => n_6346);
delay_5129: DELAY
PORT MAP ( Y => n_6346, IN1 => data(0));
and1_5130: AND1
PORT MAP ( Y => n_6347, IN1 => gnd);
and1_5131: AND1
PORT MAP ( Y => n_6348, IN1 => n_6349);
inv_5132: INV
PORT MAP ( Y => n_6349, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5133: DELAY
PORT MAP ( Y => addr_dup00_aCLK, IN1 => n_6348);
dff_5134: DFF
PORT MAP ( D => addr_dup01_aD, CLK => addr_dup01_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup01_Q);
xor2_5135: XOR2
PORT MAP ( Y => addr_dup01_aD, IN1 => n_6356, IN2 => n_6359);
or1_5136: OR1
PORT MAP ( Y => n_6356, IN1 => n_6357);
and1_5137: AND1
PORT MAP ( Y => n_6357, IN1 => n_6358);
delay_5138: DELAY
PORT MAP ( Y => n_6358, IN1 => data(1));
and1_5139: AND1
PORT MAP ( Y => n_6359, IN1 => gnd);
and1_5140: AND1
PORT MAP ( Y => n_6360, IN1 => n_6361);
inv_5141: INV
PORT MAP ( Y => n_6361, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5142: DELAY
PORT MAP ( Y => addr_dup01_aCLK, IN1 => n_6360);
dff_5143: DFF
PORT MAP ( D => addr_dup02_aD, CLK => addr_dup02_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup02_Q);
xor2_5144: XOR2
PORT MAP ( Y => addr_dup02_aD, IN1 => n_6368, IN2 => n_6371);
or1_5145: OR1
PORT MAP ( Y => n_6368, IN1 => n_6369);
and1_5146: AND1
PORT MAP ( Y => n_6369, IN1 => n_6370);
delay_5147: DELAY
PORT MAP ( Y => n_6370, IN1 => data(2));
and1_5148: AND1
PORT MAP ( Y => n_6371, IN1 => gnd);
and1_5149: AND1
PORT MAP ( Y => n_6372, IN1 => n_6373);
inv_5150: INV
PORT MAP ( Y => n_6373, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5151: DELAY
PORT MAP ( Y => addr_dup02_aCLK, IN1 => n_6372);
dff_5152: DFF
PORT MAP ( D => addr_dup03_aD, CLK => addr_dup03_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup03_Q);
xor2_5153: XOR2
PORT MAP ( Y => addr_dup03_aD, IN1 => n_6380, IN2 => n_6383);
or1_5154: OR1
PORT MAP ( Y => n_6380, IN1 => n_6381);
and1_5155: AND1
PORT MAP ( Y => n_6381, IN1 => n_6382);
delay_5156: DELAY
PORT MAP ( Y => n_6382, IN1 => data(3));
and1_5157: AND1
PORT MAP ( Y => n_6383, IN1 => gnd);
and1_5158: AND1
PORT MAP ( Y => n_6384, IN1 => n_6385);
inv_5159: INV
PORT MAP ( Y => n_6385, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5160: DELAY
PORT MAP ( Y => addr_dup03_aCLK, IN1 => n_6384);
dff_5161: DFF
PORT MAP ( D => addr_dup04_aD, CLK => addr_dup04_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup04_Q);
xor2_5162: XOR2
PORT MAP ( Y => addr_dup04_aD, IN1 => n_6392, IN2 => n_6395);
or1_5163: OR1
PORT MAP ( Y => n_6392, IN1 => n_6393);
and1_5164: AND1
PORT MAP ( Y => n_6393, IN1 => n_6394);
delay_5165: DELAY
PORT MAP ( Y => n_6394, IN1 => data(4));
and1_5166: AND1
PORT MAP ( Y => n_6395, IN1 => gnd);
and1_5167: AND1
PORT MAP ( Y => n_6396, IN1 => n_6397);
inv_5168: INV
PORT MAP ( Y => n_6397, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5169: DELAY
PORT MAP ( Y => addr_dup04_aCLK, IN1 => n_6396);
dff_5170: DFF
PORT MAP ( D => addr_dup05_aD, CLK => addr_dup05_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup05_Q);
xor2_5171: XOR2
PORT MAP ( Y => addr_dup05_aD, IN1 => n_6404, IN2 => n_6407);
or1_5172: OR1
PORT MAP ( Y => n_6404, IN1 => n_6405);
and1_5173: AND1
PORT MAP ( Y => n_6405, IN1 => n_6406);
delay_5174: DELAY
PORT MAP ( Y => n_6406, IN1 => data(5));
and1_5175: AND1
PORT MAP ( Y => n_6407, IN1 => gnd);
and1_5176: AND1
PORT MAP ( Y => n_6408, IN1 => n_6409);
inv_5177: INV
PORT MAP ( Y => n_6409, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5178: DELAY
PORT MAP ( Y => addr_dup05_aCLK, IN1 => n_6408);
dff_5179: DFF
PORT MAP ( D => addr_dup06_aD, CLK => addr_dup06_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup06_Q);
xor2_5180: XOR2
PORT MAP ( Y => addr_dup06_aD, IN1 => n_6416, IN2 => n_6419);
or1_5181: OR1
PORT MAP ( Y => n_6416, IN1 => n_6417);
and1_5182: AND1
PORT MAP ( Y => n_6417, IN1 => n_6418);
delay_5183: DELAY
PORT MAP ( Y => n_6418, IN1 => data(6));
and1_5184: AND1
PORT MAP ( Y => n_6419, IN1 => gnd);
and1_5185: AND1
PORT MAP ( Y => n_6420, IN1 => n_6421);
inv_5186: INV
PORT MAP ( Y => n_6421, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5187: DELAY
PORT MAP ( Y => addr_dup06_aCLK, IN1 => n_6420);
dff_5188: DFF
PORT MAP ( D => addr_dup07_aD, CLK => addr_dup07_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup07_Q);
xor2_5189: XOR2
PORT MAP ( Y => addr_dup07_aD, IN1 => n_6428, IN2 => n_6431);
or1_5190: OR1
PORT MAP ( Y => n_6428, IN1 => n_6429);
and1_5191: AND1
PORT MAP ( Y => n_6429, IN1 => n_6430);
delay_5192: DELAY
PORT MAP ( Y => n_6430, IN1 => data(7));
and1_5193: AND1
PORT MAP ( Y => n_6431, IN1 => gnd);
and1_5194: AND1
PORT MAP ( Y => n_6432, IN1 => n_6433);
inv_5195: INV
PORT MAP ( Y => n_6433, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5196: DELAY
PORT MAP ( Y => addr_dup07_aCLK, IN1 => n_6432);
dff_5197: DFF
PORT MAP ( D => addr_dup08_aD, CLK => addr_dup08_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup08_Q);
xor2_5198: XOR2
PORT MAP ( Y => addr_dup08_aD, IN1 => n_6440, IN2 => n_6443);
or1_5199: OR1
PORT MAP ( Y => n_6440, IN1 => n_6441);
and1_5200: AND1
PORT MAP ( Y => n_6441, IN1 => n_6442);
delay_5201: DELAY
PORT MAP ( Y => n_6442, IN1 => data(8));
and1_5202: AND1
PORT MAP ( Y => n_6443, IN1 => gnd);
and1_5203: AND1
PORT MAP ( Y => n_6444, IN1 => n_6445);
inv_5204: INV
PORT MAP ( Y => n_6445, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5205: DELAY
PORT MAP ( Y => addr_dup08_aCLK, IN1 => n_6444);
dff_5206: DFF
PORT MAP ( D => addr_dup09_aD, CLK => addr_dup09_aCLK, CLRN => vcc, PRN => vcc,
Q => addr_dup09_Q);
xor2_5207: XOR2
PORT MAP ( Y => addr_dup09_aD, IN1 => n_6452, IN2 => n_6455);
or1_5208: OR1
PORT MAP ( Y => n_6452, IN1 => n_6453);
and1_5209: AND1
PORT MAP ( Y => n_6453, IN1 => n_6454);
delay_5210: DELAY
PORT MAP ( Y => n_6454, IN1 => data(9));
and1_5211: AND1
PORT MAP ( Y => n_6455, IN1 => gnd);
and1_5212: AND1
PORT MAP ( Y => n_6456, IN1 => n_6457);
inv_5213: INV
PORT MAP ( Y => n_6457, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5214: DELAY
PORT MAP ( Y => addr_dup09_aCLK, IN1 => n_6456);
dff_5215: DFF
PORT MAP ( D => addr_dup010_aD, CLK => addr_dup010_aCLK, CLRN => vcc,
PRN => vcc, Q => addr_dup010_Q);
xor2_5216: XOR2
PORT MAP ( Y => addr_dup010_aD, IN1 => n_6464, IN2 => n_6467);
or1_5217: OR1
PORT MAP ( Y => n_6464, IN1 => n_6465);
and1_5218: AND1
PORT MAP ( Y => n_6465, IN1 => n_6466);
delay_5219: DELAY
PORT MAP ( Y => n_6466, IN1 => data(10));
and1_5220: AND1
PORT MAP ( Y => n_6467, IN1 => gnd);
and1_5221: AND1
PORT MAP ( Y => n_6468, IN1 => n_6469);
inv_5222: INV
PORT MAP ( Y => n_6469, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5223: DELAY
PORT MAP ( Y => addr_dup010_aCLK, IN1 => n_6468);
dff_5224: DFF
PORT MAP ( D => addr_dup011_aD, CLK => addr_dup011_aCLK, CLRN => vcc,
PRN => vcc, Q => addr_dup011_Q);
xor2_5225: XOR2
PORT MAP ( Y => addr_dup011_aD, IN1 => n_6476, IN2 => n_6479);
or1_5226: OR1
PORT MAP ( Y => n_6476, IN1 => n_6477);
and1_5227: AND1
PORT MAP ( Y => n_6477, IN1 => n_6478);
delay_5228: DELAY
PORT MAP ( Y => n_6478, IN1 => data(11));
and1_5229: AND1
PORT MAP ( Y => n_6479, IN1 => gnd);
and1_5230: AND1
PORT MAP ( Y => n_6480, IN1 => n_6481);
inv_5231: INV
PORT MAP ( Y => n_6481, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5232: DELAY
PORT MAP ( Y => addr_dup011_aCLK, IN1 => n_6480);
dff_5233: DFF
PORT MAP ( D => addr_dup012_aD, CLK => addr_dup012_aCLK, CLRN => vcc,
PRN => vcc, Q => addr_dup012_Q);
xor2_5234: XOR2
PORT MAP ( Y => addr_dup012_aD, IN1 => n_6488, IN2 => n_6491);
or1_5235: OR1
PORT MAP ( Y => n_6488, IN1 => n_6489);
and1_5236: AND1
PORT MAP ( Y => n_6489, IN1 => n_6490);
delay_5237: DELAY
PORT MAP ( Y => n_6490, IN1 => data(12));
and1_5238: AND1
PORT MAP ( Y => n_6491, IN1 => gnd);
and1_5239: AND1
PORT MAP ( Y => n_6492, IN1 => n_6493);
inv_5240: INV
PORT MAP ( Y => n_6493, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5241: DELAY
PORT MAP ( Y => addr_dup012_aCLK, IN1 => n_6492);
dff_5242: DFF
PORT MAP ( D => addr_dup013_aD, CLK => addr_dup013_aCLK, CLRN => vcc,
PRN => vcc, Q => addr_dup013_Q);
xor2_5243: XOR2
PORT MAP ( Y => addr_dup013_aD, IN1 => n_6500, IN2 => n_6503);
or1_5244: OR1
PORT MAP ( Y => n_6500, IN1 => n_6501);
and1_5245: AND1
PORT MAP ( Y => n_6501, IN1 => n_6502);
delay_5246: DELAY
PORT MAP ( Y => n_6502, IN1 => data(13));
and1_5247: AND1
PORT MAP ( Y => n_6503, IN1 => gnd);
and1_5248: AND1
PORT MAP ( Y => n_6504, IN1 => n_6505);
inv_5249: INV
PORT MAP ( Y => n_6505, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5250: DELAY
PORT MAP ( Y => addr_dup013_aCLK, IN1 => n_6504);
dff_5251: DFF
PORT MAP ( D => addr_dup014_aD, CLK => addr_dup014_aCLK, CLRN => vcc,
PRN => vcc, Q => addr_dup014_Q);
xor2_5252: XOR2
PORT MAP ( Y => addr_dup014_aD, IN1 => n_6512, IN2 => n_6515);
or1_5253: OR1
PORT MAP ( Y => n_6512, IN1 => n_6513);
and1_5254: AND1
PORT MAP ( Y => n_6513, IN1 => n_6514);
delay_5255: DELAY
PORT MAP ( Y => n_6514, IN1 => data(14));
and1_5256: AND1
PORT MAP ( Y => n_6515, IN1 => gnd);
and1_5257: AND1
PORT MAP ( Y => n_6516, IN1 => n_6517);
inv_5258: INV
PORT MAP ( Y => n_6517, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5259: DELAY
PORT MAP ( Y => addr_dup014_aCLK, IN1 => n_6516);
dff_5260: DFF
PORT MAP ( D => addr_dup015_aD, CLK => addr_dup015_aCLK, CLRN => vcc,
PRN => vcc, Q => addr_dup015_Q);
xor2_5261: XOR2
PORT MAP ( Y => addr_dup015_aD, IN1 => n_6524, IN2 => n_6527);
or1_5262: OR1
PORT MAP ( Y => n_6524, IN1 => n_6525);
and1_5263: AND1
PORT MAP ( Y => n_6525, IN1 => n_6526);
delay_5264: DELAY
PORT MAP ( Y => n_6526, IN1 => data(15));
and1_5265: AND1
PORT MAP ( Y => n_6527, IN1 => gnd);
and1_5266: AND1
PORT MAP ( Y => n_6528, IN1 => n_6529);
inv_5267: INV
PORT MAP ( Y => n_6529, IN1 => a_as_or4_aix1643_a_a34_aOUT_aNOT);
delay_5268: DELAY
PORT MAP ( Y => addr_dup015_aCLK, IN1 => n_6528);
delay_5269: DELAY
PORT MAP ( Y => a_as_or3_aix1644_a_a32_aOUT, IN1 => a_as_or3_aix1644_a_a32_aIN1);
xor2_5270: XOR2
PORT MAP ( Y => a_as_or3_aix1644_a_a32_aIN1, IN1 => n_6532, IN2 => n_6542);
or3_5271: OR3
PORT MAP ( Y => n_6532, IN1 => n_6533, IN2 => n_6536, IN3 => n_6539);
and2_5272: AND2
PORT MAP ( Y => n_6533, IN1 => n_6534, IN2 => n_6535);
delay_5273: DELAY
PORT MAP ( Y => n_6534, IN1 => ready);
delay_5274: DELAY
PORT MAP ( Y => n_6535, IN1 => con1_current_state5_Q);
and2_5275: AND2
PORT MAP ( Y => n_6536, IN1 => n_6537, IN2 => n_6538);
delay_5276: DELAY
PORT MAP ( Y => n_6537, IN1 => ready);
delay_5277: DELAY
PORT MAP ( Y => n_6538, IN1 => con1_current_state25_Q);
and2_5278: AND2
PORT MAP ( Y => n_6539, IN1 => n_6540, IN2 => n_6541);
delay_5279: DELAY
PORT MAP ( Y => n_6540, IN1 => ready);
delay_5280: DELAY
PORT MAP ( Y => n_6541, IN1 => con1_current_state29_Q);
and1_5281: AND1
PORT MAP ( Y => n_6542, IN1 => gnd);
delay_5282: DELAY
PORT MAP ( Y => I3_dup_732_aOUT, IN1 => I3_dup_732_aIN);
xor2_5283: XOR2
PORT MAP ( Y => I3_dup_732_aIN, IN1 => n_6544, IN2 => n_6551);
or3_5284: OR3
PORT MAP ( Y => n_6544, IN1 => n_6545, IN2 => n_6547, IN3 => n_6549);
and1_5285: AND1
PORT MAP ( Y => n_6545, IN1 => n_6546);
inv_5286: INV
PORT MAP ( Y => n_6546, IN1 => instrregout13_Q);
and1_5287: AND1
PORT MAP ( Y => n_6547, IN1 => n_6548);
delay_5288: DELAY
PORT MAP ( Y => n_6548, IN1 => instrregout15_Q);
and1_5289: AND1
PORT MAP ( Y => n_6549, IN1 => n_6550);
delay_5290: DELAY
PORT MAP ( Y => n_6550, IN1 => instrregout14_Q);
and1_5291: AND1
PORT MAP ( Y => n_6551, IN1 => gnd);
delay_5292: DELAY
PORT MAP ( Y => I3_dup_918_aOUT, IN1 => I3_dup_918_aIN);
xor2_5293: XOR2
PORT MAP ( Y => I3_dup_918_aIN, IN1 => n_6554, IN2 => n_6559);
or2_5294: OR2
PORT MAP ( Y => n_6554, IN1 => n_6555, IN2 => n_6557);
and1_5295: AND1
PORT MAP ( Y => n_6555, IN1 => n_6556);
delay_5296: DELAY
PORT MAP ( Y => n_6556, IN1 => con1_current_state44_Q);
and1_5297: AND1
PORT MAP ( Y => n_6557, IN1 => n_6558);
delay_5298: DELAY
PORT MAP ( Y => n_6558, IN1 => con1_current_state39_Q);
and1_5299: AND1
PORT MAP ( Y => n_6559, IN1 => gnd);
delay_5300: DELAY
PORT MAP ( Y => I3_dup_696_aOUT, IN1 => I3_dup_696_aIN);
xor2_5301: XOR2
PORT MAP ( Y => I3_dup_696_aIN, IN1 => n_6561, IN2 => n_6570);
or4_5302: OR4
PORT MAP ( Y => n_6561, IN1 => n_6562, IN2 => n_6564, IN3 => n_6566, IN4 => n_6568);
and1_5303: AND1
PORT MAP ( Y => n_6562, IN1 => n_6563);
delay_5304: DELAY
PORT MAP ( Y => n_6563, IN1 => con1_current_state20_Q);
and1_5305: AND1
PORT MAP ( Y => n_6564, IN1 => n_6565);
delay_5306: DELAY
PORT MAP ( Y => n_6565, IN1 => con1_current_state34_Q);
and1_5307: AND1
PORT MAP ( Y => n_6566, IN1 => n_6567);
delay_5308: DELAY
PORT MAP ( Y => n_6567, IN1 => con1_current_state33_Q);
and1_5309: AND1
PORT MAP ( Y => n_6568, IN1 => n_6569);
delay_5310: DELAY
PORT MAP ( Y => n_6569, IN1 => I3_dup_918_aOUT);
and1_5311: AND1
PORT MAP ( Y => n_6570, IN1 => gnd);
delay_5312: DELAY
PORT MAP ( Y => I1_dup_686_aOUT, IN1 => I1_dup_686_aIN);
xor2_5313: XOR2
PORT MAP ( Y => I1_dup_686_aIN, IN1 => n_6573, IN2 => n_6579);
or1_5314: OR1
PORT MAP ( Y => n_6573, IN1 => n_6574);
and4_5315: AND4
PORT MAP ( Y => n_6574, IN1 => n_6575, IN2 => n_6576, IN3 => n_6577, IN4 => n_6578);
inv_5316: INV
PORT MAP ( Y => n_6575, IN1 => con1_current_state27_Q);
inv_5317: INV
PORT MAP ( Y => n_6576, IN1 => con1_current_state26_Q);
inv_5318: INV
PORT MAP ( Y => n_6577, IN1 => con1_current_state21_Q);
inv_5319: INV
PORT MAP ( Y => n_6578, IN1 => I3_dup_696_aOUT);
and1_5320: AND1
PORT MAP ( Y => n_6579, IN1 => gnd);
delay_5321: DELAY
PORT MAP ( Y => n3_aOUT, IN1 => n3_aIN1);
and2_5322: AND2
PORT MAP ( Y => n3_aIN1, IN1 => n_6581, IN2 => n_6588);
or3_5323: OR3
PORT MAP ( Y => n_6581, IN1 => n_6582, IN2 => n_6584, IN3 => n_6586);
and1_5324: AND1
PORT MAP ( Y => n_6582, IN1 => n_6583);
delay_5325: DELAY
PORT MAP ( Y => n_6583, IN1 => instrregout12_Q);
and1_5326: AND1
PORT MAP ( Y => n_6584, IN1 => n_6585);
inv_5327: INV
PORT MAP ( Y => n_6585, IN1 => con1_current_state6_Q);
and1_5328: AND1
PORT MAP ( Y => n_6586, IN1 => n_6587);
delay_5329: DELAY
PORT MAP ( Y => n_6587, IN1 => I3_dup_732_aOUT);
delay_5330: DELAY
PORT MAP ( Y => n_6588, IN1 => I1_dup_686_aIN);
delay_5331: DELAY
PORT MAP ( Y => con1_modgen_61_nx12_aOUT, IN1 => con1_modgen_61_nx12_aIN);
xor2_5332: XOR2
PORT MAP ( Y => con1_modgen_61_nx12_aIN, IN1 => n_6590, IN2 => n_6595);
or2_5333: OR2
PORT MAP ( Y => n_6590, IN1 => n_6591, IN2 => n_6593);
and1_5334: AND1
PORT MAP ( Y => n_6591, IN1 => n_6592);
delay_5335: DELAY
PORT MAP ( Y => n_6592, IN1 => instrregout13_Q);
and1_5336: AND1
PORT MAP ( Y => n_6593, IN1 => n_6594);
delay_5337: DELAY
PORT MAP ( Y => n_6594, IN1 => instrregout14_Q);
and1_5338: AND1
PORT MAP ( Y => n_6595, IN1 => gnd);
delay_5339: DELAY
PORT MAP ( Y => con1_modgen_62_nx16_aOUT, IN1 => con1_modgen_62_nx16_aIN);
xor2_5340: XOR2
PORT MAP ( Y => con1_modgen_62_nx16_aIN, IN1 => n_6597, IN2 => n_6606);
or4_5341: OR4
PORT MAP ( Y => n_6597, IN1 => n_6598, IN2 => n_6600, IN3 => n_6602, IN4 => n_6604);
and1_5342: AND1
PORT MAP ( Y => n_6598, IN1 => n_6599);
inv_5343: INV
PORT MAP ( Y => n_6599, IN1 => instrregout12_Q);
and1_5344: AND1
PORT MAP ( Y => n_6600, IN1 => n_6601);
delay_5345: DELAY
PORT MAP ( Y => n_6601, IN1 => instrregout15_Q);
and1_5346: AND1
PORT MAP ( Y => n_6602, IN1 => n_6603);
delay_5347: DELAY
PORT MAP ( Y => n_6603, IN1 => instrregout11_Q);
and1_5348: AND1
PORT MAP ( Y => n_6604, IN1 => n_6605);
delay_5349: DELAY
PORT MAP ( Y => n_6605, IN1 => con1_modgen_61_nx12_aOUT);
and1_5350: AND1
PORT MAP ( Y => n_6606, IN1 => gnd);
delay_5351: DELAY
PORT MAP ( Y => I2_dup_1023_aOUT, IN1 => I2_dup_1023_aIN);
xor2_5352: XOR2
PORT MAP ( Y => I2_dup_1023_aIN, IN1 => n_6608, IN2 => n_6615);
or2_5353: OR2
PORT MAP ( Y => n_6608, IN1 => n_6609, IN2 => n_6612);
and2_5354: AND2
PORT MAP ( Y => n_6609, IN1 => n_6610, IN2 => n_6611);
delay_5355: DELAY
PORT MAP ( Y => n_6610, IN1 => I3_dup_732_aOUT);
delay_5356: DELAY
PORT MAP ( Y => n_6611, IN1 => con1_modgen_62_nx16_aOUT);
and2_5357: AND2
PORT MAP ( Y => n_6612, IN1 => n_6613, IN2 => n_6614);
inv_5358: INV
PORT MAP ( Y => n_6613, IN1 => instrregout12_Q);
delay_5359: DELAY
PORT MAP ( Y => n_6614, IN1 => con1_modgen_62_nx16_aOUT);
and1_5360: AND1
PORT MAP ( Y => n_6615, IN1 => gnd);
delay_5361: DELAY
PORT MAP ( Y => I3_dup_900_aOUT, IN1 => I3_dup_900_aIN);
xor2_5362: XOR2
PORT MAP ( Y => I3_dup_900_aIN, IN1 => n_6617, IN2 => n_6622);
or1_5363: OR1
PORT MAP ( Y => n_6617, IN1 => n_6618);
and3_5364: AND3
PORT MAP ( Y => n_6618, IN1 => n_6619, IN2 => n_6620, IN3 => n_6621);
inv_5365: INV
PORT MAP ( Y => n_6619, IN1 => instrregout15_Q);
inv_5366: INV
PORT MAP ( Y => n_6620, IN1 => con1_modgen_61_nx12_aOUT);
delay_5367: DELAY
PORT MAP ( Y => n_6621, IN1 => instrregout11_Q);
and1_5368: AND1
PORT MAP ( Y => n_6622, IN1 => gnd);
dff_5369: DFF
PORT MAP ( D => opregwr_aD, CLK => opregwr_aCLK, CLRN => opregwr_aCLRN,
PRN => vcc, Q => opregwr_Q);
inv_5370: INV
PORT MAP ( Y => opregwr_aCLRN, IN1 => reset);
xor2_5371: XOR2
PORT MAP ( Y => opregwr_aD, IN1 => n_6629, IN2 => n_6635);
or1_5372: OR1
PORT MAP ( Y => n_6629, IN1 => n_6630);
and4_5373: AND4
PORT MAP ( Y => n_6630, IN1 => n_6631, IN2 => n_6632, IN3 => n_6633, IN4 => n_6634);
inv_5374: INV
PORT MAP ( Y => n_6631, IN1 => instrregout11_Q);
inv_5375: INV
PORT MAP ( Y => n_6632, IN1 => I3_dup_732_aOUT);
delay_5376: DELAY
PORT MAP ( Y => n_6633, IN1 => instrregout12_Q);
delay_5377: DELAY
PORT MAP ( Y => n_6634, IN1 => con1_current_state6_Q);
and1_5378: AND1
PORT MAP ( Y => n_6635, IN1 => gnd);
delay_5379: DELAY
PORT MAP ( Y => opregwr_aCLK, IN1 => clock);
delay_5380: DELAY
PORT MAP ( Y => I3_dup_736_aOUT, IN1 => I3_dup_736_aIN);
xor2_5381: XOR2
PORT MAP ( Y => I3_dup_736_aIN, IN1 => n_6639, IN2 => n_6643);
or1_5382: OR1
PORT MAP ( Y => n_6639, IN1 => n_6640);
and2_5383: AND2
PORT MAP ( Y => n_6640, IN1 => n_6641, IN2 => n_6642);
inv_5384: INV
PORT MAP ( Y => n_6641, IN1 => con1_current_state15_Q);
inv_5385: INV
PORT MAP ( Y => n_6642, IN1 => con1_current_state17_Q);
and1_5386: AND1
PORT MAP ( Y => n_6643, IN1 => gnd);
delay_5387: DELAY
PORT MAP ( Y => con1_nx3498_aOUT, IN1 => con1_nx3498_aIN);
xor2_5388: XOR2
PORT MAP ( Y => con1_nx3498_aIN, IN1 => n_6646, IN2 => n_6655);
or4_5389: OR4
PORT MAP ( Y => n_6646, IN1 => n_6647, IN2 => n_6649, IN3 => n_6651, IN4 => n_6653);
and1_5390: AND1
PORT MAP ( Y => n_6647, IN1 => n_6648);
delay_5391: DELAY
PORT MAP ( Y => n_6648, IN1 => rw_dup0_Q);
and1_5392: AND1
PORT MAP ( Y => n_6649, IN1 => n_6650);
delay_5393: DELAY
PORT MAP ( Y => n_6650, IN1 => con1_current_state11_Q);
and1_5394: AND1
PORT MAP ( Y => n_6651, IN1 => n_6652);
delay_5395: DELAY
PORT MAP ( Y => n_6652, IN1 => opregwr_Q);
and1_5396: AND1
PORT MAP ( Y => n_6653, IN1 => n_6654);
inv_5397: INV
PORT MAP ( Y => n_6654, IN1 => I3_dup_736_aOUT);
and1_5398: AND1
PORT MAP ( Y => n_6655, IN1 => gnd);
delay_5399: DELAY
PORT MAP ( Y => opregrd_aOUT, IN1 => opregrd_aIN);
xor2_5400: XOR2
PORT MAP ( Y => opregrd_aIN, IN1 => n_6657, IN2 => n_6662);
or2_5401: OR2
PORT MAP ( Y => n_6657, IN1 => n_6658, IN2 => n_6660);
and1_5402: AND1
PORT MAP ( Y => n_6658, IN1 => n_6659);
delay_5403: DELAY
PORT MAP ( Y => n_6659, IN1 => con1_current_state32_Q);
and1_5404: AND1
PORT MAP ( Y => n_6660, IN1 => n_6661);
delay_5405: DELAY
PORT MAP ( Y => n_6661, IN1 => con1_current_state31_Q);
and1_5406: AND1
PORT MAP ( Y => n_6662, IN1 => gnd);
delay_5407: DELAY
PORT MAP ( Y => con1_nx3626_aOUT, IN1 => con1_nx3626_aIN);
xor2_5408: XOR2
PORT MAP ( Y => con1_nx3626_aIN, IN1 => n_6665, IN2 => n_6674);
or4_5409: OR4
PORT MAP ( Y => n_6665, IN1 => n_6666, IN2 => n_6668, IN3 => n_6670, IN4 => n_6672);
and1_5410: AND1
PORT MAP ( Y => n_6666, IN1 => n_6667);
delay_5411: DELAY
PORT MAP ( Y => n_6667, IN1 => con1_current_state14_Q);
and1_5412: AND1
PORT MAP ( Y => n_6668, IN1 => n_6669);
delay_5413: DELAY
PORT MAP ( Y => n_6669, IN1 => con1_current_state49_Q);
and1_5414: AND1
PORT MAP ( Y => n_6670, IN1 => n_6671);
delay_5415: DELAY
PORT MAP ( Y => n_6671, IN1 => con1_nx3498_aOUT);
and1_5416: AND1
PORT MAP ( Y => n_6672, IN1 => n_6673);
delay_5417: DELAY
PORT MAP ( Y => n_6673, IN1 => opregrd_aOUT);
and1_5418: AND1
PORT MAP ( Y => n_6674, IN1 => gnd);
delay_5419: DELAY
PORT MAP ( Y => I2_dup_823_aOUT, IN1 => I2_dup_823_aIN);
xor2_5420: XOR2
PORT MAP ( Y => I2_dup_823_aIN, IN1 => n_6676, IN2 => n_6685);
or3_5421: OR3
PORT MAP ( Y => n_6676, IN1 => n_6677, IN2 => n_6680, IN3 => n_6683);
and2_5422: AND2
PORT MAP ( Y => n_6677, IN1 => n_6678, IN2 => n_6679);
inv_5423: INV
PORT MAP ( Y => n_6678, IN1 => I2_dup_1023_aOUT);
delay_5424: DELAY
PORT MAP ( Y => n_6679, IN1 => con1_current_state6_Q);
and2_5425: AND2
PORT MAP ( Y => n_6680, IN1 => n_6681, IN2 => n_6682);
delay_5426: DELAY
PORT MAP ( Y => n_6681, IN1 => I3_dup_900_aOUT);
delay_5427: DELAY
PORT MAP ( Y => n_6682, IN1 => con1_current_state6_Q);
and1_5428: AND1
PORT MAP ( Y => n_6683, IN1 => n_6684);
delay_5429: DELAY
PORT MAP ( Y => n_6684, IN1 => con1_nx3626_aOUT);
and1_5430: AND1
PORT MAP ( Y => n_6685, IN1 => gnd);
delay_5431: DELAY
PORT MAP ( Y => I2_dup_681_aOUT, IN1 => I2_dup_681_aIN);
xor2_5432: XOR2
PORT MAP ( Y => I2_dup_681_aIN, IN1 => n_6687, IN2 => n_6696);
or4_5433: OR4
PORT MAP ( Y => n_6687, IN1 => n_6688, IN2 => n_6690, IN3 => n_6692, IN4 => n_6694);
and1_5434: AND1
PORT MAP ( Y => n_6688, IN1 => n_6689);
delay_5435: DELAY
PORT MAP ( Y => n_6689, IN1 => con1_current_state3_Q);
and1_5436: AND1
PORT MAP ( Y => n_6690, IN1 => n_6691);
delay_5437: DELAY
PORT MAP ( Y => n_6691, IN1 => con1_current_state46_Q);
and1_5438: AND1
PORT MAP ( Y => n_6692, IN1 => n_6693);
delay_5439: DELAY
PORT MAP ( Y => n_6693, IN1 => con1_current_state41_Q);
and1_5440: AND1
PORT MAP ( Y => n_6694, IN1 => n_6695);
delay_5441: DELAY
PORT MAP ( Y => n_6695, IN1 => con1_current_state36_Q);
and1_5442: AND1
PORT MAP ( Y => n_6696, IN1 => gnd);
delay_5443: DELAY
PORT MAP ( Y => O_dup_1049_aOUT, IN1 => O_dup_1049_aIN);
xor2_5444: XOR2
PORT MAP ( Y => O_dup_1049_aIN, IN1 => n_6699, IN2 => n_6705);
or1_5445: OR1
PORT MAP ( Y => n_6699, IN1 => n_6700);
and4_5446: AND4
PORT MAP ( Y => n_6700, IN1 => n_6701, IN2 => n_6702, IN3 => n_6703, IN4 => n_6704);
inv_5447: INV
PORT MAP ( Y => n_6701, IN1 => con1_current_state22_Q);
inv_5448: INV
PORT MAP ( Y => n_6702, IN1 => con1_current_state35_Q);
inv_5449: INV
PORT MAP ( Y => n_6703, IN1 => con1_current_state40_Q);
inv_5450: INV
PORT MAP ( Y => n_6704, IN1 => con1_current_state18_Q);
and1_5451: AND1
PORT MAP ( Y => n_6705, IN1 => gnd);
delay_5452: DELAY
PORT MAP ( Y => I3_dup_677_aOUT, IN1 => I3_dup_677_aIN1);
and2_5453: AND2
PORT MAP ( Y => I3_dup_677_aIN1, IN1 => n_6708, IN2 => n_6714);
or1_5454: OR1
PORT MAP ( Y => n_6708, IN1 => n_6709);
and4_5455: AND4
PORT MAP ( Y => n_6709, IN1 => n_6710, IN2 => n_6711, IN3 => n_6712, IN4 => n_6713);
inv_5456: INV
PORT MAP ( Y => n_6710, IN1 => con1_current_state2_Q);
inv_5457: INV
PORT MAP ( Y => n_6711, IN1 => con1_current_state51_Q);
inv_5458: INV
PORT MAP ( Y => n_6712, IN1 => con1_current_state19_Q);
inv_5459: INV
PORT MAP ( Y => n_6713, IN1 => I2_dup_681_aOUT);
delay_5460: DELAY
PORT MAP ( Y => n_6714, IN1 => O_dup_1049_aIN);
delay_5461: DELAY
PORT MAP ( Y => outregrd_aOUT, IN1 => outregrd_aIN);
xor2_5462: XOR2
PORT MAP ( Y => outregrd_aIN, IN1 => n_6716, IN2 => n_6725);
or4_5463: OR4
PORT MAP ( Y => n_6716, IN1 => n_6717, IN2 => n_6719, IN3 => n_6721, IN4 => n_6723);
and1_5464: AND1
PORT MAP ( Y => n_6717, IN1 => n_6718);
delay_5465: DELAY
PORT MAP ( Y => n_6718, IN1 => con1_current_state23_Q);
and1_5466: AND1
PORT MAP ( Y => n_6719, IN1 => n_6720);
delay_5467: DELAY
PORT MAP ( Y => n_6720, IN1 => con1_current_state45_Q);
and1_5468: AND1
PORT MAP ( Y => n_6721, IN1 => n_6722);
delay_5469: DELAY
PORT MAP ( Y => n_6722, IN1 => con1_current_state50_Q);
and1_5470: AND1
PORT MAP ( Y => n_6723, IN1 => n_6724);
inv_5471: INV
PORT MAP ( Y => n_6724, IN1 => I3_dup_677_aOUT);
and1_5472: AND1
PORT MAP ( Y => n_6725, IN1 => gnd);
delay_5473: DELAY
PORT MAP ( Y => a_as_or3_aix1786_a_a32_aOUT, IN1 => a_as_or3_aix1786_a_a32_aIN1);
xor2_5474: XOR2
PORT MAP ( Y => a_as_or3_aix1786_a_a32_aIN1, IN1 => n_6727, IN2 => n_6734);
or3_5475: OR3
PORT MAP ( Y => n_6727, IN1 => n_6728, IN2 => n_6730, IN3 => n_6732);
and1_5476: AND1
PORT MAP ( Y => n_6728, IN1 => n_6729);
inv_5477: INV
PORT MAP ( Y => n_6729, IN1 => n3_aOUT);
and1_5478: AND1
PORT MAP ( Y => n_6730, IN1 => n_6731);
delay_5479: DELAY
PORT MAP ( Y => n_6731, IN1 => I2_dup_823_aOUT);
and1_5480: AND1
PORT MAP ( Y => n_6732, IN1 => n_6733);
delay_5481: DELAY
PORT MAP ( Y => n_6733, IN1 => outregrd_aOUT);
and1_5482: AND1
PORT MAP ( Y => n_6734, IN1 => gnd);
delay_5483: DELAY
PORT MAP ( Y => con1_modgen_66_nx16_aOUT, IN1 => con1_modgen_66_nx16_aIN);
xor2_5484: XOR2
PORT MAP ( Y => con1_modgen_66_nx16_aIN, IN1 => n_6737, IN2 => n_6744);
or3_5485: OR3
PORT MAP ( Y => n_6737, IN1 => n_6738, IN2 => n_6740, IN3 => n_6742);
and1_5486: AND1
PORT MAP ( Y => n_6738, IN1 => n_6739);
inv_5487: INV
PORT MAP ( Y => n_6739, IN1 => instrregout12_Q);
and1_5488: AND1
PORT MAP ( Y => n_6740, IN1 => n_6741);
delay_5489: DELAY
PORT MAP ( Y => n_6741, IN1 => instrregout11_Q);
and1_5490: AND1
PORT MAP ( Y => n_6742, IN1 => n_6743);
delay_5491: DELAY
PORT MAP ( Y => n_6743, IN1 => I3_dup_732_aOUT);
and1_5492: AND1
PORT MAP ( Y => n_6744, IN1 => gnd);
delay_5493: DELAY
PORT MAP ( Y => O_dup_901_aOUT, IN1 => O_dup_901_aIN);
xor2_5494: XOR2
PORT MAP ( Y => O_dup_901_aIN, IN1 => n_6747, IN2 => n_6756);
or3_5495: OR3
PORT MAP ( Y => n_6747, IN1 => n_6748, IN2 => n_6751, IN3 => n_6754);
and2_5496: AND2
PORT MAP ( Y => n_6748, IN1 => n_6749, IN2 => n_6750);
inv_5497: INV
PORT MAP ( Y => n_6749, IN1 => con1_modgen_66_nx16_aOUT);
delay_5498: DELAY
PORT MAP ( Y => n_6750, IN1 => con1_current_state6_Q);
and2_5499: AND2
PORT MAP ( Y => n_6751, IN1 => n_6752, IN2 => n_6753);
delay_5500: DELAY
PORT MAP ( Y => n_6752, IN1 => I3_dup_900_aOUT);
delay_5501: DELAY
PORT MAP ( Y => n_6753, IN1 => con1_current_state6_Q);
and1_5502: AND1
PORT MAP ( Y => n_6754, IN1 => n_6755);
delay_5503: DELAY
PORT MAP ( Y => n_6755, IN1 => con1_nx3498_aOUT);
and1_5504: AND1
PORT MAP ( Y => n_6756, IN1 => gnd);
delay_5505: DELAY
PORT MAP ( Y => I3_dup_1509_aOUT, IN1 => I3_dup_1509_aIN);
xor2_5506: XOR2
PORT MAP ( Y => I3_dup_1509_aIN, IN1 => n_6759, IN2 => n_6763);
or1_5507: OR1
PORT MAP ( Y => n_6759, IN1 => n_6760);
and2_5508: AND2
PORT MAP ( Y => n_6760, IN1 => n_6761, IN2 => n_6762);
delay_5509: DELAY
PORT MAP ( Y => n_6761, IN1 => O_dup_901_aOUT);
delay_5510: DELAY
PORT MAP ( Y => n_6762, IN1 => instrregout4_Q);
and1_5511: AND1
PORT MAP ( Y => n_6763, IN1 => gnd);
delay_5512: DELAY
PORT MAP ( Y => con1_next_state14_aOUT, IN1 => con1_next_state14_aIN1);
xor2_5513: XOR2
PORT MAP ( Y => con1_next_state14_aIN1, IN1 => n_6766, IN2 => n_6770);
or1_5514: OR1
PORT MAP ( Y => n_6766, IN1 => n_6767);
and2_5515: AND2
PORT MAP ( Y => n_6767, IN1 => n_6768, IN2 => n_6769);
inv_5516: INV
PORT MAP ( Y => n_6768, IN1 => con1_modgen_62_nx16_aOUT);
delay_5517: DELAY
PORT MAP ( Y => n_6769, IN1 => con1_current_state6_Q);
and1_5518: AND1
PORT MAP ( Y => n_6770, IN1 => gnd);
delay_5519: DELAY
PORT MAP ( Y => con1_next_state49_aOUT, IN1 => con1_next_state49_aIN1);
xor2_5520: XOR2
PORT MAP ( Y => con1_next_state49_aIN1, IN1 => n_6773, IN2 => n_6779);
or1_5521: OR1
PORT MAP ( Y => n_6773, IN1 => n_6774);
and4_5522: AND4
PORT MAP ( Y => n_6774, IN1 => n_6775, IN2 => n_6776, IN3 => n_6777, IN4 => n_6778);
inv_5523: INV
PORT MAP ( Y => n_6775, IN1 => I3_dup_732_aOUT);
delay_5524: DELAY
PORT MAP ( Y => n_6776, IN1 => instrregout11_Q);
delay_5525: DELAY
PORT MAP ( Y => n_6777, IN1 => instrregout12_Q);
delay_5526: DELAY
PORT MAP ( Y => n_6778, IN1 => con1_current_state6_Q);
and1_5527: AND1
PORT MAP ( Y => n_6779, IN1 => gnd);
delay_5528: DELAY
PORT MAP ( Y => I1_dup_670_aOUT, IN1 => I1_dup_670_aIN);
xor2_5529: XOR2
PORT MAP ( Y => I1_dup_670_aIN, IN1 => n_6782, IN2 => n_6790);
or3_5530: OR3
PORT MAP ( Y => n_6782, IN1 => n_6783, IN2 => n_6785, IN3 => n_6788);
and1_5531: AND1
PORT MAP ( Y => n_6783, IN1 => n_6784);
delay_5532: DELAY
PORT MAP ( Y => n_6784, IN1 => con1_next_state14_aOUT);
and2_5533: AND2
PORT MAP ( Y => n_6785, IN1 => n_6786, IN2 => n_6787);
delay_5534: DELAY
PORT MAP ( Y => n_6786, IN1 => ready);
delay_5535: DELAY
PORT MAP ( Y => n_6787, IN1 => con1_current_state48_Q);
and1_5536: AND1
PORT MAP ( Y => n_6788, IN1 => n_6789);
delay_5537: DELAY
PORT MAP ( Y => n_6789, IN1 => con1_next_state49_aOUT);
and1_5538: AND1
PORT MAP ( Y => n_6790, IN1 => gnd);
delay_5539: DELAY
PORT MAP ( Y => I3_dup_1546_aOUT, IN1 => I3_dup_1546_aIN);
xor2_5540: XOR2
PORT MAP ( Y => I3_dup_1546_aIN, IN1 => n_6793, IN2 => n_6800);
or3_5541: OR3
PORT MAP ( Y => n_6793, IN1 => n_6794, IN2 => n_6796, IN3 => n_6798);
and1_5542: AND1
PORT MAP ( Y => n_6794, IN1 => n_6795);
delay_5543: DELAY
PORT MAP ( Y => n_6795, IN1 => con1_current_state13_Q);
and1_5544: AND1
PORT MAP ( Y => n_6796, IN1 => n_6797);
delay_5545: DELAY
PORT MAP ( Y => n_6797, IN1 => con1_current_state51_Q);
and1_5546: AND1
PORT MAP ( Y => n_6798, IN1 => n_6799);
delay_5547: DELAY
PORT MAP ( Y => n_6799, IN1 => con1_current_state19_Q);
and1_5548: AND1
PORT MAP ( Y => n_6800, IN1 => gnd);
delay_5549: DELAY
PORT MAP ( Y => I2_aOUT, IN1 => I2_aIN);
xor2_5550: XOR2
PORT MAP ( Y => I2_aIN, IN1 => n_6803, IN2 => n_6809);
or1_5551: OR1
PORT MAP ( Y => n_6803, IN1 => n_6804);
and4_5552: AND4
PORT MAP ( Y => n_6804, IN1 => n_6805, IN2 => n_6806, IN3 => n_6807, IN4 => n_6808);
inv_5553: INV
PORT MAP ( Y => n_6805, IN1 => con1_current_state14_Q);
inv_5554: INV
PORT MAP ( Y => n_6806, IN1 => con1_current_state49_Q);
inv_5555: INV
PORT MAP ( Y => n_6807, IN1 => I3_dup_1546_aOUT);
inv_5556: INV
PORT MAP ( Y => n_6808, IN1 => opregrd_aOUT);
and1_5557: AND1
PORT MAP ( Y => n_6809, IN1 => gnd);
delay_5558: DELAY
PORT MAP ( Y => I1_dup_755_aOUT, IN1 => I1_dup_755_aIN);
xor2_5559: XOR2
PORT MAP ( Y => I1_dup_755_aIN, IN1 => n_6811, IN2 => n_6820);
or3_5560: OR3
PORT MAP ( Y => n_6811, IN1 => n_6812, IN2 => n_6814, IN3 => n_6817);
and1_5561: AND1
PORT MAP ( Y => n_6812, IN1 => n_6813);
delay_5562: DELAY
PORT MAP ( Y => n_6813, IN1 => I3_dup_1509_aOUT);
and2_5563: AND2
PORT MAP ( Y => n_6814, IN1 => n_6815, IN2 => n_6816);
delay_5564: DELAY
PORT MAP ( Y => n_6815, IN1 => I1_dup_670_aOUT);
delay_5565: DELAY
PORT MAP ( Y => n_6816, IN1 => instrregout1_Q);
and2_5566: AND2
PORT MAP ( Y => n_6817, IN1 => n_6818, IN2 => n_6819);
inv_5567: INV
PORT MAP ( Y => n_6818, IN1 => I2_aOUT);
delay_5568: DELAY
PORT MAP ( Y => n_6819, IN1 => instrregout1_Q);
and1_5569: AND1
PORT MAP ( Y => n_6820, IN1 => gnd);
delay_5570: DELAY
PORT MAP ( Y => O_dup_1505_aOUT, IN1 => O_dup_1505_aIN);
xor2_5571: XOR2
PORT MAP ( Y => O_dup_1505_aIN, IN1 => n_6823, IN2 => n_6828);
or2_5572: OR2
PORT MAP ( Y => n_6823, IN1 => n_6824, IN2 => n_6826);
and1_5573: AND1
PORT MAP ( Y => n_6824, IN1 => n_6825);
inv_5574: INV
PORT MAP ( Y => n_6825, IN1 => instrregout2_Q);
and1_5575: AND1
PORT MAP ( Y => n_6826, IN1 => n_6827);
delay_5576: DELAY
PORT MAP ( Y => n_6827, IN1 => I2_aOUT);
and1_5577: AND1
PORT MAP ( Y => n_6828, IN1 => gnd);
delay_5578: DELAY
PORT MAP ( Y => I0_dup_770_aOUT, IN1 => I0_dup_770_aIN);
xor2_5579: XOR2
PORT MAP ( Y => I0_dup_770_aIN, IN1 => n_6830, IN2 => n_6834);
or1_5580: OR1
PORT MAP ( Y => n_6830, IN1 => n_6831);
and2_5581: AND2
PORT MAP ( Y => n_6831, IN1 => n_6832, IN2 => n_6833);
inv_5582: INV
PORT MAP ( Y => n_6832, IN1 => I1_dup_755_aOUT);
delay_5583: DELAY
PORT MAP ( Y => n_6833, IN1 => O_dup_1505_aOUT);
and1_5584: AND1
PORT MAP ( Y => n_6834, IN1 => gnd);
delay_5585: DELAY
PORT MAP ( Y => I3_aOUT, IN1 => I3_aIN);
xor2_5586: XOR2
PORT MAP ( Y => I3_aIN, IN1 => n_6837, IN2 => n_6841);
or1_5587: OR1
PORT MAP ( Y => n_6837, IN1 => n_6838);
and2_5588: AND2
PORT MAP ( Y => n_6838, IN1 => n_6839, IN2 => n_6840);
delay_5589: DELAY
PORT MAP ( Y => n_6839, IN1 => O_dup_901_aOUT);
delay_5590: DELAY
PORT MAP ( Y => n_6840, IN1 => instrregout3_Q);
and1_5591: AND1
PORT MAP ( Y => n_6841, IN1 => gnd);
delay_5592: DELAY
PORT MAP ( Y => regsel0_aOUT, IN1 => regsel0_aIN);
xor2_5593: XOR2
PORT MAP ( Y => regsel0_aIN, IN1 => n_6843, IN2 => n_6852);
or3_5594: OR3
PORT MAP ( Y => n_6843, IN1 => n_6844, IN2 => n_6846, IN3 => n_6849);
and1_5595: AND1
PORT MAP ( Y => n_6844, IN1 => n_6845);
delay_5596: DELAY
PORT MAP ( Y => n_6845, IN1 => I3_aOUT);
and2_5597: AND2
PORT MAP ( Y => n_6846, IN1 => n_6847, IN2 => n_6848);
delay_5598: DELAY
PORT MAP ( Y => n_6847, IN1 => I1_dup_670_aOUT);
delay_5599: DELAY
PORT MAP ( Y => n_6848, IN1 => instrregout0_Q);
and2_5600: AND2
PORT MAP ( Y => n_6849, IN1 => n_6850, IN2 => n_6851);
inv_5601: INV
PORT MAP ( Y => n_6850, IN1 => I2_aOUT);
delay_5602: DELAY
PORT MAP ( Y => n_6851, IN1 => instrregout0_Q);
and1_5603: AND1
PORT MAP ( Y => n_6852, IN1 => gnd);
delay_5604: DELAY
PORT MAP ( Y => O_dup_1034_aOUT, IN1 => O_dup_1034_aIN);
xor2_5605: XOR2
PORT MAP ( Y => O_dup_1034_aIN, IN1 => n_6854, IN2 => n_6861);
or2_5606: OR2
PORT MAP ( Y => n_6854, IN1 => n_6855, IN2 => n_6858);
and2_5607: AND2
PORT MAP ( Y => n_6855, IN1 => n_6856, IN2 => n_6857);
delay_5608: DELAY
PORT MAP ( Y => n_6856, IN1 => I1_dup_670_aOUT);
delay_5609: DELAY
PORT MAP ( Y => n_6857, IN1 => instrregout2_Q);
and2_5610: AND2
PORT MAP ( Y => n_6858, IN1 => n_6859, IN2 => n_6860);
delay_5611: DELAY
PORT MAP ( Y => n_6859, IN1 => O_dup_901_aOUT);
delay_5612: DELAY
PORT MAP ( Y => n_6860, IN1 => instrregout5_Q);
and1_5613: AND1
PORT MAP ( Y => n_6861, IN1 => gnd);
delay_5614: DELAY
PORT MAP ( Y => I0_dup_768_aOUT, IN1 => I0_dup_768_aIN);
xor2_5615: XOR2
PORT MAP ( Y => I0_dup_768_aIN, IN1 => n_6864, IN2 => n_6868);
or1_5616: OR1
PORT MAP ( Y => n_6864, IN1 => n_6865);
and2_5617: AND2
PORT MAP ( Y => n_6865, IN1 => n_6866, IN2 => n_6867);
inv_5618: INV
PORT MAP ( Y => n_6866, IN1 => O_dup_1034_aOUT);
inv_5619: INV
PORT MAP ( Y => n_6867, IN1 => regsel0_aOUT);
and1_5620: AND1
PORT MAP ( Y => n_6868, IN1 => gnd);
delay_5621: DELAY
PORT MAP ( Y => ix484_nx45_aOUT, IN1 => ix484_nx45_aIN);
xor2_5622: XOR2
PORT MAP ( Y => ix484_nx45_aIN, IN1 => n_6870, IN2 => n_6874);
or1_5623: OR1
PORT MAP ( Y => n_6870, IN1 => n_6871);
and2_5624: AND2
PORT MAP ( Y => n_6871, IN1 => n_6872, IN2 => n_6873);
delay_5625: DELAY
PORT MAP ( Y => n_6872, IN1 => I0_dup_770_aOUT);
delay_5626: DELAY
PORT MAP ( Y => n_6873, IN1 => I0_dup_768_aOUT);
and1_5627: AND1
PORT MAP ( Y => n_6874, IN1 => gnd);
delay_5628: DELAY
PORT MAP ( Y => O_dup_873_aOUT, IN1 => O_dup_873_aIN);
xor2_5629: XOR2
PORT MAP ( Y => O_dup_873_aIN, IN1 => n_6876, IN2 => n_6880);
or1_5630: OR1
PORT MAP ( Y => n_6876, IN1 => n_6877);
and2_5631: AND2
PORT MAP ( Y => n_6877, IN1 => n_6878, IN2 => n_6879);
delay_5632: DELAY
PORT MAP ( Y => n_6878, IN1 => I2_dup_823_aOUT);
delay_5633: DELAY
PORT MAP ( Y => n_6879, IN1 => ix484_nx45_aOUT);
and1_5634: AND1
PORT MAP ( Y => n_6880, IN1 => gnd);
delay_5635: DELAY
PORT MAP ( Y => I2_dup_756_aOUT, IN1 => I2_dup_756_aIN);
xor2_5636: XOR2
PORT MAP ( Y => I2_dup_756_aIN, IN1 => n_6882, IN2 => n_6887);
or2_5637: OR2
PORT MAP ( Y => n_6882, IN1 => n_6883, IN2 => n_6885);
and1_5638: AND1
PORT MAP ( Y => n_6883, IN1 => n_6884);
delay_5639: DELAY
PORT MAP ( Y => n_6884, IN1 => O_dup_1034_aOUT);
and1_5640: AND1
PORT MAP ( Y => n_6885, IN1 => n_6886);
inv_5641: INV
PORT MAP ( Y => n_6886, IN1 => O_dup_1505_aOUT);
and1_5642: AND1
PORT MAP ( Y => n_6887, IN1 => gnd);
delay_5643: DELAY
PORT MAP ( Y => ix484_nx41_aOUT, IN1 => ix484_nx41_aIN);
xor2_5644: XOR2
PORT MAP ( Y => ix484_nx41_aIN, IN1 => n_6889, IN2 => n_6894);
or1_5645: OR1
PORT MAP ( Y => n_6889, IN1 => n_6890);
and3_5646: AND3
PORT MAP ( Y => n_6890, IN1 => n_6891, IN2 => n_6892, IN3 => n_6893);
inv_5647: INV
PORT MAP ( Y => n_6891, IN1 => regsel0_aOUT);
inv_5648: INV
PORT MAP ( Y => n_6892, IN1 => I1_dup_755_aOUT);
delay_5649: DELAY
PORT MAP ( Y => n_6893, IN1 => I2_dup_756_aOUT);
and1_5650: AND1
PORT MAP ( Y => n_6894, IN1 => gnd);
delay_5651: DELAY
PORT MAP ( Y => O_dup_870_aOUT, IN1 => O_dup_870_aIN);
xor2_5652: XOR2
PORT MAP ( Y => O_dup_870_aIN, IN1 => n_6896, IN2 => n_6900);
or1_5653: OR1
PORT MAP ( Y => n_6896, IN1 => n_6897);
and2_5654: AND2
PORT MAP ( Y => n_6897, IN1 => n_6898, IN2 => n_6899);
delay_5655: DELAY
PORT MAP ( Y => n_6898, IN1 => I2_dup_823_aOUT);
delay_5656: DELAY
PORT MAP ( Y => n_6899, IN1 => ix484_nx41_aOUT);
and1_5657: AND1
PORT MAP ( Y => n_6900, IN1 => gnd);
delay_5658: DELAY
PORT MAP ( Y => ix484_nx38_aOUT, IN1 => ix484_nx38_aIN);
xor2_5659: XOR2
PORT MAP ( Y => ix484_nx38_aIN, IN1 => n_6902, IN2 => n_6907);
or1_5660: OR1
PORT MAP ( Y => n_6902, IN1 => n_6903);
and3_5661: AND3
PORT MAP ( Y => n_6903, IN1 => n_6904, IN2 => n_6905, IN3 => n_6906);
delay_5662: DELAY
PORT MAP ( Y => n_6904, IN1 => I1_dup_755_aOUT);
delay_5663: DELAY
PORT MAP ( Y => n_6905, IN1 => regsel0_aOUT);
delay_5664: DELAY
PORT MAP ( Y => n_6906, IN1 => I2_dup_756_aOUT);
and1_5665: AND1
PORT MAP ( Y => n_6907, IN1 => gnd);
delay_5666: DELAY
PORT MAP ( Y => O_dup_879_aOUT, IN1 => O_dup_879_aIN);
xor2_5667: XOR2
PORT MAP ( Y => O_dup_879_aIN, IN1 => n_6909, IN2 => n_6913);
or1_5668: OR1
PORT MAP ( Y => n_6909, IN1 => n_6910);
and2_5669: AND2
PORT MAP ( Y => n_6910, IN1 => n_6911, IN2 => n_6912);
delay_5670: DELAY
PORT MAP ( Y => n_6911, IN1 => I2_dup_823_aOUT);
delay_5671: DELAY
PORT MAP ( Y => n_6912, IN1 => ix484_nx38_aOUT);
and1_5672: AND1
PORT MAP ( Y => n_6913, IN1 => gnd);
delay_5673: DELAY
PORT MAP ( Y => I0_dup_766_aOUT, IN1 => I0_dup_766_aIN);
xor2_5674: XOR2
PORT MAP ( Y => I0_dup_766_aIN, IN1 => n_6915, IN2 => n_6919);
or1_5675: OR1
PORT MAP ( Y => n_6915, IN1 => n_6916);
and2_5676: AND2
PORT MAP ( Y => n_6916, IN1 => n_6917, IN2 => n_6918);
delay_5677: DELAY
PORT MAP ( Y => n_6917, IN1 => I1_dup_755_aOUT);
delay_5678: DELAY
PORT MAP ( Y => n_6918, IN1 => O_dup_1505_aOUT);
and1_5679: AND1
PORT MAP ( Y => n_6919, IN1 => gnd);
delay_5680: DELAY
PORT MAP ( Y => ix484_nx43_aOUT, IN1 => ix484_nx43_aIN);
xor2_5681: XOR2
PORT MAP ( Y => ix484_nx43_aIN, IN1 => n_6921, IN2 => n_6925);
or1_5682: OR1
PORT MAP ( Y => n_6921, IN1 => n_6922);
and2_5683: AND2
PORT MAP ( Y => n_6922, IN1 => n_6923, IN2 => n_6924);
delay_5684: DELAY
PORT MAP ( Y => n_6923, IN1 => I0_dup_768_aOUT);
delay_5685: DELAY
PORT MAP ( Y => n_6924, IN1 => I0_dup_766_aOUT);
and1_5686: AND1
PORT MAP ( Y => n_6925, IN1 => gnd);
END EPF10K10TC144_a3;
|
gpl-3.0
|
tejainece/VHDLExperiments
|
Multiply16Booth4/Multiply16Booth4.vhd
|
1
|
3756
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:23 01/22/2014
-- Design Name:
-- Module Name: Multiply16Booth4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(31 downto 0));
end Multiply16Booth4;
architecture Behavioral of Multiply16Booth4 is
COMPONENT BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end COMPONENT;
COMPONENT BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end COMPONENT;
SIGNAL aTmp: STD_LOGIC_VECTOR(16 downto 0);
SIGNAL oTmp: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL prod0: STD_LOGIC_VECTOR(19 downto 0);
SIGNAL prod1: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod2: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod3: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod4: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod5: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod6: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod7: STD_LOGIC_VECTOR(17 downto 0);
begin
aTmp <= a & '0';
prod0(19 downto 17) <= (not prod0(16)) & prod0(16) & prod0(16);
prod1(18 downto 17) <= '1' & (not prod1(16));
prod2(18 downto 17) <= '1' & (not prod2(16));
prod3(18 downto 17) <= '1' & (not prod3(16));
prod4(18 downto 17) <= '1' & (not prod4(16));
prod5(18 downto 17) <= '1' & (not prod5(16));
prod6(18 downto 17) <= '1' & (not prod6(16));
prod7(17) <= not prod7(16);
prodgen0: BoothPartProdGen PORT MAP (
bin3 => aTmp(2 downto 0),
a => b,
product => prod0(16 downto 0)
);
prodgen1: BoothPartProdGen PORT MAP (
bin3 => aTmp(4 downto 2),
a => b,
product => prod1(16 downto 0)
);
prodgen2: BoothPartProdGen PORT MAP (
bin3 => aTmp(6 downto 4),
a => b,
product => prod2(16 downto 0)
);
prodgen3: BoothPartProdGen PORT MAP (
bin3 => aTmp(8 downto 6),
a => b,
product => prod3(16 downto 0)
);
prodgen4: BoothPartProdGen PORT MAP (
bin3 => aTmp(10 downto 8),
a => b,
product => prod4(16 downto 0)
);
prodgen5: BoothPartProdGen PORT MAP (
bin3 => aTmp(12 downto 10),
a => b,
product => prod5(16 downto 0)
);
prodgen6: BoothPartProdGen PORT MAP (
bin3 => aTmp(14 downto 12),
a => b,
product => prod6(16 downto 0)
);
prodgen7: BoothPartProdGen PORT MAP (
bin3 => aTmp(16 downto 14),
a => b,
product => prod7(16 downto 0)
);
output: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => oTmp
);
o <= oTmp(31 downto 0);
end Behavioral;
|
gpl-3.0
|
marc0l92/RadioFM_FPGA
|
RadioFM_project/ipcore_dir/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.vhd
|
1
|
6020
|
-- file: clk_wiz_v3_6_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clk_wiz_v3_6_exdes;
architecture xilinx of clk_wiz_v3_6_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- When the clock goes out of lock, reset the counters
signal locked_int : std_logic;
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clk_wiz_v3_6 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Alias output to internally used signal
LOCKED <= locked_int;
-- When the clock goes out of lock, reset the counters
reset_int <= (not locked_int) or RESET or COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clk_wiz_v3_6
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int,
-- Status and control signals
RESET => RESET,
LOCKED => locked_int);
clkout_oddr : ODDR port map
(Q => CLK_OUT(1),
C => clk,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
|
gpl-3.0
|
johnmurrayvi/vhdl-projects
|
CPU/topconstruct.vhd
|
1
|
159
|
configuration topconstruct of top is
for behave
for U1 : cpu use entity work.cpu(EPF10K10TC144_a3);
end for;
end for;
end topconstruct;
|
gpl-3.0
|
tejainece/VHDLExperiments
|
BoothPartProdRed/BoothPartProdRed_tb.vhd
|
1
|
3256
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:08:01 01/21/2014
-- Design Name:
-- Module Name: /home/tejainece/learnings/xilinx/BoothPartProdRed/BoothPartProdRed_tb.vhd
-- Project Name: BoothPartProdRed
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: BoothPartProdRed
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY BoothPartProdRed_tb IS
END BoothPartProdRed_tb;
ARCHITECTURE behavior OF BoothPartProdRed_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BoothPartProdRed
PORT(
prod0 : IN std_logic_vector(19 downto 0);
prod1 : IN std_logic_vector(20 downto 2);
prod2 : IN std_logic_vector(22 downto 4);
prod3 : IN std_logic_vector(24 downto 6);
prod4 : IN std_logic_vector(26 downto 8);
prod5 : IN std_logic_vector(28 downto 10);
prod6 : IN std_logic_vector(30 downto 12);
prod7 : IN std_logic_vector(31 downto 14);
result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal prod0 : std_logic_vector(19 downto 0) := (others => '0');
signal prod1 : std_logic_vector(20 downto 2) := (others => '0');
signal prod2 : std_logic_vector(22 downto 4) := (others => '0');
signal prod3 : std_logic_vector(24 downto 6) := (others => '0');
signal prod4 : std_logic_vector(26 downto 8) := (others => '0');
signal prod5 : std_logic_vector(28 downto 10) := (others => '0');
signal prod6 : std_logic_vector(30 downto 12) := (others => '0');
signal prod7 : std_logic_vector(31 downto 14) := (others => '0');
--Outputs
signal result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
prod0 <= "11111111111111111111";
prod1 <= "1111111111111111111";
prod2 <= "0000000000000000001";
prod3 <= "1111111111111111111";
prod4 <= "0000000000000000001";
prod5 <= "0000000000000000001";
prod6 <= "0000000000000000001";
prod7 <= "000000000000000001";
wait for 100 ns;
wait for 100 ns;
wait;
end process;
END;
|
gpl-3.0
|
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/resolution_mouse_informer.vhd
|
2
|
8361
|
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic that send the mouse_controller new
-- position of the mouse and new maximum values for the position
-- when resolution changes, so that the mouse will be centered on the
-- screen and the bounds for the new resolution are properly set.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- This module implements the logic that sets the position of the mouse
-- when the fpga is powered-up and when the resolution changes. It
-- also sets the bounds of the mouse corresponding to the currently used
-- resolution.
-- The mouse is centered for the currently selected resolution and the
-- bounds are set appropriately. This way the mouse will first appear
-- in the center in the screen at start-up and when resolution is
-- changed and cannot leave the screen.
-- The position (and similarly the bounds) is set by placing and number
-- representing the middle of the screen dimension on the value output
-- and activation the corresponding set signal (setx for horizontal
-- position, sety for vertical position, setmax_x for horizontal
-- maximum value, setmax_y for the veritcal maximum value).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- clk - global clock signal
-- rst - reset signal
-- resolution - input pin, from resolution_switcher
-- - 0 for 640x480 selected resolution
-- - 1 for 800x600 selected resolution
-- switch - input pin, from resolution_switcher
-- - active for one clock period when resolution changes
-- value - output pin, 10 bits, to mouse_controller
-- - position on x or y, max value for x or y
-- - that is sent to the mouse_controller
-- setx - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - position of the mouse cursor is valid on value output
-- sety - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - position of the mouse cursor is valid on value output
-- setmax_x - output pin, to mouse_controller
-- - active for one clock period when the horizontal
-- - maximum position of the mouse cursor is valid on
-- - value output
-- setmax_y - output pin, to mouse_controller
-- - active for one clock period when the vertical
-- - maximum position of the mouse cursor is valid on
-- - value output
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the resolution_mouse_informer entity declaration
-- read above for behavioral description and port definitions.
entity resolution_mouse_informer is
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end resolution_mouse_informer;
architecture Behavioral of resolution_mouse_informer is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- center horizontal position of the mouse for 640x480 and 800x600
constant POS_X_640: std_logic_vector(9 downto 0) := "0101000000"; -- 320
constant POS_X_800: std_logic_vector(9 downto 0) := "0110010000"; -- 400
-- center vertical position of the mouse for 640x480 and 800x600
constant POS_Y_640: std_logic_vector(9 downto 0) := "0011110000"; -- 240
constant POS_Y_800: std_logic_vector(9 downto 0) := "0100101100"; -- 300
-- maximum horizontal position of the mouse for 640x480 and 800x600
constant MAX_X_640: std_logic_vector(9 downto 0) := "1001111111"; -- 639
constant MAX_X_800: std_logic_vector(9 downto 0) := "1100011111"; -- 799
-- maximum vertical position of the mouse for 640x480 and 800x600
constant MAX_Y_640: std_logic_vector(9 downto 0) := "0111011111"; -- 479
constant MAX_Y_800: std_logic_vector(9 downto 0) := "1001010111"; -- 599
constant RES_640 : std_logic := '0';
constant RES_800 : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
type fsm_state is (sReset,sIdle,sSetX,sSetY,sSetMaxX,sSetMaxY);
-- signal that holds the current state of the FSM
signal state: fsm_state := sIdle;
begin
-- value receives the horizontal position of the mouse, the vertical
-- position, the maximum horizontal value and maximum vertical
-- value for the active resolution when in the apropriate state
value <= POS_X_640 when state = sSetX and resolution = RES_640 else
POS_X_800 when state = sSetX and resolution = RES_800 else
POS_Y_640 when state = sSetY and resolution = RES_640 else
POS_Y_800 when state = sSetY and resolution = RES_800 else
MAX_X_640 when state = sSetMaxX and resolution = RES_640 else
MAX_X_800 when state = sSetMaxX and resolution = RES_800 else
MAX_Y_640 when state = sSetMaxY and resolution = RES_640 else
MAX_Y_800 when state = sSetMaxY and resolution = RES_800 else
(others => '0');
-- when in state sSetX, set the horizontal value for the mouse
setx <= '1' when state = sSetX else '0';
-- when in state sSetY, set the vertical value for the mouse
sety <= '1' when state = sSetY else '0';
-- when in state sSetMaxX, set the horizontal max value for the mouse
setmax_x <= '1' when state = sSetMaxX else '0';
-- when in state sSetMaxX, set the vertical max value for the mouse
setmax_y <= '1' when state = sSetMaxY else '0';
-- when a resolution switch occurs (even to the same resolution)
-- leave the idle state
-- if just powered up or reset occures go to reset state and
-- from there set the position and bounds for the mouse
manage_fsm: process(clk,rst)
begin
if(rst = '1') then
state <= sReset;
elsif(rising_edge(clk)) then
case state is
-- when reset occurs (or power-up) set the position
-- and bounds for the mouse.
when sReset =>
state <= sSetX;
-- remain in idle while switch is not active.
when sIdle =>
if(switch = '1') then
state <= sSetX;
else
state <= sIdle;
end if;
when sSetX =>
state <= sSetY;
when sSetY =>
state <= sSetMaxX;
when sSetMaxX =>
state <= sSetMaxY;
when sSetMaxY =>
state <= sIdle;
when others =>
state <= sIdle;
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
amof/fpga-pong
|
Pong.vhd
|
1
|
2365
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Entity Pong is
port
(
iCLK_50,iCLK_28 : IN std_logic;
iKEY : IN unsigned(3 downto 0);
oLEDR : OUT std_logic_vector(17 downto 0);
oVGA_B : OUT unsigned(9 downto 0);
oVGA_G : OUT unsigned(9 downto 0);
oVGA_R : OUT unsigned(9 downto 0);
oVGA_HS : OUT STD_LOGIC;
oVGA_VS : OUT STD_LOGIC;
oVGA_CLOCK : OUT STD_LOGIC;
oVGA_SYNC_N : OUT STD_LOGIC;
oVGA_BLANK_N : OUT STD_LOGIC
);
END Pong;
ARCHITECTURE ARCH OF Pong IS
SIGNAL UP, DOWN : STD_logic;
SIGNAL UPd, DOWNd : STD_logic;
SIGNAL RST_N, MCLK : STD_logic;
SIGNAL CPT : integer := 0;
SIGNAL clk_25MHz:std_LOGIC;
SIGNAL clk_25Hz:std_LOGIC;
SIGNAL Xcnt, Ycnt: INTEGER ;
----déclaration des composants BUTTONS et SEGMENTS
COMPONENT VGA PORT(
CLK_VGA : IN STD_LOGIC;
Hsync,Vsync : BUFFER STD_LOGIC;
BLANK,SYNC : BUFFER STD_LOGIC;
Xcnt, Ycnt : OUT INTEGER
);
END COMPONENT;
COMPONENT VGA_ctrl PORT(
VGA_R : OUT unsigned(9 downto 0);
VGA_B : OUT unsigned(9 downto 0);
VGA_G : OUT unsigned(9 downto 0);
UP, DOWN : IN STD_LOGIC;
UPd, DOWNd : IN STD_LOGIC;
PIX_X, PIX_Y : IN integer ;
MCLK : IN std_logic;
clk_ball:IN std_logic
);
END COMPONENT;
COMPONENT BUTTONS PORT
(
BOUTONS : IN unsigned(3 downto 0);
UP, DOWN : OUT STD_LOGIC;
UPd, DOWNd : OUT STD_LOGIC;
--------SYSTEMS signals
RST_N : IN STD_LOGIC;
MCLK : IN STD_LOGIC
);
END COMPONENT;
COMPONENT ClockPrescaler PORT
(
clk_25MHZ : OUT STD_LOGIC;
clk_25HZ : OUT STD_LOGIC;
--------SYSTEMS signals
RST_N : IN STD_LOGIC;
MCLK : IN STD_LOGIC
);
END COMPONENT;
begin
---instantiations composants
U0 : BUTTONS PORT MAP(iKEY, UP, DOWN, UPd, DOWNd, RST_N, MCLK);
U1 : VGA PORT MAP(clk_25MHz, oVGA_HS, oVGA_VS, oVGA_BLANK_N, oVGA_SYNC_N, Xcnt,Ycnt );
U2 : ClockPrescaler PORT MAP(clk_25MHz, clk_25Hz, RST_N, MCLK);
U3 : VGA_ctrl PORT MAP(oVGA_R, oVGA_B, oVGA_G, UP, DOWN, UPd, DOWNd, Xcnt, Ycnt, MCLK, clk_25Hz);
---affectation des signaux
MCLK<=iCLK_50;
oVGA_CLOCK<=clk_25MHz;
---créer le RST_N avec un process
PROCESS (MCLK)
BEGIN
IF rising_edge(MCLK) THEN
IF CPT < 1000 THEN
RST_N <= '0';
CPT <= CPT + 1;
oLEDR(0) <= '1';
ELSE
RST_N <= '1';
oLEDR(0) <= '0';
END IF;
END IF;
END PROCESS;
end ARCH;
|
gpl-3.0
|
zpekic/tinycomputer
|
tinycomputer.vhd
|
1
|
13958
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic ([email protected])
--
-- Create Date: 12:26:24 02/07/2016
-- Design Name:
-- Module Name: alarmclock - structural
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
-- Description: 12hr/24hr alarm clock with display dimming showcasing baseboard hardware
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tinycomputer is
port(
-- 50MHz on the Mercury board
CLK: in std_logic;
-- Master reset button on Mercury board
USR_BTN: in std_logic;
-- Switches on baseboard
-- SW3 .. SW0 == INP[0]
-- dimmer mode -- SW5 -- SW4 --
-- potentiometer on on
-- light sensor on off
-- temperature off on
-- on (max light) off off
-- debug mode -- SW6 -- SW5 --
-- none off off (display status 3..0)
-- none off on (display status 7..4)
-- program off off (display current program address and instruction and status 3..0)
-- internal on on (display instruction to Am2901 and i/o address and status 7..4)
-- clock mode -- SW7 --
-- slow off
-- fast on
-- also note that SW7 .. SW4 appear as INP[1]
-------------------------------
SW: in std_logic_vector(7 downto 0);
-- Push buttons on baseboard
-- hooked up as INPUT[3]
BTN: in std_logic_vector(3 downto 0);
-- Stereo audio output on baseboard, used to output sound if alarm is triggered
--AUDIO_OUT_L, AUDIO_OUT_R: out std_logic;
-- 7seg LED on baseboard to display debug or data (OUT[0] to OUT[3])
-- OUT[14] controls blanking of digits 3..0)
A_TO_G: out std_logic_vector(6 downto 0);
AN: out std_logic_vector(3 downto 0);
-- dot on digit 0 is lit up - PM if in 12hr mode
-- dot is extra 7seg display (OUT[15] controls lighting of dots 3..0)
DOT: out std_logic;
-- 4 LEDs on Mercury board
LED: out std_logic_vector(3 downto 0);
-- ADC interface
ADC_MISO: in std_logic;
ADC_MOSI: out std_logic;
ADC_SCK: out std_logic;
ADC_CSN: out std_logic;
-- PMOD interface (for hex keypad)
PMOD: inout std_logic_vector(7 downto 0)
);
end tinycomputer;
use work.clock_divider;
use work.mux16to4;
use work.mux32to16;
use work.fourdigitsevensegled;
use work.tinycpu;
use work.tinyrom;
use work.pwm10bit;
use work.PmodKYPD;
use work.debouncer;
architecture structural of tinycomputer is
component clock_divider is
Port ( reset : in STD_LOGIC;
clock : in STD_LOGIC;
div : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component mux16to4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC_VECTOR (3 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
nEnable : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component mux32to16 is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
sel : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component fourdigitsevensegled is
Port ( -- inputs
data : in STD_LOGIC_VECTOR (15 downto 0);
digsel : in STD_LOGIC_VECTOR (1 downto 0);
showdigit : in STD_LOGIC_VECTOR (3 downto 0);
showdot : in STD_LOGIC_VECTOR (3 downto 0);
showsegments : in STD_LOGIC;
-- outputs
anode : out STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component pwm10bit is
Port ( clk : in STD_LOGIC;
adc_samplingrate: in STD_LOGIC;
adc_channel : in STD_LOGIC_VECTOR (2 downto 0);
adc_miso : in std_logic; -- ADC SPI MISO
adc_mosi : out std_logic; -- ADC SPI MOSI
adc_cs : out std_logic; -- ADC SPI CHIP SELECT
adc_clk : out std_logic; -- ADC SPI CLOCK
adc_value: out std_logic_vector(15 downto 0);
adc_valid: out std_logic;
pwm_out : out STD_LOGIC);
end component;
component PmodKYPD is
Port (
clk : in STD_LOGIC;
reset: in STD_LOGIC;
bcdmode: in STD_LOGIC;
Col : out STD_LOGIC_VECTOR (3 downto 0);
Row : in STD_LOGIC_VECTOR (3 downto 0);
entry : out STD_LOGIC_VECTOR (15 downto 0);
key_code : out STD_LOGIC_VECTOR(3 downto 0);
key_down: out STD_LOGIC
);
end component;
component debouncer is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC);
end component;
component tinyrom is
Port ( address : in STD_LOGIC_VECTOR (9 downto 0);
data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component tinycpu is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
a : out STD_LOGIC_VECTOR (9 downto 0);
i : in STD_LOGIC_VECTOR (7 downto 0);
io_data : inout STD_LOGIC_VECTOR (3 downto 0);
nIo_read : buffer STD_LOGIC;
nIo_write : buffer STD_LOGIC;
io_address : out STD_LOGIC_VECTOR (3 downto 0);
status : out STD_LOGIC_VECTOR (7 downto 0);
step: in STD_LOGIC;
debug_port : out STD_LOGIC_VECTOR (15 downto 0));
end component;
-- output data register
type port16by4 is array (15 downto 0) of std_logic_vector(3 downto 0);
signal data_port: port16by4;
-- common signals
signal clock: std_logic;
signal reset: std_logic;
signal address_bus: std_logic_vector(9 downto 0);
signal instruction_bus: std_logic_vector(7 downto 0);
signal io_bus: std_logic_vector(3 downto 0);
signal nIo_read: std_logic;
signal nIo_write: std_logic;
signal io_address_bus: std_logic_vector(3 downto 0);
signal status_bus: std_logic_vector(7 downto 0);
signal debug_cpu: std_logic_vector(15 downto 0);
signal debug_bus: std_logic_vector(15 downto 0);
signal display_bus: std_logic_vector(15 downto 0);
-- other signals
signal freq: std_logic_vector(3 downto 0);
signal debug_enable: std_logic;
signal debug_rom: std_logic;
signal led4: std_logic_vector(3 downto 0);
signal pushbutton: std_logic_vector(3 downto 0);
signal key_buff: std_logic_vector(15 downto 0);
signal showdot: std_logic_vector(3 downto 0);
-- ADC
signal adc_valid: std_logic;
signal adc_value: std_logic_vector(15 downto 0);
signal adc_ready: std_logic;
signal adc_output: std_logic_vector(19 downto 0);
-- dimmer
signal freq16, freq32, freq64, freq128: std_logic; -- use either to drive dimmer sample rate, keyboard etc.
signal led_dimmer: std_logic;
signal adc_to_pwm: std_logic;
signal adc_channel: std_logic_vector(2 downto 0);
-- kbd
signal key_code: std_logic_vector(3 downto 0);
signal key_down: std_logic;
begin
-- common signals
reset <= USR_BTN;
clock <= (SW(7) and freq128) or ((not SW(7)) and freq(3));
debug_enable <= SW(6);
debug_rom <= SW(5);
-- CPU
tcpu: tinycpu port map
(
clock => clock,
reset => reset,
a => address_bus,
i => instruction_bus,
io_data => io_bus,
nIo_read => nIo_read,
nIo_write => nIo_write,
io_address => io_address_bus,
status => status_bus,
step => pushbutton(3),
debug_port => debug_cpu
);
-- PROGRAM ROM
trom: tinyrom port map
(
address => address_bus,
data => instruction_bus
);
-- Port I/O
input_mux: mux16to4 port map (
a => SW(3 downto 0),
b => SW(7 downto 4),
c => x"2",
d => pushbutton,
nEnable => nIo_read,
sel => io_address_bus(1 downto 0),
y => io_bus
);
write_port: process(reset, nio_write)
begin
if (reset = '1') then
data_port(0) <= x"f";
data_port(1) <= x"e";
data_port(2) <= x"e";
data_port(3) <= x"b";
-- turn on all digits
data_port(14) <= "1111";
-- turn on all dots
data_port(15) <= "1111";
else
if (rising_edge(nIo_write)) then
--if (nIo_write = '0') then
data_port(to_integer(unsigned(io_address_bus))) <= io_bus;
--end if;
end if;
end if;
end process;
-- DIMMER (the mux generates the mapping of 2 switches to 3 out of 8 possible channels and the PWM signal routing)
dimmer_mux: mux16to4 port map (
a => "1000", -- full light on, adc channel is ignored
b(3) => adc_to_pwm,
b(2 downto 0) => "010", -- measure TEMP (adc channel 2)
c(3) => adc_to_pwm, -- measure LIGHT (adc channel 3)
c(2 downto 0) => "011", -- measure LIGHT (adc channel 3)
d(3) => adc_to_pwm, -- measure POT (adc channel 4)
d(2 downto 0) => "100", -- measure POT (adc channel 4)
nEnable => '0',
sel => SW(5 downto 4),
y(3) => led_dimmer,
y(2 downto 0) => adc_channel(2 downto 0)
);
-- FREQUENCY GENERATOR
one_sec: clock_divider port map (
clock => CLK,
reset => reset,
div(7) => freq(3), -- 1Hz
div(6) => freq(2), -- 2Hz
div(5) => freq(1), -- 4Hz
div(4) => freq(0), -- 8Hz
div(3) => freq16, -- 16Hz
div(2) => freq32, -- 32Hz
div(1) => freq64, -- 64Hz
div(0) => freq128 -- 128Hz
);
-- connect to 4 display LEDs
muxled: mux16to4 port map (
a => status_bus(3 downto 0), -- NVZC (status low nibble)
b => status_bus(7 downto 4), -- SS E B X (status high nibble)
c => status_bus(3 downto 0), -- NVZC (status low nibble)
d => status_bus(7 downto 4), -- SS E B X (status high nibble)
--c(3) => '1', -- debug io
--c(2) => '1',
--c(1) => nIo_Read,
--c(0) => nIo_Write,
--d(3) => '1', -- debug io
--d(2) => '1',
--d(1) => nIo_Read,
--d(0) => nIo_Write,
y => led4,
nEnable => '0',
sel(1) => debug_enable,
sel(0) => debug_rom
);
-- dim the LEDs just like the 7seg display
LED(3) <= adc_to_pwm and led4(0);
LED(2) <= adc_to_pwm and led4(1);
LED(1) <= adc_to_pwm and led4(2);
LED(0) <= adc_to_pwm and led4(3);
-- DEBUG MUX
debugmux: mux32to16 port map
(
a => debug_cpu,
b(15 downto 8) => address_bus(7 downto 0),
b(7 downto 0) => instruction_bus,
sel => debug_rom,
y => debug_bus
);
-- MAIN DISPLAY MUX
dispmux: mux32to16 port map (
a(3 downto 0) => data_port(0),
a(7 downto 4) => data_port(1),
a(11 downto 8) => data_port(2),
a(15 downto 12) => data_port(3),
b => debug_bus,
sel => debug_enable,
y => display_bus
);
-- use dots on 4 seven-seg displays to indicate single step mode by flashing
dotmux: mux16to4 port map (
a => data_port(15),
b => data_port(15),
c => "0101",
d => "1010",
sel(1) => status_bus(7),
sel(0) => freq(2),
nEnable => '0',
y => showdot
);
-- display on 4 seven-seg displays
display: fourdigitsevensegled port map (
data => display_bus,
digsel(1) => freq128,
digsel(0) => freq64,
showsegments => led_dimmer,
showdigit => data_port(14),
showdot => showdot, --data_port(15),
anode => AN,
segment(7) => DOT,
segment(6 downto 0) => A_TO_G
);
-- DIMMER converts ADC channel signal to pulse-width-modulated one to use for displays
dimmer: pwm10bit Port map
( clk => CLK,
adc_samplingrate => freq64, -- 64Hz sampling rate
adc_miso => ADC_MISO, -- ADC SPI MISO
adc_mosi => ADC_MOSI, -- ADC SPI MOSI
adc_cs => ADC_CSN, -- ADC SPI CHIP SELECT
adc_clk => ADC_SCK, -- ADC SPI CLOCK
adc_channel => adc_channel, -- select light (011) or potentiometer (100)
adc_value => adc_value,
adc_valid => adc_valid,
pwm_out => adc_to_pwm
);
-- Capture ADC reading for display
--capture_adc: process(adc_ready)
--begin
-- if (rising_edge(adc_ready)) then
-- debug16 <= adc_output(15 downto 0);
-- end if;
--end process;
-- KEYBOARD
kbd: PmodKYPD Port map
( clk => freq64, -- 64Hz, means each key is sampled at 4Hz rate (64/16)
reset => reset,
bcdmode => SW(4),
Col(3) => PMOD(0),
Col(2) => PMOD(1),
Col(1) => PMOD(2),
Col(0) => PMOD(3),
Row(3) => PMOD(4),
Row(2) => PMOD(5),
Row(1) => PMOD(6),
Row(0) => PMOD(7),
entry => key_buff,
key_code => key_code,
key_down => key_down
);
-- DEBOUNCE the 4 push buttons
d0: debouncer port map (
reset => reset,
clock => freq128,
signal_in => BTN(0),
signal_out => pushbutton(0)
);
d1: debouncer port map (
reset => reset,
clock => freq128,
signal_in => BTN(1),
signal_out => pushbutton(1)
);
d2: debouncer port map (
reset => reset,
clock => freq128,
signal_in => BTN(2),
signal_out => pushbutton(2)
);
d3: debouncer port map (
reset => reset,
clock => freq128,
signal_in => BTN(3),
signal_out => pushbutton(3)
);
end structural;
|
gpl-3.0
|
zpekic/tinycomputer
|
fourdigitsevensegled.vhd
|
1
|
3558
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic ([email protected])
--
-- Create Date: 15:42:44 02/20/2016
-- Design Name:
-- Module Name: fourdigitsevensegled - Behavioral
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fourdigitsevensegled is
Port ( -- inputs
data : in STD_LOGIC_VECTOR (15 downto 0);
digsel : in STD_LOGIC_VECTOR (1 downto 0);
showdigit : in STD_LOGIC_VECTOR (3 downto 0);
showdot : in STD_LOGIC_VECTOR (3 downto 0);
showsegments : in STD_LOGIC;
-- outputs
anode : out STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (7 downto 0)
);
end fourdigitsevensegled;
architecture structural of fourdigitsevensegled is
component nibble2sevenseg is
Port ( nibble : in STD_LOGIC_VECTOR (3 downto 0);
segment : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
component mux16to4
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
c : in STD_LOGIC_VECTOR (3 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
nEnable : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
signal internalsegment: std_logic_vector(7 downto 0); -- 7th is the dot!
signal internalsel: std_logic_vector(3 downto 0);
signal digit: std_logic_vector(3 downto 0);
begin
-- decode position
internalsel(3) <= digsel(1) and digsel(0);
internalsel(2) <= digsel(1) and (not digsel(0));
internalsel(1) <= (not digsel(1)) and digsel(0);
internalsel(0) <= (not digsel(1)) and (not digsel(0));
-- select 1 digit out of 4 incoming
digitmux: mux16to4 port map (
a => data(3 downto 0),
b => data(7 downto 4),
c => data(11 downto 8),
d => data(15 downto 12),
nEnable => '0',
sel => digsel,
y => digit
);
-- set the anodes with digit blanking
anode(3) <= not (internalsel(3) and showdigit(3));
anode(2) <= not (internalsel(2) and showdigit(2));
anode(1) <= not (internalsel(1) and showdigit(1));
anode(0) <= not (internalsel(0) and showdigit(0));
-- hook up the cathodes
sevensegdriver: nibble2sevenseg port map (
nibble => digit,
segment => internalsegment(6 downto 0)
);
-- set cathodes with blanking (seg7 == dot)
segment(7) <= (not showsegments) or ((internalsel(3) and not showdot(3)) or (internalsel(2) and not showdot(2)) or (internalsel(1) and not showdot(1)) or (internalsel(0) and not showdot(0)));
segs: for i in 6 downto 0 generate
segment(i) <= (not showsegments) or internalsegment(i);
end generate;
end structural;
|
gpl-3.0
|
zpekic/tinycomputer
|
bin2bcd.vhd
|
1
|
4710
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:21:44 11/15/2016
-- Design Name:
-- Module Name: bin2bcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bin2bcd is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
bcd_mode : in STD_LOGIC;
input_ready : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output_ready : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (19 downto 0);
debug: out STD_LOGIC_VECTOR(3 downto 0)
);
end bin2bcd;
architecture fsm of bin2bcd is
component bcdadder is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
type state is (st_reset, st_ready, st_start, st_sync, st_busy, st_done);
signal current_state, next_state: state;
signal c0, c1, c2, c3: std_logic;
--signal val_mux: std_logic;
signal shifter: std_logic_vector(15 downto 0);
signal rom_mux, bcd_accu, bcd_val: std_logic_vector(19 downto 0);
signal counter: std_logic_vector(4 downto 0);
type rom16x20 is array (0 to 15) of std_logic_vector(19 downto 0);
constant powersof2: rom16x20 := (
X"00001",
X"00002",
X"00004",
X"00008",
X"00016",
X"00032",
X"00064",
X"00128",
X"00256",
X"00512",
X"01024",
X"02048",
X"04096",
X"08192",
X"16384",
X"32767");
begin
debug(3) <= '1' when (current_state = st_ready) else '0';
debug(2) <= '1' when (current_state = st_start) else '0';
debug(1) <= '1' when (current_state = st_busy) else '0';
debug(0) <= '1' when (current_state = st_done) else '0';
output <= bcd_accu when (bcd_mode = '1') else X"0" & input;
output_ready <= '1' when ((bcd_mode = '1' and current_state = st_done) or (bcd_mode = '0' and input_ready = '1')) else '0';
rom_mux <= powersof2(to_integer(unsigned(counter(4 downto 1)))) when shifter(0) = '1' else X"00000";
-- hook up BCD adders with ripple carry
a0: bcdadder port map (
a => rom_mux(3 downto 0),
b => bcd_accu(3 downto 0),
cin => '0',
sum => bcd_val(3 downto 0),
cout => c0
);
a1: bcdadder port map (
a => rom_mux(7 downto 4),
b => bcd_accu(7 downto 4),
cin => c0,
sum => bcd_val(7 downto 4),
cout => c1
);
a2: bcdadder port map (
a => rom_mux(11 downto 8),
b => bcd_accu(11 downto 8),
cin => c1,
sum => bcd_val(11 downto 8),
cout => c2
);
a3: bcdadder port map (
a => rom_mux(15 downto 12),
b => bcd_accu(15 downto 12),
cin => c2,
sum => bcd_val(15 downto 12),
cout => c3
);
a4: bcdadder port map (
a => rom_mux(19 downto 16),
b => bcd_accu(19 downto 16),
cin => c3,
sum => bcd_val(19 downto 16)
--cout => NC
);
fsm_lower: process(clk, reset, input)
begin
if (reset = '1') then
current_state <= st_reset;
else
if (rising_edge(clk)) then
counter <= std_logic_vector(unsigned(counter) + 1);
current_state <= next_state;
if (current_state = st_start) then
bcd_accu <= X"00000";
shifter <= input;
end if;
if (current_state = st_busy and counter(0) = '1') then
bcd_accu <= bcd_val;
end if;
if (current_state = st_busy and counter(0) = '1') then
shifter <= '0' & shifter(15 downto 1);
end if;
end if;
end if;
end process;
fsm_upper: process(current_state, input_ready, counter)
begin
case current_state is
when st_reset =>
next_state <= st_ready;
when st_ready =>
if (input_ready = '1') then
next_state <= st_start;
else
next_state <= st_ready;
end if;
when st_start =>
next_state <= st_sync;
when st_sync =>
if (counter = "11111") then
next_state <= st_busy;
else
next_state <= st_sync;
end if;
when st_busy =>
if (shifter = X"0000") then
next_state <= st_done;
else
next_state <= st_busy;
end if;
when st_done =>
next_state <= st_ready;
end case;
end process;
end fsm;
|
gpl-3.0
|
zpekic/tinycomputer
|
pwm10bit.vhd
|
1
|
3810
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic ([email protected])
--
-- Create Date: 01:57:47 02/27/2016
-- Design Name:
-- Module Name: pwm10bit - Behavioral
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
--
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm10bit is
Port ( clk : in STD_LOGIC;
adc_samplingrate: in STD_LOGIC;
adc_channel : in STD_LOGIC_VECTOR (2 downto 0);
adc_miso : in std_logic; -- ADC SPI MISO
adc_mosi : out std_logic; -- ADC SPI MOSI
adc_cs : out std_logic; -- ADC SPI CHIP SELECT
adc_clk : out std_logic; -- ADC SPI CLOCK
adc_value: out std_logic_vector(15 downto 0);
adc_valid: out std_logic;
pwm_out : out STD_LOGIC);
end pwm10bit;
-- From http://www.micro-nova.com/resources/
use work.MercuryADC;
architecture Behavioral of pwm10bit is
component MercuryADC is
port
(
-- command input
clock : in std_logic; -- 50MHz onboard oscillator
trigger : in std_logic; -- assert to sample ADC
diffn : in std_logic; -- single/differential inputs
channel : in std_logic_vector(2 downto 0); -- channel to sample
-- data output
Dout : out std_logic_vector(9 downto 0); -- data from ADC
OutVal : out std_logic; -- pulsed when data sampled
-- ADC connection
adc_miso : in std_logic; -- ADC SPI MISO
adc_mosi : out std_logic; -- ADC SPI MOSI
adc_cs : out std_logic; -- ADC SPI CHIP SELECT
adc_clk : out std_logic -- ADC SPI CLOCK
);
end component;
signal threshold: integer range 0 to 1023 := 0;
signal counter: integer range 0 to 1023 := 0;
signal adc_out: std_logic_vector(9 downto 0);
signal adc_pulse: std_logic;
begin
-- map to output and extend to 16 bits
adc_value <= "000000" & adc_out;
adc_valid <= adc_pulse;
adc: MercuryADC port map
(
-- command input
clock => clk, -- from onboard oscillator
trigger => adc_samplingrate, -- assert to sample ADC
diffn => '1', -- single/differential inputs
channel => adc_channel, -- channel to sample (3 == light sensor)
-- data output
Dout => adc_out, -- data from ADC
OutVal => adc_pulse, -- pulsed when data sampled
-- ADC connection
adc_miso => adc_miso, -- ADC SPI MISO
adc_mosi => adc_mosi, -- ADC SPI MOSI
adc_cs => adc_cs, -- ADC SPI CHIP SELECT
adc_clk => adc_clk -- ADC SPI CLOCK
);
get_adc: process(adc_pulse)
begin
if (adc_pulse = '1') then
threshold <= to_integer(unsigned(adc_out));
end if;
end process;
generate_pwm: process(clk)
begin
if (clk'event and clk = '1') then
counter <= counter + 1; -- just let it wrap around
if (counter > threshold) then
pwm_out <= '0';
else
pwm_out <= '1';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
zpekic/tinycomputer
|
hourminbcd.vhd
|
1
|
3999
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic ([email protected])
--
-- Create Date: 20:49:24 02/20/2016
-- Design Name:
-- Module Name: hourminbcd - structural
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hourminbcd is
Port ( reset : in STD_LOGIC;
sync : in STD_LOGIC;
pulse: in STD_LOGIC;
set_hr : in STD_LOGIC;
set_min : in STD_LOGIC;
set_inc : in STD_LOGIC;
set_dec : in STD_LOGIC;
key_code : in STD_LOGIC_VECTOR(3 downto 0);
key_hit : in STD_LOGIC;
bcdout : out STD_LOGIC_VECTOR (15 downto 0);
debug: out STD_LOGIC_VECTOR(3 downto 0)
);
end hourminbcd;
use work.counterwithlimit;
architecture structural of hourminbcd is
component bcd_counter is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
set : in STD_LOGIC;
inc : in STD_LOGIC;
dec : in STD_LOGIC;
maxval : in STD_LOGIC_VECTOR (7 downto 0);
setval : in STD_LOGIC_VECTOR (3 downto 0);
is_zero : out STD_LOGIC;
is_maxval : out STD_LOGIC;
bcd : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal sync_min, inc_min, dec_min, maxval_min, zero_min: std_logic;
signal sync_hr, inc_hr, dec_hr: std_logic;
signal min_key, min_up, min_down: std_logic;
signal hour_key, hour_up, hour_down: std_logic;
begin
condition_signals: process(sync)
begin
if (falling_edge(sync)) then
-- filter out defined button combinations for setting minutes
min_key <= (not set_hr) and set_min and (not set_inc) and (not set_dec);
min_up <= (not set_hr) and set_min and set_inc and (not set_dec);
min_down <= (not set_hr) and set_min and (not set_inc) and set_dec;
-- filter out defined button combinations for setting minutes
hour_key <= set_hr and (not set_min) and (not set_inc) and (not set_dec);
hour_up <= set_hr and (not set_min) and set_inc and (not set_dec);
hour_down <= set_hr and (not set_min) and (not set_inc) and set_dec;
end if;
end process;
-- drive minute digits
sync_min <= (min_key and key_hit) or ((not min_key) and sync);
inc_min <= min_up or ((not min_up) and pulse);
dec_min <= min_down;
-- drive hour digits
sync_hr <= (hour_key and key_hit) or ((not hour_key) and sync);
inc_hr <= hour_up or ((not hour_up) and maxval_min and pulse);
dec_hr <= hour_down;
-- debug signals
debug(3) <= inc_min;
debug(2) <= dec_min;
debug(1) <= sync_min;
debug(0) <= sync;
min: bcd_counter port map (
reset => reset,
clk => sync_min,
set => min_key,
inc => inc_min,
dec => dec_min,
maxval => X"59",
setval => key_code,
is_zero => zero_min,
is_maxval => maxval_min,
bcd => bcdout(7 downto 0)
);
hour: bcd_counter port map (
reset => reset,
clk => sync_hr,
set => hour_key,
inc => inc_hr,
dec => dec_hr,
maxval => X"23",
setval => key_code,
--is_zero => debug(2),
--is_maxval => debug(3),
bcd => bcdout(15 downto 8)
);
end structural;
|
gpl-3.0
|
zpekic/tinycomputer
|
aclock.vhd
|
1
|
7277
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:36:33 03/06/2016
-- Design Name:
-- Module Name: aclock - structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aclock is
Port ( reset : in STD_LOGIC;
onehertz: in STD_LOGIC;
select_alarm: in STD_LOGIC;
enable_alarm: in STD_LOGIC;
select_12hr: in STD_LOGIC;
enable_set: in STD_LOGIC;
set_hr: in STD_LOGIC;
set_min: in STD_LOGIC;
set_inc: in STD_LOGIC;
set_dec: in STD_LOGIC;
key_code : in STD_LOGIC_VECTOR(3 downto 0);
key_hit : in STD_LOGIC;
hrmin_bcd : out STD_LOGIC_VECTOR (15 downto 0);
is_pm: out STD_LOGIC;
alarm_active : out STD_LOGIC;
debug_port: out STD_LOGIC_VECTOR(3 downto 0));
end aclock;
use work.hourminbcd;
use work.comparatorwithstate;
use work.counterwithlimit;
use work.mux32to16;
architecture structural of aclock is
component bcd_counter is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
set : in STD_LOGIC;
inc : in STD_LOGIC;
dec : in STD_LOGIC;
maxval : in STD_LOGIC_VECTOR (7 downto 0);
setval : in STD_LOGIC_VECTOR (3 downto 0);
is_zero : out STD_LOGIC;
is_maxval : out STD_LOGIC;
bcd : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component counterwithlimit is
Port ( clock : in STD_LOGIC;
clear : in STD_LOGIC;
up : in STD_LOGIC;
down : in STD_LOGIC;
set: in STD_LOGIC;
limit : in STD_LOGIC_VECTOR (3 downto 0);
out_count : out STD_LOGIC_VECTOR (3 downto 0);
out_zero : out STD_LOGIC;
out_limit : out STD_LOGIC
);
end component;
component hourminbcd is
Port ( reset : in STD_LOGIC;
sync : in STD_LOGIC;
pulse: in STD_LOGIC;
set_hr : in STD_LOGIC;
set_min : in STD_LOGIC;
set_inc : in STD_LOGIC;
set_dec : in STD_LOGIC;
key_code : in STD_LOGIC_VECTOR(3 downto 0);
key_hit : in STD_LOGIC;
bcdout : out STD_LOGIC_VECTOR (15 downto 0);
debug: out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
component comparatorwithstate is
Port ( a : in STD_LOGIC_VECTOR (23 downto 0);
b : in STD_LOGIC_VECTOR (23 downto 0);
clock: in STD_LOGIC;
reset : in STD_LOGIC;
enable: in STD_LOGIC;
trigger : out STD_LOGIC
);
end component;
component mux32to16
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component converter24to12
Port ( select_12hr : in STD_LOGIC;
hour24 : in STD_LOGIC_VECTOR (7 downto 0);
hour_ispm : out STD_LOGIC;
hour_12or24 : out STD_LOGIC_VECTOR (7 downto 0));
end component;
-- common
signal mode_clock: std_logic;
signal resetbuzzer: std_logic;
signal minup: std_logic;
signal key_mode: std_logic;
signal resetseconds: std_logic;
signal hr24_bcd: std_logic_vector(7 downto 0);
-- seconds
signal secvalue: std_logic_vector(7 downto 0);
-- clock
signal clock_bcd: std_logic_vector(15 downto 0);
signal clock_ispm: std_logic;
signal clock_set_hr, clock_set_min, clock_set_inc, clock_set_dec: std_logic;
signal debug_clock: std_logic_vector(3 downto 0);
-- alarm
signal alarm_bcd: std_logic_vector(15 downto 0);
signal alarm_ispm: std_logic;
signal alarm_set_hr, alarm_set_min, alarm_set_inc, alarm_set_dec: std_logic;
signal debug_alarm: std_logic_vector(3 downto 0);
begin
resetbuzzer <= reset or set_hr or set_min or set_inc or set_dec; -- any button push should kill the alarm
resetseconds <= reset or set_min; -- when setting minutes, keep seconds at 0
-- enable clock
clock_set_hr <= enable_set and set_hr and (not select_alarm);
clock_set_min <= enable_set and set_min and (not select_alarm);
clock_set_inc <= enable_set and set_inc and (not select_alarm);
clock_set_dec <= enable_set and set_dec and (not select_alarm);
-- enable alarm
alarm_set_hr <= enable_set and set_hr and select_alarm;
alarm_set_min <= enable_set and set_min and select_alarm;
alarm_set_inc <= enable_set and set_inc and select_alarm;
alarm_set_dec <= enable_set and set_dec and select_alarm;
-- DEBUG
debug_port <= debug_alarm when select_alarm = '1' else debug_clock;
-- SECONDS
sec: bcd_counter port map (
reset => resetseconds,
clk => onehertz,
set => '0',
inc => '1',
dec => '0',
maxval => X"59",
setval => X"0",
is_maxval => minup,
bcd => secvalue
);
-- CLOCK
clock: hourminbcd port map (
reset => reset,
sync => onehertz,
pulse => minup,
set_hr => clock_set_hr,
set_min => clock_set_min,
set_inc => clock_set_inc,
set_dec => clock_set_dec,
key_code => key_code,
key_hit => key_hit,
bcdout => clock_bcd,
debug => debug_clock
);
-- ALARM
alarm: hourminbcd port map (
reset => reset,
sync => onehertz,
pulse => '0',
set_hr => alarm_set_hr,
set_min => alarm_set_min,
set_inc => alarm_set_inc,
set_dec => alarm_set_dec,
key_code => key_code,
key_hit => key_hit,
bcdout => alarm_bcd,
debug => debug_alarm
);
-- COMPARATOR
buzzer: comparatorwithstate port map (
a(23 downto 8) => clock_bcd,
a(7 downto 0) => secvalue,
b(23 downto 8) => alarm_bcd,
b(7 downto 0) => "00000000",
clock => onehertz, -- check for alarm every sec, to make sure it is triggered as minute starts
reset => resetbuzzer,
enable => enable_alarm,
trigger => alarm_active
);
-- OUTPUT
mux: mux32to16 port map (
a => clock_bcd,
b => alarm_bcd,
y(7 downto 0) => hrmin_bcd(7 downto 0), -- minutes are displayed directly
y(15 downto 8) => hr24_bcd(7 downto 0), -- hours go through optional 24 to 12am/pm conversion
s => select_alarm
);
convert2ampm: converter24to12 port map (
select_12hr => select_12hr,
hour24 => hr24_bcd(7 downto 0),
hour_ispm => is_pm,
hour_12or24 => hrmin_bcd(15 downto 8)
);
end structural;
|
gpl-3.0
|
makestuff/readback
|
vhdl/harness.vhdl
|
1
|
2243
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdram is
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- DVR interface -----------------------------------------------------------------------------
--chanAddr_in : in std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_in : in std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_in : in std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
h2fReady_out : out std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_out : out std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_out : out std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_in : in std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- SDRAM interface ---------------------------------------------------------------------------
ramCmd_out : out std_logic_vector(2 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end entity;
|
gpl-3.0
|
makestuff/readback
|
templates/fx2all-ex/vhdl/aes220.vhdl
|
1
|
2918
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.1
-- \ \ Application : xaw2vhdl
-- / / Filename : clk_gen.vhd
-- /___/ /\ Timestamp : 03/19/2013 22:48:11
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st /home/chris/build/makestuff/libs/libfpgalink/hdl/apps/makestuff/readback/vhdl/x3/./clk_gen.xaw /home/chris/build/makestuff/libs/libfpgalink/hdl/apps/makestuff/readback/vhdl/x3/./clk_gen
--Design Name: clk_gen
--Device: xc3s200a-4ft256
--
-- Module clk_gen
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clk_gen is
port ( clk_in : in std_logic;
clk000_out : out std_logic;
clk180_out : out std_logic;
locked_out : out std_logic);
end clk_gen;
architecture BEHAVIORAL of clk_gen is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal CLK180_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
clk000_out <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>clk_in,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLK180_BUFG_INST : BUFG
port map (I=>CLK180_BUF,
O=>clk180_out);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.833,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>CLK180_BUF,
CLK270=>open,
LOCKED=>locked_out,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/PSelect/PSelect_funcsim.vhdl
|
1
|
603791
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:30:51 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/PSelect/PSelect_funcsim.vhdl
-- Design : PSelect
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end PSelect_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of PSelect_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => addra(9 downto 0),
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"000000000000000000BBBB888844447777666666667777000000000000000000",
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INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"7F0FE0007F0FE0007F00FFFF7F00FFFF7F00FFFF7F00FFFF0000000000000000",
INIT_13 => X"7F00FFFC7F00FFFC7F0FE0007F0FE0007F0FE0007F0FE0007F0FE0007F0FE000",
INIT_14 => X"F800003FF800003F7F00003F7F00003F7F00003F7F00003F7F00FFFC7F00FFFC",
INIT_15 => X"0000000000000000800FFFFC800FFFFC800FFFFC800FFFFCF800003FF800003F",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000111111111111111111111111000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"00001FC000001FC000001FC000001FC000001FC000001FC00000000000000000",
INIT_13 => X"00001FC000001FC000001FC000001FC000001FC000001FC000001FC000001FC0",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"4CCCC44444444000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000044444444444444444444444",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0FFE000000FE000000FE000000FE000000FE0000000000000000000000000000",
INIT_07 => X"00FE0000FFFE0000FFFE0000FFFE0000FFFE00000FFE00000FFE00000FFE0000",
INIT_08 => X"00FE000000FE000000FE000000FE000000FE000000FE000000FE000000FE0000",
INIT_09 => X"00FE000000FE000000FE000000FE000000FE000000FE000000FE000000FE0000",
INIT_0A => X"0000000000FE000000FE000000FE000000FE000000FE000000FE000000FE0000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000007000000070000000700000007000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"555555555FFFF000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000DDDD5555555555557777555",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"00FE03F8C0FFFF80C0FFFF80C0FFFF80C0FFFF80000000000000000000000000",
INIT_07 => X"00FE03F800FE03F800FE03F800FE03F800FE03F800FE03F800FE03F800FE03F8",
INIT_08 => X"00FE3F8000FFFF8000FFFF8000FFFF8000FFFF8000FE03F800FE03F800FE03F8",
INIT_09 => X"00FE03F800FE03F800FE03F800FE03F800FE03F800FE3F8000FE3F8000FE3F80",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"AAAAAAAAABBBB000000000000000000000000000000000000000000000000000",
INITP_01 => X"000000000000000000000000000000000000000003333222222222222BBBBAAA",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"000000000000000000000555566666666EEEE666666666666AAAA99990000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"FE07F000FE07FFFFFE07FFFFFE07FFFFFE07FFFF000000000000000000000000",
INIT_07 => X"FE07F000FE07F000FE07F000FE07F000FE07F000FE07F000FE07F000FE07F000",
INIT_08 => X"0007F000E007FFFEE007FFFEE007FFFEE007FFFEFE07F000FE07F000FE07F000",
INIT_09 => X"0007F0000007F0000007F0000007F0000007F0000007F0000007F0000007F000",
INIT_0A => X"000000000007FFFF0007FFFF0007FFFF0007FFFF0007F0000007F0000007F000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"80007FFF00000000000000000000000000000000000000000000000000000000",
INIT_39 => X"7F03F80FF803F80FF803F80FF803F80FF803F80F80007FFF80007FFF80007FFF",
INIT_3A => X"7F03F8007F03F8007F03F8007F03F8007F03F8007F03F80F7F03F80F7F03F80F",
INIT_3B => X"7F03F80FFF03F800FF03F800FF03F800FF03F8007F03F8007F03F8007F03F800",
INIT_3C => X"7F007FFF7F03F80F7F03F80F7F03F80F7F03F80F7F03F80F7F03F80F7F03F80F",
INIT_3D => X"00000000000000000000000000000000000000007F007FFF7F007FFF7F007FFF",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"55555DDDD9999000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000444444444444CCCC5555555",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"000000000000000000000DDDD555555555555DDDD555555555555CCCC0000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"FF007F00F8007F00F8007F00F8007F00F8007F00000000000000000000000000",
INIT_07 => X"07F07F0007F07F0007F07F0007F07F0007F07F00FF007F00FF007F00FF007F00",
INIT_08 => X"FFF000FF07F007FF07F007FF07F007FF07F007FF07F07F0007F07F0007F07F00",
INIT_09 => X"07F000FF07F000FF07F000FF07F000FF07F000FFFFF000FFFFF000FFFFF000FF",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"9999988888888000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000FFFF9999999999999999999",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"E000003FE0000003E0000003E0000003E0000003000000000000000000000000",
INIT_07 => X"E00001FCE00001FCE00001FCE00001FCE00001FCE000003FE000003FE000003F",
INIT_08 => X"E00001FFE00001FCE00001FCE00001FCE00001FCE00001FCE00001FCE00001FC",
INIT_09 => X"E00001FCE00001FCE00001FCE00001FCE00001FCE00001FFE00001FFE00001FF",
INIT_0A => X"00000000FFFF81FCFFFF81FCFFFF81FCFFFF81FCE00001FCE00001FCE00001FC",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"000000FF00000000000000000000000000000000000000000000000000000000",
INIT_39 => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3A => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3B => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3C => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3D => X"0000000000000000000000000000000000000000000000FF000000FF000000FF",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_08 => X"7F00000F7FFFE00F7FFFE00F7FFFE00F7FFFE00F7F00FE0F7F00FE0F7F00FE0F",
INIT_09 => X"7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F",
INIT_0A => X"000000007F00000F7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"2AAAAAAAA6666000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000EEEE8888444444442222222",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"FC07F0003FFF00003FFF00003FFF00003FFF0000000000000000000000000000",
INIT_07 => X"0007F000FC07F000FC07F000FC07F000FC07F000FC07F000FC07F000FC07F000",
INIT_08 => X"03F80000007F0000007F0000007F0000007F00000007F0000007F0000007F000",
INIT_09 => X"FC0000003F8000003F8000003F8000003F80000003F8000003F8000003F80000",
INIT_0A => X"00000000FFFFF000FFFFF000FFFFF000FFFFF000FC000000FC000000FC000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(30) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(29 downto 24) => douta(25 downto 20),
DOADO(23) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(22 downto 16) => douta(19 downto 13),
DOADO(15) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(14) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(13 downto 8) => douta(12 downto 7),
DOADO(7) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(6 downto 0) => douta(6 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(2) => \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(1) => \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(0) => \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000100000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000001000000010000000100000001000000010000000100000001",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000100000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000001000000010000000100000001000000010000000100000001",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"333333333BBBB000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000BBBB333333333333BBBB333",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000044444444000044444444CCCCCCCCCCCC44440000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"007F00FEF07FFFE0F07FFFE0F07FFFE0F07FFFE0000000000000000000000000",
INIT_07 => X"007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE",
INIT_08 => X"007F0FE0007FFFE0007FFFE0007FFFE0007FFFE0007F00FE007F00FE007F00FE",
INIT_09 => X"007F00FE007F00FE007F00FE007F00FE007F00FE007F0FE0007F0FE0007F0FE0",
INIT_0A => X"00000000F07F00FEF07F00FEF07F00FEF07F00FE007F00FE007F00FE007F00FE",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"6666666667777000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000BBBBAAAAAAAAAAAABBBB666",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000006666666666666666666666666666666666660000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"7F01FC007F01FFFF7F01FFFF7F01FFFF7F01FFFF000000000000000000000000",
INIT_07 => X"7F01FC007F01FC007F01FC007F01FC007F01FC007F01FC007F01FC007F01FC00",
INIT_08 => X"8001FC00F801FFFFF801FFFFF801FFFFF801FFFF7F01FC007F01FC007F01FC00",
INIT_09 => X"8001FC008001FC008001FC008001FC008001FC008001FC008001FC008001FC00",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"7F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE00",
INIT_3B => X"7F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE00",
INIT_3C => X"07FFE0007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE00",
INIT_3D => X"000000000000000000000000000000000000000007FFE00007FFE00007FFE000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_3B => X"01FC07F001FC7FF001FC7FF001FC7FF001FC7FF001FC000001FC000001FC0000",
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INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_06 => X"F800000FF8000000F8000000F8000000F8000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"5555555556666000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000044444444444444446666555",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"1FC07F031FFFF8031FFFF8031FFFF8031FFFF803000000000000000000000000",
INIT_07 => X"1FC07F031FC07F031FC07F031FC07F031FC07F031FC07F031FC07F031FC07F03",
INIT_08 => X"1FC000031FFFF8031FFFF8031FFFF8031FFFF8031FC07F031FC07F031FC07F03",
INIT_09 => X"1FC000031FC000031FC000031FC000031FC000031FC000031FC000031FC00003",
INIT_0A => X"000000001FC000031FC000031FC000031FC000031FC000031FC000031FC00003",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end PSelect_blk_mem_gen_prim_width;
architecture STRUCTURE of PSelect_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.PSelect_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(25 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end PSelect_blk_mem_gen_generic_cstr;
architecture STRUCTURE of PSelect_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.PSelect_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
\ramloop[10].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(377 downto 342)
);
\ramloop[11].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(413 downto 378)
);
\ramloop[12].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(449 downto 414)
);
\ramloop[13].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(485 downto 450)
);
\ramloop[14].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(521 downto 486)
);
\ramloop[15].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(557 downto 522)
);
\ramloop[16].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(593 downto 558)
);
\ramloop[17].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(629 downto 594)
);
\ramloop[18].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(665 downto 630)
);
\ramloop[19].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(701 downto 666)
);
\ramloop[1].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(53 downto 18)
);
\ramloop[20].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(737 downto 702)
);
\ramloop[21].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(773 downto 738)
);
\ramloop[22].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(799 downto 774)
);
\ramloop[2].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(89 downto 54)
);
\ramloop[3].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(125 downto 90)
);
\ramloop[4].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(161 downto 126)
);
\ramloop[5].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(197 downto 162)
);
\ramloop[6].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(233 downto 198)
);
\ramloop[7].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(269 downto 234)
);
\ramloop[8].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(305 downto 270)
);
\ramloop[9].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(341 downto 306)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_top : entity is "blk_mem_gen_top";
end PSelect_blk_mem_gen_top;
architecture STRUCTURE of PSelect_blk_mem_gen_top is
begin
\valid.cstr\: entity work.PSelect_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end PSelect_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of PSelect_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.PSelect_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 799 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 799 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 799 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 3;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "PSelect.mif";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "PSelect.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "22";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 60.4532 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \PSelect_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \PSelect_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(799) <= \<const0>\;
doutb(798) <= \<const0>\;
doutb(797) <= \<const0>\;
doutb(796) <= \<const0>\;
doutb(795) <= \<const0>\;
doutb(794) <= \<const0>\;
doutb(793) <= \<const0>\;
doutb(792) <= \<const0>\;
doutb(791) <= \<const0>\;
doutb(790) <= \<const0>\;
doutb(789) <= \<const0>\;
doutb(788) <= \<const0>\;
doutb(787) <= \<const0>\;
doutb(786) <= \<const0>\;
doutb(785) <= \<const0>\;
doutb(784) <= \<const0>\;
doutb(783) <= \<const0>\;
doutb(782) <= \<const0>\;
doutb(781) <= \<const0>\;
doutb(780) <= \<const0>\;
doutb(779) <= \<const0>\;
doutb(778) <= \<const0>\;
doutb(777) <= \<const0>\;
doutb(776) <= \<const0>\;
doutb(775) <= \<const0>\;
doutb(774) <= \<const0>\;
doutb(773) <= \<const0>\;
doutb(772) <= \<const0>\;
doutb(771) <= \<const0>\;
doutb(770) <= \<const0>\;
doutb(769) <= \<const0>\;
doutb(768) <= \<const0>\;
doutb(767) <= \<const0>\;
doutb(766) <= \<const0>\;
doutb(765) <= \<const0>\;
doutb(764) <= \<const0>\;
doutb(763) <= \<const0>\;
doutb(762) <= \<const0>\;
doutb(761) <= \<const0>\;
doutb(760) <= \<const0>\;
doutb(759) <= \<const0>\;
doutb(758) <= \<const0>\;
doutb(757) <= \<const0>\;
doutb(756) <= \<const0>\;
doutb(755) <= \<const0>\;
doutb(754) <= \<const0>\;
doutb(753) <= \<const0>\;
doutb(752) <= \<const0>\;
doutb(751) <= \<const0>\;
doutb(750) <= \<const0>\;
doutb(749) <= \<const0>\;
doutb(748) <= \<const0>\;
doutb(747) <= \<const0>\;
doutb(746) <= \<const0>\;
doutb(745) <= \<const0>\;
doutb(744) <= \<const0>\;
doutb(743) <= \<const0>\;
doutb(742) <= \<const0>\;
doutb(741) <= \<const0>\;
doutb(740) <= \<const0>\;
doutb(739) <= \<const0>\;
doutb(738) <= \<const0>\;
doutb(737) <= \<const0>\;
doutb(736) <= \<const0>\;
doutb(735) <= \<const0>\;
doutb(734) <= \<const0>\;
doutb(733) <= \<const0>\;
doutb(732) <= \<const0>\;
doutb(731) <= \<const0>\;
doutb(730) <= \<const0>\;
doutb(729) <= \<const0>\;
doutb(728) <= \<const0>\;
doutb(727) <= \<const0>\;
doutb(726) <= \<const0>\;
doutb(725) <= \<const0>\;
doutb(724) <= \<const0>\;
doutb(723) <= \<const0>\;
doutb(722) <= \<const0>\;
doutb(721) <= \<const0>\;
doutb(720) <= \<const0>\;
doutb(719) <= \<const0>\;
doutb(718) <= \<const0>\;
doutb(717) <= \<const0>\;
doutb(716) <= \<const0>\;
doutb(715) <= \<const0>\;
doutb(714) <= \<const0>\;
doutb(713) <= \<const0>\;
doutb(712) <= \<const0>\;
doutb(711) <= \<const0>\;
doutb(710) <= \<const0>\;
doutb(709) <= \<const0>\;
doutb(708) <= \<const0>\;
doutb(707) <= \<const0>\;
doutb(706) <= \<const0>\;
doutb(705) <= \<const0>\;
doutb(704) <= \<const0>\;
doutb(703) <= \<const0>\;
doutb(702) <= \<const0>\;
doutb(701) <= \<const0>\;
doutb(700) <= \<const0>\;
doutb(699) <= \<const0>\;
doutb(698) <= \<const0>\;
doutb(697) <= \<const0>\;
doutb(696) <= \<const0>\;
doutb(695) <= \<const0>\;
doutb(694) <= \<const0>\;
doutb(693) <= \<const0>\;
doutb(692) <= \<const0>\;
doutb(691) <= \<const0>\;
doutb(690) <= \<const0>\;
doutb(689) <= \<const0>\;
doutb(688) <= \<const0>\;
doutb(687) <= \<const0>\;
doutb(686) <= \<const0>\;
doutb(685) <= \<const0>\;
doutb(684) <= \<const0>\;
doutb(683) <= \<const0>\;
doutb(682) <= \<const0>\;
doutb(681) <= \<const0>\;
doutb(680) <= \<const0>\;
doutb(679) <= \<const0>\;
doutb(678) <= \<const0>\;
doutb(677) <= \<const0>\;
doutb(676) <= \<const0>\;
doutb(675) <= \<const0>\;
doutb(674) <= \<const0>\;
doutb(673) <= \<const0>\;
doutb(672) <= \<const0>\;
doutb(671) <= \<const0>\;
doutb(670) <= \<const0>\;
doutb(669) <= \<const0>\;
doutb(668) <= \<const0>\;
doutb(667) <= \<const0>\;
doutb(666) <= \<const0>\;
doutb(665) <= \<const0>\;
doutb(664) <= \<const0>\;
doutb(663) <= \<const0>\;
doutb(662) <= \<const0>\;
doutb(661) <= \<const0>\;
doutb(660) <= \<const0>\;
doutb(659) <= \<const0>\;
doutb(658) <= \<const0>\;
doutb(657) <= \<const0>\;
doutb(656) <= \<const0>\;
doutb(655) <= \<const0>\;
doutb(654) <= \<const0>\;
doutb(653) <= \<const0>\;
doutb(652) <= \<const0>\;
doutb(651) <= \<const0>\;
doutb(650) <= \<const0>\;
doutb(649) <= \<const0>\;
doutb(648) <= \<const0>\;
doutb(647) <= \<const0>\;
doutb(646) <= \<const0>\;
doutb(645) <= \<const0>\;
doutb(644) <= \<const0>\;
doutb(643) <= \<const0>\;
doutb(642) <= \<const0>\;
doutb(641) <= \<const0>\;
doutb(640) <= \<const0>\;
doutb(639) <= \<const0>\;
doutb(638) <= \<const0>\;
doutb(637) <= \<const0>\;
doutb(636) <= \<const0>\;
doutb(635) <= \<const0>\;
doutb(634) <= \<const0>\;
doutb(633) <= \<const0>\;
doutb(632) <= \<const0>\;
doutb(631) <= \<const0>\;
doutb(630) <= \<const0>\;
doutb(629) <= \<const0>\;
doutb(628) <= \<const0>\;
doutb(627) <= \<const0>\;
doutb(626) <= \<const0>\;
doutb(625) <= \<const0>\;
doutb(624) <= \<const0>\;
doutb(623) <= \<const0>\;
doutb(622) <= \<const0>\;
doutb(621) <= \<const0>\;
doutb(620) <= \<const0>\;
doutb(619) <= \<const0>\;
doutb(618) <= \<const0>\;
doutb(617) <= \<const0>\;
doutb(616) <= \<const0>\;
doutb(615) <= \<const0>\;
doutb(614) <= \<const0>\;
doutb(613) <= \<const0>\;
doutb(612) <= \<const0>\;
doutb(611) <= \<const0>\;
doutb(610) <= \<const0>\;
doutb(609) <= \<const0>\;
doutb(608) <= \<const0>\;
doutb(607) <= \<const0>\;
doutb(606) <= \<const0>\;
doutb(605) <= \<const0>\;
doutb(604) <= \<const0>\;
doutb(603) <= \<const0>\;
doutb(602) <= \<const0>\;
doutb(601) <= \<const0>\;
doutb(600) <= \<const0>\;
doutb(599) <= \<const0>\;
doutb(598) <= \<const0>\;
doutb(597) <= \<const0>\;
doutb(596) <= \<const0>\;
doutb(595) <= \<const0>\;
doutb(594) <= \<const0>\;
doutb(593) <= \<const0>\;
doutb(592) <= \<const0>\;
doutb(591) <= \<const0>\;
doutb(590) <= \<const0>\;
doutb(589) <= \<const0>\;
doutb(588) <= \<const0>\;
doutb(587) <= \<const0>\;
doutb(586) <= \<const0>\;
doutb(585) <= \<const0>\;
doutb(584) <= \<const0>\;
doutb(583) <= \<const0>\;
doutb(582) <= \<const0>\;
doutb(581) <= \<const0>\;
doutb(580) <= \<const0>\;
doutb(579) <= \<const0>\;
doutb(578) <= \<const0>\;
doutb(577) <= \<const0>\;
doutb(576) <= \<const0>\;
doutb(575) <= \<const0>\;
doutb(574) <= \<const0>\;
doutb(573) <= \<const0>\;
doutb(572) <= \<const0>\;
doutb(571) <= \<const0>\;
doutb(570) <= \<const0>\;
doutb(569) <= \<const0>\;
doutb(568) <= \<const0>\;
doutb(567) <= \<const0>\;
doutb(566) <= \<const0>\;
doutb(565) <= \<const0>\;
doutb(564) <= \<const0>\;
doutb(563) <= \<const0>\;
doutb(562) <= \<const0>\;
doutb(561) <= \<const0>\;
doutb(560) <= \<const0>\;
doutb(559) <= \<const0>\;
doutb(558) <= \<const0>\;
doutb(557) <= \<const0>\;
doutb(556) <= \<const0>\;
doutb(555) <= \<const0>\;
doutb(554) <= \<const0>\;
doutb(553) <= \<const0>\;
doutb(552) <= \<const0>\;
doutb(551) <= \<const0>\;
doutb(550) <= \<const0>\;
doutb(549) <= \<const0>\;
doutb(548) <= \<const0>\;
doutb(547) <= \<const0>\;
doutb(546) <= \<const0>\;
doutb(545) <= \<const0>\;
doutb(544) <= \<const0>\;
doutb(543) <= \<const0>\;
doutb(542) <= \<const0>\;
doutb(541) <= \<const0>\;
doutb(540) <= \<const0>\;
doutb(539) <= \<const0>\;
doutb(538) <= \<const0>\;
doutb(537) <= \<const0>\;
doutb(536) <= \<const0>\;
doutb(535) <= \<const0>\;
doutb(534) <= \<const0>\;
doutb(533) <= \<const0>\;
doutb(532) <= \<const0>\;
doutb(531) <= \<const0>\;
doutb(530) <= \<const0>\;
doutb(529) <= \<const0>\;
doutb(528) <= \<const0>\;
doutb(527) <= \<const0>\;
doutb(526) <= \<const0>\;
doutb(525) <= \<const0>\;
doutb(524) <= \<const0>\;
doutb(523) <= \<const0>\;
doutb(522) <= \<const0>\;
doutb(521) <= \<const0>\;
doutb(520) <= \<const0>\;
doutb(519) <= \<const0>\;
doutb(518) <= \<const0>\;
doutb(517) <= \<const0>\;
doutb(516) <= \<const0>\;
doutb(515) <= \<const0>\;
doutb(514) <= \<const0>\;
doutb(513) <= \<const0>\;
doutb(512) <= \<const0>\;
doutb(511) <= \<const0>\;
doutb(510) <= \<const0>\;
doutb(509) <= \<const0>\;
doutb(508) <= \<const0>\;
doutb(507) <= \<const0>\;
doutb(506) <= \<const0>\;
doutb(505) <= \<const0>\;
doutb(504) <= \<const0>\;
doutb(503) <= \<const0>\;
doutb(502) <= \<const0>\;
doutb(501) <= \<const0>\;
doutb(500) <= \<const0>\;
doutb(499) <= \<const0>\;
doutb(498) <= \<const0>\;
doutb(497) <= \<const0>\;
doutb(496) <= \<const0>\;
doutb(495) <= \<const0>\;
doutb(494) <= \<const0>\;
doutb(493) <= \<const0>\;
doutb(492) <= \<const0>\;
doutb(491) <= \<const0>\;
doutb(490) <= \<const0>\;
doutb(489) <= \<const0>\;
doutb(488) <= \<const0>\;
doutb(487) <= \<const0>\;
doutb(486) <= \<const0>\;
doutb(485) <= \<const0>\;
doutb(484) <= \<const0>\;
doutb(483) <= \<const0>\;
doutb(482) <= \<const0>\;
doutb(481) <= \<const0>\;
doutb(480) <= \<const0>\;
doutb(479) <= \<const0>\;
doutb(478) <= \<const0>\;
doutb(477) <= \<const0>\;
doutb(476) <= \<const0>\;
doutb(475) <= \<const0>\;
doutb(474) <= \<const0>\;
doutb(473) <= \<const0>\;
doutb(472) <= \<const0>\;
doutb(471) <= \<const0>\;
doutb(470) <= \<const0>\;
doutb(469) <= \<const0>\;
doutb(468) <= \<const0>\;
doutb(467) <= \<const0>\;
doutb(466) <= \<const0>\;
doutb(465) <= \<const0>\;
doutb(464) <= \<const0>\;
doutb(463) <= \<const0>\;
doutb(462) <= \<const0>\;
doutb(461) <= \<const0>\;
doutb(460) <= \<const0>\;
doutb(459) <= \<const0>\;
doutb(458) <= \<const0>\;
doutb(457) <= \<const0>\;
doutb(456) <= \<const0>\;
doutb(455) <= \<const0>\;
doutb(454) <= \<const0>\;
doutb(453) <= \<const0>\;
doutb(452) <= \<const0>\;
doutb(451) <= \<const0>\;
doutb(450) <= \<const0>\;
doutb(449) <= \<const0>\;
doutb(448) <= \<const0>\;
doutb(447) <= \<const0>\;
doutb(446) <= \<const0>\;
doutb(445) <= \<const0>\;
doutb(444) <= \<const0>\;
doutb(443) <= \<const0>\;
doutb(442) <= \<const0>\;
doutb(441) <= \<const0>\;
doutb(440) <= \<const0>\;
doutb(439) <= \<const0>\;
doutb(438) <= \<const0>\;
doutb(437) <= \<const0>\;
doutb(436) <= \<const0>\;
doutb(435) <= \<const0>\;
doutb(434) <= \<const0>\;
doutb(433) <= \<const0>\;
doutb(432) <= \<const0>\;
doutb(431) <= \<const0>\;
doutb(430) <= \<const0>\;
doutb(429) <= \<const0>\;
doutb(428) <= \<const0>\;
doutb(427) <= \<const0>\;
doutb(426) <= \<const0>\;
doutb(425) <= \<const0>\;
doutb(424) <= \<const0>\;
doutb(423) <= \<const0>\;
doutb(422) <= \<const0>\;
doutb(421) <= \<const0>\;
doutb(420) <= \<const0>\;
doutb(419) <= \<const0>\;
doutb(418) <= \<const0>\;
doutb(417) <= \<const0>\;
doutb(416) <= \<const0>\;
doutb(415) <= \<const0>\;
doutb(414) <= \<const0>\;
doutb(413) <= \<const0>\;
doutb(412) <= \<const0>\;
doutb(411) <= \<const0>\;
doutb(410) <= \<const0>\;
doutb(409) <= \<const0>\;
doutb(408) <= \<const0>\;
doutb(407) <= \<const0>\;
doutb(406) <= \<const0>\;
doutb(405) <= \<const0>\;
doutb(404) <= \<const0>\;
doutb(403) <= \<const0>\;
doutb(402) <= \<const0>\;
doutb(401) <= \<const0>\;
doutb(400) <= \<const0>\;
doutb(399) <= \<const0>\;
doutb(398) <= \<const0>\;
doutb(397) <= \<const0>\;
doutb(396) <= \<const0>\;
doutb(395) <= \<const0>\;
doutb(394) <= \<const0>\;
doutb(393) <= \<const0>\;
doutb(392) <= \<const0>\;
doutb(391) <= \<const0>\;
doutb(390) <= \<const0>\;
doutb(389) <= \<const0>\;
doutb(388) <= \<const0>\;
doutb(387) <= \<const0>\;
doutb(386) <= \<const0>\;
doutb(385) <= \<const0>\;
doutb(384) <= \<const0>\;
doutb(383) <= \<const0>\;
doutb(382) <= \<const0>\;
doutb(381) <= \<const0>\;
doutb(380) <= \<const0>\;
doutb(379) <= \<const0>\;
doutb(378) <= \<const0>\;
doutb(377) <= \<const0>\;
doutb(376) <= \<const0>\;
doutb(375) <= \<const0>\;
doutb(374) <= \<const0>\;
doutb(373) <= \<const0>\;
doutb(372) <= \<const0>\;
doutb(371) <= \<const0>\;
doutb(370) <= \<const0>\;
doutb(369) <= \<const0>\;
doutb(368) <= \<const0>\;
doutb(367) <= \<const0>\;
doutb(366) <= \<const0>\;
doutb(365) <= \<const0>\;
doutb(364) <= \<const0>\;
doutb(363) <= \<const0>\;
doutb(362) <= \<const0>\;
doutb(361) <= \<const0>\;
doutb(360) <= \<const0>\;
doutb(359) <= \<const0>\;
doutb(358) <= \<const0>\;
doutb(357) <= \<const0>\;
doutb(356) <= \<const0>\;
doutb(355) <= \<const0>\;
doutb(354) <= \<const0>\;
doutb(353) <= \<const0>\;
doutb(352) <= \<const0>\;
doutb(351) <= \<const0>\;
doutb(350) <= \<const0>\;
doutb(349) <= \<const0>\;
doutb(348) <= \<const0>\;
doutb(347) <= \<const0>\;
doutb(346) <= \<const0>\;
doutb(345) <= \<const0>\;
doutb(344) <= \<const0>\;
doutb(343) <= \<const0>\;
doutb(342) <= \<const0>\;
doutb(341) <= \<const0>\;
doutb(340) <= \<const0>\;
doutb(339) <= \<const0>\;
doutb(338) <= \<const0>\;
doutb(337) <= \<const0>\;
doutb(336) <= \<const0>\;
doutb(335) <= \<const0>\;
doutb(334) <= \<const0>\;
doutb(333) <= \<const0>\;
doutb(332) <= \<const0>\;
doutb(331) <= \<const0>\;
doutb(330) <= \<const0>\;
doutb(329) <= \<const0>\;
doutb(328) <= \<const0>\;
doutb(327) <= \<const0>\;
doutb(326) <= \<const0>\;
doutb(325) <= \<const0>\;
doutb(324) <= \<const0>\;
doutb(323) <= \<const0>\;
doutb(322) <= \<const0>\;
doutb(321) <= \<const0>\;
doutb(320) <= \<const0>\;
doutb(319) <= \<const0>\;
doutb(318) <= \<const0>\;
doutb(317) <= \<const0>\;
doutb(316) <= \<const0>\;
doutb(315) <= \<const0>\;
doutb(314) <= \<const0>\;
doutb(313) <= \<const0>\;
doutb(312) <= \<const0>\;
doutb(311) <= \<const0>\;
doutb(310) <= \<const0>\;
doutb(309) <= \<const0>\;
doutb(308) <= \<const0>\;
doutb(307) <= \<const0>\;
doutb(306) <= \<const0>\;
doutb(305) <= \<const0>\;
doutb(304) <= \<const0>\;
doutb(303) <= \<const0>\;
doutb(302) <= \<const0>\;
doutb(301) <= \<const0>\;
doutb(300) <= \<const0>\;
doutb(299) <= \<const0>\;
doutb(298) <= \<const0>\;
doutb(297) <= \<const0>\;
doutb(296) <= \<const0>\;
doutb(295) <= \<const0>\;
doutb(294) <= \<const0>\;
doutb(293) <= \<const0>\;
doutb(292) <= \<const0>\;
doutb(291) <= \<const0>\;
doutb(290) <= \<const0>\;
doutb(289) <= \<const0>\;
doutb(288) <= \<const0>\;
doutb(287) <= \<const0>\;
doutb(286) <= \<const0>\;
doutb(285) <= \<const0>\;
doutb(284) <= \<const0>\;
doutb(283) <= \<const0>\;
doutb(282) <= \<const0>\;
doutb(281) <= \<const0>\;
doutb(280) <= \<const0>\;
doutb(279) <= \<const0>\;
doutb(278) <= \<const0>\;
doutb(277) <= \<const0>\;
doutb(276) <= \<const0>\;
doutb(275) <= \<const0>\;
doutb(274) <= \<const0>\;
doutb(273) <= \<const0>\;
doutb(272) <= \<const0>\;
doutb(271) <= \<const0>\;
doutb(270) <= \<const0>\;
doutb(269) <= \<const0>\;
doutb(268) <= \<const0>\;
doutb(267) <= \<const0>\;
doutb(266) <= \<const0>\;
doutb(265) <= \<const0>\;
doutb(264) <= \<const0>\;
doutb(263) <= \<const0>\;
doutb(262) <= \<const0>\;
doutb(261) <= \<const0>\;
doutb(260) <= \<const0>\;
doutb(259) <= \<const0>\;
doutb(258) <= \<const0>\;
doutb(257) <= \<const0>\;
doutb(256) <= \<const0>\;
doutb(255) <= \<const0>\;
doutb(254) <= \<const0>\;
doutb(253) <= \<const0>\;
doutb(252) <= \<const0>\;
doutb(251) <= \<const0>\;
doutb(250) <= \<const0>\;
doutb(249) <= \<const0>\;
doutb(248) <= \<const0>\;
doutb(247) <= \<const0>\;
doutb(246) <= \<const0>\;
doutb(245) <= \<const0>\;
doutb(244) <= \<const0>\;
doutb(243) <= \<const0>\;
doutb(242) <= \<const0>\;
doutb(241) <= \<const0>\;
doutb(240) <= \<const0>\;
doutb(239) <= \<const0>\;
doutb(238) <= \<const0>\;
doutb(237) <= \<const0>\;
doutb(236) <= \<const0>\;
doutb(235) <= \<const0>\;
doutb(234) <= \<const0>\;
doutb(233) <= \<const0>\;
doutb(232) <= \<const0>\;
doutb(231) <= \<const0>\;
doutb(230) <= \<const0>\;
doutb(229) <= \<const0>\;
doutb(228) <= \<const0>\;
doutb(227) <= \<const0>\;
doutb(226) <= \<const0>\;
doutb(225) <= \<const0>\;
doutb(224) <= \<const0>\;
doutb(223) <= \<const0>\;
doutb(222) <= \<const0>\;
doutb(221) <= \<const0>\;
doutb(220) <= \<const0>\;
doutb(219) <= \<const0>\;
doutb(218) <= \<const0>\;
doutb(217) <= \<const0>\;
doutb(216) <= \<const0>\;
doutb(215) <= \<const0>\;
doutb(214) <= \<const0>\;
doutb(213) <= \<const0>\;
doutb(212) <= \<const0>\;
doutb(211) <= \<const0>\;
doutb(210) <= \<const0>\;
doutb(209) <= \<const0>\;
doutb(208) <= \<const0>\;
doutb(207) <= \<const0>\;
doutb(206) <= \<const0>\;
doutb(205) <= \<const0>\;
doutb(204) <= \<const0>\;
doutb(203) <= \<const0>\;
doutb(202) <= \<const0>\;
doutb(201) <= \<const0>\;
doutb(200) <= \<const0>\;
doutb(199) <= \<const0>\;
doutb(198) <= \<const0>\;
doutb(197) <= \<const0>\;
doutb(196) <= \<const0>\;
doutb(195) <= \<const0>\;
doutb(194) <= \<const0>\;
doutb(193) <= \<const0>\;
doutb(192) <= \<const0>\;
doutb(191) <= \<const0>\;
doutb(190) <= \<const0>\;
doutb(189) <= \<const0>\;
doutb(188) <= \<const0>\;
doutb(187) <= \<const0>\;
doutb(186) <= \<const0>\;
doutb(185) <= \<const0>\;
doutb(184) <= \<const0>\;
doutb(183) <= \<const0>\;
doutb(182) <= \<const0>\;
doutb(181) <= \<const0>\;
doutb(180) <= \<const0>\;
doutb(179) <= \<const0>\;
doutb(178) <= \<const0>\;
doutb(177) <= \<const0>\;
doutb(176) <= \<const0>\;
doutb(175) <= \<const0>\;
doutb(174) <= \<const0>\;
doutb(173) <= \<const0>\;
doutb(172) <= \<const0>\;
doutb(171) <= \<const0>\;
doutb(170) <= \<const0>\;
doutb(169) <= \<const0>\;
doutb(168) <= \<const0>\;
doutb(167) <= \<const0>\;
doutb(166) <= \<const0>\;
doutb(165) <= \<const0>\;
doutb(164) <= \<const0>\;
doutb(163) <= \<const0>\;
doutb(162) <= \<const0>\;
doutb(161) <= \<const0>\;
doutb(160) <= \<const0>\;
doutb(159) <= \<const0>\;
doutb(158) <= \<const0>\;
doutb(157) <= \<const0>\;
doutb(156) <= \<const0>\;
doutb(155) <= \<const0>\;
doutb(154) <= \<const0>\;
doutb(153) <= \<const0>\;
doutb(152) <= \<const0>\;
doutb(151) <= \<const0>\;
doutb(150) <= \<const0>\;
doutb(149) <= \<const0>\;
doutb(148) <= \<const0>\;
doutb(147) <= \<const0>\;
doutb(146) <= \<const0>\;
doutb(145) <= \<const0>\;
doutb(144) <= \<const0>\;
doutb(143) <= \<const0>\;
doutb(142) <= \<const0>\;
doutb(141) <= \<const0>\;
doutb(140) <= \<const0>\;
doutb(139) <= \<const0>\;
doutb(138) <= \<const0>\;
doutb(137) <= \<const0>\;
doutb(136) <= \<const0>\;
doutb(135) <= \<const0>\;
doutb(134) <= \<const0>\;
doutb(133) <= \<const0>\;
doutb(132) <= \<const0>\;
doutb(131) <= \<const0>\;
doutb(130) <= \<const0>\;
doutb(129) <= \<const0>\;
doutb(128) <= \<const0>\;
doutb(127) <= \<const0>\;
doutb(126) <= \<const0>\;
doutb(125) <= \<const0>\;
doutb(124) <= \<const0>\;
doutb(123) <= \<const0>\;
doutb(122) <= \<const0>\;
doutb(121) <= \<const0>\;
doutb(120) <= \<const0>\;
doutb(119) <= \<const0>\;
doutb(118) <= \<const0>\;
doutb(117) <= \<const0>\;
doutb(116) <= \<const0>\;
doutb(115) <= \<const0>\;
doutb(114) <= \<const0>\;
doutb(113) <= \<const0>\;
doutb(112) <= \<const0>\;
doutb(111) <= \<const0>\;
doutb(110) <= \<const0>\;
doutb(109) <= \<const0>\;
doutb(108) <= \<const0>\;
doutb(107) <= \<const0>\;
doutb(106) <= \<const0>\;
doutb(105) <= \<const0>\;
doutb(104) <= \<const0>\;
doutb(103) <= \<const0>\;
doutb(102) <= \<const0>\;
doutb(101) <= \<const0>\;
doutb(100) <= \<const0>\;
doutb(99) <= \<const0>\;
doutb(98) <= \<const0>\;
doutb(97) <= \<const0>\;
doutb(96) <= \<const0>\;
doutb(95) <= \<const0>\;
doutb(94) <= \<const0>\;
doutb(93) <= \<const0>\;
doutb(92) <= \<const0>\;
doutb(91) <= \<const0>\;
doutb(90) <= \<const0>\;
doutb(89) <= \<const0>\;
doutb(88) <= \<const0>\;
doutb(87) <= \<const0>\;
doutb(86) <= \<const0>\;
doutb(85) <= \<const0>\;
doutb(84) <= \<const0>\;
doutb(83) <= \<const0>\;
doutb(82) <= \<const0>\;
doutb(81) <= \<const0>\;
doutb(80) <= \<const0>\;
doutb(79) <= \<const0>\;
doutb(78) <= \<const0>\;
doutb(77) <= \<const0>\;
doutb(76) <= \<const0>\;
doutb(75) <= \<const0>\;
doutb(74) <= \<const0>\;
doutb(73) <= \<const0>\;
doutb(72) <= \<const0>\;
doutb(71) <= \<const0>\;
doutb(70) <= \<const0>\;
doutb(69) <= \<const0>\;
doutb(68) <= \<const0>\;
doutb(67) <= \<const0>\;
doutb(66) <= \<const0>\;
doutb(65) <= \<const0>\;
doutb(64) <= \<const0>\;
doutb(63) <= \<const0>\;
doutb(62) <= \<const0>\;
doutb(61) <= \<const0>\;
doutb(60) <= \<const0>\;
doutb(59) <= \<const0>\;
doutb(58) <= \<const0>\;
doutb(57) <= \<const0>\;
doutb(56) <= \<const0>\;
doutb(55) <= \<const0>\;
doutb(54) <= \<const0>\;
doutb(53) <= \<const0>\;
doutb(52) <= \<const0>\;
doutb(51) <= \<const0>\;
doutb(50) <= \<const0>\;
doutb(49) <= \<const0>\;
doutb(48) <= \<const0>\;
doutb(47) <= \<const0>\;
doutb(46) <= \<const0>\;
doutb(45) <= \<const0>\;
doutb(44) <= \<const0>\;
doutb(43) <= \<const0>\;
doutb(42) <= \<const0>\;
doutb(41) <= \<const0>\;
doutb(40) <= \<const0>\;
doutb(39) <= \<const0>\;
doutb(38) <= \<const0>\;
doutb(37) <= \<const0>\;
doutb(36) <= \<const0>\;
doutb(35) <= \<const0>\;
doutb(34) <= \<const0>\;
doutb(33) <= \<const0>\;
doutb(32) <= \<const0>\;
doutb(31) <= \<const0>\;
doutb(30) <= \<const0>\;
doutb(29) <= \<const0>\;
doutb(28) <= \<const0>\;
doutb(27) <= \<const0>\;
doutb(26) <= \<const0>\;
doutb(25) <= \<const0>\;
doutb(24) <= \<const0>\;
doutb(23) <= \<const0>\;
doutb(22) <= \<const0>\;
doutb(21) <= \<const0>\;
doutb(20) <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(799) <= \<const0>\;
s_axi_rdata(798) <= \<const0>\;
s_axi_rdata(797) <= \<const0>\;
s_axi_rdata(796) <= \<const0>\;
s_axi_rdata(795) <= \<const0>\;
s_axi_rdata(794) <= \<const0>\;
s_axi_rdata(793) <= \<const0>\;
s_axi_rdata(792) <= \<const0>\;
s_axi_rdata(791) <= \<const0>\;
s_axi_rdata(790) <= \<const0>\;
s_axi_rdata(789) <= \<const0>\;
s_axi_rdata(788) <= \<const0>\;
s_axi_rdata(787) <= \<const0>\;
s_axi_rdata(786) <= \<const0>\;
s_axi_rdata(785) <= \<const0>\;
s_axi_rdata(784) <= \<const0>\;
s_axi_rdata(783) <= \<const0>\;
s_axi_rdata(782) <= \<const0>\;
s_axi_rdata(781) <= \<const0>\;
s_axi_rdata(780) <= \<const0>\;
s_axi_rdata(779) <= \<const0>\;
s_axi_rdata(778) <= \<const0>\;
s_axi_rdata(777) <= \<const0>\;
s_axi_rdata(776) <= \<const0>\;
s_axi_rdata(775) <= \<const0>\;
s_axi_rdata(774) <= \<const0>\;
s_axi_rdata(773) <= \<const0>\;
s_axi_rdata(772) <= \<const0>\;
s_axi_rdata(771) <= \<const0>\;
s_axi_rdata(770) <= \<const0>\;
s_axi_rdata(769) <= \<const0>\;
s_axi_rdata(768) <= \<const0>\;
s_axi_rdata(767) <= \<const0>\;
s_axi_rdata(766) <= \<const0>\;
s_axi_rdata(765) <= \<const0>\;
s_axi_rdata(764) <= \<const0>\;
s_axi_rdata(763) <= \<const0>\;
s_axi_rdata(762) <= \<const0>\;
s_axi_rdata(761) <= \<const0>\;
s_axi_rdata(760) <= \<const0>\;
s_axi_rdata(759) <= \<const0>\;
s_axi_rdata(758) <= \<const0>\;
s_axi_rdata(757) <= \<const0>\;
s_axi_rdata(756) <= \<const0>\;
s_axi_rdata(755) <= \<const0>\;
s_axi_rdata(754) <= \<const0>\;
s_axi_rdata(753) <= \<const0>\;
s_axi_rdata(752) <= \<const0>\;
s_axi_rdata(751) <= \<const0>\;
s_axi_rdata(750) <= \<const0>\;
s_axi_rdata(749) <= \<const0>\;
s_axi_rdata(748) <= \<const0>\;
s_axi_rdata(747) <= \<const0>\;
s_axi_rdata(746) <= \<const0>\;
s_axi_rdata(745) <= \<const0>\;
s_axi_rdata(744) <= \<const0>\;
s_axi_rdata(743) <= \<const0>\;
s_axi_rdata(742) <= \<const0>\;
s_axi_rdata(741) <= \<const0>\;
s_axi_rdata(740) <= \<const0>\;
s_axi_rdata(739) <= \<const0>\;
s_axi_rdata(738) <= \<const0>\;
s_axi_rdata(737) <= \<const0>\;
s_axi_rdata(736) <= \<const0>\;
s_axi_rdata(735) <= \<const0>\;
s_axi_rdata(734) <= \<const0>\;
s_axi_rdata(733) <= \<const0>\;
s_axi_rdata(732) <= \<const0>\;
s_axi_rdata(731) <= \<const0>\;
s_axi_rdata(730) <= \<const0>\;
s_axi_rdata(729) <= \<const0>\;
s_axi_rdata(728) <= \<const0>\;
s_axi_rdata(727) <= \<const0>\;
s_axi_rdata(726) <= \<const0>\;
s_axi_rdata(725) <= \<const0>\;
s_axi_rdata(724) <= \<const0>\;
s_axi_rdata(723) <= \<const0>\;
s_axi_rdata(722) <= \<const0>\;
s_axi_rdata(721) <= \<const0>\;
s_axi_rdata(720) <= \<const0>\;
s_axi_rdata(719) <= \<const0>\;
s_axi_rdata(718) <= \<const0>\;
s_axi_rdata(717) <= \<const0>\;
s_axi_rdata(716) <= \<const0>\;
s_axi_rdata(715) <= \<const0>\;
s_axi_rdata(714) <= \<const0>\;
s_axi_rdata(713) <= \<const0>\;
s_axi_rdata(712) <= \<const0>\;
s_axi_rdata(711) <= \<const0>\;
s_axi_rdata(710) <= \<const0>\;
s_axi_rdata(709) <= \<const0>\;
s_axi_rdata(708) <= \<const0>\;
s_axi_rdata(707) <= \<const0>\;
s_axi_rdata(706) <= \<const0>\;
s_axi_rdata(705) <= \<const0>\;
s_axi_rdata(704) <= \<const0>\;
s_axi_rdata(703) <= \<const0>\;
s_axi_rdata(702) <= \<const0>\;
s_axi_rdata(701) <= \<const0>\;
s_axi_rdata(700) <= \<const0>\;
s_axi_rdata(699) <= \<const0>\;
s_axi_rdata(698) <= \<const0>\;
s_axi_rdata(697) <= \<const0>\;
s_axi_rdata(696) <= \<const0>\;
s_axi_rdata(695) <= \<const0>\;
s_axi_rdata(694) <= \<const0>\;
s_axi_rdata(693) <= \<const0>\;
s_axi_rdata(692) <= \<const0>\;
s_axi_rdata(691) <= \<const0>\;
s_axi_rdata(690) <= \<const0>\;
s_axi_rdata(689) <= \<const0>\;
s_axi_rdata(688) <= \<const0>\;
s_axi_rdata(687) <= \<const0>\;
s_axi_rdata(686) <= \<const0>\;
s_axi_rdata(685) <= \<const0>\;
s_axi_rdata(684) <= \<const0>\;
s_axi_rdata(683) <= \<const0>\;
s_axi_rdata(682) <= \<const0>\;
s_axi_rdata(681) <= \<const0>\;
s_axi_rdata(680) <= \<const0>\;
s_axi_rdata(679) <= \<const0>\;
s_axi_rdata(678) <= \<const0>\;
s_axi_rdata(677) <= \<const0>\;
s_axi_rdata(676) <= \<const0>\;
s_axi_rdata(675) <= \<const0>\;
s_axi_rdata(674) <= \<const0>\;
s_axi_rdata(673) <= \<const0>\;
s_axi_rdata(672) <= \<const0>\;
s_axi_rdata(671) <= \<const0>\;
s_axi_rdata(670) <= \<const0>\;
s_axi_rdata(669) <= \<const0>\;
s_axi_rdata(668) <= \<const0>\;
s_axi_rdata(667) <= \<const0>\;
s_axi_rdata(666) <= \<const0>\;
s_axi_rdata(665) <= \<const0>\;
s_axi_rdata(664) <= \<const0>\;
s_axi_rdata(663) <= \<const0>\;
s_axi_rdata(662) <= \<const0>\;
s_axi_rdata(661) <= \<const0>\;
s_axi_rdata(660) <= \<const0>\;
s_axi_rdata(659) <= \<const0>\;
s_axi_rdata(658) <= \<const0>\;
s_axi_rdata(657) <= \<const0>\;
s_axi_rdata(656) <= \<const0>\;
s_axi_rdata(655) <= \<const0>\;
s_axi_rdata(654) <= \<const0>\;
s_axi_rdata(653) <= \<const0>\;
s_axi_rdata(652) <= \<const0>\;
s_axi_rdata(651) <= \<const0>\;
s_axi_rdata(650) <= \<const0>\;
s_axi_rdata(649) <= \<const0>\;
s_axi_rdata(648) <= \<const0>\;
s_axi_rdata(647) <= \<const0>\;
s_axi_rdata(646) <= \<const0>\;
s_axi_rdata(645) <= \<const0>\;
s_axi_rdata(644) <= \<const0>\;
s_axi_rdata(643) <= \<const0>\;
s_axi_rdata(642) <= \<const0>\;
s_axi_rdata(641) <= \<const0>\;
s_axi_rdata(640) <= \<const0>\;
s_axi_rdata(639) <= \<const0>\;
s_axi_rdata(638) <= \<const0>\;
s_axi_rdata(637) <= \<const0>\;
s_axi_rdata(636) <= \<const0>\;
s_axi_rdata(635) <= \<const0>\;
s_axi_rdata(634) <= \<const0>\;
s_axi_rdata(633) <= \<const0>\;
s_axi_rdata(632) <= \<const0>\;
s_axi_rdata(631) <= \<const0>\;
s_axi_rdata(630) <= \<const0>\;
s_axi_rdata(629) <= \<const0>\;
s_axi_rdata(628) <= \<const0>\;
s_axi_rdata(627) <= \<const0>\;
s_axi_rdata(626) <= \<const0>\;
s_axi_rdata(625) <= \<const0>\;
s_axi_rdata(624) <= \<const0>\;
s_axi_rdata(623) <= \<const0>\;
s_axi_rdata(622) <= \<const0>\;
s_axi_rdata(621) <= \<const0>\;
s_axi_rdata(620) <= \<const0>\;
s_axi_rdata(619) <= \<const0>\;
s_axi_rdata(618) <= \<const0>\;
s_axi_rdata(617) <= \<const0>\;
s_axi_rdata(616) <= \<const0>\;
s_axi_rdata(615) <= \<const0>\;
s_axi_rdata(614) <= \<const0>\;
s_axi_rdata(613) <= \<const0>\;
s_axi_rdata(612) <= \<const0>\;
s_axi_rdata(611) <= \<const0>\;
s_axi_rdata(610) <= \<const0>\;
s_axi_rdata(609) <= \<const0>\;
s_axi_rdata(608) <= \<const0>\;
s_axi_rdata(607) <= \<const0>\;
s_axi_rdata(606) <= \<const0>\;
s_axi_rdata(605) <= \<const0>\;
s_axi_rdata(604) <= \<const0>\;
s_axi_rdata(603) <= \<const0>\;
s_axi_rdata(602) <= \<const0>\;
s_axi_rdata(601) <= \<const0>\;
s_axi_rdata(600) <= \<const0>\;
s_axi_rdata(599) <= \<const0>\;
s_axi_rdata(598) <= \<const0>\;
s_axi_rdata(597) <= \<const0>\;
s_axi_rdata(596) <= \<const0>\;
s_axi_rdata(595) <= \<const0>\;
s_axi_rdata(594) <= \<const0>\;
s_axi_rdata(593) <= \<const0>\;
s_axi_rdata(592) <= \<const0>\;
s_axi_rdata(591) <= \<const0>\;
s_axi_rdata(590) <= \<const0>\;
s_axi_rdata(589) <= \<const0>\;
s_axi_rdata(588) <= \<const0>\;
s_axi_rdata(587) <= \<const0>\;
s_axi_rdata(586) <= \<const0>\;
s_axi_rdata(585) <= \<const0>\;
s_axi_rdata(584) <= \<const0>\;
s_axi_rdata(583) <= \<const0>\;
s_axi_rdata(582) <= \<const0>\;
s_axi_rdata(581) <= \<const0>\;
s_axi_rdata(580) <= \<const0>\;
s_axi_rdata(579) <= \<const0>\;
s_axi_rdata(578) <= \<const0>\;
s_axi_rdata(577) <= \<const0>\;
s_axi_rdata(576) <= \<const0>\;
s_axi_rdata(575) <= \<const0>\;
s_axi_rdata(574) <= \<const0>\;
s_axi_rdata(573) <= \<const0>\;
s_axi_rdata(572) <= \<const0>\;
s_axi_rdata(571) <= \<const0>\;
s_axi_rdata(570) <= \<const0>\;
s_axi_rdata(569) <= \<const0>\;
s_axi_rdata(568) <= \<const0>\;
s_axi_rdata(567) <= \<const0>\;
s_axi_rdata(566) <= \<const0>\;
s_axi_rdata(565) <= \<const0>\;
s_axi_rdata(564) <= \<const0>\;
s_axi_rdata(563) <= \<const0>\;
s_axi_rdata(562) <= \<const0>\;
s_axi_rdata(561) <= \<const0>\;
s_axi_rdata(560) <= \<const0>\;
s_axi_rdata(559) <= \<const0>\;
s_axi_rdata(558) <= \<const0>\;
s_axi_rdata(557) <= \<const0>\;
s_axi_rdata(556) <= \<const0>\;
s_axi_rdata(555) <= \<const0>\;
s_axi_rdata(554) <= \<const0>\;
s_axi_rdata(553) <= \<const0>\;
s_axi_rdata(552) <= \<const0>\;
s_axi_rdata(551) <= \<const0>\;
s_axi_rdata(550) <= \<const0>\;
s_axi_rdata(549) <= \<const0>\;
s_axi_rdata(548) <= \<const0>\;
s_axi_rdata(547) <= \<const0>\;
s_axi_rdata(546) <= \<const0>\;
s_axi_rdata(545) <= \<const0>\;
s_axi_rdata(544) <= \<const0>\;
s_axi_rdata(543) <= \<const0>\;
s_axi_rdata(542) <= \<const0>\;
s_axi_rdata(541) <= \<const0>\;
s_axi_rdata(540) <= \<const0>\;
s_axi_rdata(539) <= \<const0>\;
s_axi_rdata(538) <= \<const0>\;
s_axi_rdata(537) <= \<const0>\;
s_axi_rdata(536) <= \<const0>\;
s_axi_rdata(535) <= \<const0>\;
s_axi_rdata(534) <= \<const0>\;
s_axi_rdata(533) <= \<const0>\;
s_axi_rdata(532) <= \<const0>\;
s_axi_rdata(531) <= \<const0>\;
s_axi_rdata(530) <= \<const0>\;
s_axi_rdata(529) <= \<const0>\;
s_axi_rdata(528) <= \<const0>\;
s_axi_rdata(527) <= \<const0>\;
s_axi_rdata(526) <= \<const0>\;
s_axi_rdata(525) <= \<const0>\;
s_axi_rdata(524) <= \<const0>\;
s_axi_rdata(523) <= \<const0>\;
s_axi_rdata(522) <= \<const0>\;
s_axi_rdata(521) <= \<const0>\;
s_axi_rdata(520) <= \<const0>\;
s_axi_rdata(519) <= \<const0>\;
s_axi_rdata(518) <= \<const0>\;
s_axi_rdata(517) <= \<const0>\;
s_axi_rdata(516) <= \<const0>\;
s_axi_rdata(515) <= \<const0>\;
s_axi_rdata(514) <= \<const0>\;
s_axi_rdata(513) <= \<const0>\;
s_axi_rdata(512) <= \<const0>\;
s_axi_rdata(511) <= \<const0>\;
s_axi_rdata(510) <= \<const0>\;
s_axi_rdata(509) <= \<const0>\;
s_axi_rdata(508) <= \<const0>\;
s_axi_rdata(507) <= \<const0>\;
s_axi_rdata(506) <= \<const0>\;
s_axi_rdata(505) <= \<const0>\;
s_axi_rdata(504) <= \<const0>\;
s_axi_rdata(503) <= \<const0>\;
s_axi_rdata(502) <= \<const0>\;
s_axi_rdata(501) <= \<const0>\;
s_axi_rdata(500) <= \<const0>\;
s_axi_rdata(499) <= \<const0>\;
s_axi_rdata(498) <= \<const0>\;
s_axi_rdata(497) <= \<const0>\;
s_axi_rdata(496) <= \<const0>\;
s_axi_rdata(495) <= \<const0>\;
s_axi_rdata(494) <= \<const0>\;
s_axi_rdata(493) <= \<const0>\;
s_axi_rdata(492) <= \<const0>\;
s_axi_rdata(491) <= \<const0>\;
s_axi_rdata(490) <= \<const0>\;
s_axi_rdata(489) <= \<const0>\;
s_axi_rdata(488) <= \<const0>\;
s_axi_rdata(487) <= \<const0>\;
s_axi_rdata(486) <= \<const0>\;
s_axi_rdata(485) <= \<const0>\;
s_axi_rdata(484) <= \<const0>\;
s_axi_rdata(483) <= \<const0>\;
s_axi_rdata(482) <= \<const0>\;
s_axi_rdata(481) <= \<const0>\;
s_axi_rdata(480) <= \<const0>\;
s_axi_rdata(479) <= \<const0>\;
s_axi_rdata(478) <= \<const0>\;
s_axi_rdata(477) <= \<const0>\;
s_axi_rdata(476) <= \<const0>\;
s_axi_rdata(475) <= \<const0>\;
s_axi_rdata(474) <= \<const0>\;
s_axi_rdata(473) <= \<const0>\;
s_axi_rdata(472) <= \<const0>\;
s_axi_rdata(471) <= \<const0>\;
s_axi_rdata(470) <= \<const0>\;
s_axi_rdata(469) <= \<const0>\;
s_axi_rdata(468) <= \<const0>\;
s_axi_rdata(467) <= \<const0>\;
s_axi_rdata(466) <= \<const0>\;
s_axi_rdata(465) <= \<const0>\;
s_axi_rdata(464) <= \<const0>\;
s_axi_rdata(463) <= \<const0>\;
s_axi_rdata(462) <= \<const0>\;
s_axi_rdata(461) <= \<const0>\;
s_axi_rdata(460) <= \<const0>\;
s_axi_rdata(459) <= \<const0>\;
s_axi_rdata(458) <= \<const0>\;
s_axi_rdata(457) <= \<const0>\;
s_axi_rdata(456) <= \<const0>\;
s_axi_rdata(455) <= \<const0>\;
s_axi_rdata(454) <= \<const0>\;
s_axi_rdata(453) <= \<const0>\;
s_axi_rdata(452) <= \<const0>\;
s_axi_rdata(451) <= \<const0>\;
s_axi_rdata(450) <= \<const0>\;
s_axi_rdata(449) <= \<const0>\;
s_axi_rdata(448) <= \<const0>\;
s_axi_rdata(447) <= \<const0>\;
s_axi_rdata(446) <= \<const0>\;
s_axi_rdata(445) <= \<const0>\;
s_axi_rdata(444) <= \<const0>\;
s_axi_rdata(443) <= \<const0>\;
s_axi_rdata(442) <= \<const0>\;
s_axi_rdata(441) <= \<const0>\;
s_axi_rdata(440) <= \<const0>\;
s_axi_rdata(439) <= \<const0>\;
s_axi_rdata(438) <= \<const0>\;
s_axi_rdata(437) <= \<const0>\;
s_axi_rdata(436) <= \<const0>\;
s_axi_rdata(435) <= \<const0>\;
s_axi_rdata(434) <= \<const0>\;
s_axi_rdata(433) <= \<const0>\;
s_axi_rdata(432) <= \<const0>\;
s_axi_rdata(431) <= \<const0>\;
s_axi_rdata(430) <= \<const0>\;
s_axi_rdata(429) <= \<const0>\;
s_axi_rdata(428) <= \<const0>\;
s_axi_rdata(427) <= \<const0>\;
s_axi_rdata(426) <= \<const0>\;
s_axi_rdata(425) <= \<const0>\;
s_axi_rdata(424) <= \<const0>\;
s_axi_rdata(423) <= \<const0>\;
s_axi_rdata(422) <= \<const0>\;
s_axi_rdata(421) <= \<const0>\;
s_axi_rdata(420) <= \<const0>\;
s_axi_rdata(419) <= \<const0>\;
s_axi_rdata(418) <= \<const0>\;
s_axi_rdata(417) <= \<const0>\;
s_axi_rdata(416) <= \<const0>\;
s_axi_rdata(415) <= \<const0>\;
s_axi_rdata(414) <= \<const0>\;
s_axi_rdata(413) <= \<const0>\;
s_axi_rdata(412) <= \<const0>\;
s_axi_rdata(411) <= \<const0>\;
s_axi_rdata(410) <= \<const0>\;
s_axi_rdata(409) <= \<const0>\;
s_axi_rdata(408) <= \<const0>\;
s_axi_rdata(407) <= \<const0>\;
s_axi_rdata(406) <= \<const0>\;
s_axi_rdata(405) <= \<const0>\;
s_axi_rdata(404) <= \<const0>\;
s_axi_rdata(403) <= \<const0>\;
s_axi_rdata(402) <= \<const0>\;
s_axi_rdata(401) <= \<const0>\;
s_axi_rdata(400) <= \<const0>\;
s_axi_rdata(399) <= \<const0>\;
s_axi_rdata(398) <= \<const0>\;
s_axi_rdata(397) <= \<const0>\;
s_axi_rdata(396) <= \<const0>\;
s_axi_rdata(395) <= \<const0>\;
s_axi_rdata(394) <= \<const0>\;
s_axi_rdata(393) <= \<const0>\;
s_axi_rdata(392) <= \<const0>\;
s_axi_rdata(391) <= \<const0>\;
s_axi_rdata(390) <= \<const0>\;
s_axi_rdata(389) <= \<const0>\;
s_axi_rdata(388) <= \<const0>\;
s_axi_rdata(387) <= \<const0>\;
s_axi_rdata(386) <= \<const0>\;
s_axi_rdata(385) <= \<const0>\;
s_axi_rdata(384) <= \<const0>\;
s_axi_rdata(383) <= \<const0>\;
s_axi_rdata(382) <= \<const0>\;
s_axi_rdata(381) <= \<const0>\;
s_axi_rdata(380) <= \<const0>\;
s_axi_rdata(379) <= \<const0>\;
s_axi_rdata(378) <= \<const0>\;
s_axi_rdata(377) <= \<const0>\;
s_axi_rdata(376) <= \<const0>\;
s_axi_rdata(375) <= \<const0>\;
s_axi_rdata(374) <= \<const0>\;
s_axi_rdata(373) <= \<const0>\;
s_axi_rdata(372) <= \<const0>\;
s_axi_rdata(371) <= \<const0>\;
s_axi_rdata(370) <= \<const0>\;
s_axi_rdata(369) <= \<const0>\;
s_axi_rdata(368) <= \<const0>\;
s_axi_rdata(367) <= \<const0>\;
s_axi_rdata(366) <= \<const0>\;
s_axi_rdata(365) <= \<const0>\;
s_axi_rdata(364) <= \<const0>\;
s_axi_rdata(363) <= \<const0>\;
s_axi_rdata(362) <= \<const0>\;
s_axi_rdata(361) <= \<const0>\;
s_axi_rdata(360) <= \<const0>\;
s_axi_rdata(359) <= \<const0>\;
s_axi_rdata(358) <= \<const0>\;
s_axi_rdata(357) <= \<const0>\;
s_axi_rdata(356) <= \<const0>\;
s_axi_rdata(355) <= \<const0>\;
s_axi_rdata(354) <= \<const0>\;
s_axi_rdata(353) <= \<const0>\;
s_axi_rdata(352) <= \<const0>\;
s_axi_rdata(351) <= \<const0>\;
s_axi_rdata(350) <= \<const0>\;
s_axi_rdata(349) <= \<const0>\;
s_axi_rdata(348) <= \<const0>\;
s_axi_rdata(347) <= \<const0>\;
s_axi_rdata(346) <= \<const0>\;
s_axi_rdata(345) <= \<const0>\;
s_axi_rdata(344) <= \<const0>\;
s_axi_rdata(343) <= \<const0>\;
s_axi_rdata(342) <= \<const0>\;
s_axi_rdata(341) <= \<const0>\;
s_axi_rdata(340) <= \<const0>\;
s_axi_rdata(339) <= \<const0>\;
s_axi_rdata(338) <= \<const0>\;
s_axi_rdata(337) <= \<const0>\;
s_axi_rdata(336) <= \<const0>\;
s_axi_rdata(335) <= \<const0>\;
s_axi_rdata(334) <= \<const0>\;
s_axi_rdata(333) <= \<const0>\;
s_axi_rdata(332) <= \<const0>\;
s_axi_rdata(331) <= \<const0>\;
s_axi_rdata(330) <= \<const0>\;
s_axi_rdata(329) <= \<const0>\;
s_axi_rdata(328) <= \<const0>\;
s_axi_rdata(327) <= \<const0>\;
s_axi_rdata(326) <= \<const0>\;
s_axi_rdata(325) <= \<const0>\;
s_axi_rdata(324) <= \<const0>\;
s_axi_rdata(323) <= \<const0>\;
s_axi_rdata(322) <= \<const0>\;
s_axi_rdata(321) <= \<const0>\;
s_axi_rdata(320) <= \<const0>\;
s_axi_rdata(319) <= \<const0>\;
s_axi_rdata(318) <= \<const0>\;
s_axi_rdata(317) <= \<const0>\;
s_axi_rdata(316) <= \<const0>\;
s_axi_rdata(315) <= \<const0>\;
s_axi_rdata(314) <= \<const0>\;
s_axi_rdata(313) <= \<const0>\;
s_axi_rdata(312) <= \<const0>\;
s_axi_rdata(311) <= \<const0>\;
s_axi_rdata(310) <= \<const0>\;
s_axi_rdata(309) <= \<const0>\;
s_axi_rdata(308) <= \<const0>\;
s_axi_rdata(307) <= \<const0>\;
s_axi_rdata(306) <= \<const0>\;
s_axi_rdata(305) <= \<const0>\;
s_axi_rdata(304) <= \<const0>\;
s_axi_rdata(303) <= \<const0>\;
s_axi_rdata(302) <= \<const0>\;
s_axi_rdata(301) <= \<const0>\;
s_axi_rdata(300) <= \<const0>\;
s_axi_rdata(299) <= \<const0>\;
s_axi_rdata(298) <= \<const0>\;
s_axi_rdata(297) <= \<const0>\;
s_axi_rdata(296) <= \<const0>\;
s_axi_rdata(295) <= \<const0>\;
s_axi_rdata(294) <= \<const0>\;
s_axi_rdata(293) <= \<const0>\;
s_axi_rdata(292) <= \<const0>\;
s_axi_rdata(291) <= \<const0>\;
s_axi_rdata(290) <= \<const0>\;
s_axi_rdata(289) <= \<const0>\;
s_axi_rdata(288) <= \<const0>\;
s_axi_rdata(287) <= \<const0>\;
s_axi_rdata(286) <= \<const0>\;
s_axi_rdata(285) <= \<const0>\;
s_axi_rdata(284) <= \<const0>\;
s_axi_rdata(283) <= \<const0>\;
s_axi_rdata(282) <= \<const0>\;
s_axi_rdata(281) <= \<const0>\;
s_axi_rdata(280) <= \<const0>\;
s_axi_rdata(279) <= \<const0>\;
s_axi_rdata(278) <= \<const0>\;
s_axi_rdata(277) <= \<const0>\;
s_axi_rdata(276) <= \<const0>\;
s_axi_rdata(275) <= \<const0>\;
s_axi_rdata(274) <= \<const0>\;
s_axi_rdata(273) <= \<const0>\;
s_axi_rdata(272) <= \<const0>\;
s_axi_rdata(271) <= \<const0>\;
s_axi_rdata(270) <= \<const0>\;
s_axi_rdata(269) <= \<const0>\;
s_axi_rdata(268) <= \<const0>\;
s_axi_rdata(267) <= \<const0>\;
s_axi_rdata(266) <= \<const0>\;
s_axi_rdata(265) <= \<const0>\;
s_axi_rdata(264) <= \<const0>\;
s_axi_rdata(263) <= \<const0>\;
s_axi_rdata(262) <= \<const0>\;
s_axi_rdata(261) <= \<const0>\;
s_axi_rdata(260) <= \<const0>\;
s_axi_rdata(259) <= \<const0>\;
s_axi_rdata(258) <= \<const0>\;
s_axi_rdata(257) <= \<const0>\;
s_axi_rdata(256) <= \<const0>\;
s_axi_rdata(255) <= \<const0>\;
s_axi_rdata(254) <= \<const0>\;
s_axi_rdata(253) <= \<const0>\;
s_axi_rdata(252) <= \<const0>\;
s_axi_rdata(251) <= \<const0>\;
s_axi_rdata(250) <= \<const0>\;
s_axi_rdata(249) <= \<const0>\;
s_axi_rdata(248) <= \<const0>\;
s_axi_rdata(247) <= \<const0>\;
s_axi_rdata(246) <= \<const0>\;
s_axi_rdata(245) <= \<const0>\;
s_axi_rdata(244) <= \<const0>\;
s_axi_rdata(243) <= \<const0>\;
s_axi_rdata(242) <= \<const0>\;
s_axi_rdata(241) <= \<const0>\;
s_axi_rdata(240) <= \<const0>\;
s_axi_rdata(239) <= \<const0>\;
s_axi_rdata(238) <= \<const0>\;
s_axi_rdata(237) <= \<const0>\;
s_axi_rdata(236) <= \<const0>\;
s_axi_rdata(235) <= \<const0>\;
s_axi_rdata(234) <= \<const0>\;
s_axi_rdata(233) <= \<const0>\;
s_axi_rdata(232) <= \<const0>\;
s_axi_rdata(231) <= \<const0>\;
s_axi_rdata(230) <= \<const0>\;
s_axi_rdata(229) <= \<const0>\;
s_axi_rdata(228) <= \<const0>\;
s_axi_rdata(227) <= \<const0>\;
s_axi_rdata(226) <= \<const0>\;
s_axi_rdata(225) <= \<const0>\;
s_axi_rdata(224) <= \<const0>\;
s_axi_rdata(223) <= \<const0>\;
s_axi_rdata(222) <= \<const0>\;
s_axi_rdata(221) <= \<const0>\;
s_axi_rdata(220) <= \<const0>\;
s_axi_rdata(219) <= \<const0>\;
s_axi_rdata(218) <= \<const0>\;
s_axi_rdata(217) <= \<const0>\;
s_axi_rdata(216) <= \<const0>\;
s_axi_rdata(215) <= \<const0>\;
s_axi_rdata(214) <= \<const0>\;
s_axi_rdata(213) <= \<const0>\;
s_axi_rdata(212) <= \<const0>\;
s_axi_rdata(211) <= \<const0>\;
s_axi_rdata(210) <= \<const0>\;
s_axi_rdata(209) <= \<const0>\;
s_axi_rdata(208) <= \<const0>\;
s_axi_rdata(207) <= \<const0>\;
s_axi_rdata(206) <= \<const0>\;
s_axi_rdata(205) <= \<const0>\;
s_axi_rdata(204) <= \<const0>\;
s_axi_rdata(203) <= \<const0>\;
s_axi_rdata(202) <= \<const0>\;
s_axi_rdata(201) <= \<const0>\;
s_axi_rdata(200) <= \<const0>\;
s_axi_rdata(199) <= \<const0>\;
s_axi_rdata(198) <= \<const0>\;
s_axi_rdata(197) <= \<const0>\;
s_axi_rdata(196) <= \<const0>\;
s_axi_rdata(195) <= \<const0>\;
s_axi_rdata(194) <= \<const0>\;
s_axi_rdata(193) <= \<const0>\;
s_axi_rdata(192) <= \<const0>\;
s_axi_rdata(191) <= \<const0>\;
s_axi_rdata(190) <= \<const0>\;
s_axi_rdata(189) <= \<const0>\;
s_axi_rdata(188) <= \<const0>\;
s_axi_rdata(187) <= \<const0>\;
s_axi_rdata(186) <= \<const0>\;
s_axi_rdata(185) <= \<const0>\;
s_axi_rdata(184) <= \<const0>\;
s_axi_rdata(183) <= \<const0>\;
s_axi_rdata(182) <= \<const0>\;
s_axi_rdata(181) <= \<const0>\;
s_axi_rdata(180) <= \<const0>\;
s_axi_rdata(179) <= \<const0>\;
s_axi_rdata(178) <= \<const0>\;
s_axi_rdata(177) <= \<const0>\;
s_axi_rdata(176) <= \<const0>\;
s_axi_rdata(175) <= \<const0>\;
s_axi_rdata(174) <= \<const0>\;
s_axi_rdata(173) <= \<const0>\;
s_axi_rdata(172) <= \<const0>\;
s_axi_rdata(171) <= \<const0>\;
s_axi_rdata(170) <= \<const0>\;
s_axi_rdata(169) <= \<const0>\;
s_axi_rdata(168) <= \<const0>\;
s_axi_rdata(167) <= \<const0>\;
s_axi_rdata(166) <= \<const0>\;
s_axi_rdata(165) <= \<const0>\;
s_axi_rdata(164) <= \<const0>\;
s_axi_rdata(163) <= \<const0>\;
s_axi_rdata(162) <= \<const0>\;
s_axi_rdata(161) <= \<const0>\;
s_axi_rdata(160) <= \<const0>\;
s_axi_rdata(159) <= \<const0>\;
s_axi_rdata(158) <= \<const0>\;
s_axi_rdata(157) <= \<const0>\;
s_axi_rdata(156) <= \<const0>\;
s_axi_rdata(155) <= \<const0>\;
s_axi_rdata(154) <= \<const0>\;
s_axi_rdata(153) <= \<const0>\;
s_axi_rdata(152) <= \<const0>\;
s_axi_rdata(151) <= \<const0>\;
s_axi_rdata(150) <= \<const0>\;
s_axi_rdata(149) <= \<const0>\;
s_axi_rdata(148) <= \<const0>\;
s_axi_rdata(147) <= \<const0>\;
s_axi_rdata(146) <= \<const0>\;
s_axi_rdata(145) <= \<const0>\;
s_axi_rdata(144) <= \<const0>\;
s_axi_rdata(143) <= \<const0>\;
s_axi_rdata(142) <= \<const0>\;
s_axi_rdata(141) <= \<const0>\;
s_axi_rdata(140) <= \<const0>\;
s_axi_rdata(139) <= \<const0>\;
s_axi_rdata(138) <= \<const0>\;
s_axi_rdata(137) <= \<const0>\;
s_axi_rdata(136) <= \<const0>\;
s_axi_rdata(135) <= \<const0>\;
s_axi_rdata(134) <= \<const0>\;
s_axi_rdata(133) <= \<const0>\;
s_axi_rdata(132) <= \<const0>\;
s_axi_rdata(131) <= \<const0>\;
s_axi_rdata(130) <= \<const0>\;
s_axi_rdata(129) <= \<const0>\;
s_axi_rdata(128) <= \<const0>\;
s_axi_rdata(127) <= \<const0>\;
s_axi_rdata(126) <= \<const0>\;
s_axi_rdata(125) <= \<const0>\;
s_axi_rdata(124) <= \<const0>\;
s_axi_rdata(123) <= \<const0>\;
s_axi_rdata(122) <= \<const0>\;
s_axi_rdata(121) <= \<const0>\;
s_axi_rdata(120) <= \<const0>\;
s_axi_rdata(119) <= \<const0>\;
s_axi_rdata(118) <= \<const0>\;
s_axi_rdata(117) <= \<const0>\;
s_axi_rdata(116) <= \<const0>\;
s_axi_rdata(115) <= \<const0>\;
s_axi_rdata(114) <= \<const0>\;
s_axi_rdata(113) <= \<const0>\;
s_axi_rdata(112) <= \<const0>\;
s_axi_rdata(111) <= \<const0>\;
s_axi_rdata(110) <= \<const0>\;
s_axi_rdata(109) <= \<const0>\;
s_axi_rdata(108) <= \<const0>\;
s_axi_rdata(107) <= \<const0>\;
s_axi_rdata(106) <= \<const0>\;
s_axi_rdata(105) <= \<const0>\;
s_axi_rdata(104) <= \<const0>\;
s_axi_rdata(103) <= \<const0>\;
s_axi_rdata(102) <= \<const0>\;
s_axi_rdata(101) <= \<const0>\;
s_axi_rdata(100) <= \<const0>\;
s_axi_rdata(99) <= \<const0>\;
s_axi_rdata(98) <= \<const0>\;
s_axi_rdata(97) <= \<const0>\;
s_axi_rdata(96) <= \<const0>\;
s_axi_rdata(95) <= \<const0>\;
s_axi_rdata(94) <= \<const0>\;
s_axi_rdata(93) <= \<const0>\;
s_axi_rdata(92) <= \<const0>\;
s_axi_rdata(91) <= \<const0>\;
s_axi_rdata(90) <= \<const0>\;
s_axi_rdata(89) <= \<const0>\;
s_axi_rdata(88) <= \<const0>\;
s_axi_rdata(87) <= \<const0>\;
s_axi_rdata(86) <= \<const0>\;
s_axi_rdata(85) <= \<const0>\;
s_axi_rdata(84) <= \<const0>\;
s_axi_rdata(83) <= \<const0>\;
s_axi_rdata(82) <= \<const0>\;
s_axi_rdata(81) <= \<const0>\;
s_axi_rdata(80) <= \<const0>\;
s_axi_rdata(79) <= \<const0>\;
s_axi_rdata(78) <= \<const0>\;
s_axi_rdata(77) <= \<const0>\;
s_axi_rdata(76) <= \<const0>\;
s_axi_rdata(75) <= \<const0>\;
s_axi_rdata(74) <= \<const0>\;
s_axi_rdata(73) <= \<const0>\;
s_axi_rdata(72) <= \<const0>\;
s_axi_rdata(71) <= \<const0>\;
s_axi_rdata(70) <= \<const0>\;
s_axi_rdata(69) <= \<const0>\;
s_axi_rdata(68) <= \<const0>\;
s_axi_rdata(67) <= \<const0>\;
s_axi_rdata(66) <= \<const0>\;
s_axi_rdata(65) <= \<const0>\;
s_axi_rdata(64) <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.PSelect_blk_mem_gen_v8_2_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of PSelect : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of PSelect : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of PSelect : entity is "blk_mem_gen_v8_2,Vivado 2014.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of PSelect : entity is "PSelect,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of PSelect : entity is "PSelect,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=PSelect.mif,C_INIT_FILE=PSelect.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}";
end PSelect;
architecture STRUCTURE of PSelect is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "22";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 60.4532 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "PSelect.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "PSelect.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 800;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 800;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 800;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\PSelect_blk_mem_gen_v8_2__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(799) => '0',
dina(798) => '0',
dina(797) => '0',
dina(796) => '0',
dina(795) => '0',
dina(794) => '0',
dina(793) => '0',
dina(792) => '0',
dina(791) => '0',
dina(790) => '0',
dina(789) => '0',
dina(788) => '0',
dina(787) => '0',
dina(786) => '0',
dina(785) => '0',
dina(784) => '0',
dina(783) => '0',
dina(782) => '0',
dina(781) => '0',
dina(780) => '0',
dina(779) => '0',
dina(778) => '0',
dina(777) => '0',
dina(776) => '0',
dina(775) => '0',
dina(774) => '0',
dina(773) => '0',
dina(772) => '0',
dina(771) => '0',
dina(770) => '0',
dina(769) => '0',
dina(768) => '0',
dina(767) => '0',
dina(766) => '0',
dina(765) => '0',
dina(764) => '0',
dina(763) => '0',
dina(762) => '0',
dina(761) => '0',
dina(760) => '0',
dina(759) => '0',
dina(758) => '0',
dina(757) => '0',
dina(756) => '0',
dina(755) => '0',
dina(754) => '0',
dina(753) => '0',
dina(752) => '0',
dina(751) => '0',
dina(750) => '0',
dina(749) => '0',
dina(748) => '0',
dina(747) => '0',
dina(746) => '0',
dina(745) => '0',
dina(744) => '0',
dina(743) => '0',
dina(742) => '0',
dina(741) => '0',
dina(740) => '0',
dina(739) => '0',
dina(738) => '0',
dina(737) => '0',
dina(736) => '0',
dina(735) => '0',
dina(734) => '0',
dina(733) => '0',
dina(732) => '0',
dina(731) => '0',
dina(730) => '0',
dina(729) => '0',
dina(728) => '0',
dina(727) => '0',
dina(726) => '0',
dina(725) => '0',
dina(724) => '0',
dina(723) => '0',
dina(722) => '0',
dina(721) => '0',
dina(720) => '0',
dina(719) => '0',
dina(718) => '0',
dina(717) => '0',
dina(716) => '0',
dina(715) => '0',
dina(714) => '0',
dina(713) => '0',
dina(712) => '0',
dina(711) => '0',
dina(710) => '0',
dina(709) => '0',
dina(708) => '0',
dina(707) => '0',
dina(706) => '0',
dina(705) => '0',
dina(704) => '0',
dina(703) => '0',
dina(702) => '0',
dina(701) => '0',
dina(700) => '0',
dina(699) => '0',
dina(698) => '0',
dina(697) => '0',
dina(696) => '0',
dina(695) => '0',
dina(694) => '0',
dina(693) => '0',
dina(692) => '0',
dina(691) => '0',
dina(690) => '0',
dina(689) => '0',
dina(688) => '0',
dina(687) => '0',
dina(686) => '0',
dina(685) => '0',
dina(684) => '0',
dina(683) => '0',
dina(682) => '0',
dina(681) => '0',
dina(680) => '0',
dina(679) => '0',
dina(678) => '0',
dina(677) => '0',
dina(676) => '0',
dina(675) => '0',
dina(674) => '0',
dina(673) => '0',
dina(672) => '0',
dina(671) => '0',
dina(670) => '0',
dina(669) => '0',
dina(668) => '0',
dina(667) => '0',
dina(666) => '0',
dina(665) => '0',
dina(664) => '0',
dina(663) => '0',
dina(662) => '0',
dina(661) => '0',
dina(660) => '0',
dina(659) => '0',
dina(658) => '0',
dina(657) => '0',
dina(656) => '0',
dina(655) => '0',
dina(654) => '0',
dina(653) => '0',
dina(652) => '0',
dina(651) => '0',
dina(650) => '0',
dina(649) => '0',
dina(648) => '0',
dina(647) => '0',
dina(646) => '0',
dina(645) => '0',
dina(644) => '0',
dina(643) => '0',
dina(642) => '0',
dina(641) => '0',
dina(640) => '0',
dina(639) => '0',
dina(638) => '0',
dina(637) => '0',
dina(636) => '0',
dina(635) => '0',
dina(634) => '0',
dina(633) => '0',
dina(632) => '0',
dina(631) => '0',
dina(630) => '0',
dina(629) => '0',
dina(628) => '0',
dina(627) => '0',
dina(626) => '0',
dina(625) => '0',
dina(624) => '0',
dina(623) => '0',
dina(622) => '0',
dina(621) => '0',
dina(620) => '0',
dina(619) => '0',
dina(618) => '0',
dina(617) => '0',
dina(616) => '0',
dina(615) => '0',
dina(614) => '0',
dina(613) => '0',
dina(612) => '0',
dina(611) => '0',
dina(610) => '0',
dina(609) => '0',
dina(608) => '0',
dina(607) => '0',
dina(606) => '0',
dina(605) => '0',
dina(604) => '0',
dina(603) => '0',
dina(602) => '0',
dina(601) => '0',
dina(600) => '0',
dina(599) => '0',
dina(598) => '0',
dina(597) => '0',
dina(596) => '0',
dina(595) => '0',
dina(594) => '0',
dina(593) => '0',
dina(592) => '0',
dina(591) => '0',
dina(590) => '0',
dina(589) => '0',
dina(588) => '0',
dina(587) => '0',
dina(586) => '0',
dina(585) => '0',
dina(584) => '0',
dina(583) => '0',
dina(582) => '0',
dina(581) => '0',
dina(580) => '0',
dina(579) => '0',
dina(578) => '0',
dina(577) => '0',
dina(576) => '0',
dina(575) => '0',
dina(574) => '0',
dina(573) => '0',
dina(572) => '0',
dina(571) => '0',
dina(570) => '0',
dina(569) => '0',
dina(568) => '0',
dina(567) => '0',
dina(566) => '0',
dina(565) => '0',
dina(564) => '0',
dina(563) => '0',
dina(562) => '0',
dina(561) => '0',
dina(560) => '0',
dina(559) => '0',
dina(558) => '0',
dina(557) => '0',
dina(556) => '0',
dina(555) => '0',
dina(554) => '0',
dina(553) => '0',
dina(552) => '0',
dina(551) => '0',
dina(550) => '0',
dina(549) => '0',
dina(548) => '0',
dina(547) => '0',
dina(546) => '0',
dina(545) => '0',
dina(544) => '0',
dina(543) => '0',
dina(542) => '0',
dina(541) => '0',
dina(540) => '0',
dina(539) => '0',
dina(538) => '0',
dina(537) => '0',
dina(536) => '0',
dina(535) => '0',
dina(534) => '0',
dina(533) => '0',
dina(532) => '0',
dina(531) => '0',
dina(530) => '0',
dina(529) => '0',
dina(528) => '0',
dina(527) => '0',
dina(526) => '0',
dina(525) => '0',
dina(524) => '0',
dina(523) => '0',
dina(522) => '0',
dina(521) => '0',
dina(520) => '0',
dina(519) => '0',
dina(518) => '0',
dina(517) => '0',
dina(516) => '0',
dina(515) => '0',
dina(514) => '0',
dina(513) => '0',
dina(512) => '0',
dina(511) => '0',
dina(510) => '0',
dina(509) => '0',
dina(508) => '0',
dina(507) => '0',
dina(506) => '0',
dina(505) => '0',
dina(504) => '0',
dina(503) => '0',
dina(502) => '0',
dina(501) => '0',
dina(500) => '0',
dina(499) => '0',
dina(498) => '0',
dina(497) => '0',
dina(496) => '0',
dina(495) => '0',
dina(494) => '0',
dina(493) => '0',
dina(492) => '0',
dina(491) => '0',
dina(490) => '0',
dina(489) => '0',
dina(488) => '0',
dina(487) => '0',
dina(486) => '0',
dina(485) => '0',
dina(484) => '0',
dina(483) => '0',
dina(482) => '0',
dina(481) => '0',
dina(480) => '0',
dina(479) => '0',
dina(478) => '0',
dina(477) => '0',
dina(476) => '0',
dina(475) => '0',
dina(474) => '0',
dina(473) => '0',
dina(472) => '0',
dina(471) => '0',
dina(470) => '0',
dina(469) => '0',
dina(468) => '0',
dina(467) => '0',
dina(466) => '0',
dina(465) => '0',
dina(464) => '0',
dina(463) => '0',
dina(462) => '0',
dina(461) => '0',
dina(460) => '0',
dina(459) => '0',
dina(458) => '0',
dina(457) => '0',
dina(456) => '0',
dina(455) => '0',
dina(454) => '0',
dina(453) => '0',
dina(452) => '0',
dina(451) => '0',
dina(450) => '0',
dina(449) => '0',
dina(448) => '0',
dina(447) => '0',
dina(446) => '0',
dina(445) => '0',
dina(444) => '0',
dina(443) => '0',
dina(442) => '0',
dina(441) => '0',
dina(440) => '0',
dina(439) => '0',
dina(438) => '0',
dina(437) => '0',
dina(436) => '0',
dina(435) => '0',
dina(434) => '0',
dina(433) => '0',
dina(432) => '0',
dina(431) => '0',
dina(430) => '0',
dina(429) => '0',
dina(428) => '0',
dina(427) => '0',
dina(426) => '0',
dina(425) => '0',
dina(424) => '0',
dina(423) => '0',
dina(422) => '0',
dina(421) => '0',
dina(420) => '0',
dina(419) => '0',
dina(418) => '0',
dina(417) => '0',
dina(416) => '0',
dina(415) => '0',
dina(414) => '0',
dina(413) => '0',
dina(412) => '0',
dina(411) => '0',
dina(410) => '0',
dina(409) => '0',
dina(408) => '0',
dina(407) => '0',
dina(406) => '0',
dina(405) => '0',
dina(404) => '0',
dina(403) => '0',
dina(402) => '0',
dina(401) => '0',
dina(400) => '0',
dina(399) => '0',
dina(398) => '0',
dina(397) => '0',
dina(396) => '0',
dina(395) => '0',
dina(394) => '0',
dina(393) => '0',
dina(392) => '0',
dina(391) => '0',
dina(390) => '0',
dina(389) => '0',
dina(388) => '0',
dina(387) => '0',
dina(386) => '0',
dina(385) => '0',
dina(384) => '0',
dina(383) => '0',
dina(382) => '0',
dina(381) => '0',
dina(380) => '0',
dina(379) => '0',
dina(378) => '0',
dina(377) => '0',
dina(376) => '0',
dina(375) => '0',
dina(374) => '0',
dina(373) => '0',
dina(372) => '0',
dina(371) => '0',
dina(370) => '0',
dina(369) => '0',
dina(368) => '0',
dina(367) => '0',
dina(366) => '0',
dina(365) => '0',
dina(364) => '0',
dina(363) => '0',
dina(362) => '0',
dina(361) => '0',
dina(360) => '0',
dina(359) => '0',
dina(358) => '0',
dina(357) => '0',
dina(356) => '0',
dina(355) => '0',
dina(354) => '0',
dina(353) => '0',
dina(352) => '0',
dina(351) => '0',
dina(350) => '0',
dina(349) => '0',
dina(348) => '0',
dina(347) => '0',
dina(346) => '0',
dina(345) => '0',
dina(344) => '0',
dina(343) => '0',
dina(342) => '0',
dina(341) => '0',
dina(340) => '0',
dina(339) => '0',
dina(338) => '0',
dina(337) => '0',
dina(336) => '0',
dina(335) => '0',
dina(334) => '0',
dina(333) => '0',
dina(332) => '0',
dina(331) => '0',
dina(330) => '0',
dina(329) => '0',
dina(328) => '0',
dina(327) => '0',
dina(326) => '0',
dina(325) => '0',
dina(324) => '0',
dina(323) => '0',
dina(322) => '0',
dina(321) => '0',
dina(320) => '0',
dina(319) => '0',
dina(318) => '0',
dina(317) => '0',
dina(316) => '0',
dina(315) => '0',
dina(314) => '0',
dina(313) => '0',
dina(312) => '0',
dina(311) => '0',
dina(310) => '0',
dina(309) => '0',
dina(308) => '0',
dina(307) => '0',
dina(306) => '0',
dina(305) => '0',
dina(304) => '0',
dina(303) => '0',
dina(302) => '0',
dina(301) => '0',
dina(300) => '0',
dina(299) => '0',
dina(298) => '0',
dina(297) => '0',
dina(296) => '0',
dina(295) => '0',
dina(294) => '0',
dina(293) => '0',
dina(292) => '0',
dina(291) => '0',
dina(290) => '0',
dina(289) => '0',
dina(288) => '0',
dina(287) => '0',
dina(286) => '0',
dina(285) => '0',
dina(284) => '0',
dina(283) => '0',
dina(282) => '0',
dina(281) => '0',
dina(280) => '0',
dina(279) => '0',
dina(278) => '0',
dina(277) => '0',
dina(276) => '0',
dina(275) => '0',
dina(274) => '0',
dina(273) => '0',
dina(272) => '0',
dina(271) => '0',
dina(270) => '0',
dina(269) => '0',
dina(268) => '0',
dina(267) => '0',
dina(266) => '0',
dina(265) => '0',
dina(264) => '0',
dina(263) => '0',
dina(262) => '0',
dina(261) => '0',
dina(260) => '0',
dina(259) => '0',
dina(258) => '0',
dina(257) => '0',
dina(256) => '0',
dina(255) => '0',
dina(254) => '0',
dina(253) => '0',
dina(252) => '0',
dina(251) => '0',
dina(250) => '0',
dina(249) => '0',
dina(248) => '0',
dina(247) => '0',
dina(246) => '0',
dina(245) => '0',
dina(244) => '0',
dina(243) => '0',
dina(242) => '0',
dina(241) => '0',
dina(240) => '0',
dina(239) => '0',
dina(238) => '0',
dina(237) => '0',
dina(236) => '0',
dina(235) => '0',
dina(234) => '0',
dina(233) => '0',
dina(232) => '0',
dina(231) => '0',
dina(230) => '0',
dina(229) => '0',
dina(228) => '0',
dina(227) => '0',
dina(226) => '0',
dina(225) => '0',
dina(224) => '0',
dina(223) => '0',
dina(222) => '0',
dina(221) => '0',
dina(220) => '0',
dina(219) => '0',
dina(218) => '0',
dina(217) => '0',
dina(216) => '0',
dina(215) => '0',
dina(214) => '0',
dina(213) => '0',
dina(212) => '0',
dina(211) => '0',
dina(210) => '0',
dina(209) => '0',
dina(208) => '0',
dina(207) => '0',
dina(206) => '0',
dina(205) => '0',
dina(204) => '0',
dina(203) => '0',
dina(202) => '0',
dina(201) => '0',
dina(200) => '0',
dina(199) => '0',
dina(198) => '0',
dina(197) => '0',
dina(196) => '0',
dina(195) => '0',
dina(194) => '0',
dina(193) => '0',
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dinb(253) => '0',
dinb(252) => '0',
dinb(251) => '0',
dinb(250) => '0',
dinb(249) => '0',
dinb(248) => '0',
dinb(247) => '0',
dinb(246) => '0',
dinb(245) => '0',
dinb(244) => '0',
dinb(243) => '0',
dinb(242) => '0',
dinb(241) => '0',
dinb(240) => '0',
dinb(239) => '0',
dinb(238) => '0',
dinb(237) => '0',
dinb(236) => '0',
dinb(235) => '0',
dinb(234) => '0',
dinb(233) => '0',
dinb(232) => '0',
dinb(231) => '0',
dinb(230) => '0',
dinb(229) => '0',
dinb(228) => '0',
dinb(227) => '0',
dinb(226) => '0',
dinb(225) => '0',
dinb(224) => '0',
dinb(223) => '0',
dinb(222) => '0',
dinb(221) => '0',
dinb(220) => '0',
dinb(219) => '0',
dinb(218) => '0',
dinb(217) => '0',
dinb(216) => '0',
dinb(215) => '0',
dinb(214) => '0',
dinb(213) => '0',
dinb(212) => '0',
dinb(211) => '0',
dinb(210) => '0',
dinb(209) => '0',
dinb(208) => '0',
dinb(207) => '0',
dinb(206) => '0',
dinb(205) => '0',
dinb(204) => '0',
dinb(203) => '0',
dinb(202) => '0',
dinb(201) => '0',
dinb(200) => '0',
dinb(199) => '0',
dinb(198) => '0',
dinb(197) => '0',
dinb(196) => '0',
dinb(195) => '0',
dinb(194) => '0',
dinb(193) => '0',
dinb(192) => '0',
dinb(191) => '0',
dinb(190) => '0',
dinb(189) => '0',
dinb(188) => '0',
dinb(187) => '0',
dinb(186) => '0',
dinb(185) => '0',
dinb(184) => '0',
dinb(183) => '0',
dinb(182) => '0',
dinb(181) => '0',
dinb(180) => '0',
dinb(179) => '0',
dinb(178) => '0',
dinb(177) => '0',
dinb(176) => '0',
dinb(175) => '0',
dinb(174) => '0',
dinb(173) => '0',
dinb(172) => '0',
dinb(171) => '0',
dinb(170) => '0',
dinb(169) => '0',
dinb(168) => '0',
dinb(167) => '0',
dinb(166) => '0',
dinb(165) => '0',
dinb(164) => '0',
dinb(163) => '0',
dinb(162) => '0',
dinb(161) => '0',
dinb(160) => '0',
dinb(159) => '0',
dinb(158) => '0',
dinb(157) => '0',
dinb(156) => '0',
dinb(155) => '0',
dinb(154) => '0',
dinb(153) => '0',
dinb(152) => '0',
dinb(151) => '0',
dinb(150) => '0',
dinb(149) => '0',
dinb(148) => '0',
dinb(147) => '0',
dinb(146) => '0',
dinb(145) => '0',
dinb(144) => '0',
dinb(143) => '0',
dinb(142) => '0',
dinb(141) => '0',
dinb(140) => '0',
dinb(139) => '0',
dinb(138) => '0',
dinb(137) => '0',
dinb(136) => '0',
dinb(135) => '0',
dinb(134) => '0',
dinb(133) => '0',
dinb(132) => '0',
dinb(131) => '0',
dinb(130) => '0',
dinb(129) => '0',
dinb(128) => '0',
dinb(127) => '0',
dinb(126) => '0',
dinb(125) => '0',
dinb(124) => '0',
dinb(123) => '0',
dinb(122) => '0',
dinb(121) => '0',
dinb(120) => '0',
dinb(119) => '0',
dinb(118) => '0',
dinb(117) => '0',
dinb(116) => '0',
dinb(115) => '0',
dinb(114) => '0',
dinb(113) => '0',
dinb(112) => '0',
dinb(111) => '0',
dinb(110) => '0',
dinb(109) => '0',
dinb(108) => '0',
dinb(107) => '0',
dinb(106) => '0',
dinb(105) => '0',
dinb(104) => '0',
dinb(103) => '0',
dinb(102) => '0',
dinb(101) => '0',
dinb(100) => '0',
dinb(99) => '0',
dinb(98) => '0',
dinb(97) => '0',
dinb(96) => '0',
dinb(95) => '0',
dinb(94) => '0',
dinb(93) => '0',
dinb(92) => '0',
dinb(91) => '0',
dinb(90) => '0',
dinb(89) => '0',
dinb(88) => '0',
dinb(87) => '0',
dinb(86) => '0',
dinb(85) => '0',
dinb(84) => '0',
dinb(83) => '0',
dinb(82) => '0',
dinb(81) => '0',
dinb(80) => '0',
dinb(79) => '0',
dinb(78) => '0',
dinb(77) => '0',
dinb(76) => '0',
dinb(75) => '0',
dinb(74) => '0',
dinb(73) => '0',
dinb(72) => '0',
dinb(71) => '0',
dinb(70) => '0',
dinb(69) => '0',
dinb(68) => '0',
dinb(67) => '0',
dinb(66) => '0',
dinb(65) => '0',
dinb(64) => '0',
dinb(63) => '0',
dinb(62) => '0',
dinb(61) => '0',
dinb(60) => '0',
dinb(59) => '0',
dinb(58) => '0',
dinb(57) => '0',
dinb(56) => '0',
dinb(55) => '0',
dinb(54) => '0',
dinb(53) => '0',
dinb(52) => '0',
dinb(51) => '0',
dinb(50) => '0',
dinb(49) => '0',
dinb(48) => '0',
dinb(47) => '0',
dinb(46) => '0',
dinb(45) => '0',
dinb(44) => '0',
dinb(43) => '0',
dinb(42) => '0',
dinb(41) => '0',
dinb(40) => '0',
dinb(39) => '0',
dinb(38) => '0',
dinb(37) => '0',
dinb(36) => '0',
dinb(35) => '0',
dinb(34) => '0',
dinb(33) => '0',
dinb(32) => '0',
dinb(31) => '0',
dinb(30) => '0',
dinb(29) => '0',
dinb(28) => '0',
dinb(27) => '0',
dinb(26) => '0',
dinb(25) => '0',
dinb(24) => '0',
dinb(23) => '0',
dinb(22) => '0',
dinb(21) => '0',
dinb(20) => '0',
dinb(19) => '0',
dinb(18) => '0',
dinb(17) => '0',
dinb(16) => '0',
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(799 downto 0) => douta(799 downto 0),
doutb(799 downto 0) => NLW_U0_doutb_UNCONNECTED(799 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(799 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(799 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(799) => '0',
s_axi_wdata(798) => '0',
s_axi_wdata(797) => '0',
s_axi_wdata(796) => '0',
s_axi_wdata(795) => '0',
s_axi_wdata(794) => '0',
s_axi_wdata(793) => '0',
s_axi_wdata(792) => '0',
s_axi_wdata(791) => '0',
s_axi_wdata(790) => '0',
s_axi_wdata(789) => '0',
s_axi_wdata(788) => '0',
s_axi_wdata(787) => '0',
s_axi_wdata(786) => '0',
s_axi_wdata(785) => '0',
s_axi_wdata(784) => '0',
s_axi_wdata(783) => '0',
s_axi_wdata(782) => '0',
s_axi_wdata(781) => '0',
s_axi_wdata(780) => '0',
s_axi_wdata(779) => '0',
s_axi_wdata(778) => '0',
s_axi_wdata(777) => '0',
s_axi_wdata(776) => '0',
s_axi_wdata(775) => '0',
s_axi_wdata(774) => '0',
s_axi_wdata(773) => '0',
s_axi_wdata(772) => '0',
s_axi_wdata(771) => '0',
s_axi_wdata(770) => '0',
s_axi_wdata(769) => '0',
s_axi_wdata(768) => '0',
s_axi_wdata(767) => '0',
s_axi_wdata(766) => '0',
s_axi_wdata(765) => '0',
s_axi_wdata(764) => '0',
s_axi_wdata(763) => '0',
s_axi_wdata(762) => '0',
s_axi_wdata(761) => '0',
s_axi_wdata(760) => '0',
s_axi_wdata(759) => '0',
s_axi_wdata(758) => '0',
s_axi_wdata(757) => '0',
s_axi_wdata(756) => '0',
s_axi_wdata(755) => '0',
s_axi_wdata(754) => '0',
s_axi_wdata(753) => '0',
s_axi_wdata(752) => '0',
s_axi_wdata(751) => '0',
s_axi_wdata(750) => '0',
s_axi_wdata(749) => '0',
s_axi_wdata(748) => '0',
s_axi_wdata(747) => '0',
s_axi_wdata(746) => '0',
s_axi_wdata(745) => '0',
s_axi_wdata(744) => '0',
s_axi_wdata(743) => '0',
s_axi_wdata(742) => '0',
s_axi_wdata(741) => '0',
s_axi_wdata(740) => '0',
s_axi_wdata(739) => '0',
s_axi_wdata(738) => '0',
s_axi_wdata(737) => '0',
s_axi_wdata(736) => '0',
s_axi_wdata(735) => '0',
s_axi_wdata(734) => '0',
s_axi_wdata(733) => '0',
s_axi_wdata(732) => '0',
s_axi_wdata(731) => '0',
s_axi_wdata(730) => '0',
s_axi_wdata(729) => '0',
s_axi_wdata(728) => '0',
s_axi_wdata(727) => '0',
s_axi_wdata(726) => '0',
s_axi_wdata(725) => '0',
s_axi_wdata(724) => '0',
s_axi_wdata(723) => '0',
s_axi_wdata(722) => '0',
s_axi_wdata(721) => '0',
s_axi_wdata(720) => '0',
s_axi_wdata(719) => '0',
s_axi_wdata(718) => '0',
s_axi_wdata(717) => '0',
s_axi_wdata(716) => '0',
s_axi_wdata(715) => '0',
s_axi_wdata(714) => '0',
s_axi_wdata(713) => '0',
s_axi_wdata(712) => '0',
s_axi_wdata(711) => '0',
s_axi_wdata(710) => '0',
s_axi_wdata(709) => '0',
s_axi_wdata(708) => '0',
s_axi_wdata(707) => '0',
s_axi_wdata(706) => '0',
s_axi_wdata(705) => '0',
s_axi_wdata(704) => '0',
s_axi_wdata(703) => '0',
s_axi_wdata(702) => '0',
s_axi_wdata(701) => '0',
s_axi_wdata(700) => '0',
s_axi_wdata(699) => '0',
s_axi_wdata(698) => '0',
s_axi_wdata(697) => '0',
s_axi_wdata(696) => '0',
s_axi_wdata(695) => '0',
s_axi_wdata(694) => '0',
s_axi_wdata(693) => '0',
s_axi_wdata(692) => '0',
s_axi_wdata(691) => '0',
s_axi_wdata(690) => '0',
s_axi_wdata(689) => '0',
s_axi_wdata(688) => '0',
s_axi_wdata(687) => '0',
s_axi_wdata(686) => '0',
s_axi_wdata(685) => '0',
s_axi_wdata(684) => '0',
s_axi_wdata(683) => '0',
s_axi_wdata(682) => '0',
s_axi_wdata(681) => '0',
s_axi_wdata(680) => '0',
s_axi_wdata(679) => '0',
s_axi_wdata(678) => '0',
s_axi_wdata(677) => '0',
s_axi_wdata(676) => '0',
s_axi_wdata(675) => '0',
s_axi_wdata(674) => '0',
s_axi_wdata(673) => '0',
s_axi_wdata(672) => '0',
s_axi_wdata(671) => '0',
s_axi_wdata(670) => '0',
s_axi_wdata(669) => '0',
s_axi_wdata(668) => '0',
s_axi_wdata(667) => '0',
s_axi_wdata(666) => '0',
s_axi_wdata(665) => '0',
s_axi_wdata(664) => '0',
s_axi_wdata(663) => '0',
s_axi_wdata(662) => '0',
s_axi_wdata(661) => '0',
s_axi_wdata(660) => '0',
s_axi_wdata(659) => '0',
s_axi_wdata(658) => '0',
s_axi_wdata(657) => '0',
s_axi_wdata(656) => '0',
s_axi_wdata(655) => '0',
s_axi_wdata(654) => '0',
s_axi_wdata(653) => '0',
s_axi_wdata(652) => '0',
s_axi_wdata(651) => '0',
s_axi_wdata(650) => '0',
s_axi_wdata(649) => '0',
s_axi_wdata(648) => '0',
s_axi_wdata(647) => '0',
s_axi_wdata(646) => '0',
s_axi_wdata(645) => '0',
s_axi_wdata(644) => '0',
s_axi_wdata(643) => '0',
s_axi_wdata(642) => '0',
s_axi_wdata(641) => '0',
s_axi_wdata(640) => '0',
s_axi_wdata(639) => '0',
s_axi_wdata(638) => '0',
s_axi_wdata(637) => '0',
s_axi_wdata(636) => '0',
s_axi_wdata(635) => '0',
s_axi_wdata(634) => '0',
s_axi_wdata(633) => '0',
s_axi_wdata(632) => '0',
s_axi_wdata(631) => '0',
s_axi_wdata(630) => '0',
s_axi_wdata(629) => '0',
s_axi_wdata(628) => '0',
s_axi_wdata(627) => '0',
s_axi_wdata(626) => '0',
s_axi_wdata(625) => '0',
s_axi_wdata(624) => '0',
s_axi_wdata(623) => '0',
s_axi_wdata(622) => '0',
s_axi_wdata(621) => '0',
s_axi_wdata(620) => '0',
s_axi_wdata(619) => '0',
s_axi_wdata(618) => '0',
s_axi_wdata(617) => '0',
s_axi_wdata(616) => '0',
s_axi_wdata(615) => '0',
s_axi_wdata(614) => '0',
s_axi_wdata(613) => '0',
s_axi_wdata(612) => '0',
s_axi_wdata(611) => '0',
s_axi_wdata(610) => '0',
s_axi_wdata(609) => '0',
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s_axi_wdata(101) => '0',
s_axi_wdata(100) => '0',
s_axi_wdata(99) => '0',
s_axi_wdata(98) => '0',
s_axi_wdata(97) => '0',
s_axi_wdata(96) => '0',
s_axi_wdata(95) => '0',
s_axi_wdata(94) => '0',
s_axi_wdata(93) => '0',
s_axi_wdata(92) => '0',
s_axi_wdata(91) => '0',
s_axi_wdata(90) => '0',
s_axi_wdata(89) => '0',
s_axi_wdata(88) => '0',
s_axi_wdata(87) => '0',
s_axi_wdata(86) => '0',
s_axi_wdata(85) => '0',
s_axi_wdata(84) => '0',
s_axi_wdata(83) => '0',
s_axi_wdata(82) => '0',
s_axi_wdata(81) => '0',
s_axi_wdata(80) => '0',
s_axi_wdata(79) => '0',
s_axi_wdata(78) => '0',
s_axi_wdata(77) => '0',
s_axi_wdata(76) => '0',
s_axi_wdata(75) => '0',
s_axi_wdata(74) => '0',
s_axi_wdata(73) => '0',
s_axi_wdata(72) => '0',
s_axi_wdata(71) => '0',
s_axi_wdata(70) => '0',
s_axi_wdata(69) => '0',
s_axi_wdata(68) => '0',
s_axi_wdata(67) => '0',
s_axi_wdata(66) => '0',
s_axi_wdata(65) => '0',
s_axi_wdata(64) => '0',
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemScore/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd
|
6
|
171976
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
dWNC5O/skI155KAp5KOWoF7PAEoSa9dlQ4BEGvYf9rcCz/XPmDGb9cHdFk41xW/13JPFb1vvJI0y
paR+PkKOQw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
arDqe1SZUVXvjYDvQFyp018Qo3kBxAQuqhz4XaALefjTfUVxHLOl0QMJ32OBFkyD4ASVDy0y26uw
p1WfQag4myDUgw9X1tg1EkSAjiY2T+bS46vpr/V1iSmCBLeMocwUSy+S6/j8P6sKpKVBIwYNIUk+
GeQaTfzT2jus4jLVuYk=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LqZHaa/fqNZRMwLiq21bMdfwLQhhsi3+RWh3hUoB3NQuMju+GhGuY4MooZizud9d3j38An+LHEsr
GDrcO/p36+T8vsJNZV7Ufn94KQBBbqctMH8grLiOOYRChU9QJegXc4CDvx7EpF95l1JQ7AYhUc9m
BP637BC0zMrYW9oD9CA+HzYHObkLlwfKUJUa5Z9Gy/gRbRwROFmMiHl+pwV8bGzX77zFUBYh3AmU
ipbAakCJdSPqhrMWtt2EhngRToN7G+1BVQ/CiA7w2ILV+Itzzt5MfEy1C3HjrlzXl51xB32BWGPz
cV4O0htiI8hqTkuOzWq9nCem+ECxavU2KZ3BPg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
hl3RtgC3zulj1VBs/uKvPoBXU8IVq31Yn6TPJRPRncW3nwHlMNJjYlyG2Q6bIzixu4iWyHB/ZIHE
5gG8ea3nTO9nr3GqLifJ9msptoTv+MyyZatl294Xr44J6xsXMQ3wJxbBNjUqgn7k7sbogIV78RUM
TVWUJAXxrDcDKI89s2M=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
skw9tNQE1FYb2zddMb2x0Xv3aQBe+FTXsJkPGfwdyXRKljpuw2ofmzjM05rUP1jDryQRbTtcu8Dh
dD3xnSiXkvMjtSrAPZciwjTkVxxCHTNTshjgHiMAWWR/iLuWdsgBT0JqfSHbGB1Bi4mTjh9x7oVO
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28nKiejJmdm4L2LPF6MoBAYk8x00rX1VY1faLg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 125568)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemTextures/dist_mem_gen_v8_0/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd
|
6
|
171976
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 125568)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemScore/sim/MemScore.vhd
|
1
|
5723
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY MemScore IS
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END MemScore;
ARCHITECTURE MemScore_arch OF MemScore IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MemScore_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 8,
C_DEFAULT_DATA => "0",
C_DEPTH => 256,
C_HAS_CLK => 1,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "MemScore.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 1,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 12,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
clk => clk,
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END MemScore_arch;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/Register5.vhd
|
1
|
707
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Register5 is
Port (
rst_n : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
dout : out STD_LOGIC_VECTOR ( 4 DOWNTO 0 )
);
end Register5;
architecture Behavioral of Register5 is
signal data : STD_LOGIC_VECTOR ( 4 DOWNTO 0 );
--5 bit register
begin
PROCESS
BEGIN
wait until clk'event AND clk = '1';
IF rst_n = '1' then
data <= "00001";
elsif enable = '1' then
data <= din;
else
data <= data;
END IF;
END PROCESS;
dout <= data;
end Behavioral;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/About/About_funcsim.vhdl
|
1
|
603117
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 18:14:28 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/About/About_funcsim.vhdl
-- Design : About
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity About_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of About_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end About_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of About_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => addra(9 downto 0),
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"03F000C003F000C003F000C003F000C003F000C003F000C003F000C003F000C0",
INIT_3B => X"000000C0000000C003F000C003F000C003F000C003F000C003F000C003F000C0",
INIT_3C => X"00000000000000000000000000000000FFFFFE00FFFFFF00FFFFFF80FFFFFFC0",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000CEE2AA2FF4FFF00999999911199BBBB333BBBB99900FF",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"FFFFFFFF00000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"F0FFFCFCF0FFF8FC00FFF0FC00FFF0FC00FFE0FCF8FFC0FCF8FFC0FCF8FF80FC",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0999999DD888899DDDD000000000004400000011111111550000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000CCCCCCCCCCCCCCCCCCCCCCCCCCC0000000000000000000000000",
INITP_01 => X"08888888800001188880000000000077CCCCCCCCCCCCCCEE0000000000000000",
INITP_02 => X"0000000077444444CCCCCCCCFF000000000007777775555777777DD000000000",
INITP_03 => X"22222222200000000000DDCCCCCCDDEEEEEEDD00000000000000000000000000",
INITP_04 => X"88888888110000000000022EEEEAAAAAAEEEE220000000000000000222222222",
INITP_05 => X"000000000000000000000000000EECCCCCCCCCCCCCCEE0000000000011888888",
INITP_06 => X"0000000000000000FBBBEEBBF000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000CCCCC888833333306666666666675111111111100",
INITP_08 => X"000000000000DDDD999999999999DDDD999999998888CCCC0000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"81F0000081F0000081F0000081F0000081F0000081F0000081F0000000000000",
INIT_04 => X"FFF00000FFF00000FFF0000081F0000081F0000081F0000081F0000081F00000",
INIT_05 => X"81F0000081F0000081F0000081F0000081F0000081F0000081F0000081F00000",
INIT_06 => X"0000000000000000000000000000000081F0000081F0000081F0000081F00000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"C3800F00C3800F00C3800F00C3800F00C3800F00C3800F00C3FF0F00C3FF0F00",
INIT_0B => X"03800F0003800F00C3800F00C3800F00C3800F00C3800F00C3FE0F00C3FE0F00",
INIT_0C => X"00000000000000000000000000000000000000000000000003FF0FFE03FF0FFE",
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INIT_0E => X"00000F6700000F6700000F6700000F6700000F6700000F9F00000F9FC0000F07",
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INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0F0F001F0707801F0787803F0787803E03C3C03E03C3C07E03C1E07C01E1E0FC",
INIT_3B => X"3C7FFFFF3E3FFFFF3E3FFFFF1E3FFFFF1F1FFFFF1F1FFFFF0F0F000F0F0F000F",
INIT_3C => X"E1E00000F0F00000F0F00000F8F00000F8F8000078F800017C7C00017C7C0001",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000AAACCCCCCCCCCCCCCCCCC4442220000000000000000000000000",
INITP_01 => X"0AA332222222233332200000000000AA00111133111111BB0000000000000000",
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INITP_05 => X"0000000000000000000000000001111111111111111110000000000011111199",
INITP_06 => X"0000000000000000111111111000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000222AAAAAAAAAAAAA2222333333337777776666620",
INITP_08 => X"00000000000000000088888CCCCCEEEEECCCCC88888000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F0000F81F0000F81F0000F",
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INIT_0A => X"3C7800E13C7800E13C7800E13C7800E1F07800E1F07800E1C07FF0E1C07FF0E1",
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INIT_0C => X"000000000000000000000000000000000000000000000000C07FF01EC07FF01E",
INIT_0D => X"000700E1001FC07F001FC07F0000000000000000000000000000000000000000",
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INIT_11 => X"CF07001E3F07001E3F07001E0F07001E0F07001E0F1FC0FF0F1FC0FF00000000",
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INIT_13 => X"00000000000000000000000000000000000000000F1FC01E0F1FC01E0F07001E",
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INIT_15 => X"C00000FFC00000FF000000E1000000E1000000E1000000E13C0000E13C0000E1",
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INIT_1F => X"03800F0003803C0003803C000380F0000380F0000380F0E00380F0E00FE03F80",
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INIT_39 => X"1F0703E01F0703C01F0703C00F0707C00F0707800F07078007870F8007870F00",
INIT_3A => X"F80700F8F80700F8780700F87C0700F07C0700F03E0701F03E0701E03E0701E0",
INIT_3B => X"C007001FC007001FE007003EE007003EE007003EF007007CF007007CF007007C",
INIT_3C => X"00070003000700030007000700070007800700078007000F8007000F8007000F",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000070003",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"F000003FC000003F0000003F0000003F0000003F0000003F0000003F0000003F",
INIT_43 => X"FFFF803FFFFF003FFFFC003FFFF0003FFFE0003FFF80003FFF00003FFC00003F",
INIT_44 => X"FFE0003FFFF8003FFFFC003FFFFF003FFFFF803FFFFF803FFFFF803FFFFF803F",
INIT_45 => X"0000003F0000003F0000003FC000003FF000003FFC00003FFF00003FFF80003F",
INIT_46 => X"000000000000000000000000000000000000003F0000003F0000003F0000003F",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000CCCCCCCCCDDDCCCCCCCCCDDDDDD0000000000000000000000000",
INITP_01 => X"066EEEEEEAAAAEEEE22000000000000000000000000000000000000000000000",
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000004444444446666664444444446660000000000000000000000000",
INITP_01 => X"0000000551100004444000000000000000000000000000000000000000000000",
INITP_02 => X"0000000011111111551111115500000000000000000000000000000000000000",
INITP_03 => X"0000022220000000000000000000000000000000000000000000000000000000",
INITP_04 => X"CCCCDDDDDD000000000000000000000000000000000000000000000222200000",
INITP_05 => X"0000000000000000000000000002233333333BBBB332200000000000DDDDDDCC",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000001111111110000000000000000000000000000",
INITP_01 => X"0111100000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"8CCCCCC880000000000000000000000000000000000000000000000000000000",
INITP_04 => X"EEFFFFEECC000000000000000000000000000000000000000000000CCCCCC888",
INITP_05 => X"00000000000000000000000000022EEEEAAAAAAEEEE2200000000000CCEEEEEE",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000000000000000000000444C0000000080000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"000001FE000001F0000001F0000001F00000007E0000007E0000007E00000000",
INIT_04 => X"000000000000000000000000000001FE000001FE000001FE000001FE000001FE",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"00000F1E00000F1E00000F1E0000000000000000000000000000000000000000",
INIT_0E => X"00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E",
INIT_0F => X"00000000000000E0000000E0000003F8000003F800000F1E00000F1E00000F1E",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"FF00000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"FF000000C3800000C3800000C3800000C3800000C3800000C3800000FF000000",
INIT_20 => X"C380FC00C380FC00C380FC00C3800000C3800000CF000000CF000000FF000000",
INIT_21 => X"00000000000000000000000000000000000000000000000000000000C380FC00",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"00FE0F0700FE0F07000000000000000000000000000000000000000000000000",
INIT_27 => X"03870F7F03870F7FC3870FE7C3870FE7C3870F87C3870F87C3870F07C3870F07",
INIT_28 => X"C0FE0F07C0FE0F07C3870F07C3870F07C3870F07C3870F0703870F1F03870F1F",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"C3870F1FC3870F1EC3870F1EFF070F1EFF070F1E000000000000000000000000",
INIT_2B => X"C3870F1EC0070F1EC0070F1EC007FF1EC007FF1EC0070F1FC0070F1FC3870F1F",
INIT_2C => X"000000000000000000000000FF070F1EFF070F1EC3870F1EC3870F1EC3870F1E",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000800000000000000000000000",
INIT_3A => X"0F00000019000000190000001900000099000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000006000000060000000600000006000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"1111111000000000000000000000000000000000000000000000000000000000",
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000F0E10000F0E10000F0E10000F0E10000F0E10000F3810000F3810000FF01",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"AAAAAAAAAA000000000000000000000000000000000000000000000000000000",
INITP_05 => X"00000000000000000000000000000000000000000000000000000000EEAAAAAA",
INITP_06 => X"0000000000088888888800000000088888888888000000000000000000000000",
INITP_07 => X"0000000000000000000444444400000000002666666660000000000000000400",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"1100000011000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000EEE000000000000000000000000000000000000000000000011000000",
INITP_06 => X"BFFFECCCCFFF33000008BB3BBB11110000000000000000001110000000000000",
INITP_07 => X"000000000000000000EEE44446EEEE440001119998999899999998999899999B",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000FFE10000FFE1000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000FFE10000FFE10000F0010000F0010000F0010000F0010000F0010000F001",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"FFFFFC00FFFFFC00000000000000000000000000000000000000000000000000",
INIT_2F => X"00001C0000001C0000001C0000001C0000001C0000001C0000001C00FFFFFC00",
INIT_30 => X"00001C0000001C0000001C0000001C0000001C0000001C0000001C0000001C00",
INIT_31 => X"00001BC000001B8000001B8000001300000033000000370000001E0000001E00",
INIT_32 => X"000033CF000013CE000013CC00001BCC00001BF800001BF800001BF000001BC0",
INIT_33 => X"000066D9000066D9000062D9000033D9000033C9000033CD000033CD000033CF",
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INIT_39 => X"E3700330E37000F0E33001F0F6F000F0F6F000C0F6F000E0F6300070F4E001B0",
INIT_3A => X"FE3007C0FE3006C0F63000E0F33003F0F33003B0F3380370F33801F0F37803F0",
INIT_3B => X"3F007E003F0006007E0003007EC00700FEE00F00FCE01C80FC600100FEF00780",
INIT_3C => X"3FFE1C007BE7DC00E3E7FC00C7C7DC008FC0FC00CF80FC00FF003C007F007C00",
INIT_3D => X"0000000000000000FFFFFC00FFFFFC00DFFFFC0005F01C0003F81C000FFC1C00",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"FC66AAED5DCAEE6640888CCC44400888888888CCCCCCC4444444000000000000",
INITP_06 => X"777FFF7B9991AAACDD54011011100444066626FF177677CD9B3759886EEE4DBF",
INITP_07 => X"000000000000000000FFFFFDCEEFD7766644444667755DD7FFC44554CCCEADDD",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000011333110111110000000000000000000000000000000000000000000000",
INITP_06 => X"2333333333310111111000000000000223111111100000000000000000000000",
INITP_07 => X"0000000000000000003333333333333333323332221112322310002333233132",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000700000003000000010000000100000000000000000000000000000000",
INIT_2B => X"0000003600000036000000370000003D0000001D0000000D0000000D00000007",
INIT_2C => X"0000007B0000007B0000007B0000007300000033000000360000003600000036",
INIT_2D => X"000000FF000000FE000000DE00000076000000FC000000FD000000FD00000079",
INIT_2E => X"00FFFF6B00FFFF5B000000DE000000F7000000F7000000BD000000AF000000EB",
INIT_2F => X"00C0007D00C0006D00C0007B00C000DB00C000F600C000B600C000BD00FFFFED",
INIT_30 => X"00C0000300C0000700C0000700C0000D00C0000F00C0001B00C0003E00C00037",
INIT_31 => X"00C0000100C0000100C0000300C0000300C0000300C0000600C0000700C00003",
INIT_32 => X"00C000FF00C0003C00C0000000C0000000C0000000C0000000C0000000C00000",
INIT_33 => X"00C18F0000C0CF0000C0E78000C07BE000C03DFC00C01FFF00C007EF00C001FF",
INIT_34 => X"00DB780000CF780000CF780000CF780000C6380000C7780000C37C0000C13E00",
INIT_35 => X"00FC0FFF00FC2FC700FD7F0F00FF7E0F00FF7C0E00FF7C0E00DB581C00DB7838",
INIT_36 => X"00E7FCFD00E5FFB700E73FFA00E601FF00EE003F00EE01FF00FE03FF00FC07FF",
INIT_37 => X"00F77E0000EF0F8000FF83FC00FF8CFF00FF0F1F00FCFFEC00E3FFF600E7FFBB",
INIT_38 => X"00DFE3E700DFF1E300DFF83900DBFC9E00DB6FDF00F807F700F3E3FF00F7F8FF",
INIT_39 => X"00FFC37F00FF63FF00FE73FF00FC38FE00F4983700F0CC1B00FBCE0000FF6706",
INIT_3A => X"00C1F80000C3F91800CF311800DF317B00FF0F7F00F00FFF00E686FF00EFC006",
INIT_3B => X"00C7FFBF00C7FF3C00C3FF1800C3FF0000C3FE0000C3FD0000C1FB0000C1E600",
INIT_3C => X"00DFFFFF00DFFFFF00CFFFFE00CFFFF900CFFFF100C7FFF600C7FFFF00C7FFCF",
INIT_3D => X"000000000000000000FFFFFF00FFFFFF00FFFFFF00FFFFFF00FFFFFF00FFFFFF",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(30) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(29 downto 24) => douta(25 downto 20),
DOADO(23) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(22 downto 16) => douta(19 downto 13),
DOADO(15) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(14) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(13 downto 8) => douta(12 downto 7),
DOADO(7) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(6 downto 0) => douta(6 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(2) => \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(1) => \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(0) => \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"000000000038000001FF001F07FFC03F0FFFE03F1FFFF03F3FFFF83F7FFFF83F",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"4000000440000000000000000000000000000000000000000000000000000000",
INITP_04 => X"BB111111BB000000000000000000000000000000000000000000000440000444",
INITP_05 => X"00000000000000000000000000055444444554444445500000000000BB111111",
INITP_06 => X"F000000000000000111111111000000002222322230000000000000000000000",
INITP_07 => X"0000000000000000000022222222FFFF00DDDDDDFFBBBBBBBBBBFDDDDDD900FF",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"038000000F0000000F0000003C0000003C0000003C7800003C7800000FE00000",
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INIT_2A => X"0380F0000380F0000380F0003FF8FFE03FF8FFE0000000000000000000000000",
INIT_2B => X"0380F0000380F0000380F0000380FF800380FF800380F0000380F0000380F000",
INIT_2C => X"0000000000000000000000000380FFE00380FFE00380F0000380F0000380F000",
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INIT_3A => X"FFFF07F0F0FF07F0F07F07F0F03F87F0F03F87F0F03F87F0F03F87F0F03F87F0",
INIT_3B => X"0000000000000000FF8003F0FFF007F0FFF807F0FFFC07F0FFFE07F0FFFF07F0",
INIT_3C => X"0000FE7E0000FE600000FE7F0000FC7FFFFF0380FFFFFFFFFFFFFFFFFFFFFFFF",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000004444444440000000000000000000000000",
INITP_01 => X"000CC4400000088CC00000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"8888888770000000000000000000000000000000000000000000000000000000",
INITP_04 => X"3333333333000000000000000000000000000000000000000000000998888888",
INITP_05 => X"000000000000000000000000000FFEEEE445566EEEEDD0000000000033333333",
INITP_06 => X"3444CCC880000000000000000000000000000000000000000000000000000000",
INITP_07 => X"000000000000000000FFF000FFF000EEED11137764CCC88882222666C8800033",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0F8000007F8000007F8000007F8000007F8000007F8000007F80000000000000",
INIT_04 => X"0000000000000000000000007E0000007E0000007E0000000F8000000F800000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"C3800000FF000000FF0000000000000000000000000000000000000000000000",
INIT_0E => X"0F0000003C0000003C000000F0000000F0000000C0000000C0000000C3800000",
INIT_0F => X"00000000FF000000FF000000C3800000C380000003800000038000000F000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000CCC444444666666444444444EEE0000000000000000000000000",
INITP_01 => X"0551111111111111111000000000000000000000000000000000000000000000",
INITP_02 => X"0000000044115555111100004400000000000000000000000000000000000000",
INITP_03 => X"BBBBB88880000000000000000000000000000000000000000000000000000000",
INITP_04 => X"44441111110000000000000000000000000000000000000000000009999BBBBB",
INITP_05 => X"0000000000000000000000000000011111199111111880000000000011111111",
INITP_06 => X"7000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000003330445776655511000022233330000000011111110077",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"01F07E0001F07E0001F07E0001F07E0081FFF00081FFF00081FFF00000000000",
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INIT_36 => X"0000000100000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"1C7C70FF1C3C30FF181E38F0181E1C78180F0C78180F0E3C1807063C1803871E",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000999888888888DDDCCCCCCCCCDDD0000000000000000000000000",
INITP_01 => X"055666666EEEEEEEECC000000000000000000088888888880000000000000000",
INITP_02 => X"0000000099990000000044000000000000000FF6666667777664499000000000",
INITP_03 => X"CCCCC00220000000000000000000000000000000000000000000000000000000",
INITP_04 => X"9988888899000000000000000000000000000000000000000000000CCCCCCCCC",
INITP_05 => X"0000000000000000000000000002222222222222222220000000000099888888",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000000000000000000000000000000088888CCCC8880",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"81F07E0081F07E0081F07E0081F07E00FF807FFFFF807FFFFF807FFF00000000",
INIT_04 => X"FF807FFEFF807FFEFF807FFE81F07E0081F07E0081F07E0081F07E0081F07E00",
INIT_05 => X"80007E0080007E0080007E0080007E0080007E0080007E0080007E0080007E00",
INIT_06 => X"0000000000000000000000000000000080007FFF80007FFF80007FFF80007E00",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"C0000000C0000000C0000000C0000000C0000000C0000000C0000000C0000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"C3870F1E00FE0F1E00FE0F1E0000000000000000000000000000000000000000",
INIT_0E => X"03870F1E03870F1E03870F1EC3870F1EC3870F1EC3870F1EC3870F1EC3870F1E",
INIT_0F => X"0000000000FE03F800FE03F803870F1E03870F1E03870F1E03870F1E03870F1E",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0387038003870F0003870F0000FE0F1E00FE0F1E007803F8007803F800000000",
INIT_12 => X"03870F1E0387001E0387001E03FF007803FF0078038700E0038700E003870380",
INIT_13 => X"0000000000000000000000000000000000000000038703F8038703F803870F1E",
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INIT_15 => X"001E0000001E0000001E0000001E000003FE000003FE0000007E0000007E0000",
INIT_16 => X"001E00F8001E00F8001E00F8001E00F8001E0000001E0000001E0000001E0000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"3C07FF0700000000000000000000000000000000000000000000000000000000",
INIT_1F => X"C380F001C380F001C380F001C380F001C380F001FF00F001FF00F0013C07FF07",
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INIT_21 => X"00000000000000000000000000000000000000000000000000000000C380F007",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"00000FFE00000FFE000000000000000000000000000000000000000000000000",
INIT_27 => X"00000FF800000FF8C0000F00C0000F00C0000F00C0000F00C0000F00C0000F00",
INIT_28 => X"C0000FFEC0000FFEC0000F00C0000F00C0000F00C0000F0000000F0000000F00",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"00070F1E00070F1E00070F1E0001FC1F0001FC1F000000000000000000000000",
INIT_2B => X"00070F1E00070F1E00070F1E00070F1F00070F1F00070F1E00070F1E00070F1E",
INIT_2C => X"0000000000000000000000000001FC1E0001FC1E00070F1E00070F1E00070F1E",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"FF000000FF800000FF800000FF000000FC000000E00000008000000000000000",
INIT_39 => X"00000000000000000000000080000000E0000000F0000000FC000000FF000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000EEE444444444666444444444EEE0000000000000000000000000",
INITP_01 => X"03311111199111111BB000000000002200000022111111330000000000000000",
INITP_02 => X"00000088AAAA8888888888880000000000000AA0000222200000022000000000",
INITP_03 => X"000110000000000000008800002222000000AA00000000000000000000000000",
INITP_04 => X"BB999999BB000000000000000000044000000440000000000000000444400000",
INITP_05 => X"00000000000000000000000000044444444555555555500000000000BB999999",
INITP_06 => X"6733333333333333322222200000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000000888880008888888888888888CCCCDDD7777777766",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \About_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \About_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity About_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of About_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end About_blk_mem_gen_prim_width;
architecture STRUCTURE of About_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.About_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(25 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \About_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \About_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\About_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity About_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of About_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end About_blk_mem_gen_generic_cstr;
architecture STRUCTURE of About_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.About_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
\ramloop[10].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(377 downto 342)
);
\ramloop[11].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(413 downto 378)
);
\ramloop[12].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(449 downto 414)
);
\ramloop[13].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(485 downto 450)
);
\ramloop[14].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(521 downto 486)
);
\ramloop[15].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(557 downto 522)
);
\ramloop[16].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(593 downto 558)
);
\ramloop[17].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(629 downto 594)
);
\ramloop[18].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(665 downto 630)
);
\ramloop[19].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(701 downto 666)
);
\ramloop[1].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(53 downto 18)
);
\ramloop[20].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(737 downto 702)
);
\ramloop[21].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(773 downto 738)
);
\ramloop[22].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(799 downto 774)
);
\ramloop[2].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(89 downto 54)
);
\ramloop[3].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(125 downto 90)
);
\ramloop[4].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(161 downto 126)
);
\ramloop[5].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(197 downto 162)
);
\ramloop[6].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(233 downto 198)
);
\ramloop[7].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(269 downto 234)
);
\ramloop[8].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(305 downto 270)
);
\ramloop[9].ram.r\: entity work.\About_blk_mem_gen_prim_width__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(341 downto 306)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity About_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of About_blk_mem_gen_top : entity is "blk_mem_gen_top";
end About_blk_mem_gen_top;
architecture STRUCTURE of About_blk_mem_gen_top is
begin
\valid.cstr\: entity work.About_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity About_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of About_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end About_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of About_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.About_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \About_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 799 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 799 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 799 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 3;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "About.mif";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "About.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \About_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "22";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 60.4532 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \About_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \About_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \About_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(799) <= \<const0>\;
doutb(798) <= \<const0>\;
doutb(797) <= \<const0>\;
doutb(796) <= \<const0>\;
doutb(795) <= \<const0>\;
doutb(794) <= \<const0>\;
doutb(793) <= \<const0>\;
doutb(792) <= \<const0>\;
doutb(791) <= \<const0>\;
doutb(790) <= \<const0>\;
doutb(789) <= \<const0>\;
doutb(788) <= \<const0>\;
doutb(787) <= \<const0>\;
doutb(786) <= \<const0>\;
doutb(785) <= \<const0>\;
doutb(784) <= \<const0>\;
doutb(783) <= \<const0>\;
doutb(782) <= \<const0>\;
doutb(781) <= \<const0>\;
doutb(780) <= \<const0>\;
doutb(779) <= \<const0>\;
doutb(778) <= \<const0>\;
doutb(777) <= \<const0>\;
doutb(776) <= \<const0>\;
doutb(775) <= \<const0>\;
doutb(774) <= \<const0>\;
doutb(773) <= \<const0>\;
doutb(772) <= \<const0>\;
doutb(771) <= \<const0>\;
doutb(770) <= \<const0>\;
doutb(769) <= \<const0>\;
doutb(768) <= \<const0>\;
doutb(767) <= \<const0>\;
doutb(766) <= \<const0>\;
doutb(765) <= \<const0>\;
doutb(764) <= \<const0>\;
doutb(763) <= \<const0>\;
doutb(762) <= \<const0>\;
doutb(761) <= \<const0>\;
doutb(760) <= \<const0>\;
doutb(759) <= \<const0>\;
doutb(758) <= \<const0>\;
doutb(757) <= \<const0>\;
doutb(756) <= \<const0>\;
doutb(755) <= \<const0>\;
doutb(754) <= \<const0>\;
doutb(753) <= \<const0>\;
doutb(752) <= \<const0>\;
doutb(751) <= \<const0>\;
doutb(750) <= \<const0>\;
doutb(749) <= \<const0>\;
doutb(748) <= \<const0>\;
doutb(747) <= \<const0>\;
doutb(746) <= \<const0>\;
doutb(745) <= \<const0>\;
doutb(744) <= \<const0>\;
doutb(743) <= \<const0>\;
doutb(742) <= \<const0>\;
doutb(741) <= \<const0>\;
doutb(740) <= \<const0>\;
doutb(739) <= \<const0>\;
doutb(738) <= \<const0>\;
doutb(737) <= \<const0>\;
doutb(736) <= \<const0>\;
doutb(735) <= \<const0>\;
doutb(734) <= \<const0>\;
doutb(733) <= \<const0>\;
doutb(732) <= \<const0>\;
doutb(731) <= \<const0>\;
doutb(730) <= \<const0>\;
doutb(729) <= \<const0>\;
doutb(728) <= \<const0>\;
doutb(727) <= \<const0>\;
doutb(726) <= \<const0>\;
doutb(725) <= \<const0>\;
doutb(724) <= \<const0>\;
doutb(723) <= \<const0>\;
doutb(722) <= \<const0>\;
doutb(721) <= \<const0>\;
doutb(720) <= \<const0>\;
doutb(719) <= \<const0>\;
doutb(718) <= \<const0>\;
doutb(717) <= \<const0>\;
doutb(716) <= \<const0>\;
doutb(715) <= \<const0>\;
doutb(714) <= \<const0>\;
doutb(713) <= \<const0>\;
doutb(712) <= \<const0>\;
doutb(711) <= \<const0>\;
doutb(710) <= \<const0>\;
doutb(709) <= \<const0>\;
doutb(708) <= \<const0>\;
doutb(707) <= \<const0>\;
doutb(706) <= \<const0>\;
doutb(705) <= \<const0>\;
doutb(704) <= \<const0>\;
doutb(703) <= \<const0>\;
doutb(702) <= \<const0>\;
doutb(701) <= \<const0>\;
doutb(700) <= \<const0>\;
doutb(699) <= \<const0>\;
doutb(698) <= \<const0>\;
doutb(697) <= \<const0>\;
doutb(696) <= \<const0>\;
doutb(695) <= \<const0>\;
doutb(694) <= \<const0>\;
doutb(693) <= \<const0>\;
doutb(692) <= \<const0>\;
doutb(691) <= \<const0>\;
doutb(690) <= \<const0>\;
doutb(689) <= \<const0>\;
doutb(688) <= \<const0>\;
doutb(687) <= \<const0>\;
doutb(686) <= \<const0>\;
doutb(685) <= \<const0>\;
doutb(684) <= \<const0>\;
doutb(683) <= \<const0>\;
doutb(682) <= \<const0>\;
doutb(681) <= \<const0>\;
doutb(680) <= \<const0>\;
doutb(679) <= \<const0>\;
doutb(678) <= \<const0>\;
doutb(677) <= \<const0>\;
doutb(676) <= \<const0>\;
doutb(675) <= \<const0>\;
doutb(674) <= \<const0>\;
doutb(673) <= \<const0>\;
doutb(672) <= \<const0>\;
doutb(671) <= \<const0>\;
doutb(670) <= \<const0>\;
doutb(669) <= \<const0>\;
doutb(668) <= \<const0>\;
doutb(667) <= \<const0>\;
doutb(666) <= \<const0>\;
doutb(665) <= \<const0>\;
doutb(664) <= \<const0>\;
doutb(663) <= \<const0>\;
doutb(662) <= \<const0>\;
doutb(661) <= \<const0>\;
doutb(660) <= \<const0>\;
doutb(659) <= \<const0>\;
doutb(658) <= \<const0>\;
doutb(657) <= \<const0>\;
doutb(656) <= \<const0>\;
doutb(655) <= \<const0>\;
doutb(654) <= \<const0>\;
doutb(653) <= \<const0>\;
doutb(652) <= \<const0>\;
doutb(651) <= \<const0>\;
doutb(650) <= \<const0>\;
doutb(649) <= \<const0>\;
doutb(648) <= \<const0>\;
doutb(647) <= \<const0>\;
doutb(646) <= \<const0>\;
doutb(645) <= \<const0>\;
doutb(644) <= \<const0>\;
doutb(643) <= \<const0>\;
doutb(642) <= \<const0>\;
doutb(641) <= \<const0>\;
doutb(640) <= \<const0>\;
doutb(639) <= \<const0>\;
doutb(638) <= \<const0>\;
doutb(637) <= \<const0>\;
doutb(636) <= \<const0>\;
doutb(635) <= \<const0>\;
doutb(634) <= \<const0>\;
doutb(633) <= \<const0>\;
doutb(632) <= \<const0>\;
doutb(631) <= \<const0>\;
doutb(630) <= \<const0>\;
doutb(629) <= \<const0>\;
doutb(628) <= \<const0>\;
doutb(627) <= \<const0>\;
doutb(626) <= \<const0>\;
doutb(625) <= \<const0>\;
doutb(624) <= \<const0>\;
doutb(623) <= \<const0>\;
doutb(622) <= \<const0>\;
doutb(621) <= \<const0>\;
doutb(620) <= \<const0>\;
doutb(619) <= \<const0>\;
doutb(618) <= \<const0>\;
doutb(617) <= \<const0>\;
doutb(616) <= \<const0>\;
doutb(615) <= \<const0>\;
doutb(614) <= \<const0>\;
doutb(613) <= \<const0>\;
doutb(612) <= \<const0>\;
doutb(611) <= \<const0>\;
doutb(610) <= \<const0>\;
doutb(609) <= \<const0>\;
doutb(608) <= \<const0>\;
doutb(607) <= \<const0>\;
doutb(606) <= \<const0>\;
doutb(605) <= \<const0>\;
doutb(604) <= \<const0>\;
doutb(603) <= \<const0>\;
doutb(602) <= \<const0>\;
doutb(601) <= \<const0>\;
doutb(600) <= \<const0>\;
doutb(599) <= \<const0>\;
doutb(598) <= \<const0>\;
doutb(597) <= \<const0>\;
doutb(596) <= \<const0>\;
doutb(595) <= \<const0>\;
doutb(594) <= \<const0>\;
doutb(593) <= \<const0>\;
doutb(592) <= \<const0>\;
doutb(591) <= \<const0>\;
doutb(590) <= \<const0>\;
doutb(589) <= \<const0>\;
doutb(588) <= \<const0>\;
doutb(587) <= \<const0>\;
doutb(586) <= \<const0>\;
doutb(585) <= \<const0>\;
doutb(584) <= \<const0>\;
doutb(583) <= \<const0>\;
doutb(582) <= \<const0>\;
doutb(581) <= \<const0>\;
doutb(580) <= \<const0>\;
doutb(579) <= \<const0>\;
doutb(578) <= \<const0>\;
doutb(577) <= \<const0>\;
doutb(576) <= \<const0>\;
doutb(575) <= \<const0>\;
doutb(574) <= \<const0>\;
doutb(573) <= \<const0>\;
doutb(572) <= \<const0>\;
doutb(571) <= \<const0>\;
doutb(570) <= \<const0>\;
doutb(569) <= \<const0>\;
doutb(568) <= \<const0>\;
doutb(567) <= \<const0>\;
doutb(566) <= \<const0>\;
doutb(565) <= \<const0>\;
doutb(564) <= \<const0>\;
doutb(563) <= \<const0>\;
doutb(562) <= \<const0>\;
doutb(561) <= \<const0>\;
doutb(560) <= \<const0>\;
doutb(559) <= \<const0>\;
doutb(558) <= \<const0>\;
doutb(557) <= \<const0>\;
doutb(556) <= \<const0>\;
doutb(555) <= \<const0>\;
doutb(554) <= \<const0>\;
doutb(553) <= \<const0>\;
doutb(552) <= \<const0>\;
doutb(551) <= \<const0>\;
doutb(550) <= \<const0>\;
doutb(549) <= \<const0>\;
doutb(548) <= \<const0>\;
doutb(547) <= \<const0>\;
doutb(546) <= \<const0>\;
doutb(545) <= \<const0>\;
doutb(544) <= \<const0>\;
doutb(543) <= \<const0>\;
doutb(542) <= \<const0>\;
doutb(541) <= \<const0>\;
doutb(540) <= \<const0>\;
doutb(539) <= \<const0>\;
doutb(538) <= \<const0>\;
doutb(537) <= \<const0>\;
doutb(536) <= \<const0>\;
doutb(535) <= \<const0>\;
doutb(534) <= \<const0>\;
doutb(533) <= \<const0>\;
doutb(532) <= \<const0>\;
doutb(531) <= \<const0>\;
doutb(530) <= \<const0>\;
doutb(529) <= \<const0>\;
doutb(528) <= \<const0>\;
doutb(527) <= \<const0>\;
doutb(526) <= \<const0>\;
doutb(525) <= \<const0>\;
doutb(524) <= \<const0>\;
doutb(523) <= \<const0>\;
doutb(522) <= \<const0>\;
doutb(521) <= \<const0>\;
doutb(520) <= \<const0>\;
doutb(519) <= \<const0>\;
doutb(518) <= \<const0>\;
doutb(517) <= \<const0>\;
doutb(516) <= \<const0>\;
doutb(515) <= \<const0>\;
doutb(514) <= \<const0>\;
doutb(513) <= \<const0>\;
doutb(512) <= \<const0>\;
doutb(511) <= \<const0>\;
doutb(510) <= \<const0>\;
doutb(509) <= \<const0>\;
doutb(508) <= \<const0>\;
doutb(507) <= \<const0>\;
doutb(506) <= \<const0>\;
doutb(505) <= \<const0>\;
doutb(504) <= \<const0>\;
doutb(503) <= \<const0>\;
doutb(502) <= \<const0>\;
doutb(501) <= \<const0>\;
doutb(500) <= \<const0>\;
doutb(499) <= \<const0>\;
doutb(498) <= \<const0>\;
doutb(497) <= \<const0>\;
doutb(496) <= \<const0>\;
doutb(495) <= \<const0>\;
doutb(494) <= \<const0>\;
doutb(493) <= \<const0>\;
doutb(492) <= \<const0>\;
doutb(491) <= \<const0>\;
doutb(490) <= \<const0>\;
doutb(489) <= \<const0>\;
doutb(488) <= \<const0>\;
doutb(487) <= \<const0>\;
doutb(486) <= \<const0>\;
doutb(485) <= \<const0>\;
doutb(484) <= \<const0>\;
doutb(483) <= \<const0>\;
doutb(482) <= \<const0>\;
doutb(481) <= \<const0>\;
doutb(480) <= \<const0>\;
doutb(479) <= \<const0>\;
doutb(478) <= \<const0>\;
doutb(477) <= \<const0>\;
doutb(476) <= \<const0>\;
doutb(475) <= \<const0>\;
doutb(474) <= \<const0>\;
doutb(473) <= \<const0>\;
doutb(472) <= \<const0>\;
doutb(471) <= \<const0>\;
doutb(470) <= \<const0>\;
doutb(469) <= \<const0>\;
doutb(468) <= \<const0>\;
doutb(467) <= \<const0>\;
doutb(466) <= \<const0>\;
doutb(465) <= \<const0>\;
doutb(464) <= \<const0>\;
doutb(463) <= \<const0>\;
doutb(462) <= \<const0>\;
doutb(461) <= \<const0>\;
doutb(460) <= \<const0>\;
doutb(459) <= \<const0>\;
doutb(458) <= \<const0>\;
doutb(457) <= \<const0>\;
doutb(456) <= \<const0>\;
doutb(455) <= \<const0>\;
doutb(454) <= \<const0>\;
doutb(453) <= \<const0>\;
doutb(452) <= \<const0>\;
doutb(451) <= \<const0>\;
doutb(450) <= \<const0>\;
doutb(449) <= \<const0>\;
doutb(448) <= \<const0>\;
doutb(447) <= \<const0>\;
doutb(446) <= \<const0>\;
doutb(445) <= \<const0>\;
doutb(444) <= \<const0>\;
doutb(443) <= \<const0>\;
doutb(442) <= \<const0>\;
doutb(441) <= \<const0>\;
doutb(440) <= \<const0>\;
doutb(439) <= \<const0>\;
doutb(438) <= \<const0>\;
doutb(437) <= \<const0>\;
doutb(436) <= \<const0>\;
doutb(435) <= \<const0>\;
doutb(434) <= \<const0>\;
doutb(433) <= \<const0>\;
doutb(432) <= \<const0>\;
doutb(431) <= \<const0>\;
doutb(430) <= \<const0>\;
doutb(429) <= \<const0>\;
doutb(428) <= \<const0>\;
doutb(427) <= \<const0>\;
doutb(426) <= \<const0>\;
doutb(425) <= \<const0>\;
doutb(424) <= \<const0>\;
doutb(423) <= \<const0>\;
doutb(422) <= \<const0>\;
doutb(421) <= \<const0>\;
doutb(420) <= \<const0>\;
doutb(419) <= \<const0>\;
doutb(418) <= \<const0>\;
doutb(417) <= \<const0>\;
doutb(416) <= \<const0>\;
doutb(415) <= \<const0>\;
doutb(414) <= \<const0>\;
doutb(413) <= \<const0>\;
doutb(412) <= \<const0>\;
doutb(411) <= \<const0>\;
doutb(410) <= \<const0>\;
doutb(409) <= \<const0>\;
doutb(408) <= \<const0>\;
doutb(407) <= \<const0>\;
doutb(406) <= \<const0>\;
doutb(405) <= \<const0>\;
doutb(404) <= \<const0>\;
doutb(403) <= \<const0>\;
doutb(402) <= \<const0>\;
doutb(401) <= \<const0>\;
doutb(400) <= \<const0>\;
doutb(399) <= \<const0>\;
doutb(398) <= \<const0>\;
doutb(397) <= \<const0>\;
doutb(396) <= \<const0>\;
doutb(395) <= \<const0>\;
doutb(394) <= \<const0>\;
doutb(393) <= \<const0>\;
doutb(392) <= \<const0>\;
doutb(391) <= \<const0>\;
doutb(390) <= \<const0>\;
doutb(389) <= \<const0>\;
doutb(388) <= \<const0>\;
doutb(387) <= \<const0>\;
doutb(386) <= \<const0>\;
doutb(385) <= \<const0>\;
doutb(384) <= \<const0>\;
doutb(383) <= \<const0>\;
doutb(382) <= \<const0>\;
doutb(381) <= \<const0>\;
doutb(380) <= \<const0>\;
doutb(379) <= \<const0>\;
doutb(378) <= \<const0>\;
doutb(377) <= \<const0>\;
doutb(376) <= \<const0>\;
doutb(375) <= \<const0>\;
doutb(374) <= \<const0>\;
doutb(373) <= \<const0>\;
doutb(372) <= \<const0>\;
doutb(371) <= \<const0>\;
doutb(370) <= \<const0>\;
doutb(369) <= \<const0>\;
doutb(368) <= \<const0>\;
doutb(367) <= \<const0>\;
doutb(366) <= \<const0>\;
doutb(365) <= \<const0>\;
doutb(364) <= \<const0>\;
doutb(363) <= \<const0>\;
doutb(362) <= \<const0>\;
doutb(361) <= \<const0>\;
doutb(360) <= \<const0>\;
doutb(359) <= \<const0>\;
doutb(358) <= \<const0>\;
doutb(357) <= \<const0>\;
doutb(356) <= \<const0>\;
doutb(355) <= \<const0>\;
doutb(354) <= \<const0>\;
doutb(353) <= \<const0>\;
doutb(352) <= \<const0>\;
doutb(351) <= \<const0>\;
doutb(350) <= \<const0>\;
doutb(349) <= \<const0>\;
doutb(348) <= \<const0>\;
doutb(347) <= \<const0>\;
doutb(346) <= \<const0>\;
doutb(345) <= \<const0>\;
doutb(344) <= \<const0>\;
doutb(343) <= \<const0>\;
doutb(342) <= \<const0>\;
doutb(341) <= \<const0>\;
doutb(340) <= \<const0>\;
doutb(339) <= \<const0>\;
doutb(338) <= \<const0>\;
doutb(337) <= \<const0>\;
doutb(336) <= \<const0>\;
doutb(335) <= \<const0>\;
doutb(334) <= \<const0>\;
doutb(333) <= \<const0>\;
doutb(332) <= \<const0>\;
doutb(331) <= \<const0>\;
doutb(330) <= \<const0>\;
doutb(329) <= \<const0>\;
doutb(328) <= \<const0>\;
doutb(327) <= \<const0>\;
doutb(326) <= \<const0>\;
doutb(325) <= \<const0>\;
doutb(324) <= \<const0>\;
doutb(323) <= \<const0>\;
doutb(322) <= \<const0>\;
doutb(321) <= \<const0>\;
doutb(320) <= \<const0>\;
doutb(319) <= \<const0>\;
doutb(318) <= \<const0>\;
doutb(317) <= \<const0>\;
doutb(316) <= \<const0>\;
doutb(315) <= \<const0>\;
doutb(314) <= \<const0>\;
doutb(313) <= \<const0>\;
doutb(312) <= \<const0>\;
doutb(311) <= \<const0>\;
doutb(310) <= \<const0>\;
doutb(309) <= \<const0>\;
doutb(308) <= \<const0>\;
doutb(307) <= \<const0>\;
doutb(306) <= \<const0>\;
doutb(305) <= \<const0>\;
doutb(304) <= \<const0>\;
doutb(303) <= \<const0>\;
doutb(302) <= \<const0>\;
doutb(301) <= \<const0>\;
doutb(300) <= \<const0>\;
doutb(299) <= \<const0>\;
doutb(298) <= \<const0>\;
doutb(297) <= \<const0>\;
doutb(296) <= \<const0>\;
doutb(295) <= \<const0>\;
doutb(294) <= \<const0>\;
doutb(293) <= \<const0>\;
doutb(292) <= \<const0>\;
doutb(291) <= \<const0>\;
doutb(290) <= \<const0>\;
doutb(289) <= \<const0>\;
doutb(288) <= \<const0>\;
doutb(287) <= \<const0>\;
doutb(286) <= \<const0>\;
doutb(285) <= \<const0>\;
doutb(284) <= \<const0>\;
doutb(283) <= \<const0>\;
doutb(282) <= \<const0>\;
doutb(281) <= \<const0>\;
doutb(280) <= \<const0>\;
doutb(279) <= \<const0>\;
doutb(278) <= \<const0>\;
doutb(277) <= \<const0>\;
doutb(276) <= \<const0>\;
doutb(275) <= \<const0>\;
doutb(274) <= \<const0>\;
doutb(273) <= \<const0>\;
doutb(272) <= \<const0>\;
doutb(271) <= \<const0>\;
doutb(270) <= \<const0>\;
doutb(269) <= \<const0>\;
doutb(268) <= \<const0>\;
doutb(267) <= \<const0>\;
doutb(266) <= \<const0>\;
doutb(265) <= \<const0>\;
doutb(264) <= \<const0>\;
doutb(263) <= \<const0>\;
doutb(262) <= \<const0>\;
doutb(261) <= \<const0>\;
doutb(260) <= \<const0>\;
doutb(259) <= \<const0>\;
doutb(258) <= \<const0>\;
doutb(257) <= \<const0>\;
doutb(256) <= \<const0>\;
doutb(255) <= \<const0>\;
doutb(254) <= \<const0>\;
doutb(253) <= \<const0>\;
doutb(252) <= \<const0>\;
doutb(251) <= \<const0>\;
doutb(250) <= \<const0>\;
doutb(249) <= \<const0>\;
doutb(248) <= \<const0>\;
doutb(247) <= \<const0>\;
doutb(246) <= \<const0>\;
doutb(245) <= \<const0>\;
doutb(244) <= \<const0>\;
doutb(243) <= \<const0>\;
doutb(242) <= \<const0>\;
doutb(241) <= \<const0>\;
doutb(240) <= \<const0>\;
doutb(239) <= \<const0>\;
doutb(238) <= \<const0>\;
doutb(237) <= \<const0>\;
doutb(236) <= \<const0>\;
doutb(235) <= \<const0>\;
doutb(234) <= \<const0>\;
doutb(233) <= \<const0>\;
doutb(232) <= \<const0>\;
doutb(231) <= \<const0>\;
doutb(230) <= \<const0>\;
doutb(229) <= \<const0>\;
doutb(228) <= \<const0>\;
doutb(227) <= \<const0>\;
doutb(226) <= \<const0>\;
doutb(225) <= \<const0>\;
doutb(224) <= \<const0>\;
doutb(223) <= \<const0>\;
doutb(222) <= \<const0>\;
doutb(221) <= \<const0>\;
doutb(220) <= \<const0>\;
doutb(219) <= \<const0>\;
doutb(218) <= \<const0>\;
doutb(217) <= \<const0>\;
doutb(216) <= \<const0>\;
doutb(215) <= \<const0>\;
doutb(214) <= \<const0>\;
doutb(213) <= \<const0>\;
doutb(212) <= \<const0>\;
doutb(211) <= \<const0>\;
doutb(210) <= \<const0>\;
doutb(209) <= \<const0>\;
doutb(208) <= \<const0>\;
doutb(207) <= \<const0>\;
doutb(206) <= \<const0>\;
doutb(205) <= \<const0>\;
doutb(204) <= \<const0>\;
doutb(203) <= \<const0>\;
doutb(202) <= \<const0>\;
doutb(201) <= \<const0>\;
doutb(200) <= \<const0>\;
doutb(199) <= \<const0>\;
doutb(198) <= \<const0>\;
doutb(197) <= \<const0>\;
doutb(196) <= \<const0>\;
doutb(195) <= \<const0>\;
doutb(194) <= \<const0>\;
doutb(193) <= \<const0>\;
doutb(192) <= \<const0>\;
doutb(191) <= \<const0>\;
doutb(190) <= \<const0>\;
doutb(189) <= \<const0>\;
doutb(188) <= \<const0>\;
doutb(187) <= \<const0>\;
doutb(186) <= \<const0>\;
doutb(185) <= \<const0>\;
doutb(184) <= \<const0>\;
doutb(183) <= \<const0>\;
doutb(182) <= \<const0>\;
doutb(181) <= \<const0>\;
doutb(180) <= \<const0>\;
doutb(179) <= \<const0>\;
doutb(178) <= \<const0>\;
doutb(177) <= \<const0>\;
doutb(176) <= \<const0>\;
doutb(175) <= \<const0>\;
doutb(174) <= \<const0>\;
doutb(173) <= \<const0>\;
doutb(172) <= \<const0>\;
doutb(171) <= \<const0>\;
doutb(170) <= \<const0>\;
doutb(169) <= \<const0>\;
doutb(168) <= \<const0>\;
doutb(167) <= \<const0>\;
doutb(166) <= \<const0>\;
doutb(165) <= \<const0>\;
doutb(164) <= \<const0>\;
doutb(163) <= \<const0>\;
doutb(162) <= \<const0>\;
doutb(161) <= \<const0>\;
doutb(160) <= \<const0>\;
doutb(159) <= \<const0>\;
doutb(158) <= \<const0>\;
doutb(157) <= \<const0>\;
doutb(156) <= \<const0>\;
doutb(155) <= \<const0>\;
doutb(154) <= \<const0>\;
doutb(153) <= \<const0>\;
doutb(152) <= \<const0>\;
doutb(151) <= \<const0>\;
doutb(150) <= \<const0>\;
doutb(149) <= \<const0>\;
doutb(148) <= \<const0>\;
doutb(147) <= \<const0>\;
doutb(146) <= \<const0>\;
doutb(145) <= \<const0>\;
doutb(144) <= \<const0>\;
doutb(143) <= \<const0>\;
doutb(142) <= \<const0>\;
doutb(141) <= \<const0>\;
doutb(140) <= \<const0>\;
doutb(139) <= \<const0>\;
doutb(138) <= \<const0>\;
doutb(137) <= \<const0>\;
doutb(136) <= \<const0>\;
doutb(135) <= \<const0>\;
doutb(134) <= \<const0>\;
doutb(133) <= \<const0>\;
doutb(132) <= \<const0>\;
doutb(131) <= \<const0>\;
doutb(130) <= \<const0>\;
doutb(129) <= \<const0>\;
doutb(128) <= \<const0>\;
doutb(127) <= \<const0>\;
doutb(126) <= \<const0>\;
doutb(125) <= \<const0>\;
doutb(124) <= \<const0>\;
doutb(123) <= \<const0>\;
doutb(122) <= \<const0>\;
doutb(121) <= \<const0>\;
doutb(120) <= \<const0>\;
doutb(119) <= \<const0>\;
doutb(118) <= \<const0>\;
doutb(117) <= \<const0>\;
doutb(116) <= \<const0>\;
doutb(115) <= \<const0>\;
doutb(114) <= \<const0>\;
doutb(113) <= \<const0>\;
doutb(112) <= \<const0>\;
doutb(111) <= \<const0>\;
doutb(110) <= \<const0>\;
doutb(109) <= \<const0>\;
doutb(108) <= \<const0>\;
doutb(107) <= \<const0>\;
doutb(106) <= \<const0>\;
doutb(105) <= \<const0>\;
doutb(104) <= \<const0>\;
doutb(103) <= \<const0>\;
doutb(102) <= \<const0>\;
doutb(101) <= \<const0>\;
doutb(100) <= \<const0>\;
doutb(99) <= \<const0>\;
doutb(98) <= \<const0>\;
doutb(97) <= \<const0>\;
doutb(96) <= \<const0>\;
doutb(95) <= \<const0>\;
doutb(94) <= \<const0>\;
doutb(93) <= \<const0>\;
doutb(92) <= \<const0>\;
doutb(91) <= \<const0>\;
doutb(90) <= \<const0>\;
doutb(89) <= \<const0>\;
doutb(88) <= \<const0>\;
doutb(87) <= \<const0>\;
doutb(86) <= \<const0>\;
doutb(85) <= \<const0>\;
doutb(84) <= \<const0>\;
doutb(83) <= \<const0>\;
doutb(82) <= \<const0>\;
doutb(81) <= \<const0>\;
doutb(80) <= \<const0>\;
doutb(79) <= \<const0>\;
doutb(78) <= \<const0>\;
doutb(77) <= \<const0>\;
doutb(76) <= \<const0>\;
doutb(75) <= \<const0>\;
doutb(74) <= \<const0>\;
doutb(73) <= \<const0>\;
doutb(72) <= \<const0>\;
doutb(71) <= \<const0>\;
doutb(70) <= \<const0>\;
doutb(69) <= \<const0>\;
doutb(68) <= \<const0>\;
doutb(67) <= \<const0>\;
doutb(66) <= \<const0>\;
doutb(65) <= \<const0>\;
doutb(64) <= \<const0>\;
doutb(63) <= \<const0>\;
doutb(62) <= \<const0>\;
doutb(61) <= \<const0>\;
doutb(60) <= \<const0>\;
doutb(59) <= \<const0>\;
doutb(58) <= \<const0>\;
doutb(57) <= \<const0>\;
doutb(56) <= \<const0>\;
doutb(55) <= \<const0>\;
doutb(54) <= \<const0>\;
doutb(53) <= \<const0>\;
doutb(52) <= \<const0>\;
doutb(51) <= \<const0>\;
doutb(50) <= \<const0>\;
doutb(49) <= \<const0>\;
doutb(48) <= \<const0>\;
doutb(47) <= \<const0>\;
doutb(46) <= \<const0>\;
doutb(45) <= \<const0>\;
doutb(44) <= \<const0>\;
doutb(43) <= \<const0>\;
doutb(42) <= \<const0>\;
doutb(41) <= \<const0>\;
doutb(40) <= \<const0>\;
doutb(39) <= \<const0>\;
doutb(38) <= \<const0>\;
doutb(37) <= \<const0>\;
doutb(36) <= \<const0>\;
doutb(35) <= \<const0>\;
doutb(34) <= \<const0>\;
doutb(33) <= \<const0>\;
doutb(32) <= \<const0>\;
doutb(31) <= \<const0>\;
doutb(30) <= \<const0>\;
doutb(29) <= \<const0>\;
doutb(28) <= \<const0>\;
doutb(27) <= \<const0>\;
doutb(26) <= \<const0>\;
doutb(25) <= \<const0>\;
doutb(24) <= \<const0>\;
doutb(23) <= \<const0>\;
doutb(22) <= \<const0>\;
doutb(21) <= \<const0>\;
doutb(20) <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(799) <= \<const0>\;
s_axi_rdata(798) <= \<const0>\;
s_axi_rdata(797) <= \<const0>\;
s_axi_rdata(796) <= \<const0>\;
s_axi_rdata(795) <= \<const0>\;
s_axi_rdata(794) <= \<const0>\;
s_axi_rdata(793) <= \<const0>\;
s_axi_rdata(792) <= \<const0>\;
s_axi_rdata(791) <= \<const0>\;
s_axi_rdata(790) <= \<const0>\;
s_axi_rdata(789) <= \<const0>\;
s_axi_rdata(788) <= \<const0>\;
s_axi_rdata(787) <= \<const0>\;
s_axi_rdata(786) <= \<const0>\;
s_axi_rdata(785) <= \<const0>\;
s_axi_rdata(784) <= \<const0>\;
s_axi_rdata(783) <= \<const0>\;
s_axi_rdata(782) <= \<const0>\;
s_axi_rdata(781) <= \<const0>\;
s_axi_rdata(780) <= \<const0>\;
s_axi_rdata(779) <= \<const0>\;
s_axi_rdata(778) <= \<const0>\;
s_axi_rdata(777) <= \<const0>\;
s_axi_rdata(776) <= \<const0>\;
s_axi_rdata(775) <= \<const0>\;
s_axi_rdata(774) <= \<const0>\;
s_axi_rdata(773) <= \<const0>\;
s_axi_rdata(772) <= \<const0>\;
s_axi_rdata(771) <= \<const0>\;
s_axi_rdata(770) <= \<const0>\;
s_axi_rdata(769) <= \<const0>\;
s_axi_rdata(768) <= \<const0>\;
s_axi_rdata(767) <= \<const0>\;
s_axi_rdata(766) <= \<const0>\;
s_axi_rdata(765) <= \<const0>\;
s_axi_rdata(764) <= \<const0>\;
s_axi_rdata(763) <= \<const0>\;
s_axi_rdata(762) <= \<const0>\;
s_axi_rdata(761) <= \<const0>\;
s_axi_rdata(760) <= \<const0>\;
s_axi_rdata(759) <= \<const0>\;
s_axi_rdata(758) <= \<const0>\;
s_axi_rdata(757) <= \<const0>\;
s_axi_rdata(756) <= \<const0>\;
s_axi_rdata(755) <= \<const0>\;
s_axi_rdata(754) <= \<const0>\;
s_axi_rdata(753) <= \<const0>\;
s_axi_rdata(752) <= \<const0>\;
s_axi_rdata(751) <= \<const0>\;
s_axi_rdata(750) <= \<const0>\;
s_axi_rdata(749) <= \<const0>\;
s_axi_rdata(748) <= \<const0>\;
s_axi_rdata(747) <= \<const0>\;
s_axi_rdata(746) <= \<const0>\;
s_axi_rdata(745) <= \<const0>\;
s_axi_rdata(744) <= \<const0>\;
s_axi_rdata(743) <= \<const0>\;
s_axi_rdata(742) <= \<const0>\;
s_axi_rdata(741) <= \<const0>\;
s_axi_rdata(740) <= \<const0>\;
s_axi_rdata(739) <= \<const0>\;
s_axi_rdata(738) <= \<const0>\;
s_axi_rdata(737) <= \<const0>\;
s_axi_rdata(736) <= \<const0>\;
s_axi_rdata(735) <= \<const0>\;
s_axi_rdata(734) <= \<const0>\;
s_axi_rdata(733) <= \<const0>\;
s_axi_rdata(732) <= \<const0>\;
s_axi_rdata(731) <= \<const0>\;
s_axi_rdata(730) <= \<const0>\;
s_axi_rdata(729) <= \<const0>\;
s_axi_rdata(728) <= \<const0>\;
s_axi_rdata(727) <= \<const0>\;
s_axi_rdata(726) <= \<const0>\;
s_axi_rdata(725) <= \<const0>\;
s_axi_rdata(724) <= \<const0>\;
s_axi_rdata(723) <= \<const0>\;
s_axi_rdata(722) <= \<const0>\;
s_axi_rdata(721) <= \<const0>\;
s_axi_rdata(720) <= \<const0>\;
s_axi_rdata(719) <= \<const0>\;
s_axi_rdata(718) <= \<const0>\;
s_axi_rdata(717) <= \<const0>\;
s_axi_rdata(716) <= \<const0>\;
s_axi_rdata(715) <= \<const0>\;
s_axi_rdata(714) <= \<const0>\;
s_axi_rdata(713) <= \<const0>\;
s_axi_rdata(712) <= \<const0>\;
s_axi_rdata(711) <= \<const0>\;
s_axi_rdata(710) <= \<const0>\;
s_axi_rdata(709) <= \<const0>\;
s_axi_rdata(708) <= \<const0>\;
s_axi_rdata(707) <= \<const0>\;
s_axi_rdata(706) <= \<const0>\;
s_axi_rdata(705) <= \<const0>\;
s_axi_rdata(704) <= \<const0>\;
s_axi_rdata(703) <= \<const0>\;
s_axi_rdata(702) <= \<const0>\;
s_axi_rdata(701) <= \<const0>\;
s_axi_rdata(700) <= \<const0>\;
s_axi_rdata(699) <= \<const0>\;
s_axi_rdata(698) <= \<const0>\;
s_axi_rdata(697) <= \<const0>\;
s_axi_rdata(696) <= \<const0>\;
s_axi_rdata(695) <= \<const0>\;
s_axi_rdata(694) <= \<const0>\;
s_axi_rdata(693) <= \<const0>\;
s_axi_rdata(692) <= \<const0>\;
s_axi_rdata(691) <= \<const0>\;
s_axi_rdata(690) <= \<const0>\;
s_axi_rdata(689) <= \<const0>\;
s_axi_rdata(688) <= \<const0>\;
s_axi_rdata(687) <= \<const0>\;
s_axi_rdata(686) <= \<const0>\;
s_axi_rdata(685) <= \<const0>\;
s_axi_rdata(684) <= \<const0>\;
s_axi_rdata(683) <= \<const0>\;
s_axi_rdata(682) <= \<const0>\;
s_axi_rdata(681) <= \<const0>\;
s_axi_rdata(680) <= \<const0>\;
s_axi_rdata(679) <= \<const0>\;
s_axi_rdata(678) <= \<const0>\;
s_axi_rdata(677) <= \<const0>\;
s_axi_rdata(676) <= \<const0>\;
s_axi_rdata(675) <= \<const0>\;
s_axi_rdata(674) <= \<const0>\;
s_axi_rdata(673) <= \<const0>\;
s_axi_rdata(672) <= \<const0>\;
s_axi_rdata(671) <= \<const0>\;
s_axi_rdata(670) <= \<const0>\;
s_axi_rdata(669) <= \<const0>\;
s_axi_rdata(668) <= \<const0>\;
s_axi_rdata(667) <= \<const0>\;
s_axi_rdata(666) <= \<const0>\;
s_axi_rdata(665) <= \<const0>\;
s_axi_rdata(664) <= \<const0>\;
s_axi_rdata(663) <= \<const0>\;
s_axi_rdata(662) <= \<const0>\;
s_axi_rdata(661) <= \<const0>\;
s_axi_rdata(660) <= \<const0>\;
s_axi_rdata(659) <= \<const0>\;
s_axi_rdata(658) <= \<const0>\;
s_axi_rdata(657) <= \<const0>\;
s_axi_rdata(656) <= \<const0>\;
s_axi_rdata(655) <= \<const0>\;
s_axi_rdata(654) <= \<const0>\;
s_axi_rdata(653) <= \<const0>\;
s_axi_rdata(652) <= \<const0>\;
s_axi_rdata(651) <= \<const0>\;
s_axi_rdata(650) <= \<const0>\;
s_axi_rdata(649) <= \<const0>\;
s_axi_rdata(648) <= \<const0>\;
s_axi_rdata(647) <= \<const0>\;
s_axi_rdata(646) <= \<const0>\;
s_axi_rdata(645) <= \<const0>\;
s_axi_rdata(644) <= \<const0>\;
s_axi_rdata(643) <= \<const0>\;
s_axi_rdata(642) <= \<const0>\;
s_axi_rdata(641) <= \<const0>\;
s_axi_rdata(640) <= \<const0>\;
s_axi_rdata(639) <= \<const0>\;
s_axi_rdata(638) <= \<const0>\;
s_axi_rdata(637) <= \<const0>\;
s_axi_rdata(636) <= \<const0>\;
s_axi_rdata(635) <= \<const0>\;
s_axi_rdata(634) <= \<const0>\;
s_axi_rdata(633) <= \<const0>\;
s_axi_rdata(632) <= \<const0>\;
s_axi_rdata(631) <= \<const0>\;
s_axi_rdata(630) <= \<const0>\;
s_axi_rdata(629) <= \<const0>\;
s_axi_rdata(628) <= \<const0>\;
s_axi_rdata(627) <= \<const0>\;
s_axi_rdata(626) <= \<const0>\;
s_axi_rdata(625) <= \<const0>\;
s_axi_rdata(624) <= \<const0>\;
s_axi_rdata(623) <= \<const0>\;
s_axi_rdata(622) <= \<const0>\;
s_axi_rdata(621) <= \<const0>\;
s_axi_rdata(620) <= \<const0>\;
s_axi_rdata(619) <= \<const0>\;
s_axi_rdata(618) <= \<const0>\;
s_axi_rdata(617) <= \<const0>\;
s_axi_rdata(616) <= \<const0>\;
s_axi_rdata(615) <= \<const0>\;
s_axi_rdata(614) <= \<const0>\;
s_axi_rdata(613) <= \<const0>\;
s_axi_rdata(612) <= \<const0>\;
s_axi_rdata(611) <= \<const0>\;
s_axi_rdata(610) <= \<const0>\;
s_axi_rdata(609) <= \<const0>\;
s_axi_rdata(608) <= \<const0>\;
s_axi_rdata(607) <= \<const0>\;
s_axi_rdata(606) <= \<const0>\;
s_axi_rdata(605) <= \<const0>\;
s_axi_rdata(604) <= \<const0>\;
s_axi_rdata(603) <= \<const0>\;
s_axi_rdata(602) <= \<const0>\;
s_axi_rdata(601) <= \<const0>\;
s_axi_rdata(600) <= \<const0>\;
s_axi_rdata(599) <= \<const0>\;
s_axi_rdata(598) <= \<const0>\;
s_axi_rdata(597) <= \<const0>\;
s_axi_rdata(596) <= \<const0>\;
s_axi_rdata(595) <= \<const0>\;
s_axi_rdata(594) <= \<const0>\;
s_axi_rdata(593) <= \<const0>\;
s_axi_rdata(592) <= \<const0>\;
s_axi_rdata(591) <= \<const0>\;
s_axi_rdata(590) <= \<const0>\;
s_axi_rdata(589) <= \<const0>\;
s_axi_rdata(588) <= \<const0>\;
s_axi_rdata(587) <= \<const0>\;
s_axi_rdata(586) <= \<const0>\;
s_axi_rdata(585) <= \<const0>\;
s_axi_rdata(584) <= \<const0>\;
s_axi_rdata(583) <= \<const0>\;
s_axi_rdata(582) <= \<const0>\;
s_axi_rdata(581) <= \<const0>\;
s_axi_rdata(580) <= \<const0>\;
s_axi_rdata(579) <= \<const0>\;
s_axi_rdata(578) <= \<const0>\;
s_axi_rdata(577) <= \<const0>\;
s_axi_rdata(576) <= \<const0>\;
s_axi_rdata(575) <= \<const0>\;
s_axi_rdata(574) <= \<const0>\;
s_axi_rdata(573) <= \<const0>\;
s_axi_rdata(572) <= \<const0>\;
s_axi_rdata(571) <= \<const0>\;
s_axi_rdata(570) <= \<const0>\;
s_axi_rdata(569) <= \<const0>\;
s_axi_rdata(568) <= \<const0>\;
s_axi_rdata(567) <= \<const0>\;
s_axi_rdata(566) <= \<const0>\;
s_axi_rdata(565) <= \<const0>\;
s_axi_rdata(564) <= \<const0>\;
s_axi_rdata(563) <= \<const0>\;
s_axi_rdata(562) <= \<const0>\;
s_axi_rdata(561) <= \<const0>\;
s_axi_rdata(560) <= \<const0>\;
s_axi_rdata(559) <= \<const0>\;
s_axi_rdata(558) <= \<const0>\;
s_axi_rdata(557) <= \<const0>\;
s_axi_rdata(556) <= \<const0>\;
s_axi_rdata(555) <= \<const0>\;
s_axi_rdata(554) <= \<const0>\;
s_axi_rdata(553) <= \<const0>\;
s_axi_rdata(552) <= \<const0>\;
s_axi_rdata(551) <= \<const0>\;
s_axi_rdata(550) <= \<const0>\;
s_axi_rdata(549) <= \<const0>\;
s_axi_rdata(548) <= \<const0>\;
s_axi_rdata(547) <= \<const0>\;
s_axi_rdata(546) <= \<const0>\;
s_axi_rdata(545) <= \<const0>\;
s_axi_rdata(544) <= \<const0>\;
s_axi_rdata(543) <= \<const0>\;
s_axi_rdata(542) <= \<const0>\;
s_axi_rdata(541) <= \<const0>\;
s_axi_rdata(540) <= \<const0>\;
s_axi_rdata(539) <= \<const0>\;
s_axi_rdata(538) <= \<const0>\;
s_axi_rdata(537) <= \<const0>\;
s_axi_rdata(536) <= \<const0>\;
s_axi_rdata(535) <= \<const0>\;
s_axi_rdata(534) <= \<const0>\;
s_axi_rdata(533) <= \<const0>\;
s_axi_rdata(532) <= \<const0>\;
s_axi_rdata(531) <= \<const0>\;
s_axi_rdata(530) <= \<const0>\;
s_axi_rdata(529) <= \<const0>\;
s_axi_rdata(528) <= \<const0>\;
s_axi_rdata(527) <= \<const0>\;
s_axi_rdata(526) <= \<const0>\;
s_axi_rdata(525) <= \<const0>\;
s_axi_rdata(524) <= \<const0>\;
s_axi_rdata(523) <= \<const0>\;
s_axi_rdata(522) <= \<const0>\;
s_axi_rdata(521) <= \<const0>\;
s_axi_rdata(520) <= \<const0>\;
s_axi_rdata(519) <= \<const0>\;
s_axi_rdata(518) <= \<const0>\;
s_axi_rdata(517) <= \<const0>\;
s_axi_rdata(516) <= \<const0>\;
s_axi_rdata(515) <= \<const0>\;
s_axi_rdata(514) <= \<const0>\;
s_axi_rdata(513) <= \<const0>\;
s_axi_rdata(512) <= \<const0>\;
s_axi_rdata(511) <= \<const0>\;
s_axi_rdata(510) <= \<const0>\;
s_axi_rdata(509) <= \<const0>\;
s_axi_rdata(508) <= \<const0>\;
s_axi_rdata(507) <= \<const0>\;
s_axi_rdata(506) <= \<const0>\;
s_axi_rdata(505) <= \<const0>\;
s_axi_rdata(504) <= \<const0>\;
s_axi_rdata(503) <= \<const0>\;
s_axi_rdata(502) <= \<const0>\;
s_axi_rdata(501) <= \<const0>\;
s_axi_rdata(500) <= \<const0>\;
s_axi_rdata(499) <= \<const0>\;
s_axi_rdata(498) <= \<const0>\;
s_axi_rdata(497) <= \<const0>\;
s_axi_rdata(496) <= \<const0>\;
s_axi_rdata(495) <= \<const0>\;
s_axi_rdata(494) <= \<const0>\;
s_axi_rdata(493) <= \<const0>\;
s_axi_rdata(492) <= \<const0>\;
s_axi_rdata(491) <= \<const0>\;
s_axi_rdata(490) <= \<const0>\;
s_axi_rdata(489) <= \<const0>\;
s_axi_rdata(488) <= \<const0>\;
s_axi_rdata(487) <= \<const0>\;
s_axi_rdata(486) <= \<const0>\;
s_axi_rdata(485) <= \<const0>\;
s_axi_rdata(484) <= \<const0>\;
s_axi_rdata(483) <= \<const0>\;
s_axi_rdata(482) <= \<const0>\;
s_axi_rdata(481) <= \<const0>\;
s_axi_rdata(480) <= \<const0>\;
s_axi_rdata(479) <= \<const0>\;
s_axi_rdata(478) <= \<const0>\;
s_axi_rdata(477) <= \<const0>\;
s_axi_rdata(476) <= \<const0>\;
s_axi_rdata(475) <= \<const0>\;
s_axi_rdata(474) <= \<const0>\;
s_axi_rdata(473) <= \<const0>\;
s_axi_rdata(472) <= \<const0>\;
s_axi_rdata(471) <= \<const0>\;
s_axi_rdata(470) <= \<const0>\;
s_axi_rdata(469) <= \<const0>\;
s_axi_rdata(468) <= \<const0>\;
s_axi_rdata(467) <= \<const0>\;
s_axi_rdata(466) <= \<const0>\;
s_axi_rdata(465) <= \<const0>\;
s_axi_rdata(464) <= \<const0>\;
s_axi_rdata(463) <= \<const0>\;
s_axi_rdata(462) <= \<const0>\;
s_axi_rdata(461) <= \<const0>\;
s_axi_rdata(460) <= \<const0>\;
s_axi_rdata(459) <= \<const0>\;
s_axi_rdata(458) <= \<const0>\;
s_axi_rdata(457) <= \<const0>\;
s_axi_rdata(456) <= \<const0>\;
s_axi_rdata(455) <= \<const0>\;
s_axi_rdata(454) <= \<const0>\;
s_axi_rdata(453) <= \<const0>\;
s_axi_rdata(452) <= \<const0>\;
s_axi_rdata(451) <= \<const0>\;
s_axi_rdata(450) <= \<const0>\;
s_axi_rdata(449) <= \<const0>\;
s_axi_rdata(448) <= \<const0>\;
s_axi_rdata(447) <= \<const0>\;
s_axi_rdata(446) <= \<const0>\;
s_axi_rdata(445) <= \<const0>\;
s_axi_rdata(444) <= \<const0>\;
s_axi_rdata(443) <= \<const0>\;
s_axi_rdata(442) <= \<const0>\;
s_axi_rdata(441) <= \<const0>\;
s_axi_rdata(440) <= \<const0>\;
s_axi_rdata(439) <= \<const0>\;
s_axi_rdata(438) <= \<const0>\;
s_axi_rdata(437) <= \<const0>\;
s_axi_rdata(436) <= \<const0>\;
s_axi_rdata(435) <= \<const0>\;
s_axi_rdata(434) <= \<const0>\;
s_axi_rdata(433) <= \<const0>\;
s_axi_rdata(432) <= \<const0>\;
s_axi_rdata(431) <= \<const0>\;
s_axi_rdata(430) <= \<const0>\;
s_axi_rdata(429) <= \<const0>\;
s_axi_rdata(428) <= \<const0>\;
s_axi_rdata(427) <= \<const0>\;
s_axi_rdata(426) <= \<const0>\;
s_axi_rdata(425) <= \<const0>\;
s_axi_rdata(424) <= \<const0>\;
s_axi_rdata(423) <= \<const0>\;
s_axi_rdata(422) <= \<const0>\;
s_axi_rdata(421) <= \<const0>\;
s_axi_rdata(420) <= \<const0>\;
s_axi_rdata(419) <= \<const0>\;
s_axi_rdata(418) <= \<const0>\;
s_axi_rdata(417) <= \<const0>\;
s_axi_rdata(416) <= \<const0>\;
s_axi_rdata(415) <= \<const0>\;
s_axi_rdata(414) <= \<const0>\;
s_axi_rdata(413) <= \<const0>\;
s_axi_rdata(412) <= \<const0>\;
s_axi_rdata(411) <= \<const0>\;
s_axi_rdata(410) <= \<const0>\;
s_axi_rdata(409) <= \<const0>\;
s_axi_rdata(408) <= \<const0>\;
s_axi_rdata(407) <= \<const0>\;
s_axi_rdata(406) <= \<const0>\;
s_axi_rdata(405) <= \<const0>\;
s_axi_rdata(404) <= \<const0>\;
s_axi_rdata(403) <= \<const0>\;
s_axi_rdata(402) <= \<const0>\;
s_axi_rdata(401) <= \<const0>\;
s_axi_rdata(400) <= \<const0>\;
s_axi_rdata(399) <= \<const0>\;
s_axi_rdata(398) <= \<const0>\;
s_axi_rdata(397) <= \<const0>\;
s_axi_rdata(396) <= \<const0>\;
s_axi_rdata(395) <= \<const0>\;
s_axi_rdata(394) <= \<const0>\;
s_axi_rdata(393) <= \<const0>\;
s_axi_rdata(392) <= \<const0>\;
s_axi_rdata(391) <= \<const0>\;
s_axi_rdata(390) <= \<const0>\;
s_axi_rdata(389) <= \<const0>\;
s_axi_rdata(388) <= \<const0>\;
s_axi_rdata(387) <= \<const0>\;
s_axi_rdata(386) <= \<const0>\;
s_axi_rdata(385) <= \<const0>\;
s_axi_rdata(384) <= \<const0>\;
s_axi_rdata(383) <= \<const0>\;
s_axi_rdata(382) <= \<const0>\;
s_axi_rdata(381) <= \<const0>\;
s_axi_rdata(380) <= \<const0>\;
s_axi_rdata(379) <= \<const0>\;
s_axi_rdata(378) <= \<const0>\;
s_axi_rdata(377) <= \<const0>\;
s_axi_rdata(376) <= \<const0>\;
s_axi_rdata(375) <= \<const0>\;
s_axi_rdata(374) <= \<const0>\;
s_axi_rdata(373) <= \<const0>\;
s_axi_rdata(372) <= \<const0>\;
s_axi_rdata(371) <= \<const0>\;
s_axi_rdata(370) <= \<const0>\;
s_axi_rdata(369) <= \<const0>\;
s_axi_rdata(368) <= \<const0>\;
s_axi_rdata(367) <= \<const0>\;
s_axi_rdata(366) <= \<const0>\;
s_axi_rdata(365) <= \<const0>\;
s_axi_rdata(364) <= \<const0>\;
s_axi_rdata(363) <= \<const0>\;
s_axi_rdata(362) <= \<const0>\;
s_axi_rdata(361) <= \<const0>\;
s_axi_rdata(360) <= \<const0>\;
s_axi_rdata(359) <= \<const0>\;
s_axi_rdata(358) <= \<const0>\;
s_axi_rdata(357) <= \<const0>\;
s_axi_rdata(356) <= \<const0>\;
s_axi_rdata(355) <= \<const0>\;
s_axi_rdata(354) <= \<const0>\;
s_axi_rdata(353) <= \<const0>\;
s_axi_rdata(352) <= \<const0>\;
s_axi_rdata(351) <= \<const0>\;
s_axi_rdata(350) <= \<const0>\;
s_axi_rdata(349) <= \<const0>\;
s_axi_rdata(348) <= \<const0>\;
s_axi_rdata(347) <= \<const0>\;
s_axi_rdata(346) <= \<const0>\;
s_axi_rdata(345) <= \<const0>\;
s_axi_rdata(344) <= \<const0>\;
s_axi_rdata(343) <= \<const0>\;
s_axi_rdata(342) <= \<const0>\;
s_axi_rdata(341) <= \<const0>\;
s_axi_rdata(340) <= \<const0>\;
s_axi_rdata(339) <= \<const0>\;
s_axi_rdata(338) <= \<const0>\;
s_axi_rdata(337) <= \<const0>\;
s_axi_rdata(336) <= \<const0>\;
s_axi_rdata(335) <= \<const0>\;
s_axi_rdata(334) <= \<const0>\;
s_axi_rdata(333) <= \<const0>\;
s_axi_rdata(332) <= \<const0>\;
s_axi_rdata(331) <= \<const0>\;
s_axi_rdata(330) <= \<const0>\;
s_axi_rdata(329) <= \<const0>\;
s_axi_rdata(328) <= \<const0>\;
s_axi_rdata(327) <= \<const0>\;
s_axi_rdata(326) <= \<const0>\;
s_axi_rdata(325) <= \<const0>\;
s_axi_rdata(324) <= \<const0>\;
s_axi_rdata(323) <= \<const0>\;
s_axi_rdata(322) <= \<const0>\;
s_axi_rdata(321) <= \<const0>\;
s_axi_rdata(320) <= \<const0>\;
s_axi_rdata(319) <= \<const0>\;
s_axi_rdata(318) <= \<const0>\;
s_axi_rdata(317) <= \<const0>\;
s_axi_rdata(316) <= \<const0>\;
s_axi_rdata(315) <= \<const0>\;
s_axi_rdata(314) <= \<const0>\;
s_axi_rdata(313) <= \<const0>\;
s_axi_rdata(312) <= \<const0>\;
s_axi_rdata(311) <= \<const0>\;
s_axi_rdata(310) <= \<const0>\;
s_axi_rdata(309) <= \<const0>\;
s_axi_rdata(308) <= \<const0>\;
s_axi_rdata(307) <= \<const0>\;
s_axi_rdata(306) <= \<const0>\;
s_axi_rdata(305) <= \<const0>\;
s_axi_rdata(304) <= \<const0>\;
s_axi_rdata(303) <= \<const0>\;
s_axi_rdata(302) <= \<const0>\;
s_axi_rdata(301) <= \<const0>\;
s_axi_rdata(300) <= \<const0>\;
s_axi_rdata(299) <= \<const0>\;
s_axi_rdata(298) <= \<const0>\;
s_axi_rdata(297) <= \<const0>\;
s_axi_rdata(296) <= \<const0>\;
s_axi_rdata(295) <= \<const0>\;
s_axi_rdata(294) <= \<const0>\;
s_axi_rdata(293) <= \<const0>\;
s_axi_rdata(292) <= \<const0>\;
s_axi_rdata(291) <= \<const0>\;
s_axi_rdata(290) <= \<const0>\;
s_axi_rdata(289) <= \<const0>\;
s_axi_rdata(288) <= \<const0>\;
s_axi_rdata(287) <= \<const0>\;
s_axi_rdata(286) <= \<const0>\;
s_axi_rdata(285) <= \<const0>\;
s_axi_rdata(284) <= \<const0>\;
s_axi_rdata(283) <= \<const0>\;
s_axi_rdata(282) <= \<const0>\;
s_axi_rdata(281) <= \<const0>\;
s_axi_rdata(280) <= \<const0>\;
s_axi_rdata(279) <= \<const0>\;
s_axi_rdata(278) <= \<const0>\;
s_axi_rdata(277) <= \<const0>\;
s_axi_rdata(276) <= \<const0>\;
s_axi_rdata(275) <= \<const0>\;
s_axi_rdata(274) <= \<const0>\;
s_axi_rdata(273) <= \<const0>\;
s_axi_rdata(272) <= \<const0>\;
s_axi_rdata(271) <= \<const0>\;
s_axi_rdata(270) <= \<const0>\;
s_axi_rdata(269) <= \<const0>\;
s_axi_rdata(268) <= \<const0>\;
s_axi_rdata(267) <= \<const0>\;
s_axi_rdata(266) <= \<const0>\;
s_axi_rdata(265) <= \<const0>\;
s_axi_rdata(264) <= \<const0>\;
s_axi_rdata(263) <= \<const0>\;
s_axi_rdata(262) <= \<const0>\;
s_axi_rdata(261) <= \<const0>\;
s_axi_rdata(260) <= \<const0>\;
s_axi_rdata(259) <= \<const0>\;
s_axi_rdata(258) <= \<const0>\;
s_axi_rdata(257) <= \<const0>\;
s_axi_rdata(256) <= \<const0>\;
s_axi_rdata(255) <= \<const0>\;
s_axi_rdata(254) <= \<const0>\;
s_axi_rdata(253) <= \<const0>\;
s_axi_rdata(252) <= \<const0>\;
s_axi_rdata(251) <= \<const0>\;
s_axi_rdata(250) <= \<const0>\;
s_axi_rdata(249) <= \<const0>\;
s_axi_rdata(248) <= \<const0>\;
s_axi_rdata(247) <= \<const0>\;
s_axi_rdata(246) <= \<const0>\;
s_axi_rdata(245) <= \<const0>\;
s_axi_rdata(244) <= \<const0>\;
s_axi_rdata(243) <= \<const0>\;
s_axi_rdata(242) <= \<const0>\;
s_axi_rdata(241) <= \<const0>\;
s_axi_rdata(240) <= \<const0>\;
s_axi_rdata(239) <= \<const0>\;
s_axi_rdata(238) <= \<const0>\;
s_axi_rdata(237) <= \<const0>\;
s_axi_rdata(236) <= \<const0>\;
s_axi_rdata(235) <= \<const0>\;
s_axi_rdata(234) <= \<const0>\;
s_axi_rdata(233) <= \<const0>\;
s_axi_rdata(232) <= \<const0>\;
s_axi_rdata(231) <= \<const0>\;
s_axi_rdata(230) <= \<const0>\;
s_axi_rdata(229) <= \<const0>\;
s_axi_rdata(228) <= \<const0>\;
s_axi_rdata(227) <= \<const0>\;
s_axi_rdata(226) <= \<const0>\;
s_axi_rdata(225) <= \<const0>\;
s_axi_rdata(224) <= \<const0>\;
s_axi_rdata(223) <= \<const0>\;
s_axi_rdata(222) <= \<const0>\;
s_axi_rdata(221) <= \<const0>\;
s_axi_rdata(220) <= \<const0>\;
s_axi_rdata(219) <= \<const0>\;
s_axi_rdata(218) <= \<const0>\;
s_axi_rdata(217) <= \<const0>\;
s_axi_rdata(216) <= \<const0>\;
s_axi_rdata(215) <= \<const0>\;
s_axi_rdata(214) <= \<const0>\;
s_axi_rdata(213) <= \<const0>\;
s_axi_rdata(212) <= \<const0>\;
s_axi_rdata(211) <= \<const0>\;
s_axi_rdata(210) <= \<const0>\;
s_axi_rdata(209) <= \<const0>\;
s_axi_rdata(208) <= \<const0>\;
s_axi_rdata(207) <= \<const0>\;
s_axi_rdata(206) <= \<const0>\;
s_axi_rdata(205) <= \<const0>\;
s_axi_rdata(204) <= \<const0>\;
s_axi_rdata(203) <= \<const0>\;
s_axi_rdata(202) <= \<const0>\;
s_axi_rdata(201) <= \<const0>\;
s_axi_rdata(200) <= \<const0>\;
s_axi_rdata(199) <= \<const0>\;
s_axi_rdata(198) <= \<const0>\;
s_axi_rdata(197) <= \<const0>\;
s_axi_rdata(196) <= \<const0>\;
s_axi_rdata(195) <= \<const0>\;
s_axi_rdata(194) <= \<const0>\;
s_axi_rdata(193) <= \<const0>\;
s_axi_rdata(192) <= \<const0>\;
s_axi_rdata(191) <= \<const0>\;
s_axi_rdata(190) <= \<const0>\;
s_axi_rdata(189) <= \<const0>\;
s_axi_rdata(188) <= \<const0>\;
s_axi_rdata(187) <= \<const0>\;
s_axi_rdata(186) <= \<const0>\;
s_axi_rdata(185) <= \<const0>\;
s_axi_rdata(184) <= \<const0>\;
s_axi_rdata(183) <= \<const0>\;
s_axi_rdata(182) <= \<const0>\;
s_axi_rdata(181) <= \<const0>\;
s_axi_rdata(180) <= \<const0>\;
s_axi_rdata(179) <= \<const0>\;
s_axi_rdata(178) <= \<const0>\;
s_axi_rdata(177) <= \<const0>\;
s_axi_rdata(176) <= \<const0>\;
s_axi_rdata(175) <= \<const0>\;
s_axi_rdata(174) <= \<const0>\;
s_axi_rdata(173) <= \<const0>\;
s_axi_rdata(172) <= \<const0>\;
s_axi_rdata(171) <= \<const0>\;
s_axi_rdata(170) <= \<const0>\;
s_axi_rdata(169) <= \<const0>\;
s_axi_rdata(168) <= \<const0>\;
s_axi_rdata(167) <= \<const0>\;
s_axi_rdata(166) <= \<const0>\;
s_axi_rdata(165) <= \<const0>\;
s_axi_rdata(164) <= \<const0>\;
s_axi_rdata(163) <= \<const0>\;
s_axi_rdata(162) <= \<const0>\;
s_axi_rdata(161) <= \<const0>\;
s_axi_rdata(160) <= \<const0>\;
s_axi_rdata(159) <= \<const0>\;
s_axi_rdata(158) <= \<const0>\;
s_axi_rdata(157) <= \<const0>\;
s_axi_rdata(156) <= \<const0>\;
s_axi_rdata(155) <= \<const0>\;
s_axi_rdata(154) <= \<const0>\;
s_axi_rdata(153) <= \<const0>\;
s_axi_rdata(152) <= \<const0>\;
s_axi_rdata(151) <= \<const0>\;
s_axi_rdata(150) <= \<const0>\;
s_axi_rdata(149) <= \<const0>\;
s_axi_rdata(148) <= \<const0>\;
s_axi_rdata(147) <= \<const0>\;
s_axi_rdata(146) <= \<const0>\;
s_axi_rdata(145) <= \<const0>\;
s_axi_rdata(144) <= \<const0>\;
s_axi_rdata(143) <= \<const0>\;
s_axi_rdata(142) <= \<const0>\;
s_axi_rdata(141) <= \<const0>\;
s_axi_rdata(140) <= \<const0>\;
s_axi_rdata(139) <= \<const0>\;
s_axi_rdata(138) <= \<const0>\;
s_axi_rdata(137) <= \<const0>\;
s_axi_rdata(136) <= \<const0>\;
s_axi_rdata(135) <= \<const0>\;
s_axi_rdata(134) <= \<const0>\;
s_axi_rdata(133) <= \<const0>\;
s_axi_rdata(132) <= \<const0>\;
s_axi_rdata(131) <= \<const0>\;
s_axi_rdata(130) <= \<const0>\;
s_axi_rdata(129) <= \<const0>\;
s_axi_rdata(128) <= \<const0>\;
s_axi_rdata(127) <= \<const0>\;
s_axi_rdata(126) <= \<const0>\;
s_axi_rdata(125) <= \<const0>\;
s_axi_rdata(124) <= \<const0>\;
s_axi_rdata(123) <= \<const0>\;
s_axi_rdata(122) <= \<const0>\;
s_axi_rdata(121) <= \<const0>\;
s_axi_rdata(120) <= \<const0>\;
s_axi_rdata(119) <= \<const0>\;
s_axi_rdata(118) <= \<const0>\;
s_axi_rdata(117) <= \<const0>\;
s_axi_rdata(116) <= \<const0>\;
s_axi_rdata(115) <= \<const0>\;
s_axi_rdata(114) <= \<const0>\;
s_axi_rdata(113) <= \<const0>\;
s_axi_rdata(112) <= \<const0>\;
s_axi_rdata(111) <= \<const0>\;
s_axi_rdata(110) <= \<const0>\;
s_axi_rdata(109) <= \<const0>\;
s_axi_rdata(108) <= \<const0>\;
s_axi_rdata(107) <= \<const0>\;
s_axi_rdata(106) <= \<const0>\;
s_axi_rdata(105) <= \<const0>\;
s_axi_rdata(104) <= \<const0>\;
s_axi_rdata(103) <= \<const0>\;
s_axi_rdata(102) <= \<const0>\;
s_axi_rdata(101) <= \<const0>\;
s_axi_rdata(100) <= \<const0>\;
s_axi_rdata(99) <= \<const0>\;
s_axi_rdata(98) <= \<const0>\;
s_axi_rdata(97) <= \<const0>\;
s_axi_rdata(96) <= \<const0>\;
s_axi_rdata(95) <= \<const0>\;
s_axi_rdata(94) <= \<const0>\;
s_axi_rdata(93) <= \<const0>\;
s_axi_rdata(92) <= \<const0>\;
s_axi_rdata(91) <= \<const0>\;
s_axi_rdata(90) <= \<const0>\;
s_axi_rdata(89) <= \<const0>\;
s_axi_rdata(88) <= \<const0>\;
s_axi_rdata(87) <= \<const0>\;
s_axi_rdata(86) <= \<const0>\;
s_axi_rdata(85) <= \<const0>\;
s_axi_rdata(84) <= \<const0>\;
s_axi_rdata(83) <= \<const0>\;
s_axi_rdata(82) <= \<const0>\;
s_axi_rdata(81) <= \<const0>\;
s_axi_rdata(80) <= \<const0>\;
s_axi_rdata(79) <= \<const0>\;
s_axi_rdata(78) <= \<const0>\;
s_axi_rdata(77) <= \<const0>\;
s_axi_rdata(76) <= \<const0>\;
s_axi_rdata(75) <= \<const0>\;
s_axi_rdata(74) <= \<const0>\;
s_axi_rdata(73) <= \<const0>\;
s_axi_rdata(72) <= \<const0>\;
s_axi_rdata(71) <= \<const0>\;
s_axi_rdata(70) <= \<const0>\;
s_axi_rdata(69) <= \<const0>\;
s_axi_rdata(68) <= \<const0>\;
s_axi_rdata(67) <= \<const0>\;
s_axi_rdata(66) <= \<const0>\;
s_axi_rdata(65) <= \<const0>\;
s_axi_rdata(64) <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.About_blk_mem_gen_v8_2_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity About is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of About : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of About : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of About : entity is "blk_mem_gen_v8_2,Vivado 2014.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of About : entity is "About,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of About : entity is "About,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=About.mif,C_INIT_FILE=About.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}";
end About;
architecture STRUCTURE of About is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "22";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 60.4532 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "About.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "About.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 800;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 800;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 800;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\About_blk_mem_gen_v8_2__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(799) => '0',
dina(798) => '0',
dina(797) => '0',
dina(796) => '0',
dina(795) => '0',
dina(794) => '0',
dina(793) => '0',
dina(792) => '0',
dina(791) => '0',
dina(790) => '0',
dina(789) => '0',
dina(788) => '0',
dina(787) => '0',
dina(786) => '0',
dina(785) => '0',
dina(784) => '0',
dina(783) => '0',
dina(782) => '0',
dina(781) => '0',
dina(780) => '0',
dina(779) => '0',
dina(778) => '0',
dina(777) => '0',
dina(776) => '0',
dina(775) => '0',
dina(774) => '0',
dina(773) => '0',
dina(772) => '0',
dina(771) => '0',
dina(770) => '0',
dina(769) => '0',
dina(768) => '0',
dina(767) => '0',
dina(766) => '0',
dina(765) => '0',
dina(764) => '0',
dina(763) => '0',
dina(762) => '0',
dina(761) => '0',
dina(760) => '0',
dina(759) => '0',
dina(758) => '0',
dina(757) => '0',
dina(756) => '0',
dina(755) => '0',
dina(754) => '0',
dina(753) => '0',
dina(752) => '0',
dina(751) => '0',
dina(750) => '0',
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dinb(74) => '0',
dinb(73) => '0',
dinb(72) => '0',
dinb(71) => '0',
dinb(70) => '0',
dinb(69) => '0',
dinb(68) => '0',
dinb(67) => '0',
dinb(66) => '0',
dinb(65) => '0',
dinb(64) => '0',
dinb(63) => '0',
dinb(62) => '0',
dinb(61) => '0',
dinb(60) => '0',
dinb(59) => '0',
dinb(58) => '0',
dinb(57) => '0',
dinb(56) => '0',
dinb(55) => '0',
dinb(54) => '0',
dinb(53) => '0',
dinb(52) => '0',
dinb(51) => '0',
dinb(50) => '0',
dinb(49) => '0',
dinb(48) => '0',
dinb(47) => '0',
dinb(46) => '0',
dinb(45) => '0',
dinb(44) => '0',
dinb(43) => '0',
dinb(42) => '0',
dinb(41) => '0',
dinb(40) => '0',
dinb(39) => '0',
dinb(38) => '0',
dinb(37) => '0',
dinb(36) => '0',
dinb(35) => '0',
dinb(34) => '0',
dinb(33) => '0',
dinb(32) => '0',
dinb(31) => '0',
dinb(30) => '0',
dinb(29) => '0',
dinb(28) => '0',
dinb(27) => '0',
dinb(26) => '0',
dinb(25) => '0',
dinb(24) => '0',
dinb(23) => '0',
dinb(22) => '0',
dinb(21) => '0',
dinb(20) => '0',
dinb(19) => '0',
dinb(18) => '0',
dinb(17) => '0',
dinb(16) => '0',
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(799 downto 0) => douta(799 downto 0),
doutb(799 downto 0) => NLW_U0_doutb_UNCONNECTED(799 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(799 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(799 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(799) => '0',
s_axi_wdata(798) => '0',
s_axi_wdata(797) => '0',
s_axi_wdata(796) => '0',
s_axi_wdata(795) => '0',
s_axi_wdata(794) => '0',
s_axi_wdata(793) => '0',
s_axi_wdata(792) => '0',
s_axi_wdata(791) => '0',
s_axi_wdata(790) => '0',
s_axi_wdata(789) => '0',
s_axi_wdata(788) => '0',
s_axi_wdata(787) => '0',
s_axi_wdata(786) => '0',
s_axi_wdata(785) => '0',
s_axi_wdata(784) => '0',
s_axi_wdata(783) => '0',
s_axi_wdata(782) => '0',
s_axi_wdata(781) => '0',
s_axi_wdata(780) => '0',
s_axi_wdata(779) => '0',
s_axi_wdata(778) => '0',
s_axi_wdata(777) => '0',
s_axi_wdata(776) => '0',
s_axi_wdata(775) => '0',
s_axi_wdata(774) => '0',
s_axi_wdata(773) => '0',
s_axi_wdata(772) => '0',
s_axi_wdata(771) => '0',
s_axi_wdata(770) => '0',
s_axi_wdata(769) => '0',
s_axi_wdata(768) => '0',
s_axi_wdata(767) => '0',
s_axi_wdata(766) => '0',
s_axi_wdata(765) => '0',
s_axi_wdata(764) => '0',
s_axi_wdata(763) => '0',
s_axi_wdata(762) => '0',
s_axi_wdata(761) => '0',
s_axi_wdata(760) => '0',
s_axi_wdata(759) => '0',
s_axi_wdata(758) => '0',
s_axi_wdata(757) => '0',
s_axi_wdata(756) => '0',
s_axi_wdata(755) => '0',
s_axi_wdata(754) => '0',
s_axi_wdata(753) => '0',
s_axi_wdata(752) => '0',
s_axi_wdata(751) => '0',
s_axi_wdata(750) => '0',
s_axi_wdata(749) => '0',
s_axi_wdata(748) => '0',
s_axi_wdata(747) => '0',
s_axi_wdata(746) => '0',
s_axi_wdata(745) => '0',
s_axi_wdata(744) => '0',
s_axi_wdata(743) => '0',
s_axi_wdata(742) => '0',
s_axi_wdata(741) => '0',
s_axi_wdata(740) => '0',
s_axi_wdata(739) => '0',
s_axi_wdata(738) => '0',
s_axi_wdata(737) => '0',
s_axi_wdata(736) => '0',
s_axi_wdata(735) => '0',
s_axi_wdata(734) => '0',
s_axi_wdata(733) => '0',
s_axi_wdata(732) => '0',
s_axi_wdata(731) => '0',
s_axi_wdata(730) => '0',
s_axi_wdata(729) => '0',
s_axi_wdata(728) => '0',
s_axi_wdata(727) => '0',
s_axi_wdata(726) => '0',
s_axi_wdata(725) => '0',
s_axi_wdata(724) => '0',
s_axi_wdata(723) => '0',
s_axi_wdata(722) => '0',
s_axi_wdata(721) => '0',
s_axi_wdata(720) => '0',
s_axi_wdata(719) => '0',
s_axi_wdata(718) => '0',
s_axi_wdata(717) => '0',
s_axi_wdata(716) => '0',
s_axi_wdata(715) => '0',
s_axi_wdata(714) => '0',
s_axi_wdata(713) => '0',
s_axi_wdata(712) => '0',
s_axi_wdata(711) => '0',
s_axi_wdata(710) => '0',
s_axi_wdata(709) => '0',
s_axi_wdata(708) => '0',
s_axi_wdata(707) => '0',
s_axi_wdata(706) => '0',
s_axi_wdata(705) => '0',
s_axi_wdata(704) => '0',
s_axi_wdata(703) => '0',
s_axi_wdata(702) => '0',
s_axi_wdata(701) => '0',
s_axi_wdata(700) => '0',
s_axi_wdata(699) => '0',
s_axi_wdata(698) => '0',
s_axi_wdata(697) => '0',
s_axi_wdata(696) => '0',
s_axi_wdata(695) => '0',
s_axi_wdata(694) => '0',
s_axi_wdata(693) => '0',
s_axi_wdata(692) => '0',
s_axi_wdata(691) => '0',
s_axi_wdata(690) => '0',
s_axi_wdata(689) => '0',
s_axi_wdata(688) => '0',
s_axi_wdata(687) => '0',
s_axi_wdata(686) => '0',
s_axi_wdata(685) => '0',
s_axi_wdata(684) => '0',
s_axi_wdata(683) => '0',
s_axi_wdata(682) => '0',
s_axi_wdata(681) => '0',
s_axi_wdata(680) => '0',
s_axi_wdata(679) => '0',
s_axi_wdata(678) => '0',
s_axi_wdata(677) => '0',
s_axi_wdata(676) => '0',
s_axi_wdata(675) => '0',
s_axi_wdata(674) => '0',
s_axi_wdata(673) => '0',
s_axi_wdata(672) => '0',
s_axi_wdata(671) => '0',
s_axi_wdata(670) => '0',
s_axi_wdata(669) => '0',
s_axi_wdata(668) => '0',
s_axi_wdata(667) => '0',
s_axi_wdata(666) => '0',
s_axi_wdata(665) => '0',
s_axi_wdata(664) => '0',
s_axi_wdata(663) => '0',
s_axi_wdata(662) => '0',
s_axi_wdata(661) => '0',
s_axi_wdata(660) => '0',
s_axi_wdata(659) => '0',
s_axi_wdata(658) => '0',
s_axi_wdata(657) => '0',
s_axi_wdata(656) => '0',
s_axi_wdata(655) => '0',
s_axi_wdata(654) => '0',
s_axi_wdata(653) => '0',
s_axi_wdata(652) => '0',
s_axi_wdata(651) => '0',
s_axi_wdata(650) => '0',
s_axi_wdata(649) => '0',
s_axi_wdata(648) => '0',
s_axi_wdata(647) => '0',
s_axi_wdata(646) => '0',
s_axi_wdata(645) => '0',
s_axi_wdata(644) => '0',
s_axi_wdata(643) => '0',
s_axi_wdata(642) => '0',
s_axi_wdata(641) => '0',
s_axi_wdata(640) => '0',
s_axi_wdata(639) => '0',
s_axi_wdata(638) => '0',
s_axi_wdata(637) => '0',
s_axi_wdata(636) => '0',
s_axi_wdata(635) => '0',
s_axi_wdata(634) => '0',
s_axi_wdata(633) => '0',
s_axi_wdata(632) => '0',
s_axi_wdata(631) => '0',
s_axi_wdata(630) => '0',
s_axi_wdata(629) => '0',
s_axi_wdata(628) => '0',
s_axi_wdata(627) => '0',
s_axi_wdata(626) => '0',
s_axi_wdata(625) => '0',
s_axi_wdata(624) => '0',
s_axi_wdata(623) => '0',
s_axi_wdata(622) => '0',
s_axi_wdata(621) => '0',
s_axi_wdata(620) => '0',
s_axi_wdata(619) => '0',
s_axi_wdata(618) => '0',
s_axi_wdata(617) => '0',
s_axi_wdata(616) => '0',
s_axi_wdata(615) => '0',
s_axi_wdata(614) => '0',
s_axi_wdata(613) => '0',
s_axi_wdata(612) => '0',
s_axi_wdata(611) => '0',
s_axi_wdata(610) => '0',
s_axi_wdata(609) => '0',
s_axi_wdata(608) => '0',
s_axi_wdata(607) => '0',
s_axi_wdata(606) => '0',
s_axi_wdata(605) => '0',
s_axi_wdata(604) => '0',
s_axi_wdata(603) => '0',
s_axi_wdata(602) => '0',
s_axi_wdata(601) => '0',
s_axi_wdata(600) => '0',
s_axi_wdata(599) => '0',
s_axi_wdata(598) => '0',
s_axi_wdata(597) => '0',
s_axi_wdata(596) => '0',
s_axi_wdata(595) => '0',
s_axi_wdata(594) => '0',
s_axi_wdata(593) => '0',
s_axi_wdata(592) => '0',
s_axi_wdata(591) => '0',
s_axi_wdata(590) => '0',
s_axi_wdata(589) => '0',
s_axi_wdata(588) => '0',
s_axi_wdata(587) => '0',
s_axi_wdata(586) => '0',
s_axi_wdata(585) => '0',
s_axi_wdata(584) => '0',
s_axi_wdata(583) => '0',
s_axi_wdata(582) => '0',
s_axi_wdata(581) => '0',
s_axi_wdata(580) => '0',
s_axi_wdata(579) => '0',
s_axi_wdata(578) => '0',
s_axi_wdata(577) => '0',
s_axi_wdata(576) => '0',
s_axi_wdata(575) => '0',
s_axi_wdata(574) => '0',
s_axi_wdata(573) => '0',
s_axi_wdata(572) => '0',
s_axi_wdata(571) => '0',
s_axi_wdata(570) => '0',
s_axi_wdata(569) => '0',
s_axi_wdata(568) => '0',
s_axi_wdata(567) => '0',
s_axi_wdata(566) => '0',
s_axi_wdata(565) => '0',
s_axi_wdata(564) => '0',
s_axi_wdata(563) => '0',
s_axi_wdata(562) => '0',
s_axi_wdata(561) => '0',
s_axi_wdata(560) => '0',
s_axi_wdata(559) => '0',
s_axi_wdata(558) => '0',
s_axi_wdata(557) => '0',
s_axi_wdata(556) => '0',
s_axi_wdata(555) => '0',
s_axi_wdata(554) => '0',
s_axi_wdata(553) => '0',
s_axi_wdata(552) => '0',
s_axi_wdata(551) => '0',
s_axi_wdata(550) => '0',
s_axi_wdata(549) => '0',
s_axi_wdata(548) => '0',
s_axi_wdata(547) => '0',
s_axi_wdata(546) => '0',
s_axi_wdata(545) => '0',
s_axi_wdata(544) => '0',
s_axi_wdata(543) => '0',
s_axi_wdata(542) => '0',
s_axi_wdata(541) => '0',
s_axi_wdata(540) => '0',
s_axi_wdata(539) => '0',
s_axi_wdata(538) => '0',
s_axi_wdata(537) => '0',
s_axi_wdata(536) => '0',
s_axi_wdata(535) => '0',
s_axi_wdata(534) => '0',
s_axi_wdata(533) => '0',
s_axi_wdata(532) => '0',
s_axi_wdata(531) => '0',
s_axi_wdata(530) => '0',
s_axi_wdata(529) => '0',
s_axi_wdata(528) => '0',
s_axi_wdata(527) => '0',
s_axi_wdata(526) => '0',
s_axi_wdata(525) => '0',
s_axi_wdata(524) => '0',
s_axi_wdata(523) => '0',
s_axi_wdata(522) => '0',
s_axi_wdata(521) => '0',
s_axi_wdata(520) => '0',
s_axi_wdata(519) => '0',
s_axi_wdata(518) => '0',
s_axi_wdata(517) => '0',
s_axi_wdata(516) => '0',
s_axi_wdata(515) => '0',
s_axi_wdata(514) => '0',
s_axi_wdata(513) => '0',
s_axi_wdata(512) => '0',
s_axi_wdata(511) => '0',
s_axi_wdata(510) => '0',
s_axi_wdata(509) => '0',
s_axi_wdata(508) => '0',
s_axi_wdata(507) => '0',
s_axi_wdata(506) => '0',
s_axi_wdata(505) => '0',
s_axi_wdata(504) => '0',
s_axi_wdata(503) => '0',
s_axi_wdata(502) => '0',
s_axi_wdata(501) => '0',
s_axi_wdata(500) => '0',
s_axi_wdata(499) => '0',
s_axi_wdata(498) => '0',
s_axi_wdata(497) => '0',
s_axi_wdata(496) => '0',
s_axi_wdata(495) => '0',
s_axi_wdata(494) => '0',
s_axi_wdata(493) => '0',
s_axi_wdata(492) => '0',
s_axi_wdata(491) => '0',
s_axi_wdata(490) => '0',
s_axi_wdata(489) => '0',
s_axi_wdata(488) => '0',
s_axi_wdata(487) => '0',
s_axi_wdata(486) => '0',
s_axi_wdata(485) => '0',
s_axi_wdata(484) => '0',
s_axi_wdata(483) => '0',
s_axi_wdata(482) => '0',
s_axi_wdata(481) => '0',
s_axi_wdata(480) => '0',
s_axi_wdata(479) => '0',
s_axi_wdata(478) => '0',
s_axi_wdata(477) => '0',
s_axi_wdata(476) => '0',
s_axi_wdata(475) => '0',
s_axi_wdata(474) => '0',
s_axi_wdata(473) => '0',
s_axi_wdata(472) => '0',
s_axi_wdata(471) => '0',
s_axi_wdata(470) => '0',
s_axi_wdata(469) => '0',
s_axi_wdata(468) => '0',
s_axi_wdata(467) => '0',
s_axi_wdata(466) => '0',
s_axi_wdata(465) => '0',
s_axi_wdata(464) => '0',
s_axi_wdata(463) => '0',
s_axi_wdata(462) => '0',
s_axi_wdata(461) => '0',
s_axi_wdata(460) => '0',
s_axi_wdata(459) => '0',
s_axi_wdata(458) => '0',
s_axi_wdata(457) => '0',
s_axi_wdata(456) => '0',
s_axi_wdata(455) => '0',
s_axi_wdata(454) => '0',
s_axi_wdata(453) => '0',
s_axi_wdata(452) => '0',
s_axi_wdata(451) => '0',
s_axi_wdata(450) => '0',
s_axi_wdata(449) => '0',
s_axi_wdata(448) => '0',
s_axi_wdata(447) => '0',
s_axi_wdata(446) => '0',
s_axi_wdata(445) => '0',
s_axi_wdata(444) => '0',
s_axi_wdata(443) => '0',
s_axi_wdata(442) => '0',
s_axi_wdata(441) => '0',
s_axi_wdata(440) => '0',
s_axi_wdata(439) => '0',
s_axi_wdata(438) => '0',
s_axi_wdata(437) => '0',
s_axi_wdata(436) => '0',
s_axi_wdata(435) => '0',
s_axi_wdata(434) => '0',
s_axi_wdata(433) => '0',
s_axi_wdata(432) => '0',
s_axi_wdata(431) => '0',
s_axi_wdata(430) => '0',
s_axi_wdata(429) => '0',
s_axi_wdata(428) => '0',
s_axi_wdata(427) => '0',
s_axi_wdata(426) => '0',
s_axi_wdata(425) => '0',
s_axi_wdata(424) => '0',
s_axi_wdata(423) => '0',
s_axi_wdata(422) => '0',
s_axi_wdata(421) => '0',
s_axi_wdata(420) => '0',
s_axi_wdata(419) => '0',
s_axi_wdata(418) => '0',
s_axi_wdata(417) => '0',
s_axi_wdata(416) => '0',
s_axi_wdata(415) => '0',
s_axi_wdata(414) => '0',
s_axi_wdata(413) => '0',
s_axi_wdata(412) => '0',
s_axi_wdata(411) => '0',
s_axi_wdata(410) => '0',
s_axi_wdata(409) => '0',
s_axi_wdata(408) => '0',
s_axi_wdata(407) => '0',
s_axi_wdata(406) => '0',
s_axi_wdata(405) => '0',
s_axi_wdata(404) => '0',
s_axi_wdata(403) => '0',
s_axi_wdata(402) => '0',
s_axi_wdata(401) => '0',
s_axi_wdata(400) => '0',
s_axi_wdata(399) => '0',
s_axi_wdata(398) => '0',
s_axi_wdata(397) => '0',
s_axi_wdata(396) => '0',
s_axi_wdata(395) => '0',
s_axi_wdata(394) => '0',
s_axi_wdata(393) => '0',
s_axi_wdata(392) => '0',
s_axi_wdata(391) => '0',
s_axi_wdata(390) => '0',
s_axi_wdata(389) => '0',
s_axi_wdata(388) => '0',
s_axi_wdata(387) => '0',
s_axi_wdata(386) => '0',
s_axi_wdata(385) => '0',
s_axi_wdata(384) => '0',
s_axi_wdata(383) => '0',
s_axi_wdata(382) => '0',
s_axi_wdata(381) => '0',
s_axi_wdata(380) => '0',
s_axi_wdata(379) => '0',
s_axi_wdata(378) => '0',
s_axi_wdata(377) => '0',
s_axi_wdata(376) => '0',
s_axi_wdata(375) => '0',
s_axi_wdata(374) => '0',
s_axi_wdata(373) => '0',
s_axi_wdata(372) => '0',
s_axi_wdata(371) => '0',
s_axi_wdata(370) => '0',
s_axi_wdata(369) => '0',
s_axi_wdata(368) => '0',
s_axi_wdata(367) => '0',
s_axi_wdata(366) => '0',
s_axi_wdata(365) => '0',
s_axi_wdata(364) => '0',
s_axi_wdata(363) => '0',
s_axi_wdata(362) => '0',
s_axi_wdata(361) => '0',
s_axi_wdata(360) => '0',
s_axi_wdata(359) => '0',
s_axi_wdata(358) => '0',
s_axi_wdata(357) => '0',
s_axi_wdata(356) => '0',
s_axi_wdata(355) => '0',
s_axi_wdata(354) => '0',
s_axi_wdata(353) => '0',
s_axi_wdata(352) => '0',
s_axi_wdata(351) => '0',
s_axi_wdata(350) => '0',
s_axi_wdata(349) => '0',
s_axi_wdata(348) => '0',
s_axi_wdata(347) => '0',
s_axi_wdata(346) => '0',
s_axi_wdata(345) => '0',
s_axi_wdata(344) => '0',
s_axi_wdata(343) => '0',
s_axi_wdata(342) => '0',
s_axi_wdata(341) => '0',
s_axi_wdata(340) => '0',
s_axi_wdata(339) => '0',
s_axi_wdata(338) => '0',
s_axi_wdata(337) => '0',
s_axi_wdata(336) => '0',
s_axi_wdata(335) => '0',
s_axi_wdata(334) => '0',
s_axi_wdata(333) => '0',
s_axi_wdata(332) => '0',
s_axi_wdata(331) => '0',
s_axi_wdata(330) => '0',
s_axi_wdata(329) => '0',
s_axi_wdata(328) => '0',
s_axi_wdata(327) => '0',
s_axi_wdata(326) => '0',
s_axi_wdata(325) => '0',
s_axi_wdata(324) => '0',
s_axi_wdata(323) => '0',
s_axi_wdata(322) => '0',
s_axi_wdata(321) => '0',
s_axi_wdata(320) => '0',
s_axi_wdata(319) => '0',
s_axi_wdata(318) => '0',
s_axi_wdata(317) => '0',
s_axi_wdata(316) => '0',
s_axi_wdata(315) => '0',
s_axi_wdata(314) => '0',
s_axi_wdata(313) => '0',
s_axi_wdata(312) => '0',
s_axi_wdata(311) => '0',
s_axi_wdata(310) => '0',
s_axi_wdata(309) => '0',
s_axi_wdata(308) => '0',
s_axi_wdata(307) => '0',
s_axi_wdata(306) => '0',
s_axi_wdata(305) => '0',
s_axi_wdata(304) => '0',
s_axi_wdata(303) => '0',
s_axi_wdata(302) => '0',
s_axi_wdata(301) => '0',
s_axi_wdata(300) => '0',
s_axi_wdata(299) => '0',
s_axi_wdata(298) => '0',
s_axi_wdata(297) => '0',
s_axi_wdata(296) => '0',
s_axi_wdata(295) => '0',
s_axi_wdata(294) => '0',
s_axi_wdata(293) => '0',
s_axi_wdata(292) => '0',
s_axi_wdata(291) => '0',
s_axi_wdata(290) => '0',
s_axi_wdata(289) => '0',
s_axi_wdata(288) => '0',
s_axi_wdata(287) => '0',
s_axi_wdata(286) => '0',
s_axi_wdata(285) => '0',
s_axi_wdata(284) => '0',
s_axi_wdata(283) => '0',
s_axi_wdata(282) => '0',
s_axi_wdata(281) => '0',
s_axi_wdata(280) => '0',
s_axi_wdata(279) => '0',
s_axi_wdata(278) => '0',
s_axi_wdata(277) => '0',
s_axi_wdata(276) => '0',
s_axi_wdata(275) => '0',
s_axi_wdata(274) => '0',
s_axi_wdata(273) => '0',
s_axi_wdata(272) => '0',
s_axi_wdata(271) => '0',
s_axi_wdata(270) => '0',
s_axi_wdata(269) => '0',
s_axi_wdata(268) => '0',
s_axi_wdata(267) => '0',
s_axi_wdata(266) => '0',
s_axi_wdata(265) => '0',
s_axi_wdata(264) => '0',
s_axi_wdata(263) => '0',
s_axi_wdata(262) => '0',
s_axi_wdata(261) => '0',
s_axi_wdata(260) => '0',
s_axi_wdata(259) => '0',
s_axi_wdata(258) => '0',
s_axi_wdata(257) => '0',
s_axi_wdata(256) => '0',
s_axi_wdata(255) => '0',
s_axi_wdata(254) => '0',
s_axi_wdata(253) => '0',
s_axi_wdata(252) => '0',
s_axi_wdata(251) => '0',
s_axi_wdata(250) => '0',
s_axi_wdata(249) => '0',
s_axi_wdata(248) => '0',
s_axi_wdata(247) => '0',
s_axi_wdata(246) => '0',
s_axi_wdata(245) => '0',
s_axi_wdata(244) => '0',
s_axi_wdata(243) => '0',
s_axi_wdata(242) => '0',
s_axi_wdata(241) => '0',
s_axi_wdata(240) => '0',
s_axi_wdata(239) => '0',
s_axi_wdata(238) => '0',
s_axi_wdata(237) => '0',
s_axi_wdata(236) => '0',
s_axi_wdata(235) => '0',
s_axi_wdata(234) => '0',
s_axi_wdata(233) => '0',
s_axi_wdata(232) => '0',
s_axi_wdata(231) => '0',
s_axi_wdata(230) => '0',
s_axi_wdata(229) => '0',
s_axi_wdata(228) => '0',
s_axi_wdata(227) => '0',
s_axi_wdata(226) => '0',
s_axi_wdata(225) => '0',
s_axi_wdata(224) => '0',
s_axi_wdata(223) => '0',
s_axi_wdata(222) => '0',
s_axi_wdata(221) => '0',
s_axi_wdata(220) => '0',
s_axi_wdata(219) => '0',
s_axi_wdata(218) => '0',
s_axi_wdata(217) => '0',
s_axi_wdata(216) => '0',
s_axi_wdata(215) => '0',
s_axi_wdata(214) => '0',
s_axi_wdata(213) => '0',
s_axi_wdata(212) => '0',
s_axi_wdata(211) => '0',
s_axi_wdata(210) => '0',
s_axi_wdata(209) => '0',
s_axi_wdata(208) => '0',
s_axi_wdata(207) => '0',
s_axi_wdata(206) => '0',
s_axi_wdata(205) => '0',
s_axi_wdata(204) => '0',
s_axi_wdata(203) => '0',
s_axi_wdata(202) => '0',
s_axi_wdata(201) => '0',
s_axi_wdata(200) => '0',
s_axi_wdata(199) => '0',
s_axi_wdata(198) => '0',
s_axi_wdata(197) => '0',
s_axi_wdata(196) => '0',
s_axi_wdata(195) => '0',
s_axi_wdata(194) => '0',
s_axi_wdata(193) => '0',
s_axi_wdata(192) => '0',
s_axi_wdata(191) => '0',
s_axi_wdata(190) => '0',
s_axi_wdata(189) => '0',
s_axi_wdata(188) => '0',
s_axi_wdata(187) => '0',
s_axi_wdata(186) => '0',
s_axi_wdata(185) => '0',
s_axi_wdata(184) => '0',
s_axi_wdata(183) => '0',
s_axi_wdata(182) => '0',
s_axi_wdata(181) => '0',
s_axi_wdata(180) => '0',
s_axi_wdata(179) => '0',
s_axi_wdata(178) => '0',
s_axi_wdata(177) => '0',
s_axi_wdata(176) => '0',
s_axi_wdata(175) => '0',
s_axi_wdata(174) => '0',
s_axi_wdata(173) => '0',
s_axi_wdata(172) => '0',
s_axi_wdata(171) => '0',
s_axi_wdata(170) => '0',
s_axi_wdata(169) => '0',
s_axi_wdata(168) => '0',
s_axi_wdata(167) => '0',
s_axi_wdata(166) => '0',
s_axi_wdata(165) => '0',
s_axi_wdata(164) => '0',
s_axi_wdata(163) => '0',
s_axi_wdata(162) => '0',
s_axi_wdata(161) => '0',
s_axi_wdata(160) => '0',
s_axi_wdata(159) => '0',
s_axi_wdata(158) => '0',
s_axi_wdata(157) => '0',
s_axi_wdata(156) => '0',
s_axi_wdata(155) => '0',
s_axi_wdata(154) => '0',
s_axi_wdata(153) => '0',
s_axi_wdata(152) => '0',
s_axi_wdata(151) => '0',
s_axi_wdata(150) => '0',
s_axi_wdata(149) => '0',
s_axi_wdata(148) => '0',
s_axi_wdata(147) => '0',
s_axi_wdata(146) => '0',
s_axi_wdata(145) => '0',
s_axi_wdata(144) => '0',
s_axi_wdata(143) => '0',
s_axi_wdata(142) => '0',
s_axi_wdata(141) => '0',
s_axi_wdata(140) => '0',
s_axi_wdata(139) => '0',
s_axi_wdata(138) => '0',
s_axi_wdata(137) => '0',
s_axi_wdata(136) => '0',
s_axi_wdata(135) => '0',
s_axi_wdata(134) => '0',
s_axi_wdata(133) => '0',
s_axi_wdata(132) => '0',
s_axi_wdata(131) => '0',
s_axi_wdata(130) => '0',
s_axi_wdata(129) => '0',
s_axi_wdata(128) => '0',
s_axi_wdata(127) => '0',
s_axi_wdata(126) => '0',
s_axi_wdata(125) => '0',
s_axi_wdata(124) => '0',
s_axi_wdata(123) => '0',
s_axi_wdata(122) => '0',
s_axi_wdata(121) => '0',
s_axi_wdata(120) => '0',
s_axi_wdata(119) => '0',
s_axi_wdata(118) => '0',
s_axi_wdata(117) => '0',
s_axi_wdata(116) => '0',
s_axi_wdata(115) => '0',
s_axi_wdata(114) => '0',
s_axi_wdata(113) => '0',
s_axi_wdata(112) => '0',
s_axi_wdata(111) => '0',
s_axi_wdata(110) => '0',
s_axi_wdata(109) => '0',
s_axi_wdata(108) => '0',
s_axi_wdata(107) => '0',
s_axi_wdata(106) => '0',
s_axi_wdata(105) => '0',
s_axi_wdata(104) => '0',
s_axi_wdata(103) => '0',
s_axi_wdata(102) => '0',
s_axi_wdata(101) => '0',
s_axi_wdata(100) => '0',
s_axi_wdata(99) => '0',
s_axi_wdata(98) => '0',
s_axi_wdata(97) => '0',
s_axi_wdata(96) => '0',
s_axi_wdata(95) => '0',
s_axi_wdata(94) => '0',
s_axi_wdata(93) => '0',
s_axi_wdata(92) => '0',
s_axi_wdata(91) => '0',
s_axi_wdata(90) => '0',
s_axi_wdata(89) => '0',
s_axi_wdata(88) => '0',
s_axi_wdata(87) => '0',
s_axi_wdata(86) => '0',
s_axi_wdata(85) => '0',
s_axi_wdata(84) => '0',
s_axi_wdata(83) => '0',
s_axi_wdata(82) => '0',
s_axi_wdata(81) => '0',
s_axi_wdata(80) => '0',
s_axi_wdata(79) => '0',
s_axi_wdata(78) => '0',
s_axi_wdata(77) => '0',
s_axi_wdata(76) => '0',
s_axi_wdata(75) => '0',
s_axi_wdata(74) => '0',
s_axi_wdata(73) => '0',
s_axi_wdata(72) => '0',
s_axi_wdata(71) => '0',
s_axi_wdata(70) => '0',
s_axi_wdata(69) => '0',
s_axi_wdata(68) => '0',
s_axi_wdata(67) => '0',
s_axi_wdata(66) => '0',
s_axi_wdata(65) => '0',
s_axi_wdata(64) => '0',
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemScore/synth/MemScore.vhd
|
1
|
6786
|
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-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY MemScore IS
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END MemScore;
ARCHITECTURE MemScore_arch OF MemScore IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF MemScore_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF MemScore_arch: ARCHITECTURE IS "dist_mem_gen_v8_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF MemScore_arch : ARCHITECTURE IS "MemScore,dist_mem_gen_v8_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF MemScore_arch: ARCHITECTURE IS "MemScore,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_ADDR_WIDTH=8,C_DEFAULT_DATA=0,C_DEPTH=256,C_HAS_CLK=1,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=MemScore.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=1,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=12,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 8,
C_DEFAULT_DATA => "0",
C_DEPTH => 256,
C_HAS_CLK => 1,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "MemScore.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 1,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 12,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
clk => clk,
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END MemScore_arch;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/VHDL/BlockRamWinner.vhd
|
1
|
1649
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BlockRamWinner is
Port ( Clock : in STD_LOGIC;
Row : in STD_LOGIC_VECTOR (4 downto 0);
Column : in STD_LOGIC_VECTOR (6 downto 0);
DataOutPixel : out STD_LOGIC
);
end BlockRamWinner;
architecture Behavioral of BlockRamWinner is
component RowToAddr
Port (
Row : in STD_LOGIC_VECTOR (4 downto 0);
AddressOut : out STD_LOGIC_VECTOR (4 downto 0)
);
end component;
component MemWinner
PORT (
a : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
clk : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(107 DOWNTO 0)
);
end component;
component Reg7
Port (
Clock : in STD_LOGIC;
ColumnIn : in STD_LOGIC_VECTOR (6 downto 0);
ColumnOut : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
component ToPixelWinner
Port (
DataIn : in STD_LOGIC_VECTOR (107 downto 0);
Column : in STD_LOGIC_VECTOR (6 downto 0);
PixelOut : out STD_LOGIC
);
end component;
--------SIGNALS
signal AddressOut_signal : std_logic_vector(4 downto 0);
signal MemOut_signal : std_logic_vector(107 downto 0);
signal ColumnOut_signal : std_logic_vector(6 downto 0);
begin
--------PORT MAPS
RowToAddres:RowToAddr
port map(Row => Row,
AddressOut => AddressOut_signal);
CoreWinner:MemWinner
port map(a => AddressOut_signal,
clk => Clock,
spo => MemOut_signal);
Register7:Reg7
port map(Clock => Clock,
ColumnIn => Column,
ColumnOut => ColumnOut_signal);
ToPixel:ToPixelWinner
port map(DataIn => MemOut_signal,
Column => ColumnOut_signal,
PixelOut => DataOutPixel);
end Behavioral;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Pointer/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd
|
24
|
19921
|
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ZloTK9KTfsT7LhhY
`protect end_protected
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/imports/new/SevSeg_top.vhd
|
1
|
5875
|
---Top level module of the Sev Seg display part
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity SevSeg_top is
Port ( P1D1 : in STD_LOGIC_VECTOR (3 downto 0);
P1D2 : in STD_LOGIC_VECTOR (3 downto 0);
P2D1 : in STD_LOGIC_VECTOR (3 downto 0);
P2D2 : in STD_LOGIC_VECTOR (3 downto 0);
Clk : in STD_LOGIC;
Reset_button : in STD_LOGIC;
Change_button : in STD_LOGIC;--INITIANLIZE DONE
DataEn : out STD_LOGIC_VECTOR (7 downto 0);----COMMON ANODES
DataOut : out STD_LOGIC_VECTOR (7 downto 0));-----CATHODES
end SevSeg_top;
architecture Behavioral of SevSeg_top is
Component BCD2SSD is-------------------------------------------translates the input Score Digits into SSD compatible format
Port ( Data_In1 : in STD_LOGIC_VECTOR (3 downto 0);
Data_In2 : in STD_LOGIC_VECTOR (3 downto 0);
Player_in : in STD_LOGIC_VECTOR (15 downto 0);
SSDisplay : out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
Component SelectFSM is-----------------------------------------Selects what is to be displayed based on the game state( Hello message, or Score digits)
Port ( SSDisp_in : in STD_LOGIC_VECTOR (31 downto 0);
RstDisp_in : in STD_LOGIC_VECTOR (31 downto 0);
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Change : in STD_LOGIC;
Select_out : out STD_LOGIC_VECTOR (31 downto 0)
);
end Component;
Component DigitFSM is--------------------------------------counts a number of clock cycles for the refresh rate to not be noticable by the human eye
Port ( Clock : in STD_LOGIC;
Data_En : out STD_LOGIC_VECTOR (7 downto 0);
Digit_sel : out STD_LOGIC_VECTOR (2 downto 0));
end Component;
signal SSDisplay_sig1: STD_LOGIC_VECTOR (31 downto 0);
signal DataDisplay_sig1: STD_LOGIC_VECTOR (31 downto 0);
signal SSDisplay_sig2: STD_LOGIC_VECTOR (31 downto 0);
signal DataDisplay_sig2: STD_LOGIC_VECTOR (31 downto 0);
signal Player1_sig : STD_LOGIC_VECTOR (15 downto 0):="0011000111110010";--P1.
signal Player2_sig : STD_LOGIC_VECTOR (15 downto 0):="0011000100100100";--P2.
signal Digit_sel_sig : STD_LOGIC_VECTOR (2 downto 0);
SIGNAL counter : natural:=0;
signal Reset_display_sig1 : STD_LOGIC_VECTOR (31 downto 0):="11111111111111111111111110010001";--H --
signal Reset_display_sig2 : STD_LOGIC_VECTOR (31 downto 0):="01100001111000111110001100000011";--ELLO--"11111111111101010100100111100001";--rSt
begin
process(Digit_sel_sig,DataDisplay_sig1,DataDisplay_sig2) --Digit Mux
begin
if Digit_sel_sig="000" then--- Based on the digit that is to be displayed selects which part of the 32 bit signal shall be driven into the cathodes
DataOut<=DataDisplay_sig1(7 downto 0);
elsif Digit_sel_sig="001" then
DataOut<=DataDisplay_sig1(15 downto 8);
elsif Digit_sel_sig="010" then
DataOut<=DataDisplay_sig1(23 downto 16);
elsif Digit_sel_sig="011" then
DataOut<=DataDisplay_sig1(31 downto 24);
elsif Digit_sel_sig="100" then
DataOut<=DataDisplay_sig2(7 downto 0);
elsif Digit_sel_sig="101" then
DataOut<=DataDisplay_sig2(15 downto 8);
elsif Digit_sel_sig="110" then
DataOut<=DataDisplay_sig2(23 downto 16);
elsif Digit_sel_sig="111" then
DataOut<=DataDisplay_sig2(31 downto 24);
end if;
end process;
process ---------------------------------Rolling HELLO message during the Menu State of the game
begin
Wait until Clk'event and Clk='1';
if counter > 160000000 then
counter<=0;
else
if counter <=20000000 then
Reset_display_sig1<="11111111111111111111111110010001";
Reset_display_sig2<="01100001111000111110001100000011";
elsif counter <=40000000 then
Reset_display_sig1<="11111111111111111001000101100001";
Reset_display_sig2<="11100011111000110000001111111111";
elsif counter <=60000000 then
Reset_display_sig1<="11111111100100010110000111100011";
Reset_display_sig2<="11100011000000111111111111111111";
elsif counter <=80000000 then
Reset_display_sig1<="10010001011000011110001111100011";
Reset_display_sig2<="00000011111111111111111111111111";
elsif counter <=100000000 then
Reset_display_sig1<="01100001111000111110001100000011";
Reset_display_sig2<="11111111111111111111111110010001";
elsif counter <=120000000 then
Reset_display_sig1<="11100011111000110000001111111111";
Reset_display_sig2<="11111111111111111001000101100001";
elsif counter <=140000000 then
Reset_display_sig1<="11100011000000111111111111111111";
Reset_display_sig2<="11111111100100010110000111100011";
else
Reset_display_sig1<="00000011111111111111111111111111";
Reset_display_sig2<="10010001011000011110001111100011";
-- counter <=160000000
end if;
counter<=counter +1;
end if;
end process;
---------------------------------------------------SCORE 1
BCD2SSD_Port1: BCD2SSD port map(
Data_In1 =>P1D1,
Data_In2 =>P1D2,
Player_in=>Player1_sig,
SSDisplay =>SSDisplay_sig1
);
SelectFSM_Port1: SelectFSM port map(
SSDisp_in =>SSDisplay_sig1,
RstDisp_in =>Reset_display_sig1,
Clock =>Clk,
Reset =>Reset_button,
Change =>Change_button,
Select_out =>DataDisplay_sig1
);
--------------------------------------------------SCORE 2
BCD2SSD_Port2: BCD2SSD port map(
Data_In1 =>P2D1,
Data_In2 =>P2D2,
Player_in=> Player2_sig,
SSDisplay =>SSDisplay_sig2
);
SelectFSM_Port2: SelectFSM port map(
SSDisp_in =>SSDisplay_sig2,
RstDisp_in =>Reset_display_sig2,
Clock =>Clk,
Reset =>Reset_button,
Change =>Change_button,
Select_out =>DataDisplay_sig2
);
------------------------------------------------------------ DIGIT SELECTION
DigitFSM_Port: DigitFSM port map(
Clock => Clk,
Data_En =>DataEn,
Digit_sel => Digit_sel_sig
);
end Behavioral;
|
gpl-3.0
|
dbousias/RoachSweeper
|
Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Mem/Mem_funcsim.vhdl
|
1
|
30476
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:23:38 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Mem/Mem_funcsim.vhdl
-- Design : Mem
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_dpram__parameterized0\ is
port (
spo : out STD_LOGIC_VECTOR ( 4 downto 0 );
dpo : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ( 4 downto 0 );
a : in STD_LOGIC_VECTOR ( 8 downto 0 );
dpra : in STD_LOGIC_VECTOR ( 8 downto 0 );
we : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_dpram__parameterized0\ : entity is "dpram";
end \Mem_dpram__parameterized0\;
architecture STRUCTURE of \Mem_dpram__parameterized0\ is
signal \^dpo\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal n_0_ram_reg_0_127_0_0 : STD_LOGIC;
signal n_0_ram_reg_0_127_0_0_i_1 : STD_LOGIC;
signal n_0_ram_reg_0_127_1_1 : STD_LOGIC;
signal n_0_ram_reg_0_127_2_2 : STD_LOGIC;
signal n_0_ram_reg_0_127_3_3 : STD_LOGIC;
signal n_0_ram_reg_0_127_4_4 : STD_LOGIC;
signal n_0_ram_reg_128_255_0_0 : STD_LOGIC;
signal n_0_ram_reg_128_255_0_0_i_1 : STD_LOGIC;
signal n_0_ram_reg_128_255_1_1 : STD_LOGIC;
signal n_0_ram_reg_128_255_2_2 : STD_LOGIC;
signal n_0_ram_reg_128_255_3_3 : STD_LOGIC;
signal n_0_ram_reg_128_255_4_4 : STD_LOGIC;
signal n_0_ram_reg_256_383_0_0 : STD_LOGIC;
signal n_0_ram_reg_256_383_0_0_i_1 : STD_LOGIC;
signal n_0_ram_reg_256_383_1_1 : STD_LOGIC;
signal n_0_ram_reg_256_383_2_2 : STD_LOGIC;
signal n_0_ram_reg_256_383_3_3 : STD_LOGIC;
signal n_0_ram_reg_256_383_4_4 : STD_LOGIC;
signal n_0_ram_reg_384_511_0_0 : STD_LOGIC;
signal n_0_ram_reg_384_511_0_0_i_1 : STD_LOGIC;
signal n_0_ram_reg_384_511_1_1 : STD_LOGIC;
signal n_0_ram_reg_384_511_2_2 : STD_LOGIC;
signal n_0_ram_reg_384_511_3_3 : STD_LOGIC;
signal n_0_ram_reg_384_511_4_4 : STD_LOGIC;
signal n_1_ram_reg_0_127_0_0 : STD_LOGIC;
signal n_1_ram_reg_0_127_1_1 : STD_LOGIC;
signal n_1_ram_reg_0_127_2_2 : STD_LOGIC;
signal n_1_ram_reg_0_127_3_3 : STD_LOGIC;
signal n_1_ram_reg_0_127_4_4 : STD_LOGIC;
signal n_1_ram_reg_128_255_0_0 : STD_LOGIC;
signal n_1_ram_reg_128_255_1_1 : STD_LOGIC;
signal n_1_ram_reg_128_255_2_2 : STD_LOGIC;
signal n_1_ram_reg_128_255_3_3 : STD_LOGIC;
signal n_1_ram_reg_128_255_4_4 : STD_LOGIC;
signal n_1_ram_reg_256_383_0_0 : STD_LOGIC;
signal n_1_ram_reg_256_383_1_1 : STD_LOGIC;
signal n_1_ram_reg_256_383_2_2 : STD_LOGIC;
signal n_1_ram_reg_256_383_3_3 : STD_LOGIC;
signal n_1_ram_reg_256_383_4_4 : STD_LOGIC;
signal n_1_ram_reg_384_511_0_0 : STD_LOGIC;
signal n_1_ram_reg_384_511_1_1 : STD_LOGIC;
signal n_1_ram_reg_384_511_2_2 : STD_LOGIC;
signal n_1_ram_reg_384_511_3_3 : STD_LOGIC;
signal n_1_ram_reg_384_511_4_4 : STD_LOGIC;
signal qdpo_int : STD_LOGIC_VECTOR ( 4 downto 0 );
signal qspo_int : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^spo\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute KEEP : string;
attribute KEEP of \qdpo_int_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \qdpo_int_reg[0]\ : label is "no";
attribute KEEP of \qdpo_int_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \qdpo_int_reg[1]\ : label is "no";
attribute KEEP of \qdpo_int_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \qdpo_int_reg[2]\ : label is "no";
attribute KEEP of \qdpo_int_reg[3]\ : label is "yes";
attribute equivalent_register_removal of \qdpo_int_reg[3]\ : label is "no";
attribute KEEP of \qdpo_int_reg[4]\ : label is "yes";
attribute equivalent_register_removal of \qdpo_int_reg[4]\ : label is "no";
attribute KEEP of \qspo_int_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[0]\ : label is "no";
attribute KEEP of \qspo_int_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[1]\ : label is "no";
attribute KEEP of \qspo_int_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[2]\ : label is "no";
attribute KEEP of \qspo_int_reg[3]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[3]\ : label is "no";
attribute KEEP of \qspo_int_reg[4]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[4]\ : label is "no";
begin
dpo(4 downto 0) <= \^dpo\(4 downto 0);
spo(4 downto 0) <= \^spo\(4 downto 0);
\dpo[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_0_ram_reg_384_511_0_0,
I1 => n_0_ram_reg_256_383_0_0,
I2 => dpra(8),
I3 => n_0_ram_reg_128_255_0_0,
I4 => dpra(7),
I5 => n_0_ram_reg_0_127_0_0,
O => \^dpo\(0)
);
\dpo[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_0_ram_reg_384_511_1_1,
I1 => n_0_ram_reg_256_383_1_1,
I2 => dpra(8),
I3 => n_0_ram_reg_128_255_1_1,
I4 => dpra(7),
I5 => n_0_ram_reg_0_127_1_1,
O => \^dpo\(1)
);
\dpo[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_0_ram_reg_384_511_2_2,
I1 => n_0_ram_reg_256_383_2_2,
I2 => dpra(8),
I3 => n_0_ram_reg_128_255_2_2,
I4 => dpra(7),
I5 => n_0_ram_reg_0_127_2_2,
O => \^dpo\(2)
);
\dpo[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_0_ram_reg_384_511_3_3,
I1 => n_0_ram_reg_256_383_3_3,
I2 => dpra(8),
I3 => n_0_ram_reg_128_255_3_3,
I4 => dpra(7),
I5 => n_0_ram_reg_0_127_3_3,
O => \^dpo\(3)
);
\dpo[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_0_ram_reg_384_511_4_4,
I1 => n_0_ram_reg_256_383_4_4,
I2 => dpra(8),
I3 => n_0_ram_reg_128_255_4_4,
I4 => dpra(7),
I5 => n_0_ram_reg_0_127_4_4,
O => \^dpo\(4)
);
\qdpo_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^dpo\(0),
Q => qdpo_int(0),
R => '0'
);
\qdpo_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^dpo\(1),
Q => qdpo_int(1),
R => '0'
);
\qdpo_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^dpo\(2),
Q => qdpo_int(2),
R => '0'
);
\qdpo_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^dpo\(3),
Q => qdpo_int(3),
R => '0'
);
\qdpo_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^dpo\(4),
Q => qdpo_int(4),
R => '0'
);
\qspo_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(0),
Q => qspo_int(0),
R => '0'
);
\qspo_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(1),
Q => qspo_int(1),
R => '0'
);
\qspo_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(2),
Q => qspo_int(2),
R => '0'
);
\qspo_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(3),
Q => qspo_int(3),
R => '0'
);
\qspo_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(4),
Q => qspo_int(4),
R => '0'
);
ram_reg_0_127_0_0: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"000060000180000600001800007FFFFF"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(0),
DPO => n_0_ram_reg_0_127_0_0,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_0_127_0_0,
WCLK => clk,
WE => n_0_ram_reg_0_127_0_0_i_1
);
ram_reg_0_127_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(7),
I2 => a(8),
O => n_0_ram_reg_0_127_0_0_i_1
);
ram_reg_0_127_1_1: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"000060000180000600001800007FFFFF"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(1),
DPO => n_0_ram_reg_0_127_1_1,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_0_127_1_1,
WCLK => clk,
WE => n_0_ram_reg_0_127_0_0_i_1
);
ram_reg_0_127_2_2: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00000000000000000000000000000000"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(2),
DPO => n_0_ram_reg_0_127_2_2,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_0_127_2_2,
WCLK => clk,
WE => n_0_ram_reg_0_127_0_0_i_1
);
ram_reg_0_127_3_3: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"000060000180000600001800007FFFFF"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(3),
DPO => n_0_ram_reg_0_127_3_3,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_0_127_3_3,
WCLK => clk,
WE => n_0_ram_reg_0_127_0_0_i_1
);
ram_reg_0_127_4_4: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"000060000180000600001800007FFFFF"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(4),
DPO => n_0_ram_reg_0_127_4_4,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_0_127_4_4,
WCLK => clk,
WE => n_0_ram_reg_0_127_0_0_i_1
);
ram_reg_128_255_0_0: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00060000180000600001800006000018"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(0),
DPO => n_0_ram_reg_128_255_0_0,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_128_255_0_0,
WCLK => clk,
WE => n_0_ram_reg_128_255_0_0_i_1
);
ram_reg_128_255_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(7),
I2 => we,
O => n_0_ram_reg_128_255_0_0_i_1
);
ram_reg_128_255_1_1: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00060000180000600001800006000018"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(1),
DPO => n_0_ram_reg_128_255_1_1,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_128_255_1_1,
WCLK => clk,
WE => n_0_ram_reg_128_255_0_0_i_1
);
ram_reg_128_255_2_2: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00000000000000000000000000000000"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(2),
DPO => n_0_ram_reg_128_255_2_2,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_128_255_2_2,
WCLK => clk,
WE => n_0_ram_reg_128_255_0_0_i_1
);
ram_reg_128_255_3_3: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00060000180000600001800006000018"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(3),
DPO => n_0_ram_reg_128_255_3_3,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_128_255_3_3,
WCLK => clk,
WE => n_0_ram_reg_128_255_0_0_i_1
);
ram_reg_128_255_4_4: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00060000180000600001800006000018"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(4),
DPO => n_0_ram_reg_128_255_4_4,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_128_255_4_4,
WCLK => clk,
WE => n_0_ram_reg_128_255_0_0_i_1
);
ram_reg_256_383_0_0: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00600001800006000018000060000180"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(0),
DPO => n_0_ram_reg_256_383_0_0,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_256_383_0_0,
WCLK => clk,
WE => n_0_ram_reg_256_383_0_0_i_1
);
ram_reg_256_383_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(7),
I1 => a(8),
I2 => we,
O => n_0_ram_reg_256_383_0_0_i_1
);
ram_reg_256_383_1_1: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00600001800006000018000060000180"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(1),
DPO => n_0_ram_reg_256_383_1_1,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_256_383_1_1,
WCLK => clk,
WE => n_0_ram_reg_256_383_0_0_i_1
);
ram_reg_256_383_2_2: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00000000000000000000000000000000"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(2),
DPO => n_0_ram_reg_256_383_2_2,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_256_383_2_2,
WCLK => clk,
WE => n_0_ram_reg_256_383_0_0_i_1
);
ram_reg_256_383_3_3: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00600001800006000018000060000180"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(3),
DPO => n_0_ram_reg_256_383_3_3,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_256_383_3_3,
WCLK => clk,
WE => n_0_ram_reg_256_383_0_0_i_1
);
ram_reg_256_383_4_4: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00600001800006000018000060000180"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(4),
DPO => n_0_ram_reg_256_383_4_4,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_256_383_4_4,
WCLK => clk,
WE => n_0_ram_reg_256_383_0_0_i_1
);
ram_reg_384_511_0_0: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"0000000FFFFFE0000180000600001800"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(0),
DPO => n_0_ram_reg_384_511_0_0,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_384_511_0_0,
WCLK => clk,
WE => n_0_ram_reg_384_511_0_0_i_1
);
ram_reg_384_511_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(7),
I2 => a(8),
O => n_0_ram_reg_384_511_0_0_i_1
);
ram_reg_384_511_1_1: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"0000000FFFFFE0000180000600001800"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(1),
DPO => n_0_ram_reg_384_511_1_1,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_384_511_1_1,
WCLK => clk,
WE => n_0_ram_reg_384_511_0_0_i_1
);
ram_reg_384_511_2_2: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"00000000000000000000000000000000"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(2),
DPO => n_0_ram_reg_384_511_2_2,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_384_511_2_2,
WCLK => clk,
WE => n_0_ram_reg_384_511_0_0_i_1
);
ram_reg_384_511_3_3: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"0000000FFFFFE0000180000600001800"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(3),
DPO => n_0_ram_reg_384_511_3_3,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_384_511_3_3,
WCLK => clk,
WE => n_0_ram_reg_384_511_0_0_i_1
);
ram_reg_384_511_4_4: unisim.vcomponents.RAM128X1D
generic map(
INIT => X"0000000FFFFFE0000180000600001800"
)
port map (
A(6 downto 0) => a(6 downto 0),
D => d(4),
DPO => n_0_ram_reg_384_511_4_4,
DPRA(6 downto 0) => dpra(6 downto 0),
SPO => n_1_ram_reg_384_511_4_4,
WCLK => clk,
WE => n_0_ram_reg_384_511_0_0_i_1
);
\spo[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_1_ram_reg_384_511_0_0,
I1 => n_1_ram_reg_256_383_0_0,
I2 => a(8),
I3 => n_1_ram_reg_128_255_0_0,
I4 => a(7),
I5 => n_1_ram_reg_0_127_0_0,
O => \^spo\(0)
);
\spo[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_1_ram_reg_384_511_1_1,
I1 => n_1_ram_reg_256_383_1_1,
I2 => a(8),
I3 => n_1_ram_reg_128_255_1_1,
I4 => a(7),
I5 => n_1_ram_reg_0_127_1_1,
O => \^spo\(1)
);
\spo[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_1_ram_reg_384_511_2_2,
I1 => n_1_ram_reg_256_383_2_2,
I2 => a(8),
I3 => n_1_ram_reg_128_255_2_2,
I4 => a(7),
I5 => n_1_ram_reg_0_127_2_2,
O => \^spo\(2)
);
\spo[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_1_ram_reg_384_511_3_3,
I1 => n_1_ram_reg_256_383_3_3,
I2 => a(8),
I3 => n_1_ram_reg_128_255_3_3,
I4 => a(7),
I5 => n_1_ram_reg_0_127_3_3,
O => \^spo\(3)
);
\spo[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => n_1_ram_reg_384_511_4_4,
I1 => n_1_ram_reg_256_383_4_4,
I2 => a(8),
I3 => n_1_ram_reg_128_255_4_4,
I4 => a(7),
I5 => n_1_ram_reg_0_127_4_4,
O => \^spo\(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem_dist_mem_gen_v8_0_synth is
port (
spo : out STD_LOGIC_VECTOR ( 4 downto 0 );
dpo : out STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ( 4 downto 0 );
a : in STD_LOGIC_VECTOR ( 8 downto 0 );
dpra : in STD_LOGIC_VECTOR ( 8 downto 0 );
we : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Mem_dist_mem_gen_v8_0_synth : entity is "dist_mem_gen_v8_0_synth";
end Mem_dist_mem_gen_v8_0_synth;
architecture STRUCTURE of Mem_dist_mem_gen_v8_0_synth is
begin
\gen_dp_ram.dpram_inst\: entity work.\Mem_dpram__parameterized0\
port map (
a(8 downto 0) => a(8 downto 0),
clk => clk,
d(4 downto 0) => d(4 downto 0),
dpo(4 downto 0) => dpo(4 downto 0),
dpra(8 downto 0) => dpra(8 downto 0),
spo(4 downto 0) => spo(4 downto 0),
we => we
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \Mem_dist_mem_gen_v8_0__parameterized0\ is
port (
a : in STD_LOGIC_VECTOR ( 8 downto 0 );
d : in STD_LOGIC_VECTOR ( 4 downto 0 );
dpra : in STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
i_ce : in STD_LOGIC;
qspo_ce : in STD_LOGIC;
qdpo_ce : in STD_LOGIC;
qdpo_clk : in STD_LOGIC;
qspo_rst : in STD_LOGIC;
qdpo_rst : in STD_LOGIC;
qspo_srst : in STD_LOGIC;
qdpo_srst : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 4 downto 0 );
dpo : out STD_LOGIC_VECTOR ( 4 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 4 downto 0 );
qdpo : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is "dist_mem_gen_v8_0";
attribute C_FAMILY : string;
attribute C_FAMILY of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is "artix7";
attribute C_ADDR_WIDTH : integer;
attribute C_ADDR_WIDTH of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 9;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is "0";
attribute C_DEPTH : integer;
attribute C_DEPTH of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 512;
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_HAS_D : integer;
attribute C_HAS_D of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_HAS_I_CE : integer;
attribute C_HAS_I_CE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QSPO : integer;
attribute C_HAS_QSPO of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QSPO_CE : integer;
attribute C_HAS_QSPO_CE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QSPO_RST : integer;
attribute C_HAS_QSPO_RST of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_QSPO_SRST : integer;
attribute C_HAS_QSPO_SRST of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_HAS_SPO : integer;
attribute C_HAS_SPO of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_MEM_INIT_FILE : string;
attribute C_MEM_INIT_FILE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is "Mem.mif";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is "./";
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 2;
attribute C_PIPELINE_STAGES : integer;
attribute C_PIPELINE_STAGES of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_QUALIFY_WE : integer;
attribute C_QUALIFY_WE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_READ_MIF : integer;
attribute C_READ_MIF of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_REG_A_D_INPUTS : integer;
attribute C_REG_A_D_INPUTS of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 0;
attribute C_SYNC_ENABLE : integer;
attribute C_SYNC_ENABLE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
attribute C_WIDTH : integer;
attribute C_WIDTH of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 5;
attribute C_PARSER_TYPE : integer;
attribute C_PARSER_TYPE of \Mem_dist_mem_gen_v8_0__parameterized0\ : entity is 1;
end \Mem_dist_mem_gen_v8_0__parameterized0\;
architecture STRUCTURE of \Mem_dist_mem_gen_v8_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
qdpo(4) <= \<const0>\;
qdpo(3) <= \<const0>\;
qdpo(2) <= \<const0>\;
qdpo(1) <= \<const0>\;
qdpo(0) <= \<const0>\;
qspo(4) <= \<const0>\;
qspo(3) <= \<const0>\;
qspo(2) <= \<const0>\;
qspo(1) <= \<const0>\;
qspo(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\synth_options.dist_mem_inst\: entity work.Mem_dist_mem_gen_v8_0_synth
port map (
a(8 downto 0) => a(8 downto 0),
clk => clk,
d(4 downto 0) => d(4 downto 0),
dpo(4 downto 0) => dpo(4 downto 0),
dpra(8 downto 0) => dpra(8 downto 0),
spo(4 downto 0) => spo(4 downto 0),
we => we
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Mem is
port (
a : in STD_LOGIC_VECTOR ( 8 downto 0 );
d : in STD_LOGIC_VECTOR ( 4 downto 0 );
dpra : in STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 4 downto 0 );
dpo : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Mem : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Mem : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of Mem : entity is "dist_mem_gen_v8_0,Vivado 2014.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of Mem : entity is "Mem,dist_mem_gen_v8_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of Mem : entity is "Mem,dist_mem_gen_v8_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_ADDR_WIDTH=9,C_DEFAULT_DATA=0,C_DEPTH=512,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=1,C_HAS_DPRA=1,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=Mem.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=2,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=5,C_PARSER_TYPE=1}";
end Mem;
architecture STRUCTURE of Mem is
signal NLW_U0_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_qspo_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of U0 : label is 1;
attribute C_HAS_D : integer;
attribute C_HAS_D of U0 : label is 1;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute c_addr_width : integer;
attribute c_addr_width of U0 : label is 9;
attribute c_default_data : string;
attribute c_default_data of U0 : label is "0";
attribute c_depth : integer;
attribute c_depth of U0 : label is 512;
attribute c_elaboration_dir : string;
attribute c_elaboration_dir of U0 : label is "./";
attribute c_has_dpo : integer;
attribute c_has_dpo of U0 : label is 1;
attribute c_has_dpra : integer;
attribute c_has_dpra of U0 : label is 1;
attribute c_has_i_ce : integer;
attribute c_has_i_ce of U0 : label is 0;
attribute c_has_qdpo : integer;
attribute c_has_qdpo of U0 : label is 0;
attribute c_has_qdpo_ce : integer;
attribute c_has_qdpo_ce of U0 : label is 0;
attribute c_has_qdpo_clk : integer;
attribute c_has_qdpo_clk of U0 : label is 0;
attribute c_has_qdpo_rst : integer;
attribute c_has_qdpo_rst of U0 : label is 0;
attribute c_has_qdpo_srst : integer;
attribute c_has_qdpo_srst of U0 : label is 0;
attribute c_has_qspo : integer;
attribute c_has_qspo of U0 : label is 0;
attribute c_has_qspo_ce : integer;
attribute c_has_qspo_ce of U0 : label is 0;
attribute c_has_qspo_rst : integer;
attribute c_has_qspo_rst of U0 : label is 0;
attribute c_has_qspo_srst : integer;
attribute c_has_qspo_srst of U0 : label is 0;
attribute c_has_spo : integer;
attribute c_has_spo of U0 : label is 1;
attribute c_mem_init_file : string;
attribute c_mem_init_file of U0 : label is "Mem.mif";
attribute c_parser_type : integer;
attribute c_parser_type of U0 : label is 1;
attribute c_pipeline_stages : integer;
attribute c_pipeline_stages of U0 : label is 0;
attribute c_qce_joined : integer;
attribute c_qce_joined of U0 : label is 0;
attribute c_qualify_we : integer;
attribute c_qualify_we of U0 : label is 0;
attribute c_read_mif : integer;
attribute c_read_mif of U0 : label is 1;
attribute c_reg_a_d_inputs : integer;
attribute c_reg_a_d_inputs of U0 : label is 0;
attribute c_reg_dpra_input : integer;
attribute c_reg_dpra_input of U0 : label is 0;
attribute c_sync_enable : integer;
attribute c_sync_enable of U0 : label is 1;
attribute c_width : integer;
attribute c_width of U0 : label is 5;
begin
U0: entity work.\Mem_dist_mem_gen_v8_0__parameterized0\
port map (
a(8 downto 0) => a(8 downto 0),
clk => clk,
d(4 downto 0) => d(4 downto 0),
dpo(4 downto 0) => dpo(4 downto 0),
dpra(8 downto 0) => dpra(8 downto 0),
i_ce => '1',
qdpo(4 downto 0) => NLW_U0_qdpo_UNCONNECTED(4 downto 0),
qdpo_ce => '1',
qdpo_clk => '0',
qdpo_rst => '0',
qdpo_srst => '0',
qspo(4 downto 0) => NLW_U0_qspo_UNCONNECTED(4 downto 0),
qspo_ce => '1',
qspo_rst => '0',
qspo_srst => '0',
spo(4 downto 0) => spo(4 downto 0),
we => we
);
end STRUCTURE;
|
gpl-3.0
|
iti-luebeck/Desert
|
RTeasy/src/vhdltmpl/tristate_comp.vhd
|
3
|
266
|
COMPONENT tristate
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : tristate USE ENTITY WORK.tristate(primitive);
|
gpl-3.0
|
iti-luebeck/Desert
|
RTeasy/src/vhdltmpl/sram_array_comp.vhd
|
2
|
405
|
COMPONENT sram_array
GENERIC(addr_width, data_width : positive);
PORT(
CS, WE : IN std_logic;
SELECT_ALL : IN std_logic;
ADDR : IN std_logic_vector(addr_width-1 DOWNTO 0);
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
DATA_OUT : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : sram_array USE ENTITY WORK.sram_array(primitive);
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_wrapper_65.vhd
|
3
|
6377
|
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component SHKA65_4096X32X1CM4
port(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11 : in std_logic;
DO0,DO1,DO2,
DO3,DO4,DO5,DO6,DO7,DO8,DO9,DO10,DO11,DO12,
DO13,DO14,DO15,DO16,DO17,DO18,DO19,DO20,
DO21,DO22,DO23,DO24,DO25,DO26,DO27,DO28,
DO29,DO30,DO31 : out std_logic;
DI0,DI1,DI2,DI3,DI4,DI5,
DI6,DI7,DI8,DI9,DI10,DI11,DI12,DI13,DI14,
DI15,DI16,DI17,DI18,DI19,DI20,DI21,DI22,
DI23,DI24,DI25,DI26,DI27,DI28,DI29,DI30,
DI31,CK,WEB,DVSE,DVS0,DVS1,DVS2,CSB: in std_logic);
end component;
signal write_enable: std_logic;
signal not_clock: std_logic;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
begin
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
IJTAG_data_read <= (others =>'0');
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
data_read <= (others =>'0');
end case;
end process;
RAM_unit: SHKA65_4096X32X1CM4
generic map (cdeFileInit => stim_file)
port map(
A0 => Mem_address(2),
A1 => Mem_address(3),
A2 => Mem_address(4),
A3 => Mem_address(5),
A4 => Mem_address(6),
A5 => Mem_address(7),
A6 => Mem_address(8),
A7 => Mem_address(9),
A8 => Mem_address(10),
A9 => Mem_address(11),
A10 => Mem_address(12),
A11 => Mem_address(13),
DO0 => Mem_data_read(0),
DO1 => Mem_data_read(1),
DO2 => Mem_data_read(2),
DO3 => Mem_data_read(3),
DO4 => Mem_data_read(4),
DO5 => Mem_data_read(5),
DO6 => Mem_data_read(6),
DO7 => Mem_data_read(7),
DO8 => Mem_data_read(8),
DO9 => Mem_data_read(9),
DO10 => Mem_data_read(10),
DO11 => Mem_data_read(11),
DO12 => Mem_data_read(12),
DO13 => Mem_data_read(13),
DO14 => Mem_data_read(14),
DO15 => Mem_data_read(15),
DO16 => Mem_data_read(16),
DO17 => Mem_data_read(17),
DO18 => Mem_data_read(18),
DO19 => Mem_data_read(19),
DO20 => Mem_data_read(20),
DO21 => Mem_data_read(21),
DO22 => Mem_data_read(22),
DO23 => Mem_data_read(23),
DO24 => Mem_data_read(24),
DO25 => Mem_data_read(25),
DO26 => Mem_data_read(26),
DO27 => Mem_data_read(27),
DO28 => Mem_data_read(28),
DO29 => Mem_data_read(29),
DO30 => Mem_data_read(30),
DO31 => Mem_data_read(31),
DI0 => Mem_data_write(0),
DI1 => Mem_data_write(1),
DI2 => Mem_data_write(2),
DI3 => Mem_data_write(3),
DI4 => Mem_data_write(4),
DI5 => Mem_data_write(5),
DI6 => Mem_data_write(6),
DI7 => Mem_data_write(7),
DI8 => Mem_data_write(8),
DI9 => Mem_data_write(9),
DI10 => Mem_data_write(10),
DI11 => Mem_data_write(11),
DI12 => Mem_data_write(12),
DI13 => Mem_data_write(13),
DI14 => Mem_data_write(14),
DI15 => Mem_data_write(15),
DI16 => Mem_data_write(16),
DI17 => Mem_data_write(17),
DI18 => Mem_data_write(18),
DI19 => Mem_data_write(19),
DI20 => Mem_data_write(20),
DI21 => Mem_data_write(21),
DI22 => Mem_data_write(22),
DI23 => Mem_data_write(23),
DI24 => Mem_data_write(24),
DI25 => Mem_data_write(25),
DI26 => Mem_data_write(26),
DI27 => Mem_data_write(27),
DI28 => Mem_data_write(28),
DI29 => Mem_data_write(29),
DI30 => Mem_data_write(30),
DI31 => Mem_data_write(31),
CK => Mem_clk,
WEB => write_enable,
DVSE => '0',
DVS0 => '0',
DVS1 => '0',
DVS2 => '0',
CSB => '0'
);
end; --architecture logic
|
gpl-3.0
|
sea212/vhdl_wishbone_intercon_generator
|
vhdl/the_intercon.vhdl
|
1
|
4024
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2016-03-25 13:21:34.929354
-- Design Name: Wishbone intercon
-- Module Name: the_intercon
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Generated by wishbone intercon generator
-- https://github.com/sea212/vhdl_wishbone_intercon_generator
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity intercon is
Port ( -- General intercon signals
clk_i : in std_logic;
rst_i : in std_logic;
-- Wishbone Master
btn_ctrl_dat_i : out std_logic_vector(7 downto 0) := (others => '0');
btn_ctrl_dat_o : in std_logic_vector(7 downto 0);
btn_ctrl_adr_o : in std_logic_vector(7 downto 0);
btn_ctrl_ack_i : out std_logic := '0';
btn_ctrl_cyc_o : in std_logic;
btn_ctrl_sel_o : in std_logic_vector(0 downto 0);
btn_ctrl_stb_o : in std_logic;
btn_ctrl_we_o : in std_logic;
-- Wishbone Slaves
led_ctrl_dat_i : out std_logic_vector(7 downto 0) := (others => '0');
led_ctrl_dat_o : in std_logic_vector(7 downto 0);
led_ctrl_adr_i : out std_logic_vector(7 downto 0) := (others => '0');
led_ctrl_ack_o : in std_logic;
led_ctrl_cyc_i : out std_logic := '0';
led_ctrl_sel_i : out std_logic_vector(0 downto 0) := (others => '0');
led_ctrl_stb_i : out std_logic := '0';
led_ctrl_we_i : out std_logic := '0'
);
end intercon;
architecture Behavioral of intercon is
-- define required signals
signal adr : std_logic_vector(7 downto 0) := (others => '0');
signal datm2s, dats2m : std_logic_vector(7 downto 0) := (others => '0');
signal sel : std_logic_vector(0 downto 0) := (others => '0');
-- define required 1-bit signals
signal we, stb, ack, cyc : std_logic := '0';
-- define additional signals (err,rty,tga,tgc,tgd)
begin
datm2s <= btn_ctrl_dat_o;
adr <= btn_ctrl_adr_o;
sel <= btn_ctrl_sel_o;
we <= btn_ctrl_we_o;
btn_ctrl_dat_i <= dats2m;
btn_ctrl_ack_i <= ack;
-- interconnect
interconnect : process (rst_i, adr, btn_ctrl_cyc_o)
begin
--if (rising_edge(clk_i)) then
if (rst_i = '1') then
--synchronous reset
stb <= '0';
cyc <= '0';
else
stb <= btn_ctrl_stb_o;
cyc <= btn_ctrl_cyc_o;
if (btn_ctrl_cyc_o = '1') then
-- address decoder (slave select) = ifs
-- interconnection = inside ifs
-- Baseaddress: 0x0, size: 0x100000
if (to_integer(unsigned(adr)) <= 1048576) then
led_ctrl_dat_i <= datm2s;
dats2m <= led_ctrl_dat_o;
led_ctrl_sel_i <= sel;
ack <= led_ctrl_ack_o;
led_ctrl_adr_i <= adr(7 downto 0);
led_ctrl_cyc_i <= cyc;
led_ctrl_stb_i <= stb;
led_ctrl_we_i <= we;
else
-- prevent latches on invalid slave selection
led_ctrl_dat_i <= (others => '0');
led_ctrl_sel_i <= (others => '0');
led_ctrl_adr_i <= (others => '0');
led_ctrl_cyc_i <= '0';
led_ctrl_stb_i <= '0';
led_ctrl_we_i <= '0';
dats2m <= (others => '0');
ack <= '0';
end if;
else
-- prevent latches on invalid cycles
led_ctrl_dat_i <= (others => '0');
led_ctrl_sel_i <= (others => '0');
led_ctrl_adr_i <= (others => '0');
led_ctrl_cyc_i <= '0';
led_ctrl_stb_i <= '0';
led_ctrl_we_i <= '0';
dats2m <= (others => '0');
ack <= '0';
end if;
end if;
--else
--null;
--end if;
end process interconnect;
end Behavioral;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/NI_Test/xbar.vhd
|
20
|
1004
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity XBAR is
generic (
DATA_WIDTH: integer := 8
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end;
architecture behavior of XBAR is
begin
process(sel, North_in, East_in, West_in, South_in, Local_in) begin
case(sel) is
when "00001" =>
Data_out <= Local_in;
when "00010" =>
Data_out <= South_in;
when "00100" =>
Data_out <= West_in;
when "01000" =>
Data_out <= East_in;
when others =>
Data_out <= North_in;
end case;
end process;
end;
|
gpl-3.0
|
camacazio/de0_nano_DAC
|
DE0_12bitDAC_controller/comm_pll.vhd
|
1
|
16301
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: comm_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY comm_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END comm_pll;
ARCHITECTURE SYN OF comm_pll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=comm_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire1,
clk => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "5.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "comm_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL comm_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/NI.vhd
|
3
|
22746
|
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(7 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end; --entity NI
architecture logic of NI is
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(7 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(11 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_TAIL);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
signal fault_info, fault_info_in: std_logic_vector(12 downto 0);
signal sent_info, fault_info_ready, fault_info_ready_in: std_logic;
signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0);
signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic;
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= "000000000000";
state <= IDLE;
packet_counter_out <= "00000000";
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
fault_info <= (others => '0');
fault_info_ready <= '0';
self_diagnosis_reg_out <= (others => '0');
self_diagnosis_flag <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
fault_info <= fault_info_in;
fault_info_ready <= fault_info_ready_in;
self_diagnosis_reg_out <= self_diagnosis_reg_in;
self_diagnosis_flag <= self_diagnosis_flag_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
process(enable, address, write_byte_enable) begin
Reconfig_command <= '0';
Rxy_reconf_PE <= (others =>'0');
Cx_reconf_PE <= (others =>'0');
if address = reconfiguration_address and enable = '1' then
if write_byte_enable /= "0000" then
Rxy_reconf_PE <= data_write(7 downto 0);
Cx_reconf_PE <= data_write(4 downto 8);
Reconfig_command <= '1';
end if;
end if;
end process;
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1'then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
process(P2N_FIFO_read_pointer, grant)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
-- flag setting and clearing for self diagnosis
process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin
if (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address = current_address then
self_diagnosis_flag_in <= '1';
elsif old_address = self_diagnosis_address then
self_diagnosis_flag_in <= '0';
else
self_diagnosis_flag_in <= self_diagnosis_flag;
end if;
end process;
-- handling fault information!
process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin
self_diagnosis_reg_in <= self_diagnosis_reg_out;
if (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address /= current_address then
fault_info_in <= turn_faults & link_faults;
fault_info_ready_in <= '1';
elsif (link_faults /= "00000" or turn_faults /= "00000000") and SHMU_address = current_address then
self_diagnosis_reg_in <= "0000000000000000000" & turn_faults & link_faults;
else
fault_info_in <= fault_info;
fault_info_ready_in <= fault_info_ready;
end if;
if sent_info = '1' then
fault_info_ready_in <= '0';
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready)
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
sent_info <= '0';
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if fault_info_ready = '1' then
state_in <= DIAGNOSIS_HEADER;
elsif P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" &
FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= BODY_FLIT;
packet_length_counter_in <= ("0000" & FIFO_Data_out(23 downto 16))-1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - "000000000001";
if packet_length_counter_out = "000000000010" then
state_in <= TAIL_FLIT;
else
state_in <= BODY_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
-- SHMU stuff ----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
when DIAGNOSIS_HEADER =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= DIAGNOSIS_BODY;
else
state_in <= DIAGNOSIS_HEADER;
end if;
when DIAGNOSIS_BODY =>
if credit_counter_out /= "00" then
grant <= '1';
--FD (Fault Diagnosis) : 01000110 01000100
-- fault info is 13 bits
TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0));
state_in <= DIAGNOSIS_TAIL;
else
state_in <= DIAGNOSIS_BODY;
end if;
when DIAGNOSIS_TAIL =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "100" & fault_info(12) & "000000000000000000000000000" & XOR_REDUCE("100" & fault_info(12) & "000000000000000000000000000");
state_in <= IDLE;
sent_info <= '1';
packet_counter_in <= packet_counter_out +1;
else
state_in <= DIAGNOSIS_TAIL;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
elsif old_address = self_diagnosis_address then
data_read <= self_diagnosis_reg_out;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag& "00000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/SIB_mux_pre_FCX_SELgate.vhd
|
3
|
4908
|
--Copyright (C) 2017 Konstantin Shibin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX_SELgate;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX_SELgate is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= SEL and SR_do(3) and CE;
toSE <= SEL and SR_do(3) and SE;
toUE <= SEL and SR_do(3) and UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
Test/credit_based/TB_Package_32_bit_credit_based_NI.vhd
|
3
|
16691
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function CX_GEN(current_address, network_size : integer) return integer;
procedure NI_control(network_size, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
signal self_diagnosis_address : in std_logic_vector(29 downto 0);
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0));
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function CX_GEN(current_address, network_size : integer) return integer is
variable X, Y : integer := 0;
variable CN, CE, CW, CS : std_logic := '0';
variable CX : std_logic_vector(3 downto 0);
begin
X := current_address mod network_size;
Y := current_address / network_size;
if X /= 0 then
CW := '1';
end if;
if X /= network_size-1 then
CE := '1';
end if;
if Y /= 0 then
CN := '1';
end if;
if Y /= network_size-1 then
CS := '1';
end if;
CX := CS&CW&CE&CN;
return to_integer(unsigned(CX));
end CX_GEN;
procedure NI_control(network_size, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
signal self_diagnosis_address : in std_logic_vector(29 downto 0);
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0)) is
-- variables for random functions
constant DATA_WIDTH : integer := 32;
variable seed1 :positive := current_address+1;
variable seed2 :positive := current_address+1;
variable rand : real ;
--file handling variables
variable SEND_LINEVARIABLE : line;
file SEND_FILE : text;
variable RECEIVED_LINEVARIABLE : line;
file RECEIVED_FILE : text;
variable DIAGNOSIS_LINEVARIABLE : line;
file DIAGNOSIS_FILE : text;
-- receiving variables
variable receive_source_node, receive_destination_node, receive_packet_id, receive_counter, receive_packet_length: integer;
variable diagnosis_source_node, diagnosis_destination_node, diagnosis_packet_id, diagnosis_counter, diagnosis_packet_length: integer;
-- sending variables
variable send_destination_node, send_counter, send_id_counter: integer:= 0;
variable send_packet_length: integer:= 8;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit);
variable state : state_type;
variable frame_starting_delay : integer:= 0;
variable frame_counter: integer:= 0;
variable diagnosis : std_logic := '0';
variable diagnosis_data: std_logic_vector(24 downto 0);
variable first_packet : boolean := True;
begin
file_open(DIAGNOSIS_FILE,"diagnosis.txt",WRITE_MODE);
file_open(RECEIVED_FILE,"received.txt",WRITE_MODE);
file_open(SEND_FILE,"sent.txt",WRITE_MODE);
enable <= '1';
state := Idle;
send_packet_length := min_packet_size;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size-1)))/100);
wait until clk'event and clk ='0';
address <= reconfiguration_address;
wait until clk'event and clk ='0';
write_byte_enable <= "1111";
data_write <= "00000000000000000000" & std_logic_vector(to_unsigned(CX_GEN(current_address, network_size), 4)) & std_logic_vector(to_unsigned(60, 8));
wait until clk'event and clk ='0';
write_byte_enable <= "0000";
data_write <= (others =>'0');
while true loop
-- read the flag status
address <= flag_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
--flag register is organized like this:
-- .-------------------------------------------------.
-- | N2P_empty | P2N_full | self_diagnosis_flag | ...|
-- '-------------------------------------------------'
if data_read(29) = '1' then -- self diagnosis data is ready!
-- read the received self diagnosis data status
address <= self_diagnosis_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
test <= data_read;
write(DIAGNOSIS_LINEVARIABLE, string'("Self diagnosis of SHMU Node:"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
if data_read(0) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("Local input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(1) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("South input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(2) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("West input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(3) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("East input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(4) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("North input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
write(DIAGNOSIS_LINEVARIABLE, string'("--------------------------------"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
wait until clk'event and clk ='0';
elsif data_read(31) = '0' then -- N2P is not empty, can receive flit
-- read the received data status
address <= counter_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
-- read the received data status
address <= reserved_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node := to_integer(unsigned(data_read(14 downto 1)));
receive_source_node := to_integer(unsigned(data_read(28 downto 15)));
receive_counter := 1;
diagnosis := '0';
diagnosis_data := (others => '0');
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter = 1 then
receive_packet_length := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter := receive_counter+1;
if data_read(28 downto 13) = "0100011001000100" then
diagnosis := '1';
diagnosis_data(11 downto 0) := data_read(12 downto 1);
end if;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter := receive_counter+1;
if diagnosis = '0' then
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
else
diagnosis_data(24 downto 12) := data_read(28 downto 16);
write(DIAGNOSIS_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id) & " diagnosis: " );
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
write(DIAGNOSIS_LINEVARIABLE, to_bitvector(diagnosis_data));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
if diagnosis_data(0) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("Local input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(1) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("South input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(2) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("West input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(3) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("East input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(4) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("North input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
write(DIAGNOSIS_LINEVARIABLE, string'("--------------------------------"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
end if;
elsif data_read(30) = '0' then -- P2N is not full, can send flit
if frame_counter >= frame_starting_delay then
if state = Idle and now < finish_time then
if frame_counter < frame_starting_delay+1 then
state := Header_flit;
send_counter := send_counter+1;
-- generating the destination address
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_size**2)-1));
while (send_destination_node = current_address) loop
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_size**2)-1));
end loop;
--generating the packet length
uniform(seed1, seed2, rand);
send_packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (send_packet_length < min_packet_size) then
send_packet_length:=min_packet_size;
end if;
if (send_packet_length > max_packet_size) then
send_packet_length:=max_packet_size;
end if;
-- this is the header flit
address <= reserved_address;
write_byte_enable <= "1111";
data_write <= "0000" & std_logic_vector(to_unsigned(0, 14)) & std_logic_vector(to_unsigned(send_destination_node, 14));
write(SEND_LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(current_address) & " to " & integer'image(send_destination_node) & " with length: "& integer'image(send_packet_length) & " id: " & integer'image(send_id_counter));
writeline(SEND_FILE, SEND_LINEVARIABLE);
else
state := Idle;
end if;
elsif state = Header_flit then
-- first body flit
address <= reserved_address;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
else
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
end if;
send_counter := send_counter+1;
state := Body_flit;
elsif state = Body_flit then
-- rest of body flits
address <= reserved_address;
write_byte_enable <= "1111";
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
send_counter := send_counter+1;
if send_counter = send_packet_length-1 then
state := Tail_flit;
else
state := Body_flit;
end if;
elsif state = Tail_flit then
-- tail flit
address <= reserved_address;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & "0000000000000000000000000000";
first_packet := False;
else
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
end if;
send_counter := 0;
state := Idle;
send_id_counter := send_id_counter + 1;
if send_id_counter = 16384 then
send_id_counter := 0;
end if;
end if;
end if;
frame_counter := frame_counter + 1;
if frame_counter = frame_length then
frame_counter := 0;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size)))/100);
end if;
wait until clk'event and clk ='0';
end if;
end loop;
file_close(SEND_FILE);
file_close(RECEIVED_FILE);
file_close(DIAGNOSIS_FILE);
end NI_control;
end TB_Package;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/REG.vhd
|
3
|
597
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY REG IS
PORT(
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
I : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END REG;
ARCHITECTURE main OF REG IS
BEGIN
PROCESS(CLK, CLR)
VARIABLE DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
IF(CLR = '1') THEN
DATA := x"0000";
O <= x"0000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(LOAD = '1') THEN
DATA := I;
END IF;
END IF;
O <= DATA;
END PROCESS;
END main;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/allocator_with_checkers.vhd
|
6
|
128714
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic;
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N,
N_err_IDLE_grant_N,
N_err_North_Req_N,
N_err_North_grant_N,
N_err_East_Req_E,
N_err_East_grant_E,
N_err_West_Req_W,
N_err_West_grant_W,
N_err_South_Req_S,
N_err_South_grant_S,
N_err_Local_Req_L,
N_err_Local_grant_L,
N_err_IDLE_Req_E,
N_err_IDLE_grant_E,
N_err_North_Req_E,
N_err_North_grant_E,
N_err_East_Req_W,
N_err_East_grant_W,
N_err_West_Req_S,
N_err_West_grant_S,
N_err_South_Req_L,
N_err_South_grant_L,
N_err_Local_Req_N,
N_err_Local_grant_N,
N_err_IDLE_Req_W,
N_err_IDLE_grant_W,
N_err_North_Req_W,
N_err_North_grant_W,
N_err_East_Req_S,
N_err_East_grant_S,
N_err_West_Req_L,
N_err_West_grant_L,
N_err_South_Req_N,
N_err_South_grant_N,
N_err_Local_Req_E,
N_err_Local_grant_E,
N_err_IDLE_Req_S,
N_err_IDLE_grant_S,
N_err_North_Req_S,
N_err_North_grant_S,
N_err_East_Req_L,
N_err_East_grant_L,
N_err_West_Req_N,
N_err_West_grant_N,
N_err_South_Req_E,
N_err_South_grant_E,
N_err_Local_Req_W,
N_err_Local_grant_W,
N_err_IDLE_Req_L,
N_err_IDLE_grant_L,
N_err_North_Req_L,
N_err_North_grant_L,
N_err_East_Req_N,
N_err_East_grant_N,
N_err_West_Req_E,
N_err_West_grant_E,
N_err_South_Req_W,
N_err_South_grant_W,
N_err_Local_Req_S,
N_err_Local_grant_S,
N_err_state_in_onehot,
N_err_no_request_grants,
N_err_request_no_grants,
N_err_no_Req_N_grant_N,
N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W,
N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N,
E_err_IDLE_grant_N,
E_err_North_Req_N,
E_err_North_grant_N,
E_err_East_Req_E,
E_err_East_grant_E,
E_err_West_Req_W,
E_err_West_grant_W,
E_err_South_Req_S,
E_err_South_grant_S,
E_err_Local_Req_L,
E_err_Local_grant_L,
E_err_IDLE_Req_E,
E_err_IDLE_grant_E,
E_err_North_Req_E,
E_err_North_grant_E,
E_err_East_Req_W,
E_err_East_grant_W,
E_err_West_Req_S,
E_err_West_grant_S,
E_err_South_Req_L,
E_err_South_grant_L,
E_err_Local_Req_N,
E_err_Local_grant_N,
E_err_IDLE_Req_W,
E_err_IDLE_grant_W,
E_err_North_Req_W,
E_err_North_grant_W,
E_err_East_Req_S,
E_err_East_grant_S,
E_err_West_Req_L,
E_err_West_grant_L,
E_err_South_Req_N,
E_err_South_grant_N,
E_err_Local_Req_E,
E_err_Local_grant_E,
E_err_IDLE_Req_S,
E_err_IDLE_grant_S,
E_err_North_Req_S,
E_err_North_grant_S,
E_err_East_Req_L,
E_err_East_grant_L,
E_err_West_Req_N,
E_err_West_grant_N,
E_err_South_Req_E,
E_err_South_grant_E,
E_err_Local_Req_W,
E_err_Local_grant_W,
E_err_IDLE_Req_L,
E_err_IDLE_grant_L,
E_err_North_Req_L,
E_err_North_grant_L,
E_err_East_Req_N,
E_err_East_grant_N,
E_err_West_Req_E,
E_err_West_grant_E,
E_err_South_Req_W,
E_err_South_grant_W,
E_err_Local_Req_S,
E_err_Local_grant_S,
E_err_state_in_onehot,
E_err_no_request_grants,
E_err_request_no_grants,
E_err_no_Req_N_grant_N,
E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W,
E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N,
W_err_IDLE_grant_N,
W_err_North_Req_N,
W_err_North_grant_N,
W_err_East_Req_E,
W_err_East_grant_E,
W_err_West_Req_W,
W_err_West_grant_W,
W_err_South_Req_S,
W_err_South_grant_S,
W_err_Local_Req_L,
W_err_Local_grant_L,
W_err_IDLE_Req_E,
W_err_IDLE_grant_E,
W_err_North_Req_E,
W_err_North_grant_E,
W_err_East_Req_W,
W_err_East_grant_W,
W_err_West_Req_S,
W_err_West_grant_S,
W_err_South_Req_L,
W_err_South_grant_L,
W_err_Local_Req_N,
W_err_Local_grant_N,
W_err_IDLE_Req_W,
W_err_IDLE_grant_W,
W_err_North_Req_W,
W_err_North_grant_W,
W_err_East_Req_S,
W_err_East_grant_S,
W_err_West_Req_L,
W_err_West_grant_L,
W_err_South_Req_N,
W_err_South_grant_N,
W_err_Local_Req_E,
W_err_Local_grant_E,
W_err_IDLE_Req_S,
W_err_IDLE_grant_S,
W_err_North_Req_S,
W_err_North_grant_S,
W_err_East_Req_L,
W_err_East_grant_L,
W_err_West_Req_N,
W_err_West_grant_N,
W_err_South_Req_E,
W_err_South_grant_E,
W_err_Local_Req_W,
W_err_Local_grant_W,
W_err_IDLE_Req_L,
W_err_IDLE_grant_L,
W_err_North_Req_L,
W_err_North_grant_L,
W_err_East_Req_N,
W_err_East_grant_N,
W_err_West_Req_E,
W_err_West_grant_E,
W_err_South_Req_W,
W_err_South_grant_W,
W_err_Local_Req_S,
W_err_Local_grant_S,
W_err_state_in_onehot,
W_err_no_request_grants,
W_err_request_no_grants,
W_err_no_Req_N_grant_N,
W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W,
W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N,
S_err_IDLE_grant_N,
S_err_North_Req_N,
S_err_North_grant_N,
S_err_East_Req_E,
S_err_East_grant_E,
S_err_West_Req_W,
S_err_West_grant_W,
S_err_South_Req_S,
S_err_South_grant_S,
S_err_Local_Req_L,
S_err_Local_grant_L,
S_err_IDLE_Req_E,
S_err_IDLE_grant_E,
S_err_North_Req_E,
S_err_North_grant_E,
S_err_East_Req_W,
S_err_East_grant_W,
S_err_West_Req_S,
S_err_West_grant_S,
S_err_South_Req_L,
S_err_South_grant_L,
S_err_Local_Req_N,
S_err_Local_grant_N,
S_err_IDLE_Req_W,
S_err_IDLE_grant_W,
S_err_North_Req_W,
S_err_North_grant_W,
S_err_East_Req_S,
S_err_East_grant_S,
S_err_West_Req_L,
S_err_West_grant_L,
S_err_South_Req_N,
S_err_South_grant_N,
S_err_Local_Req_E,
S_err_Local_grant_E,
S_err_IDLE_Req_S,
S_err_IDLE_grant_S,
S_err_North_Req_S,
S_err_North_grant_S,
S_err_East_Req_L,
S_err_East_grant_L,
S_err_West_Req_N,
S_err_West_grant_N,
S_err_South_Req_E,
S_err_South_grant_E,
S_err_Local_Req_W,
S_err_Local_grant_W,
S_err_IDLE_Req_L,
S_err_IDLE_grant_L,
S_err_North_Req_L,
S_err_North_grant_L,
S_err_East_Req_N,
S_err_East_grant_N,
S_err_West_Req_E,
S_err_West_grant_E,
S_err_South_Req_W,
S_err_South_grant_W,
S_err_Local_Req_S,
S_err_Local_grant_S,
S_err_state_in_onehot,
S_err_no_request_grants,
S_err_request_no_grants,
S_err_no_Req_N_grant_N,
S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W,
S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N,
L_err_IDLE_grant_N,
L_err_North_Req_N,
L_err_North_grant_N,
L_err_East_Req_E,
L_err_East_grant_E,
L_err_West_Req_W,
L_err_West_grant_W,
L_err_South_Req_S,
L_err_South_grant_S,
L_err_Local_Req_L,
L_err_Local_grant_L,
L_err_IDLE_Req_E,
L_err_IDLE_grant_E,
L_err_North_Req_E,
L_err_North_grant_E,
L_err_East_Req_W,
L_err_East_grant_W,
L_err_West_Req_S,
L_err_West_grant_S,
L_err_South_Req_L,
L_err_South_grant_L,
L_err_Local_Req_N,
L_err_Local_grant_N,
L_err_IDLE_Req_W,
L_err_IDLE_grant_W,
L_err_North_Req_W,
L_err_North_grant_W,
L_err_East_Req_S,
L_err_East_grant_S,
L_err_West_Req_L,
L_err_West_grant_L,
L_err_South_Req_N,
L_err_South_grant_N,
L_err_Local_Req_E,
L_err_Local_grant_E,
L_err_IDLE_Req_S,
L_err_IDLE_grant_S,
L_err_North_Req_S,
L_err_North_grant_S,
L_err_East_Req_L,
L_err_East_grant_L,
L_err_West_Req_N,
L_err_West_grant_N,
L_err_South_Req_E,
L_err_South_grant_E,
L_err_Local_Req_W,
L_err_Local_grant_W,
L_err_IDLE_Req_L,
L_err_IDLE_grant_L,
L_err_North_Req_L,
L_err_North_grant_L,
L_err_East_Req_N,
L_err_East_grant_N,
L_err_West_Req_E,
L_err_West_grant_E,
L_err_South_Req_W,
L_err_South_grant_W,
L_err_Local_Req_S,
L_err_Local_grant_S,
L_err_state_in_onehot,
L_err_no_request_grants,
L_err_request_no_grants,
L_err_no_Req_N_grant_N,
L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W,
L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E,
N_err_North_req_X_E,
N_err_East_req_X_W,
N_err_West_req_X_S,
N_err_South_req_X_L,
N_err_Local_req_X_N,
N_err_IDLE_req_X_W,
N_err_North_req_X_W,
N_err_East_req_X_S,
N_err_West_req_X_L,
N_err_South_req_X_N,
N_err_Local_req_X_E,
N_err_IDLE_req_X_S,
N_err_North_req_X_S,
N_err_East_req_X_L,
N_err_West_req_X_N,
N_err_South_req_X_E,
N_err_Local_req_X_W,
N_err_IDLE_req_X_L,
N_err_North_req_X_L,
N_err_East_req_X_N,
N_err_West_req_X_E,
N_err_South_req_X_W,
N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E,
E_err_North_req_X_E,
E_err_East_req_X_W,
E_err_West_req_X_S,
E_err_South_req_X_L,
E_err_Local_req_X_N,
E_err_IDLE_req_X_W,
E_err_North_req_X_W,
E_err_East_req_X_S,
E_err_West_req_X_L,
E_err_South_req_X_N,
E_err_Local_req_X_E,
E_err_IDLE_req_X_S,
E_err_North_req_X_S,
E_err_East_req_X_L,
E_err_West_req_X_N,
E_err_South_req_X_E,
E_err_Local_req_X_W,
E_err_IDLE_req_X_L,
E_err_North_req_X_L,
E_err_East_req_X_N,
E_err_West_req_X_E,
E_err_South_req_X_W,
E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N,
W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E,
W_err_North_req_X_E,
W_err_East_req_X_W,
W_err_West_req_X_S,
W_err_South_req_X_L,
W_err_Local_req_X_N,
W_err_IDLE_req_X_W,
W_err_North_req_X_W,
W_err_East_req_X_S,
W_err_West_req_X_L,
W_err_South_req_X_N,
W_err_Local_req_X_E,
W_err_IDLE_req_X_S,
W_err_North_req_X_S,
W_err_East_req_X_L,
W_err_West_req_X_N,
W_err_South_req_X_E,
W_err_Local_req_X_W,
W_err_IDLE_req_X_L,
W_err_North_req_X_L,
W_err_East_req_X_N,
W_err_West_req_X_E,
W_err_South_req_X_W,
W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants,
W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant,
W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N,
S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E,
S_err_North_req_X_E,
S_err_East_req_X_W,
S_err_West_req_X_S,
S_err_South_req_X_L,
S_err_Local_req_X_N,
S_err_IDLE_req_X_W,
S_err_North_req_X_W,
S_err_East_req_X_S,
S_err_West_req_X_L,
S_err_South_req_X_N,
S_err_Local_req_X_E,
S_err_IDLE_req_X_S,
S_err_North_req_X_S,
S_err_East_req_X_L,
S_err_West_req_X_N,
S_err_South_req_X_E,
S_err_Local_req_X_W,
S_err_IDLE_req_X_L,
S_err_North_req_X_L,
S_err_East_req_X_N,
S_err_West_req_X_E,
S_err_South_req_X_W,
S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants,
S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant,
S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant,
S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N,
L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E,
L_err_North_req_X_E,
L_err_East_req_X_W,
L_err_West_req_X_S,
L_err_South_req_X_L,
L_err_Local_req_X_N,
L_err_IDLE_req_X_W,
L_err_North_req_X_W,
L_err_East_req_X_S,
L_err_West_req_X_L,
L_err_South_req_X_N,
L_err_Local_req_X_E,
L_err_IDLE_req_X_S,
L_err_North_req_X_S,
L_err_East_req_X_L,
L_err_West_req_X_N,
L_err_South_req_X_E,
L_err_Local_req_X_W,
L_err_IDLE_req_X_L,
L_err_North_req_X_L,
L_err_East_req_X_N,
L_err_West_req_X_E,
L_err_South_req_X_W,
L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : out std_logic
);
end allocator;
architecture behavior of allocator is
-- so the idea is that we should have counters that keep track of credit!
signal credit_counter_N_in, credit_counter_N_out: std_logic_vector(1 downto 0);
signal credit_counter_E_in, credit_counter_E_out: std_logic_vector(1 downto 0);
signal credit_counter_W_in, credit_counter_W_out: std_logic_vector(1 downto 0);
signal credit_counter_S_in, credit_counter_S_out: std_logic_vector(1 downto 0);
signal credit_counter_L_in, credit_counter_L_out: std_logic_vector(1 downto 0);
signal grant_N, grant_E, grant_W, grant_S, grant_L: std_logic;
signal X_N_N, X_N_E, X_N_W, X_N_S, X_N_L: std_logic;
signal X_E_N, X_E_E, X_E_W, X_E_S, X_E_L: std_logic;
signal X_W_N, X_W_E, X_W_W, X_W_S, X_W_L: std_logic;
signal X_S_N, X_S_E, X_S_W, X_S_S, X_S_L: std_logic;
signal X_L_N, X_L_E, X_L_W, X_L_S, X_L_L: std_logic;
signal grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: std_logic;
signal grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: std_logic;
signal grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: std_logic;
signal grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: std_logic;
signal grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: std_logic;
signal valid_N_sig, valid_E_sig, valid_W_sig, valid_S_sig, valid_L_sig : std_logic;
signal grant_N_N_signal, grant_N_E_signal, grant_N_W_signal, grant_N_S_signal, grant_N_L_signal: std_logic;
signal grant_E_N_signal, grant_E_E_signal, grant_E_W_signal, grant_E_S_signal, grant_E_L_signal: std_logic;
signal grant_W_N_signal, grant_W_E_signal, grant_W_W_signal, grant_W_S_signal, grant_W_L_signal: std_logic;
signal grant_S_N_signal, grant_S_E_signal, grant_S_W_signal, grant_S_S_signal, grant_S_L_signal: std_logic;
signal grant_L_N_signal, grant_L_E_signal, grant_L_W_signal, grant_L_S_signal, grant_L_L_signal: std_logic;
-- Allocator logic checker outputs and allocator credit counter logic checker outputs go directly to the output interface of Allocator
component Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N,
err_IDLE_grant_N,
err_North_Req_N,
err_North_grant_N,
err_East_Req_E,
err_East_grant_E,
err_West_Req_W,
err_West_grant_W,
err_South_Req_S,
err_South_grant_S,
err_Local_Req_L,
err_Local_grant_L,
err_IDLE_Req_E,
err_IDLE_grant_E,
err_North_Req_E,
err_North_grant_E,
err_East_Req_W,
err_East_grant_W,
err_West_Req_S,
err_West_grant_S,
err_South_Req_L,
err_South_grant_L,
err_Local_Req_N,
err_Local_grant_N,
err_IDLE_Req_W,
err_IDLE_grant_W,
err_North_Req_W,
err_North_grant_W,
err_East_Req_S,
err_East_grant_S,
err_West_Req_L,
err_West_grant_L,
err_South_Req_N,
err_South_grant_N,
err_Local_Req_E,
err_Local_grant_E,
err_IDLE_Req_S,
err_IDLE_grant_S,
err_North_Req_S,
err_North_grant_S,
err_East_Req_L,
err_East_grant_L,
err_West_Req_N,
err_West_grant_N,
err_South_Req_E,
err_South_grant_E,
err_Local_Req_W,
err_Local_grant_W,
err_IDLE_Req_L,
err_IDLE_grant_L,
err_North_Req_L,
err_North_grant_L,
err_East_Req_N,
err_East_grant_N,
err_West_Req_E,
err_West_grant_E,
err_South_Req_W,
err_South_grant_W,
err_Local_Req_S,
err_Local_grant_S,
err_state_in_onehot,
err_no_request_grants,
err_request_no_grants,
err_no_Req_N_grant_N,
err_no_Req_E_grant_E,
err_no_Req_W_grant_W,
err_no_Req_S_grant_S,
err_no_Req_L_grant_L : out std_logic
);
end component;
component arbiter_out is
port ( reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y:in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L :out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end component;
-- Checker modules
component allocator_logic_pseudo_checkers is
port (
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
grant_N_N_sig, grant_N_E_sig, grant_N_W_sig, grant_N_S_sig, grant_N_L_sig: in std_logic;
grant_E_N_sig, grant_E_E_sig, grant_E_W_sig, grant_E_S_sig, grant_E_L_sig: in std_logic;
grant_W_N_sig, grant_W_E_sig, grant_W_W_sig, grant_W_S_sig, grant_W_L_sig: in std_logic;
grant_S_N_sig, grant_S_E_sig, grant_S_W_sig, grant_S_S_sig, grant_S_L_sig: in std_logic;
grant_L_N_sig, grant_L_E_sig, grant_L_W_sig, grant_L_S_sig, grant_L_L_sig: in std_logic;
valid_N, valid_E, valid_W, valid_S, valid_L : in std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: in std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: in std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: in std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: in std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L : in std_logic;
-- Checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N,
err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E,
err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W,
err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S,
err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L,
err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match : out std_logic
);
end component;
component allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
-- Not complete yet !
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end component;
begin
-- sequential part
process(clk, reset)
begin
if reset = '0' then
-- we start with all full cradit
credit_counter_N_out <= (others=>'1');
credit_counter_E_out <= (others=>'1');
credit_counter_W_out <= (others=>'1');
credit_counter_S_out <= (others=>'1');
credit_counter_L_out <= (others=>'1');
elsif clk'event and clk = '1' then
credit_counter_N_out <= credit_counter_N_in;
credit_counter_E_out <= credit_counter_E_in;
credit_counter_W_out <= credit_counter_W_in;
credit_counter_S_out <= credit_counter_S_in;
credit_counter_L_out <= credit_counter_L_in;
end if;
end process;
-- The combionational part
-- We did this because of the checkers
valid_N <= valid_N_sig;
valid_E <= valid_E_sig;
valid_W <= valid_W_sig;
valid_S <= valid_S_sig;
valid_L <= valid_L_sig;
grant_N_N <= grant_N_N_signal;
grant_E_N <= grant_E_N_signal;
grant_W_N <= grant_W_N_signal;
grant_S_N <= grant_S_N_signal;
grant_L_N <= grant_L_N_signal;
grant_N_E <= grant_N_E_signal;
grant_E_E <= grant_E_E_signal;
grant_W_E <= grant_W_E_signal;
grant_S_E <= grant_S_E_signal;
grant_L_E <= grant_L_E_signal;
grant_N_W <= grant_N_W_signal;
grant_E_W <= grant_E_W_signal;
grant_W_W <= grant_W_W_signal;
grant_S_W <= grant_S_W_signal;
grant_L_W <= grant_L_W_signal;
grant_N_S <= grant_N_S_signal;
grant_E_S <= grant_E_S_signal;
grant_W_S <= grant_W_S_signal;
grant_S_S <= grant_S_S_signal;
grant_L_S <= grant_L_S_signal;
grant_N_L <= grant_N_L_signal;
grant_E_L <= grant_E_L_signal;
grant_W_L <= grant_W_L_signal;
grant_S_L <= grant_S_L_signal;
grant_L_L <= grant_L_L_signal;
-- Taking Arbiter_in checker outputs to outputs of Allocator
grant_N_N_signal <= grant_N_N_sig and not empty_N;
grant_N_E_signal <= grant_N_E_sig and not empty_E;
grant_N_W_signal <= grant_N_W_sig and not empty_W;
grant_N_S_signal <= grant_N_S_sig and not empty_S;
grant_N_L_signal <= grant_N_L_sig and not empty_L;
grant_E_N_signal <= grant_E_N_sig and not empty_N;
grant_E_E_signal <= grant_E_E_sig and not empty_E;
grant_E_W_signal <= grant_E_W_sig and not empty_W;
grant_E_S_signal <= grant_E_S_sig and not empty_S;
grant_E_L_signal <= grant_E_L_sig and not empty_L;
grant_W_N_signal <= grant_W_N_sig and not empty_N;
grant_W_E_signal <= grant_W_E_sig and not empty_E;
grant_W_W_signal <= grant_W_W_sig and not empty_W;
grant_W_S_signal <= grant_W_S_sig and not empty_S;
grant_W_L_signal <= grant_W_L_sig and not empty_L;
grant_S_N_signal <= grant_S_N_sig and not empty_N;
grant_S_E_signal <= grant_S_E_sig and not empty_E;
grant_S_W_signal <= grant_S_W_sig and not empty_W;
grant_S_S_signal <= grant_S_S_sig and not empty_S;
grant_S_L_signal <= grant_S_L_sig and not empty_L;
grant_L_N_signal <= grant_L_N_sig and not empty_N;
grant_L_E_signal <= grant_L_E_sig and not empty_E;
grant_L_W_signal <= grant_L_W_sig and not empty_W;
grant_L_S_signal <= grant_L_S_sig and not empty_S;
grant_L_L_signal <= grant_L_L_sig and not empty_L;
grant_N <= (grant_N_N_sig and not empty_N )or (grant_N_E_sig and not empty_E) or (grant_N_W_sig and not empty_W) or (grant_N_S_sig and not empty_S) or (grant_N_L_sig and not empty_L);
grant_E <= (grant_E_N_sig and not empty_N )or (grant_E_E_sig and not empty_E) or (grant_E_W_sig and not empty_W) or (grant_E_S_sig and not empty_S) or (grant_E_L_sig and not empty_L);
grant_W <= (grant_W_N_sig and not empty_N )or (grant_W_E_sig and not empty_E) or (grant_W_W_sig and not empty_W) or (grant_W_S_sig and not empty_S) or (grant_W_L_sig and not empty_L);
grant_S <= (grant_S_N_sig and not empty_N )or (grant_S_E_sig and not empty_E) or (grant_S_W_sig and not empty_W) or (grant_S_S_sig and not empty_S) or (grant_S_L_sig and not empty_L);
grant_L <= (grant_L_N_sig and not empty_N )or (grant_L_E_sig and not empty_E) or (grant_L_W_sig and not empty_W) or (grant_L_S_sig and not empty_S) or (grant_L_L_sig and not empty_L);
-- this process handles the credit counters!
process(credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L, grant_N, grant_E, grant_W, grant_S, grant_L,
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out
)
begin
credit_counter_N_in <= credit_counter_N_out;
credit_counter_E_in <= credit_counter_E_out;
credit_counter_W_in <= credit_counter_W_out;
credit_counter_S_in <= credit_counter_S_out;
credit_counter_L_in <= credit_counter_L_out;
if credit_in_N = '1' and grant_N = '1' then
credit_counter_N_in <= credit_counter_N_out;
elsif credit_in_N = '1' and credit_counter_N_out < 3 then
credit_counter_N_in <= credit_counter_N_out + 1;
elsif grant_N = '1' and credit_counter_N_out > 0 then
credit_counter_N_in <= credit_counter_N_out - 1;
end if;
if credit_in_E = '1' and grant_E = '1' then
credit_counter_E_in <= credit_counter_E_out;
elsif credit_in_E = '1' and credit_counter_E_out < 3 then
credit_counter_E_in <= credit_counter_E_out + 1;
elsif grant_E = '1' and credit_counter_E_out > 0 then
credit_counter_E_in <= credit_counter_E_out - 1;
end if;
if credit_in_W = '1' and grant_W = '1' then
credit_counter_W_in <= credit_counter_W_out;
elsif credit_in_W = '1' and credit_counter_W_out < 3 then
credit_counter_W_in <= credit_counter_W_out + 1;
elsif grant_W = '1' and credit_counter_W_out > 0 then
credit_counter_W_in <= credit_counter_W_out - 1;
end if;
if credit_in_S = '1' and grant_S = '1' then
credit_counter_S_in <= credit_counter_S_out;
elsif credit_in_S = '1' and credit_counter_S_out < 3 then
credit_counter_S_in <= credit_counter_S_out + 1;
elsif grant_S = '1' and credit_counter_S_out > 0 then
credit_counter_S_in <= credit_counter_S_out - 1;
end if;
if credit_in_L = '1' and grant_L = '1' then
credit_counter_L_in <= credit_counter_L_out;
elsif credit_in_L = '1' and credit_counter_L_out < 3 then
credit_counter_L_in <= credit_counter_L_out + 1;
elsif grant_L = '1' and credit_counter_L_out > 0 then
credit_counter_L_in <= credit_counter_L_out - 1;
end if;
end process;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Allocator logic checkers module instantiation
ALLOCATOR_LOGIC_CHECKERS: allocator_logic_pseudo_checkers PORT MAP (
empty_N => empty_N,
empty_E => empty_E,
empty_W => empty_W,
empty_S => empty_S,
empty_L => empty_L,
grant_N_N_sig => grant_N_N_sig, grant_N_E_sig => grant_N_E_sig, grant_N_W_sig => grant_N_W_sig, grant_N_S_sig => grant_N_S_sig, grant_N_L_sig => grant_N_L_sig,
grant_E_N_sig => grant_E_N_sig, grant_E_E_sig => grant_E_E_sig, grant_E_W_sig => grant_E_W_sig, grant_E_S_sig => grant_E_S_sig, grant_E_L_sig => grant_E_L_sig,
grant_W_N_sig => grant_W_N_sig, grant_W_E_sig => grant_W_E_sig, grant_W_W_sig => grant_W_W_sig, grant_W_S_sig => grant_W_S_sig, grant_W_L_sig => grant_W_L_sig,
grant_S_N_sig => grant_S_N_sig, grant_S_E_sig => grant_S_E_sig, grant_S_W_sig => grant_S_W_sig, grant_S_S_sig => grant_S_S_sig, grant_S_L_sig => grant_S_L_sig,
grant_L_N_sig => grant_L_N_sig, grant_L_E_sig => grant_L_E_sig, grant_L_W_sig => grant_L_W_sig, grant_L_S_sig => grant_L_S_sig, grant_L_L_sig => grant_L_L_sig,
valid_N => valid_N_sig,
valid_E => valid_E_sig,
valid_W => valid_W_sig,
valid_S => valid_S_sig,
valid_L => valid_L_sig,
grant_N_N => grant_N_N_signal,
grant_N_E => grant_N_E_signal,
grant_N_W => grant_N_W_signal,
grant_N_S => grant_N_S_signal,
grant_N_L => grant_N_L_signal,
grant_E_N => grant_E_N_signal,
grant_E_E => grant_E_E_signal,
grant_E_W => grant_E_W_signal,
grant_E_S => grant_E_S_signal,
grant_E_L => grant_E_L_signal,
grant_W_N => grant_W_N_signal,
grant_W_E => grant_W_E_signal,
grant_W_W => grant_W_W_signal,
grant_W_S => grant_W_S_signal,
grant_W_L => grant_W_L_signal,
grant_S_N => grant_S_N_signal,
grant_S_E => grant_S_E_signal,
grant_S_W => grant_S_W_signal,
grant_S_S => grant_S_S_signal,
grant_S_L => grant_S_L_signal,
grant_L_N => grant_L_N_signal,
grant_L_E => grant_L_E_signal,
grant_L_W => grant_L_W_signal,
grant_L_S => grant_L_S_signal,
grant_L_L => grant_L_L_signal,
grant_N => grant_N,
grant_E => grant_E,
grant_W => grant_W,
grant_S => grant_S,
grant_L => grant_L,
-- Checker Outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match
);
-- Allocator credit counter logic checkers module instantiation
ALLOCATOR_CREDIT_COUNTER_LOGIC_CHECKERS: allocator_credit_counter_logic_pseudo_checkers PORT MAP (
credit_in_N => credit_in_N,
credit_in_E => credit_in_E,
credit_in_W => credit_in_W,
credit_in_S => credit_in_S,
credit_in_L => credit_in_L,
credit_counter_N_out => credit_counter_N_out, credit_counter_E_out => credit_counter_E_out, credit_counter_W_out => credit_counter_W_out, credit_counter_S_out => credit_counter_S_out, credit_counter_L_out => credit_counter_L_out,
valid_N => grant_N, -- Must be connected to grant signals!
valid_E => grant_E, -- Must be connected to grant signals!
valid_W => grant_W, -- Must be connected to grant signals!
valid_S => grant_S, -- Must be connected to grant signals!
valid_L => grant_L, -- Must be connected to grant signals!
credit_counter_N_in => credit_counter_N_in,
credit_counter_E_in => credit_counter_E_in,
credit_counter_W_in => credit_counter_W_in,
credit_counter_S_in => credit_counter_S_in,
credit_counter_L_in => credit_counter_L_in,
-- Checker Outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter In
-- North Arbiter_in with checkers integrated (module instantiation)
arb_N_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_N_N, Req_X_E=> req_N_E, Req_X_W=>req_N_W, Req_X_S=>req_N_S, Req_X_L=>req_N_L,
X_N=>X_N_N, X_E=>X_N_E, X_W=>X_N_W, X_S=>X_N_S, X_L=>X_N_L,
-- North Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => N_err_IDLE_Req_N,
err_IDLE_grant_N => N_err_IDLE_grant_N,
err_North_Req_N => N_err_North_Req_N,
err_North_grant_N => N_err_North_grant_N,
err_East_Req_E => N_err_East_Req_E,
err_East_grant_E => N_err_East_grant_E,
err_West_Req_W => N_err_West_Req_W,
err_West_grant_W => N_err_West_grant_W,
err_South_Req_S => N_err_South_Req_S,
err_South_grant_S => N_err_South_grant_S,
err_Local_Req_L => N_err_Local_Req_L,
err_Local_grant_L => N_err_Local_grant_L,
err_IDLE_Req_E => N_err_IDLE_Req_E,
err_IDLE_grant_E => N_err_IDLE_grant_E,
err_North_Req_E => N_err_North_Req_E,
err_North_grant_E => N_err_North_grant_E,
err_East_Req_W => N_err_East_Req_W,
err_East_grant_W => N_err_East_grant_W,
err_West_Req_S => N_err_West_Req_S,
err_West_grant_S => N_err_West_grant_S,
err_South_Req_L => N_err_South_Req_L,
err_South_grant_L => N_err_South_grant_L,
err_Local_Req_N => N_err_Local_Req_N,
err_Local_grant_N => N_err_Local_grant_N,
err_IDLE_Req_W => N_err_IDLE_Req_W,
err_IDLE_grant_W => N_err_IDLE_grant_W,
err_North_Req_W => N_err_North_Req_W,
err_North_grant_W => N_err_North_grant_W,
err_East_Req_S => N_err_East_Req_S,
err_East_grant_S => N_err_East_grant_S,
err_West_Req_L => N_err_West_Req_L,
err_West_grant_L => N_err_West_grant_L,
err_South_Req_N => N_err_South_Req_N,
err_South_grant_N => N_err_South_grant_N,
err_Local_Req_E => N_err_Local_Req_E,
err_Local_grant_E => N_err_Local_grant_E,
err_IDLE_Req_S => N_err_IDLE_Req_S,
err_IDLE_grant_S => N_err_IDLE_grant_S,
err_North_Req_S => N_err_North_Req_S,
err_North_grant_S => N_err_North_grant_S,
err_East_Req_L => N_err_East_Req_L,
err_East_grant_L => N_err_East_grant_L,
err_West_Req_N => N_err_West_Req_N,
err_West_grant_N => N_err_West_grant_N,
err_South_Req_E => N_err_South_Req_E,
err_South_grant_E => N_err_South_grant_E,
err_Local_Req_W => N_err_Local_Req_W,
err_Local_grant_W => N_err_Local_grant_W,
err_IDLE_Req_L => N_err_IDLE_Req_L,
err_IDLE_grant_L => N_err_IDLE_grant_L,
err_North_Req_L => N_err_North_Req_L,
err_North_grant_L => N_err_North_grant_L,
err_East_Req_N => N_err_East_Req_N,
err_East_grant_N => N_err_East_grant_N,
err_West_Req_E => N_err_West_Req_E,
err_West_grant_E => N_err_West_grant_E,
err_South_Req_W => N_err_South_Req_W,
err_South_grant_W => N_err_South_grant_W,
err_Local_Req_S => N_err_Local_Req_S,
err_Local_grant_S => N_err_Local_grant_S,
err_state_in_onehot => N_err_state_in_onehot,
err_no_request_grants => N_err_no_request_grants,
err_request_no_grants => N_err_request_no_grants,
err_no_Req_N_grant_N => N_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => N_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => N_err_no_Req_L_grant_L
);
arb_E_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_E_N, Req_X_E=> req_E_E, Req_X_W=>req_E_W, Req_X_S=>req_E_S, Req_X_L=>req_E_L,
X_N=>X_E_N, X_E=>X_E_E, X_W=>X_E_W, X_S=>X_E_S, X_L=>X_E_L,
-- East Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => E_err_IDLE_Req_N,
err_IDLE_grant_N => E_err_IDLE_grant_N,
err_North_Req_N => E_err_North_Req_N,
err_North_grant_N => E_err_North_grant_N,
err_East_Req_E => E_err_East_Req_E,
err_East_grant_E => E_err_East_grant_E,
err_West_Req_W => E_err_West_Req_W,
err_West_grant_W => E_err_West_grant_W,
err_South_Req_S => E_err_South_Req_S,
err_South_grant_S => E_err_South_grant_S,
err_Local_Req_L => E_err_Local_Req_L,
err_Local_grant_L => E_err_Local_grant_L,
err_IDLE_Req_E => E_err_IDLE_Req_E,
err_IDLE_grant_E => E_err_IDLE_grant_E,
err_North_Req_E => E_err_North_Req_E,
err_North_grant_E => E_err_North_grant_E,
err_East_Req_W => E_err_East_Req_W,
err_East_grant_W => E_err_East_grant_W,
err_West_Req_S => E_err_West_Req_S,
err_West_grant_S => E_err_West_grant_S,
err_South_Req_L => E_err_South_Req_L,
err_South_grant_L => E_err_South_grant_L,
err_Local_Req_N => E_err_Local_Req_N,
err_Local_grant_N => E_err_Local_grant_N,
err_IDLE_Req_W => E_err_IDLE_Req_W,
err_IDLE_grant_W => E_err_IDLE_grant_W,
err_North_Req_W => E_err_North_Req_W,
err_North_grant_W => E_err_North_grant_W,
err_East_Req_S => E_err_East_Req_S,
err_East_grant_S => E_err_East_grant_S,
err_West_Req_L => E_err_West_Req_L,
err_West_grant_L => E_err_West_grant_L,
err_South_Req_N => E_err_South_Req_N,
err_South_grant_N => E_err_South_grant_N,
err_Local_Req_E => E_err_Local_Req_E,
err_Local_grant_E => E_err_Local_grant_E,
err_IDLE_Req_S => E_err_IDLE_Req_S,
err_IDLE_grant_S => E_err_IDLE_grant_S,
err_North_Req_S => E_err_North_Req_S,
err_North_grant_S => E_err_North_grant_S,
err_East_Req_L => E_err_East_Req_L,
err_East_grant_L => E_err_East_grant_L,
err_West_Req_N => E_err_West_Req_N,
err_West_grant_N => E_err_West_grant_N,
err_South_Req_E => E_err_South_Req_E,
err_South_grant_E => E_err_South_grant_E,
err_Local_Req_W => E_err_Local_Req_W,
err_Local_grant_W => E_err_Local_grant_W,
err_IDLE_Req_L => E_err_IDLE_Req_L,
err_IDLE_grant_L => E_err_IDLE_grant_L,
err_North_Req_L => E_err_North_Req_L,
err_North_grant_L => E_err_North_grant_L,
err_East_Req_N => E_err_East_Req_N,
err_East_grant_N => E_err_East_grant_N,
err_West_Req_E => E_err_West_Req_E,
err_West_grant_E => E_err_West_grant_E,
err_South_Req_W => E_err_South_Req_W,
err_South_grant_W => E_err_South_grant_W,
err_Local_Req_S => E_err_Local_Req_S,
err_Local_grant_S => E_err_Local_grant_S,
err_state_in_onehot => E_err_state_in_onehot,
err_no_request_grants => E_err_no_request_grants,
err_request_no_grants => E_err_request_no_grants,
err_no_Req_N_grant_N => E_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => E_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => E_err_no_Req_L_grant_L
);
arb_W_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_W_N, Req_X_E=> req_W_E, Req_X_W=>req_W_W, Req_X_S=>req_W_S, Req_X_L=>req_W_L,
X_N=>X_W_N, X_E=>X_W_E, X_W=>X_W_W, X_S=>X_W_S, X_L=>X_W_L,
-- West Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => W_err_IDLE_Req_N,
err_IDLE_grant_N => W_err_IDLE_grant_N,
err_North_Req_N => W_err_North_Req_N,
err_North_grant_N => W_err_North_grant_N,
err_East_Req_E => W_err_East_Req_E,
err_East_grant_E => W_err_East_grant_E,
err_West_Req_W => W_err_West_Req_W,
err_West_grant_W => W_err_West_grant_W,
err_South_Req_S => W_err_South_Req_S,
err_South_grant_S => W_err_South_grant_S,
err_Local_Req_L => W_err_Local_Req_L,
err_Local_grant_L => W_err_Local_grant_L,
err_IDLE_Req_E => W_err_IDLE_Req_E,
err_IDLE_grant_E => W_err_IDLE_grant_E,
err_North_Req_E => W_err_North_Req_E,
err_North_grant_E => W_err_North_grant_E,
err_East_Req_W => W_err_East_Req_W,
err_East_grant_W => W_err_East_grant_W,
err_West_Req_S => W_err_West_Req_S,
err_West_grant_S => W_err_West_grant_S,
err_South_Req_L => W_err_South_Req_L,
err_South_grant_L => W_err_South_grant_L,
err_Local_Req_N => W_err_Local_Req_N,
err_Local_grant_N => W_err_Local_grant_N,
err_IDLE_Req_W => W_err_IDLE_Req_W,
err_IDLE_grant_W => W_err_IDLE_grant_W,
err_North_Req_W => W_err_North_Req_W,
err_North_grant_W => W_err_North_grant_W,
err_East_Req_S => W_err_East_Req_S,
err_East_grant_S => W_err_East_grant_S,
err_West_Req_L => W_err_West_Req_L,
err_West_grant_L => W_err_West_grant_L,
err_South_Req_N => W_err_South_Req_N,
err_South_grant_N => W_err_South_grant_N,
err_Local_Req_E => W_err_Local_Req_E,
err_Local_grant_E => W_err_Local_grant_E,
err_IDLE_Req_S => W_err_IDLE_Req_S,
err_IDLE_grant_S => W_err_IDLE_grant_S,
err_North_Req_S => W_err_North_Req_S,
err_North_grant_S => W_err_North_grant_S,
err_East_Req_L => W_err_East_Req_L,
err_East_grant_L => W_err_East_grant_L,
err_West_Req_N => W_err_West_Req_N,
err_West_grant_N => W_err_West_grant_N,
err_South_Req_E => W_err_South_Req_E,
err_South_grant_E => W_err_South_grant_E,
err_Local_Req_W => W_err_Local_Req_W,
err_Local_grant_W => W_err_Local_grant_W,
err_IDLE_Req_L => W_err_IDLE_Req_L,
err_IDLE_grant_L => W_err_IDLE_grant_L,
err_North_Req_L => W_err_North_Req_L,
err_North_grant_L => W_err_North_grant_L,
err_East_Req_N => W_err_East_Req_N,
err_East_grant_N => W_err_East_grant_N,
err_West_Req_E => W_err_West_Req_E,
err_West_grant_E => W_err_West_grant_E,
err_South_Req_W => W_err_South_Req_W,
err_South_grant_W => W_err_South_grant_W,
err_Local_Req_S => W_err_Local_Req_S,
err_Local_grant_S => W_err_Local_grant_S,
err_state_in_onehot => W_err_state_in_onehot,
err_no_request_grants => W_err_no_request_grants,
err_request_no_grants => W_err_request_no_grants,
err_no_Req_N_grant_N => W_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => W_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => W_err_no_Req_L_grant_L
);
arb_S_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_S_N, Req_X_E=> req_S_E, Req_X_W=>req_S_W, Req_X_S=>req_S_S, Req_X_L=>req_S_L,
X_N=>X_S_N, X_E=>X_S_E, X_W=>X_S_W, X_S=>X_S_S, X_L=>X_S_L,
-- South Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => S_err_IDLE_Req_N,
err_IDLE_grant_N => S_err_IDLE_grant_N,
err_North_Req_N => S_err_North_Req_N,
err_North_grant_N => S_err_North_grant_N,
err_East_Req_E => S_err_East_Req_E,
err_East_grant_E => S_err_East_grant_E,
err_West_Req_W => S_err_West_Req_W,
err_West_grant_W => S_err_West_grant_W,
err_South_Req_S => S_err_South_Req_S,
err_South_grant_S => S_err_South_grant_S,
err_Local_Req_L => S_err_Local_Req_L,
err_Local_grant_L => S_err_Local_grant_L,
err_IDLE_Req_E => S_err_IDLE_Req_E,
err_IDLE_grant_E => S_err_IDLE_grant_E,
err_North_Req_E => S_err_North_Req_E,
err_North_grant_E => S_err_North_grant_E,
err_East_Req_W => S_err_East_Req_W,
err_East_grant_W => S_err_East_grant_W,
err_West_Req_S => S_err_West_Req_S,
err_West_grant_S => S_err_West_grant_S,
err_South_Req_L => S_err_South_Req_L,
err_South_grant_L => S_err_South_grant_L,
err_Local_Req_N => S_err_Local_Req_N,
err_Local_grant_N => S_err_Local_grant_N,
err_IDLE_Req_W => S_err_IDLE_Req_W,
err_IDLE_grant_W => S_err_IDLE_grant_W,
err_North_Req_W => S_err_North_Req_W,
err_North_grant_W => S_err_North_grant_W,
err_East_Req_S => S_err_East_Req_S,
err_East_grant_S => S_err_East_grant_S,
err_West_Req_L => S_err_West_Req_L,
err_West_grant_L => S_err_West_grant_L,
err_South_Req_N => S_err_South_Req_N,
err_South_grant_N => S_err_South_grant_N,
err_Local_Req_E => S_err_Local_Req_E,
err_Local_grant_E => S_err_Local_grant_E,
err_IDLE_Req_S => S_err_IDLE_Req_S,
err_IDLE_grant_S => S_err_IDLE_grant_S,
err_North_Req_S => S_err_North_Req_S,
err_North_grant_S => S_err_North_grant_S,
err_East_Req_L => S_err_East_Req_L,
err_East_grant_L => S_err_East_grant_L,
err_West_Req_N => S_err_West_Req_N,
err_West_grant_N => S_err_West_grant_N,
err_South_Req_E => S_err_South_Req_E,
err_South_grant_E => S_err_South_grant_E,
err_Local_Req_W => S_err_Local_Req_W,
err_Local_grant_W => S_err_Local_grant_W,
err_IDLE_Req_L => S_err_IDLE_Req_L,
err_IDLE_grant_L => S_err_IDLE_grant_L,
err_North_Req_L => S_err_North_Req_L,
err_North_grant_L => S_err_North_grant_L,
err_East_Req_N => S_err_East_Req_N,
err_East_grant_N => S_err_East_grant_N,
err_West_Req_E => S_err_West_Req_E,
err_West_grant_E => S_err_West_grant_E,
err_South_Req_W => S_err_South_Req_W,
err_South_grant_W => S_err_South_grant_W,
err_Local_Req_S => S_err_Local_Req_S,
err_Local_grant_S => S_err_Local_grant_S,
err_state_in_onehot => S_err_state_in_onehot,
err_no_request_grants => S_err_no_request_grants,
err_request_no_grants => S_err_request_no_grants,
err_no_Req_N_grant_N => S_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => S_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => S_err_no_Req_L_grant_L
);
arb_L_X: Arbiter_in PORT MAP (reset => reset, clk => clk,
Req_X_N=>req_L_N, Req_X_E=> req_L_E, Req_X_W=>req_L_W, Req_X_S=>req_L_S, Req_X_L=>req_L_L,
X_N=>X_L_N, X_E=>X_L_E, X_W=>X_L_W, X_S=>X_L_S, X_L=>X_L_L,
-- Local Arbiter_in Checker outputs
err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => L_err_IDLE_Req_N,
err_IDLE_grant_N => L_err_IDLE_grant_N,
err_North_Req_N => L_err_North_Req_N,
err_North_grant_N => L_err_North_grant_N,
err_East_Req_E => L_err_East_Req_E,
err_East_grant_E => L_err_East_grant_E,
err_West_Req_W => L_err_West_Req_W,
err_West_grant_W => L_err_West_grant_W,
err_South_Req_S => L_err_South_Req_S,
err_South_grant_S => L_err_South_grant_S,
err_Local_Req_L => L_err_Local_Req_L,
err_Local_grant_L => L_err_Local_grant_L,
err_IDLE_Req_E => L_err_IDLE_Req_E,
err_IDLE_grant_E => L_err_IDLE_grant_E,
err_North_Req_E => L_err_North_Req_E,
err_North_grant_E => L_err_North_grant_E,
err_East_Req_W => L_err_East_Req_W,
err_East_grant_W => L_err_East_grant_W,
err_West_Req_S => L_err_West_Req_S,
err_West_grant_S => L_err_West_grant_S,
err_South_Req_L => L_err_South_Req_L,
err_South_grant_L => L_err_South_grant_L,
err_Local_Req_N => L_err_Local_Req_N,
err_Local_grant_N => L_err_Local_grant_N,
err_IDLE_Req_W => L_err_IDLE_Req_W,
err_IDLE_grant_W => L_err_IDLE_grant_W,
err_North_Req_W => L_err_North_Req_W,
err_North_grant_W => L_err_North_grant_W,
err_East_Req_S => L_err_East_Req_S,
err_East_grant_S => L_err_East_grant_S,
err_West_Req_L => L_err_West_Req_L,
err_West_grant_L => L_err_West_grant_L,
err_South_Req_N => L_err_South_Req_N,
err_South_grant_N => L_err_South_grant_N,
err_Local_Req_E => L_err_Local_Req_E,
err_Local_grant_E => L_err_Local_grant_E,
err_IDLE_Req_S => L_err_IDLE_Req_S,
err_IDLE_grant_S => L_err_IDLE_grant_S,
err_North_Req_S => L_err_North_Req_S,
err_North_grant_S => L_err_North_grant_S,
err_East_Req_L => L_err_East_Req_L,
err_East_grant_L => L_err_East_grant_L,
err_West_Req_N => L_err_West_Req_N,
err_West_grant_N => L_err_West_grant_N,
err_South_Req_E => L_err_South_Req_E,
err_South_grant_E => L_err_South_grant_E,
err_Local_Req_W => L_err_Local_Req_W,
err_Local_grant_W => L_err_Local_grant_W,
err_IDLE_Req_L => L_err_IDLE_Req_L,
err_IDLE_grant_L => L_err_IDLE_grant_L,
err_North_Req_L => L_err_North_Req_L,
err_North_grant_L => L_err_North_grant_L,
err_East_Req_N => L_err_East_Req_N,
err_East_grant_N => L_err_East_grant_N,
err_West_Req_E => L_err_West_Req_E,
err_West_grant_E => L_err_West_grant_E,
err_South_Req_W => L_err_South_Req_W,
err_South_grant_W => L_err_South_grant_W,
err_Local_Req_S => L_err_Local_Req_S,
err_Local_grant_S => L_err_Local_grant_S,
err_state_in_onehot => L_err_state_in_onehot,
err_no_request_grants => L_err_no_request_grants,
err_request_no_grants => L_err_request_no_grants,
err_no_Req_N_grant_N => L_err_no_Req_N_grant_N,
err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
err_no_Req_W_grant_W => L_err_no_Req_W_grant_W,
err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
err_no_Req_L_grant_L => L_err_no_Req_L_grant_L
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter Out mobuldes instantiation(s)
-- Y is N now
-- North Arbiter_out with checkers integrated
arb_X_N: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_N, X_E_Y => X_E_N, X_W_Y => X_W_N, X_S_Y => X_S_N, X_L_Y => X_L_N,
credit => credit_counter_N_out,
grant_Y_N => grant_N_N_sig,
grant_Y_E => grant_N_E_sig,
grant_Y_W => grant_N_W_sig,
grant_Y_S => grant_N_S_sig,
grant_Y_L => grant_N_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => N_err_IDLE_req_X_N,
err_North_req_X_N => N_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => N_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => N_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => N_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => N_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => N_err_IDLE_req_X_E,
err_North_req_X_E => N_err_North_req_X_E,
err_East_req_X_W => N_err_East_req_X_W,
err_West_req_X_S => N_err_West_req_X_S,
err_South_req_X_L => N_err_South_req_X_L,
err_Local_req_X_N => N_err_Local_req_X_N,
err_IDLE_req_X_W => N_err_IDLE_req_X_W,
err_North_req_X_W => N_err_North_req_X_W,
err_East_req_X_S => N_err_East_req_X_S,
err_West_req_X_L => N_err_West_req_X_L,
err_South_req_X_N => N_err_South_req_X_N,
err_Local_req_X_E => N_err_Local_req_X_E,
err_IDLE_req_X_S => N_err_IDLE_req_X_S,
err_North_req_X_S => N_err_North_req_X_S,
err_East_req_X_L => N_err_East_req_X_L,
err_West_req_X_N => N_err_West_req_X_N,
err_South_req_X_E => N_err_South_req_X_E,
err_Local_req_X_W => N_err_Local_req_X_W,
err_IDLE_req_X_L => N_err_IDLE_req_X_L,
err_North_req_X_L => N_err_North_req_X_L,
err_East_req_X_N => N_err_East_req_X_N,
err_West_req_X_E => N_err_West_req_X_E,
err_South_req_X_W => N_err_South_req_X_W,
err_Local_req_X_S => N_err_Local_req_X_S,
err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
err_no_request_grants => N_arbiter_out_err_no_request_grants,
err_request_IDLE_state => N_err_request_IDLE_state,
err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero
);
-- Y is E now
-- East Arbiter_out with checkers integrated
arb_X_E: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_E, X_E_Y => X_E_E, X_W_Y => X_W_E, X_S_Y => X_S_E, X_L_Y => X_L_E,
credit => credit_counter_E_out,
grant_Y_N => grant_E_N_sig,
grant_Y_E => grant_E_E_sig,
grant_Y_W => grant_E_W_sig,
grant_Y_S => grant_E_S_sig,
grant_Y_L => grant_E_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => E_err_IDLE_req_X_N,
err_North_req_X_N => E_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => E_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => E_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => E_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => E_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => E_err_IDLE_req_X_E,
err_North_req_X_E => E_err_North_req_X_E,
err_East_req_X_W => E_err_East_req_X_W,
err_West_req_X_S => E_err_West_req_X_S,
err_South_req_X_L => E_err_South_req_X_L,
err_Local_req_X_N => E_err_Local_req_X_N,
err_IDLE_req_X_W => E_err_IDLE_req_X_W,
err_North_req_X_W => E_err_North_req_X_W,
err_East_req_X_S => E_err_East_req_X_S,
err_West_req_X_L => E_err_West_req_X_L,
err_South_req_X_N => E_err_South_req_X_N,
err_Local_req_X_E => E_err_Local_req_X_E,
err_IDLE_req_X_S => E_err_IDLE_req_X_S,
err_North_req_X_S => E_err_North_req_X_S,
err_East_req_X_L => E_err_East_req_X_L,
err_West_req_X_N => E_err_West_req_X_N,
err_South_req_X_E => E_err_South_req_X_E,
err_Local_req_X_W => E_err_Local_req_X_W,
err_IDLE_req_X_L => E_err_IDLE_req_X_L,
err_North_req_X_L => E_err_North_req_X_L,
err_East_req_X_N => E_err_East_req_X_N,
err_West_req_X_E => E_err_West_req_X_E,
err_South_req_X_W => E_err_South_req_X_W,
err_Local_req_X_S => E_err_Local_req_X_S,
err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
err_no_request_grants => E_arbiter_out_err_no_request_grants,
err_request_IDLE_state => E_err_request_IDLE_state,
err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero
);
-- Y is W now
-- West Arbiter_out with checkers integrated
arb_X_W: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_W, X_E_Y => X_E_W, X_W_Y => X_W_W, X_S_Y => X_S_W, X_L_Y => X_L_W,
credit => credit_counter_W_out,
grant_Y_N => grant_W_N_sig,
grant_Y_E => grant_W_E_sig,
grant_Y_W => grant_W_W_sig,
grant_Y_S => grant_W_S_sig,
grant_Y_L => grant_W_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => W_err_IDLE_req_X_N,
err_North_req_X_N => W_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => W_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => W_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => W_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => W_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => W_err_IDLE_req_X_E,
err_North_req_X_E => W_err_North_req_X_E,
err_East_req_X_W => W_err_East_req_X_W,
err_West_req_X_S => W_err_West_req_X_S,
err_South_req_X_L => W_err_South_req_X_L,
err_Local_req_X_N => W_err_Local_req_X_N,
err_IDLE_req_X_W => W_err_IDLE_req_X_W,
err_North_req_X_W => W_err_North_req_X_W,
err_East_req_X_S => W_err_East_req_X_S,
err_West_req_X_L => W_err_West_req_X_L,
err_South_req_X_N => W_err_South_req_X_N,
err_Local_req_X_E => W_err_Local_req_X_E,
err_IDLE_req_X_S => W_err_IDLE_req_X_S,
err_North_req_X_S => W_err_North_req_X_S,
err_East_req_X_L => W_err_East_req_X_L,
err_West_req_X_N => W_err_West_req_X_N,
err_South_req_X_E => W_err_South_req_X_E,
err_Local_req_X_W => W_err_Local_req_X_W,
err_IDLE_req_X_L => W_err_IDLE_req_X_L,
err_North_req_X_L => W_err_North_req_X_L,
err_East_req_X_N => W_err_East_req_X_N,
err_West_req_X_E => W_err_West_req_X_E,
err_South_req_X_W => W_err_South_req_X_W,
err_Local_req_X_S => W_err_Local_req_X_S,
err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
err_no_request_grants => W_arbiter_out_err_no_request_grants,
err_request_IDLE_state => W_err_request_IDLE_state,
err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero
);
-- Y is S now
-- South Arbiter_out with checkers integrated
arb_X_S: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_S, X_E_Y => X_E_S, X_W_Y => X_W_S, X_S_Y => X_S_S, X_L_Y => X_L_S,
credit => credit_counter_S_out,
grant_Y_N => grant_S_N_sig,
grant_Y_E => grant_S_E_sig,
grant_Y_W => grant_S_W_sig,
grant_Y_S => grant_S_S_sig,
grant_Y_L => grant_S_L_sig,
-- Checker outputs
err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => S_err_IDLE_req_X_N,
err_North_req_X_N => S_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => S_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => S_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => S_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => S_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => S_err_IDLE_req_X_E,
err_North_req_X_E => S_err_North_req_X_E,
err_East_req_X_W => S_err_East_req_X_W,
err_West_req_X_S => S_err_West_req_X_S,
err_South_req_X_L => S_err_South_req_X_L,
err_Local_req_X_N => S_err_Local_req_X_N,
err_IDLE_req_X_W => S_err_IDLE_req_X_W,
err_North_req_X_W => S_err_North_req_X_W,
err_East_req_X_S => S_err_East_req_X_S,
err_West_req_X_L => S_err_West_req_X_L,
err_South_req_X_N => S_err_South_req_X_N,
err_Local_req_X_E => S_err_Local_req_X_E,
err_IDLE_req_X_S => S_err_IDLE_req_X_S,
err_North_req_X_S => S_err_North_req_X_S,
err_East_req_X_L => S_err_East_req_X_L,
err_West_req_X_N => S_err_West_req_X_N,
err_South_req_X_E => S_err_South_req_X_E,
err_Local_req_X_W => S_err_Local_req_X_W,
err_IDLE_req_X_L => S_err_IDLE_req_X_L,
err_North_req_X_L => S_err_North_req_X_L,
err_East_req_X_N => S_err_East_req_X_N,
err_West_req_X_E => S_err_West_req_X_E,
err_South_req_X_W => S_err_South_req_X_W,
err_Local_req_X_S => S_err_Local_req_X_S,
err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
err_no_request_grants => S_arbiter_out_err_no_request_grants,
err_request_IDLE_state => S_err_request_IDLE_state,
err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero
);
-- Y is L now
-- Local Arbiter_out with checkers integrated
arb_X_L: arbiter_out port map (reset => reset, clk => clk,
X_N_Y => X_N_L, X_E_Y => X_E_L, X_W_Y => X_W_L, X_S_Y => X_S_L, X_L_Y => X_L_L,
credit => credit_counter_L_out,
grant_Y_N => grant_L_N_sig,
grant_Y_E => grant_L_E_sig,
grant_Y_W => grant_L_W_sig,
grant_Y_S => grant_L_S_sig,
grant_Y_L => grant_L_L_sig,
err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N => L_err_IDLE_req_X_N,
err_North_req_X_N => L_err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E => L_err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W => L_err_West_req_X_W,
err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S => L_err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L => L_err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E => L_err_IDLE_req_X_E,
err_North_req_X_E => L_err_North_req_X_E,
err_East_req_X_W => L_err_East_req_X_W,
err_West_req_X_S => L_err_West_req_X_S,
err_South_req_X_L => L_err_South_req_X_L,
err_Local_req_X_N => L_err_Local_req_X_N,
err_IDLE_req_X_W => L_err_IDLE_req_X_W,
err_North_req_X_W => L_err_North_req_X_W,
err_East_req_X_S => L_err_East_req_X_S,
err_West_req_X_L => L_err_West_req_X_L,
err_South_req_X_N => L_err_South_req_X_N,
err_Local_req_X_E => L_err_Local_req_X_E,
err_IDLE_req_X_S => L_err_IDLE_req_X_S,
err_North_req_X_S => L_err_North_req_X_S,
err_East_req_X_L => L_err_East_req_X_L,
err_West_req_X_N => L_err_West_req_X_N,
err_South_req_X_E => L_err_South_req_X_E,
err_Local_req_X_W => L_err_Local_req_X_W,
err_IDLE_req_X_L => L_err_IDLE_req_X_L,
err_North_req_X_L => L_err_North_req_X_L,
err_East_req_X_N => L_err_East_req_X_N,
err_West_req_X_E => L_err_West_req_X_E,
err_South_req_X_W => L_err_South_req_X_W,
err_Local_req_X_S => L_err_Local_req_X_S,
err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
err_no_request_grants => L_arbiter_out_err_no_request_grants,
err_request_IDLE_state => L_err_request_IDLE_state,
err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
valid_N_sig <= grant_N;
valid_E_sig <= grant_E;
valid_W_sig <= grant_W;
valid_S_sig <= grant_S;
valid_L_sig <= grant_L;
END;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Rxy_Reconf/RTL/Rxy_Reconf_pseudo_checkers.vhd
|
6
|
3437
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/control.vhd
|
3
|
23321
|
---------------------------------------------------------------------
-- TITLE: Controller / Opcode Decoder
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: control.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- NOTE: MIPS(tm) is a registered trademark of MIPS Technologies.
-- MIPS Technologies does not endorse and is not associated with
-- this project.
-- DESCRIPTION:
-- Controls the CPU by decoding the opcode and generating control
-- signals to the rest of the CPU.
-- This entity decodes the MIPS(tm) opcode into a
-- Very-Long-Word-Instruction.
-- The 32-bit opcode is converted to a
-- 6+6+6+16+4+2+4+3+2+2+3+2+4 = 60 bit VLWI opcode.
-- Based on information found in:
-- "MIPS RISC Architecture" by Gerry Kane and Joe Heinrich
-- and "The Designer's Guide to VHDL" by Peter J. Ashenden
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * EPC register have been changed! It used to be R0, now it is R26
-- * added the instruction type and signal for debuging the CPU behaviour!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity control is
port(opcode : in std_logic_vector(31 downto 0); -- not opcode, but the whole instruction !!! (opcode is the first 6 most significant bits of the instruction.)
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end; --entity control
architecture logic of control is
-- this type and the signal after it has been added for debugging!
-- you can comment this if you dont want to debug!
type instruction_name is (i_None, i_SLL, i_SRL, i_SRA, i_SLLV, i_SRLV, i_SRAV,
i_JR, i_JALR, i_SYSCALL, i_BREAK, i_SYNC, i_MFHI,
i_MTHI, i_MFLO, i_MTLO, i_MULT, i_MULTU, i_DIV, i_DIVU, i_ADD,
i_ADDU, i_SUB, i_SUBU, i_AND, i_OR, i_XOR, i_NOR, i_SLT,
i_SLTU, i_DADDU, i_BLTZAL, i_BLTZ, i_BGEZAL, i_BGEZ,
i_JAL, i_J, i_BEQ, i_BNE, i_BLEZ, i_BGTZ, i_ADDI,
i_ADDIU, i_SLTI, i_SLTIU, i_ANDI, i_ORI, i_XORI, i_LUI,
i_MFC0, i_MTC0, i_SUBI, i_LB, i_LH, i_LWL, i_LW, i_LBU,
i_LHU, i_SB, i_SH, i_SWL, i_SW);
signal instruction : instruction_name;
-- end of debugging block
begin
control_proc: process(opcode, intr_signal)
variable op, func : std_logic_vector(5 downto 0);
variable rs, rt, rd : std_logic_vector(5 downto 0);
variable rtx : std_logic_vector(4 downto 0);
variable imm : std_logic_vector(15 downto 0);
variable alu_function : alu_function_type;
variable shift_function : shift_function_type;
variable mult_function : mult_function_type;
variable a_source : a_source_type;
variable b_source : b_source_type;
variable c_source : c_source_type;
variable pc_source : pc_source_type;
variable branch_function: branch_function_type;
variable mem_source : mem_source_type;
variable is_syscall : std_logic;
begin
alu_function := ALU_NOTHING;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_NULL;
pc_source := FROM_INC4;
branch_function := BRANCH_EQ;
mem_source := MEM_FETCH;
op := opcode(31 downto 26);
rs := '0' & opcode(25 downto 21);
rt := '0' & opcode(20 downto 16);
rtx := opcode(20 downto 16);
rd := '0' & opcode(15 downto 11);
func := opcode(5 downto 0);
imm := opcode(15 downto 0);
is_syscall := '0';
instruction <= i_None;
case op is
when "000000" => --SPECIAL
case func is
when "000000" => --SLL r[rd]=r[rt]<<re;
-- This is overlapping with NOP instruction in which all bits are zero, so opcode is zero and the last 6 bits (funct) are also zero,
-- does this mean that NOP acts as SLL ???
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLL;
when "000010" => --SRL r[rd]=u[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_shift;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000011" => --SRA r[rd]=r[rt]>>re;
a_source := A_FROM_IMM10_6;
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRL;
when "000100" => --SLLV r[rd]=r[rt]<<r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_LEFT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLLV;
when "000110" => --SRLV r[rd]=u[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_UNSIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRLV;
when "000111" => --SRAV r[rd]=r[rt]>>r[rs];
c_source := C_FROM_SHIFT;
shift_function := SHIFT_RIGHT_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SRAV;
when "001000" => --JR s->pc_next=r[rs];
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JR;
when "001001" => --JALR r[rd]=s->pc_next; s->pc_next=r[rs];
c_source := C_FROM_PC_PLUS4;
pc_source := FROM_BRANCH;
alu_function := ALU_ADD;
branch_function := BRANCH_YES;
--Comment the next line if you dont want to debug!
instruction <= i_JALR;
--when "001010" => --MOVZ if(!r[rt]) r[rd]=r[rs]; /*IV*/
--when "001011" => --MOVN if(r[rt]) r[rd]=r[rs]; /*IV*/
when "001100" => --SYSCALL
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_SYSCALL;
when "001101" => --BREAK s->wakeup=1;
is_syscall := '1';
--Comment the next line if you dont want to debug!
instruction <= i_BREAK;
--when "001111" => --SYNC s->wakeup=1;
when "010000" => --MFHI r[rd]=s->hi;
c_source := C_FROM_MULT;
mult_function := MULT_READ_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MFHI;
when "010001" => --MTHI s->hi=r[rs];
mult_function := MULT_WRITE_HI;
--Comment the next line if you dont want to debug!
instruction <= i_MTHI;
when "010010" => --MFLO r[rd]=s->lo;
c_source := C_FROM_MULT;
mult_function := MULT_READ_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MFLO;
when "010011" => --MTLO s->lo=r[rs];
mult_function := MULT_WRITE_LO;
--Comment the next line if you dont want to debug!
instruction <= i_MTLO;
when "011000" => --MULT s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_SIGNED_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULT;
when "011001" => --MULTU s->lo=r[rs]*r[rt]; s->hi=0;
mult_function := MULT_MULT;
--Comment the next line if you dont want to debug!
instruction <= i_MULTU;
when "011010" => --DIV s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_SIGNED_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIV;
when "011011" => --DIVU s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt];
mult_function := MULT_DIVIDE;
--Comment the next line if you dont want to debug!
instruction <= i_DIVU;
when "100000" => --ADD r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADD;
when "100001" => --ADDU r[rd]=r[rs]+r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDU;
when "100010" => --SUB r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUB;
when "100011" => --SUBU r[rd]=r[rs]-r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBU;
when "100100" => --AND r[rd]=r[rs]&r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_AND;
when "100101" => --OR r[rd]=r[rs]|r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_OR;
when "100110" => --XOR r[rd]=r[rs]^r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XOR;
when "100111" => --NOR r[rd]=~(r[rs]|r[rt]);
c_source := C_FROM_ALU;
alu_function := ALU_NOR;
--Comment the next line if you dont want to debug!
instruction <= i_NOR;
when "101010" => --SLT r[rd]=r[rs]<r[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLT;
when "101011" => --SLTU r[rd]=u[rs]<u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTU;
when "101101" => --DADDU r[rd]=r[rs]+u[rt];
c_source := C_FROM_ALU;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_DADDU;
--when "110001" => --TGEU
--when "110010" => --TLT
--when "110011" => --TLTU
--when "110100" => --TEQ
--when "110110" => --TNE
when others =>
end case;
when "000001" => --REGIMM
rt := "000000";
rd := "011111";
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--if(test) pc=pc+imm*4
case rtx is
when "10000" => --BLTZAL r[31]=s->pc_next; branch=r[rs]<0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZAL;
when "00000" => --BLTZ branch=r[rs]<0;
branch_function := BRANCH_LTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLTZ;
when "10001" => --BGEZAL r[31]=s->pc_next; branch=r[rs]>=0;
c_source := C_FROM_PC_PLUS4;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZAL;
when "00001" => --BGEZ branch=r[rs]>=0;
branch_function := BRANCH_GEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGEZ;
--when "10010" => --BLTZALL r[31]=s->pc_next; lbranch=r[rs]<0;
--when "00010" => --BLTZL lbranch=r[rs]<0;
--when "10011" => --BGEZALL r[31]=s->pc_next; lbranch=r[rs]>=0;
--when "00011" => --BGEZL lbranch=r[rs]>=0;
when others =>
end case;
when "000011" => --JAL r[31]=s->pc_next; s->pc_next=(s->pc&0xf0000000)|target;
c_source := C_FROM_PC_PLUS4;
rd := "011111";
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_JAL;
when "000010" => --J s->pc_next=(s->pc&0xf0000000)|target;
pc_source := FROM_OPCODE25_0;
--Comment the next line if you dont want to debug!
instruction <= i_J;
when "000100" => --BEQ branch=r[rs]==r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_EQ;
--Comment the next line if you dont want to debug!
instruction <= i_BEQ;
when "000101" => --BNE branch=r[rs]!=r[rt];
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_NE;
--Comment the next line if you dont want to debug!
instruction <= i_BNE;
when "000110" => --BLEZ branch=r[rs]<=0;
a_source := A_FROM_PC;
b_source := b_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_LEZ;
--Comment the next line if you dont want to debug!
instruction <= i_BLEZ;
when "000111" => --BGTZ branch=r[rs]>0;
a_source := A_FROM_PC;
b_source := B_FROM_IMMX4;
alu_function := ALU_ADD;
pc_source := FROM_BRANCH;
branch_function := BRANCH_GTZ;
--Comment the next line if you dont want to debug!
instruction <= i_BGTZ;
when "001000" => --ADDI r[rt]=r[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDI;
when "001001" => --ADDIU u[rt]=u[rs]+(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_ADD;
--Comment the next line if you dont want to debug!
instruction <= i_ADDIU;
when "001010" => --SLTI r[rt]=r[rs]<(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN_SIGNED;
--Comment the next line if you dont want to debug!
instruction <= i_SLTI;
when "001011" => --SLTIU u[rt]=u[rs]<(unsigned long)(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_LESS_THAN;
--Comment the next line if you dont want to debug!
instruction <= i_SLTIU;
when "001100" => --ANDI r[rt]=r[rs]&imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_AND;
--Comment the next line if you dont want to debug!
instruction <= i_ANDI;
when "001101" => --ORI r[rt]=r[rs]|imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_OR;
--Comment the next line if you dont want to debug!
instruction <= i_ORI;
when "001110" => --XORI r[rt]=r[rs]^imm;
b_source := B_FROM_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_XOR;
--Comment the next line if you dont want to debug!
instruction <= i_XORI;
when "001111" => --LUI r[rt]=(imm<<16);
c_source := C_FROM_IMM_SHIFT16;
rd := rt;
--Comment the next line if you dont want to debug!
instruction <= i_LUI;
when "010000" => --COP0
alu_function := ALU_OR;
c_source := C_FROM_ALU;
if opcode(23) = '0' then --move from CP0
rs := '1' & opcode(15 downto 11);
rt := "000000";
rd := '0' & opcode(20 downto 16);
--Comment the next line if you dont want to debug!
instruction <= i_MFC0;
else --move to CP0
rs := "000000";
rd(5) := '1';
pc_source := FROM_BRANCH; --delay possible interrupt
branch_function := BRANCH_NO;
--Comment the next line if you dont want to debug!
instruction <= i_MTC0;
end if;
--when "010001" => --COP1
--when "010010" => --COP2
--when "010011" => --COP3
--when "010100" => --BEQL lbranch=r[rs]==r[rt];
--when "010101" => --BNEL lbranch=r[rs]!=r[rt];
--when "010110" => --BLEZL lbranch=r[rs]<=0;
--when "010111" => --BGTZL lbranch=r[rs]>0;
when "011010" => -- SUBI r[rt]=r[rs]-(short)imm;
b_source := B_FROM_SIGNED_IMM;
c_source := C_FROM_ALU;
rd := rt;
alu_function := ALU_SUBTRACT;
--Comment the next line if you dont want to debug!
instruction <= i_SUBI;
when "100000" => --LB r[rt]=*(signed char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LB;
when "100001" => --LH r[rt]=*(signed short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16S; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LH;
when "100010" => --LWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LWL;
when "100011" => --LW r[rt]=*(long*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ32;
--Comment the next line if you dont want to debug!
instruction <= i_LW;
when "100100" => --LBU r[rt]=*(unsigned char*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LBU;
when "100101" => --LHU r[rt]=*(unsigned short*)ptr;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
rd := rt;
c_source := C_FROM_MEMORY;
mem_source := MEM_READ16; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_LHU;
--when "100110" => --LWR //Not Implemented
when "101000" => --SB *(char*)ptr=(char)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE8; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SB;
when "101001" => --SH *(short*)ptr=(short)r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE16;
--Comment the next line if you dont want to debug!
instruction <= i_SH;
when "101010" => --SWL //Not Implemented
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SWL;
when "101011" => --SW *(long*)ptr=r[rt];
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_SIGNED_IMM;
alu_function := ALU_ADD;
mem_source := MEM_WRITE32; --address=(short)imm+r[rs];
--Comment the next line if you dont want to debug!
instruction <= i_SW;
--when "101110" => --SWR //Not Implemented
--when "101111" => --CACHE
--when "110000" => --LL r[rt]=*(long*)ptr;
--when "110001" => --LWC1
--when "110010" => --LWC2
--when "110011" => --LWC3
--when "110101" => --LDC1
--when "110110" => --LDC2
--when "110111" => --LDC3
--when "111000" => --SC *(long*)ptr=r[rt]; r[rt]=1;
--when "111001" => --SWC1
--when "111010" => --SWC2
--when "111011" => --SWC3
--when "111101" => --SDC1
--when "111110" => --SDC2
--when "111111" => --SDC3
when others =>
end case;
if c_source = C_FROM_NULL then
rd := "000000";
end if;
if intr_signal = '1' or is_syscall = '1' then
rs := "111111"; --interrupt vector
rt := "000000";
rd := "101110"; --save PC in EPC
alu_function := ALU_OR;
shift_function := SHIFT_NOTHING;
mult_function := MULT_NOTHING;
branch_function := BRANCH_YES;
a_source := A_FROM_REG_SOURCE;
b_source := B_FROM_REG_TARGET;
c_source := C_FROM_PC;
pc_source := FROM_LBRANCH; -- "11"
mem_source := MEM_FETCH;
exception_out <= '1';
else
exception_out <= '0';
end if;
rs_index <= rs;
rt_index <= rt;
rd_index <= rd;
imm_out <= imm;
alu_func <= alu_function;
shift_func <= shift_function;
mult_func <= mult_function;
branch_func <= branch_function;
a_source_out <= a_source;
b_source_out <= b_source;
c_source_out <= c_source;
pc_source_out <= pc_source;
mem_source_out <= mem_source;
end process;
end; --logic
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/arbiter_out.vhd
|
12
|
4006
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/arbiter_out.vhd
|
12
|
4006
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity arbiter_out is
port (
reset: in std_logic;
clk: in std_logic;
X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules
credit: in std_logic_vector(1 downto 0);
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic -- Grants given to LBDR requests (encoded as one-hot)
);
end;
architecture behavior of arbiter_out is
TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SIGNAL state, state_in : STATE_TYPE := IDLE;
begin
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
case state is
when IDLE =>
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and X_N_Y = '1'then
grant_Y_N <= '1';
end if;
if X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and X_E_Y = '1'then
grant_Y_E <= '1';
end if;
if X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and X_W_Y = '1'then
grant_Y_W <= '1';
end if;
if X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and X_S_Y = '1' then
grant_Y_S <= '1';
end if;
if X_S_Y = '1' then
state_in <= South;
elsif X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others =>
if credit /= "00" and X_L_Y = '1' then
grant_Y_L <= '1';
end if;
if X_L_Y = '1' then
state_in <= Local;
elsif X_N_Y ='1' then
state_in <= North;
elsif X_E_Y = '1' then
state_in <= East;
elsif X_W_Y = '1' then
state_in <= West;
elsif X_S_Y = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/customized_routers/Router_32_bit_NE_credit_based_packet_drop_classifier_SHMU_will_full_set_of_checkers_with_FI.vhd
|
3
|
305650
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_NE_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
link_faults_async: out std_logic_vector(4 downto 0);
turn_faults_async: out std_logic_vector(19 downto 0)
);
end router_NE_credit_based_PD_C_SHMU;
architecture behavior of router_NE_credit_based_PD_C_SHMU is
-------------------------------
-- Added because of Checkers --
-------------------------------
--signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?!
--signal shift_parallel_data: std_logic_vector(19 downto 0);
-------------------------------
-------------------------------
signal FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_WW, Req_SW, Req_LW: std_logic;
signal Req_WS, Req_SS, Req_LS: std_logic;
signal Req_WL, Req_SL, Req_LL: std_logic;
signal empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
-- Signals related to link fault classification modules
signal healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
-- Signals related to Control part checkers fault classification modules
signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic;
signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic;
signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic;
signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic;
signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic;
signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic;
-- Signals needed for control part checkers
-- Signals needed for LBDR packet drop checkers
-- West
signal W_err_header_empty_Requests_FF_Requests_in,
W_err_tail_Requests_in_all_zero,
W_err_tail_empty_Requests_FF_Requests_in,
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
W_err_grants_onehot,
W_err_grants_mismatch,
W_err_header_tail_Requests_FF_Requests_in,
W_err_dst_addr_cur_addr_N1, W_err_dst_addr_cur_addr_not_N1, W_err_dst_addr_cur_addr_E1, W_err_dst_addr_cur_addr_not_E1,
W_err_dst_addr_cur_addr_W1, W_err_dst_addr_cur_addr_not_W1, W_err_dst_addr_cur_addr_S1, W_err_dst_addr_cur_addr_not_S1, W_err_dst_addr_cur_addr_Req_L_in,
W_err_dst_addr_cur_addr_not_Req_L_in,
W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--W_err_header_not_empty_Req_L_in, -- added according to new design
W_err_header_not_empty_Req_N_in, W_err_header_not_empty_Req_E_in, W_err_header_not_empty_Req_W_in, W_err_header_not_empty_Req_S_in,
W_err_header_empty_packet_drop_in_packet_drop_equal,
W_err_tail_not_empty_packet_drop_not_packet_drop_in,
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
W_err_packet_drop_order,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- South
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_tail_empty_Requests_FF_Requests_in,
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
S_err_grants_onehot,
S_err_grants_mismatch,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1, S_err_dst_addr_cur_addr_not_N1, S_err_dst_addr_cur_addr_E1, S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1, S_err_dst_addr_cur_addr_not_W1, S_err_dst_addr_cur_addr_S1, S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--S_err_header_not_empty_Req_L_in, -- added according to new design
S_err_header_not_empty_Req_N_in, S_err_header_not_empty_Req_E_in, S_err_header_not_empty_Req_W_in, S_err_header_not_empty_Req_S_in,
S_err_header_empty_packet_drop_in_packet_drop_equal,
S_err_tail_not_empty_packet_drop_not_packet_drop_in,
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
S_err_packet_drop_order,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- Local
L_err_header_empty_Requests_FF_Requests_in, L_err_tail_Requests_in_all_zero, L_err_tail_empty_Requests_FF_Requests_in,
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, L_err_grants_onehot, L_err_grants_mismatch,
L_err_header_tail_Requests_FF_Requests_in, L_err_dst_addr_cur_addr_N1, L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1, L_err_dst_addr_cur_addr_not_E1, L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1, L_err_dst_addr_cur_addr_S1, L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_Req_L_in, L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--L_err_header_not_empty_Req_L_in, -- added according to new design
L_err_header_not_empty_Req_N_in, L_err_header_not_empty_Req_E_in, L_err_header_not_empty_Req_W_in, L_err_header_not_empty_Req_S_in,
L_err_header_empty_packet_drop_in_packet_drop_equal,
L_err_tail_not_empty_packet_drop_not_packet_drop_in,
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
L_err_packet_drop_order,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- Signals needed for FIFO packet drop with fault classifier support checkers
-- West
-- Functional checkers
signal W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot,
-- Structural checkers
W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty,
W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment,
W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
W_err_fake_credit_read_en_fake_credit_counter_in_increment,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
W_err_fake_credit_read_en_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
W_err_state_out_Idle_not_fault_out_not_fake_credit,
W_err_state_out_Idle_not_fault_out_not_fault_info_in,
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Idle_fault_out_fake_credit,
W_err_state_out_Idle_fault_out_state_in_Packet_drop,
W_err_state_out_Idle_fault_out_fault_info_in,
W_err_state_out_Idle_fault_out_faulty_packet_in,
W_err_state_out_Idle_not_health_info,
W_err_state_out_Idle_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
W_err_state_out_Body_flit_valid_in_not_health_info,
W_err_state_out_Body_flit_not_fake_credit,
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
W_err_state_out_Tail_flit_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
W_err_fault_info_fault_info_out_equal,
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- South
-- Functional checkers
S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot,
-- Structural checkers
S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment,
S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
S_err_fake_credit_read_en_fake_credit_counter_in_increment,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
S_err_fake_credit_read_en_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
S_err_state_out_Idle_not_fault_out_not_fake_credit, S_err_state_out_Idle_not_fault_out_not_fault_info_in,
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Idle_fault_out_fake_credit,
S_err_state_out_Idle_fault_out_state_in_Packet_drop, S_err_state_out_Idle_fault_out_fault_info_in, S_err_state_out_Idle_fault_out_faulty_packet_in,
S_err_state_out_Idle_not_health_info, S_err_state_out_Idle_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
S_err_state_out_Body_flit_valid_in_not_health_info,
S_err_state_out_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
S_err_state_out_Tail_flit_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
S_err_fault_info_fault_info_out_equal,
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- Local
-- Functional checkers
L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot,
-- Structural checkers
L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1,
L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
L_err_fake_credit_read_en_fake_credit_counter_in_increment,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
L_err_fake_credit_read_en_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
L_err_state_out_Idle_not_fault_out_not_fake_credit,
L_err_state_out_Idle_not_fault_out_not_fault_info_in,
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Idle_fault_out_fake_credit,
L_err_state_out_Idle_fault_out_state_in_Packet_drop,
L_err_state_out_Idle_fault_out_fault_info_in,
L_err_state_out_Idle_fault_out_faulty_packet_in,
L_err_state_out_Idle_not_health_info,
L_err_state_out_Idle_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
L_err_state_out_Body_flit_valid_in_not_health_info,
L_err_state_out_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
L_err_state_out_Tail_flit_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
L_err_fault_info_fault_info_out_equal,
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for Allocator unit
-- Allocator logic checker outputs
-- Might need to be changed ?!
signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match: std_logic;
-- Allocator credit_counter logic checker outputs
signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_in Checker signals (part of allocator unit)
-- North Arbiter_in checker outputs
signal N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W,
N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S,
N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L,
N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N,
N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E,
N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W,
E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S,
E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L,
E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N,
E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E,
E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W,
W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S,
W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L,
W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N,
W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E,
W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W,
S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S,
S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L,
S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N,
S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E,
S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_arbiter_state_in_onehot,
S_err_no_request_grants,
S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E,
L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S,
L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W,
L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L,
L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S,
L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N,
L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L,
L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E,
L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N,
L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W,
L_err_Local_Req_S, L_err_Local_grant_S,
L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_out Checker signals (part of allocator unit)
-- North Arbiter_out checker outputs
signal N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : std_logic;
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---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for grouping checkers to model turn/path faults
signal W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic;
signal W2S_turn_fault, S2W_turn_fault : std_logic;
signal not_W2S_turn_fault, not_S2W_turn_fault : std_logic;
signal L2W_fault, L2S_fault, W2L_fault, S2L_fault : std_logic;
signal not_L2W_fault, not_L2S_fault, not_W2L_fault, not_S2L_fault : std_logic;
-- Just used temporarily for debugging purposes!
signal W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic;
signal Allocator_checkers_ORed : std_logic;
--signal turn_faults_sig : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------------------------
-- Added because of the chain we make for sending faulty values ---------------------------------
-- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ----------------------------
-- then L, N, E, W and S Arbiter_in, --------------------
-- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! --
-------------------------------------------------------------------------------------------------
--TODO: the chains should be fixed!
--Fixed!
signal fault_DO_serial_L_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic;
signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_W_LBDR: std_logic;
signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic;
------------------------------------------------------------------
------------------------------------------------------------------
begin
not_W2S_turn_fault <= not W2S_turn_fault;
not_S2W_turn_fault <= not S2W_turn_fault;
not_L2W_fault <= not L2W_fault;
not_L2S_fault <= not L2S_fault;
not_W2L_fault <= not W2L_fault;
not_S2L_fault <= not S2L_fault;
-- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers
-- corresponding to that input are ORed together.
-- West
W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or
W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or
W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or
W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or
W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or
W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or
W_err_read_en_mismatch1 or
W_err_fake_credit_read_en_fake_credit_counter_in_increment or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
W_err_fake_credit_read_en_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
W_err_state_out_Idle_not_fault_out_not_fake_credit or
W_err_state_out_Idle_not_fault_out_not_fault_info_in or
W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Idle_fault_out_fake_credit or
W_err_state_out_Idle_fault_out_state_in_Packet_drop or
W_err_state_out_Idle_fault_out_fault_info_in or
W_err_state_out_Idle_fault_out_faulty_packet_in or
W_err_state_out_Idle_not_health_info or
W_err_state_out_Idle_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
W_err_state_out_Body_flit_valid_in_not_health_info or
W_err_state_out_Body_flit_not_fake_credit or
W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
W_err_state_out_Tail_flit_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
W_err_fault_info_fault_info_out_equal or
W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- South
S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or
S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or
S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or
S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or
S_err_read_en_mismatch1 or
S_err_fake_credit_read_en_fake_credit_counter_in_increment or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
S_err_fake_credit_read_en_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
S_err_state_out_Idle_not_fault_out_not_fake_credit or
S_err_state_out_Idle_not_fault_out_not_fault_info_in or
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Idle_fault_out_fake_credit or
S_err_state_out_Idle_fault_out_state_in_Packet_drop or
S_err_state_out_Idle_fault_out_fault_info_in or
S_err_state_out_Idle_fault_out_faulty_packet_in or
S_err_state_out_Idle_not_health_info or
S_err_state_out_Idle_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
S_err_state_out_Body_flit_valid_in_not_health_info or
S_err_state_out_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
S_err_state_out_Tail_flit_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
S_err_fault_info_fault_info_out_equal or
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- Local
L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or
L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or
L_err_write_en_write_pointer or L_err_not_write_en_write_pointer or L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or L_err_read_pointer_write_pointer_not_full or L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or L_err_read_pointer_not_increment or
L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or
L_err_read_en_mismatch or L_err_read_en_mismatch1 or
L_err_fake_credit_read_en_fake_credit_counter_in_increment or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
L_err_fake_credit_read_en_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
L_err_state_out_Idle_not_fault_out_not_fake_credit or
L_err_state_out_Idle_not_fault_out_not_fault_info_in or
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Idle_fault_out_fake_credit or
L_err_state_out_Idle_fault_out_state_in_Packet_drop or
L_err_state_out_Idle_fault_out_fault_info_in or
L_err_state_out_Idle_fault_out_faulty_packet_in or
L_err_state_out_Idle_not_health_info or
L_err_state_out_Idle_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
L_err_state_out_Body_flit_valid_in_not_health_info or
L_err_state_out_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
L_err_state_out_Tail_flit_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
L_err_fault_info_fault_info_out_equal or
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
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-- Just for debugging purposes of the checkers!
-- LBDR checker outputs ORed
-- West
-- Routing part checkers
W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or W_err_dst_addr_cur_addr_W1 or
W_err_dst_addr_cur_addr_not_W1 or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--W_err_header_not_empty_Req_L_in or -- added according to new design
W_err_header_not_empty_Req_N_in or W_err_header_not_empty_Req_E_in or W_err_header_not_empty_Req_W_in or W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
-- Cx_Reconf checkers
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- South
-- Routing part checkers
S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_dst_addr_cur_addr_S1 or S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--S_err_header_not_empty_Req_L_in or -- added according to new design
S_err_header_not_empty_Req_N_in or S_err_header_not_empty_Req_E_in or S_err_header_not_empty_Req_W_in or S_err_header_not_empty_Req_S_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or
-- Cx_Reconf checkers
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- Local
-- Routing part checkers
L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_dst_addr_cur_addr_Req_L_in or
L_err_dst_addr_cur_addr_not_Req_L_in or L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--L_err_header_not_empty_Req_L_in or -- added according to new design
L_err_header_not_empty_Req_N_in or L_err_header_not_empty_Req_E_in or L_err_header_not_empty_Req_W_in or L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
-- Cx_Reconf checkers
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
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-- Allocator checker outputs ORed !
-- Allocator logic checker outputs
Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or
err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or
err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or
err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or
err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or
err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or
err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or
err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or
err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or
err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or
err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or
err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or
err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or
err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or
err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or
err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or
err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or
err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal or
N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or
N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or
N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or
N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or
N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or
N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or
N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or
N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or
N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or
N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or
N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or
N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or
N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or
N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or
N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or
N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or
N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal or
E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or
E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or
E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or
E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or
E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or
E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or
E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or
E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or
E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or
E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or
E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or
E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or
E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or
E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or
E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or
E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal or
W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or
W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or
W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or
W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or
W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or
W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or
W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or
W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or
W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or
W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or
W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or
W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or
W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or
W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or
W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal or
S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or
S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or
S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or
S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or
S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or
S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or
S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or
S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or
S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or
S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or
S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or
S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or
S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or
S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or
S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal or
L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or
L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or
L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or
L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or
L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or
L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or
L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or
L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or
L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or
L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or
L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or
L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or
L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or
L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_IDLE_req_X_N or
N_err_North_req_X_N or
N_err_North_credit_not_zero_req_X_N_grant_N or
N_err_North_credit_zero_or_not_req_X_N_not_grant_N or
N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or
N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or
N_err_West_credit_zero_or_not_req_X_W_not_grant_W or
N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or
N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_East_req_X_W or N_err_West_req_X_S or N_err_South_req_X_L or N_err_Local_req_X_N or
N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_East_req_X_S or N_err_West_req_X_L or N_err_South_req_X_N or N_err_Local_req_X_E or
N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_East_req_X_L or N_err_West_req_X_N or N_err_South_req_X_E or N_err_Local_req_X_W or
N_err_IDLE_req_X_L or N_err_North_req_X_L or N_err_East_req_X_N or N_err_West_req_X_E or N_err_South_req_X_W or N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or N_err_state_North_Invalid_Grant or N_err_state_East_Invalid_Grant or N_err_state_West_Invalid_Grant or
N_err_state_South_Invalid_Grant or N_err_state_Local_Invalid_Grant or N_err_Grants_onehot_or_all_zero or
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_IDLE_req_X_N or
E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or
E_err_North_credit_zero_or_not_req_X_N_not_grant_N or
E_err_East_req_X_E or
E_err_East_credit_not_zero_req_X_E_grant_E or
E_err_East_credit_zero_or_not_req_X_E_not_grant_E or
E_err_West_req_X_W or
E_err_West_credit_not_zero_req_X_W_grant_W or
E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or
E_err_South_credit_zero_or_not_req_X_S_not_grant_S or
E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or E_err_Local_req_X_N or
E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or E_err_Local_req_X_E or
E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or E_err_Local_req_X_W or
E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or E_err_Local_req_X_S or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or
E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or
E_err_Grants_onehot_or_all_zero or
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or
W_err_East_credit_zero_or_not_req_X_E_not_grant_E or
W_err_West_req_X_W or
W_err_West_credit_not_zero_req_X_W_grant_W or
W_err_West_credit_zero_or_not_req_X_W_not_grant_W or
W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or
W_err_South_credit_zero_or_not_req_X_S_not_grant_S or
W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or W_err_Local_req_X_N or
W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or W_err_Local_req_X_E or
W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or W_err_Local_req_X_W or
W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or W_err_Local_req_X_S or
W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or
W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or
W_err_Grants_onehot_or_all_zero or
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_IDLE_req_X_N or
S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or
S_err_North_credit_zero_or_not_req_X_N_not_grant_N or
S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or
S_err_East_credit_zero_or_not_req_X_E_not_grant_E or
S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or
S_err_West_credit_zero_or_not_req_X_W_not_grant_W or
S_err_South_req_X_S or
S_err_South_credit_not_zero_req_X_S_grant_S or
S_err_South_credit_zero_or_not_req_X_S_not_grant_S or
S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or
S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or
S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or
S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or
S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or
S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or
S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or
S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or
S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or
S_err_Grants_onehot_or_all_zero or
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or
L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or
L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_Local_req_X_L or L_err_Local_credit_not_zero_req_X_L_grant_L or
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or L_err_Local_req_X_N or
L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or L_err_Local_req_X_E or
L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or L_err_Local_req_X_W or
L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or L_err_Local_req_X_S or
L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or
L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or
L_err_Grants_onehot_or_all_zero;
------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------
-- Turn fault checkers
-- FIFO
W2S_turn_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or
W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or
W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2W_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
S_err_header_not_empty_Req_W_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or
W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- Checkers for Paths/turns from/to Local port
-- FIFO
L2W_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or
W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or
err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal;
-- FIFO
L2S_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or
L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or
S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
W2L_fault <= W_FIFO_checkers_ORed or
-- LBDR
W_err_header_empty_Requests_FF_Requests_in or
W_err_tail_Requests_in_all_zero or
W_err_tail_empty_Requests_FF_Requests_in or
W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
W_err_grants_onehot or
W_err_grants_mismatch or
W_err_header_tail_Requests_FF_Requests_in or
W_err_dst_addr_cur_addr_Req_L_in or
W_err_dst_addr_cur_addr_not_Req_L_in or
W_err_header_not_empty_faulty_drop_packet_in or
W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
W_err_header_not_empty_faulty_Req_in_all_zero or
--W_err_header_not_empty_Req_L_in or
W_err_header_empty_packet_drop_in_packet_drop_equal or
W_err_tail_not_empty_packet_drop_not_packet_drop_in or
W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
W_err_packet_drop_order or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or
W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or
W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or
L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
S2L_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or --S_err_header_not_empty_Req_L_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or
S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or
S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or
L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
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-- Link faults and turn faults
-- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits
-- N2E, N2W, E2N, E2S,
-- W2N, W2S, S2E, S2W,
-- N2S, S2N, E2W, W2E,
-- L2N, L2E, L2W, L2S,
-- N2L, E2L, W2L, S2L
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-- Taking classified fault information to output
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turn_faults <= '0' & '0' & '0' & '0' &
'0' & faulty_W2S_turn_fault & '0' & faulty_S2W_turn_fault &
'0' & '0' & '0' & '0' &
'0' & '0' & faulty_L2W_fault & faulty_L2S_fault &
'0' & '0' & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults
link_faults <= '0' & '0' & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; -- sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
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-- Taking non-classified fault information to output
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turn_faults_async <= '0' & '0' & '0' & '0' &
'0' & W2S_turn_fault & '0' & S2W_turn_fault &
'0' & '0' & '0' & '0' &
'0' & '0' & L2W_fault & L2S_fault &
'0' & '0' & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults
link_faults_async <= '0' & '0' & faulty_packet_W & faulty_packet_S & faulty_packet_L; -- faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
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Faulty_W_out <= sig_Faulty_W_out; --sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out; --sig_Faulty_S_out;
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-- all the counter_threshold modules
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
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-- all the Checker Counter Threshold modules
-- Turn faults
CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault,
Healthy => Healthy_W2S_turn_fault, Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault);
CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault,
Healthy => Healthy_S2W_turn_fault, Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault);
CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault,
Healthy => Healthy_L2W_fault, Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault);
CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault,
Healthy => Healthy_L2S_fault, Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault);
-- Local port related faults (to/from local port)
CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault,
Healthy => Healthy_W2L_fault, Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault);
CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault,
Healthy => Healthy_S2L_fault, Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault);
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FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => '0', read_en_E =>'0', read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en,
err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => W_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => W_err_write_en_write_pointer,
err_not_write_en_write_pointer => W_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full,
err_read_pointer_increment => W_err_read_pointer_increment,
err_read_pointer_not_increment => W_err_read_pointer_not_increment,
err_write_en => W_err_write_en,
err_not_write_en => W_err_not_write_en,
err_not_write_en1 => W_err_not_write_en1,
err_not_write_en2 => W_err_not_write_en2,
err_read_en_mismatch => W_err_read_en_mismatch,
err_read_en_mismatch1 => W_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => '0', read_en_E =>'0', read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR,
-- Checker outputs
-- Functional checkers
err_empty_full => S_err_empty_full,
err_empty_read_en => S_err_empty_read_en,
err_full_write_en => S_err_full_write_en,
err_state_in_onehot => S_err_state_in_onehot,
err_read_pointer_in_onehot => S_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => S_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_write_en => S_err_not_write_en,
err_not_write_en1 => S_err_not_write_en1,
err_not_write_en2 => S_err_not_write_en2,
err_read_en_mismatch => S_err_read_en_mismatch,
err_read_en_mismatch1 => S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => '0', read_en_E =>'0', read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_W_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en,
err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => L_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_write_en => L_err_not_write_en,
err_not_write_en1 => L_err_not_write_en1,
err_not_write_en2 => L_err_not_write_en2,
err_read_en_mismatch => L_err_read_en_mismatch,
err_read_en_mismatch1 => L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
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parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
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LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => '0', Faulty_C_E => '0', Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W,
grant_N => '0', grant_E =>'0', grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> open, Req_E=>open, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => W_err_grants_onehot,
err_grants_mismatch => W_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => W_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => '0', Faulty_C_E => '0', Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S,
grant_N => '0', grant_E =>'0', grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> open, Req_E=>open, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => S_err_grants_onehot,
err_grants_mismatch => S_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => S_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => '0', Faulty_C_E => '0', Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L,
grant_N => '0', grant_E =>'0', grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> open, Req_E=>open, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_W_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => L_err_grants_onehot,
err_grants_mismatch => L_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => L_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
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------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => '0', credit_in_E => '0', credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => '0', req_N_W => '0', req_N_S => '0', req_N_L => '0',
req_E_N => '0', req_E_E => '0', req_E_W => '0', req_E_S => '0', req_E_L => '0',
req_W_N => '0', req_W_E => '0', req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => '0', req_S_E => '0', req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => '0', req_L_E => '0', req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => '0', empty_E => '0', empty_W => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => open, valid_E => open, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => open, grant_N_E => open, grant_N_W => open, grant_N_S => open, grant_N_L => open,
grant_E_N => open, grant_E_E => open, grant_E_W => open, grant_E_S => open, grant_E_L => open,
grant_W_N => open, grant_W_E => open, grant_W_W => open, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => open, grant_S_E => open, grant_S_W => Grant_SW, grant_S_S => open, grant_S_L => Grant_SL,
grant_L_N => open, grant_L_E => open, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => open,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO,
-- Checker outputs
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N ,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N ,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E ,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E ,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W ,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W ,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S ,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S ,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L ,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L ,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N ,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N ,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E ,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E ,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W ,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W ,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S ,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S ,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L ,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L ,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N ,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N ,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E ,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E ,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W ,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W ,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S ,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S ,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L ,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L ,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N ,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N ,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E ,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E ,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W ,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W ,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S ,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S ,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L ,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L ,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N ,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N ,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E ,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E ,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W ,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W ,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S ,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S ,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L ,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L ,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match ,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment ,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change ,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement ,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change ,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment ,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change ,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement ,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change ,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment ,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change ,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement ,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change ,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment ,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change ,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement ,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change ,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment ,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change ,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement ,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change ,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
-- North Arbiter_in Checker outputs
N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N,
N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E,
N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S,
N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L,
N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E,
N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W,
N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L,
N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N,
N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W,
N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S,
N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N,
N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E,
N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S,
N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L,
N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E,
N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W,
N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L,
N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N,
N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W,
N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S,
N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants,
N_err_request_no_grants => N_err_request_no_grants,
N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L,
-- East Arbiter_in Checker outputs
E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N,
E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E,
E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S,
E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L,
E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E,
E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W,
E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L,
E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N,
E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W,
E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S,
E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N,
E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E,
E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S,
E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L,
E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E,
E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W,
E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L,
E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N,
E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W,
E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S,
E_err_state_in_onehot => E_err_arbiter_state_in_onehot,
E_err_no_request_grants => E_err_no_request_grants,
E_err_request_no_grants => E_err_request_no_grants,
E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L,
-- West Arbiter_in Checker outputs
W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N,
W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E,
W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S,
W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L,
W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E,
W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W,
W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L,
W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N,
W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W,
W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S,
W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N,
W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E,
W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S,
W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L,
W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E,
W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W,
W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L,
W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N,
W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W,
W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S,
W_err_state_in_onehot => W_err_arbiter_state_in_onehot,
W_err_no_request_grants => W_err_no_request_grants,
W_err_request_no_grants => W_err_request_no_grants,
W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L,
-- South Arbiter_in Checker outputs
S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N,
S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E,
S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S,
S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L,
S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E,
S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W,
S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L,
S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N,
S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W,
S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S,
S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N,
S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E,
S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S,
S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L,
S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E,
S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W,
S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L,
S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N,
S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W,
S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S,
S_err_state_in_onehot => S_err_arbiter_state_in_onehot,
S_err_no_request_grants => S_err_no_request_grants,
S_err_request_no_grants => S_err_request_no_grants,
S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L,
-- Local Arbiter_in Checker outputs
L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N,
L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E,
L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S,
L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L,
L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E,
L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W,
L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L,
L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N,
L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W,
L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S,
L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N,
L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E,
L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S,
L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L,
L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E,
L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W,
L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L,
L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N,
L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W,
L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S,
L_err_state_in_onehot => L_err_arbiter_state_in_onehot,
L_err_no_request_grants => L_err_no_request_grants,
L_err_request_no_grants => L_err_request_no_grants,
L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N => N_err_IDLE_req_X_N,
N_err_North_req_X_N => N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E => N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W => N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S => N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L => N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W,
N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N,
N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S,
N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E,
N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L,
N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W,
N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N,
N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state => N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N => E_err_IDLE_req_X_N,
E_err_North_req_X_N => E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E => E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W => E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S => E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L => E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W,
E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N,
E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S,
E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E,
E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L,
E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W,
E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N,
E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state => E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N => W_err_IDLE_req_X_N,
W_err_North_req_X_N => W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E => W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W => W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S => W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L => W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W,
W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N,
W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S,
W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E,
W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L,
W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W,
W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N,
W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state => W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N => S_err_IDLE_req_X_N,
S_err_North_req_X_N => S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E => S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W => S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S => S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L => S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W,
S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N,
S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S,
S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E,
S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L,
S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W,
S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N,
S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state => S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N => L_err_IDLE_req_X_N,
L_err_North_req_X_N => L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E => L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W => L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S => L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L => L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W,
L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N,
L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S,
L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E,
L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L,
L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W,
L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N,
L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state => L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_W <= '0' & '0' & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= '0' & '0' & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= '0' & '0' & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => (others =>'0'), East_in => (others =>'0'), West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => (others =>'0'), East_in => (others =>'0'), West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => (others =>'0'), East_in => (others =>'0'), West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
end;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/KB_TRANSCEIVER.vhd
|
4
|
3439
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_TRANSCEIVER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KBCLK : INOUT STD_LOGIC;
KBDATA : INOUT STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_TRANSCEIVER;
ARCHITECTURE main OF KB_TRANSCEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
SIGNAL WR_EN : STD_LOGIC;
SIGNAL WR_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0' AND WR_EN = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, HALT_REQ, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT : INTEGER RANGE 0 TO 5000;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
WR_EN <= '0';
ELSIF(CLK'EVENT AND CLK = '1' AND HALT_REQ = '1') THEN
CASE STATE IS
WHEN x"0" =>
IF(COUNT = 5000) THEN
COUNT := 0;
KBCLK <= '1';
STATE := x"1";
END IF;
KBCLK <= '0';
COUNT := COUNT + 1;
WHEN x"1" =>
WR_DATA <= x"EE";
WR_EN <= '1';
STATE := x"1";
WHEN x"2" =>
IF(COUNT = 200) THEN
COUNT := 0;
WR_EN <= '0';
STATE := x"3";
END IF;
COUNT := COUNT + 1;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(KBCLK, WR_EN, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 12;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '1') THEN
CASE STATE IS
WHEN x"0" =>
STATE := x"1";
WHEN x"1" =>
KBDATA <= WR_DATA(ITERATOR);
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
KBDATA <= WR_DATA(0) XOR WR_DATA(1) XOR WR_DATA(2) XOR WR_DATA(3) XOR WR_DATA(4) XOR WR_DATA(5) XOR WR_DATA(6) XOR WR_DATA(7);
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"3";
WHEN OTHERS =>
END CASE;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '0') THEN
STATE := x"0";
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1);
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support.vhd
|
3
|
16854
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info <= '0';
health_info <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
health_info <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' and flit_type = "001" then
fault_info <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers/FIFO_one_hot_credit_based_packet_drop_classifier_support_with_checkers.vhd
|
3
|
61663
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- Checker outputs
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
component FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end component;
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
--alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
--type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
--signal state_out, state_in : state_type;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers: FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N,
read_en_E => read_en_E,
read_en_W => read_en_W,
read_en_S => read_en_S,
read_en_L => read_en_L,
read_pointer => read_pointer,
read_pointer_in => read_pointer_in,
write_pointer => write_pointer,
write_pointer_in => write_pointer_in,
credit_out => credit_in, -- correct ?
empty_out => empty,
full_out => full,
read_en_out => read_en,
write_en_out => write_en,
fake_credit => fake_credit,
fake_credit_counter => fake_credit_counter,
fake_credit_counter_in => fake_credit_counter_in,
state_out => state_out,
state_in => state_in,
fault_info => fault_info_sig, -- connected to signal
fault_info_out => fault_info_out,
fault_info_in => fault_info_in,
health_info => health_info_sig, -- connected to signal
faulty_packet_out => faulty_packet_out,
faulty_packet_in => faulty_packet_in,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3),
fault_out => fault_out,
write_fake_flit => write_fake_flit,
-- Functional checkers
err_empty_full => err_empty_full,
err_empty_read_en => err_empty_read_en,
err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot,
err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer,
err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment,
err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en,
err_not_write_en => err_not_write_en,
err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2,
err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig;
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/reg_bank.vhd
|
6
|
17338
|
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "TRI_PORT_X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
signal tri_port_ram : ram_type := (others => ZERO);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new,
intr_enable_reg, data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "01110";--"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
-- Added by Behrad
--if interrupt_in = '1' then -- ??
-- intr_enable_reg <= '1';
--end if;
-- Added by Behrad
end if;
intr_enable <= intr_enable_reg;
end process;
--------------------------------------------------------------
---- Pick only ONE of the dual-port RAM implementations below!
--------------------------------------------------------------
-- Option #1
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
tri_port_mem:
if memory_type = "TRI_PORT_X" generate
ram_proc: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) <= reg_dest_new;
end if;
end if;
end process;
end generate; --tri_port_mem
-- Option #2
-- Two dual-port RAMs, each with one read-port and one write-port
dual_port_mem:
if memory_type = "DUAL_PORT_" generate
ram_proc2: process(clk, addr_read1, addr_read2,
addr_write, reg_dest_new, write_enable)
variable dual_port_ram1 : ram_type := (others => ZERO);
variable dual_port_ram2 : ram_type := (others => ZERO);
begin
data_out1 <= dual_port_ram1(conv_integer(addr_read1));
data_out2 <= dual_port_ram2(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
dual_port_ram1(conv_integer(addr_write)) := reg_dest_new;
dual_port_ram2(conv_integer(addr_write)) := reg_dest_new;
end if;
end if;
end process;
end generate; --dual_port_mem
---- Option #3
---- RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port
---- distributed RAM for all Xilinx FPGAs
---- From library UNISIM; use UNISIM.vcomponents.all;
--xilinx_16x1d:
--if memory_type = "XILINX_16X" generate
-- signal data_out1A, data_out1B : std_logic_vector(31 downto 0);
-- signal data_out2A, data_out2B : std_logic_vector(31 downto 0);
-- signal weA, weB : std_logic;
-- signal no_connect : std_logic_vector(127 downto 0);
--begin
-- weA <= write_enable and not addr_write(4); --lower 16 registers
-- weB <= write_enable and addr_write(4); --upper 16 registers
-- reg_loop: for i in 0 to 31 generate
-- begin
-- --Read port 1 lower 16 registers
-- reg_bit1a : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weA, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read1(0), -- Port B address[0] input bit
-- DPRA1 => addr_read1(1), -- Port B address[1] input bit
-- DPRA2 => addr_read1(2), -- Port B address[2] input bit
-- DPRA3 => addr_read1(3), -- Port B address[3] input bit
-- DPO => data_out1A(i), -- Port B 1-bit data output
-- SPO => no_connect(i) -- Port A 1-bit data output
-- );
-- --Read port 1 upper 16 registers
-- reg_bit1b : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weB, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read1(0), -- Port B address[0] input bit
-- DPRA1 => addr_read1(1), -- Port B address[1] input bit
-- DPRA2 => addr_read1(2), -- Port B address[2] input bit
-- DPRA3 => addr_read1(3), -- Port B address[3] input bit
-- DPO => data_out1B(i), -- Port B 1-bit data output
-- SPO => no_connect(32+i) -- Port A 1-bit data output
-- );
-- --Read port 2 lower 16 registers
-- reg_bit2a : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weA, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read2(0), -- Port B address[0] input bit
-- DPRA1 => addr_read2(1), -- Port B address[1] input bit
-- DPRA2 => addr_read2(2), -- Port B address[2] input bit
-- DPRA3 => addr_read2(3), -- Port B address[3] input bit
-- DPO => data_out2A(i), -- Port B 1-bit data output
-- SPO => no_connect(64+i) -- Port A 1-bit data output
-- );
-- --Read port 2 upper 16 registers
-- reg_bit2b : RAM16X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => weB, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read2(0), -- Port B address[0] input bit
-- DPRA1 => addr_read2(1), -- Port B address[1] input bit
-- DPRA2 => addr_read2(2), -- Port B address[2] input bit
-- DPRA3 => addr_read2(3), -- Port B address[3] input bit
-- DPO => data_out2B(i), -- Port B 1-bit data output
-- SPO => no_connect(96+i) -- Port A 1-bit data output
-- );
-- end generate; --reg_loop
-- data_out1 <= data_out1A when addr_read1(4)='0' else data_out1B;
-- data_out2 <= data_out2A when addr_read2(4)='0' else data_out2B;
--end generate; --xilinx_16x1d
---- Option #4
---- RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port
---- distributed RAM for 5-LUT Xilinx FPGAs such as Virtex-5
---- From library UNISIM; use UNISIM.vcomponents.all;
--xilinx_32x1d:
--if memory_type = "XILINX_32X" generate
-- signal no_connect : std_logic_vector(63 downto 0);
--begin
-- reg_loop: for i in 0 to 31 generate
-- begin
-- --Read port 1
-- reg_bit1 : RAM32X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => write_enable, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- A4 => addr_write(4), -- Port A address[4] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read1(0), -- Port B address[0] input bit
-- DPRA1 => addr_read1(1), -- Port B address[1] input bit
-- DPRA2 => addr_read1(2), -- Port B address[2] input bit
-- DPRA3 => addr_read1(3), -- Port B address[3] input bit
-- DPRA4 => addr_read1(4), -- Port B address[4] input bit
-- DPO => data_out1(i), -- Port B 1-bit data output
-- SPO => no_connect(i) -- Port A 1-bit data output
-- );
-- --Read port 2
-- reg_bit2 : RAM32X1D
-- port map (
-- WCLK => clk, -- Port A write clock input
-- WE => write_enable, -- Port A write enable input
-- A0 => addr_write(0), -- Port A address[0] input bit
-- A1 => addr_write(1), -- Port A address[1] input bit
-- A2 => addr_write(2), -- Port A address[2] input bit
-- A3 => addr_write(3), -- Port A address[3] input bit
-- A4 => addr_write(4), -- Port A address[4] input bit
-- D => reg_dest_new(i), -- Port A 1-bit data input
-- DPRA0 => addr_read2(0), -- Port B address[0] input bit
-- DPRA1 => addr_read2(1), -- Port B address[1] input bit
-- DPRA2 => addr_read2(2), -- Port B address[2] input bit
-- DPRA3 => addr_read2(3), -- Port B address[3] input bit
-- DPRA4 => addr_read2(4), -- Port B address[4] input bit
-- DPO => data_out2(i), -- Port B 1-bit data output
-- SPO => no_connect(32+i) -- Port A 1-bit data output
-- );
-- end generate; --reg_loop
--end generate; --xilinx_32x1d
---- Option #5
---- Altera LPM_RAM_DP
--altera_mem:
--if memory_type = "ALTERA_LPM" generate
-- signal clk_delayed : std_logic;
-- signal addr_reg : std_logic_vector(4 downto 0);
-- signal data_reg : std_logic_vector(31 downto 0);
-- signal q1 : std_logic_vector(31 downto 0);
-- signal q2 : std_logic_vector(31 downto 0);
--begin
-- -- Altera dual port RAMs must have the addresses registered (sampled
-- -- at the rising edge). This is very unfortunate.
-- -- Therefore, the dual port RAM read clock must delayed so that
-- -- the read address signal can be sent from the mem_ctrl block.
-- -- This solution also delays the how fast the registers are read so the
-- -- maximum clock speed is cut in half (12.5 MHz instead of 25 MHz).
-- clk_delayed <= not clk; --Could be delayed by 1/4 clock cycle instead
-- dpram_bypass: process(clk, addr_write, reg_dest_new, write_enable)
-- begin
-- if rising_edge(clk) and write_enable = '1' then
-- addr_reg <= addr_write;
-- data_reg <= reg_dest_new;
-- end if;
-- end process; --dpram_bypass
-- -- Bypass dpram if reading what was just written (Altera limitation)
-- data_out1 <= q1 when addr_read1 /= addr_reg else data_reg;
-- data_out2 <= q2 when addr_read2 /= addr_reg else data_reg;
-- lpm_ram_dp_component1 : lpm_ram_dp
-- generic map (
-- LPM_WIDTH => 32,
-- LPM_WIDTHAD => 5,
-- --LPM_NUMWORDS => 0,
-- LPM_INDATA => "REGISTERED",
-- LPM_OUTDATA => "UNREGISTERED",
-- LPM_RDADDRESS_CONTROL => "REGISTERED",
-- LPM_WRADDRESS_CONTROL => "REGISTERED",
-- LPM_FILE => "UNUSED",
-- LPM_TYPE => "LPM_RAM_DP",
-- USE_EAB => "ON",
-- INTENDED_DEVICE_FAMILY => "UNUSED",
-- RDEN_USED => "FALSE",
-- LPM_HINT => "UNUSED")
-- port map (
-- RDCLOCK => clk_delayed,
-- RDCLKEN => '1',
-- RDADDRESS => addr_read1,
-- RDEN => '1',
-- DATA => reg_dest_new,
-- WRADDRESS => addr_write,
-- WREN => write_enable,
-- WRCLOCK => clk,
-- WRCLKEN => '1',
-- Q => q1);
-- lpm_ram_dp_component2 : lpm_ram_dp
-- generic map (
-- LPM_WIDTH => 32,
-- LPM_WIDTHAD => 5,
-- --LPM_NUMWORDS => 0,
-- LPM_INDATA => "REGISTERED",
-- LPM_OUTDATA => "UNREGISTERED",
-- LPM_RDADDRESS_CONTROL => "REGISTERED",
-- LPM_WRADDRESS_CONTROL => "REGISTERED",
-- LPM_FILE => "UNUSED",
-- LPM_TYPE => "LPM_RAM_DP",
-- USE_EAB => "ON",
-- INTENDED_DEVICE_FAMILY => "UNUSED",
-- RDEN_USED => "FALSE",
-- LPM_HINT => "UNUSED")
-- port map (
-- RDCLOCK => clk_delayed,
-- RDCLKEN => '1',
-- RDADDRESS => addr_read2,
-- RDEN => '1',
-- DATA => reg_dest_new,
-- WRADDRESS => addr_write,
-- WREN => write_enable,
-- WRCLOCK => clk,
-- WRCLKEN => '1',
-- Q => q2);
--end generate; --altera_mem
end; --architecture ram_block
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/clk_div.vhd
|
3
|
3768
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY clk_div IS
PORT
(
clock_25Mhz : IN STD_LOGIC;
clock_12Mhz : OUT STD_LOGIC;
clock_6Mhz : OUT STD_LOGIC;
clock_3Mhz : OUT STD_LOGIC;
clock_1MHz : OUT STD_LOGIC;
clock_100KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_1KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_1Hz : OUT STD_LOGIC
);
END clk_div;
ARCHITECTURE a OF clk_div IS
SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int, clock_12Mhz_int, clock_6Mhz_int, clock_3Mhz_int : STD_LOGIC;
BEGIN
PROCESS -- 25 divide by 2
BEGIN
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
clock_12Mhz_int <= not clock_12Mhz_int;
END PROCESS;
PROCESS -- 12 divide by 2
BEGIN
WAIT UNTIL clock_12Mhz_int'EVENT and clock_12Mhz_int = '1';
clock_6Mhz_int <= not clock_6Mhz_int;
END PROCESS;
PROCESS -- 6 divide by 2
BEGIN
WAIT UNTIL clock_6Mhz_int'EVENT and clock_6Mhz_int = '1';
clock_3Mhz_int <= not clock_3Mhz_int;
END PROCESS;
PROCESS
BEGIN
-- Divide by 25
WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
IF count_1Mhz < 24 THEN
count_1Mhz <= count_1Mhz + 1;
ELSE
count_1Mhz <= "00000";
END IF;
IF count_1Mhz < 12 THEN
clock_1Mhz_int <= '0';
ELSE
clock_1Mhz_int <= '1';
END IF;
-- Ripple clocks are used in this code to save prescalar hardware
-- Sync all clock prescalar outputs back to master clock signal
clock_12Mhz <= clock_12Mhz_int;
clock_3Mhz <= clock_3Mhz_int;
clock_1Mhz <= clock_1Mhz_int;
clock_100Khz <= clock_100Khz_int;
clock_10Khz <= clock_10Khz_int;
clock_1Khz <= clock_1Khz_int;
clock_100hz <= clock_100hz_int;
clock_10hz <= clock_10hz_int;
clock_6Mhz <= clock_6Mhz_int;
clock_1hz <= clock_1hz_int;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
IF count_100Khz /= 4 THEN
count_100Khz <= count_100Khz + 1;
ELSE
count_100khz <= "000";
clock_100Khz_int <= NOT clock_100Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
IF count_10Khz /= 4 THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10khz <= "000";
clock_10Khz_int <= NOT clock_10Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
IF count_1Khz /= 4 THEN
count_1Khz <= count_1Khz + 1;
ELSE
count_1khz <= "000";
clock_1Khz_int <= NOT clock_1Khz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
IF count_100hz /= 4 THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= "000";
clock_100hz_int <= NOT clock_100hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
IF count_10hz /= 4 THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= "000";
clock_10hz_int <= NOT clock_10hz_int;
END IF;
END PROCESS;
-- Divide by 10
PROCESS
BEGIN
WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
IF count_1hz /= 4 THEN
count_1hz <= count_1hz + 1;
ELSE
count_1hz <= "000";
clock_1hz_int <= NOT clock_1hz_int;
END IF;
END PROCESS;
END a;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/FIFO_one_hot_credit_based_packet_drop_classifier_support.vhd
|
6
|
17242
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
fault_info <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info_in <= '0';
health_info <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
health_info <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and flit_type = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/IJTAG_files/immortal_sensor_IJTAG_interface.vhd
|
3
|
13320
|
--Copyright (C) 2017 Konstantin Shibin
------------------------------------------------------------
-- File name: immortal_sensor_IJTAG_interface.vhd
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
entity immortal_sensor_IJTAG_interface is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
temperature_control : out std_logic_vector(2 downto 0);
temperature_data : in std_logic_vector(12 downto 0);
iddt_control : out std_logic_vector(2 downto 0);
iddt_data : in std_logic_vector(12 downto 0);
slack_control : out std_logic_vector(2 downto 0);
slack_data : in std_logic_vector(31 downto 0);
voltage_control : out std_logic_vector(2 downto 0);
voltage_data : in std_logic_vector(31 downto 0)
);
end immortal_sensor_IJTAG_interface;
architecture rtl of immortal_sensor_IJTAG_interface is
component SIB_mux_pre_FCX_SELgate is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC); -- From an AND of all C flags in the underlying network segment
end component;
component immortal_slack_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end component;
component immortal_volt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
data : in std_logic_vector(31 downto 0)
);
end component;
component immortal_temp_iddt_monitor_instrument is
port (
-- IJTAG connection
TCK : in std_logic;
RST : in std_logic;
SEL : in std_logic;
SI : in std_logic;
SE : in std_logic;
UE : in std_logic;
CE : in std_logic;
SO : out std_logic;
toF : out std_logic;
toC : out std_logic;
-- Monitor connections
control : out std_logic_vector(2 downto 0);
adc_data : in std_logic_vector(11 downto 0);
adc_drdy : in std_logic
);
end component;
signal SIB_temp_SO, SIB_iddt_SO, SIB_slack_SO, SIB_voltage_SO : std_logic;
signal SIB_temp_toF, SIB_iddt_toF, SIB_slack_toF, SIB_voltage_toF : std_logic;
signal SIB_temp_toC, SIB_iddt_toC, SIB_slack_toC, SIB_voltage_toC : std_logic;
signal SIB_main_toSI, SIB_temp_toSI, SIB_iddt_toSI, SIB_slack_toSI, SIB_voltage_toSI : std_logic;
signal SIB_main_toTCK, SIB_temp_toTCK, SIB_iddt_toTCK, SIB_slack_toTCK, SIB_voltage_toTCK : std_logic;
signal SIB_main_toSEL, SIB_temp_toSEL, SIB_iddt_toSEL, SIB_slack_toSEL, SIB_voltage_toSEL : std_logic;
signal SIB_main_toRST, SIB_temp_toRST, SIB_iddt_toRST, SIB_slack_toRST, SIB_voltage_toRST : std_logic;
signal SIB_main_toUE, SIB_temp_toUE, SIB_iddt_toUE, SIB_slack_toUE, SIB_voltage_toUE : std_logic;
signal SIB_main_toSE, SIB_temp_toSE, SIB_iddt_toSE, SIB_slack_toSE, SIB_voltage_toSE : std_logic;
signal SIB_main_toCE, SIB_temp_toCE, SIB_iddt_toCE, SIB_slack_toCE, SIB_voltage_toCE : std_logic;
signal temp_monitor_SO, iddt_monitor_SO, slack_monitor_SO, voltage_monitor_SO : std_logic;
signal temp_monitor_toF, iddt_monitor_toF, slack_monitor_toF, voltage_monitor_toF, toF_SIB_main : std_logic;
signal temp_monitor_toC, iddt_monitor_toC, slack_monitor_toC, voltage_monitor_toC, toC_SIB_main : std_logic;
begin
-- .-----------.
-- SI ----| sib_main |---------------------------------------------- SO
-- '-----------'
-- | |_____________________________________________.
-- | |
-- | .----------. .----------. .----------. .----------. |
-- '-| sib_temp |-| sib_iddt |-| sib_slck |-| sib_volt |-'
-- '----------' '----------' '----------' '----------'
--
-- the order of bits in each sib is: SXCF where S is opening bit!
------------------------------------------------------------
-- Main SIB connected to the top interface
------------------------------------------------------------
SIB_main : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SI,
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SO,
toF => toF,
toC => toC,
-- Scan Interface host ----------------
fromSO => SIB_voltage_SO,
toCE => SIB_main_toCE,
toSE => SIB_main_toSE,
toUE => SIB_main_toUE,
toSEL => SIB_main_toSEL,
toRST => SIB_main_toRST,
toTCK => SIB_main_toTCK,
toSI => SIB_main_toSI,
fromF => toF_SIB_main,
fromC => toC_SIB_main
);
toF_SIB_main <= SIB_temp_toF or SIB_iddt_toF or SIB_slack_toF or SIB_voltage_toF;
toC_SIB_main <= SIB_temp_toC and SIB_iddt_toC and SIB_slack_toC and SIB_voltage_toC;
------------------------------------------------------------
-- Temperature SIB and monitor interface
------------------------------------------------------------
SIB_temp : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_main_toSI,
CE => SIB_main_toCE,
SE => SIB_main_toSE,
UE => SIB_main_toUE,
SEL => SIB_main_toSEL,
RST => SIB_main_toRST,
TCK => SIB_main_toTCK,
SO => SIB_temp_SO,
toF => SIB_temp_toF,
toC => SIB_temp_toC,
-- Scan Interface host ----------------
fromSO => temp_monitor_SO,
toCE => SIB_temp_toCE,
toSE => SIB_temp_toSE,
toUE => SIB_temp_toUE,
toSEL => SIB_temp_toSEL,
toRST => SIB_temp_toRST,
toTCK => SIB_temp_toTCK,
toSI => SIB_temp_toSI,
fromF => temp_monitor_toF,
fromC => temp_monitor_toC
);
temp_monitor: immortal_temp_iddt_monitor_instrument
port map (
-- IJTAG connection
TCK => SIB_temp_toTCK,
RST => SIB_temp_toRST,
SEL => SIB_temp_toSEL,
SI => SIB_temp_toSI,
SE => SIB_temp_toSE,
UE => SIB_temp_toUE,
CE => SIB_temp_toCE,
SO => temp_monitor_SO,
toF => temp_monitor_toF,
toC => temp_monitor_toC,
-- Monitor connections
control => temperature_control,
adc_data => temperature_data(12 downto 1),
adc_drdy => temperature_data(0)
);
------------------------------------------------------------
-- IDDt SIB and monitor interface
------------------------------------------------------------
SIB_iddt : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_temp_SO,
CE => SIB_main_toCE,
SE => SIB_main_toSE,
UE => SIB_main_toUE,
SEL => SIB_main_toSEL,
RST => SIB_main_toRST,
TCK => SIB_main_toTCK,
SO => SIB_iddt_SO,
toF => SIB_iddt_toF,
toC => SIB_iddt_toC,
-- Scan Interface host ----------------
fromSO => iddt_monitor_SO,
toCE => SIB_iddt_toCE,
toSE => SIB_iddt_toSE,
toUE => SIB_iddt_toUE,
toSEL => SIB_iddt_toSEL,
toRST => SIB_iddt_toRST,
toTCK => SIB_iddt_toTCK,
toSI => SIB_iddt_toSI,
fromF => iddt_monitor_toF,
fromC => iddt_monitor_toC
);
iddt_monitor: immortal_temp_iddt_monitor_instrument
port map (
-- IJTAG connection
TCK => SIB_iddt_toTCK,
RST => SIB_iddt_toRST,
SEL => SIB_iddt_toSEL,
SI => SIB_iddt_toSI,
SE => SIB_iddt_toSE,
UE => SIB_iddt_toUE,
CE => SIB_iddt_toCE,
SO => iddt_monitor_SO,
toF => iddt_monitor_toF,
toC => iddt_monitor_toC,
-- Monitor connections
control => iddt_control,
adc_data => iddt_data(12 downto 1),
adc_drdy => iddt_data(0)
);
------------------------------------------------------------
-- Slack SIB and monitor interface
------------------------------------------------------------
SIB_slack : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_iddt_SO,
CE => SIB_main_toCE,
SE => SIB_main_toSE,
UE => SIB_main_toUE,
SEL => SIB_main_toSEL,
RST => SIB_main_toRST,
TCK => SIB_main_toTCK,
SO => SIB_slack_SO,
toF => SIB_slack_toF,
toC => SIB_slack_toC,
-- Scan Interface host ----------------
fromSO => slack_monitor_SO,
toCE => SIB_slack_toCE,
toSE => SIB_slack_toSE,
toUE => SIB_slack_toUE,
toSEL => SIB_slack_toSEL,
toRST => SIB_slack_toRST,
toTCK => SIB_slack_toTCK,
toSI => SIB_slack_toSI,
fromF => slack_monitor_toF,
fromC => slack_monitor_toC
);
slack_monitor : immortal_slack_monitor_instrument
port map (
-- IJTAG connection
TCK => SIB_slack_toTCK,
RST => SIB_slack_toRST,
SEL => SIB_slack_toSEL,
SI => SIB_slack_toSI,
SE => SIB_slack_toSE,
UE => SIB_slack_toUE,
CE => SIB_slack_toCE,
SO => slack_monitor_SO,
toF => slack_monitor_toF,
toC => slack_monitor_toC,
-- Monitor connections
control => slack_control,
data => slack_data
);
------------------------------------------------------------
-- Voltage SIB and monitor interface
------------------------------------------------------------
SIB_voltage : SIB_mux_pre_FCX_SELgate
port map ( -- Scan Interface client --------------
SI => SIB_slack_SO,
CE => SIB_main_toCE,
SE => SIB_main_toSE,
UE => SIB_main_toUE,
SEL => SIB_main_toSEL,
RST => SIB_main_toRST,
TCK => SIB_main_toTCK,
SO => SIB_voltage_SO,
toF => SIB_voltage_toF,
toC => SIB_voltage_toC,
-- Scan Interface host ----------------
fromSO => voltage_monitor_SO,
toCE => SIB_voltage_toCE,
toSE => SIB_voltage_toSE,
toUE => SIB_voltage_toUE,
toSEL => SIB_voltage_toSEL,
toRST => SIB_voltage_toRST,
toTCK => SIB_voltage_toTCK,
toSI => SIB_voltage_toSI,
fromF => voltage_monitor_toF,
fromC => voltage_monitor_toC
);
voltage_monitor : immortal_volt_monitor_instrument
port map (
-- IJTAG connection
TCK => SIB_voltage_toTCK,
RST => SIB_voltage_toRST,
SEL => SIB_voltage_toSEL,
SI => SIB_voltage_toSI,
SE => SIB_voltage_toSE,
UE => SIB_voltage_toUE,
CE => SIB_voltage_toCE,
SO => voltage_monitor_SO,
toF => voltage_monitor_toF,
toC => voltage_monitor_toC,
-- Monitor connections
control => voltage_control,
data => voltage_data
);
end;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/color_bridge.vhd
|
6
|
2522
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COLOR_BRIDGE;
ARCHITECTURE main OF COLOR_BRIDGE IS
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(BRG_EN = '1') THEN
CASE COLOR IS
--BLACK
WHEN x"0" =>
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
--DARK RED
WHEN x"1" =>
R <= "0111111111";
G <= "0000000000";
B <= "0000000000";
--DARK GREEN
WHEN x"2" =>
R <= "0000000000";
G <= "0111111111";
B <= "0000000000";
--DARK YELLOW
WHEN x"3" =>
R <= "0111111111";
G <= "0111111111";
B <= "0000000000";
--DARK BLUE
WHEN x"4" =>
R <= "0000000000";
G <= "0000000000";
B <= "0111111111";
--PURPLE
WHEN x"5" =>
R <= "0111111111";
G <= "0000000000";
B <= "0111111111";
--GREENISH BLUE
WHEN x"6" =>
R <= "0000000000";
G <= "0111111111";
B <= "0111111111";
--LIGHT GRAY
WHEN x"7" =>
R <= "1011111111";
G <= "1011111111";
B <= "1011111111";
--GRAY
WHEN x"8" =>
R <= "0111111111";
G <= "0111111111";
B <= "0111111111";
--RED
WHEN x"9" =>
R <= "1111111111";
G <= "0000000000";
B <= "0000000000";
--GREEN
WHEN x"A" =>
R <= "0000000000";
G <= "1111111111";
B <= "0000000000";
--YELLOW
WHEN x"B" =>
R <= "1111111111";
G <= "1111111111";
B <= "0000000000";
--BLUE
WHEN x"C" =>
R <= "0000000000";
G <= "0000000000";
B <= "1111111111";
--PINK
WHEN x"D" =>
R <= "1111111111";
G <= "0000000000";
B <= "1111111111";
--SKY BLUE
WHEN x"E" =>
R <= "0000000000";
G <= "1111111111";
B <= "1111111111";
--WHITE
WHEN x"F" =>
R <= "1111111111";
G <= "1111111111";
B <= "1111111111";
WHEN OTHERS =>
END CASE;
ELSE
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
END IF;
END IF;
END PROCESS;
END main;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Software_Assembly/IR_Controller/Processor_IR_PWM_DE2_70/AP9_cpu.vhd
|
2
|
32012
|
---------------------------------------------------
--apx-arch ap9 micro-processor---------------------
--16-bits width bus--------------------------------
--external clock-----------------------------------
--builded by microenix, cOPyright (r) 2011---------
--for detailed description about this--------------
--architechture, please refer to the ap9 reference--
--manual.------------------------------------------
---------------------------------------------------
libraRY ieee;
use ieee.std_LOGIC_1164.all;
use ieee.std_LOGIC_ARITH.all;
use ieee.std_LOGIC_unsigned.all;
entity AP9_cpu is
port( clk : in std_LOGIC;
reset : in std_LOGIC;
Mem : in STD_LOGIC_VECTOR(15 downto 0);
M5 : out STD_LOGIC_VECTOR(15 downto 0);
M1 : out STD_LOGIC_VECTOR(15 downto 0);
RW : out std_LOGIC;
key : in STD_LOGIC_VECTOR(7 downto 0);
videoflag : out std_LOGIC;
vga_pos : out STD_LOGIC_VECTOR(15 downto 0);
vga_char : out STD_LOGIC_VECTOR(15 downto 0);
Ponto : out STD_LOGIC_VECTOR(2 downto 0);
halt_ack : out std_LOGIC;
halt_req : in std_LOGIC;
PC_data : out STD_LOGIC_VECTOR(15 downto 0)
);
end AP9_cpu;
ARCHITECTURE main of AP9_cpu is
TYPE STATES is (fetch, decode, exec, halted); -- Estados da Maquina de Controle do Processador
TYPE Registers is array(0 to 7) of STD_LOGIC_VECTOR(15 downto 0); -- Banco de Registradores
TYPE LoadRegisters is array(0 to 7) of std_LOGIC; -- Sinais de LOAD dos Registradores do Banco
-- INSTRUCTION SET: 29 INSTRUCTIONS
-- Data Manipulation Instructions: -- Usage -- Action -- Format
CONSTANT LOAD : STD_LOGIC_VECTOR(5 downto 0) := "110000"; -- LOAD RX END -- RX <- M[END] Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT STORE : STD_LOGIC_VECTOR(5 downto 0) := "110001"; -- STORE END RX -- M[END] <- RX Format: < inst(6) | RX(3) | xxxxxxx > + 16bit END
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 downto 0) := "111000"; -- LOADN RX Nr -- RX <- Nr Format: < inst(6) | RX(3) | xxxxxxb0 > + 16bit Numero
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111100"; -- LOADI RX RY -- RX <- M[RY] Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 downto 0) := "111101"; -- STOREI RX RY -- M[RX] <- RY Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT MOV : STD_LOGIC_VECTOR(5 downto 0) := "110011"; -- MOV RX RY -- RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
-- I/O Instructions:
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110010"; -- OUTCHAR RX RY -- Video[RY] <- Char(RX) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 downto 0) := "110101"; -- INCHAR RX -- RX[5..0] <- KeyPressed RX[15..6] <- 0's Format: < inst(6) | RX(3) | xxxxxxx >
-- Se nao pressionar nenhuma tecla, RX recebe 00FF
CONSTANT ARITH : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- Aritmethic Instructions(All should begin wiht "10"):
CONSTANT ADD : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- ADD RX RY RZ / ADDC RX RY RZ -- RX <- RY + RZ / RX <- RY + RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT SUB : STD_LOGIC_VECTOR(3 downto 0) := "0001"; -- SUB RX RY RZ / SUBC RX RY RZ -- RX <- RY - RZ / RX <- RY - RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT MULT : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- MUL RX RY RZ / MUL RX RY RZ -- RX <- RY * RZ / RX <- RY * RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT DIV : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- DIV RX RY RZ -- RX <- RY / RZ / RX <- RY / RZ + C -- b0=CarRY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| C >
CONSTANT INC : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- INC RX / DEC RX -- RX <- RX + 1 / RX <- RX - 1 -- b6= INC/DEC : 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT LMOD : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- MOD RX RY RZ -- RX <- RY MOD RZ Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- LOGIC Instructions (All should begin wiht "01"):
CONSTANT LAND : STD_LOGIC_VECTOR(3 downto 0) := "0010"; -- AND RX RY RZ -- RZ <- RX AND RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LOR : STD_LOGIC_VECTOR(3 downto 0) := "0011"; -- OR RX RY RZ -- RZ <- RX OR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LXOR : STD_LOGIC_VECTOR(3 downto 0) := "0100"; -- XOR RX RY RZ -- RZ <- RX XOR RY Format: < inst(6) | RX(3) | RY(3) | RZ(3)| x >
CONSTANT LNOT : STD_LOGIC_VECTOR(3 downto 0) := "0101"; -- NOT RX RY -- RX <- NOT(RY) Format: < inst(6) | RX(3) | RY(3) | xxxx >
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 downto 0) := "0000"; -- SHIFTL0 RX,n / SHIFTL1 RX,n / SHIFTR0 RX,n / SHIFTR1 RX,n / ROTL RX,n / ROTR RX,n
-- SHIFT/Rotate RX -- b6=shif/rotate: 0/1 b5=left/right: 0/1; b4=fill;
-- Format: < inst(6) | RX(3) | b6 b5 b4 | nnnn >
CONSTANT CMP : STD_LOGIC_VECTOR(3 downto 0) := "0110"; -- CMP RX RY -- Compare RX and RY and set FR : Format: < inst(6) | RX(3) | RY(3) | xxxx > Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
-- JMP Condition: (UNconditional, EQual, Not Equal, Zero, Not Zero, CarRY, Not CarRY, GReater, LEsser, Equal or Greater, Equal or Lesser, OVerflow, Not OVerflow, Negative, DIVbyZero, NOT USED)
-- FLOW CONTROL Instructions:
CONSTANT JMP : STD_LOGIC_VECTOR(5 downto 0) := "000010"; -- JMP END -- PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT CALL : STD_LOGIC_VECTOR(5 downto 0) := "000011"; -- CALL END -- M[SP] <- PC | SP-- | PC <- 16bit END : b9-b6 = COND Format: < inst(6) | COND(4) | xxxxxx > + 16bit END
CONSTANT RTS : STD_LOGIC_VECTOR(5 downto 0) := "000100"; -- RTS -- SP++ | PC <- M[SP] | b6=RX/FR: 1/0 Format: < inst(6) | xxxxxxxxxx >
CONSTANT PUSH : STD_LOGIC_VECTOR(5 downto 0) := "000101"; -- PUSH RX / PUSH FR -- M[SP] <- RX / M[SP] <- FR | SP-- : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
CONSTANT POP : STD_LOGIC_VECTOR(5 downto 0) := "000110"; -- POP RX / POP FR -- SP++ | RX <- M[SP] / FR <- M[SP] : b6=RX/FR: 0/1 Format: < inst(6) | RX(3) | b6 | xxxxxx >
-- Control Instructions:
CONSTANT NOP : STD_LOGIC_VECTOR(5 downto 0) := "000000"; -- NOP -- Do Nothing Format: < inst(6) | xxxxxxxxxx >
CONSTANT HALT : STD_LOGIC_VECTOR(5 downto 0) := "001111"; -- HALT -- StOP Here Format: < inst(6) | xxxxxxxxxx >
CONSTANT SETC : STD_LOGIC_VECTOR(5 downto 0) := "001000"; -- CLEARC / SETC -- Set/Clear CarRY: b9 = 1-set; 0-clear Format: < inst(6) | b9 | xxxxxxxxx >
CONSTANT BREAKP : STD_LOGIC_VECTOR(5 downto 0) := "001110"; -- BREAK POINT -- Switch to manual clock Format: < inst(6) | xxxxxxxxxx >
-- CONSTANTes para controle do Mux2
CONSTANT sULA : STD_LOGIC_VECTOR (2 downto 0) := "000";
CONSTANT sMem : STD_LOGIC_VECTOR (2 downto 0) := "001";
CONSTANT sM4 : STD_LOGIC_VECTOR (2 downto 0) := "010";
CONSTANT skey : STD_LOGIC_VECTOR (2 downto 0) := "011";
--CONSTANT sTECLADO : STD_LOGIC_VECTOR (2 downto 0) := "011";
CONSTANT sSP : STD_LOGIC_VECTOR (2 downto 0) := "100";
-- CONSTANTes para controle do Mux2
-- CONSTANT sULA : STD_LOGIC_VECTOR(1 downto 0) := "00";
-- CONSTANT sMem : STD_LOGIC_VECTOR(1 downto 0) := "01";
-- CONSTANT sM4 : STD_LOGIC_VECTOR(1 downto 0) := "10";
-- CONSTANT skey : STD_LOGIC_VECTOR(1 downto 0) := "11";
-- Sinais para o Processo da ULA
signal OP : STD_LOGIC_VECTOR(6 downto 0); -- OP(6) deve ser setado para OPeracoes com carRY
signal x, y, result : STD_LOGIC_VECTOR(15 downto 0);
signal FR : STD_LOGIC_VECTOR(15 downto 0); -- Flag Register: <...DIVbyZero|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
signal auxFR : STD_LOGIC_VECTOR(15 downto 0); -- Representa um barramento conectando a ULA ao Mux6 para escrever no FR
begin
-- Maquina de Controle
process(clk, reset)
--Register Declaration:
variable PC : STD_LOGIC_VECTOR(15 downto 0); -- Program Counter
variable IR : STD_LOGIC_VECTOR(15 downto 0); -- Instruction Register
variable SP : STD_LOGIC_VECTOR(15 downto 0); -- Stack Pointer
variable MAR : STD_LOGIC_VECTOR(15 downto 0); -- Memory address Register
--VARIABLE TECLADO :STD_LOGIC_VECTOR(15 downto 0); -- Registrador para receber dados do teclado
variable reg : Registers;
-- Mux dos barramentos de dados internos
VARIABLE M2 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos barramentos de dados internos para os Registradores
VARIABLE M3, M4 :STD_LOGIC_VECTOR(15 downto 0); -- Mux dos Registradores para as entradas da ULA
-- Novos Sinais da V2
variable LoadReg : LoadRegisters;
variable LoadIR : std_LOGIC;
variable LoadMAR : std_LOGIC;
variable LoadPC : std_LOGIC;
variable IncPC : std_LOGIC;
VARIABLE LoadSP : STD_LOGIC;
variable IncSP : std_LOGIC;
variable DecSP : std_LOGIC;
variable selM2 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM2 :STD_LOGIC_VECTOR (2 downto 0);
variable selM6 : STD_LOGIC_VECTOR(2 downto 0); -- VARIABLE selM6 :STD_LOGIC_VECTOR (2 downto 0);
VARIABLE BreakFlag : STD_LOGIC;
variable state : STATES;
variable RX : integer;
variable RY : integer;
variable RZ : integer;
begin
if(reset = '1') then
state := fetch;
M1(15 downto 0) <= x"0000";
videoflag <= '0';
RX := 0;
RY := 0;
RZ := 0;
RW <= '0';
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
selM2 := sMem;
selM6 := sULA;
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
REG(0) := x"0000";
REG(1) := x"0000";
REG(2) := x"0000";
REG(3) := x"0000";
REG(4) := x"0000";
REG(5) := x"0000";
REG(6) := x"0000";
REG(7) := x"0000";
PC := x"0000";
SP := x"3ffc"; -- 7ffc
IR := x"0000";
MAR := x"0000";
-- TECLADO := x"0000";
BreakFlag:= '0'; -- Break Point Flag
--BREAK <= '0'; -- Break Point output to switch to manual clock
-- nao tinha
HALT_ack <= '0';
elsif(clk'event and clk = '1') then
if(LoadIR = '1') then IR := Mem; end if;
if(LoadPC = '1') then PC := Mem; end if;
if(IncPC = '1') then PC := PC + x"0001"; end if;
if(LoadMAR = '1') then MAR := Mem; end if;
if(LoadSP = '1') then SP := M3; end if;
if(IncSP = '1') then SP := SP + x"0001"; end if;
if(DecSP = '1') then SP := SP - x"0001"; end if;
-- Selecao do Mux6
if (selM6 = sULA) THEN FR <= auxFR; -- Sempre recebe flags da ULA
ELSIF (selM6 = sMem) THEN FR <= Mem; END IF; -- A menos que seja POP FR, quando recebe da Memoria
-- Atualiza o nome dos registradores!!!
RX := conv_integer(IR(9 downto 7));
RY := conv_integer(IR(6 downto 4));
RZ := conv_integer(IR(3 downto 1));
-- Selecao do Mux2
if (selM2 = sULA) THEN M2 := RESULT;
ELSIF (selM2 = sMem) THEN M2 := Mem;
ELSIF (selM2 = sM4) THEN M2 := M4;
ELSIF (selM2 = skey) THEN M2(15 downto 8) := x"00";
M2(7 downto 0) := key;
ELSIF (selM2 = sSP) THEN M2 := SP;
END IF;
-- if (LoadReg(RX) = '1') then REG(RX) := M2; end if;
if(LoadReg(RX) = '1') then reg(RX) := m2; end if;
-- Reseta os sinais de controle APOS usa-los acima
-- Zera todos os sinais de controle, para depois ligar um por um a medida que for necessario: a ultima atribuicao e' a que vale no processo!!!
LoadIR := '0';
LoadMAR := '0';
LoadPC := '0';
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadSP := '0';
selM6 := sULA; -- Sempre atualiza o FR da ULA, a nao ser que a instrucao seja POP FR
LoadReg(0) := '0';
LoadReg(1) := '0';
LoadReg(2) := '0';
LoadReg(3) := '0';
LoadReg(4) := '0';
LoadReg(5) := '0';
LoadReg(6) := '0';
LoadReg(7) := '0';
videoflag <= '0';
RW <= '0';
-- nao tinha
if(halt_req = '1') then state := halted; end if;
PC_data <= PC;
case state is
--************************************************************************
-- FETCH STATE
--************************************************************************
when fetch =>
PONTO <= "001";
-- Inicio das acoes do ciclo de Busca !!
M1 <= PC;
RW <= '0';
LoadIR := '1';
IncPC := '1';
STATE := decode;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- DECODE STATE
--************************************************************************
when decode =>
PONTO <= "010";
--========================================================================
-- INCHAR RX[5..0] <- KeyPressed RX[15..6] <- 0
--========================================================================
IF(IR(15 DOWNTO 10) = INCHAR) THEN
selM2 := skey;
LoadReg(RX) := '1';
state := fetch;
END IF;
--========================================================================
-- OUTCHAR Video[RY] <- Char(RX)
--========================================================================
IF(IR(15 DOWNTO 10) = OUTCHAR) THEN
M3 := Reg(Rx); -- M3 <- Rx
M4 := Reg(Ry); -- M4 <- Ry
vga_char <= M3;
vga_pos <= M4;
videoflag <= '1';
state := fetch;
END IF;
--========================================================================
-- MOV RX/SP <- RY/SP
-- MOV RX RY RX <- RY Format: < inst(6) | RX(3) | RY(3) | xx | x0 >
-- MOV RX SP RX <- SP Format: < inst(6) | RX(3) | xxx | xx | 01 >
-- MOV SP RX SP <- RX Format: < inst(6) | RX(3) | xxx | xx | 11 >
--========================================================================
IF(IR(15 DOWNTO 10) = MOV) THEN
IF(IR(0) = '0') THEN
M4 := REG(RY);
selM2 := sM4;
LoadReg(RX) := '1';
ELSE
IF(IR(1) = '0') THEN
selM2 := sSP;
LoadReg(RX) := '1';
ELSE
M3 := REG(RX);
LoadSP := '1';
END IF;
END IF;
state := fetch;
END IF;
--========================================================================
-- STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN -- Busca o endereco
M1 <= PC;
RW <= '0';
LoadMAR := '1';
IncPC := '1';
state := exec;
END IF;
--========================================================================
-- STORE indexado por registrador M[RX] <- RY
--========================================================================
IF(IR(15 DOWNTO 10) = STOREINDEX) THEN
M4 := Reg(Rx); -- M4 <- Rx
M1 <= M4; -- M1 <- M4
M3 := Reg(Ry); -- M3 <- Ry
M5 <= M3;
Rw <= '1'; -- Rw <- 1
state := fetch;
END IF;
--========================================================================
-- LOAD Direto RX <- M[End]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN -- Busca o endereco
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <- 0
LoadMAR := '1';-- LMAR <- 1
IncPC := '1';
state := exec;
END IF;
--========================================================================
-- LOAD Imediato RX <- Nr
--========================================================================
IF(IR(15 DOWNTO 10) = LOADIMED) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- Rw <= '0'
selM2 := sMeM; -- LRx <- 1
LoadReg(RX) := '1'; -- IncPC <- 1
IncPC := '1'; -- M2 <- MEM
state := fetch;
END IF;
--========================================================================
-- LOAD Indexado por registrador RX <- M(RY)
--========================================================================
IF(IR(15 DOWNTO 10) = LOADINDEX) THEN
M4 := Reg(Ry); -- M4 <- Ry
M1 <= M4; -- M1 <- M4
Rw <= '0'; -- Rw <- 0
selM2 := sMEM; -- M2 <- MEM
LoadReg(Rx) := '1'; -- LRx <- 1
state := fetch;
END IF;
--========================================================================
-- LOGIC OPERATION ('SHIFT', 'CMP' AND 'NOT' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) /= SHIFT AND IR(13 DOWNTO 10) /= LNOT AND IR(13 DOWNTO 10) /= CMP) THEN
M3 := Reg(Ry);
M4 := Reg(Rz);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- NOT RX, RY RX <- NOT(RY)
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = LNOT) THEN
M3 := REG(RX);
M4 := REG(RY);
X <= M3;
Y <= M4;
OP(5 downto 0) <= IR(15 downto 10);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- CMP RX, RY
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC AND IR(13 DOWNTO 10) = CMP) THEN
M3 := Reg(Rx);
M4 := Reg(Ry);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
state := fetch;
END IF;
--========================================================================
-- SHIFT RX, RY RX <- SHIFT[ RY] ROTATE INCluded !
--========================================================================
IF(IR(15 DOWNTO 14) = LOGIC and (IR(13 DOWNTO 10) = SHIFT)) THEN
if(IR(6 DOWNTO 4) = "000") then -- SHIFT LEFT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))sll conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "001") then -- SHIFT LEFT 1
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))sll conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 4) = "010") then -- SHIFT RIGHT 0
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))srl conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 4) = "011") then -- SHIFT RIGHT 0
Reg(RX) := not (To_StdLOGICVector(to_bitvector(not Reg(RY))srl conv_integer(IR(3 DOWNTO 0))));
elsif(IR(6 DOWNTO 5) = "11") then -- ROTATE RIGHT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))ror conv_integer(IR(3 DOWNTO 0)));
elsif(IR(6 DOWNTO 5) = "10") then -- ROTATE LEFT
Reg(RX) := To_StdLOGICVector(to_bitvector(Reg(RY))rol conv_integer(IR(3 DOWNTO 0)));
end if;
state := fetch;
end if;
--========================================================================
-- JMP END PC <- 16bit END : b9-b6 = COND
-- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
--========================================================================
IF(IR(15 DOWNTO 10) = JMP) THEN
if((IR(9 downto 6) = "0000") or -- NO COND
(IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER
(IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal
(IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser
(IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal
(IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal
(IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal
(IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero
(IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero
(IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry
(IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry
(IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow
(IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow
(IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0
(IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative
M1 <= PC;
RW <= '0';
LoadPC := '1';
else
IncPC := '1';
end if;
state := fetch;
END IF;
--========================================================================
-- PUSH RX
--========================================================================
IF(IR(15 DOWNTO 10) = PUSH) THEN
M1 <= SP; -- M1 <- SP
Rw <= '1'; -- R/W <- 1
if(IR(6) = '0') then
M3 := Reg(Rx); -- M3 <- Rx
elsif(IR(6) = '1') then
M3 := FR;
end if;
M5 <= M3; -- M5 <- M3
DecSP := '1'; -- DecSP <- 1
state := fetch;
END IF;
--========================================================================
-- POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
IncSP := '1';
state := exec;
END IF;
--========================================================================
-- CALL END PC <- 16bit END : b9-b6 = COND PUSH(PC)
-- Flag Register: <...|StackUnderflow|StackOverflow|DIVByZero|ARITHmeticOverflow|carRY|zero|equal|lesser|greater>
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
if((IR(9 downto 6) = "0000") or -- NO COND
(IR(9 downto 6) = "0111" and FR(0) = '1') or -- GREATER
(IR(9 downto 6) = "1001" and FR(2 downto 0) = "101") or -- greater equal
(IR(9 downto 6) = "1000" and FR(1) = '1') or -- lesser
(IR(9 downto 6) = "1010" and FR(2 downto 0) = "110") or -- lesser equal
(IR(9 downto 6) = "0001" and FR(2) = '1') or -- equal
(IR(9 downto 6) = "0010" and FR(2) = '0') or -- not equal
(IR(9 downto 6) = "0011" and FR(3) = '1') or -- zero
(IR(9 downto 6) = "0100" and FR(3) = '0') or -- not zero
(IR(9 downto 6) = "0101" and FR(4) = '1') or -- carry
(IR(9 downto 6) = "0110" and FR(4) = '0') or -- not carry
(IR(9 downto 6) = "1011" and FR(5) = '1') or -- overflow
(IR(9 downto 6) = "1100" and FR(5) = '0') or -- not overflow
(IR(9 downto 6) = "1101" and FR(6) = '1') or -- DIV0
(IR(9 downto 6) = "1110" and FR(9) = '1')) then -- result negative
RW <= '1'; -- Escreve PC na Pilha (M[SP] <- PC)
M5 <= PC;
M1 <= SP;
DecSP := '1';
state := exec;
ELSE
IncPC := '1';
state := fetch;
END IF;
END IF;
--========================================================================
-- RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
IncSP := '1';
state := exec;
END IF;
--========================================================================
-- ARITH OPERATION ('INC' NOT INCLUDED) RX <- RY (?) RZ
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) /= INC) THEN
M3 := Reg(Ry);
M4 := Reg(RZ);
X <= M3;
Y <= M4;
OP(5 downto 0 ) <= IR(15 downto 10);
OP(6) <= IR(0);
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- INC RX <- RX (+ or -) 1
--========================================================================
IF(IR(15 DOWNTO 14) = ARITH AND IR(13 DOWNTO 10) = INC) THEN
M3 := Reg(Rx);
M4 := x"0001";
X <= M3;
Y <= M4;
OP(5 downto 4) <= ARITH;
IF(IR(6) = '0') THEN
OP(3 downto 0) <= ADD;
ELSE
OP(3 downto 0) <= SUB;
END IF;
selM2 := sULA;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- NOP
--========================================================================
IF( IR(15 DOWNTO 10) = NOP) THEN
state := fetch;
end if;
--========================================================================
-- HALT
--========================================================================
IF( IR(15 DOWNTO 10) = HALT) THEN
state := halted;
END IF;
--========================================================================
-- SETC/CLEARC
--========================================================================
IF( IR(15 DOWNTO 10) = SETC) THEN
FR(4) <= IR(9);
state := fetch;
end if;
--========================================================================
-- BREAKP
--========================================================================
IF( IR(15 DOWNTO 10) = BREAKP) THEN
BreakFlag := not(BreakFlag);
--BREAK <= BreakFlag;
state := fetch;
PONTO <= "101";
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- EXECUTE STATE
--************************************************************************
when exec =>
PONTO <= "100";
--========================================================================
-- EXEC STORE DIReto M[END] <- RX
--========================================================================
IF(IR(15 DOWNTO 10) = STORE) THEN
M1 <= MAR;
Rw <= '1';
M3 := Reg(Rx);
M5 <= M3;
state := fetch;
END IF;
--========================================================================
-- EXEC LOAD DIReto RX <- M[END]
--========================================================================
IF(IR(15 DOWNTO 10) = LOAD) THEN
M1 <= Mar;
Rw <= '0';
selM2 := sMem;
LoadReg(Rx) := '1';
state := fetch;
END IF;
--========================================================================
-- EXEC POP RX
--========================================================================
IF(IR(15 DOWNTO 10) = POP) THEN
M1 <= SP; -- M1 <- SP
Rw <= '0'; -- R/W <- 0
if(IR(6) = '0') then
selM2 := sMem; -- M2 <- MEM
LoadReg(Rx) := '1'; -- LRx <- 1
elsif(IR(6) = '1') then
selM6 := sMem;
end if;
state := fetch;
END IF;
--========================================================================
-- EXEC CALL Pilha <- PC e PC <- 16bit END :
--========================================================================
IF(IR(15 DOWNTO 10) = CALL) THEN
M1 <= PC; -- M1 <- PC
Rw <= '0'; -- R/W <- 0
LoadPC := '1'; -- LPC <- 1
state := fetch;
END IF;
--========================================================================
-- EXEC RTS PC <- Mem[SP]
--========================================================================
IF(IR(15 DOWNTO 10) = RTS) THEN
M1 <= SP;
Rw <= '0';
LoadPC := '1';
IncPC := '1'; -- fazer em outro estado pq INCrementar e LOAD sao na SUBida de clock
state := fetch;
END IF;
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--************************************************************************
-- HALT STATE
--************************************************************************
WHEN halted =>
PONTO <= "111";
state := halted;
halt_ack <= '1';
WHEN OTHERS =>
state := fetch;
videoflag <= '0';
PONTO <= "000";
END CASE;
end if;
end process;
--************************************************************************
-- ULA ---> 3456 (3042)
--************************************************************************
PROCESS (OP, X, Y, reset)
VARIABLE AUX : STD_LOGIC_VECTOR(15 downto 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 downto 0);
BEGIN
IF (reset = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
else
auxFR <= FR;
--========================================================================
-- ARITH
--========================================================================
IF (OP (5 downto 4) = ARITH) THEN
CASE OP (3 downto 0) IS
WHEN ADD =>
IF (OP(6) = '1') THEN --Soma com carRY
AUX := X + Y + FR(4);
RESULT32 := (x"00000000" + X + Y + FR(4));
ELSE --Soma sem carRY
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
end if;
if(RESULT32 > "01111111111111111") THEN -- CarRY
auxFR(4) <= '1';
ELSE
auxFR(4) <= '0';
end if;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 downto 0);
if(RESULT32 > x"0000FFFF") THEN -- ARITHmetic Overflow
auxFR(5) <= '1';
ELSE
auxFR(5) <= '0';
end if;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN LMOD =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(6) <= '1'; -- DIV by Zero
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) mod CONV_INTEGER(Y), 16);
auxFR(6) <= '0';
END IF;
WHEN others => -- invalid operation, defaults to nothing
AUX := X;
END CASE;
if(AUX = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
if(AUX < x"0000") THEN -- NEGATIVO
auxFR(9) <= '1';
ELSE
auxFR(9) <= '0';
end if;
RESULT <= AUX;
ELSIF (OP (5 downto 4) = LOGIC) THEN
IF (OP (3 downto 0) = CMP) THEN
result <= x;
IF (x > y) THEN
auxFR(2 downto 0) <= "001"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x < y) THEN
auxFR(2 downto 0) <= "010"; -- FR = <...|zero|equal|lesser|greater>
ELSIF (x = y) THEN
auxFR(2 downto 0) <= "100"; -- FR = <...|zero|equal|lesser|greater>
END IF;
ELSE
CASE OP (3 downto 0) IS
WHEN LAND => result <= x and y;
WHEN LXOR => result <= x xor y;
WHEN LOR => result <= x or y;
WHEN LNOT => result <= not y;
WHEN others => -- invalid operation, defaults to nothing
RESULT <= X;
END CASE;
if(result = x"0000") THEN
auxFR(3) <= '1'; -- FR = <...|zero|equal|lesser|greater>
ELSE
auxFR(3) <= '0'; -- FR = <...|zero|equal|lesser|greater>
end if;
END IF;
END IF;
END IF; -- Reset
END PROCESS;
end main;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/lpm_dff2.vhd
|
3
|
3921
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff2.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff2 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END lpm_dff2;
ARCHITECTURE SYN OF lpm_dff2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (20 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(20 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 21
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "21"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 21 0 INPUT NODEFVAL data[20..0]
-- Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL q[20..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
-- Retrieval info: CONNECT: @data 0 0 21 0 data 0 0 21 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/customized_routers/Router_32_bit_NW_credit_based_packet_drop_classifier_SHMU_will_full_set_of_checkers_with_FI.vhd
|
3
|
311814
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
use work.component_pack.all;
entity router_NW_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_E, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_E, credit_in_S, credit_in_L: in std_logic;
valid_in_E, valid_in_S, valid_in_L : in std_logic;
valid_out_E, valid_out_S, valid_out_L : out std_logic;
credit_out_E, credit_out_S, credit_out_L: out std_logic;
TX_E, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_E_in, Faulty_S_in: in std_logic;
Faulty_E_out, Faulty_S_out: out std_logic;
-- should be connected to NI (Outputs for classified fault information)
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
---- Outputs for non-classified fault information
link_faults_async: out std_logic_vector(4 downto 0);
turn_faults_async: out std_logic_vector(19 downto 0)
);
end router_NW_credit_based_PD_C_SHMU;
architecture behavior of router_NW_credit_based_PD_C_SHMU is
-------------------------------
-- Added because of Checkers --
-------------------------------
--signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?!
--signal shift_parallel_data: std_logic_vector(19 downto 0);
-------------------------------
-------------------------------
signal FIFO_D_out_E, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_EE, Grant_ES, Grant_EL: std_logic;
signal Grant_SE, Grant_SS, Grant_SL: std_logic;
signal Grant_LE, Grant_LS, Grant_LL: std_logic;
signal Req_EE, Req_SE, Req_LE: std_logic;
signal Req_ES, Req_SS, Req_LS: std_logic;
signal Req_EL, Req_SL, Req_LL: std_logic;
signal empty_E, empty_S, empty_L: std_logic;
signal Xbar_sel_E, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_E, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_E, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_E, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_E, packet_drop_order_S, packet_drop_order_L: std_logic;
-- Signals related to link fault classification modules
signal healthy_link_E, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_E_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_E, intermittent_link_S, intermittent_link_L: std_logic;
-- Signals related to Control part checkers fault classification modules
signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic;
signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic;
signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic;
signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic;
signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic;
signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic;
-- Signals needed for control part checkers
-- Signals needed for LBDR packet drop checkers
-- East
signal E_err_header_empty_Requests_FF_Requests_in,
E_err_tail_Requests_in_all_zero,
E_err_tail_empty_Requests_FF_Requests_in,
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
E_err_grants_onehot,
E_err_grants_mismatch,
E_err_header_tail_Requests_FF_Requests_in,
E_err_dst_addr_cur_addr_N1,
E_err_dst_addr_cur_addr_not_N1,
E_err_dst_addr_cur_addr_E1,
E_err_dst_addr_cur_addr_not_E1,
E_err_dst_addr_cur_addr_W1,
E_err_dst_addr_cur_addr_not_W1,
E_err_dst_addr_cur_addr_S1,
E_err_dst_addr_cur_addr_not_S1,
E_err_dst_addr_cur_addr_Req_L_in,
E_err_dst_addr_cur_addr_not_Req_L_in,
E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--E_err_header_not_empty_Req_L_in, -- added according to new design
E_err_header_not_empty_Req_N_in,
E_err_header_not_empty_Req_E_in,
E_err_header_not_empty_Req_W_in,
E_err_header_not_empty_Req_S_in,
E_err_header_empty_packet_drop_in_packet_drop_equal,
E_err_tail_not_empty_packet_drop_not_packet_drop_in,
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
E_err_packet_drop_order,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- South
S_err_header_empty_Requests_FF_Requests_in,
S_err_tail_Requests_in_all_zero,
S_err_tail_empty_Requests_FF_Requests_in,
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
S_err_grants_onehot,
S_err_grants_mismatch,
S_err_header_tail_Requests_FF_Requests_in,
S_err_dst_addr_cur_addr_N1,
S_err_dst_addr_cur_addr_not_N1,
S_err_dst_addr_cur_addr_E1,
S_err_dst_addr_cur_addr_not_E1,
S_err_dst_addr_cur_addr_W1,
S_err_dst_addr_cur_addr_not_W1,
S_err_dst_addr_cur_addr_S1,
S_err_dst_addr_cur_addr_not_S1,
S_err_dst_addr_cur_addr_Req_L_in,
S_err_dst_addr_cur_addr_not_Req_L_in,
S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--S_err_header_not_empty_Req_L_in, -- added according to new design
S_err_header_not_empty_Req_N_in,
S_err_header_not_empty_Req_E_in,
S_err_header_not_empty_Req_W_in,
S_err_header_not_empty_Req_S_in,
S_err_header_empty_packet_drop_in_packet_drop_equal,
S_err_tail_not_empty_packet_drop_not_packet_drop_in,
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
S_err_packet_drop_order,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal,
-- Local
L_err_header_empty_Requests_FF_Requests_in,
L_err_tail_Requests_in_all_zero,
L_err_tail_empty_Requests_FF_Requests_in,
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
L_err_grants_onehot,
L_err_grants_mismatch,
L_err_header_tail_Requests_FF_Requests_in,
L_err_dst_addr_cur_addr_N1,
L_err_dst_addr_cur_addr_not_N1,
L_err_dst_addr_cur_addr_E1,
L_err_dst_addr_cur_addr_not_E1,
L_err_dst_addr_cur_addr_W1,
L_err_dst_addr_cur_addr_not_W1,
L_err_dst_addr_cur_addr_S1,
L_err_dst_addr_cur_addr_not_S1,
L_err_dst_addr_cur_addr_Req_L_in,
L_err_dst_addr_cur_addr_not_Req_L_in,
L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--L_err_header_not_empty_Req_L_in, -- added according to new design
L_err_header_not_empty_Req_N_in,
L_err_header_not_empty_Req_E_in,
L_err_header_not_empty_Req_W_in,
L_err_header_not_empty_Req_S_in,
L_err_header_empty_packet_drop_in_packet_drop_equal,
L_err_tail_not_empty_packet_drop_not_packet_drop_in,
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
L_err_packet_drop_order,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic;
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
-- Signals needed for FIFO packet drop with fault classifier support checkers
-- East
signal -- Functional checkers
E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot,
-- Structural checkers
E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty,
E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment,
E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
E_err_fake_credit_read_en_fake_credit_counter_in_increment,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
E_err_fake_credit_read_en_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
E_err_state_out_Idle_not_fault_out_not_fake_credit,
E_err_state_out_Idle_not_fault_out_not_fault_info_in,
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Idle_fault_out_fake_credit,
E_err_state_out_Idle_fault_out_state_in_Packet_drop,
E_err_state_out_Idle_fault_out_fault_info_in,
E_err_state_out_Idle_fault_out_faulty_packet_in,
E_err_state_out_Idle_not_health_info,
E_err_state_out_Idle_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
E_err_state_out_Body_flit_valid_in_not_health_info,
E_err_state_out_Body_flit_not_fake_credit,
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
E_err_state_out_Tail_flit_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
E_err_fault_info_fault_info_out_equal,
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- South
-- Functional checkers
S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot,
-- Structural checkers
S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty,
S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment,
S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
S_err_fake_credit_read_en_fake_credit_counter_in_increment,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
S_err_fake_credit_read_en_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
S_err_state_out_Idle_not_fault_out_not_fake_credit,
S_err_state_out_Idle_not_fault_out_not_fault_info_in,
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Idle_fault_out_fake_credit,
S_err_state_out_Idle_fault_out_state_in_Packet_drop,
S_err_state_out_Idle_fault_out_fault_info_in,
S_err_state_out_Idle_fault_out_faulty_packet_in,
S_err_state_out_Idle_not_health_info,
S_err_state_out_Idle_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
S_err_state_out_Body_flit_valid_in_not_health_info,
S_err_state_out_Body_flit_not_fake_credit,
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
S_err_state_out_Tail_flit_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
S_err_fault_info_fault_info_out_equal,
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in,
-- Local
-- Functional checkers
L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot,
-- Structural checkers
L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty,
L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full,
L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1,
L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
L_err_fake_credit_read_en_fake_credit_counter_in_increment,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
L_err_fake_credit_read_en_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
L_err_state_out_Idle_not_fault_out_not_fake_credit,
L_err_state_out_Idle_not_fault_out_not_fault_info_in,
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Idle_fault_out_fake_credit,
L_err_state_out_Idle_fault_out_state_in_Packet_drop,
L_err_state_out_Idle_fault_out_fault_info_in,
L_err_state_out_Idle_fault_out_faulty_packet_in,
L_err_state_out_Idle_not_health_info,
L_err_state_out_Idle_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
L_err_state_out_Body_flit_valid_in_not_health_info,
L_err_state_out_Body_flit_not_fake_credit,
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
L_err_state_out_Tail_flit_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
L_err_fault_info_fault_info_out_equal,
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic;
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---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for Allocator unit
-- Allocator logic checker outputs
-- Might need to be changed ?!
signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N,
err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E,
err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W,
err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S,
err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L,
err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N,
err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E,
err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W,
err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S,
err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L,
err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N,
err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E,
err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W,
err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S,
err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L,
err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N,
err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E,
err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W,
err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S,
err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L,
err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N,
err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E,
err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W,
err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S,
err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L,
err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N,
err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E,
err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W,
err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S,
err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L,
err_grants_valid_not_match: std_logic;
-- Allocator credit_counter logic checker outputs
signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_in Checker signals (part of allocator unit)
-- North Arbiter_in checker outputs
signal N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W,
N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L,
N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S,
N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N,
N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L,
N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E,
N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N,
N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W,
N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E,
N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S,
N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants,
N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L,
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W,
E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L,
E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S,
E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N,
E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L,
E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E,
E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N,
E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W,
E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E,
E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S,
E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants,
E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L,
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W,
W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L,
W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S,
W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N,
W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L,
W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E,
W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N,
W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W,
W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E,
W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S,
W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants,
W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L,
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W,
S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L,
S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S,
S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N,
S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L,
S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E,
S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N,
S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W,
S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E,
S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S,
S_err_arbiter_state_in_onehot,
S_err_no_request_grants,
S_err_request_no_grants,
S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L,
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E,
L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S,
L_err_Local_Req_L, L_err_Local_grant_L,
L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W,
L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L,
L_err_Local_Req_N, L_err_Local_grant_N,
L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S,
L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N,
L_err_Local_Req_E, L_err_Local_grant_E,
L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L,
L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E,
L_err_Local_Req_W, L_err_Local_grant_W,
L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N,
L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W,
L_err_Local_Req_S, L_err_Local_grant_S,
L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants,
L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Arbiter_out Checker signals (part of allocator unit)
-- North Arbiter_out checker outputs
signal N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N,
N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S,
N_err_South_req_X_L, N_err_Local_req_X_N,
N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L,
N_err_South_req_X_N, N_err_Local_req_X_E,
N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N,
N_err_South_req_X_E, N_err_Local_req_X_W,
N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E,
N_err_South_req_X_W, N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N,
E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N,
E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E,
E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W,
E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S,
W_err_South_req_X_L, W_err_Local_req_X_N,
W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L,
W_err_South_req_X_N, W_err_Local_req_X_E,
W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N,
W_err_South_req_X_E, W_err_Local_req_X_W,
W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E,
W_err_South_req_X_W, W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant,
W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N,
S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E,
S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W,
S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N,
L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E,
L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W,
L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero : std_logic;
---------------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------------------
-- Signals needed for grouping checkers to model turn/path faults
signal E_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic;
signal E2S_turn_fault, S2E_turn_fault : std_logic;
signal not_E2S_turn_fault, not_S2E_turn_fault : std_logic;
signal L2E_fault, L2S_fault, E2L_fault, S2L_fault : std_logic;
signal not_L2E_fault, not_L2S_fault, not_E2L_fault, not_S2L_fault : std_logic;
-- Just used temporarily for debugging purposes!
signal E_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic;
signal Allocator_checkers_ORed : std_logic;
--signal turn_faults_sig : std_logic_vector(19 downto 0);
-------------------------------------------------------------------------------------------------
-- Added because of the chain we make for sending faulty values ---------------------------------
-- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ----------------------------
-- then L, N, E, W and S Arbiter_in, --------------------
-- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! --
-------------------------------------------------------------------------------------------------
--TODO: the chains should be fixed!
--Fixed!
signal fault_DO_serial_L_FIFO_to_E_FIFO, fault_DO_serial_E_FIFO_to_S_FIFO: std_logic;
signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_E_LBDR: std_logic;
signal fault_DO_serial_E_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic;
------------------------------------------------------------------
------------------------------------------------------------------
begin
not_E2S_turn_fault <= not E2S_turn_fault;
not_S2E_turn_fault <= not S2E_turn_fault;
not_L2E_fault <= not L2E_fault;
not_L2S_fault <= not L2S_fault;
not_E2L_fault <= not E2L_fault;
not_S2L_fault <= not S2L_fault;
-- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers
-- corresponding to that input are ORed together.
-- East
E_FIFO_checkers_ORed <= E_err_empty_full or
E_err_empty_read_en or
E_err_full_write_en or
E_err_state_in_onehot or
E_err_read_pointer_in_onehot or
E_err_write_pointer_in_onehot or
E_err_write_en_write_pointer or
E_err_not_write_en_write_pointer or
E_err_read_pointer_write_pointer_not_empty or
E_err_read_pointer_write_pointer_empty or
E_err_read_pointer_write_pointer_not_full or
E_err_read_pointer_write_pointer_full or
E_err_read_pointer_increment or
E_err_read_pointer_not_increment or
E_err_write_en or
E_err_not_write_en or
E_err_not_write_en1 or
E_err_not_write_en2 or
E_err_read_en_mismatch or
E_err_read_en_mismatch1 or
E_err_fake_credit_read_en_fake_credit_counter_in_increment or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
E_err_fake_credit_read_en_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
E_err_state_out_Idle_not_fault_out_not_fake_credit or
E_err_state_out_Idle_not_fault_out_not_fault_info_in or
E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Idle_fault_out_fake_credit or
E_err_state_out_Idle_fault_out_state_in_Packet_drop or
E_err_state_out_Idle_fault_out_fault_info_in or
E_err_state_out_Idle_fault_out_faulty_packet_in or
E_err_state_out_Idle_not_health_info or
E_err_state_out_Idle_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
E_err_state_out_Body_flit_valid_in_not_health_info or
E_err_state_out_Body_flit_not_fake_credit or
E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
E_err_state_out_Tail_flit_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
E_err_fault_info_fault_info_out_equal or
E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- South
S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or
S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or
S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or
S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or
S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or
S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or
S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or
S_err_read_en_mismatch1 or
S_err_fake_credit_read_en_fake_credit_counter_in_increment or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
S_err_fake_credit_read_en_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
S_err_state_out_Idle_not_fault_out_not_fake_credit or
S_err_state_out_Idle_not_fault_out_not_fault_info_in or
S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Idle_fault_out_fake_credit or
S_err_state_out_Idle_fault_out_state_in_Packet_drop or
S_err_state_out_Idle_fault_out_fault_info_in or
S_err_state_out_Idle_fault_out_faulty_packet_in or
S_err_state_out_Idle_not_health_info or
S_err_state_out_Idle_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
S_err_state_out_Body_flit_valid_in_not_health_info or
S_err_state_out_Body_flit_not_fake_credit or
S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
S_err_state_out_Tail_flit_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
S_err_fault_info_fault_info_out_equal or
S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
-- Local
L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or
L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or
L_err_write_en_write_pointer or
L_err_not_write_en_write_pointer or
L_err_read_pointer_write_pointer_not_empty or
L_err_read_pointer_write_pointer_empty or
L_err_read_pointer_write_pointer_not_full or
L_err_read_pointer_write_pointer_full or
L_err_read_pointer_increment or
L_err_read_pointer_not_increment or
L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or
L_err_read_en_mismatch or L_err_read_en_mismatch1 or
L_err_fake_credit_read_en_fake_credit_counter_in_increment or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or
L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or
L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or
L_err_fake_credit_read_en_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or
L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or
L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or
L_err_state_out_Idle_not_fault_out_not_fake_credit or
L_err_state_out_Idle_not_fault_out_not_fault_info_in or
L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Idle_fault_out_fake_credit or
L_err_state_out_Idle_fault_out_state_in_Packet_drop or
L_err_state_out_Idle_fault_out_fault_info_in or
L_err_state_out_Idle_fault_out_faulty_packet_in or
L_err_state_out_Idle_not_health_info or
L_err_state_out_Idle_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or
L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or
L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or
L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or
L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or
L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or
L_err_state_out_Body_flit_valid_in_not_health_info or
L_err_state_out_Body_flit_not_fake_credit or
L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or
L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or
L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or
L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or
L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or
L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or
L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or
L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or
L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or
L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or
L_err_state_out_Tail_flit_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or
L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or
L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or
L_err_fault_info_fault_info_out_equal or
L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or
L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or
L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or
L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in;
------------------------------------------------------------------------------------------------------------------------------
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-- Just for debugging purposes of the checkers!
-- LBDR checker outputs ORed
-- East
-- Routing part checkers
E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_N1 or
E_err_dst_addr_cur_addr_not_N1 or
E_err_dst_addr_cur_addr_E1 or
E_err_dst_addr_cur_addr_not_E1 or
E_err_dst_addr_cur_addr_W1 or
E_err_dst_addr_cur_addr_not_W1 or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--E_err_header_not_empty_Req_L_in or -- added according to new design
E_err_header_not_empty_Req_N_in or
E_err_header_not_empty_Req_E_in or
E_err_header_not_empty_Req_W_in or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
-- Cx_Reconf checkers
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- South
-- Routing part checkers
S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_N1 or
S_err_dst_addr_cur_addr_not_N1 or
S_err_dst_addr_cur_addr_E1 or
S_err_dst_addr_cur_addr_not_E1 or
S_err_dst_addr_cur_addr_W1 or
S_err_dst_addr_cur_addr_not_W1 or
S_err_dst_addr_cur_addr_S1 or
S_err_dst_addr_cur_addr_not_S1 or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--S_err_header_not_empty_Req_L_in or -- added according to new design
S_err_header_not_empty_Req_N_in or
S_err_header_not_empty_Req_E_in or
S_err_header_not_empty_Req_W_in or
S_err_header_not_empty_Req_S_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
-- Cx_Reconf checkers
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
-- Local
-- Routing part checkers
L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or
L_err_tail_Requests_in_all_zero or
L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
L_err_grants_onehot or
L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or
L_err_dst_addr_cur_addr_N1 or
L_err_dst_addr_cur_addr_not_N1 or
L_err_dst_addr_cur_addr_E1 or
L_err_dst_addr_cur_addr_not_E1 or
L_err_dst_addr_cur_addr_W1 or
L_err_dst_addr_cur_addr_not_W1 or
L_err_dst_addr_cur_addr_S1 or
L_err_dst_addr_cur_addr_not_S1 or
L_err_dst_addr_cur_addr_Req_L_in or
L_err_dst_addr_cur_addr_not_Req_L_in or
L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design
L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design
L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design
--L_err_header_not_empty_Req_L_in or -- added according to new design
L_err_header_not_empty_Req_N_in or
L_err_header_not_empty_Req_E_in or
L_err_header_not_empty_Req_W_in or
L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
-- Cx_Reconf checkers
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Rxy_Reconf checkers
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal;
------------------------------------------------------------------------------------------------------------------------------
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-- Allocator checker outputs ORed !
-- Allocator logic checker outputs
Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or
err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or
err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or
err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or
err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or
err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or
err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or
err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or
err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or
err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or
err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or
err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or
err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or
err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or
err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or
err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or
err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or
err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or
err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or
err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or
err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or
err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or
err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or
err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or
err_grants_valid_not_match or
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_N_credit_counter_N_out_increment or
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or
err_grant_N_credit_counter_N_out_decrement or
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_W_credit_counter_W_out_increment or
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or
err_grant_W_credit_counter_W_out_decrement or
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or
err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or
-- Arbiter_in checker outputs
-- North Arbiter_in checker outputs
N_err_Requests_state_in_state_not_equal or
N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or
N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or
N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or
N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or
N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or
N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or
N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or
N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or
N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or
N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or
N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or
N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or
N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or
N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or
N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or
N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or
N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or
N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or
-- East Arbiter_in checker outputs
E_err_Requests_state_in_state_not_equal or
E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or
E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or
E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or
E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or
E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or
E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or
E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or
E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or
E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or
E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or
E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or
E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or
E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or
E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or
E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or
E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or
-- West Arbiter_in checker outputs
W_err_Requests_state_in_state_not_equal or
W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or
W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or
W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or
W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or
W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or
W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or
W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or
W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or
W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or
W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or
W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or
W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or
W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or
W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or
W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or
W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or
W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or
W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or
-- South Arbiter_in checker outputs
S_err_Requests_state_in_state_not_equal or
S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or
S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or
S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or
S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or
S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or
S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or
S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or
S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or
S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or
S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or
S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or
S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or
S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or
S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or
S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or
S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or
-- Local Arbiter_in checker outputs
L_err_Requests_state_in_state_not_equal or
L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or
L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or
L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or
L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or
L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or
L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or
L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or
L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or
L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or
L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or
L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or
L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or
L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or
L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or
L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or
L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal or
N_err_IDLE_req_X_N or
N_err_North_req_X_N or
N_err_North_credit_not_zero_req_X_N_grant_N or
N_err_North_credit_zero_or_not_req_X_N_not_grant_N or
N_err_East_req_X_E or
N_err_East_credit_not_zero_req_X_E_grant_E or
N_err_East_credit_zero_or_not_req_X_E_not_grant_E or
N_err_West_req_X_W or
N_err_West_credit_not_zero_req_X_W_grant_W or
N_err_West_credit_zero_or_not_req_X_W_not_grant_W or
N_err_South_req_X_S or
N_err_South_credit_not_zero_req_X_S_grant_S or
N_err_South_credit_zero_or_not_req_X_S_not_grant_S or
N_err_Local_req_X_L or
N_err_Local_credit_not_zero_req_X_L_grant_L or
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
N_err_IDLE_req_X_E or
N_err_North_req_X_E or
N_err_East_req_X_W or
N_err_West_req_X_S or
N_err_South_req_X_L or
N_err_Local_req_X_N or
N_err_IDLE_req_X_W or
N_err_North_req_X_W or
N_err_East_req_X_S or
N_err_West_req_X_L or
N_err_South_req_X_N or
N_err_Local_req_X_E or
N_err_IDLE_req_X_S or
N_err_North_req_X_S or
N_err_East_req_X_L or
N_err_West_req_X_N or
N_err_South_req_X_E or
N_err_Local_req_X_W or
N_err_IDLE_req_X_L or
N_err_North_req_X_L or
N_err_East_req_X_N or
N_err_West_req_X_E or
N_err_South_req_X_W or
N_err_Local_req_X_S or
N_arbiter_out_err_state_in_onehot or
N_arbiter_out_err_no_request_grants or
N_err_request_IDLE_state or
N_err_request_IDLE_not_Grants or
N_err_state_North_Invalid_Grant or
N_err_state_East_Invalid_Grant or
N_err_state_West_Invalid_Grant or
N_err_state_South_Invalid_Grant or
N_err_state_Local_Invalid_Grant or
N_err_Grants_onehot_or_all_zero or
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal or
E_err_IDLE_req_X_N or
E_err_North_req_X_N or
E_err_North_credit_not_zero_req_X_N_grant_N or
E_err_North_credit_zero_or_not_req_X_N_not_grant_N or
E_err_East_req_X_E or
E_err_East_credit_not_zero_req_X_E_grant_E or
E_err_East_credit_zero_or_not_req_X_E_not_grant_E or
E_err_West_req_X_W or
E_err_West_credit_not_zero_req_X_W_grant_W or
E_err_West_credit_zero_or_not_req_X_W_not_grant_W or
E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or
E_err_South_credit_zero_or_not_req_X_S_not_grant_S or
E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or
E_err_Local_req_X_N or
E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or
E_err_Local_req_X_E or
E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or
E_err_Local_req_X_W or
E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or
E_err_Local_req_X_S or
E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or
E_err_request_IDLE_state or
E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or
E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or
E_err_Grants_onehot_or_all_zero or
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal or
W_err_IDLE_req_X_N or
W_err_North_req_X_N or
W_err_North_credit_not_zero_req_X_N_grant_N or
W_err_North_credit_zero_or_not_req_X_N_not_grant_N or
W_err_East_req_X_E or
W_err_East_credit_not_zero_req_X_E_grant_E or
W_err_East_credit_zero_or_not_req_X_E_not_grant_E or
W_err_West_req_X_W or
W_err_West_credit_not_zero_req_X_W_grant_W or
W_err_West_credit_zero_or_not_req_X_W_not_grant_W or
W_err_South_req_X_S or
W_err_South_credit_not_zero_req_X_S_grant_S or
W_err_South_credit_zero_or_not_req_X_S_not_grant_S or
W_err_Local_req_X_L or
W_err_Local_credit_not_zero_req_X_L_grant_L or
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or
W_err_Local_req_X_N or
W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or
W_err_Local_req_X_E or
W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or
W_err_Local_req_X_W or
W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or
W_err_Local_req_X_S or
W_arbiter_out_err_state_in_onehot or
W_arbiter_out_err_no_request_grants or
W_err_request_IDLE_state or
W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or
W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or
W_err_Grants_onehot_or_all_zero or
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal or
S_err_IDLE_req_X_N or
S_err_North_req_X_N or
S_err_North_credit_not_zero_req_X_N_grant_N or
S_err_North_credit_zero_or_not_req_X_N_not_grant_N or
S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or
S_err_East_credit_zero_or_not_req_X_E_not_grant_E or
S_err_West_req_X_W or
S_err_West_credit_not_zero_req_X_W_grant_W or
S_err_West_credit_zero_or_not_req_X_W_not_grant_W or
S_err_South_req_X_S or
S_err_South_credit_not_zero_req_X_S_grant_S or
S_err_South_credit_zero_or_not_req_X_S_not_grant_S or
S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or
S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or
S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or
S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or
S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or
S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or
S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or
S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or
S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or
S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or
S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or
S_err_Grants_onehot_or_all_zero or
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal or
L_err_IDLE_req_X_N or
L_err_North_req_X_N or
L_err_North_credit_not_zero_req_X_N_grant_N or
L_err_North_credit_zero_or_not_req_X_N_not_grant_N or
L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or
L_err_East_credit_zero_or_not_req_X_E_not_grant_E or
L_err_West_req_X_W or
L_err_West_credit_not_zero_req_X_W_grant_W or
L_err_West_credit_zero_or_not_req_X_W_not_grant_W or
L_err_South_req_X_S or
L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or
L_err_Local_req_X_L or
L_err_Local_credit_not_zero_req_X_L_grant_L or
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or
L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or
L_err_Local_req_X_N or
L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or
L_err_Local_req_X_E or
L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or
L_err_Local_req_X_W or
L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or
L_err_Local_req_X_S or
L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or
L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or
L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or
L_err_Grants_onehot_or_all_zero;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- Turn fault checkers
-- FIFO
E2S_turn_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_S1 or
E_err_dst_addr_cur_addr_not_S1 or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
E_err_header_not_empty_Req_S_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or
E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or
E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or
S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or
S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
S2E_turn_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or
S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or
S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or
S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or
S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or
E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or
E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or
err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or
err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
L2E_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or
L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or
L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or
L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or
E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or
E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or
E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or
err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or
err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal;
-- FIFO
L2S_fault <= L_FIFO_checkers_ORed or
-- LBDR
L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or
L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or
L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or
L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or
L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or
L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
L_err_packet_drop_order or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or
L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or
L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or
L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or
S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or
S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or
S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or
err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or
err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal;
-- FIFO
E2L_fault <= E_FIFO_checkers_ORed or
-- LBDR
E_err_header_empty_Requests_FF_Requests_in or
E_err_tail_Requests_in_all_zero or
E_err_tail_empty_Requests_FF_Requests_in or
E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
E_err_grants_onehot or
E_err_grants_mismatch or
E_err_header_tail_Requests_FF_Requests_in or
E_err_dst_addr_cur_addr_Req_L_in or
E_err_dst_addr_cur_addr_not_Req_L_in or
E_err_header_not_empty_faulty_drop_packet_in or
E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
E_err_header_not_empty_faulty_Req_in_all_zero or
--E_err_header_not_empty_Req_L_in or
E_err_header_empty_packet_drop_in_packet_drop_equal or
E_err_tail_not_empty_packet_drop_not_packet_drop_in or
E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
E_err_packet_drop_order or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or
E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or
E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or
E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or
L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or
L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or
L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
-- FIFO
S2L_fault <= S_FIFO_checkers_ORed or
-- LBDR
S_err_header_empty_Requests_FF_Requests_in or
S_err_tail_Requests_in_all_zero or
S_err_tail_empty_Requests_FF_Requests_in or
S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or
S_err_grants_onehot or
S_err_grants_mismatch or
S_err_header_tail_Requests_FF_Requests_in or
S_err_dst_addr_cur_addr_Req_L_in or
S_err_dst_addr_cur_addr_not_Req_L_in or
S_err_header_not_empty_faulty_drop_packet_in or
S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or
S_err_header_not_empty_faulty_Req_in_all_zero or
--S_err_header_not_empty_Req_L_in or
S_err_header_empty_packet_drop_in_packet_drop_equal or
S_err_tail_not_empty_packet_drop_not_packet_drop_in or
S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or
S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or
S_err_packet_drop_order or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or
S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or
S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or
S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added
S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added
-- Allocator
S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or
S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or
S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or
S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or
L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or
L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or
L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or
L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or
err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or
err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or
err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal;
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-- Link faults and turn faults
-- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits
-- N2E, N2W, E2N, E2S,
-- W2N, W2S, S2E, S2W,
-- N2S, S2N, E2W, W2E,
-- L2N, L2E, L2W, L2S,
-- N2L, E2L, W2L, S2L
------------------------------------------------------------------------------------------------------------------------------
-- Taking classified fault information to output
------------------------------------------------------------------------------------------------------------------------------
turn_faults <= '0' & '0' & '0' & faulty_E2S_turn_fault & -- faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault &
'0' & '0' & faulty_S2E_turn_fault & '0' & -- faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault &
'0' & '0' & '0' & '0' & -- faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault &
'0' & faulty_L2E_fault & '0' & faulty_L2S_fault & -- faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault &
'0' & faulty_E2L_fault & '0' & faulty_S2L_fault; -- faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; 20 bits because of turn/path faults
link_faults <= '0' & sig_Faulty_E_out & '0' & sig_Faulty_S_out & faulty_link_L; -- sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
------------------------------------------------------------------------------------------------------------------------------
-- Taking non-classified fault information to output
------------------------------------------------------------------------------------------------------------------------------
turn_faults_async <= '0' & '0' & '0' & E2S_turn_fault & -- N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault &
'0' & '0' & S2E_turn_fault & '0' & -- W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault &
'0' & '0' & '0' & '0' & -- N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault &
'0' & L2E_fault & '0' & L2S_fault & -- L2N_fault & L2E_fault & L2W_fault & L2S_fault
'0' & E2L_fault & '0' & S2L_fault; -- N2L_fault & E2L_fault & W2L_fault & S2L_fault; 20 bits because of turn/path faults
link_faults_async <= '0' & faulty_packet_E & '0' & faulty_packet_S & faulty_packet_L; -- faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
------------------------------------------------------------------------------------------------------------------------------
Faulty_E_out <= sig_Faulty_E_out; --sig_Faulty_E_out;
Faulty_S_out <= sig_Faulty_S_out; --sig_Faulty_S_out;
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the counter_threshold modules
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
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------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Checker Counter Threshold modules
-- Turn faults
CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault,
Healthy => Healthy_E2S_turn_fault, Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault);
CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault,
Healthy => Healthy_S2E_turn_fault, Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault);
CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault,
Healthy => Healthy_L2E_fault, Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault);
CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault,
Healthy => Healthy_L2S_fault, Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault);
CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault,
Healthy => Healthy_E2L_fault, Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault);
CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault,
Healthy => Healthy_S2L_fault, Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => '0', read_en_E =>packet_drop_order_E, read_en_W =>'0', read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_S_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en,
err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => E_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => E_err_write_en_write_pointer,
err_not_write_en_write_pointer => E_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full,
err_read_pointer_increment => E_err_read_pointer_increment,
err_read_pointer_not_increment => E_err_read_pointer_not_increment,
err_write_en => E_err_write_en,
err_not_write_en => E_err_not_write_en,
err_not_write_en1 => E_err_not_write_en1,
err_not_write_en2 => E_err_not_write_en2,
err_read_en_mismatch => E_err_read_en_mismatch,
err_read_en_mismatch1 => E_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => '0', read_en_E =>Grant_ES, read_en_W =>'0', read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR,
-- Checker outputs
-- Functional checkers
err_empty_full => S_err_empty_full,
err_empty_read_en => S_err_empty_read_en,
err_full_write_en => S_err_full_write_en,
err_state_in_onehot => S_err_state_in_onehot,
err_read_pointer_in_onehot => S_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => S_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => S_err_write_en_write_pointer,
err_not_write_en_write_pointer => S_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full,
err_read_pointer_increment => S_err_read_pointer_increment,
err_read_pointer_not_increment => S_err_read_pointer_not_increment,
err_write_en => S_err_write_en,
err_not_write_en => S_err_not_write_en,
err_not_write_en1 => S_err_not_write_en1,
err_not_write_en2 => S_err_not_write_en2,
err_read_en_mismatch => S_err_read_en_mismatch,
err_read_en_mismatch1 => S_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => '0', read_en_E =>Grant_EL, read_en_W =>'0', read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L,
TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_E_FIFO,
-- Checker outputs
-- Functional checkers
err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en,
err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot,
err_write_pointer_in_onehot => L_err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => L_err_write_en_write_pointer,
err_not_write_en_write_pointer => L_err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full,
err_read_pointer_increment => L_err_read_pointer_increment,
err_read_pointer_not_increment => L_err_read_pointer_not_increment,
err_write_en => L_err_write_en,
err_not_write_en => L_err_not_write_en,
err_not_write_en1 => L_err_not_write_en1,
err_not_write_en2 => L_err_not_write_en2,
err_read_en_mismatch => L_err_read_en_mismatch,
err_read_en_mismatch1 => L_err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
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parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
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LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => '0', Faulty_C_E => Faulty_E_in, Faulty_C_W => '0', Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E,
grant_N => '0', grant_E =>'0', grant_W => '0', grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> open, Req_E=>Req_EE, Req_W=>open, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_S_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => E_err_grants_onehot,
err_grants_mismatch => E_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => E_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => '0', Faulty_C_E => Faulty_E_in, Faulty_C_W => '0', Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S,
grant_N => '0', grant_E =>Grant_ES, grant_W =>'0' ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> open, Req_E=>Req_SE, Req_W=>open, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => S_err_grants_onehot,
err_grants_mismatch => S_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => S_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => '0', Faulty_C_E => Faulty_E_in, Faulty_C_W => '0', Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L,
grant_N => '0', grant_E =>Grant_EL, grant_W => '0', grant_S=>Grant_SL, grant_L =>'0',
Req_N=> open, Req_E=>Req_LE, Req_W=>open, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_E_LBDR,
-- Checker outputs
err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot => L_err_grants_onehot,
err_grants_mismatch => L_err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order => L_err_packet_drop_order,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal
);
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-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => '0', credit_in_E => credit_in_E, credit_in_W => '0', credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => '0', req_N_W => '0', req_N_S => '0', req_N_L => '0',
req_E_N => '0', req_E_E => '0', req_E_W => '0', req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => '0', req_W_E => '0', req_W_W => '0', req_W_S => '0', req_W_L => '0',
req_S_N => '0', req_S_E => Req_SE, req_S_W => '0', req_S_S => '0', req_S_L => Req_SL,
req_L_N => '0', req_L_E => Req_LE, req_L_W => '0', req_L_S => Req_LS, req_L_L => '0',
empty_N => '0', empty_E => empty_E, empty_W => '0', empty_S => empty_S, empty_L => empty_L,
valid_N => open, valid_E => valid_out_E, valid_W => open, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => open, grant_N_E => open, grant_N_W => open, grant_N_S => open, grant_N_L => open,
grant_E_N => open, grant_E_E => open, grant_E_W => open, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => open, grant_W_E => open, grant_W_W => open, grant_W_S => open, grant_W_L => open,
grant_S_N => open, grant_S_E => Grant_SE, grant_S_W => open, grant_S_S => open, grant_S_L => Grant_SL,
grant_L_N => open, grant_L_E => Grant_LE, grant_L_W => open, grant_L_S => Grant_LS, grant_L_L => open,
TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO,
-- Checker outputs
-- Allocator logic checker outputs
err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N ,
err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N ,
err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E ,
err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E ,
err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W ,
err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W ,
err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S ,
err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S ,
err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L ,
err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L ,
err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N ,
err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N ,
err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E ,
err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E ,
err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W ,
err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W ,
err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S ,
err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S ,
err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L ,
err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L ,
err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N ,
err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N ,
err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E ,
err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E ,
err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W ,
err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W ,
err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S ,
err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S ,
err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L ,
err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L ,
err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N ,
err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N ,
err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E ,
err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E ,
err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W ,
err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W ,
err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S ,
err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S ,
err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L ,
err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L ,
err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N ,
err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N ,
err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E ,
err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E ,
err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W ,
err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W ,
err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S ,
err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S ,
err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L ,
err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L ,
err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N ,
err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N ,
err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E ,
err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E ,
err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W ,
err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W ,
err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S ,
err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S ,
err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L ,
err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L ,
err_grants_valid_not_match => err_grants_valid_not_match ,
-- Allocator credit counter logic checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment ,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change ,
err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement ,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change ,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal ,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment ,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change ,
err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement ,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change ,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal ,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment ,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change ,
err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement ,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change ,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal ,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment ,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change ,
err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement ,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change ,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal ,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment ,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change ,
err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement ,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change ,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal ,
-- North Arbiter_in Checker outputs
N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal,
N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N,
N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E,
N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S,
N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L,
N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E,
N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W,
N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L,
N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N,
N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W,
N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S,
N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N,
N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E,
N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S,
N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L,
N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E,
N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W,
N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L,
N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N,
N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W,
N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S,
N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants,
N_err_request_no_grants => N_err_request_no_grants,
N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E,
N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S,
N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L,
-- East Arbiter_in Checker outputs
E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal,
E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N,
E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E,
E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S,
E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L,
E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E,
E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W,
E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L,
E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N,
E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W,
E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S,
E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N,
E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E,
E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S,
E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L,
E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E,
E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W,
E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L,
E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N,
E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W,
E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S,
E_err_state_in_onehot => E_err_arbiter_state_in_onehot,
E_err_no_request_grants => E_err_no_request_grants,
E_err_request_no_grants => E_err_request_no_grants,
E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E,
E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S,
E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L,
-- West Arbiter_in Checker outputs
W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal,
W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N,
W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E,
W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S,
W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L,
W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E,
W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W,
W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L,
W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N,
W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W,
W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S,
W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N,
W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E,
W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S,
W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L,
W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E,
W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W,
W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L,
W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N,
W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W,
W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S,
W_err_state_in_onehot => W_err_arbiter_state_in_onehot,
W_err_no_request_grants => W_err_no_request_grants,
W_err_request_no_grants => W_err_request_no_grants,
W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E,
W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S,
W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L,
-- South Arbiter_in Checker outputs
S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal,
S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N,
S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E,
S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S,
S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L,
S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E,
S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W,
S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L,
S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N,
S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W,
S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S,
S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N,
S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E,
S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S,
S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L,
S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E,
S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W,
S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L,
S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N,
S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W,
S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S,
S_err_state_in_onehot => S_err_arbiter_state_in_onehot,
S_err_no_request_grants => S_err_no_request_grants,
S_err_request_no_grants => S_err_request_no_grants,
S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E,
S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S,
S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L,
-- Local Arbiter_in Checker outputs
L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal,
L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N,
L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E,
L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S,
L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L,
L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E,
L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W,
L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L,
L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N,
L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W,
L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S,
L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N,
L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E,
L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S,
L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L,
L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E,
L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W,
L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L,
L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N,
L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W,
L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S,
L_err_state_in_onehot => L_err_arbiter_state_in_onehot,
L_err_no_request_grants => L_err_no_request_grants,
L_err_request_no_grants => L_err_request_no_grants,
L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E,
L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S,
L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L,
-- Arbiter_out checker outputs
-- North Arbiter_out checker outputs
N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal,
N_err_IDLE_req_X_N => N_err_IDLE_req_X_N,
N_err_North_req_X_N => N_err_North_req_X_N,
N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N,
N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N,
N_err_East_req_X_E => N_err_East_req_X_E,
N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E,
N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E,
N_err_West_req_X_W => N_err_West_req_X_W,
N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W,
N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W,
N_err_South_req_X_S => N_err_South_req_X_S,
N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S,
N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S,
N_err_Local_req_X_L => N_err_Local_req_X_L,
N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L,
N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W,
N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N,
N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S,
N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E,
N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L,
N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W,
N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N,
N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S,
N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot,
N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants,
N_err_request_IDLE_state => N_err_request_IDLE_state,
N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants,
N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant,
N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant,
N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant,
N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant,
N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant,
N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero,
-- East Arbiter_out checker outputs
E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal,
E_err_IDLE_req_X_N => E_err_IDLE_req_X_N,
E_err_North_req_X_N => E_err_North_req_X_N,
E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N,
E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N,
E_err_East_req_X_E => E_err_East_req_X_E,
E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E,
E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E,
E_err_West_req_X_W => E_err_West_req_X_W,
E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W,
E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W,
E_err_South_req_X_S => E_err_South_req_X_S,
E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S,
E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S,
E_err_Local_req_X_L => E_err_Local_req_X_L,
E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L,
E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W,
E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N,
E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S,
E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E,
E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L,
E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W,
E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N,
E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S,
E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot,
E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants,
E_err_request_IDLE_state => E_err_request_IDLE_state,
E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants,
E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant,
E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant,
E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant,
E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant,
E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant,
E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero,
-- West Arbiter_out checker outputs
W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal,
W_err_IDLE_req_X_N => W_err_IDLE_req_X_N,
W_err_North_req_X_N => W_err_North_req_X_N,
W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N,
W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N,
W_err_East_req_X_E => W_err_East_req_X_E,
W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E,
W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E,
W_err_West_req_X_W => W_err_West_req_X_W,
W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W,
W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W,
W_err_South_req_X_S => W_err_South_req_X_S,
W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S,
W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S,
W_err_Local_req_X_L => W_err_Local_req_X_L,
W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L,
W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W,
W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N,
W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S,
W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E,
W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L,
W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W,
W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N,
W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S,
W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot,
W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants,
W_err_request_IDLE_state => W_err_request_IDLE_state,
W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant,
W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant,
W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant,
W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero,
-- South Arbiter_out checker outputs
S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal,
S_err_IDLE_req_X_N => S_err_IDLE_req_X_N,
S_err_North_req_X_N => S_err_North_req_X_N,
S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N,
S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N,
S_err_East_req_X_E => S_err_East_req_X_E,
S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E,
S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E,
S_err_West_req_X_W => S_err_West_req_X_W,
S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W,
S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W,
S_err_South_req_X_S => S_err_South_req_X_S,
S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S,
S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S,
S_err_Local_req_X_L => S_err_Local_req_X_L,
S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L,
S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W,
S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N,
S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S,
S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E,
S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L,
S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W,
S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N,
S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S,
S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot,
S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants,
S_err_request_IDLE_state => S_err_request_IDLE_state,
S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant,
S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant,
S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant,
S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero,
-- Local Arbiter_out checker outputs
L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal,
L_err_IDLE_req_X_N => L_err_IDLE_req_X_N,
L_err_North_req_X_N => L_err_North_req_X_N,
L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N,
L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N,
L_err_East_req_X_E => L_err_East_req_X_E,
L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E,
L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E,
L_err_West_req_X_W => L_err_West_req_X_W,
L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W,
L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W,
L_err_South_req_X_S => L_err_South_req_X_S,
L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S,
L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S,
L_err_Local_req_X_L => L_err_Local_req_X_L,
L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L,
L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L,
L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W,
L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N,
L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S,
L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E,
L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L,
L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W,
L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N,
L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S,
L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot,
L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants,
L_err_request_IDLE_state => L_err_request_IDLE_state,
L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants,
L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant,
L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant,
L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant,
L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant,
L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant,
L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_E <= '0' & '0' & '0' & Grant_ES & Grant_EL;
Xbar_sel_S <= '0' & Grant_SE & '0' & '0' & Grant_SL;
Xbar_sel_L <= '0' & Grant_LE & '0' & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
-- Correct ?!
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => (others =>'0'), East_in => FIFO_D_out_E, West_in => (others =>'0'), South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => (others =>'0'), East_in => FIFO_D_out_E, West_in => (others =>'0'), South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => (others =>'0'), East_in => FIFO_D_out_E, West_in => (others =>'0'), South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
end;
|
gpl-3.0
|
domagalski/pocketcorr
|
fpga/snap/pfb_fir_2048ch_core.vhd
|
1
|
4209
|
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_core_ip is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end pfb_fir_2048ch_core_ip;
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_core_ip_struct is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 )
);
end pfb_fir_2048ch_core_ip_struct;
architecture structural of pfb_fir_2048ch_core_ip_struct is
component pfb_fir_2048ch_core_ip
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol2_in0 : in std_logic_vector( 8-1 downto 0 );
pol2_in1 : in std_logic_vector( 8-1 downto 0 );
pol3_in0 : in std_logic_vector( 8-1 downto 0 );
pol3_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol2_out0 : out std_logic_vector( 18-1 downto 0 );
pol3_out0 : out std_logic_vector( 18-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
pol2_out1 : out std_logic_vector( 18-1 downto 0 );
pol3_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end component;
begin
pfb_fir_2048ch_core_ip_inst : pfb_fir_2048ch_core_ip
port map (
pol0_in0 => pol0_in0,
pol1_in0 => pol1_in0,
sync => sync,
pol2_in0 => pol2_in0,
pol2_in1 => pol2_in1,
pol3_in0 => pol3_in0,
pol3_in1 => pol3_in1,
pol0_in1 => pol0_in1,
pol1_in1 => pol1_in1,
clk => clk_1,
pol0_out0 => pol0_out0,
pol1_out0 => pol1_out0,
sync_out => sync_out,
pol2_out0 => pol2_out0,
pol3_out0 => pol3_out0,
pol0_out1 => pol0_out1,
pol1_out1 => pol1_out1,
pol2_out1 => pol2_out1,
pol3_out1 => pol3_out1
);
end structural;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/ASCII_CONV.vhd
|
3
|
491
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY ASCII_CONV IS
PORT( ASCII : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CMAP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END ASCII_CONV;
ARCHITECTURE main OF ASCII_CONV IS
BEGIN
PROCESS(ASCII)
BEGIN
--IF(ASCII < x"20") THEN
-- CMAP <= "1011111";
--ELSE
-- CMAP <= ASCII(6 DOWNTO 0) - "0100000"; -- ASCII - 32
--END IF;
CMAP <= ASCII(6 DOWNTO 0);
END PROCESS;
END main;
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_in_one_hot_with_checkers_with_FI.vhd
|
3
|
13338
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use work.component_pack.all;
-- Is this like the old arbiter in the router with handshaking FC ??
entity Arbiter_in is
port ( reset: in std_logic;
clk: in std_logic;
Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules
X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E,
err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L,
err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W,
err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N,
err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S,
err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E,
err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L,
err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W,
err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N,
err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S,
err_state_in_onehot, err_no_request_grants, err_request_no_grants,
err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic
);
end Arbiter_in;
architecture behavior of Arbiter_in is
component shift_register_serial_in is
generic (
REG_WIDTH: integer := 32
);
port (
TCK, reset : in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0)
);
end component;
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 7 bits
signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
----------------------------------------
----------------------------------------
--TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
--SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
--SIGNAL state, state_in : STATE_TYPE := IDLE;
SIGNAL state, state_in : STD_LOGIC_VECTOR (5 downto 0) := IDLE;
SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports
-- of Arbiter_in to checker inputs
-- Signal(s) used for creating the chain of injected fault locations
-- Total: 17 bits ??!!
-- Arbiter_in internal-related signals
signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0);
-- Arbiter_in output-related signals
signal X_N_sig_faulty, X_E_sig_faulty, X_W_sig_faulty, X_S_sig_faulty, X_L_sig_faulty: std_logic;
begin
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 17 bits
-- for X_N, ... , X_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!!
non_faulty_signals <= state & state_in & X_N_sig & X_E_sig & X_W_sig & X_S_sig & X_L_sig;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5)
port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 17 bits
state_faulty <= faulty_signals (16 downto 11);
state_in_faulty <= faulty_signals (10 downto 5);
X_N_sig_faulty <= faulty_signals (4);
X_E_sig_faulty <= faulty_signals (3);
X_W_sig_faulty <= faulty_signals (2);
X_S_sig_faulty <= faulty_signals (1);
X_L_sig_faulty <= faulty_signals (0);
-- Total: 7 bits
SR: shift_register_serial_in generic map(REG_WIDTH => 7)
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta
);
-------------------------------------
-------------------------------------
-- Becuase of checkers we did this
X_N <= X_N_sig;
X_E <= X_E_sig;
X_W <= X_W_sig;
X_S <= X_S_sig;
X_L <= X_L_sig;
-- Arbiter_in Checkers module instantiation
ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map (
req_X_N => req_X_N, -- _sig not needed, because it is an input port
req_X_E => req_X_E, -- _sig not needed, because it is an input port
req_X_W => req_X_W, -- _sig not needed, because it is an input port
req_X_S => req_X_S, -- _sig not needed, because it is an input port
req_X_L => req_X_L, -- _sig not needed, because it is an input port
state => state_faulty, -- _sig not needed, because it is an input port
state_in => state_in_faulty, -- _sig not needed, because it is an internal signal
X_N => X_N_sig_faulty, X_E => X_E_sig_faulty, X_W => X_W_sig_faulty,
X_S => X_S_sig_faulty, X_L => X_L_sig_faulty,
-- Checker outputs
err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal,
err_IDLE_Req_N => err_IDLE_Req_N, err_IDLE_grant_N => err_IDLE_grant_N,
err_North_Req_N => err_North_Req_N, err_North_grant_N => err_North_grant_N,
err_East_Req_E => err_East_Req_E, err_East_grant_E => err_East_grant_E,
err_West_Req_W => err_West_Req_W, err_West_grant_W => err_West_grant_W,
err_South_Req_S => err_South_Req_S, err_South_grant_S => err_South_grant_S,
err_Local_Req_L => err_Local_Req_L, err_Local_grant_L => err_Local_grant_L,
err_IDLE_Req_E => err_IDLE_Req_E, err_IDLE_grant_E => err_IDLE_grant_E,
err_North_Req_E => err_North_Req_E, err_North_grant_E => err_North_grant_E,
err_East_Req_W => err_East_Req_W, err_East_grant_W => err_East_grant_W,
err_West_Req_S => err_West_Req_S, err_West_grant_S => err_West_grant_S,
err_South_Req_L => err_South_Req_L, err_South_grant_L => err_South_grant_L,
err_Local_Req_N => err_Local_Req_N, err_Local_grant_N => err_Local_grant_N,
err_IDLE_Req_W => err_IDLE_Req_W, err_IDLE_grant_W => err_IDLE_grant_W,
err_North_Req_W => err_North_Req_W, err_North_grant_W => err_North_grant_W,
err_East_Req_S => err_East_Req_S, err_East_grant_S => err_East_grant_S,
err_West_Req_L => err_West_Req_L, err_West_grant_L => err_West_grant_L,
err_South_Req_N => err_South_Req_N, err_South_grant_N => err_South_grant_N,
err_Local_Req_E => err_Local_Req_E, err_Local_grant_E => err_Local_grant_E,
err_IDLE_Req_S => err_IDLE_Req_S, err_IDLE_grant_S => err_IDLE_grant_S,
err_North_Req_S => err_North_Req_S, err_North_grant_S => err_North_grant_S,
err_East_Req_L => err_East_Req_L, err_East_grant_L => err_East_grant_L,
err_West_Req_N => err_West_Req_N, err_West_grant_N => err_West_grant_N,
err_South_Req_E => err_South_Req_E, err_South_grant_E => err_South_grant_E,
err_Local_Req_W => err_Local_Req_W, err_Local_grant_W => err_Local_grant_W,
err_IDLE_Req_L => err_IDLE_Req_L, err_IDLE_grant_L => err_IDLE_grant_L,
err_North_Req_L => err_North_Req_L, err_North_grant_L => err_North_grant_L,
err_East_Req_N => err_East_Req_N, err_East_grant_N => err_East_grant_N,
err_West_Req_E => err_West_Req_E, err_West_grant_E => err_West_grant_E,
err_South_Req_W => err_South_Req_W, err_South_grant_W => err_South_grant_W,
err_Local_Req_S => err_Local_Req_S, err_Local_grant_S => err_Local_grant_S,
err_state_in_onehot => err_state_in_onehot,
err_no_request_grants => err_no_request_grants,
err_request_no_grants => err_request_no_grants,
err_no_Req_N_grant_N => err_no_Req_N_grant_N, err_no_Req_E_grant_E => err_no_Req_E_grant_E,
err_no_Req_W_grant_W => err_no_Req_W_grant_W, err_no_Req_S_grant_S => err_no_Req_S_grant_S,
err_no_Req_L_grant_L => err_no_Req_L_grant_L
);
-- Sequential part
process (clk, reset)begin
if reset = '0' then
state <= IDLE;
elsif clk'event and clk ='1'then
state <= state_in;
end if;
end process;
-- anything below here is pure combinational
-- Main Logic of Arbiter_in
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L)
begin
X_N_sig <= '0';
X_E_sig <= '0';
X_W_sig <= '0';
X_S_sig <= '0';
X_L_sig <= '0';
case state is
when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S)
-- Here it seems N has the higest priority, is it fine ?
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when North =>
if req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
else
state_in <= state;
end if;
when East =>
if req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
else
state_in <= state;
end if;
when West =>
if req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
else
state_in <= state;
end if;
when South =>
if req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
elsif req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
else
state_in <= state;
end if;
when others =>
if req_X_L = '1' then
state_in <= Local;
X_L_sig <= '1';
elsif req_X_N ='1' then
state_in <= North;
X_N_sig <= '1';
elsif req_X_E = '1' then
state_in <= East;
X_E_sig <= '1';
elsif req_X_W = '1' then
state_in <= West;
X_W_sig <= '1';
elsif req_X_S = '1' then
state_in <= South;
X_S_sig <= '1';
else
state_in <= state;
end if;
end case;
end process;
end;
|
gpl-3.0
|
simoesusp/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE70/lpm_constant0.vhd
|
4
|
3424
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "LPM_CONSTANT",
lpm_width => 5
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL "result[4..0]"
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-3.0
|
siavooshpayandehazad/NoC_Router
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/NI.vhd
|
3
|
22786
|
---------------------------------------------------------------------
-- Copyright (C) 2016 Siavoosh Payandeh Azad
--
-- Network interface: Its an interrupt based memory mapped I/O for sending and recieving packets.
-- the data that is sent to NI should be of the following form:
-- FIRST write: 4bit source(31-28), 4 bit destination(27-14), 8bit packet length(23-16)
-- Body write: 28 bit data(27-0)
-- Last write: 28 bit data(27-0)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
use ieee.std_logic_misc.all;
entity NI is
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0;
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010"; -- reserved address for reconfiguration register
self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011"); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end; --entity NI
architecture logic of NI is
-- all the following signals are for sending data from processor to NoC
signal storage, storage_in : std_logic_vector(31 downto 0);
signal valid_data_in, valid_data: std_logic;
signal old_address: std_logic_vector(31 downto 2);
signal P2N_FIFO_read_pointer, P2N_FIFO_read_pointer_in, P2N_FIFO_write_pointer, P2N_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal P2N_write_en: std_logic;
signal P2N_FIFO_MEM_1, P2N_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_2, P2N_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_3, P2N_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal P2N_FIFO_MEM_4, P2N_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal P2N_full, P2N_empty: std_logic;
signal credit_counter_in, credit_counter_out: std_logic_vector(1 downto 0);
signal packet_counter_in, packet_counter_out: std_logic_vector(7 downto 0);
signal packet_length_counter_in, packet_length_counter_out: std_logic_vector(11 downto 0);
signal grant : std_logic;
type STATE_TYPE IS (IDLE, HEADER_FLIT, BODY_FLIT, TAIL_FLIT, DIAGNOSIS_HEADER, DIAGNOSIS_BODY, DIAGNOSIS_TAIL);
signal state, state_in : STATE_TYPE := IDLE;
signal FIFO_Data_out : std_logic_vector(31 downto 0);
signal flag_register, flag_register_in : std_logic_vector(31 downto 0);
-- all the following signals are for sending the packets from NoC to processor
signal N2P_FIFO_MEM_1, N2P_FIFO_MEM_1_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_2, N2P_FIFO_MEM_2_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_3, N2P_FIFO_MEM_3_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_MEM_4, N2P_FIFO_MEM_4_in : std_logic_vector(31 downto 0);
signal N2P_Data_out, data_read_in : std_logic_vector(31 downto 0);
signal N2P_FIFO_read_pointer, N2P_FIFO_read_pointer_in: std_logic_vector(3 downto 0);
signal N2P_FIFO_write_pointer, N2P_FIFO_write_pointer_in: std_logic_vector(3 downto 0);
signal N2P_full, N2P_empty: std_logic;
signal N2P_read_en, N2P_read_en_in, N2P_write_en: std_logic;
signal counter_register_in, counter_register : std_logic_vector(1 downto 0);
signal fault_info, fault_info_in: std_logic_vector(24 downto 0);
signal sent_info, fault_info_ready, fault_info_ready_in: std_logic;
signal self_diagnosis_reg_out, self_diagnosis_reg_in: std_logic_vector(31 downto 0);
signal self_diagnosis_flag, self_diagnosis_flag_in: std_logic;
begin
process(clk, enable, write_byte_enable) begin
if reset = '1' then
storage <= (others => '0');
valid_data <= '0';
P2N_FIFO_read_pointer <= "0001";
P2N_FIFO_write_pointer <= "0001";
P2N_FIFO_MEM_1 <= (others=>'0');
P2N_FIFO_MEM_2 <= (others=>'0');
P2N_FIFO_MEM_3 <= (others=>'0');
P2N_FIFO_MEM_4 <= (others=>'0');
credit_counter_out <= "11";
packet_length_counter_out <= "000000000000";
state <= IDLE;
packet_counter_out <= "00000000";
------------------------------------------------
N2P_FIFO_MEM_1 <= (others=>'0');
N2P_FIFO_MEM_2 <= (others=>'0');
N2P_FIFO_MEM_3 <= (others=>'0');
N2P_FIFO_MEM_4 <= (others=>'0');
N2P_FIFO_read_pointer <= "0001";
N2P_FIFO_write_pointer <= "0001";
credit_out <= '0';
counter_register <= (others => '0');
N2P_read_en <= '0';
flag_register <= (others =>'0');
old_address <= (others =>'0');
fault_info <= (others => '0');
fault_info_ready <= '0';
self_diagnosis_reg_out <= (others => '0');
self_diagnosis_flag <= '0';
elsif clk'event and clk = '1' then
old_address <= address;
P2N_FIFO_write_pointer <= P2N_FIFO_write_pointer_in;
P2N_FIFO_read_pointer <= P2N_FIFO_read_pointer_in;
credit_counter_out <= credit_counter_in;
packet_length_counter_out <= packet_length_counter_in;
valid_data <= valid_data_in;
if P2N_write_en = '1' then
--write into the memory
P2N_FIFO_MEM_1 <= P2N_FIFO_MEM_1_in;
P2N_FIFO_MEM_2 <= P2N_FIFO_MEM_2_in;
P2N_FIFO_MEM_3 <= P2N_FIFO_MEM_3_in;
P2N_FIFO_MEM_4 <= P2N_FIFO_MEM_4_in;
end if;
packet_counter_out <= packet_counter_in;
if write_byte_enable /= "0000" then
storage <= storage_in;
end if;
state <= state_in;
------------------------------------------------
if N2P_write_en = '1' then
--write into the memory
N2P_FIFO_MEM_1 <= N2P_FIFO_MEM_1_in;
N2P_FIFO_MEM_2 <= N2P_FIFO_MEM_2_in;
N2P_FIFO_MEM_3 <= N2P_FIFO_MEM_3_in;
N2P_FIFO_MEM_4 <= N2P_FIFO_MEM_4_in;
end if;
counter_register <= counter_register_in;
N2P_FIFO_write_pointer <= N2P_FIFO_write_pointer_in;
N2P_FIFO_read_pointer <= N2P_FIFO_read_pointer_in;
credit_out <= '0';
N2P_read_en <= N2P_read_en_in;
if N2P_read_en = '1' then
credit_out <= '1';
end if;
flag_register <= flag_register_in;
fault_info <= fault_info_in;
fault_info_ready <= fault_info_ready_in;
self_diagnosis_reg_out <= self_diagnosis_reg_in;
self_diagnosis_flag <= self_diagnosis_flag_in;
end if;
end process;
-- everything bellow this line is pure combinatorial!
---------------------------------------------------------------------------------------
--below this is code for communication from PE 2 NoC
process(write_byte_enable, address) begin
Reconfig_command <= '0';
Rxy_reconf_PE <= (others =>'0');
Cx_reconf_PE <= (others =>'0');
if address = reconfiguration_address and enable = '1' then
Rxy_reconf_PE <= data_write(7 downto 0);
Cx_reconf_PE <= data_write(4 downto 8);
Reconfig_command <= '1';
end if;
end process;
process(write_byte_enable, enable, address, storage, data_write, valid_data, P2N_write_en) begin
storage_in <= storage ;
valid_data_in <= valid_data;
if enable = '1' and address = reserved_address then
if write_byte_enable /= "0000" then
valid_data_in <= '1';
end if;
if write_byte_enable(0) = '1' then
storage_in(7 downto 0) <= data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
storage_in(15 downto 8) <= data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
storage_in(23 downto 16) <= data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
storage_in(31 downto 24) <= data_write(31 downto 24);
end if;
end if;
if P2N_write_en = '1' then
valid_data_in <= '0';
end if;
end process;
process(storage, P2N_FIFO_write_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case(P2N_FIFO_write_pointer) is
when "0001" => P2N_FIFO_MEM_1_in <= storage; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0010" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= storage; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "0100" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= storage; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
when "1000" => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= storage;
when others => P2N_FIFO_MEM_1_in <= P2N_FIFO_MEM_1; P2N_FIFO_MEM_2_in <= P2N_FIFO_MEM_2; P2N_FIFO_MEM_3_in <= P2N_FIFO_MEM_3; P2N_FIFO_MEM_4_in <= P2N_FIFO_MEM_4;
end case ;
end process;
process(P2N_FIFO_read_pointer, P2N_FIFO_MEM_1, P2N_FIFO_MEM_2, P2N_FIFO_MEM_3, P2N_FIFO_MEM_4)begin
case( P2N_FIFO_read_pointer ) is
when "0001" => FIFO_Data_out <= P2N_FIFO_MEM_1;
when "0010" => FIFO_Data_out <= P2N_FIFO_MEM_2;
when "0100" => FIFO_Data_out <= P2N_FIFO_MEM_3;
when "1000" => FIFO_Data_out <= P2N_FIFO_MEM_4;
when others => FIFO_Data_out <= P2N_FIFO_MEM_1;
end case ;
end process;
process(P2N_write_en, P2N_FIFO_write_pointer)begin
if P2N_write_en = '1'then
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer(2 downto 0) & P2N_FIFO_write_pointer(3);
else
P2N_FIFO_write_pointer_in <= P2N_FIFO_write_pointer;
end if;
end process;
process(P2N_FIFO_read_pointer, grant)begin
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer;
if grant = '1' then
P2N_FIFO_read_pointer_in <= P2N_FIFO_read_pointer(2 downto 0) & P2N_FIFO_read_pointer(3);
end if;
end process;
process(P2N_full, valid_data) begin
if valid_data = '1' and P2N_full ='0' then
P2N_write_en <= '1';
else
P2N_write_en <= '0';
end if;
end process;
process(P2N_FIFO_write_pointer, P2N_FIFO_read_pointer) begin
P2N_empty <= '0';
P2N_full <= '0';
if P2N_FIFO_read_pointer = P2N_FIFO_write_pointer then
P2N_empty <= '1';
end if;
if P2N_FIFO_write_pointer = P2N_FIFO_read_pointer(0) & P2N_FIFO_read_pointer(3 downto 1) then
P2N_full <= '1';
end if;
end process;
process (credit_in, credit_counter_out, grant)begin
credit_counter_in <= credit_counter_out;
if credit_in = '1' and grant = '1' then
credit_counter_in <= credit_counter_out;
elsif credit_in = '1' and credit_counter_out < 3 then
credit_counter_in <= credit_counter_out + 1;
elsif grant = '1' and credit_counter_out > 0 then
credit_counter_in <= credit_counter_out - 1;
end if;
end process;
-- flag setting and clearing for self diagnosis
process(link_faults, turn_faults, self_diagnosis_flag, old_address)begin
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_flag_in <= '1';
elsif old_address = self_diagnosis_address then
self_diagnosis_flag_in <= '0';
else
self_diagnosis_flag_in <= self_diagnosis_flag;
end if;
end process;
-- handling fault information!
process(link_faults, turn_faults, sent_info, fault_info_ready, fault_info)begin
self_diagnosis_reg_in <= self_diagnosis_reg_out;
if (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address /= current_address then
fault_info_in <= turn_faults & link_faults;
fault_info_ready_in <= '1';
elsif (link_faults /= "00000" or turn_faults /= "00000000000000000000") and SHMU_address = current_address then
self_diagnosis_reg_in <= "0000000" & turn_faults & link_faults; -- turn_faults : 20 bits + link_faults : 5 bits => remaining : 7 bits (all zeros)
else
fault_info_in <= fault_info;
fault_info_ready_in <= fault_info_ready;
end if;
if sent_info = '1' then
fault_info_ready_in <= '0';
end if;
end process;
process(P2N_empty, state, credit_counter_out, packet_length_counter_out, packet_counter_out, FIFO_Data_out, fault_info_ready)
variable LINEVARIABLE : line;
file VEC_FILE : text is out "sent.txt";
begin
sent_info <= '0';
TX <= (others => '0');
grant<= '0';
packet_length_counter_in <= packet_length_counter_out;
packet_counter_in <= packet_counter_out;
case(state) is
when IDLE =>
if fault_info_ready = '1' then
state_in <= DIAGNOSIS_HEADER;
elsif P2N_empty = '0' then
state_in <= HEADER_FLIT;
else
state_in <= IDLE;
end if;
when HEADER_FLIT =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & "0000" & FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "0000" &
FIFO_Data_out(23 downto 16) & FIFO_Data_out(31 downto 28) &
std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= BODY_FLIT;
packet_length_counter_in <= ("0000" & FIFO_Data_out(23 downto 16))-1;
else
state_in <= HEADER_FLIT;
end if;
when BODY_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0'then
grant <= '1';
TX <= "010" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("010" & FIFO_Data_out(27 downto 0));
packet_length_counter_in <= packet_length_counter_out - "000000000001";
if packet_length_counter_out = "000000000010" then
state_in <= TAIL_FLIT;
else
state_in <= BODY_FLIT;
end if;
else
state_in <= BODY_FLIT;
end if;
when TAIL_FLIT =>
if credit_counter_out /= "00" and P2N_empty = '0' then
grant <= '1';
TX <= "100" & FIFO_Data_out(27 downto 0) & XOR_REDUCE("100" & FIFO_Data_out(27 downto 0));
packet_counter_in <= packet_counter_out +1;
state_in <= IDLE;
else
state_in <= TAIL_FLIT;
end if;
-- SHMU stuff ----------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
when DIAGNOSIS_HEADER =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out & XOR_REDUCE("001" & "000000000011" & "0000" & std_logic_vector(to_unsigned(current_address, 4)) & packet_counter_out);
state_in <= DIAGNOSIS_BODY;
else
state_in <= DIAGNOSIS_HEADER;
end if;
when DIAGNOSIS_BODY =>
if credit_counter_out /= "00" then
grant <= '1';
--FD (Fault Diagnosis) : 01000110 01000100
-- fault info is 25 bits
TX <= "010" & "0100011001000100" & fault_info(11 downto 0) & XOR_REDUCE("010" & "0100011001000100" & fault_info(11 downto 0));
state_in <= DIAGNOSIS_TAIL;
else
state_in <= DIAGNOSIS_BODY;
end if;
when DIAGNOSIS_TAIL =>
if credit_counter_out /= "00" then
grant <= '1';
TX <= "100" & fault_info(24 downto 12) & "000000000000000" & XOR_REDUCE("100" & fault_info(12) & "000000000000000000000000000");
state_in <= IDLE;
sent_info <= '1';
packet_counter_in <= packet_counter_out +1;
else
state_in <= DIAGNOSIS_TAIL;
end if;
when others =>
state_in <= IDLE;
end case ;
end procesS;
valid_out <= grant;
----------------------------------------------------------------------------------------
--below this is code for communication from NoC 2 PE
process(RX, N2P_FIFO_write_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_write_pointer ) is
when "0001" => N2P_FIFO_MEM_1_in <= RX; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0010" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= RX; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "0100" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= RX; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
when "1000" => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= RX;
when others => N2P_FIFO_MEM_1_in <= N2P_FIFO_MEM_1; N2P_FIFO_MEM_2_in <= N2P_FIFO_MEM_2; N2P_FIFO_MEM_3_in <= N2P_FIFO_MEM_3; N2P_FIFO_MEM_4_in <= N2P_FIFO_MEM_4;
end case ;
end process;
process(N2P_FIFO_read_pointer, N2P_FIFO_MEM_1, N2P_FIFO_MEM_2, N2P_FIFO_MEM_3, N2P_FIFO_MEM_4)begin
case( N2P_FIFO_read_pointer ) is
when "0001" => N2P_Data_out <= N2P_FIFO_MEM_1;
when "0010" => N2P_Data_out <= N2P_FIFO_MEM_2;
when "0100" => N2P_Data_out <= N2P_FIFO_MEM_3;
when "1000" => N2P_Data_out <= N2P_FIFO_MEM_4;
when others => N2P_Data_out <= N2P_FIFO_MEM_1;
end case ;
end process;
process(address, write_byte_enable, N2P_empty)begin
if address = reserved_address and write_byte_enable = "0000" and N2P_empty = '0' then
N2P_read_en_in <= '1';
else
N2P_read_en_in <= '0';
end if;
end process;
process(N2P_write_en, N2P_FIFO_write_pointer)begin
if N2P_write_en = '1'then
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer(2 downto 0)&N2P_FIFO_write_pointer(3);
else
N2P_FIFO_write_pointer_in <= N2P_FIFO_write_pointer;
end if;
end process;
process(N2P_read_en, N2P_empty, N2P_FIFO_read_pointer)begin
if (N2P_read_en = '1' and N2P_empty = '0') then
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer(2 downto 0)&N2P_FIFO_read_pointer(3);
else
N2P_FIFO_read_pointer_in <= N2P_FIFO_read_pointer;
end if;
end process;
process(N2P_full, valid_in) begin
if (valid_in = '1' and N2P_full ='0') then
N2P_write_en <= '1';
else
N2P_write_en <= '0';
end if;
end process;
process(N2P_FIFO_write_pointer, N2P_FIFO_read_pointer) begin
if N2P_FIFO_read_pointer = N2P_FIFO_write_pointer then
N2P_empty <= '1';
else
N2P_empty <= '0';
end if;
if N2P_FIFO_write_pointer = N2P_FIFO_read_pointer(0)&N2P_FIFO_read_pointer(3 downto 1) then
N2P_full <= '1';
else
N2P_full <= '0';
end if;
end process;
process(N2P_read_en, N2P_Data_out, old_address, flag_register) begin
if old_address = reserved_address and N2P_read_en = '1' then
data_read <= N2P_Data_out;
elsif old_address = flag_address then
data_read <= flag_register;
elsif old_address = counter_address then
data_read <= "000000000000000000000000000000" & counter_register;
elsif old_address = self_diagnosis_address then
data_read <= self_diagnosis_reg_out;
else
data_read <= (others => 'U');
end if;
end process;
process(N2P_write_en, N2P_read_en, RX, N2P_Data_out)begin
counter_register_in <= counter_register;
if N2P_write_en = '1' and RX(31 downto 29) = "001" and N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register;
elsif N2P_write_en = '1' and RX(31 downto 29) = "001" then
counter_register_in <= counter_register +1;
elsif N2P_read_en = '1' and N2P_Data_out(31 downto 29) = "100" then
counter_register_in <= counter_register -1;
end if;
end process;
flag_register_in <= N2P_empty & P2N_full & self_diagnosis_flag& "00000000000000000000000000000";
--NI_read_flag <= N2P_empty;
--NI_write_flag <= P2N_full;
irq_out <= '0';
end; --architecture logic
|
gpl-3.0
|
LemurPwned/classic-fpga
|
memory/lifo_tb.vhdl
|
1
|
1086
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lifo_tb is
end entity;
architecture lifo_tb of lifo_tb is
component lifo is
port (
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0);
clk : in std_logic;
wr : in std_logic;
empty, full : out std_logic
);
end component;
signal x : std_logic_vector(3 downto 0) := "0000";
signal y : std_logic_vector(3 downto 0) := "0000";
signal clk : std_logic := '1';
signal wr : std_logic := '0';
signal empty : std_logic := '0';
signal full : std_logic := '0';
constant period : time := 10 ns;
begin
mapping: lifo port map(clk=>clk, x=>x, y=>y, wr=>wr,
empty=>empty, full=>full);
clk_proc : process
begin
clk <= not clk;
wait for period/2;
end process;
stim_proc: process
begin
wait for 3 ns;
x<="0100";
wr<='1';
wait for period;
x<="1100";
wait for period;
wr<='0';
wait for period;
--wr<='0';
--re<='1';
wait;
end process;
end architecture;
|
gpl-3.0
|
LemurPwned/classic-fpga
|
multiplexers_registers/sipo_tb.vhdl
|
1
|
997
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo_tb is
end entity;
architecture arch of sipo_tb is
component sipo is
port (
clk : in std_logic;
se : in std_logic_vector(1 downto 0);
D : in std_logic_vector(3 downto 0);
Dl, Dr : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end component;
for sipo_0 : sipo use entity work.sipo;
signal clk : std_logic :='1';
signal Q, D : std_logic_vector(3 downto 0);
signal Dl, Dr : std_logic;
signal se : std_logic_vector(1 downto 0);
constant period : time := 10 ns;
begin
sipo_0 : sipo port map (clk=>clk, D=>D, Dr=>Dr, Dl=>Dl, Q=>Q, se=>se);
clk_proc:
process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc:
process
begin
se<="00";
D<="1011";
Dl<='1';
Dr<='1';
wait for 35 ns;
se<="01";
wait for 20 ns;
se<="11";
wait for 15 ns;
wait;
end process;
end architecture;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_6_1_1_2.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
chrreisinger/OpenVC
|
document/Masterarbeit/src/ast/LogicalExpression.vhd
|
1
|
32
|
a + b sll 1 <= c * d and not e
|
gpl-3.0
|
malkadi/FGPU
|
RTL/FGPU.vhd
|
1
|
44323
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.FGPU_definitions.all;
------------------------------------------------------------------------------------------------- }}}
entity FGPU is
-- Generics & ports {{{
port(
clk : in std_logic;
-- Contorl Interface - AXI LITE SLAVE {{{
s0_awaddr : in std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0);
s0_awprot : in std_logic_vector(2 downto 0);
s0_awvalid : in std_logic;
s0_awready : out std_logic := '0';
s0_wdata : in std_logic_vector(DATA_W-1 downto 0);
s0_wstrb : in std_logic_vector((DATA_W/8)-1 downto 0);
s0_wvalid : in std_logic;
s0_wready : out std_logic := '0';
s0_bresp : out std_logic_vector(1 downto 0) := (others=>'0');
s0_bvalid : out std_logic := '0';
s0_bready : in std_logic;
s0_araddr : in std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0);
s0_arprot : in std_logic_vector(2 downto 0);
s0_arvalid : in std_logic;
s0_arready : out std_logic := '0';
s0_rdata : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
s0_rresp : out std_logic_vector(1 downto 0) := (others=>'0');
s0_rvalid : out std_logic := '0';
s0_rready : in std_logic;
-- }}}
-- AXI MASTER 0 {{{
-- ar channel
m0_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m0_arlen : out std_logic_vector(7 downto 0):= (others=>'0');
m0_arsize : out std_logic_vector(2 downto 0):= (others=>'0');
m0_arburst : out std_logic_vector(1 downto 0):= (others=>'0');
m0_arvalid : out std_logic := '0';
m0_arready : in std_logic;
m0_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m0_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m0_rresp : in std_logic_vector(1 downto 0):= (others=>'0');
m0_rlast : in std_logic;
m0_rvalid : in std_logic;
m0_rready : out std_logic := '0';
m0_rid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- aw channel
m0_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m0_awvalid : out std_logic := '0';
m0_awready : in std_logic;
m0_awlen : out std_logic_vector(7 downto 0):= (others=>'0');
m0_awsize : out std_logic_vector(2 downto 0):= (others=>'0');
m0_awburst : out std_logic_vector(1 downto 0):= (others=>'0');
m0_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m0_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0');
m0_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0');
m0_wlast : out std_logic := '0';
m0_wvalid : out std_logic := '0';
m0_wready : in std_logic;
-- b channel
m0_bvalid : in std_logic;
m0_bready : out std_logic := '0';
m0_bid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- }}}}
-- AXI MASTER 1 {{{
-- ar channel
m1_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m1_arlen : out std_logic_vector(7 downto 0):= (others=>'0');
m1_arsize : out std_logic_vector(2 downto 0):= (others=>'0');
m1_arburst : out std_logic_vector(1 downto 0):= (others=>'0');
m1_arvalid : out std_logic := '0';
m1_arready : in std_logic;
m1_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m1_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m1_rresp : in std_logic_vector(1 downto 0):= (others=>'0');
m1_rlast : in std_logic;
m1_rvalid : in std_logic;
m1_rready : out std_logic := '0';
m1_rid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- -- aw channel
m1_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m1_awvalid : out std_logic := '0';
m1_awready : in std_logic;
m1_awlen : out std_logic_vector(7 downto 0):= (others=>'0');
m1_awsize : out std_logic_vector(2 downto 0):= (others=>'0');
m1_awburst : out std_logic_vector(1 downto 0):= (others=>'0');
m1_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m1_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0');
m1_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0');
m1_wlast : out std_logic := '0';
m1_wvalid : out std_logic := '0';
m1_wready : in std_logic;
-- b channel
m1_bvalid : in std_logic;
m1_bready : out std_logic := '0';
m1_bid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- }}}}
-- AXI MASTER 2 {{{
-- ar channel
m2_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m2_arlen : out std_logic_vector(7 downto 0):= (others=>'0');
m2_arsize : out std_logic_vector(2 downto 0):= (others=>'0');
m2_arburst : out std_logic_vector(1 downto 0):= (others=>'0');
m2_arvalid : out std_logic := '0';
m2_arready : in std_logic;
m2_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m2_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m2_rresp : in std_logic_vector(1 downto 0):= (others=>'0');
m2_rlast : in std_logic;
m2_rvalid : in std_logic;
m2_rready : out std_logic := '0';
m2_rid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- -- aw channel
m2_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m2_awvalid : out std_logic := '0';
m2_awready : in std_logic;
m2_awlen : out std_logic_vector(7 downto 0):= (others=>'0');
m2_awsize : out std_logic_vector(2 downto 0):= (others=>'0');
m2_awburst : out std_logic_vector(1 downto 0):= (others=>'0');
m2_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m2_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0');
m2_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0');
m2_wlast : out std_logic := '0';
m2_wvalid : out std_logic := '0';
m2_wready : in std_logic;
-- b channel
m2_bvalid : in std_logic;
m2_bready : out std_logic := '0';
m2_bid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- }}}}
-- AXI MASTER 3 {{{
-- ar channel
m3_araddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m3_arlen : out std_logic_vector(7 downto 0):= (others=>'0');
m3_arsize : out std_logic_vector(2 downto 0):= (others=>'0');
m3_arburst : out std_logic_vector(1 downto 0):= (others=>'0');
m3_arvalid : out std_logic := '0';
m3_arready : in std_logic;
m3_arid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m3_rdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m3_rresp : in std_logic_vector(1 downto 0):= (others=>'0');
m3_rlast : in std_logic;
m3_rvalid : in std_logic;
m3_rready : out std_logic := '0';
m3_rid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- -- aw channel
m3_awaddr : out std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m3_awvalid : out std_logic := '0';
m3_awready : in std_logic;
m3_awlen : out std_logic_vector(7 downto 0):= (others=>'0');
m3_awsize : out std_logic_vector(2 downto 0):= (others=>'0');
m3_awburst : out std_logic_vector(1 downto 0):= (others=>'0');
m3_awid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m3_wdata : out std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0):= (others=>'0');
m3_wstrb : out std_logic_vector(DATA_W*GMEM_N_BANK/8-1 downto 0):= (others=>'0');
m3_wlast : out std_logic := '0';
m3_wvalid : out std_logic := '0';
m3_wready : in std_logic;
-- b channel
m3_bvalid : in std_logic;
m3_bready : out std_logic := '0';
m3_bid : in std_logic_vector(ID_WIDTH-1 downto 0);
-- }}}}
nrst : in std_logic
);
-- ports }}}
end FGPU;
architecture Behavioral of FGPU is
-- internal signals definitions {{{
signal s0_awready_i, s0_bvalid_i : std_logic := '0';
signal s0_wready_i, s0_arready_i : std_logic := '0';
signal nrst_CUs : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal nrst_gmem_cntrl : std_logic := '0';
signal nrst_wgDispatcher : std_logic := '0';
-- }}}
-- slave axi interface {{{
signal mainProc_we : std_logic := '0';
signal mainProc_wrAddr : std_logic_vector(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0');
signal mainProc_rdAddr : unsigned(INTERFCE_W_ADDR_W-1 downto 0) := (others=>'0');
signal s0_rvalid_vec : std_logic_vector(3 downto 0) := (others=>'0');
signal s0_wdata_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
-- }}}
-- general signals definitions {{{
signal KRNL_SCHEDULER_RAM : KRNL_SCHEDULER_RAM_type := init_krnl_ram("krnl_ram.mif");
-- signal cram_b1 : CRAM_type := init_CRAM("cram_LUdecomposition.mif", 930);
signal cram_b1 : CRAM_type := init_CRAM("cram.mif", 3000);
signal KRNL_SCH_we : std_logic := '0';
signal krnl_sch_rdData : std_logic_vector(DATA_W-1 downto 0) := (others => '0');
signal krnl_sch_rdData_n : std_logic_vector(DATA_W-1 downto 0) := (others => '0');
signal krnl_sch_rdAddr : unsigned(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0');
signal krnl_sch_rdAddr_WGD : std_logic_vector(KRNL_SCH_ADDR_W-1 downto 0) := (others => '0');
signal CRAM_we : std_logic := '0';
-- signal cram_rdData, cram_rdData_n : SLV32_ARRAY(CRAM_BLOCKS-1 downto 0) := (others=>(others=>'0'));
-- signal cram_rdAddr, cram_rdAddr_d0 : CRAM_ADDR_ARRAY(CRAM_BLOCKS-1 downto 0) := (others=>(others=>'0'));
signal cram_rdData, cram_rdData_n : std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
signal cram_rdData_vec : slv32_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal cram_rdAddr, cram_rdAddr_d0 : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0');
signal cram_rdAddr_d0_vec : cram_addr_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal status_reg : std_logic_vector(DATA_W-1 downto 0) := (others => '0');
signal regFile_we, regFile_we_d0 : std_logic := '0';
signal Rstat : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others => '0');
signal Rstart : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others => '0');
signal RcleanCache : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others=>'0');
signal RInitiate : std_logic_vector(NEW_KRNL_MAX_INDX-1 downto 0) := (others=>'0');
type WG_dispatcher_state_type is (idle, st1_dispatch);
signal st_wg_disp, st_wg_disp_n : WG_dispatcher_state_type := idle;
signal new_krnl_indx : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0;
signal new_krnl_field : std_logic_vector(NEW_KRNL_DESC_W-1 downto 0) := (others =>'0');
signal start_kernel, clean_cache : std_logic := '0';
signal start_CUs, initialize_d0 : std_logic := '0'; -- informs all CUs to start working after initialization phase of the WG_dispatcher is finished
signal start_CUs_vec : std_logic_vector(max(N_CU-1, 0) downto 0) := (others=>'0'); -- to improve timing
signal finish_exec : std_logic := '0'; -- high when execution of a kernel is done
signal WGsDispatched : std_logic := '0'; -- high when WG_Dispatcher has schedules all WGs
signal finish_exec_d0 : std_logic := '0';
signal finish_krnl_indx : integer range 0 to NEW_KRNL_MAX_INDX-1 := 0;
signal wg_req : std_logic_vector(N_CU-1 downto 0) := (others => '0');
signal wg_ack : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
type wg_req_vec_type is array(natural range <>) of std_logic_vector(N_CU-1 downto 0);
signal wg_req_vec : wg_req_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal wg_ack_vec : wg_req_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal CU_cram_rqst : std_logic_vector(N_CU-1 downto 0) := (others => '0');
signal sch_rqst_n_WFs_m1 : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0');
type sch_rqst_n_WFs_m1_vec_type is array (natural range <>) of unsigned(N_WF_CU_W-1 downto 0);
signal sch_rqst_n_WFs_m1_vec : sch_rqst_n_WFs_m1_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal cram_served_CUs : std_logic := '0'; -- one-bit-toggle to serve different CUs when fetching instructions
signal CU_cram_rdAddr : CRAM_ADDR_ARRay(N_CU-1 downto 0) := (others =>(others=>'0'));
signal start_addr : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- the address of the first instruction to be fetched
signal start_addr_vec : cram_addr_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0')); -- just to improve timing
signal rdData_alu_en : alu_en_vec_type(N_CU-1 downto 0) := (others=>(others=>'0'));
signal rdAddr_alu_en : alu_en_rdAddr_type(N_CU-1 downto 0) := (others=>(others=>'0'));
signal rtm_wrAddr_wg : unsigned(RTM_ADDR_W-1 downto 0) := (others => '0');
type rtm_addr_vec_type is array (natural range<>) of unsigned(RTM_ADDR_W-1 downto 0);
signal rtm_wrAddr_wg_vec : rtm_addr_vec_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal rtm_wrData_wg : unsigned(RTM_DATA_W-1 downto 0) := (others => '0');
signal rtm_wrData_wg_vec : rtm_ram_type(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
signal rtm_we_wg : std_logic := '0';
signal rtm_we_wg_vec : std_logic_vector(max(N_CU-1, 0) downto 0) := (others=>'0');
signal wg_info : unsigned(DATA_W-1 downto 0) := (others=>'0');
signal wg_info_vec : slv32_array(max(N_CU-1, 0) downto 0) := (others=>(others=>'0'));
-- }}}
-- global memory ---------------------------------------------------- {{{
-- cache signals
function distribute_cache_rd_ports_on_CUs (n_cus: integer) return nat_array is -- {{{
variable res: nat_array(n_cus-1 downto 0) := (others=>0);
-- res(0) will have the maximum distance to the global memory controller
begin
for i in 0 to n_cus-1 loop
res(i) := n_cus/2*(i mod 2) + (i/2);
end loop;
return res;
end; -- }}}
constant cache_rd_port_to_CU : nat_array(N_CU-1 downto 0) := distribute_cache_rd_ports_on_CUs(N_CU);
type cache_rdData_vec_type is array(natural range <>) of std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0);
signal cache_rdData_vec : cache_rdData_vec_type(N_CU downto 0) := (others=>(others=>'0'));
signal atomic_rdData_vec : slv32_array(N_CU downto 0) := (others=>(others=>'0'));
type rdData_v_vec_type is array(natural range <>) of std_logic_vector(N_CU-1 downto 0);
signal atomic_rdData_v_vec : rdData_v_vec_type(N_CU downto 0) := (others=>(others=>'0'));
type atomic_sgntr_vec_type is array(natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
signal atomic_sgntr_vec : atomic_sgntr_vec_type(N_CU downto 0) := (others=>(others=>'0'));
signal cache_rdAddr_vec : GMEM_ADDR_ARRAY_NO_BANK(N_CU downto 0) := (others=>(others=>'0'));
signal cache_rdAck_vec : rdData_v_vec_type(N_CU downto 0) := (others=>(others=>'0'));
signal cache_rdData_out : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0) := (others=>'0');
signal cache_rdAddr_out : unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0) := (others=>'0');
signal cache_rdAck_out : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal atomic_rdData : std_logic_vector(DATA_W-1 downto 0) := (others=>'0');
signal atomic_rdData_v : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal atomic_sgntr : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0');
signal cu_gmem_valid, cu_gmem_ready : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal cu_gmem_we : be_array(N_CU-1 downto 0) := (others=>(others=>'0'));
signal cu_gmem_rnw, cu_gmem_atomic : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal cu_gmem_atomic_sgntr : atomic_sgntr_array(N_CU-1 downto 0) := (others=>(others=>'0'));
signal cu_rqst_addr : GMEM_WORD_ADDR_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0'));
signal cu_gmem_wrData : SLV32_ARRAY(N_CU-1 downto 0) := (others=>(others=>'0'));
signal wf_active : wf_active_array(N_CU-1 downto 0) := (others=>(others=>'0'));
signal CU_gmem_idle : std_logic_vector(N_CU-1 downto 0) := (others=>'0');
signal CUs_gmem_idle : std_logic := '0';
signal axi_araddr : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal axi_arvalid, axi_arready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_rdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal axi_rlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_rvalid, axi_rready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_awaddr : GMEM_ADDR_ARRAY(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal axi_awvalid, axi_awready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_wdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal axi_wstrb : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal axi_wlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_wvalid, axi_wready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_bvalid, axi_bready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal axi_arid, axi_rid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal axi_awid, axi_bid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
--}}}
begin
-- asserts -------------------------------------------------------------------------------------------{{{
assert KRNL_SCH_ADDR_W <= CRAM_ADDR_W severity failure; --Code RAM is the biggest block
assert CRAM_ADDR_W <= INTERFCE_W_ADDR_W-2 severity failure; --there should be two bits to choose among: HW_sch_RAM, CRAM and the register file
assert DATA_W >= GMEM_ADDR_W report "the width bus between a gmem_ctrl_CV and gmem_ctrl is GMEM_DATA_W" severity failure;
assert CV_SIZE = 8 or CV_SIZE = 4 severity failure;
assert 2**N_CU_STATIONS_W >= N_STATIONS_ALU*CV_SIZE report "increase N_STATIONS_W" severity failure;
assert N_TAG_MANAGERS_W > 0 report "There should be at least two tag managers" severity failure;
assert DATA_W = 32;
-- assert CRAM_BLOCKS = 1 or CRAM_BLOCKS = 2;
-- assert N_AXI = 1 or N_AXI = 2;
-- assert N_AXI = 1 or N_AXI = 2;
---------------------------------------------------------------------------------------------------------}}}
-- interal signals assignments --------------------------------------------------------------------------{{{
s0_awready <= s0_awready_i;
s0_bvalid <= s0_bvalid_i;
s0_wready <= s0_wready_i;
s0_arready <= s0_arready_i;
---------------------------------------------------------------------------------------------------------}}}
-- slave axi interface ----------------------------------------------------------------------------------{{{
-- aw & w channels
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
s0_awready_i <= '0';
s0_wready_i <= '0';
mainProc_we <= '0';
mainProc_wrAddr <= (others=>'0');
else
if s0_awready_i = '0' and s0_awvalid = '1' and s0_wvalid = '1' then
s0_awready_i <= '1';
mainProc_wrAddr <= s0_awaddr;
s0_wready_i <= '1';
mainProc_we <= '1';
else
s0_awready_i <= '0';
s0_wready_i <= '0';
mainProc_we <= '0';
end if;
end if;
end if;
end process;
-- b channel
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
s0_bvalid_i <= '0';
else
if s0_awready_i = '1' and s0_awvalid = '1' and s0_wready_i = '1' and s0_wvalid = '1' and s0_bvalid_i = '0' then
s0_bvalid_i <= '1';
elsif s0_bready = '1' and s0_bvalid_i = '1' then
s0_bvalid_i <= '0';
end if;
end if;
end if;
end process;
-- ar channel
process(clk)
begin
if rising_edge(clk) then
-- if nrst = '0' then
-- s_arready_i <= '0';
-- mainProc_rdAddr <= (others=>'0');
-- else
if s0_arready_i = '0' and s0_arvalid = '1' then
s0_arready_i <= '1';
mainProc_rdAddr <= unsigned(s0_araddr);
else
s0_arready_i <= '0';
end if;
-- end if;
end if;
end process;
-- r channel
process(clk)
begin
if rising_edge(clk) then
if nrst = '0' then
s0_rvalid_vec <= (others=>'0');
s0_rvalid <= '0';
else
s0_rvalid_vec(s0_rvalid_vec'high-1 downto 0) <= s0_rvalid_vec(s0_rvalid_vec'high downto 1);
if s0_arready_i = '1' and s0_arvalid = '1' and s0_rvalid_vec(s0_rvalid_vec'high) = '0' then
s0_rvalid_vec(s0_rvalid_vec'high) <= '1';
else
s0_rvalid_vec(s0_rvalid_vec'high) <= '0';
end if;
if s0_rvalid_vec(1) = '1' then
s0_rvalid <= '1';
end if;
if s0_rvalid_vec(0) = '1' then
if s0_rready = '1' then
s0_rvalid <= '0';
else
s0_rvalid_vec(0) <= '1';
end if;
end if;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if mainProc_rdAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "00" then -- HW_scheduler_ram
s0_rdata <= krnl_sch_rdData;
elsif mainProc_rdAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "01" then -- Code_ram
s0_rdata <= cram_rdData;
-- s0_rdata <= cram_rdData(0);
else -- "10", register file
case mainProc_rdAddr(1 downto 0) is
when "00" =>
s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= Rstat(NEW_KRNL_MAX_INDX-1 downto 0);
when "10" =>
s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= RcleanCache(NEW_KRNL_MAX_INDX-1 downto 0);
when others =>
s0_rdata(NEW_KRNL_MAX_INDX-1 downto 0) <= RInitiate(NEW_KRNL_MAX_INDX-1 downto 0);
end case;
s0_rdata(DATA_W-1 downto NEW_KRNL_MAX_INDX) <= (others=>'0');
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- fixed signals --------------------------------------------------------------------------------- {{{
s0_bresp <= "00";
s0_rresp <= "00";
------------------------------------------------------------------------------------------------- }}}
-- HW Scheduler RAM ----------------------------------------------------------------------------- {{{
Krnl_Scheduler: process (clk)
begin
if rising_edge(clk) then
krnl_sch_rdData_n <= KRNL_SCHEDULER_RAM(to_integer(krnl_sch_rdAddr));
krnl_sch_rdData <= krnl_sch_rdData_n;
if KRNL_SCH_we = '1' then
KRNL_SCHEDULER_RAM(to_integer(unsigned(mainProc_wrAddr(KRNL_SCH_ADDR_W-1 downto 0)))) <= s0_wdata_d0;
end if;
end if;
end process;
krnl_sch_rdAddr <= mainProc_rdAddr(KRNL_SCH_ADDR_W-1 downto 0) when st_wg_disp = idle else unsigned(krnl_sch_rdAddr_WGD);
KRNL_SCH_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "00" and mainProc_we = '1' else '0';
------------------------------------------------------------------------------------------------- }}}
-- Code RAM -------------------------------------------------------------------------------------- {{{
CRAM_inst: process (clk)
begin
if rising_edge(clk) then
nrst_wgDispatcher <= nrst;
cram_rdData_n <= cram_b1(to_integer(cram_rdAddr));
-- cram_rdData_n <= cram_b1(to_integer(cram_rdAddr(0)));
-- cram_rdData_n(0) <= cram_b1(to_integer(cram_rdAddr(0)));
if CRAM_we = '1' then
cram_b1(to_integer(unsigned(mainProc_wrAddr(CRAM_ADDR_W-1 downto 0)))) <= s0_wdata_d0;
end if;
-- if CRAM_BLOCKS > 1 then
-- cram_rdData_n(CRAM_BLOCKS-1) <= cram_b2(to_integer(cram_rdAddr(CRAM_BLOCKS-1)));
-- if CRAM_we = '1' then
-- cram_b2(to_integer(unsigned(mainProc_wrAddr(CRAM_ADDR_W-1 downto 0)))) <= s0_wdata_d0;
-- end if;
-- end if;
cram_rdData <= cram_rdData_n;
end if;
end process;
CRAM_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "01" and mainProc_we = '1' else '0';
process(clk)
begin
if rising_edge(clk) then
cram_rdAddr_d0 <= cram_rdAddr;
cram_rdAddr <= mainProc_rdAddr(CRAM_ADDR_W-1 downto 0);
-- cram_rdAddr(0) <= mainProc_rdAddr(CRAM_ADDR_W-1 downto 0);
cram_served_CUs <= not cram_served_CUs;
if cram_served_CUs = '0' then
for i in 0 to max(N_CU/2-1,0) loop
if CU_cram_rqst(i) = '1' then
cram_rdAddr <= CU_cram_rdAddr(i);
-- cram_rdAddr(i mod CRAM_BLOCKS) <= CU_cram_rdAddr(i);
end if;
end loop;
else
for i in N_CU/2 to N_CU-1 loop
if CU_cram_rqst(i) = '1' then
cram_rdAddr <= CU_cram_rdAddr(i);
-- cram_rdAddr(i mod CRAM_BLOCKS) <= CU_cram_rdAddr(i);
end if;
end loop;
end if;
end if;
end process;
------------------------------------------------------------------------------------------------- }}}
-- WG dispatcher -------------------------------------------------------------------------------------- {{{
WG_dispatcher_inst: entity WG_dispatcher
port map(
krnl_indx => new_krnl_indx,
start => start_kernel,
initialize_d0 => initialize_d0,
krnl_sch_rdAddr => krnl_sch_rdAddr_WGD,
krnl_sch_rdData => krnl_sch_rdData,
finish_krnl_indx => finish_krnl_indx,
-- to CUs
start_exec => start_CUs,
req => wg_req,
ack => wg_ack,
rtm_wrAddr => rtm_wrAddr_wg,
rtm_wrData => rtm_wrData_wg,
rtm_we => rtm_we_wg,
sch_rqst_n_WFs_m1 => sch_rqst_n_WFs_m1,
finish => WGsDispatched,
start_addr => start_addr,
rdData_alu_en => rdData_alu_en,
wg_info => wg_info,
-- from CUs
wf_active => wf_active,
rdAddr_alu_en => rdAddr_alu_en,
clk => clk,
nrst => nrst_wgDispatcher
);
------------------------------------------------------------------------------------------------- }}}
-- compute units -------------------------------------------------------------------------------------- {{{
compute_units_i: for i in 0 to N_CU-1 generate
begin
compute_unit_inst: entity compute_unit
port map(
clk => clk,
wf_active => wf_active(i),
WGsDispatched => WGsDispatched,
nrst => nrst_CUs(i),
cram_rdAddr => CU_cram_rdAddr(i),
cram_rdData => cram_rdData_vec(i),
-- cram_rdData => cram_rdData(i mod CRAM_BLOCKS),
cram_rqst => CU_cram_rqst(i),
cram_rdAddr_conf => cram_rdAddr_d0_vec(i),
-- cram_rdAddr_conf => cram_rdAddr_d0(i mod CRAM_BLOCKS),
start_addr => start_addr_vec(i),
start_CUs => start_CUs_vec(i),
sch_rqst_n_wfs_m1 => sch_rqst_n_WFs_m1_vec(i),
sch_rqst => wg_req_vec(i)(i),
sch_ack => wg_ack(i),
wg_info => unsigned(wg_info_vec(i)),
rtm_wrAddr_wg => rtm_wrAddr_wg_vec(i),
rtm_wrData_wg => rtm_wrData_wg_vec(i),
rtm_we_wg => rtm_we_wg_vec(i),
rdData_alu_en => rdData_alu_en(i),
rdAddr_alu_en => rdAddr_alu_en(i),
gmem_valid => cu_gmem_valid(i),
gmem_we => cu_gmem_we(i),
gmem_rnw => cu_gmem_rnw(i),
gmem_atomic => cu_gmem_atomic(i),
gmem_atomic_sgntr => cu_gmem_atomic_sgntr(i),
gmem_rqst_addr => cu_rqst_addr(i),
gmem_ready => cu_gmem_ready(i),
gmem_wrData => cu_gmem_wrData(i),
--cache read data
cache_rdAddr => cache_rdAddr_vec(cache_rd_port_to_CU(i)),
cache_rdAck => cache_rdAck_vec(cache_rd_port_to_CU(i))(i),
cache_rdData => cache_rdData_vec(cache_rd_port_to_CU(i)),
atomic_rdData => atomic_rdData_vec(cache_rd_port_to_CU(i)),
atomic_rdData_v => atomic_rdData_v_vec(cache_rd_port_to_CU(i))(i),
atomic_sgntr => atomic_sgntr_vec(cache_rd_port_to_CU(i)),
gmem_cntrl_idle => CU_gmem_idle(i)
-- loc_mem_rdAddr_dummy => loc_mem_rdAddr_dummy(DATA_W*(i+1)-1 downto i*DATA_W)
);
end generate;
process(clk)
begin
if rising_edge(clk) then
cache_rdAck_vec(cache_rdAck_vec'high) <= cache_rdAck_out;
cache_rdAck_vec(cache_rdAck_vec'high-1 downto 0) <= cache_rdAck_vec(cache_rdAck_vec'high downto 1);
cache_rdAddr_vec(cache_rdAddr_vec'high) <= cache_rdAddr_out;
cache_rdAddr_vec(cache_rdAddr_vec'high-1 downto 0) <= cache_rdAddr_vec(cache_rdAddr_vec'high downto 1);
cache_rdData_vec(cache_rdData_vec'high) <= cache_rdData_out;
cache_rdData_vec(cache_rdData_vec'high-1 downto 0) <= cache_rdData_vec(cache_rdData_vec'high downto 1);
atomic_rdData_vec(atomic_rdData_vec'high) <= atomic_rdData;
atomic_rdData_vec(atomic_rdData_vec'high-1 downto 0) <= atomic_rdData_vec(atomic_rdData_vec'high downto 1);
atomic_rdData_v_vec(atomic_rdData_v_vec'high) <= atomic_rdData_v;
atomic_rdData_v_vec(atomic_rdData_vec'high -1 downto 0) <= atomic_rdData_v_vec(atomic_rdData_v_vec'high downto 1);
atomic_sgntr_vec(atomic_sgntr_vec'high) <= atomic_sgntr;
atomic_sgntr_vec(atomic_sgntr_vec'high-1 downto 0) <= atomic_sgntr_vec(atomic_sgntr_vec'high downto 1);
start_addr_vec(start_addr_vec'high) <= start_addr;
start_addr_vec(start_addr_vec'high-1 downto 0) <= start_addr_vec(start_addr_vec'high downto 1);
start_CUs_vec(start_CUs_vec'high) <= start_CUs;
wg_req_vec(wg_req_vec'high) <= wg_req;
wg_info_vec(wg_info_vec'high) <= std_logic_vector(wg_info);
rtm_we_wg_vec(rtm_we_wg_vec'high) <= rtm_we_wg;
sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high) <= sch_rqst_n_WFs_m1;
rtm_wrData_wg_vec(rtm_wrData_wg_vec'high) <= rtm_wrData_wg;
rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high) <= rtm_wrAddr_wg;
cram_rdData_vec(cram_rdData_vec'high) <= cram_rdData;
cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high) <= cram_rdAddr_d0;
if N_CU > 1 then
start_CUs_vec(start_CUs_vec'high-1 downto 0) <= start_CUs_vec(start_CUs_vec'high downto 1);
wg_req_vec(wg_req_vec'high-1 downto 0) <= wg_req_vec(wg_req_vec'high downto 1);
-- wg_ack_vec(wg_ack_vec'high-1 downto 0) <= wg_ack_vec(wg_ack_vec'high downto 1);
wg_info_vec(wg_info_vec'high-1 downto 0) <= wg_info_vec(wg_info_vec'high downto 1);
rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high-1 downto 0) <= rtm_wrAddr_wg_vec(rtm_wrAddr_wg_vec'high downto 1);
rtm_wrData_wg_vec(rtm_wrData_wg_vec'high-1 downto 0) <= rtm_wrData_wg_vec(rtm_wrData_wg_vec'high downto 1);
rtm_we_wg_vec(rtm_we_wg_vec'high-1 downto 0) <= rtm_we_wg_vec(rtm_we_wg_vec'high downto 1);
sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high-1 downto 0) <= sch_rqst_n_WFs_m1_vec(sch_rqst_n_WFs_m1_vec'high downto 1);
cram_rdData_vec(cram_rdData_vec'high-1 downto 0) <= cram_rdData_vec(cram_rdData_vec'high downto 1);
cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high-1 downto 0) <= cram_rdAddr_d0_vec(cram_rdAddr_d0_vec'high downto 1);
end if;
for i in 0 to N_CU-1 loop
nrst_CUs(i) <= nrst;
end loop;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if to_integer(unsigned(CU_gmem_idle)) = 2**N_CU-1 then
CUs_gmem_idle <= '1';
else
CUs_gmem_idle <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------------- }}}
-- global memory controller----------------------------------------------------------------------------------- {{{
gmem_controller_inst: entity gmem_cntrl
port map(
clk => clk,
cu_valid => cu_gmem_valid,
cu_ready => cu_gmem_ready,
cu_we => cu_gmem_we,
cu_rnw => cu_gmem_rnw,
cu_atomic => cu_gmem_atomic,
cu_atomic_sgntr => cu_gmem_atomic_sgntr,
cu_rqst_addr => cu_rqst_addr,
cu_wrData => cu_gmem_wrData,
WGsDispatched => WGsDispatched,
finish_exec => finish_exec,
start_kernel => start_kernel,
clean_cache => clean_cache,
CUs_gmem_idle => CUs_gmem_idle,
-- read data from cache
rdAck => cache_rdAck_out,
rdAddr => cache_rdAddr_out,
rdData => cache_rdData_out,
atomic_rdData => atomic_rdData,
atomic_rdData_v => atomic_rdData_v,
atomic_sgntr => atomic_sgntr,
-- read axi bus {{{
-- ar channel
axi_araddr => axi_araddr,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_arid => axi_arid,
-- r channel
axi_rdata => axi_rdata,
axi_rlast => axi_rlast,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rid => axi_rid,
-- aw channel
axi_awaddr => axi_awaddr,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_awid => axi_awid,
-- w channel
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_wlast => axi_wlast,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
-- b channel
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bid => axi_bid,
--}}}
nrst => nrst_gmem_cntrl
);
-- fixed signals assignments {{{
m0_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m0_arlen'length));
m1_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m1_arlen'length));
m2_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m2_arlen'length));
m3_arlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m3_arlen'length));
m0_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m1_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m2_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m3_arsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m0_arburst <= "01"; --INCR burst type
m1_arburst <= "01"; --INCR burst type
m2_arburst <= "01"; --INCR burst type
m3_arburst <= "01"; --INCR burst type
m0_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m0_awlen'length));
m1_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m1_awlen'length));
m2_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m2_awlen'length));
m3_awlen <= std_logic_vector(to_unsigned((2**BURST_W)-1, m3_awlen'length));
m0_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m1_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m2_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m3_awsize <= std_logic_vector(to_unsigned(2+GMEM_N_BANK_W, 3)); -- in 2^n bytes,
m0_awburst <= "01"; --INCR burst type
m1_awburst <= "01"; --INCR burst type
m2_awburst <= "01"; --INCR burst type
m3_awburst <= "01"; --INCR burst type
--}}}
-- ar & r assignments {{{
m0_araddr <= std_logic_vector(axi_araddr(0));
m0_arvalid <= axi_arvalid(0);
axi_arready(0) <= m0_arready;
axi_rdata(0) <= m0_rdata;
axi_rlast(0) <= m0_rlast;
axi_rvalid(0) <= m0_rvalid;
axi_rid(0) <= m0_rid;
axi_bid(0) <= m0_bid;
m0_awid <= axi_awid(0);
m0_rready <= axi_rready(0);
m0_arid <= axi_arid(0);
AXI_READ_1: if N_AXI > 1 generate
m1_araddr <= std_logic_vector(axi_araddr(1));
m1_arvalid <= axi_arvalid(1);
axi_arready(1) <= m1_arready;
axi_rdata(1) <= m1_rdata;
axi_rlast(1) <= m1_rlast;
axi_rvalid(1) <= m1_rvalid;
axi_rid(1) <= m1_rid;
axi_bid(1) <= m1_bid;
m1_awid <= axi_awid(1);
m1_rready <= axi_rready(1);
m1_arid <= axi_arid(1);
end generate;
AXI_READ_2: if N_AXI > 2 generate
m2_araddr <= std_logic_vector(axi_araddr(2));
m2_arvalid <= axi_arvalid(2);
axi_arready(2) <= m2_arready;
axi_rdata(2) <= m2_rdata;
axi_rlast(2) <= m2_rlast;
axi_rvalid(2) <= m2_rvalid;
axi_rid(2) <= m2_rid;
axi_bid(2) <= m2_bid;
m2_awid <= axi_awid(2);
m2_rready <= axi_rready(2);
m2_arid <= axi_arid(2);
end generate;
AXI_READ_3: if N_AXI > 3 generate
m3_araddr <= std_logic_vector(axi_araddr(3));
m3_arvalid <= axi_arvalid(3);
axi_arready(3) <= m3_arready;
axi_rdata(3) <= m3_rdata;
axi_rlast(3) <= m3_rlast;
axi_rvalid(3) <= m3_rvalid;
axi_rid(3) <= m3_rid;
axi_bid(3) <= m3_bid;
m3_awid <= axi_awid(3);
m3_rready <= axi_rready(3);
m3_arid <= axi_arid(3);
end generate;
-- }}}
-- aw, w & b assignments {{{
m0_awaddr <= std_logic_vector(axi_awaddr(0));
m0_awvalid <= axi_awvalid(0);
axi_awready(0) <= m0_awready;
m0_wdata <= axi_wdata(0);
m0_wstrb <= axi_wstrb(0);
m0_wlast <= axi_wlast(0);
m0_wvalid <= axi_wvalid(0);
axi_wready(0) <= m0_wready;
axi_bvalid(0) <= m0_bvalid;
m0_bready <= axi_bready(0);
AXI_WRITE_1: if N_AXI > 1 generate
m1_awaddr <= std_logic_vector(axi_awaddr(1));
m1_awvalid <= axi_awvalid(1);
axi_awready(1) <= m1_awready;
m1_wdata <= axi_wdata(1);
m1_wstrb <= axi_wstrb(1);
m1_wlast <= axi_wlast(1);
m1_wvalid <= axi_wvalid(1);
axi_wready(1) <= m1_wready;
axi_bvalid(1) <= m1_bvalid;
m1_bready <= axi_bready(1);
end generate;
AXI_WRITE_2: if N_AXI > 2 generate
m2_awaddr <= std_logic_vector(axi_awaddr(2));
m2_awvalid <= axi_awvalid(2);
axi_awready(2) <= m2_awready;
m2_wdata <= axi_wdata(2);
m2_wstrb <= axi_wstrb(2);
m2_wlast <= axi_wlast(2);
m2_wvalid <= axi_wvalid(2);
axi_wready(2) <= m2_wready;
axi_bvalid(2) <= m2_bvalid;
m2_bready <= axi_bready(2);
end generate;
AXI_WRITE_3: if N_AXI > 3 generate
m3_awaddr <= std_logic_vector(axi_awaddr(3));
m3_awvalid <= axi_awvalid(3);
axi_awready(3) <= m3_awready;
m3_wdata <= axi_wdata(3);
m3_wstrb <= axi_wstrb(3);
m3_wlast <= axi_wlast(3);
m3_wvalid <= axi_wvalid(3);
axi_wready(3) <= m3_wready;
axi_bvalid(3) <= m3_bvalid;
m3_bready <= axi_bready(3);
end generate;
-- }}}
------------------------------------------------------------------------------------------------- }}}
-- WG dispatcher FSM -------------------------------------------------------------------------------------- {{{
regFile_we <= '1' when mainProc_wrAddr(INTERFCE_W_ADDR_W-1 downto INTERFCE_W_ADDR_W-2) = "10" and mainProc_we = '1' else '0';
regs_trans: process(clk)
begin
if rising_edge(clk) then
nrst_gmem_cntrl <= nrst;
if start_kernel = '1' then
clean_cache <= RcleanCache(new_krnl_indx);
initialize_d0 <= RInitiate(new_krnl_indx);
end if;
s0_wdata_d0 <= s0_wdata;
finish_exec_d0 <= finish_exec;
if nrst = '0' then
st_wg_disp <= idle;
Rstat <= (others =>'0');
RcleanCache <= (others=>'0');
Rstart <= (others =>'0');
RInitiate <= (others=>'0');
else
st_wg_disp <= st_wg_disp_n;
-- regFile_we_d0 <= regFile_we;
if start_kernel = '1' then
Rstart(new_krnl_indx) <= '0';
elsif regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = Rstart_regFile_addr then
Rstart <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0);
end if;
if regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = RcleanCache_regFile_addr then
RcleanCache <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0);
end if;
if regFile_we = '1' and to_integer(unsigned(mainProc_wrAddr(N_REG_W-1 downto 0))) = RInitiate_regFile_addr then
RInitiate <= s0_wdata_d0(NEW_KRNL_MAX_INDX-1 downto 0);
end if;
if start_kernel = '1' then
Rstat(new_krnl_indx) <= '0';
elsif finish_exec = '1' and finish_exec_d0 = '0' then
Rstat(finish_krnl_indx) <= '1';
end if;
end if;
end if;
end process;
process(Rstart)
begin
new_krnl_indx <= 0;
for i in NEW_KRNL_MAX_INDX-1 downto 0 loop
if Rstart(i) = '1' then
new_krnl_indx <= i;
end if;
end loop;
end process;
start_kernel <= '1' when st_wg_disp_n = st1_dispatch and st_wg_disp = idle else '0';
process(st_wg_disp, finish_exec, Rstart)
begin
st_wg_disp_n <= st_wg_disp;
case(st_wg_disp) is
when idle =>
if to_integer(unsigned(Rstart)) /= 0 then --new kernel to start
st_wg_disp_n <= st1_dispatch;
end if;
when st1_dispatch =>
if finish_exec = '1' then -- kernel is dispatched
st_wg_disp_n <= idle;
end if;
end case;
end process;
------------------------------------------------------------------------------------------------- }}}
end Behavioral;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_4CUs_no_fdiv_area_estimation.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_4CACHE_W.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_8CUs_fslt_2AXI_2CACHE_WORDS.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
joalcava/sparcv8-monocicle
|
MuxPC.vhd
|
1
|
691
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MuxPC is
Port ( PCdisp30 : in STD_LOGIC_VECTOR(31 downto 0);
PCdisp22 : in STD_LOGIC_VECTOR(31 downto 0);
PC : in STD_LOGIC_VECTOR(31 downto 0);
PCplus1 : in STD_LOGIC_VECTOR(31 downto 0);
PCSource: in STD_LOGIC_VECTOR(1 downto 0);
nPC : out STD_LOGIC_VECTOR(31 downto 0)
);
end MuxPC;
architecture Behavioral of MuxPC is
begin
process(PCdisp30,PCdisp22,PC,PCSource)
begin
if (PCSource="10") then
nPC <= PCdisp22;
elsif (PCsource="01") then
nPC <= PCdisp30;
elsif (PCSource="00") then
nPC <= PC;
else
nPC <= PCplus1;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
Kinxil/VHDL_Projects
|
Mandelbrot/mux2.vhd
|
1
|
1563
|
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
entity muxandcpt is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
i_iters1 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters2 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters3 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters4 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters5 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters6 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters7 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
i_iters8 : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
startVGA : in STD_LOGIC;
o_iters : out STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
doneVGA : out STD_LOGIC);
end muxandcpt;
architecture Behavioral of muxandcpt is
signal cpt : integer range 0 to 7;
begin
process(clock, reset, startVGA, cpt)
begin
if reset='1' then
cpt <= 0;
doneVGA <= '0';
elsif rising_edge(clock) then
if startVGA='1' then
if(cpt=7) then
cpt<=0;
doneVGA<='1';
else
cpt <= cpt + 1;
doneVGA<='0';
end if;
end if;
end if;
end process;
o_iters <= i_iters7 when (cpt = 7) else
i_iters6 when (cpt = 6) else
i_iters5 when (cpt = 5) else
i_iters4 when (cpt = 4) else
i_iters3 when (cpt = 3) else
i_iters2 when (cpt = 2) else
i_iters1 when (cpt = 1) else
i_iters8;
end Behavioral;
|
gpl-3.0
|
Kinxil/VHDL_Projects
|
Mandelbrot/vga_bitmap_160x100.vhd
|
2
|
11975
|
-------------------------------------------------------------------------------
-- Bitmap VGA display
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.CONSTANTS.all;
entity VGA_bitmap_160x100 is
generic(grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
-- ADDR : in std_logic_vector(13 downto 0);
endcalcul : in std_logic;
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end VGA_bitmap_160x100;
architecture Behavioral of VGA_bitmap_160x100 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 16383) of std_logic_vector(bit_per_pixel - 1 downto 0);
signal screen : GRAM; -- the memory representation of the image
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 15999:=0; -- the address at which displayed data is read
signal next_pixel : std_logic_vector(bit_per_pixel - 1 downto 0); -- the data coding the value of the pixel to be displayed
signal ADDR : unsigned(13 downto 0);
begin
ADDRmanagement : process(clk,reset, data_write)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR < 15999 then
ADDR<=ADDR+1;
else
ADDR<=(others=>'0');
end if;
end if;
end if;
end if;
end process;
-- This process performs data access (read and write) to the memory
memory_management : process(clk)
begin
if clk'event and clk='1' then
next_pixel <= screen(pix_read_addr);
data_out <= screen(to_integer(ADDR));
if data_write = '1' then
screen(to_integer(ADDR)) <= data_in;
end if;
end if;
end process;
pixel_read_addr : process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 16)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (not TOP_line) and h_counter = 0 and ((v_counter mod 4)/= 3) then
-- each line is repeated 4 times, the first 3 times, we have to restart at the
-- beginning og the line instead of continue to the next line
pix_read_addr <= pix_read_addr - 160;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 75 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 475 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if (not TOP_line) or (not TOP_display) then
VGA_red <= "0000";
VGA_green <= "0000";
VGA_blue <= "0000";
else
case bit_per_pixel is
when 1 =>
VGA_red <= (others => next_pixel(0));
VGA_green <= (others => next_pixel(0));
VGA_blue <= (others => next_pixel(0));
when 2 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel;
VGA_green <= next_pixel & next_pixel;
VGA_red <= next_pixel & next_pixel;
else
VGA_red <= (others => (next_pixel(0) and next_pixel(1)));
VGA_green <= (others => (next_pixel(1) and not next_pixel(0)));
VGA_blue <= (others => (next_pixel(0) and not next_pixel(1)));
end if;
when 3 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_green <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_red <= next_pixel & next_pixel(bit_per_pixel - 1);
else
VGA_red <= (others => next_pixel(2));
VGA_green <= (others => next_pixel(1));
VGA_blue <= (others => next_pixel(0));
end if;
when 4 =>
if grayscale then
VGA_blue <= next_pixel;
VGA_green <= next_pixel;
VGA_red <= next_pixel;
elsif next_pixel="1000" then
VGA_red <= "0100";
VGA_green <= "0100";
VGA_blue <= "0100";
else
VGA_red(2 downto 0) <= (others => (next_pixel(2) and next_pixel(3)));
VGA_green(2 downto 0) <= (others => (next_pixel(1) and next_pixel(3)));
VGA_blue(2 downto 0) <= (others => (next_pixel(0) and next_pixel(3)));
VGA_red(3) <= next_pixel(2);
VGA_green(3) <= next_pixel(1);
VGA_blue(3) <= next_pixel(0);
end if;
when 5 =>
case to_integer(unsigned(next_pixel)) is
when 0 | 3 | 6 | 9 | 12 | 15 | 18 | 21 | 24 => VGA_blue <= "0000";
when 1 | 4 | 7 | 10 | 13 | 16 | 19 | 22 | 25 => VGA_blue <= "1000";
when others => VGA_blue <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 9 | 10 | 11 | 18 | 19 | 20 => VGA_green <= "0000";
when 3 | 4 | 5 | 12 | 13 | 14 | 21 | 22 | 23 => VGA_green <= "1000";
when others => VGA_green <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => VGA_red <= "0000";
when 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 => VGA_red <= "1000";
when others => VGA_red <= "1111";
end case;
when 6 =>
VGA_red <= next_pixel(5 downto 4) & next_pixel(5 downto 4);
VGA_green <= next_pixel(3 downto 2) & next_pixel(3 downto 2);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 7 =>
VGA_red <= next_pixel(6 downto 5) & next_pixel(6 downto 5);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 8 =>
VGA_red <= next_pixel(7 downto 5) & next_pixel(7);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 9 =>
VGA_red <= next_pixel(8 downto 6) & next_pixel(8);
VGA_green <= next_pixel(5 downto 3) & next_pixel(5);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 10 =>
VGA_red <= next_pixel(9 downto 7) & next_pixel(9);
VGA_green <= next_pixel(6 downto 3);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 11 =>
VGA_red <= next_pixel(10 downto 7);
VGA_green <= next_pixel( 6 downto 3);
VGA_blue <= next_pixel( 2 downto 0) & next_pixel(2);
when 12 =>
VGA_red <= next_pixel(11 downto 8);
VGA_green <= next_pixel( 7 downto 4);
VGA_blue <= next_pixel( 3 downto 0);
when others => null;
end case;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_1CU_min_area.vhd
|
1
|
23421
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 0; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant FADD_DELAY : integer := 11;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 4;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
viccuad/fpga-thingies
|
pong/ps2KeyboardInterface.vhd
|
4
|
2985
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY ps2KeyboardInterface IS
PORT (
clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
END ps2KeyboardInterface;
ARCHITECTURE ps2KeyboardInterfaceArch OF ps2KeyboardInterface IS
SIGNAL ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic;
SIGNAL ps2DataRegOut: std_logic_vector(10 DOWNTO 0);
SIGNAL goodParity: std_logic;
BEGIN
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
ps2ClkSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
ps2ClkSync <= aux1;
aux1 := ps2Clk;
END IF;
END PROCESS synchronizer;
edgeDetector:
PROCESS (rst, clk)
VARIABLE aux1, aux2: std_logic;
BEGIN
ps2ClkFallingEdge <= (NOT aux1) AND aux2;
IF (rst='0') THEN
aux1 := '1';
aux2 := '1';
ELSIF (clk'EVENT AND clk='1') THEN
aux2 := aux1;
aux1 := ps2ClkSync;
END IF;
END PROCESS edgeDetector;
ps2DataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
ps2DataRegOut <= (OTHERS =>'1');
ELSIF (clk'EVENT AND clk='1') THEN
IF (lastBitRcv='1') THEN
ps2DataRegOut <= (OTHERS=>'1');
ELSIF (ps2ClkFallingEdge='1') THEN
ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1);
END IF;
END IF;
END PROCESS ps2DataReg;
oddParityCheker:
goodParity <=
((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6)))
XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2)))
XOR ps2DataRegOut(1);
lastBitRcv <= NOT ps2DataRegOut(0);
validData <= lastBitRcv AND goodParity;
dataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
data <= (OTHERS=>'0');
ELSIF (clk'EVENT AND clk='1') THEN
IF (ldData='1') THEN
data <= ps2DataRegOut(8 downto 1);
END IF;
END IF;
END PROCESS dataReg;
controller:
PROCESS (validData, rst, clk)
TYPE states IS (waitingData, waitingNewDataAck);
VARIABLE state: states;
BEGIN
ldData <= '0';
newData <= '0';
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
ldData <= '1';
END IF;
WHEN waitingNewDataAck =>
newData <= '1';
WHEN OTHERS => NULL;
END CASE;
IF (rst='0') THEN
state := waitingData;
ELSIF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
state := waitingNewDataAck;
END IF;
WHEN waitingNewDataAck =>
IF (newDataAck='1') THEN
state := waitingData;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS controller;
END ps2KeyboardInterfaceArch;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_4CUs_6Stations_2TAGM.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI_4CACHE_WORDS.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 2;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
joalcava/sparcv8-monocicle
|
control_unit.vhd
|
1
|
12657
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_unit is
Port (
op : in STD_LOGIC_VECTOR (1 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
cond: in STD_LOGIC_VECTOR (3 downto 0);
Aluop: out STD_LOGIC_VECTOR (5 downto 0);
wrenDM: out STD_LOGIC;
RFSource: out STD_LOGIC_VECTOR(1 downto 0);
PCSource: out STD_LOGIC_VECTOR(1 downto 0);
RFdest: out STD_LOGIC;
write_enable : out STD_LOGIC);
end control_unit;
architecture arq_UnidadControl of control_unit is
begin
process(op,op2,op3,icc,cond)
begin
if(op = "01") then --CALL
PCSource<= "01";--PC + disp30
write_enable <= '1';--Permitimos guardar datos en RF (Valor actual de PC)
RFSource<= "10";--Elegimos PC
RFdest<='1';--Se debe elegir el O7 en el RF
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
if(op= "00") then
if(op2= "010") then
case cond is
when "1000" => --Branch Always
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
when "1001" => --Branch on Not Equal
if(not(icc(2)) = '1') then --not z
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "0001" => --Branch on Equal
if(icc(2) = '1') then
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "1010" => --Branch on Greater
if((not(icc(2) or (icc(3) xor icc(1)))) = '1') then --not(Z or (N xor V))
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "0010" => --Branch on Less or Equal
if((icc(2) or (icc(3) xor icc(1))) = '1') then --Z or (N xor V)
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "1011" => -- Branch on Greater or Equal
if((not(icc(3) xor icc(1))) = '1') then --not (N xor V)
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when "0011" => --Branch on Less
if((icc(3) xor icc(1)) = '1') then -- (N xor V)
PCSource<= "10";--PC + seu(disp22)
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
else
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
when others =>
PCSource<= "11";--PC + PCaddress
write_enable <= '0';--No Permitimos guardar datos en RF
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end case;
elsif(op2 = "100") then --NOP
PCSource<= "11";--PC + 1
write_enable <= '0';--No Permitimos guardar datos en RF (Valor actual de PC)
RFSource<= "00";--Elegimos aluresult
RFdest<='0';--Se debe elegir nRd
wrenDM <= '0';--No escribimos en DM
Aluop <= "111111";--No hacemos operaciones aritmetico logicas
end if;
elsif(op = "10")then
case op3 is
when "000000" => -- ADD
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010000" => --ADDcc
Aluop <= "001000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "001000" => --ADDX
Aluop <= "001010";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "011000" => --ADDXcc
Aluop <= "001011";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000100" => -- SUB
Aluop <= "000001";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010100" => -- SUBcc
Aluop <= "001001";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "001100" => -- SUBX
Aluop <= "001100";
write_enable <= '1';
RFSource<= "00";
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "011100" => -- SUBXcc
Aluop <= "001101";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000001" => -- AND
Aluop <= "000011";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010001" => -- ANDcc
Aluop <= "001111";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000101" => --ANDN
Aluop <= "000110";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
when "010101" => --ANDNcc
Aluop <= "010001";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000010" => -- OR
Aluop <= "000010";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010010" => -- ORcc
Aluop <= "001110";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000110" => --ORN
Aluop <= "000101";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010110" => --ORNcc
Aluop <= "010010";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000011" => -- XOR
Aluop <= "000100";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010011" => -- XORcc
Aluop <= "010000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000111" => -- XNOR
Aluop <= "000111";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "010111" => -- XNORcc
Aluop <= "010011";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "111100" => -- SAVE
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "111101" => -- RESTORE
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "111000" => --JMPL
Aluop <= "000000";
write_enable <= '1';
wrenDM <= '0';
RFSource<= "10";
PCSource<= "00";--PC calculada
RFdest<='0';--Se debe elegir el nrd en el RF
when "100101" => --SLL
Aluop <= "010100";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "10";
PCSource<= "00";
RFdest<='0';
when "100110" => --SRL
Aluop <= "010101";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "10";
PCSource<= "00";
RFdest<='0';
when others => --En otros casos desconocidos
Aluop <= "111111";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
end case;
elsif(OP = "11") then
case op3 is
when "000100" => --SW
Aluop <= "000000";
write_enable <= '0';
wrenDM <= '1';--Habilitamos la escritura en el DM
RFSource <= "00";
PCSource <= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
when "000000" => --LW
Aluop <= "000000";
write_enable <= '1';--Habilitamos la escritura en el RF
wrenDM <= '0';--Si no habilitamos la escritura, es porque vamos a leer
RFSource <= "01";
PCSource <= "11";--Se salta a PC + 1
RFdest <='0';--Se debe elegir el nrd en el RF
when others =>
Aluop <= "000000";
write_enable <= '0';
wrenDM <= '0';
RFSource<= "00";
PCSource<= "11";--Se salta a PC + 1
RFdest<='0';--Se debe elegir el nrd en el RF
end case;
end if;
end if;
end process;
end arq_UnidadControl;
|
gpl-3.0
|
joalcava/sparcv8-monocicle
|
Test_PC.vhd
|
1
|
1337
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Test_PC IS
END Test_PC;
ARCHITECTURE behavior OF Test_PC IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pc
PORT(
clk : IN std_logic;
rst : IN std_logic;
address : IN std_logic_vector(31 downto 0);
sig : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal address : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal sig : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pc PORT MAP (
clk => clk,
rst => rst,
address => address,
sig => sig
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
address <= x"FFFFFFFF";
wait for 200 ns;
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for 50 ns;
address <= x"11111111";
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
malkadi/FGPU
|
RTL/floating_point/xbip_dsp48_multadd_v3_0_2/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
|
5
|
73491
|
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Hdr9
`protect end_protected
|
gpl-3.0
|
malkadi/FGPU
|
bitstreams/settings_and_utilization/V2_8CUs_2AXI_2CACHE_WORDS.vhd
|
1
|
24067
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
gpl-3.0
|
witoldo7/puc-2
|
PUC/PUC_567/PUC/simulation/qsim/work/cw3_vlg_vec_tst/_primary.vhd
|
2
|
90
|
library verilog;
use verilog.vl_types.all;
entity cw3_vlg_vec_tst is
end cw3_vlg_vec_tst;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/asap-alap-random/hal_alap.vhd
|
1
|
1612
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:58:01)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_alap_entity;
ARCHITECTURE hal_alap_description OF hal_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register2 * register1;
WHEN "00000011" =>
register2 := input4 * 4;
register3 := register3 * 6;
register1 := register1 - 8;
register4 := input5 + 9;
WHEN "00000100" =>
output1 <= register2 + 10;
output2 <= register1 - register3;
IF (register4 < 12) THEN
output3 <= register4;
ELSE
output3 <= "01100";
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_alap_description;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_14.vhd
|
1
|
469703
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_14x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A73: buffer std_logic
);
end x25_14x;
architecture x25_14x_behav of x25_14x is
signal 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1234a,a21235a,a21236a,a21240a,a21241a,a21245a,a21246a,a21247a,a21251a,a21252a,a21255a,a21258a,a21259a,a21260a,a21264a,a21265a,a21269a,a21270a,a21271a,a21275a,a21276a,a21279a,a21282a,a21283a,a21284a,a21288a,a21289a,a21293a,a21294a,a21295a,a21299a,a21300a,a21303a,a21306a,a21307a,a21308a,a21312a,a21313a,a21317a,a21318a,a21319a,a21323a,a21324a,a21327a,a21330a,a21331a,a21332a,a21336a,a21337a,a21341a,a21342a,a21343a,a21347a,a21348a,a21351a,a21354a,a21355a,a21356a,a21360a,a21361a,a21365a,a21366a,a21367a,a21371a,a21372a,a21375a,a21378a,a21379a,a21380a,a21384a,a21385a,a21389a,a21390a,a21391a,a21395a,a21396a,a21399a,a21402a,a21403a,a21404a,a21408a,a21409a,a21413a,a21414a,a21415a,a21419a,a21420a,a21423a,a21426a,a21427a,a21428a,a21432a,a21433a,a21437a,a21438a,a21439a,a21443a,a21444a,a21447a,a21450a,a21451a,a21452a,a21456a,a21457a,a21461a,a21462a,a21463a,a21467a,a21468a,a21471a,a21474a,a21475a,a21476a,a21480a,a21481a,a21485a,a21486a,a21487a,a21491a,a21492a,a21495a,a21498a,a21499a,a21500a,a21504a,a21505a,a21509a,a21510a,a21511a,a21515a,a21516a,a21519a,a21522a,a21523a,a21524a,a21528a,a21529a,a21532a,a21535a,a21536a,a21537a,a21541a,a21542a,a21545a,a21548a,a21549a,a21550a,a21554a,a21555a,a21558a,a21561a,a21562a,a21563a,a21567a,a21568a,a21571a,a21574a,a21575a,a21576a,a21580a,a21581a,a21584a,a21587a,a21588a,a21589a,a21593a,a21594a,a21597a,a21600a,a21601a,a21602a,a21606a,a21607a,a21610a,a21613a,a21614a,a21615a,a21619a,a21620a,a21623a,a21626a,a21627a,a21628a,a21632a,a21633a,a21636a,a21639a,a21640a,a21641a,a21645a,a21646a,a21649a,a21652a,a21653a,a21654a,a21658a,a21659a,a21662a,a21665a,a21666a,a21667a,a21671a,a21672a,a21675a,a21678a,a21679a,a21680a,a21684a,a21685a,a21688a,a21691a,a21692a,a21693a,a21697a,a21698a,a21701a,a21704a,a21705a,a21706a,a21710a,a21711a,a21714a,a21717a,a21718a,a21719a,a21723a,a21724a,a21727a,a21730a,a21731a,a21732a,a21736a,a21737a,a21740a,a21743a,a21744a,a21745a,a21749a,a21750a,a21753a,a21756a,a21757a,a21758a,a21762a,a21763a,a21766a,a21769a,a21770a,a21771a,a21775a,a21776a,a21779a,a21782a,a21783a,a21784a,a21788a,a21789a,a21792a,a21795a,a21796a,a21797a,a21801a,a21802a,a21805a,a21808a,a21809a,a21810a,a21814a,a21815a,a21818a,a21821a,a21822a,a21823a,a21827a,a21828a,a21831a,a21834a,a21835a,a21836a,a21840a,a21841a,a21844a,a21847a,a21848a,a21849a,a21853a,a21854a,a21857a,a21860a,a21861a,a21862a,a21866a,a21867a,a21870a,a21873a,a21874a,a21875a,a21879a,a21880a,a21883a,a21886a,a21887a,a21888a,a21892a,a21893a,a21896a,a21899a,a21900a,a21901a,a21905a,a21906a,a21909a,a21912a,a21913a,a21914a,a21918a,a21919a,a21922a,a21925a,a21926a,a21927a,a21931a,a21932a,a21935a,a21938a,a21939a,a21940a,a21944a,a21945a,a21948a,a21951a,a21952a,a21953a,a21957a,a21958a,a21961a,a21964a,a21965a,a21966a,a21970a,a21971a,a21974a,a21977a,a21978a,a21979a,a21983a,a21984a,a21987a,a21990a,a21991a,a21992a,a21996a,a21997a,a22000a,a22003a,a22004a,a22005a,a22009a,a22010a,a22013a,a22016a,a22017a,a22018a,a22022a,a22023a,a22026a,a22029a,a22030a,a22031a,a22035a,a22036a,a22039a,a22042a,a22043a,a22044a,a22048a,a22049a,a22052a,a22055a,a22056a,a22057a,a22061a,a22062a,a22065a,a22068a,a22069a,a22070a,a22074a,a22075a,a22078a,a22081a,a22082a,a22083a,a22087a,a22088a,a22091a,a22094a,a22095a,a22096a,a22100a,a22101a,a22104a,a22107a,a22108a,a22109a,a22112a,a22115a,a22116a,a22119a,a22122a,a22123a,a22124a,a22128a,a22129a,a22132a,a22135a,a22136a,a22137a,a22140a,a22143a,a22144a,a22147a,a22150a,a22151a,a22152a: std_logic;
begin
A73 <=( a3028a ) or ( a2019a );
a1a <=( a22152a and a22137a );
a2a <=( a22124a and a22109a );
a3a <=( a22096a and a22083a );
a4a <=( a22070a and a22057a );
a5a <=( a22044a and a22031a );
a6a <=( a22018a and a22005a );
a7a <=( a21992a and a21979a );
a8a <=( a21966a and a21953a );
a9a <=( a21940a and a21927a );
a10a <=( a21914a and a21901a );
a11a <=( a21888a and a21875a );
a12a <=( a21862a and a21849a );
a13a <=( a21836a and a21823a );
a14a <=( a21810a and a21797a );
a15a <=( a21784a and a21771a );
a16a <=( a21758a and a21745a );
a17a <=( a21732a and a21719a );
a18a <=( a21706a and a21693a );
a19a <=( a21680a and a21667a );
a20a <=( a21654a and a21641a );
a21a <=( a21628a and a21615a );
a22a <=( a21602a and a21589a );
a23a <=( a21576a and a21563a );
a24a <=( a21550a and a21537a );
a25a <=( a21524a and a21511a );
a26a <=( a21500a and a21487a );
a27a <=( a21476a and a21463a );
a28a <=( a21452a and a21439a );
a29a <=( a21428a and a21415a );
a30a <=( a21404a and a21391a );
a31a <=( a21380a and a21367a );
a32a <=( a21356a and a21343a );
a33a <=( a21332a and a21319a );
a34a <=( a21308a and a21295a );
a35a <=( a21284a and a21271a );
a36a <=( a21260a and a21247a );
a37a <=( a21236a and a21223a );
a38a <=( a21212a and a21199a );
a39a <=( a21188a and a21175a );
a40a <=( a21164a and a21151a );
a41a <=( a21140a and a21127a );
a42a <=( a21116a and a21103a );
a43a <=( a21092a and a21079a );
a44a <=( a21068a and a21055a );
a45a <=( a21044a and a21031a );
a46a <=( a21020a and a21007a );
a47a <=( a20996a and a20983a );
a48a <=( a20972a and a20959a );
a49a <=( a20948a and a20935a );
a50a <=( a20924a and a20911a );
a51a <=( a20900a and a20887a );
a52a <=( a20876a and a20863a );
a53a <=( a20852a and a20839a );
a54a <=( a20828a and a20815a );
a55a <=( a20804a and a20791a );
a56a <=( a20780a and a20767a );
a57a <=( a20756a and a20743a );
a58a <=( a20732a and a20719a );
a59a <=( a20708a and a20695a );
a60a <=( a20684a and a20671a );
a61a <=( a20660a and a20647a );
a62a <=( a20636a and a20623a );
a63a <=( a20612a and a20599a );
a64a <=( a20588a and a20575a );
a65a <=( a20564a and a20551a );
a66a <=( a20540a and a20527a );
a67a <=( a20516a and a20503a );
a68a <=( a20492a and a20479a );
a69a <=( a20468a and a20455a );
a70a <=( a20444a and a20431a );
a71a <=( a20420a and a20407a );
a72a <=( a20396a and a20383a );
a73a <=( a20372a and a20359a );
a74a <=( a20348a and a20335a );
a75a <=( a20324a and a20311a );
a76a <=( a20300a and a20287a );
a77a <=( a20276a and a20263a );
a78a <=( a20252a and a20239a );
a79a <=( a20228a and a20215a );
a80a <=( a20204a and a20191a );
a81a <=( a20180a and a20167a );
a82a <=( a20156a and a20143a );
a83a <=( a20132a and a20119a );
a84a <=( a20108a and a20095a );
a85a <=( a20084a and a20071a );
a86a <=( a20060a and a20047a );
a87a <=( a20036a and a20023a );
a88a <=( a20012a and a19999a );
a89a <=( a19988a and a19975a );
a90a <=( a19964a and a19951a );
a91a <=( a19940a and a19927a );
a92a <=( a19916a and a19903a );
a93a <=( a19892a and a19879a );
a94a <=( a19868a and a19855a );
a95a <=( a19844a and a19831a );
a96a <=( a19820a and a19807a );
a97a <=( a19796a and a19783a );
a98a <=( a19772a and a19759a );
a99a <=( a19748a and a19735a );
a100a <=( a19724a and a19711a );
a101a <=( a19700a and a19687a );
a102a <=( a19676a and a19663a );
a103a <=( a19652a and a19639a );
a104a <=( a19628a and a19615a );
a105a <=( a19604a and a19591a );
a106a <=( a19580a and a19567a );
a107a <=( a19556a and a19543a );
a108a <=( a19532a and a19519a );
a109a <=( a19508a and a19495a );
a110a <=( a19484a and a19471a );
a111a <=( a19460a and a19447a );
a112a <=( a19436a and a19423a );
a113a <=( a19412a and a19399a );
a114a <=( a19388a and a19375a );
a115a <=( a19364a and a19351a );
a116a <=( a19340a and a19327a );
a117a <=( a19316a and a19303a );
a118a <=( a19292a and a19281a );
a119a <=( a19270a and a19259a );
a120a <=( a19248a and a19237a );
a121a <=( a19226a and a19215a );
a122a <=( a19204a and a19193a );
a123a <=( a19182a and a19171a );
a124a <=( a19160a and a19149a );
a125a <=( a19138a and a19127a );
a126a <=( a19116a and a19105a );
a127a <=( a19094a and a19083a );
a128a <=( a19072a and a19061a );
a129a <=( a19050a and a19039a );
a130a <=( a19028a and a19017a );
a131a <=( a19006a and a18995a );
a132a <=( a18984a and a18973a );
a133a <=( a18962a and a18951a );
a134a <=( a18940a and a18929a );
a135a <=( a18918a and a18907a );
a136a <=( a18896a and a18885a );
a137a <=( a18874a and a18863a );
a138a <=( a18852a and a18841a );
a139a <=( a18830a and a18819a );
a140a <=( a18808a and a18797a );
a141a <=( a18786a and a18775a );
a142a <=( a18764a and a18753a );
a143a <=( a18742a and a18731a );
a144a <=( a18720a and a18709a );
a145a <=( a18698a and a18687a );
a146a <=( a18676a and a18665a );
a147a <=( a18654a and a18643a );
a148a <=( a18632a and a18621a );
a149a <=( a18610a and a18599a );
a150a <=( a18588a and a18577a );
a151a <=( a18566a and a18555a );
a152a <=( a18544a and a18533a );
a153a <=( a18522a and a18511a );
a154a <=( a18500a and a18489a );
a155a <=( a18478a and a18467a );
a156a <=( a18456a and a18445a );
a157a <=( a18434a and a18423a );
a158a <=( a18412a and a18401a );
a159a <=( a18390a and a18379a );
a160a <=( a18368a and a18357a );
a161a <=( a18346a and a18335a );
a162a <=( a18324a and a18313a );
a163a <=( a18302a and a18291a );
a164a <=( a18280a and a18269a );
a165a <=( a18258a and a18247a );
a166a <=( a18236a and a18225a );
a167a <=( a18214a and a18203a );
a168a <=( a18192a and a18181a );
a169a <=( a18170a and a18159a );
a170a <=( a18148a and a18137a );
a171a <=( a18126a and a18115a );
a172a <=( a18104a and a18093a );
a173a <=( a18082a and a18071a );
a174a <=( a18060a and a18049a );
a175a <=( a18038a and a18027a );
a176a <=( a18016a and a18005a );
a177a <=( a17994a and a17983a );
a178a <=( a17972a and a17961a );
a179a <=( a17950a and a17939a );
a180a <=( a17928a and a17917a );
a181a <=( a17906a and a17895a );
a182a <=( a17884a and a17873a );
a183a <=( a17862a and a17851a );
a184a <=( a17840a and a17829a );
a185a <=( a17818a and a17807a );
a186a <=( a17796a and a17785a );
a187a <=( a17774a and a17763a );
a188a <=( a17752a and a17741a );
a189a <=( a17730a and a17719a );
a190a <=( a17708a and a17697a );
a191a <=( a17686a and a17675a );
a192a <=( a17664a and a17653a );
a193a <=( a17642a and a17631a );
a194a <=( a17620a and a17609a );
a195a <=( a17598a and a17587a );
a196a <=( a17576a and a17565a );
a197a <=( a17554a and a17543a );
a198a <=( a17532a and a17521a );
a199a <=( a17510a and a17499a );
a200a <=( a17488a and a17477a );
a201a <=( a17466a and a17455a );
a202a <=( a17444a and a17433a );
a203a <=( a17422a and a17411a );
a204a <=( a17400a and a17389a );
a205a <=( a17378a and a17367a );
a206a <=( a17356a and a17345a );
a207a <=( a17334a and a17323a );
a208a <=( a17312a and a17301a );
a209a <=( a17290a and a17279a );
a210a <=( a17268a and a17257a );
a211a <=( a17246a and a17235a );
a212a <=( a17224a and a17213a );
a213a <=( a17202a and a17191a );
a214a <=( a17180a and a17169a );
a215a <=( a17158a and a17147a );
a216a <=( a17136a and a17125a );
a217a <=( a17114a and a17103a );
a218a <=( a17092a and a17081a );
a219a <=( a17070a and a17059a );
a220a <=( a17048a and a17037a );
a221a <=( a17026a and a17015a );
a222a <=( a17004a and a16993a );
a223a <=( a16982a and a16971a );
a224a <=( a16960a and a16949a );
a225a <=( a16938a and a16927a );
a226a <=( a16916a and a16905a );
a227a <=( a16894a and a16883a );
a228a <=( a16872a and a16861a );
a229a <=( a16850a and a16839a );
a230a <=( a16828a and a16817a );
a231a <=( a16806a and a16795a );
a232a <=( a16784a and a16773a );
a233a <=( a16762a and a16751a );
a234a <=( a16740a and a16729a );
a235a <=( a16718a and a16707a );
a236a <=( a16696a and a16685a );
a237a <=( a16674a and a16663a );
a238a <=( a16652a and a16641a );
a239a <=( a16630a and a16619a );
a240a <=( a16608a and a16597a );
a241a <=( a16586a and a16575a );
a242a <=( a16564a and a16553a );
a243a <=( a16542a and a16531a );
a244a <=( a16520a and a16509a );
a245a <=( a16498a and a16487a );
a246a <=( a16476a and a16465a );
a247a <=( a16454a and a16443a );
a248a <=( a16432a and a16421a );
a249a <=( a16410a and a16399a );
a250a <=( a16388a and a16377a );
a251a <=( a16366a and a16355a );
a252a <=( a16344a and a16333a );
a253a <=( a16322a and a16311a );
a254a <=( a16300a and a16289a );
a255a <=( a16278a and a16267a );
a256a <=( a16256a and a16245a );
a257a <=( a16234a and a16223a );
a258a <=( a16212a and a16201a );
a259a <=( a16190a and a16179a );
a260a <=( a16168a and a16157a );
a261a <=( a16146a and a16135a );
a262a <=( a16124a and a16113a );
a263a <=( a16102a and a16091a );
a264a <=( a16080a and a16069a );
a265a <=( a16058a and a16047a );
a266a <=( a16036a and a16025a );
a267a <=( a16014a and a16003a );
a268a <=( a15992a and a15981a );
a269a <=( a15970a and a15959a );
a270a <=( a15948a and a15937a );
a271a <=( a15926a and a15915a );
a272a <=( a15904a and a15893a );
a273a <=( a15882a and a15871a );
a274a <=( a15860a and a15849a );
a275a <=( a15838a and a15827a );
a276a <=( a15816a and a15805a );
a277a <=( a15794a and a15783a );
a278a <=( a15772a and a15761a );
a279a <=( a15750a and a15739a );
a280a <=( a15728a and a15717a );
a281a <=( a15706a and a15695a );
a282a <=( a15684a and a15673a );
a283a <=( a15662a and a15651a );
a284a <=( a15640a and a15629a );
a285a <=( a15618a and a15607a );
a286a <=( a15596a and a15585a );
a287a <=( a15574a and a15563a );
a288a <=( a15552a and a15541a );
a289a <=( a15530a and a15519a );
a290a <=( a15508a and a15497a );
a291a <=( a15486a and a15475a );
a292a <=( a15464a and a15453a );
a293a <=( a15442a and a15431a );
a294a <=( a15420a and a15409a );
a295a <=( a15398a and a15387a );
a296a <=( a15376a and a15365a );
a297a <=( a15354a and a15343a );
a298a <=( a15332a and a15321a );
a299a <=( a15310a and a15299a );
a300a <=( a15288a and a15277a );
a301a <=( a15266a and a15255a );
a302a <=( a15244a and a15233a );
a303a <=( a15222a and a15211a );
a304a <=( a15200a and a15189a );
a305a <=( a15178a and a15167a );
a306a <=( a15156a and a15145a );
a307a <=( a15134a and a15123a );
a308a <=( a15112a and a15101a );
a309a <=( a15090a and a15079a );
a310a <=( a15068a and a15057a );
a311a <=( a15046a and a15035a );
a312a <=( a15024a and a15013a );
a313a <=( a15002a and a14991a );
a314a <=( a14980a and a14969a );
a315a <=( a14958a and a14947a );
a316a <=( a14936a and a14925a );
a317a <=( a14916a and a14905a );
a318a <=( a14896a and a14885a );
a319a <=( a14876a and a14865a );
a320a <=( a14856a and a14845a );
a321a <=( a14836a and a14825a );
a322a <=( a14816a and a14805a );
a323a <=( a14796a and a14785a );
a324a <=( a14776a and a14765a );
a325a <=( a14756a and a14745a );
a326a <=( a14736a and a14725a );
a327a <=( a14716a and a14705a );
a328a <=( a14696a and a14685a );
a329a <=( a14676a and a14665a );
a330a <=( a14656a and a14645a );
a331a <=( a14636a and a14625a );
a332a <=( a14616a and a14605a );
a333a <=( a14596a and a14585a );
a334a <=( a14576a and a14565a );
a335a <=( a14556a and a14545a );
a336a <=( a14536a and a14525a );
a337a <=( a14516a and a14505a );
a338a <=( a14496a and a14485a );
a339a <=( a14476a and a14465a );
a340a <=( a14456a and a14445a );
a341a <=( a14436a and a14425a );
a342a <=( a14416a and a14405a );
a343a <=( a14396a and a14385a );
a344a <=( a14376a and a14365a );
a345a <=( a14356a and a14345a );
a346a <=( a14336a and a14325a );
a347a <=( a14316a and a14305a );
a348a <=( a14296a and a14285a );
a349a <=( a14276a and a14265a );
a350a <=( a14256a and a14245a );
a351a <=( a14236a and a14225a );
a352a <=( a14216a and a14205a );
a353a <=( a14196a and a14185a );
a354a <=( a14176a and a14165a );
a355a <=( a14156a and a14145a );
a356a <=( a14136a and a14125a );
a357a <=( a14116a and a14105a );
a358a <=( a14096a and a14085a );
a359a <=( a14076a and a14065a );
a360a <=( a14056a and a14045a );
a361a <=( a14036a and a14025a );
a362a <=( a14016a and a14005a );
a363a <=( a13996a and a13985a );
a364a <=( a13976a and a13965a );
a365a <=( a13956a and a13945a );
a366a <=( a13936a and a13925a );
a367a <=( a13916a and a13905a );
a368a <=( a13896a and a13885a );
a369a <=( a13876a and a13865a );
a370a <=( a13856a and a13845a );
a371a <=( a13836a and a13825a );
a372a <=( a13816a and a13805a );
a373a <=( a13796a and a13785a );
a374a <=( a13776a and a13765a );
a375a <=( a13756a and a13745a );
a376a <=( a13736a and a13725a );
a377a <=( a13716a and a13705a );
a378a <=( a13696a and a13685a );
a379a <=( a13676a and a13665a );
a380a <=( a13656a and a13645a );
a381a <=( a13636a and a13625a );
a382a <=( a13616a and a13605a );
a383a <=( a13596a and a13585a );
a384a <=( a13576a and a13565a );
a385a <=( a13556a and a13545a );
a386a <=( a13536a and a13525a );
a387a <=( a13516a and a13505a );
a388a <=( a13496a and a13485a );
a389a <=( a13476a and a13465a );
a390a <=( a13456a and a13445a );
a391a <=( a13436a and a13425a );
a392a <=( a13416a and a13405a );
a393a <=( a13396a and a13385a );
a394a <=( a13376a and a13365a );
a395a <=( a13356a and a13345a );
a396a <=( a13336a and a13325a );
a397a <=( a13316a and a13305a );
a398a <=( a13296a and a13285a );
a399a <=( a13276a and a13265a );
a400a <=( a13256a and a13245a );
a401a <=( a13236a and a13225a );
a402a <=( a13216a and a13205a );
a403a <=( a13196a and a13185a );
a404a <=( a13176a and a13165a );
a405a <=( a13156a and a13145a );
a406a <=( a13136a and a13125a );
a407a <=( a13116a and a13105a );
a408a <=( a13096a and a13085a );
a409a <=( a13076a and a13065a );
a410a <=( a13056a and a13045a );
a411a <=( a13036a and a13025a );
a412a <=( a13016a and a13005a );
a413a <=( a12996a and a12985a );
a414a <=( a12976a and a12965a );
a415a <=( a12956a and a12945a );
a416a <=( a12936a and a12925a );
a417a <=( a12916a and a12905a );
a418a <=( a12896a and a12885a );
a419a <=( a12876a and a12865a );
a420a <=( a12856a and a12845a );
a421a <=( a12836a and a12825a );
a422a <=( a12816a and a12805a );
a423a <=( a12796a and a12785a );
a424a <=( a12776a and a12765a );
a425a <=( a12756a and a12745a );
a426a <=( a12736a and a12725a );
a427a <=( a12716a and a12705a );
a428a <=( a12696a and a12685a );
a429a <=( a12676a and a12665a );
a430a <=( a12656a and a12645a );
a431a <=( a12636a and a12625a );
a432a <=( a12616a and a12605a );
a433a <=( a12596a and a12585a );
a434a <=( a12576a and a12565a );
a435a <=( a12556a and a12545a );
a436a <=( a12536a and a12525a );
a437a <=( a12516a and a12505a );
a438a <=( a12496a and a12485a );
a439a <=( a12476a and a12465a );
a440a <=( a12456a and a12445a );
a441a <=( a12436a and a12425a );
a442a <=( a12416a and a12405a );
a443a <=( a12396a and a12385a );
a444a <=( a12376a and a12365a );
a445a <=( a12356a and a12345a );
a446a <=( a12336a and a12325a );
a447a <=( a12316a and a12305a );
a448a <=( a12296a and a12285a );
a449a <=( a12276a and a12265a );
a450a <=( a12256a and a12245a );
a451a <=( a12236a and a12225a );
a452a <=( a12216a and a12205a );
a453a <=( a12196a and a12185a );
a454a <=( a12176a and a12165a );
a455a <=( a12156a and a12145a );
a456a <=( a12136a and a12125a );
a457a <=( a12116a and a12105a );
a458a <=( a12096a and a12085a );
a459a <=( a12076a and a12065a );
a460a <=( a12056a and a12045a );
a461a <=( a12036a and a12025a );
a462a <=( a12016a and a12005a );
a463a <=( a11996a and a11985a );
a464a <=( a11976a and a11965a );
a465a <=( a11956a and a11945a );
a466a <=( a11936a and a11925a );
a467a <=( a11916a and a11905a );
a468a <=( a11896a and a11885a );
a469a <=( a11876a and a11865a );
a470a <=( a11856a and a11845a );
a471a <=( a11836a and a11825a );
a472a <=( a11816a and a11805a );
a473a <=( a11796a and a11785a );
a474a <=( a11776a and a11765a );
a475a <=( a11756a and a11745a );
a476a <=( a11736a and a11725a );
a477a <=( a11716a and a11705a );
a478a <=( a11696a and a11685a );
a479a <=( a11676a and a11665a );
a480a <=( a11656a and a11645a );
a481a <=( a11636a and a11625a );
a482a <=( a11616a and a11605a );
a483a <=( a11596a and a11585a );
a484a <=( a11576a and a11565a );
a485a <=( a11556a and a11545a );
a486a <=( a11536a and a11525a );
a487a <=( a11516a and a11505a );
a488a <=( a11496a and a11485a );
a489a <=( a11476a and a11465a );
a490a <=( a11456a and a11445a );
a491a <=( a11436a and a11425a );
a492a <=( a11416a and a11405a );
a493a <=( a11396a and a11385a );
a494a <=( a11376a and a11365a );
a495a <=( a11356a and a11345a );
a496a <=( a11336a and a11325a );
a497a <=( a11316a and a11305a );
a498a <=( a11296a and a11285a );
a499a <=( a11276a and a11265a );
a500a <=( a11256a and a11245a );
a501a <=( a11236a and a11225a );
a502a <=( a11216a and a11205a );
a503a <=( a11196a and a11185a );
a504a <=( a11176a and a11165a );
a505a <=( a11156a and a11145a );
a506a <=( a11136a and a11125a );
a507a <=( a11116a and a11105a );
a508a <=( a11096a and a11085a );
a509a <=( a11076a and a11065a );
a510a <=( a11056a and a11045a );
a511a <=( a11036a and a11025a );
a512a <=( a11016a and a11005a );
a513a <=( a10996a and a10985a );
a514a <=( a10976a and a10965a );
a515a <=( a10956a and a10945a );
a516a <=( a10936a and a10925a );
a517a <=( a10916a and a10905a );
a518a <=( a10896a and a10885a );
a519a <=( a10876a and a10865a );
a520a <=( a10856a and a10845a );
a521a <=( a10836a and a10825a );
a522a <=( a10816a and a10805a );
a523a <=( a10796a and a10785a );
a524a <=( a10776a and a10765a );
a525a <=( a10756a and a10745a );
a526a <=( a10736a and a10725a );
a527a <=( a10716a and a10705a );
a528a <=( a10696a and a10685a );
a529a <=( a10676a and a10665a );
a530a <=( a10656a and a10645a );
a531a <=( a10636a and a10625a );
a532a <=( a10616a and a10605a );
a533a <=( a10596a and a10585a );
a534a <=( a10576a and a10565a );
a535a <=( a10556a and a10545a );
a536a <=( a10536a and a10525a );
a537a <=( a10516a and a10505a );
a538a <=( a10496a and a10485a );
a539a <=( a10476a and a10465a );
a540a <=( a10456a and a10445a );
a541a <=( a10436a and a10425a );
a542a <=( a10416a and a10405a );
a543a <=( a10396a and a10385a );
a544a <=( a10376a and a10365a );
a545a <=( a10356a and a10345a );
a546a <=( a10336a and a10325a );
a547a <=( a10316a and a10305a );
a548a <=( a10296a and a10285a );
a549a <=( a10276a and a10265a );
a550a <=( a10256a and a10245a );
a551a <=( a10236a and a10225a );
a552a <=( a10216a and a10205a );
a553a <=( a10196a and a10185a );
a554a <=( a10176a and a10165a );
a555a <=( a10156a and a10145a );
a556a <=( a10136a and a10125a );
a557a <=( a10116a and a10105a );
a558a <=( a10096a and a10085a );
a559a <=( a10076a and a10065a );
a560a <=( a10056a and a10045a );
a561a <=( a10036a and a10025a );
a562a <=( a10016a and a10005a );
a563a <=( a9996a and a9985a );
a564a <=( a9976a and a9967a );
a565a <=( a9958a and a9949a );
a566a <=( a9940a and a9931a );
a567a <=( a9922a and a9913a );
a568a <=( a9904a and a9895a );
a569a <=( a9886a and a9877a );
a570a <=( a9868a and a9859a );
a571a <=( a9850a and a9841a );
a572a <=( a9832a and a9823a );
a573a <=( a9814a and a9805a );
a574a <=( a9796a and a9787a );
a575a <=( a9778a and a9769a );
a576a <=( a9760a and a9751a );
a577a <=( a9742a and a9733a );
a578a <=( a9724a and a9715a );
a579a <=( a9706a and a9697a );
a580a <=( a9688a and a9679a );
a581a <=( a9670a and a9661a );
a582a <=( a9652a and a9643a );
a583a <=( a9634a and a9625a );
a584a <=( a9616a and a9607a );
a585a <=( a9598a and a9589a );
a586a <=( a9580a and a9571a );
a587a <=( a9562a and a9553a );
a588a <=( a9544a and a9535a );
a589a <=( a9526a and a9517a );
a590a <=( a9508a and a9499a );
a591a <=( a9490a and a9481a );
a592a <=( a9472a and a9463a );
a593a <=( a9454a and a9445a );
a594a <=( a9436a and a9427a );
a595a <=( a9418a and a9409a );
a596a <=( a9400a and a9391a );
a597a <=( a9382a and a9373a );
a598a <=( a9364a and a9355a );
a599a <=( a9346a and a9337a );
a600a <=( a9328a and a9319a );
a601a <=( a9310a and a9301a );
a602a <=( a9292a and a9283a );
a603a <=( a9274a and a9265a );
a604a <=( a9256a and a9247a );
a605a <=( a9238a and a9229a );
a606a <=( a9220a and a9211a );
a607a <=( a9202a and a9193a );
a608a <=( a9184a and a9175a );
a609a <=( a9166a and a9157a );
a610a <=( a9148a and a9139a );
a611a <=( a9130a and a9121a );
a612a <=( a9112a and a9103a );
a613a <=( a9094a and a9085a );
a614a <=( a9076a and a9067a );
a615a <=( a9058a and a9049a );
a616a <=( a9040a and a9031a );
a617a <=( a9022a and a9013a );
a618a <=( a9004a and a8995a );
a619a <=( a8986a and a8977a );
a620a <=( a8968a and a8959a );
a621a <=( a8950a and a8941a );
a622a <=( a8932a and a8923a );
a623a <=( a8914a and a8905a );
a624a <=( a8896a and a8887a );
a625a <=( a8878a and a8869a );
a626a <=( a8860a and a8851a );
a627a <=( a8842a and a8833a );
a628a <=( a8824a and a8815a );
a629a <=( a8806a and a8797a );
a630a <=( a8788a and a8779a );
a631a <=( a8770a and a8761a );
a632a <=( a8752a and a8743a );
a633a <=( a8734a and a8725a );
a634a <=( a8716a and a8707a );
a635a <=( a8698a and a8689a );
a636a <=( a8680a and a8671a );
a637a <=( a8662a and a8653a );
a638a <=( a8644a and a8635a );
a639a <=( a8626a and a8617a );
a640a <=( a8608a and a8599a );
a641a <=( a8590a and a8581a );
a642a <=( a8572a and a8563a );
a643a <=( a8554a and a8545a );
a644a <=( a8536a and a8527a );
a645a <=( a8518a and a8509a );
a646a <=( a8500a and a8491a );
a647a <=( a8482a and a8473a );
a648a <=( a8464a and a8455a );
a649a <=( a8446a and a8437a );
a650a <=( a8428a and a8419a );
a651a <=( a8410a and a8401a );
a652a <=( a8392a and a8383a );
a653a <=( a8374a and a8365a );
a654a <=( a8356a and a8347a );
a655a <=( a8338a and a8329a );
a656a <=( a8320a and a8311a );
a657a <=( a8302a and a8293a );
a658a <=( a8284a and a8275a );
a659a <=( a8266a and a8257a );
a660a <=( a8248a and a8239a );
a661a <=( a8230a and a8221a );
a662a <=( a8212a and a8203a );
a663a <=( a8194a and a8185a );
a664a <=( a8176a and a8167a );
a665a <=( a8158a and a8149a );
a666a <=( a8140a and a8131a );
a667a <=( a8122a and a8113a );
a668a <=( a8104a and a8095a );
a669a <=( a8086a and a8077a );
a670a <=( a8068a and a8059a );
a671a <=( a8050a and a8041a );
a672a <=( a8032a and a8023a );
a673a <=( a8014a and a8005a );
a674a <=( a7996a and a7987a );
a675a <=( a7978a and a7969a );
a676a <=( a7960a and a7951a );
a677a <=( a7942a and a7933a );
a678a <=( a7924a and a7915a );
a679a <=( a7906a and a7897a );
a680a <=( a7888a and a7879a );
a681a <=( a7870a and a7861a );
a682a <=( a7852a and a7843a );
a683a <=( a7834a and a7825a );
a684a <=( a7816a and a7807a );
a685a <=( a7798a and a7789a );
a686a <=( a7780a and a7771a );
a687a <=( a7762a and a7753a );
a688a <=( a7744a and a7735a );
a689a <=( a7726a and a7717a );
a690a <=( a7708a and a7699a );
a691a <=( a7690a and a7681a );
a692a <=( a7672a and a7663a );
a693a <=( a7654a and a7645a );
a694a <=( a7636a and a7627a );
a695a <=( a7618a and a7609a );
a696a <=( a7600a and a7591a );
a697a <=( a7582a and a7573a );
a698a <=( a7564a and a7555a );
a699a <=( a7546a and a7537a );
a700a <=( a7528a and a7519a );
a701a <=( a7510a and a7501a );
a702a <=( a7492a and a7483a );
a703a <=( a7474a and a7465a );
a704a <=( a7456a and a7447a );
a705a <=( a7438a and a7429a );
a706a <=( a7420a and a7411a );
a707a <=( a7402a and a7393a );
a708a <=( a7384a and a7375a );
a709a <=( a7366a and a7357a );
a710a <=( a7348a and a7339a );
a711a <=( a7330a and a7321a );
a712a <=( a7312a and a7303a );
a713a <=( a7294a and a7285a );
a714a <=( a7276a and a7267a );
a715a <=( a7258a and a7249a );
a716a <=( a7240a and a7231a );
a717a <=( a7222a and a7213a );
a718a <=( a7204a and a7195a );
a719a <=( a7186a and a7177a );
a720a <=( a7168a and a7159a );
a721a <=( a7150a and a7141a );
a722a <=( a7132a and a7123a );
a723a <=( a7114a and a7105a );
a724a <=( a7096a and a7087a );
a725a <=( a7078a and a7069a );
a726a <=( a7060a and a7051a );
a727a <=( a7042a and a7033a );
a728a <=( a7024a and a7015a );
a729a <=( a7006a and a6997a );
a730a <=( a6988a and a6979a );
a731a <=( a6970a and a6961a );
a732a <=( a6952a and a6943a );
a733a <=( a6934a and a6925a );
a734a <=( a6916a and a6907a );
a735a <=( a6898a and a6889a );
a736a <=( a6880a and a6871a );
a737a <=( a6862a and a6853a );
a738a <=( a6844a and a6835a );
a739a <=( a6826a and a6817a );
a740a <=( a6808a and a6799a );
a741a <=( a6790a and a6781a );
a742a <=( a6772a and a6763a );
a743a <=( a6754a and a6745a );
a744a <=( a6736a and a6727a );
a745a <=( a6718a and a6709a );
a746a <=( a6700a and a6691a );
a747a <=( a6682a and a6673a );
a748a <=( a6664a and a6655a );
a749a <=( a6646a and a6637a );
a750a <=( a6628a and a6619a );
a751a <=( a6610a and a6601a );
a752a <=( a6592a and a6583a );
a753a <=( a6574a and a6565a );
a754a <=( a6556a and a6547a );
a755a <=( a6538a and a6529a );
a756a <=( a6520a and a6511a );
a757a <=( a6502a and a6493a );
a758a <=( a6484a and a6475a );
a759a <=( a6466a and a6457a );
a760a <=( a6448a and a6439a );
a761a <=( a6430a and a6421a );
a762a <=( a6412a and a6403a );
a763a <=( a6394a and a6385a );
a764a <=( a6376a and a6367a );
a765a <=( a6358a and a6349a );
a766a <=( a6340a and a6331a );
a767a <=( a6322a and a6313a );
a768a <=( a6304a and a6295a );
a769a <=( a6286a and a6277a );
a770a <=( a6268a and a6259a );
a771a <=( a6250a and a6241a );
a772a <=( a6232a and a6223a );
a773a <=( a6214a and a6205a );
a774a <=( a6196a and a6187a );
a775a <=( a6180a and a6171a );
a776a <=( a6164a and a6155a );
a777a <=( a6148a and a6139a );
a778a <=( a6132a and a6123a );
a779a <=( a6116a and a6107a );
a780a <=( a6100a and a6091a );
a781a <=( a6084a and a6075a );
a782a <=( a6068a and a6059a );
a783a <=( a6052a and a6043a );
a784a <=( a6036a and a6027a );
a785a <=( a6020a and a6011a );
a786a <=( a6004a and a5995a );
a787a <=( a5988a and a5979a );
a788a <=( a5972a and a5963a );
a789a <=( a5956a and a5947a );
a790a <=( a5940a and a5931a );
a791a <=( a5924a and a5915a );
a792a <=( a5908a and a5899a );
a793a <=( a5892a and a5883a );
a794a <=( a5876a and a5867a );
a795a <=( a5860a and a5851a );
a796a <=( a5844a and a5835a );
a797a <=( a5828a and a5819a );
a798a <=( a5812a and a5803a );
a799a <=( a5796a and a5787a );
a800a <=( a5780a and a5771a );
a801a <=( a5764a and a5755a );
a802a <=( a5748a and a5739a );
a803a <=( a5732a and a5723a );
a804a <=( a5716a and a5707a );
a805a <=( a5700a and a5691a );
a806a <=( a5684a and a5675a );
a807a <=( a5668a and a5659a );
a808a <=( a5652a and a5643a );
a809a <=( a5636a and a5627a );
a810a <=( a5620a and a5611a );
a811a <=( a5604a and a5595a );
a812a <=( a5588a and a5579a );
a813a <=( a5572a and a5563a );
a814a <=( a5556a and a5547a );
a815a <=( a5540a and a5531a );
a816a <=( a5524a and a5515a );
a817a <=( a5508a and a5499a );
a818a <=( a5492a and a5483a );
a819a <=( a5476a and a5467a );
a820a <=( a5460a and a5451a );
a821a <=( a5444a and a5435a );
a822a <=( a5428a and a5419a );
a823a <=( a5412a and a5403a );
a824a <=( a5396a and a5387a );
a825a <=( a5380a and a5371a );
a826a <=( a5364a and a5355a );
a827a <=( a5348a and a5339a );
a828a <=( a5332a and a5323a );
a829a <=( a5316a and a5307a );
a830a <=( a5300a and a5291a );
a831a <=( a5284a and a5275a );
a832a <=( a5268a and a5259a );
a833a <=( a5252a and a5243a );
a834a <=( a5236a and a5227a );
a835a <=( a5220a and a5211a );
a836a <=( a5204a and a5195a );
a837a <=( a5188a and a5179a );
a838a <=( a5172a and a5163a );
a839a <=( a5156a and a5147a );
a840a <=( a5140a and a5131a );
a841a <=( a5124a and a5115a );
a842a <=( a5108a and a5099a );
a843a <=( a5092a and a5083a );
a844a <=( a5076a and a5067a );
a845a <=( a5060a and a5051a );
a846a <=( a5044a and a5035a );
a847a <=( a5028a and a5019a );
a848a <=( a5012a and a5003a );
a849a <=( a4996a and a4987a );
a850a <=( a4980a and a4971a );
a851a <=( a4964a and a4955a );
a852a <=( a4948a and a4939a );
a853a <=( a4932a and a4923a );
a854a <=( a4916a and a4907a );
a855a <=( a4900a and a4891a );
a856a <=( a4884a and a4875a );
a857a <=( a4868a and a4859a );
a858a <=( a4852a and a4843a );
a859a <=( a4836a and a4827a );
a860a <=( a4820a and a4811a );
a861a <=( a4804a and a4795a );
a862a <=( a4788a and a4779a );
a863a <=( a4772a and a4763a );
a864a <=( a4756a and a4747a );
a865a <=( a4740a and a4731a );
a866a <=( a4724a and a4715a );
a867a <=( a4708a and a4699a );
a868a <=( a4692a and a4683a );
a869a <=( a4676a and a4667a );
a870a <=( a4660a and a4651a );
a871a <=( a4644a and a4635a );
a872a <=( a4628a and a4619a );
a873a <=( a4612a and a4603a );
a874a <=( a4596a and a4587a );
a875a <=( a4580a and a4571a );
a876a <=( a4564a and a4555a );
a877a <=( a4548a and a4539a );
a878a <=( a4532a and a4523a );
a879a <=( a4516a and a4507a );
a880a <=( a4500a and a4491a );
a881a <=( a4484a and a4475a );
a882a <=( a4468a and a4459a );
a883a <=( a4452a and a4443a );
a884a <=( a4436a and a4427a );
a885a <=( a4420a and a4411a );
a886a <=( a4404a and a4395a );
a887a <=( a4388a and a4379a );
a888a <=( a4372a and a4363a );
a889a <=( a4356a and a4347a );
a890a <=( a4340a and a4331a );
a891a <=( a4324a and a4315a );
a892a <=( a4308a and a4299a );
a893a <=( a4292a and a4283a );
a894a <=( a4276a and a4267a );
a895a <=( a4260a and a4251a );
a896a <=( a4244a and a4237a );
a897a <=( a4230a and a4223a );
a898a <=( a4216a and a4209a );
a899a <=( a4202a and a4195a );
a900a <=( a4188a and a4181a );
a901a <=( a4174a and a4167a );
a902a <=( a4160a and a4153a );
a903a <=( a4146a and a4139a );
a904a <=( a4132a and a4125a );
a905a <=( a4118a and a4111a );
a906a <=( a4104a and a4097a );
a907a <=( a4090a and a4083a );
a908a <=( a4076a and a4069a );
a909a <=( a4062a and a4055a );
a910a <=( a4048a and a4041a );
a911a <=( a4034a and a4027a );
a912a <=( a4020a and a4013a );
a913a <=( a4006a and a3999a );
a914a <=( a3992a and a3985a );
a915a <=( a3978a and a3971a );
a916a <=( a3964a and a3957a );
a917a <=( a3950a and a3943a );
a918a <=( a3936a and a3929a );
a919a <=( a3922a and a3915a );
a920a <=( a3908a and a3901a );
a921a <=( a3894a and a3887a );
a922a <=( a3880a and a3873a );
a923a <=( a3866a and a3859a );
a924a <=( a3852a and a3845a );
a925a <=( a3838a and a3831a );
a926a <=( a3824a and a3817a );
a927a <=( a3810a and a3803a );
a928a <=( a3796a and a3789a );
a929a <=( a3782a and a3775a );
a930a <=( a3768a and a3761a );
a931a <=( a3754a and a3747a );
a932a <=( a3740a and a3733a );
a933a <=( a3726a and a3719a );
a934a <=( a3712a and a3705a );
a935a <=( a3698a and a3691a );
a936a <=( a3684a and a3677a );
a937a <=( a3670a and a3663a );
a938a <=( a3656a and a3649a );
a939a <=( a3642a and a3635a );
a940a <=( a3628a and a3621a );
a941a <=( a3614a and a3607a );
a942a <=( a3600a and a3593a );
a943a <=( a3586a and a3579a );
a944a <=( a3572a and a3565a );
a945a <=( a3558a and a3551a );
a946a <=( a3544a and a3537a );
a947a <=( a3532a and a3525a );
a948a <=( a3520a and a3513a );
a949a <=( a3508a and a3501a );
a950a <=( a3496a and a3489a );
a951a <=( a3484a and a3477a );
a952a <=( a3472a and a3465a );
a953a <=( a3460a and a3453a );
a954a <=( a3448a and a3441a );
a955a <=( a3436a and a3429a );
a956a <=( a3424a and a3417a );
a957a <=( a3412a and a3405a );
a958a <=( a3400a and a3393a );
a959a <=( a3388a and a3383a );
a960a <=( a3378a and a3373a );
a961a <=( a3368a and a3363a );
a962a <=( a3358a and a3353a );
a963a <=( a3348a and a3343a );
a964a <=( a3338a and a3333a );
a965a <=( a3328a and a3323a );
a966a <=( a3318a and a3313a );
a967a <=( a3308a and a3303a );
a968a <=( a3298a and a3293a );
a969a <=( a3288a and a3283a );
a970a <=( a3280a and a3275a );
a971a <=( a3272a and a3267a );
a972a <=( a3264a and a3259a );
a973a <=( a3256a and a3251a );
a974a <=( a3248a and a3243a );
a975a <=( a3240a and a3235a );
a976a <=( a3232a and a3227a );
a977a <=( a3224a and a3219a );
a978a <=( a3216a and a3211a );
a979a <=( a3208a and a3203a );
a980a <=( a3200a and a3195a );
a981a <=( a3192a and a3187a );
a982a <=( a3184a and a3179a );
a983a <=( a3176a and a3171a );
a984a <=( a3168a and a3163a );
a985a <=( a3160a and a3157a );
a986a <=( a3154a and a3151a );
a987a <=( a3148a and a3145a );
a988a <=( a3142a and a3139a );
a989a <=( a3136a and a3133a );
a990a <=( a3130a and a3127a );
a991a <=( a3124a and a3121a );
a992a <=( a3118a and a3115a );
a993a <=( a3112a and a3109a );
a994a <=( a3106a and a3103a );
a995a <=( a3100a and a3097a );
a996a <=( a3094a and a3091a );
a997a <=( a3088a and a3085a );
a998a <=( a3082a and a3079a );
a999a <=( a3076a and a3073a );
a1000a <=( a3070a and a3067a );
a1001a <=( A169 and a3064a );
a1002a <=( A169 and a3060a );
a1003a <=( A168 and a3056a );
a1004a <=( A168 and a3052a );
a1005a <=( A200 and a3048a );
a1006a <=( A199 and a3044a );
a1007a <=( A202 and a3040a );
a1008a <=( A202 and a3036a );
a1009a <=( A235 and A169 );
a1010a <=( A235 and A202 );
a1014a <=( a1008a ) or ( a1009a );
a1015a <=( a1010a ) or ( a1014a );
a1018a <=( a1006a ) or ( a1007a );
a1021a <=( a1004a ) or ( a1005a );
a1022a <=( a1021a ) or ( a1018a );
a1023a <=( a1022a ) or ( a1015a );
a1026a <=( a1002a ) or ( a1003a );
a1029a <=( a1000a ) or ( a1001a );
a1030a <=( a1029a ) or ( a1026a );
a1033a <=( a998a ) or ( a999a );
a1036a <=( a996a ) or ( a997a );
a1037a <=( a1036a ) or ( a1033a );
a1038a <=( a1037a ) or ( a1030a );
a1039a <=( a1038a ) or ( a1023a );
a1042a <=( a994a ) or ( a995a );
a1045a <=( a992a ) or ( a993a );
a1046a <=( a1045a ) or ( a1042a );
a1049a <=( a990a ) or ( a991a );
a1052a <=( a988a ) or ( a989a );
a1053a <=( a1052a ) or ( a1049a );
a1054a <=( a1053a ) or ( a1046a );
a1057a <=( a986a ) or ( a987a );
a1060a <=( a984a ) or ( a985a );
a1061a <=( a1060a ) or ( a1057a );
a1064a <=( a982a ) or ( a983a );
a1067a <=( a980a ) or ( a981a );
a1068a <=( a1067a ) or ( a1064a );
a1069a <=( a1068a ) or ( a1061a );
a1070a <=( a1069a ) or ( a1054a );
a1071a <=( a1070a ) or ( a1039a );
a1074a <=( a978a ) or ( a979a );
a1077a <=( a976a ) or ( a977a );
a1078a <=( a1077a ) or ( a1074a );
a1081a <=( a974a ) or ( a975a );
a1084a <=( a972a ) or ( a973a );
a1085a <=( a1084a ) or ( a1081a );
a1086a <=( a1085a ) or ( a1078a );
a1089a <=( a970a ) or ( a971a );
a1092a <=( a968a ) or ( a969a );
a1093a <=( a1092a ) or ( a1089a );
a1096a <=( a966a ) or ( a967a );
a1099a <=( a964a ) or ( a965a );
a1100a <=( a1099a ) or ( a1096a );
a1101a <=( a1100a ) or ( a1093a );
a1102a <=( a1101a ) or ( a1086a );
a1105a <=( a962a ) or ( a963a );
a1108a <=( a960a ) or ( a961a );
a1109a <=( a1108a ) or ( a1105a );
a1112a <=( a958a ) or ( a959a );
a1115a <=( a956a ) or ( a957a );
a1116a <=( a1115a ) or ( a1112a );
a1117a <=( a1116a ) or ( a1109a );
a1120a <=( a954a ) or ( a955a );
a1123a <=( a952a ) or ( a953a );
a1124a <=( a1123a ) or ( a1120a );
a1127a <=( a950a ) or ( a951a );
a1130a <=( a948a ) or ( a949a );
a1131a <=( a1130a ) or ( a1127a );
a1132a <=( a1131a ) or ( a1124a );
a1133a <=( a1132a ) or ( a1117a );
a1134a <=( a1133a ) or ( a1102a );
a1135a <=( a1134a ) or ( a1071a );
a1139a <=( a945a ) or ( a946a );
a1140a <=( a947a ) or ( a1139a );
a1143a <=( a943a ) or ( a944a );
a1146a <=( a941a ) or ( a942a );
a1147a <=( a1146a ) or ( a1143a );
a1148a <=( a1147a ) or ( a1140a );
a1151a <=( a939a ) or ( a940a );
a1154a <=( a937a ) or ( a938a );
a1155a <=( a1154a ) or ( a1151a );
a1158a <=( a935a ) or ( a936a );
a1161a <=( a933a ) or ( a934a );
a1162a <=( a1161a ) or ( a1158a );
a1163a <=( a1162a ) or ( a1155a );
a1164a <=( a1163a ) or ( a1148a );
a1167a <=( a931a ) or ( a932a );
a1170a <=( a929a ) or ( a930a );
a1171a <=( a1170a ) or ( a1167a );
a1174a <=( a927a ) or ( a928a );
a1177a <=( a925a ) or ( a926a );
a1178a <=( a1177a ) or ( a1174a );
a1179a <=( a1178a ) or ( a1171a );
a1182a <=( a923a ) or ( a924a );
a1185a <=( a921a ) or ( a922a );
a1186a <=( a1185a ) or ( a1182a );
a1189a <=( a919a ) or ( a920a );
a1192a <=( a917a ) or ( a918a );
a1193a <=( a1192a ) or ( a1189a );
a1194a <=( a1193a ) or ( a1186a );
a1195a <=( a1194a ) or ( a1179a );
a1196a <=( a1195a ) or ( a1164a );
a1199a <=( a915a ) or ( a916a );
a1202a <=( a913a ) or ( a914a );
a1203a <=( a1202a ) or ( a1199a );
a1206a <=( a911a ) or ( a912a );
a1209a <=( a909a ) or ( a910a );
a1210a <=( a1209a ) or ( a1206a );
a1211a <=( a1210a ) or ( a1203a );
a1214a <=( a907a ) or ( a908a );
a1217a <=( a905a ) or ( a906a );
a1218a <=( a1217a ) or ( a1214a );
a1221a <=( a903a ) or ( a904a );
a1224a <=( a901a ) or ( a902a );
a1225a <=( a1224a ) or ( a1221a );
a1226a <=( a1225a ) or ( a1218a );
a1227a <=( a1226a ) or ( a1211a );
a1230a <=( a899a ) or ( a900a );
a1233a <=( a897a ) or ( a898a );
a1234a <=( a1233a ) or ( a1230a );
a1237a <=( a895a ) or ( a896a );
a1240a <=( a893a ) or ( a894a );
a1241a <=( a1240a ) or ( a1237a );
a1242a <=( a1241a ) or ( a1234a );
a1245a <=( a891a ) or ( a892a );
a1248a <=( a889a ) or ( a890a );
a1249a <=( a1248a ) or ( a1245a );
a1252a <=( a887a ) or ( a888a );
a1255a <=( a885a ) or ( a886a );
a1256a <=( a1255a ) or ( a1252a );
a1257a <=( a1256a ) or ( a1249a );
a1258a <=( a1257a ) or ( a1242a );
a1259a <=( a1258a ) or ( a1227a );
a1260a <=( a1259a ) or ( a1196a );
a1261a <=( a1260a ) or ( a1135a );
a1265a <=( a882a ) or ( a883a );
a1266a <=( a884a ) or ( a1265a );
a1269a <=( a880a ) or ( a881a );
a1272a <=( a878a ) or ( a879a );
a1273a <=( a1272a ) or ( a1269a );
a1274a <=( a1273a ) or ( a1266a );
a1277a <=( a876a ) or ( a877a );
a1280a <=( a874a ) or ( a875a );
a1281a <=( a1280a ) or ( a1277a );
a1284a <=( a872a ) or ( a873a );
a1287a <=( a870a ) or ( a871a );
a1288a <=( a1287a ) or ( a1284a );
a1289a <=( a1288a ) or ( a1281a );
a1290a <=( a1289a ) or ( a1274a );
a1293a <=( a868a ) or ( a869a );
a1296a <=( a866a ) or ( a867a );
a1297a <=( a1296a ) or ( a1293a );
a1300a <=( a864a ) or ( a865a );
a1303a <=( a862a ) or ( a863a );
a1304a <=( a1303a ) or ( a1300a );
a1305a <=( a1304a ) or ( a1297a );
a1308a <=( a860a ) or ( a861a );
a1311a <=( a858a ) or ( a859a );
a1312a <=( a1311a ) or ( a1308a );
a1315a <=( a856a ) or ( a857a );
a1318a <=( a854a ) or ( a855a );
a1319a <=( a1318a ) or ( a1315a );
a1320a <=( a1319a ) or ( a1312a );
a1321a <=( a1320a ) or ( a1305a );
a1322a <=( a1321a ) or ( a1290a );
a1325a <=( a852a ) or ( a853a );
a1328a <=( a850a ) or ( a851a );
a1329a <=( a1328a ) or ( a1325a );
a1332a <=( a848a ) or ( a849a );
a1335a <=( a846a ) or ( a847a );
a1336a <=( a1335a ) or ( a1332a );
a1337a <=( a1336a ) or ( a1329a );
a1340a <=( a844a ) or ( a845a );
a1343a <=( a842a ) or ( a843a );
a1344a <=( a1343a ) or ( a1340a );
a1347a <=( a840a ) or ( a841a );
a1350a <=( a838a ) or ( a839a );
a1351a <=( a1350a ) or ( a1347a );
a1352a <=( a1351a ) or ( a1344a );
a1353a <=( a1352a ) or ( a1337a );
a1356a <=( a836a ) or ( a837a );
a1359a <=( a834a ) or ( a835a );
a1360a <=( a1359a ) or ( a1356a );
a1363a <=( a832a ) or ( a833a );
a1366a <=( a830a ) or ( a831a );
a1367a <=( a1366a ) or ( a1363a );
a1368a <=( a1367a ) or ( a1360a );
a1371a <=( a828a ) or ( a829a );
a1374a <=( a826a ) or ( a827a );
a1375a <=( a1374a ) or ( a1371a );
a1378a <=( a824a ) or ( a825a );
a1381a <=( a822a ) or ( a823a );
a1382a <=( a1381a ) or ( a1378a );
a1383a <=( a1382a ) or ( a1375a );
a1384a <=( a1383a ) or ( a1368a );
a1385a <=( a1384a ) or ( a1353a );
a1386a <=( a1385a ) or ( a1322a );
a1390a <=( a819a ) or ( a820a );
a1391a <=( a821a ) or ( a1390a );
a1394a <=( a817a ) or ( a818a );
a1397a <=( a815a ) or ( a816a );
a1398a <=( a1397a ) or ( a1394a );
a1399a <=( a1398a ) or ( a1391a );
a1402a <=( a813a ) or ( a814a );
a1405a <=( a811a ) or ( a812a );
a1406a <=( a1405a ) or ( a1402a );
a1409a <=( a809a ) or ( a810a );
a1412a <=( a807a ) or ( a808a );
a1413a <=( a1412a ) or ( a1409a );
a1414a <=( a1413a ) or ( a1406a );
a1415a <=( a1414a ) or ( a1399a );
a1418a <=( a805a ) or ( a806a );
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a1422a <=( a1421a ) or ( a1418a );
a1425a <=( a801a ) or ( a802a );
a1428a <=( a799a ) or ( a800a );
a1429a <=( a1428a ) or ( a1425a );
a1430a <=( a1429a ) or ( a1422a );
a1433a <=( a797a ) or ( a798a );
a1436a <=( a795a ) or ( a796a );
a1437a <=( a1436a ) or ( a1433a );
a1440a <=( a793a ) or ( a794a );
a1443a <=( a791a ) or ( a792a );
a1444a <=( a1443a ) or ( a1440a );
a1445a <=( a1444a ) or ( a1437a );
a1446a <=( a1445a ) or ( a1430a );
a1447a <=( a1446a ) or ( a1415a );
a1450a <=( a789a ) or ( a790a );
a1453a <=( a787a ) or ( a788a );
a1454a <=( a1453a ) or ( a1450a );
a1457a <=( a785a ) or ( a786a );
a1460a <=( a783a ) or ( a784a );
a1461a <=( a1460a ) or ( a1457a );
a1462a <=( a1461a ) or ( a1454a );
a1465a <=( a781a ) or ( a782a );
a1468a <=( a779a ) or ( a780a );
a1469a <=( a1468a ) or ( a1465a );
a1472a <=( a777a ) or ( a778a );
a1475a <=( a775a ) or ( a776a );
a1476a <=( a1475a ) or ( a1472a );
a1477a <=( a1476a ) or ( a1469a );
a1478a <=( a1477a ) or ( a1462a );
a1481a <=( a773a ) or ( a774a );
a1484a <=( a771a ) or ( a772a );
a1485a <=( a1484a ) or ( a1481a );
a1488a <=( a769a ) or ( a770a );
a1491a <=( a767a ) or ( a768a );
a1492a <=( a1491a ) or ( a1488a );
a1493a <=( a1492a ) or ( a1485a );
a1496a <=( a765a ) or ( a766a );
a1499a <=( a763a ) or ( a764a );
a1500a <=( a1499a ) or ( a1496a );
a1503a <=( a761a ) or ( a762a );
a1506a <=( a759a ) or ( a760a );
a1507a <=( a1506a ) or ( a1503a );
a1508a <=( a1507a ) or ( a1500a );
a1509a <=( a1508a ) or ( a1493a );
a1510a <=( a1509a ) or ( a1478a );
a1511a <=( a1510a ) or ( a1447a );
a1512a <=( a1511a ) or ( a1386a );
a1513a <=( a1512a ) or ( a1261a );
a1517a <=( a756a ) or ( a757a );
a1518a <=( a758a ) or ( a1517a );
a1521a <=( a754a ) or ( a755a );
a1524a <=( a752a ) or ( a753a );
a1525a <=( a1524a ) or ( a1521a );
a1526a <=( a1525a ) or ( a1518a );
a1529a <=( a750a ) or ( a751a );
a1532a <=( a748a ) or ( a749a );
a1533a <=( a1532a ) or ( a1529a );
a1536a <=( a746a ) or ( a747a );
a1539a <=( a744a ) or ( a745a );
a1540a <=( a1539a ) or ( a1536a );
a1541a <=( a1540a ) or ( a1533a );
a1542a <=( a1541a ) or ( a1526a );
a1545a <=( a742a ) or ( a743a );
a1548a <=( a740a ) or ( a741a );
a1549a <=( a1548a ) or ( a1545a );
a1552a <=( a738a ) or ( a739a );
a1555a <=( a736a ) or ( a737a );
a1556a <=( a1555a ) or ( a1552a );
a1557a <=( a1556a ) or ( a1549a );
a1560a <=( a734a ) or ( a735a );
a1563a <=( a732a ) or ( a733a );
a1564a <=( a1563a ) or ( a1560a );
a1567a <=( a730a ) or ( a731a );
a1570a <=( a728a ) or ( a729a );
a1571a <=( a1570a ) or ( a1567a );
a1572a <=( a1571a ) or ( a1564a );
a1573a <=( a1572a ) or ( a1557a );
a1574a <=( a1573a ) or ( a1542a );
a1577a <=( a726a ) or ( a727a );
a1580a <=( a724a ) or ( a725a );
a1581a <=( a1580a ) or ( a1577a );
a1584a <=( a722a ) or ( a723a );
a1587a <=( a720a ) or ( a721a );
a1588a <=( a1587a ) or ( a1584a );
a1589a <=( a1588a ) or ( a1581a );
a1592a <=( a718a ) or ( a719a );
a1595a <=( a716a ) or ( a717a );
a1596a <=( a1595a ) or ( a1592a );
a1599a <=( a714a ) or ( a715a );
a1602a <=( a712a ) or ( a713a );
a1603a <=( a1602a ) or ( a1599a );
a1604a <=( a1603a ) or ( a1596a );
a1605a <=( a1604a ) or ( a1589a );
a1608a <=( a710a ) or ( a711a );
a1611a <=( a708a ) or ( a709a );
a1612a <=( a1611a ) or ( a1608a );
a1615a <=( a706a ) or ( a707a );
a1618a <=( a704a ) or ( a705a );
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a1620a <=( a1619a ) or ( a1612a );
a1623a <=( a702a ) or ( a703a );
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a1627a <=( a1626a ) or ( a1623a );
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a1635a <=( a1634a ) or ( a1627a );
a1636a <=( a1635a ) or ( a1620a );
a1637a <=( a1636a ) or ( a1605a );
a1638a <=( a1637a ) or ( a1574a );
a1642a <=( a693a ) or ( a694a );
a1643a <=( a695a ) or ( a1642a );
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a1650a <=( a1649a ) or ( a1646a );
a1651a <=( a1650a ) or ( a1643a );
a1654a <=( a687a ) or ( a688a );
a1657a <=( a685a ) or ( a686a );
a1658a <=( a1657a ) or ( a1654a );
a1661a <=( a683a ) or ( a684a );
a1664a <=( a681a ) or ( a682a );
a1665a <=( a1664a ) or ( a1661a );
a1666a <=( a1665a ) or ( a1658a );
a1667a <=( a1666a ) or ( a1651a );
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a1673a <=( a677a ) or ( a678a );
a1674a <=( a1673a ) or ( a1670a );
a1677a <=( a675a ) or ( a676a );
a1680a <=( a673a ) or ( a674a );
a1681a <=( a1680a ) or ( a1677a );
a1682a <=( a1681a ) or ( a1674a );
a1685a <=( a671a ) or ( a672a );
a1688a <=( a669a ) or ( a670a );
a1689a <=( a1688a ) or ( a1685a );
a1692a <=( a667a ) or ( a668a );
a1695a <=( a665a ) or ( a666a );
a1696a <=( a1695a ) or ( a1692a );
a1697a <=( a1696a ) or ( a1689a );
a1698a <=( a1697a ) or ( a1682a );
a1699a <=( a1698a ) or ( a1667a );
a1702a <=( a663a ) or ( a664a );
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a1717a <=( a655a ) or ( a656a );
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a1730a <=( a1729a ) or ( a1714a );
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a1736a <=( a645a ) or ( a646a );
a1737a <=( a1736a ) or ( a1733a );
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a1744a <=( a1743a ) or ( a1740a );
a1745a <=( a1744a ) or ( a1737a );
a1748a <=( a639a ) or ( a640a );
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a1752a <=( a1751a ) or ( a1748a );
a1755a <=( a635a ) or ( a636a );
a1758a <=( a633a ) or ( a634a );
a1759a <=( a1758a ) or ( a1755a );
a1760a <=( a1759a ) or ( a1752a );
a1761a <=( a1760a ) or ( a1745a );
a1762a <=( a1761a ) or ( a1730a );
a1763a <=( a1762a ) or ( a1699a );
a1764a <=( a1763a ) or ( a1638a );
a1768a <=( a630a ) or ( a631a );
a1769a <=( a632a ) or ( a1768a );
a1772a <=( a628a ) or ( a629a );
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a1776a <=( a1775a ) or ( a1772a );
a1777a <=( a1776a ) or ( a1769a );
a1780a <=( a624a ) or ( a625a );
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a1784a <=( a1783a ) or ( a1780a );
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a1791a <=( a1790a ) or ( a1787a );
a1792a <=( a1791a ) or ( a1784a );
a1793a <=( a1792a ) or ( a1777a );
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a1800a <=( a1799a ) or ( a1796a );
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a1822a <=( a1821a ) or ( a1818a );
a1823a <=( a1822a ) or ( a1815a );
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a1825a <=( a1824a ) or ( a1793a );
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a1832a <=( a1831a ) or ( a1828a );
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a1839a <=( a1838a ) or ( a1835a );
a1840a <=( a1839a ) or ( a1832a );
a1843a <=( a592a ) or ( a593a );
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a1847a <=( a1846a ) or ( a1843a );
a1850a <=( a588a ) or ( a589a );
a1853a <=( a586a ) or ( a587a );
a1854a <=( a1853a ) or ( a1850a );
a1855a <=( a1854a ) or ( a1847a );
a1856a <=( a1855a ) or ( a1840a );
a1859a <=( a584a ) or ( a585a );
a1862a <=( a582a ) or ( a583a );
a1863a <=( a1862a ) or ( a1859a );
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a1870a <=( a1869a ) or ( a1866a );
a1871a <=( a1870a ) or ( a1863a );
a1874a <=( a576a ) or ( a577a );
a1877a <=( a574a ) or ( a575a );
a1878a <=( a1877a ) or ( a1874a );
a1881a <=( a572a ) or ( a573a );
a1884a <=( a570a ) or ( a571a );
a1885a <=( a1884a ) or ( a1881a );
a1886a <=( a1885a ) or ( a1878a );
a1887a <=( a1886a ) or ( a1871a );
a1888a <=( a1887a ) or ( a1856a );
a1889a <=( a1888a ) or ( a1825a );
a1892a <=( a568a ) or ( a569a );
a1895a <=( a566a ) or ( a567a );
a1896a <=( a1895a ) or ( a1892a );
a1899a <=( a564a ) or ( a565a );
a1902a <=( a562a ) or ( a563a );
a1903a <=( a1902a ) or ( a1899a );
a1904a <=( a1903a ) or ( a1896a );
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a1911a <=( a1910a ) or ( a1907a );
a1914a <=( a556a ) or ( a557a );
a1917a <=( a554a ) or ( a555a );
a1918a <=( a1917a ) or ( a1914a );
a1919a <=( a1918a ) or ( a1911a );
a1920a <=( a1919a ) or ( a1904a );
a1923a <=( a552a ) or ( a553a );
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a1930a <=( a548a ) or ( a549a );
a1933a <=( a546a ) or ( a547a );
a1934a <=( a1933a ) or ( a1930a );
a1935a <=( a1934a ) or ( a1927a );
a1938a <=( a544a ) or ( a545a );
a1941a <=( a542a ) or ( a543a );
a1942a <=( a1941a ) or ( a1938a );
a1945a <=( a540a ) or ( a541a );
a1948a <=( a538a ) or ( a539a );
a1949a <=( a1948a ) or ( a1945a );
a1950a <=( a1949a ) or ( a1942a );
a1951a <=( a1950a ) or ( a1935a );
a1952a <=( a1951a ) or ( a1920a );
a1955a <=( a536a ) or ( a537a );
a1958a <=( a534a ) or ( a535a );
a1959a <=( a1958a ) or ( a1955a );
a1962a <=( a532a ) or ( a533a );
a1965a <=( a530a ) or ( a531a );
a1966a <=( a1965a ) or ( a1962a );
a1967a <=( a1966a ) or ( a1959a );
a1970a <=( a528a ) or ( a529a );
a1973a <=( a526a ) or ( a527a );
a1974a <=( a1973a ) or ( a1970a );
a1977a <=( a524a ) or ( a525a );
a1980a <=( a522a ) or ( a523a );
a1981a <=( a1980a ) or ( a1977a );
a1982a <=( a1981a ) or ( a1974a );
a1983a <=( a1982a ) or ( a1967a );
a1986a <=( a520a ) or ( a521a );
a1989a <=( a518a ) or ( a519a );
a1990a <=( a1989a ) or ( a1986a );
a1993a <=( a516a ) or ( a517a );
a1996a <=( a514a ) or ( a515a );
a1997a <=( a1996a ) or ( a1993a );
a1998a <=( a1997a ) or ( a1990a );
a2001a <=( a512a ) or ( a513a );
a2004a <=( a510a ) or ( a511a );
a2005a <=( a2004a ) or ( a2001a );
a2008a <=( a508a ) or ( a509a );
a2011a <=( a506a ) or ( a507a );
a2012a <=( a2011a ) or ( a2008a );
a2013a <=( a2012a ) or ( a2005a );
a2014a <=( a2013a ) or ( a1998a );
a2015a <=( a2014a ) or ( a1983a );
a2016a <=( a2015a ) or ( a1952a );
a2017a <=( a2016a ) or ( a1889a );
a2018a <=( a2017a ) or ( a1764a );
a2019a <=( a2018a ) or ( a1513a );
a2023a <=( a503a ) or ( a504a );
a2024a <=( a505a ) or ( a2023a );
a2027a <=( a501a ) or ( a502a );
a2030a <=( a499a ) or ( a500a );
a2031a <=( a2030a ) or ( a2027a );
a2032a <=( a2031a ) or ( a2024a );
a2035a <=( a497a ) or ( a498a );
a2038a <=( a495a ) or ( a496a );
a2039a <=( a2038a ) or ( a2035a );
a2042a <=( a493a ) or ( a494a );
a2045a <=( a491a ) or ( a492a );
a2046a <=( a2045a ) or ( a2042a );
a2047a <=( a2046a ) or ( a2039a );
a2048a <=( a2047a ) or ( a2032a );
a2051a <=( a489a ) or ( a490a );
a2054a <=( a487a ) or ( a488a );
a2055a <=( a2054a ) or ( a2051a );
a2058a <=( a485a ) or ( a486a );
a2061a <=( a483a ) or ( a484a );
a2062a <=( a2061a ) or ( a2058a );
a2063a <=( a2062a ) or ( a2055a );
a2066a <=( a481a ) or ( a482a );
a2069a <=( a479a ) or ( a480a );
a2070a <=( a2069a ) or ( a2066a );
a2073a <=( a477a ) or ( a478a );
a2076a <=( a475a ) or ( a476a );
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a2935a <=( a45a ) or ( a46a );
a2936a <=( a2935a ) or ( a2932a );
a2939a <=( a43a ) or ( a44a );
a2942a <=( a41a ) or ( a42a );
a2943a <=( a2942a ) or ( a2939a );
a2944a <=( a2943a ) or ( a2936a );
a2947a <=( a39a ) or ( a40a );
a2950a <=( a37a ) or ( a38a );
a2951a <=( a2950a ) or ( a2947a );
a2954a <=( a35a ) or ( a36a );
a2957a <=( a33a ) or ( a34a );
a2958a <=( a2957a ) or ( a2954a );
a2959a <=( a2958a ) or ( a2951a );
a2960a <=( a2959a ) or ( a2944a );
a2961a <=( a2960a ) or ( a2929a );
a2964a <=( a31a ) or ( a32a );
a2967a <=( a29a ) or ( a30a );
a2968a <=( a2967a ) or ( a2964a );
a2971a <=( a27a ) or ( a28a );
a2974a <=( a25a ) or ( a26a );
a2975a <=( a2974a ) or ( a2971a );
a2976a <=( a2975a ) or ( a2968a );
a2979a <=( a23a ) or ( a24a );
a2982a <=( a21a ) or ( a22a );
a2983a <=( a2982a ) or ( a2979a );
a2986a <=( a19a ) or ( a20a );
a2989a <=( a17a ) or ( a18a );
a2990a <=( a2989a ) or ( a2986a );
a2991a <=( a2990a ) or ( a2983a );
a2992a <=( a2991a ) or ( a2976a );
a2995a <=( a15a ) or ( a16a );
a2998a <=( a13a ) or ( a14a );
a2999a <=( a2998a ) or ( a2995a );
a3002a <=( a11a ) or ( a12a );
a3005a <=( a9a ) or ( a10a );
a3006a <=( a3005a ) or ( a3002a );
a3007a <=( a3006a ) or ( a2999a );
a3010a <=( a7a ) or ( a8a );
a3013a <=( a5a ) or ( a6a );
a3014a <=( a3013a ) or ( a3010a );
a3017a <=( a3a ) or ( a4a );
a3020a <=( a1a ) or ( a2a );
a3021a <=( a3020a ) or ( a3017a );
a3022a <=( a3021a ) or ( a3014a );
a3023a <=( a3022a ) or ( a3007a );
a3024a <=( a3023a ) or ( a2992a );
a3025a <=( a3024a ) or ( a2961a );
a3026a <=( a3025a ) or ( a2898a );
a3027a <=( a3026a ) or ( a2773a );
a3028a <=( a3027a ) or ( a2522a );
a3036a <=( A234 and A232 );
a3040a <=( A234 and A233 );
a3044a <=( A235 and A201 );
a3048a <=( A235 and A201 );
a3052a <=( A235 and A166 );
a3056a <=( A235 and A167 );
a3060a <=( A234 and A232 );
a3064a <=( A234 and A233 );
a3067a <=( (not A232) and A202 );
a3070a <=( A236 and A233 );
a3073a <=( A232 and A202 );
a3076a <=( A236 and (not A233) );
a3079a <=( A201 and A199 );
a3082a <=( A234 and A232 );
a3085a <=( A201 and A199 );
a3088a <=( A234 and A233 );
a3091a <=( A201 and A200 );
a3094a <=( A234 and A232 );
a3097a <=( A201 and A200 );
a3100a <=( A234 and A233 );
a3103a <=( A200 and (not A199) );
a3106a <=( A235 and A203 );
a3109a <=( (not A200) and A199 );
a3112a <=( A235 and A203 );
a3115a <=( A166 and A168 );
a3118a <=( A234 and A232 );
a3121a <=( A166 and A168 );
a3124a <=( A234 and A233 );
a3127a <=( A167 and A168 );
a3130a <=( A234 and A232 );
a3133a <=( A167 and A168 );
a3136a <=( A234 and A233 );
a3139a <=( A167 and A170 );
a3142a <=( A235 and (not A166) );
a3145a <=( (not A167) and A170 );
a3148a <=( A235 and A166 );
a3151a <=( (not A232) and A169 );
a3154a <=( A236 and A233 );
a3157a <=( A232 and A169 );
a3160a <=( A236 and (not A233) );
a3163a <=( A201 and A199 );
a3167a <=( A236 and A233 );
a3168a <=( (not A232) and a3167a );
a3171a <=( A201 and A199 );
a3175a <=( A236 and (not A233) );
a3176a <=( A232 and a3175a );
a3179a <=( A201 and A200 );
a3183a <=( A236 and A233 );
a3184a <=( (not A232) and a3183a );
a3187a <=( A201 and A200 );
a3191a <=( A236 and (not A233) );
a3192a <=( A232 and a3191a );
a3195a <=( A200 and (not A199) );
a3199a <=( A234 and A232 );
a3200a <=( A203 and a3199a );
a3203a <=( A200 and (not A199) );
a3207a <=( A234 and A233 );
a3208a <=( A203 and a3207a );
a3211a <=( (not A200) and A199 );
a3215a <=( A234 and A232 );
a3216a <=( A203 and a3215a );
a3219a <=( (not A200) and A199 );
a3223a <=( A234 and A233 );
a3224a <=( A203 and a3223a );
a3227a <=( A166 and A168 );
a3231a <=( A236 and A233 );
a3232a <=( (not A232) and a3231a );
a3235a <=( A166 and A168 );
a3239a <=( A236 and (not A233) );
a3240a <=( A232 and a3239a );
a3243a <=( A167 and A168 );
a3247a <=( A236 and A233 );
a3248a <=( (not A232) and a3247a );
a3251a <=( A167 and A168 );
a3255a <=( A236 and (not A233) );
a3256a <=( A232 and a3255a );
a3259a <=( A167 and A170 );
a3263a <=( A234 and A232 );
a3264a <=( (not A166) and a3263a );
a3267a <=( A167 and A170 );
a3271a <=( A234 and A233 );
a3272a <=( (not A166) and a3271a );
a3275a <=( (not A167) and A170 );
a3279a <=( A234 and A232 );
a3280a <=( A166 and a3279a );
a3283a <=( (not A167) and A170 );
a3287a <=( A234 and A233 );
a3288a <=( A166 and a3287a );
a3292a <=( A203 and A200 );
a3293a <=( (not A199) and a3292a );
a3297a <=( A236 and A233 );
a3298a <=( (not A232) and a3297a );
a3302a <=( A203 and A200 );
a3303a <=( (not A199) and a3302a );
a3307a <=( A236 and (not A233) );
a3308a <=( A232 and a3307a );
a3312a <=( A203 and (not A200) );
a3313a <=( A199 and a3312a );
a3317a <=( A236 and A233 );
a3318a <=( (not A232) and a3317a );
a3322a <=( A203 and (not A200) );
a3323a <=( A199 and a3322a );
a3327a <=( A236 and (not A233) );
a3328a <=( A232 and a3327a );
a3332a <=( (not A166) and A167 );
a3333a <=( A170 and a3332a );
a3337a <=( A236 and A233 );
a3338a <=( (not A232) and a3337a );
a3342a <=( (not A166) and A167 );
a3343a <=( A170 and a3342a );
a3347a <=( A236 and (not A233) );
a3348a <=( A232 and a3347a );
a3352a <=( A166 and (not A167) );
a3353a <=( A170 and a3352a );
a3357a <=( A236 and A233 );
a3358a <=( (not A232) and a3357a );
a3362a <=( A166 and (not A167) );
a3363a <=( A170 and a3362a );
a3367a <=( A236 and (not A233) );
a3368a <=( A232 and a3367a );
a3372a <=( A268 and A202 );
a3373a <=( A169 and a3372a );
a3377a <=( (not A302) and (not A301) );
a3378a <=( (not A300) and a3377a );
a3382a <=( A268 and A202 );
a3383a <=( A169 and a3382a );
a3387a <=( (not A301) and (not A299) );
a3388a <=( (not A298) and a3387a );
a3392a <=( A202 and A166 );
a3393a <=( A168 and a3392a );
a3396a <=( (not A300) and A268 );
a3399a <=( (not A302) and (not A301) );
a3400a <=( a3399a and a3396a );
a3404a <=( A202 and A166 );
a3405a <=( A168 and a3404a );
a3408a <=( (not A298) and A268 );
a3411a <=( (not A301) and (not A299) );
a3412a <=( a3411a and a3408a );
a3416a <=( A202 and A167 );
a3417a <=( A168 and a3416a );
a3420a <=( (not A300) and A268 );
a3423a <=( (not A302) and (not A301) );
a3424a <=( a3423a and a3420a );
a3428a <=( A202 and A167 );
a3429a <=( A168 and a3428a );
a3432a <=( (not A298) and A268 );
a3435a <=( (not A301) and (not A299) );
a3436a <=( a3435a and a3432a );
a3440a <=( A268 and A202 );
a3441a <=( A169 and a3440a );
a3444a <=( A299 and A298 );
a3447a <=( (not A301) and (not A300) );
a3448a <=( a3447a and a3444a );
a3452a <=( A265 and A202 );
a3453a <=( A169 and a3452a );
a3456a <=( (not A300) and A267 );
a3459a <=( (not A302) and (not A301) );
a3460a <=( a3459a and a3456a );
a3464a <=( A265 and A202 );
a3465a <=( A169 and a3464a );
a3468a <=( (not A298) and A267 );
a3471a <=( (not A301) and (not A299) );
a3472a <=( a3471a and a3468a );
a3476a <=( A266 and A202 );
a3477a <=( A169 and a3476a );
a3480a <=( (not A300) and A267 );
a3483a <=( (not A302) and (not A301) );
a3484a <=( a3483a and a3480a );
a3488a <=( A266 and A202 );
a3489a <=( A169 and a3488a );
a3492a <=( (not A298) and A267 );
a3495a <=( (not A301) and (not A299) );
a3496a <=( a3495a and a3492a );
a3500a <=( A201 and A199 );
a3501a <=( A169 and a3500a );
a3504a <=( (not A300) and A268 );
a3507a <=( (not A302) and (not A301) );
a3508a <=( a3507a and a3504a );
a3512a <=( A201 and A199 );
a3513a <=( A169 and a3512a );
a3516a <=( (not A298) and A268 );
a3519a <=( (not A301) and (not A299) );
a3520a <=( a3519a and a3516a );
a3524a <=( A201 and A200 );
a3525a <=( A169 and a3524a );
a3528a <=( (not A300) and A268 );
a3531a <=( (not A302) and (not A301) );
a3532a <=( a3531a and a3528a );
a3536a <=( A201 and A200 );
a3537a <=( A169 and a3536a );
a3540a <=( (not A298) and A268 );
a3543a <=( (not A301) and (not A299) );
a3544a <=( a3543a and a3540a );
a3547a <=( A166 and A168 );
a3550a <=( A268 and A202 );
a3551a <=( a3550a and a3547a );
a3554a <=( A299 and A298 );
a3557a <=( (not A301) and (not A300) );
a3558a <=( a3557a and a3554a );
a3561a <=( A166 and A168 );
a3564a <=( A265 and A202 );
a3565a <=( a3564a and a3561a );
a3568a <=( (not A300) and A267 );
a3571a <=( (not A302) and (not A301) );
a3572a <=( a3571a and a3568a );
a3575a <=( A166 and A168 );
a3578a <=( A265 and A202 );
a3579a <=( a3578a and a3575a );
a3582a <=( (not A298) and A267 );
a3585a <=( (not A301) and (not A299) );
a3586a <=( a3585a and a3582a );
a3589a <=( A166 and A168 );
a3592a <=( A266 and A202 );
a3593a <=( a3592a and a3589a );
a3596a <=( (not A300) and A267 );
a3599a <=( (not A302) and (not A301) );
a3600a <=( a3599a and a3596a );
a3603a <=( A166 and A168 );
a3606a <=( A266 and A202 );
a3607a <=( a3606a and a3603a );
a3610a <=( (not A298) and A267 );
a3613a <=( (not A301) and (not A299) );
a3614a <=( a3613a and a3610a );
a3617a <=( A166 and A168 );
a3620a <=( A201 and A199 );
a3621a <=( a3620a and a3617a );
a3624a <=( (not A300) and A268 );
a3627a <=( (not A302) and (not A301) );
a3628a <=( a3627a and a3624a );
a3631a <=( A166 and A168 );
a3634a <=( A201 and A199 );
a3635a <=( a3634a and a3631a );
a3638a <=( (not A298) and A268 );
a3641a <=( (not A301) and (not A299) );
a3642a <=( a3641a and a3638a );
a3645a <=( A166 and A168 );
a3648a <=( A201 and A200 );
a3649a <=( a3648a and a3645a );
a3652a <=( (not A300) and A268 );
a3655a <=( (not A302) and (not A301) );
a3656a <=( a3655a and a3652a );
a3659a <=( A166 and A168 );
a3662a <=( A201 and A200 );
a3663a <=( a3662a and a3659a );
a3666a <=( (not A298) and A268 );
a3669a <=( (not A301) and (not A299) );
a3670a <=( a3669a and a3666a );
a3673a <=( A167 and A168 );
a3676a <=( A268 and A202 );
a3677a <=( a3676a and a3673a );
a3680a <=( A299 and A298 );
a3683a <=( (not A301) and (not A300) );
a3684a <=( a3683a and a3680a );
a3687a <=( A167 and A168 );
a3690a <=( A265 and A202 );
a3691a <=( a3690a and a3687a );
a3694a <=( (not A300) and A267 );
a3697a <=( (not A302) and (not A301) );
a3698a <=( a3697a and a3694a );
a3701a <=( A167 and A168 );
a3704a <=( A265 and A202 );
a3705a <=( a3704a and a3701a );
a3708a <=( (not A298) and A267 );
a3711a <=( (not A301) and (not A299) );
a3712a <=( a3711a and a3708a );
a3715a <=( A167 and A168 );
a3718a <=( A266 and A202 );
a3719a <=( a3718a and a3715a );
a3722a <=( (not A300) and A267 );
a3725a <=( (not A302) and (not A301) );
a3726a <=( a3725a and a3722a );
a3729a <=( A167 and A168 );
a3732a <=( A266 and A202 );
a3733a <=( a3732a and a3729a );
a3736a <=( (not A298) and A267 );
a3739a <=( (not A301) and (not A299) );
a3740a <=( a3739a and a3736a );
a3743a <=( A167 and A168 );
a3746a <=( A201 and A199 );
a3747a <=( a3746a and a3743a );
a3750a <=( (not A300) and A268 );
a3753a <=( (not A302) and (not A301) );
a3754a <=( a3753a and a3750a );
a3757a <=( A167 and A168 );
a3760a <=( A201 and A199 );
a3761a <=( a3760a and a3757a );
a3764a <=( (not A298) and A268 );
a3767a <=( (not A301) and (not A299) );
a3768a <=( a3767a and a3764a );
a3771a <=( A167 and A168 );
a3774a <=( A201 and A200 );
a3775a <=( a3774a and a3771a );
a3778a <=( (not A300) and A268 );
a3781a <=( (not A302) and (not A301) );
a3782a <=( a3781a and a3778a );
a3785a <=( A167 and A168 );
a3788a <=( A201 and A200 );
a3789a <=( a3788a and a3785a );
a3792a <=( (not A298) and A268 );
a3795a <=( (not A301) and (not A299) );
a3796a <=( a3795a and a3792a );
a3799a <=( A167 and A170 );
a3802a <=( A202 and (not A166) );
a3803a <=( a3802a and a3799a );
a3806a <=( (not A300) and A268 );
a3809a <=( (not A302) and (not A301) );
a3810a <=( a3809a and a3806a );
a3813a <=( A167 and A170 );
a3816a <=( A202 and (not A166) );
a3817a <=( a3816a and a3813a );
a3820a <=( (not A298) and A268 );
a3823a <=( (not A301) and (not A299) );
a3824a <=( a3823a and a3820a );
a3827a <=( (not A167) and A170 );
a3830a <=( A202 and A166 );
a3831a <=( a3830a and a3827a );
a3834a <=( (not A300) and A268 );
a3837a <=( (not A302) and (not A301) );
a3838a <=( a3837a and a3834a );
a3841a <=( (not A167) and A170 );
a3844a <=( A202 and A166 );
a3845a <=( a3844a and a3841a );
a3848a <=( (not A298) and A268 );
a3851a <=( (not A301) and (not A299) );
a3852a <=( a3851a and a3848a );
a3855a <=( A202 and A169 );
a3858a <=( A267 and A265 );
a3859a <=( a3858a and a3855a );
a3862a <=( A299 and A298 );
a3865a <=( (not A301) and (not A300) );
a3866a <=( a3865a and a3862a );
a3869a <=( A202 and A169 );
a3872a <=( A267 and A266 );
a3873a <=( a3872a and a3869a );
a3876a <=( A299 and A298 );
a3879a <=( (not A301) and (not A300) );
a3880a <=( a3879a and a3876a );
a3883a <=( A202 and A169 );
a3886a <=( A266 and (not A265) );
a3887a <=( a3886a and a3883a );
a3890a <=( (not A300) and A269 );
a3893a <=( (not A302) and (not A301) );
a3894a <=( a3893a and a3890a );
a3897a <=( A202 and A169 );
a3900a <=( A266 and (not A265) );
a3901a <=( a3900a and a3897a );
a3904a <=( (not A298) and A269 );
a3907a <=( (not A301) and (not A299) );
a3908a <=( a3907a and a3904a );
a3911a <=( A202 and A169 );
a3914a <=( (not A266) and A265 );
a3915a <=( a3914a and a3911a );
a3918a <=( (not A300) and A269 );
a3921a <=( (not A302) and (not A301) );
a3922a <=( a3921a and a3918a );
a3925a <=( A202 and A169 );
a3928a <=( (not A266) and A265 );
a3929a <=( a3928a and a3925a );
a3932a <=( (not A298) and A269 );
a3935a <=( (not A301) and (not A299) );
a3936a <=( a3935a and a3932a );
a3939a <=( (not A201) and A169 );
a3942a <=( (not A203) and (not A202) );
a3943a <=( a3942a and a3939a );
a3946a <=( (not A268) and (not A267) );
a3949a <=( A301 and (not A269) );
a3950a <=( a3949a and a3946a );
a3953a <=( (not A201) and A169 );
a3956a <=( (not A203) and (not A202) );
a3957a <=( a3956a and a3953a );
a3960a <=( (not A266) and (not A265) );
a3963a <=( A301 and (not A268) );
a3964a <=( a3963a and a3960a );
a3967a <=( A199 and A169 );
a3970a <=( A268 and A201 );
a3971a <=( a3970a and a3967a );
a3974a <=( A299 and A298 );
a3977a <=( (not A301) and (not A300) );
a3978a <=( a3977a and a3974a );
a3981a <=( A199 and A169 );
a3984a <=( A265 and A201 );
a3985a <=( a3984a and a3981a );
a3988a <=( (not A300) and A267 );
a3991a <=( (not A302) and (not A301) );
a3992a <=( a3991a and a3988a );
a3995a <=( A199 and A169 );
a3998a <=( A265 and A201 );
a3999a <=( a3998a and a3995a );
a4002a <=( (not A298) and A267 );
a4005a <=( (not A301) and (not A299) );
a4006a <=( a4005a and a4002a );
a4009a <=( A199 and A169 );
a4012a <=( A266 and A201 );
a4013a <=( a4012a and a4009a );
a4016a <=( (not A300) and A267 );
a4019a <=( (not A302) and (not A301) );
a4020a <=( a4019a and a4016a );
a4023a <=( A199 and A169 );
a4026a <=( A266 and A201 );
a4027a <=( a4026a and a4023a );
a4030a <=( (not A298) and A267 );
a4033a <=( (not A301) and (not A299) );
a4034a <=( a4033a and a4030a );
a4037a <=( A200 and A169 );
a4040a <=( A268 and A201 );
a4041a <=( a4040a and a4037a );
a4044a <=( A299 and A298 );
a4047a <=( (not A301) and (not A300) );
a4048a <=( a4047a and a4044a );
a4051a <=( A200 and A169 );
a4054a <=( A265 and A201 );
a4055a <=( a4054a and a4051a );
a4058a <=( (not A300) and A267 );
a4061a <=( (not A302) and (not A301) );
a4062a <=( a4061a and a4058a );
a4065a <=( A200 and A169 );
a4068a <=( A265 and A201 );
a4069a <=( a4068a and a4065a );
a4072a <=( (not A298) and A267 );
a4075a <=( (not A301) and (not A299) );
a4076a <=( a4075a and a4072a );
a4079a <=( A200 and A169 );
a4082a <=( A266 and A201 );
a4083a <=( a4082a and a4079a );
a4086a <=( (not A300) and A267 );
a4089a <=( (not A302) and (not A301) );
a4090a <=( a4089a and a4086a );
a4093a <=( A200 and A169 );
a4096a <=( A266 and A201 );
a4097a <=( a4096a and a4093a );
a4100a <=( (not A298) and A267 );
a4103a <=( (not A301) and (not A299) );
a4104a <=( a4103a and a4100a );
a4107a <=( (not A199) and A169 );
a4110a <=( A203 and A200 );
a4111a <=( a4110a and a4107a );
a4114a <=( (not A300) and A268 );
a4117a <=( (not A302) and (not A301) );
a4118a <=( a4117a and a4114a );
a4121a <=( (not A199) and A169 );
a4124a <=( A203 and A200 );
a4125a <=( a4124a and a4121a );
a4128a <=( (not A298) and A268 );
a4131a <=( (not A301) and (not A299) );
a4132a <=( a4131a and a4128a );
a4135a <=( A199 and A169 );
a4138a <=( A203 and (not A200) );
a4139a <=( a4138a and a4135a );
a4142a <=( (not A300) and A268 );
a4145a <=( (not A302) and (not A301) );
a4146a <=( a4145a and a4142a );
a4149a <=( A199 and A169 );
a4152a <=( A203 and (not A200) );
a4153a <=( a4152a and a4149a );
a4156a <=( (not A298) and A268 );
a4159a <=( (not A301) and (not A299) );
a4160a <=( a4159a and a4156a );
a4163a <=( (not A199) and A169 );
a4166a <=( (not A202) and (not A200) );
a4167a <=( a4166a and a4163a );
a4170a <=( (not A268) and (not A267) );
a4173a <=( A301 and (not A269) );
a4174a <=( a4173a and a4170a );
a4177a <=( (not A199) and A169 );
a4180a <=( (not A202) and (not A200) );
a4181a <=( a4180a and a4177a );
a4184a <=( (not A266) and (not A265) );
a4187a <=( A301 and (not A268) );
a4188a <=( a4187a and a4184a );
a4191a <=( (not A167) and (not A169) );
a4194a <=( A202 and (not A166) );
a4195a <=( a4194a and a4191a );
a4198a <=( (not A268) and (not A267) );
a4201a <=( A301 and (not A269) );
a4202a <=( a4201a and a4198a );
a4205a <=( (not A167) and (not A169) );
a4208a <=( A202 and (not A166) );
a4209a <=( a4208a and a4205a );
a4212a <=( (not A266) and (not A265) );
a4215a <=( A301 and (not A268) );
a4216a <=( a4215a and a4212a );
a4219a <=( (not A169) and (not A170) );
a4222a <=( A202 and (not A168) );
a4223a <=( a4222a and a4219a );
a4226a <=( (not A268) and (not A267) );
a4229a <=( A301 and (not A269) );
a4230a <=( a4229a and a4226a );
a4233a <=( (not A169) and (not A170) );
a4236a <=( A202 and (not A168) );
a4237a <=( a4236a and a4233a );
a4240a <=( (not A266) and (not A265) );
a4243a <=( A301 and (not A268) );
a4244a <=( a4243a and a4240a );
a4247a <=( A166 and A168 );
a4250a <=( A265 and A202 );
a4251a <=( a4250a and a4247a );
a4254a <=( A298 and A267 );
a4258a <=( (not A301) and (not A300) );
a4259a <=( A299 and a4258a );
a4260a <=( a4259a and a4254a );
a4263a <=( A166 and A168 );
a4266a <=( A266 and A202 );
a4267a <=( a4266a and a4263a );
a4270a <=( A298 and A267 );
a4274a <=( (not A301) and (not A300) );
a4275a <=( A299 and a4274a );
a4276a <=( a4275a and a4270a );
a4279a <=( A166 and A168 );
a4282a <=( (not A265) and A202 );
a4283a <=( a4282a and a4279a );
a4286a <=( A269 and A266 );
a4290a <=( (not A302) and (not A301) );
a4291a <=( (not A300) and a4290a );
a4292a <=( a4291a and a4286a );
a4295a <=( A166 and A168 );
a4298a <=( (not A265) and A202 );
a4299a <=( a4298a and a4295a );
a4302a <=( A269 and A266 );
a4306a <=( (not A301) and (not A299) );
a4307a <=( (not A298) and a4306a );
a4308a <=( a4307a and a4302a );
a4311a <=( A166 and A168 );
a4314a <=( A265 and A202 );
a4315a <=( a4314a and a4311a );
a4318a <=( A269 and (not A266) );
a4322a <=( (not A302) and (not A301) );
a4323a <=( (not A300) and a4322a );
a4324a <=( a4323a and a4318a );
a4327a <=( A166 and A168 );
a4330a <=( A265 and A202 );
a4331a <=( a4330a and a4327a );
a4334a <=( A269 and (not A266) );
a4338a <=( (not A301) and (not A299) );
a4339a <=( (not A298) and a4338a );
a4340a <=( a4339a and a4334a );
a4343a <=( A166 and A168 );
a4346a <=( (not A202) and (not A201) );
a4347a <=( a4346a and a4343a );
a4350a <=( (not A267) and (not A203) );
a4354a <=( A301 and (not A269) );
a4355a <=( (not A268) and a4354a );
a4356a <=( a4355a and a4350a );
a4359a <=( A166 and A168 );
a4362a <=( (not A202) and (not A201) );
a4363a <=( a4362a and a4359a );
a4366a <=( (not A265) and (not A203) );
a4370a <=( A301 and (not A268) );
a4371a <=( (not A266) and a4370a );
a4372a <=( a4371a and a4366a );
a4375a <=( A166 and A168 );
a4378a <=( A201 and A199 );
a4379a <=( a4378a and a4375a );
a4382a <=( A298 and A268 );
a4386a <=( (not A301) and (not A300) );
a4387a <=( A299 and a4386a );
a4388a <=( a4387a and a4382a );
a4391a <=( A166 and A168 );
a4394a <=( A201 and A199 );
a4395a <=( a4394a and a4391a );
a4398a <=( A267 and A265 );
a4402a <=( (not A302) and (not A301) );
a4403a <=( (not A300) and a4402a );
a4404a <=( a4403a and a4398a );
a4407a <=( A166 and A168 );
a4410a <=( A201 and A199 );
a4411a <=( a4410a and a4407a );
a4414a <=( A267 and A265 );
a4418a <=( (not A301) and (not A299) );
a4419a <=( (not A298) and a4418a );
a4420a <=( a4419a and a4414a );
a4423a <=( A166 and A168 );
a4426a <=( A201 and A199 );
a4427a <=( a4426a and a4423a );
a4430a <=( A267 and A266 );
a4434a <=( (not A302) and (not A301) );
a4435a <=( (not A300) and a4434a );
a4436a <=( a4435a and a4430a );
a4439a <=( A166 and A168 );
a4442a <=( A201 and A199 );
a4443a <=( a4442a and a4439a );
a4446a <=( A267 and A266 );
a4450a <=( (not A301) and (not A299) );
a4451a <=( (not A298) and a4450a );
a4452a <=( a4451a and a4446a );
a4455a <=( A166 and A168 );
a4458a <=( A201 and A200 );
a4459a <=( a4458a and a4455a );
a4462a <=( A298 and A268 );
a4466a <=( (not A301) and (not A300) );
a4467a <=( A299 and a4466a );
a4468a <=( a4467a and a4462a );
a4471a <=( A166 and A168 );
a4474a <=( A201 and A200 );
a4475a <=( a4474a and a4471a );
a4478a <=( A267 and A265 );
a4482a <=( (not A302) and (not A301) );
a4483a <=( (not A300) and a4482a );
a4484a <=( a4483a and a4478a );
a4487a <=( A166 and A168 );
a4490a <=( A201 and A200 );
a4491a <=( a4490a and a4487a );
a4494a <=( A267 and A265 );
a4498a <=( (not A301) and (not A299) );
a4499a <=( (not A298) and a4498a );
a4500a <=( a4499a and a4494a );
a4503a <=( A166 and A168 );
a4506a <=( A201 and A200 );
a4507a <=( a4506a and a4503a );
a4510a <=( A267 and A266 );
a4514a <=( (not A302) and (not A301) );
a4515a <=( (not A300) and a4514a );
a4516a <=( a4515a and a4510a );
a4519a <=( A166 and A168 );
a4522a <=( A201 and A200 );
a4523a <=( a4522a and a4519a );
a4526a <=( A267 and A266 );
a4530a <=( (not A301) and (not A299) );
a4531a <=( (not A298) and a4530a );
a4532a <=( a4531a and a4526a );
a4535a <=( A166 and A168 );
a4538a <=( A200 and (not A199) );
a4539a <=( a4538a and a4535a );
a4542a <=( A268 and A203 );
a4546a <=( (not A302) and (not A301) );
a4547a <=( (not A300) and a4546a );
a4548a <=( a4547a and a4542a );
a4551a <=( A166 and A168 );
a4554a <=( A200 and (not A199) );
a4555a <=( a4554a and a4551a );
a4558a <=( A268 and A203 );
a4562a <=( (not A301) and (not A299) );
a4563a <=( (not A298) and a4562a );
a4564a <=( a4563a and a4558a );
a4567a <=( A166 and A168 );
a4570a <=( (not A200) and A199 );
a4571a <=( a4570a and a4567a );
a4574a <=( A268 and A203 );
a4578a <=( (not A302) and (not A301) );
a4579a <=( (not A300) and a4578a );
a4580a <=( a4579a and a4574a );
a4583a <=( A166 and A168 );
a4586a <=( (not A200) and A199 );
a4587a <=( a4586a and a4583a );
a4590a <=( A268 and A203 );
a4594a <=( (not A301) and (not A299) );
a4595a <=( (not A298) and a4594a );
a4596a <=( a4595a and a4590a );
a4599a <=( A166 and A168 );
a4602a <=( (not A200) and (not A199) );
a4603a <=( a4602a and a4599a );
a4606a <=( (not A267) and (not A202) );
a4610a <=( A301 and (not A269) );
a4611a <=( (not A268) and a4610a );
a4612a <=( a4611a and a4606a );
a4615a <=( A166 and A168 );
a4618a <=( (not A200) and (not A199) );
a4619a <=( a4618a and a4615a );
a4622a <=( (not A265) and (not A202) );
a4626a <=( A301 and (not A268) );
a4627a <=( (not A266) and a4626a );
a4628a <=( a4627a and a4622a );
a4631a <=( A167 and A168 );
a4634a <=( A265 and A202 );
a4635a <=( a4634a and a4631a );
a4638a <=( A298 and A267 );
a4642a <=( (not A301) and (not A300) );
a4643a <=( A299 and a4642a );
a4644a <=( a4643a and a4638a );
a4647a <=( A167 and A168 );
a4650a <=( A266 and A202 );
a4651a <=( a4650a and a4647a );
a4654a <=( A298 and A267 );
a4658a <=( (not A301) and (not A300) );
a4659a <=( A299 and a4658a );
a4660a <=( a4659a and a4654a );
a4663a <=( A167 and A168 );
a4666a <=( (not A265) and A202 );
a4667a <=( a4666a and a4663a );
a4670a <=( A269 and A266 );
a4674a <=( (not A302) and (not A301) );
a4675a <=( (not A300) and a4674a );
a4676a <=( a4675a and a4670a );
a4679a <=( A167 and A168 );
a4682a <=( (not A265) and A202 );
a4683a <=( a4682a and a4679a );
a4686a <=( A269 and A266 );
a4690a <=( (not A301) and (not A299) );
a4691a <=( (not A298) and a4690a );
a4692a <=( a4691a and a4686a );
a4695a <=( A167 and A168 );
a4698a <=( A265 and A202 );
a4699a <=( a4698a and a4695a );
a4702a <=( A269 and (not A266) );
a4706a <=( (not A302) and (not A301) );
a4707a <=( (not A300) and a4706a );
a4708a <=( a4707a and a4702a );
a4711a <=( A167 and A168 );
a4714a <=( A265 and A202 );
a4715a <=( a4714a and a4711a );
a4718a <=( A269 and (not A266) );
a4722a <=( (not A301) and (not A299) );
a4723a <=( (not A298) and a4722a );
a4724a <=( a4723a and a4718a );
a4727a <=( A167 and A168 );
a4730a <=( (not A202) and (not A201) );
a4731a <=( a4730a and a4727a );
a4734a <=( (not A267) and (not A203) );
a4738a <=( A301 and (not A269) );
a4739a <=( (not A268) and a4738a );
a4740a <=( a4739a and a4734a );
a4743a <=( A167 and A168 );
a4746a <=( (not A202) and (not A201) );
a4747a <=( a4746a and a4743a );
a4750a <=( (not A265) and (not A203) );
a4754a <=( A301 and (not A268) );
a4755a <=( (not A266) and a4754a );
a4756a <=( a4755a and a4750a );
a4759a <=( A167 and A168 );
a4762a <=( A201 and A199 );
a4763a <=( a4762a and a4759a );
a4766a <=( A298 and A268 );
a4770a <=( (not A301) and (not A300) );
a4771a <=( A299 and a4770a );
a4772a <=( a4771a and a4766a );
a4775a <=( A167 and A168 );
a4778a <=( A201 and A199 );
a4779a <=( a4778a and a4775a );
a4782a <=( A267 and A265 );
a4786a <=( (not A302) and (not A301) );
a4787a <=( (not A300) and a4786a );
a4788a <=( a4787a and a4782a );
a4791a <=( A167 and A168 );
a4794a <=( A201 and A199 );
a4795a <=( a4794a and a4791a );
a4798a <=( A267 and A265 );
a4802a <=( (not A301) and (not A299) );
a4803a <=( (not A298) and a4802a );
a4804a <=( a4803a and a4798a );
a4807a <=( A167 and A168 );
a4810a <=( A201 and A199 );
a4811a <=( a4810a and a4807a );
a4814a <=( A267 and A266 );
a4818a <=( (not A302) and (not A301) );
a4819a <=( (not A300) and a4818a );
a4820a <=( a4819a and a4814a );
a4823a <=( A167 and A168 );
a4826a <=( A201 and A199 );
a4827a <=( a4826a and a4823a );
a4830a <=( A267 and A266 );
a4834a <=( (not A301) and (not A299) );
a4835a <=( (not A298) and a4834a );
a4836a <=( a4835a and a4830a );
a4839a <=( A167 and A168 );
a4842a <=( A201 and A200 );
a4843a <=( a4842a and a4839a );
a4846a <=( A298 and A268 );
a4850a <=( (not A301) and (not A300) );
a4851a <=( A299 and a4850a );
a4852a <=( a4851a and a4846a );
a4855a <=( A167 and A168 );
a4858a <=( A201 and A200 );
a4859a <=( a4858a and a4855a );
a4862a <=( A267 and A265 );
a4866a <=( (not A302) and (not A301) );
a4867a <=( (not A300) and a4866a );
a4868a <=( a4867a and a4862a );
a4871a <=( A167 and A168 );
a4874a <=( A201 and A200 );
a4875a <=( a4874a and a4871a );
a4878a <=( A267 and A265 );
a4882a <=( (not A301) and (not A299) );
a4883a <=( (not A298) and a4882a );
a4884a <=( a4883a and a4878a );
a4887a <=( A167 and A168 );
a4890a <=( A201 and A200 );
a4891a <=( a4890a and a4887a );
a4894a <=( A267 and A266 );
a4898a <=( (not A302) and (not A301) );
a4899a <=( (not A300) and a4898a );
a4900a <=( a4899a and a4894a );
a4903a <=( A167 and A168 );
a4906a <=( A201 and A200 );
a4907a <=( a4906a and a4903a );
a4910a <=( A267 and A266 );
a4914a <=( (not A301) and (not A299) );
a4915a <=( (not A298) and a4914a );
a4916a <=( a4915a and a4910a );
a4919a <=( A167 and A168 );
a4922a <=( A200 and (not A199) );
a4923a <=( a4922a and a4919a );
a4926a <=( A268 and A203 );
a4930a <=( (not A302) and (not A301) );
a4931a <=( (not A300) and a4930a );
a4932a <=( a4931a and a4926a );
a4935a <=( A167 and A168 );
a4938a <=( A200 and (not A199) );
a4939a <=( a4938a and a4935a );
a4942a <=( A268 and A203 );
a4946a <=( (not A301) and (not A299) );
a4947a <=( (not A298) and a4946a );
a4948a <=( a4947a and a4942a );
a4951a <=( A167 and A168 );
a4954a <=( (not A200) and A199 );
a4955a <=( a4954a and a4951a );
a4958a <=( A268 and A203 );
a4962a <=( (not A302) and (not A301) );
a4963a <=( (not A300) and a4962a );
a4964a <=( a4963a and a4958a );
a4967a <=( A167 and A168 );
a4970a <=( (not A200) and A199 );
a4971a <=( a4970a and a4967a );
a4974a <=( A268 and A203 );
a4978a <=( (not A301) and (not A299) );
a4979a <=( (not A298) and a4978a );
a4980a <=( a4979a and a4974a );
a4983a <=( A167 and A168 );
a4986a <=( (not A200) and (not A199) );
a4987a <=( a4986a and a4983a );
a4990a <=( (not A267) and (not A202) );
a4994a <=( A301 and (not A269) );
a4995a <=( (not A268) and a4994a );
a4996a <=( a4995a and a4990a );
a4999a <=( A167 and A168 );
a5002a <=( (not A200) and (not A199) );
a5003a <=( a5002a and a4999a );
a5006a <=( (not A265) and (not A202) );
a5010a <=( A301 and (not A268) );
a5011a <=( (not A266) and a5010a );
a5012a <=( a5011a and a5006a );
a5015a <=( A167 and A170 );
a5018a <=( A202 and (not A166) );
a5019a <=( a5018a and a5015a );
a5022a <=( A298 and A268 );
a5026a <=( (not A301) and (not A300) );
a5027a <=( A299 and a5026a );
a5028a <=( a5027a and a5022a );
a5031a <=( A167 and A170 );
a5034a <=( A202 and (not A166) );
a5035a <=( a5034a and a5031a );
a5038a <=( A267 and A265 );
a5042a <=( (not A302) and (not A301) );
a5043a <=( (not A300) and a5042a );
a5044a <=( a5043a and a5038a );
a5047a <=( A167 and A170 );
a5050a <=( A202 and (not A166) );
a5051a <=( a5050a and a5047a );
a5054a <=( A267 and A265 );
a5058a <=( (not A301) and (not A299) );
a5059a <=( (not A298) and a5058a );
a5060a <=( a5059a and a5054a );
a5063a <=( A167 and A170 );
a5066a <=( A202 and (not A166) );
a5067a <=( a5066a and a5063a );
a5070a <=( A267 and A266 );
a5074a <=( (not A302) and (not A301) );
a5075a <=( (not A300) and a5074a );
a5076a <=( a5075a and a5070a );
a5079a <=( A167 and A170 );
a5082a <=( A202 and (not A166) );
a5083a <=( a5082a and a5079a );
a5086a <=( A267 and A266 );
a5090a <=( (not A301) and (not A299) );
a5091a <=( (not A298) and a5090a );
a5092a <=( a5091a and a5086a );
a5095a <=( A167 and A170 );
a5098a <=( A199 and (not A166) );
a5099a <=( a5098a and a5095a );
a5102a <=( A268 and A201 );
a5106a <=( (not A302) and (not A301) );
a5107a <=( (not A300) and a5106a );
a5108a <=( a5107a and a5102a );
a5111a <=( A167 and A170 );
a5114a <=( A199 and (not A166) );
a5115a <=( a5114a and a5111a );
a5118a <=( A268 and A201 );
a5122a <=( (not A301) and (not A299) );
a5123a <=( (not A298) and a5122a );
a5124a <=( a5123a and a5118a );
a5127a <=( A167 and A170 );
a5130a <=( A200 and (not A166) );
a5131a <=( a5130a and a5127a );
a5134a <=( A268 and A201 );
a5138a <=( (not A302) and (not A301) );
a5139a <=( (not A300) and a5138a );
a5140a <=( a5139a and a5134a );
a5143a <=( A167 and A170 );
a5146a <=( A200 and (not A166) );
a5147a <=( a5146a and a5143a );
a5150a <=( A268 and A201 );
a5154a <=( (not A301) and (not A299) );
a5155a <=( (not A298) and a5154a );
a5156a <=( a5155a and a5150a );
a5159a <=( (not A167) and A170 );
a5162a <=( A202 and A166 );
a5163a <=( a5162a and a5159a );
a5166a <=( A298 and A268 );
a5170a <=( (not A301) and (not A300) );
a5171a <=( A299 and a5170a );
a5172a <=( a5171a and a5166a );
a5175a <=( (not A167) and A170 );
a5178a <=( A202 and A166 );
a5179a <=( a5178a and a5175a );
a5182a <=( A267 and A265 );
a5186a <=( (not A302) and (not A301) );
a5187a <=( (not A300) and a5186a );
a5188a <=( a5187a and a5182a );
a5191a <=( (not A167) and A170 );
a5194a <=( A202 and A166 );
a5195a <=( a5194a and a5191a );
a5198a <=( A267 and A265 );
a5202a <=( (not A301) and (not A299) );
a5203a <=( (not A298) and a5202a );
a5204a <=( a5203a and a5198a );
a5207a <=( (not A167) and A170 );
a5210a <=( A202 and A166 );
a5211a <=( a5210a and a5207a );
a5214a <=( A267 and A266 );
a5218a <=( (not A302) and (not A301) );
a5219a <=( (not A300) and a5218a );
a5220a <=( a5219a and a5214a );
a5223a <=( (not A167) and A170 );
a5226a <=( A202 and A166 );
a5227a <=( a5226a and a5223a );
a5230a <=( A267 and A266 );
a5234a <=( (not A301) and (not A299) );
a5235a <=( (not A298) and a5234a );
a5236a <=( a5235a and a5230a );
a5239a <=( (not A167) and A170 );
a5242a <=( A199 and A166 );
a5243a <=( a5242a and a5239a );
a5246a <=( A268 and A201 );
a5250a <=( (not A302) and (not A301) );
a5251a <=( (not A300) and a5250a );
a5252a <=( a5251a and a5246a );
a5255a <=( (not A167) and A170 );
a5258a <=( A199 and A166 );
a5259a <=( a5258a and a5255a );
a5262a <=( A268 and A201 );
a5266a <=( (not A301) and (not A299) );
a5267a <=( (not A298) and a5266a );
a5268a <=( a5267a and a5262a );
a5271a <=( (not A167) and A170 );
a5274a <=( A200 and A166 );
a5275a <=( a5274a and a5271a );
a5278a <=( A268 and A201 );
a5282a <=( (not A302) and (not A301) );
a5283a <=( (not A300) and a5282a );
a5284a <=( a5283a and a5278a );
a5287a <=( (not A167) and A170 );
a5290a <=( A200 and A166 );
a5291a <=( a5290a and a5287a );
a5294a <=( A268 and A201 );
a5298a <=( (not A301) and (not A299) );
a5299a <=( (not A298) and a5298a );
a5300a <=( a5299a and a5294a );
a5303a <=( A202 and A169 );
a5306a <=( A266 and (not A265) );
a5307a <=( a5306a and a5303a );
a5310a <=( A298 and A269 );
a5314a <=( (not A301) and (not A300) );
a5315a <=( A299 and a5314a );
a5316a <=( a5315a and a5310a );
a5319a <=( A202 and A169 );
a5322a <=( (not A266) and A265 );
a5323a <=( a5322a and a5319a );
a5326a <=( A298 and A269 );
a5330a <=( (not A301) and (not A300) );
a5331a <=( A299 and a5330a );
a5332a <=( a5331a and a5326a );
a5335a <=( (not A201) and A169 );
a5338a <=( (not A203) and (not A202) );
a5339a <=( a5338a and a5335a );
a5342a <=( (not A268) and (not A267) );
a5346a <=( A300 and A299 );
a5347a <=( (not A269) and a5346a );
a5348a <=( a5347a and a5342a );
a5351a <=( (not A201) and A169 );
a5354a <=( (not A203) and (not A202) );
a5355a <=( a5354a and a5351a );
a5358a <=( (not A268) and (not A267) );
a5362a <=( A300 and A298 );
a5363a <=( (not A269) and a5362a );
a5364a <=( a5363a and a5358a );
a5367a <=( (not A201) and A169 );
a5370a <=( (not A203) and (not A202) );
a5371a <=( a5370a and a5367a );
a5374a <=( A266 and A265 );
a5378a <=( A301 and (not A268) );
a5379a <=( (not A267) and a5378a );
a5380a <=( a5379a and a5374a );
a5383a <=( (not A201) and A169 );
a5386a <=( (not A203) and (not A202) );
a5387a <=( a5386a and a5383a );
a5390a <=( (not A266) and (not A265) );
a5394a <=( A300 and A299 );
a5395a <=( (not A268) and a5394a );
a5396a <=( a5395a and a5390a );
a5399a <=( (not A201) and A169 );
a5402a <=( (not A203) and (not A202) );
a5403a <=( a5402a and a5399a );
a5406a <=( (not A266) and (not A265) );
a5410a <=( A300 and A298 );
a5411a <=( (not A268) and a5410a );
a5412a <=( a5411a and a5406a );
a5415a <=( A199 and A169 );
a5418a <=( A265 and A201 );
a5419a <=( a5418a and a5415a );
a5422a <=( A298 and A267 );
a5426a <=( (not A301) and (not A300) );
a5427a <=( A299 and a5426a );
a5428a <=( a5427a and a5422a );
a5431a <=( A199 and A169 );
a5434a <=( A266 and A201 );
a5435a <=( a5434a and a5431a );
a5438a <=( A298 and A267 );
a5442a <=( (not A301) and (not A300) );
a5443a <=( A299 and a5442a );
a5444a <=( a5443a and a5438a );
a5447a <=( A199 and A169 );
a5450a <=( (not A265) and A201 );
a5451a <=( a5450a and a5447a );
a5454a <=( A269 and A266 );
a5458a <=( (not A302) and (not A301) );
a5459a <=( (not A300) and a5458a );
a5460a <=( a5459a and a5454a );
a5463a <=( A199 and A169 );
a5466a <=( (not A265) and A201 );
a5467a <=( a5466a and a5463a );
a5470a <=( A269 and A266 );
a5474a <=( (not A301) and (not A299) );
a5475a <=( (not A298) and a5474a );
a5476a <=( a5475a and a5470a );
a5479a <=( A199 and A169 );
a5482a <=( A265 and A201 );
a5483a <=( a5482a and a5479a );
a5486a <=( A269 and (not A266) );
a5490a <=( (not A302) and (not A301) );
a5491a <=( (not A300) and a5490a );
a5492a <=( a5491a and a5486a );
a5495a <=( A199 and A169 );
a5498a <=( A265 and A201 );
a5499a <=( a5498a and a5495a );
a5502a <=( A269 and (not A266) );
a5506a <=( (not A301) and (not A299) );
a5507a <=( (not A298) and a5506a );
a5508a <=( a5507a and a5502a );
a5511a <=( A200 and A169 );
a5514a <=( A265 and A201 );
a5515a <=( a5514a and a5511a );
a5518a <=( A298 and A267 );
a5522a <=( (not A301) and (not A300) );
a5523a <=( A299 and a5522a );
a5524a <=( a5523a and a5518a );
a5527a <=( A200 and A169 );
a5530a <=( A266 and A201 );
a5531a <=( a5530a and a5527a );
a5534a <=( A298 and A267 );
a5538a <=( (not A301) and (not A300) );
a5539a <=( A299 and a5538a );
a5540a <=( a5539a and a5534a );
a5543a <=( A200 and A169 );
a5546a <=( (not A265) and A201 );
a5547a <=( a5546a and a5543a );
a5550a <=( A269 and A266 );
a5554a <=( (not A302) and (not A301) );
a5555a <=( (not A300) and a5554a );
a5556a <=( a5555a and a5550a );
a5559a <=( A200 and A169 );
a5562a <=( (not A265) and A201 );
a5563a <=( a5562a and a5559a );
a5566a <=( A269 and A266 );
a5570a <=( (not A301) and (not A299) );
a5571a <=( (not A298) and a5570a );
a5572a <=( a5571a and a5566a );
a5575a <=( A200 and A169 );
a5578a <=( A265 and A201 );
a5579a <=( a5578a and a5575a );
a5582a <=( A269 and (not A266) );
a5586a <=( (not A302) and (not A301) );
a5587a <=( (not A300) and a5586a );
a5588a <=( a5587a and a5582a );
a5591a <=( A200 and A169 );
a5594a <=( A265 and A201 );
a5595a <=( a5594a and a5591a );
a5598a <=( A269 and (not A266) );
a5602a <=( (not A301) and (not A299) );
a5603a <=( (not A298) and a5602a );
a5604a <=( a5603a and a5598a );
a5607a <=( A199 and A169 );
a5610a <=( (not A201) and A200 );
a5611a <=( a5610a and a5607a );
a5614a <=( (not A267) and (not A202) );
a5618a <=( A301 and (not A269) );
a5619a <=( (not A268) and a5618a );
a5620a <=( a5619a and a5614a );
a5623a <=( A199 and A169 );
a5626a <=( (not A201) and A200 );
a5627a <=( a5626a and a5623a );
a5630a <=( (not A265) and (not A202) );
a5634a <=( A301 and (not A268) );
a5635a <=( (not A266) and a5634a );
a5636a <=( a5635a and a5630a );
a5639a <=( (not A199) and A169 );
a5642a <=( A203 and A200 );
a5643a <=( a5642a and a5639a );
a5646a <=( A298 and A268 );
a5650a <=( (not A301) and (not A300) );
a5651a <=( A299 and a5650a );
a5652a <=( a5651a and a5646a );
a5655a <=( (not A199) and A169 );
a5658a <=( A203 and A200 );
a5659a <=( a5658a and a5655a );
a5662a <=( A267 and A265 );
a5666a <=( (not A302) and (not A301) );
a5667a <=( (not A300) and a5666a );
a5668a <=( a5667a and a5662a );
a5671a <=( (not A199) and A169 );
a5674a <=( A203 and A200 );
a5675a <=( a5674a and a5671a );
a5678a <=( A267 and A265 );
a5682a <=( (not A301) and (not A299) );
a5683a <=( (not A298) and a5682a );
a5684a <=( a5683a and a5678a );
a5687a <=( (not A199) and A169 );
a5690a <=( A203 and A200 );
a5691a <=( a5690a and a5687a );
a5694a <=( A267 and A266 );
a5698a <=( (not A302) and (not A301) );
a5699a <=( (not A300) and a5698a );
a5700a <=( a5699a and a5694a );
a5703a <=( (not A199) and A169 );
a5706a <=( A203 and A200 );
a5707a <=( a5706a and a5703a );
a5710a <=( A267 and A266 );
a5714a <=( (not A301) and (not A299) );
a5715a <=( (not A298) and a5714a );
a5716a <=( a5715a and a5710a );
a5719a <=( A199 and A169 );
a5722a <=( A203 and (not A200) );
a5723a <=( a5722a and a5719a );
a5726a <=( A298 and A268 );
a5730a <=( (not A301) and (not A300) );
a5731a <=( A299 and a5730a );
a5732a <=( a5731a and a5726a );
a5735a <=( A199 and A169 );
a5738a <=( A203 and (not A200) );
a5739a <=( a5738a and a5735a );
a5742a <=( A267 and A265 );
a5746a <=( (not A302) and (not A301) );
a5747a <=( (not A300) and a5746a );
a5748a <=( a5747a and a5742a );
a5751a <=( A199 and A169 );
a5754a <=( A203 and (not A200) );
a5755a <=( a5754a and a5751a );
a5758a <=( A267 and A265 );
a5762a <=( (not A301) and (not A299) );
a5763a <=( (not A298) and a5762a );
a5764a <=( a5763a and a5758a );
a5767a <=( A199 and A169 );
a5770a <=( A203 and (not A200) );
a5771a <=( a5770a and a5767a );
a5774a <=( A267 and A266 );
a5778a <=( (not A302) and (not A301) );
a5779a <=( (not A300) and a5778a );
a5780a <=( a5779a and a5774a );
a5783a <=( A199 and A169 );
a5786a <=( A203 and (not A200) );
a5787a <=( a5786a and a5783a );
a5790a <=( A267 and A266 );
a5794a <=( (not A301) and (not A299) );
a5795a <=( (not A298) and a5794a );
a5796a <=( a5795a and a5790a );
a5799a <=( (not A199) and A169 );
a5802a <=( (not A202) and (not A200) );
a5803a <=( a5802a and a5799a );
a5806a <=( (not A268) and (not A267) );
a5810a <=( A300 and A299 );
a5811a <=( (not A269) and a5810a );
a5812a <=( a5811a and a5806a );
a5815a <=( (not A199) and A169 );
a5818a <=( (not A202) and (not A200) );
a5819a <=( a5818a and a5815a );
a5822a <=( (not A268) and (not A267) );
a5826a <=( A300 and A298 );
a5827a <=( (not A269) and a5826a );
a5828a <=( a5827a and a5822a );
a5831a <=( (not A199) and A169 );
a5834a <=( (not A202) and (not A200) );
a5835a <=( a5834a and a5831a );
a5838a <=( A266 and A265 );
a5842a <=( A301 and (not A268) );
a5843a <=( (not A267) and a5842a );
a5844a <=( a5843a and a5838a );
a5847a <=( (not A199) and A169 );
a5850a <=( (not A202) and (not A200) );
a5851a <=( a5850a and a5847a );
a5854a <=( (not A266) and (not A265) );
a5858a <=( A300 and A299 );
a5859a <=( (not A268) and a5858a );
a5860a <=( a5859a and a5854a );
a5863a <=( (not A199) and A169 );
a5866a <=( (not A202) and (not A200) );
a5867a <=( a5866a and a5863a );
a5870a <=( (not A266) and (not A265) );
a5874a <=( A300 and A298 );
a5875a <=( (not A268) and a5874a );
a5876a <=( a5875a and a5870a );
a5879a <=( (not A167) and (not A169) );
a5882a <=( A202 and (not A166) );
a5883a <=( a5882a and a5879a );
a5886a <=( (not A268) and (not A267) );
a5890a <=( A300 and A299 );
a5891a <=( (not A269) and a5890a );
a5892a <=( a5891a and a5886a );
a5895a <=( (not A167) and (not A169) );
a5898a <=( A202 and (not A166) );
a5899a <=( a5898a and a5895a );
a5902a <=( (not A268) and (not A267) );
a5906a <=( A300 and A298 );
a5907a <=( (not A269) and a5906a );
a5908a <=( a5907a and a5902a );
a5911a <=( (not A167) and (not A169) );
a5914a <=( A202 and (not A166) );
a5915a <=( a5914a and a5911a );
a5918a <=( A266 and A265 );
a5922a <=( A301 and (not A268) );
a5923a <=( (not A267) and a5922a );
a5924a <=( a5923a and a5918a );
a5927a <=( (not A167) and (not A169) );
a5930a <=( A202 and (not A166) );
a5931a <=( a5930a and a5927a );
a5934a <=( (not A266) and (not A265) );
a5938a <=( A300 and A299 );
a5939a <=( (not A268) and a5938a );
a5940a <=( a5939a and a5934a );
a5943a <=( (not A167) and (not A169) );
a5946a <=( A202 and (not A166) );
a5947a <=( a5946a and a5943a );
a5950a <=( (not A266) and (not A265) );
a5954a <=( A300 and A298 );
a5955a <=( (not A268) and a5954a );
a5956a <=( a5955a and a5950a );
a5959a <=( (not A167) and (not A169) );
a5962a <=( A199 and (not A166) );
a5963a <=( a5962a and a5959a );
a5966a <=( (not A267) and A201 );
a5970a <=( A301 and (not A269) );
a5971a <=( (not A268) and a5970a );
a5972a <=( a5971a and a5966a );
a5975a <=( (not A167) and (not A169) );
a5978a <=( A199 and (not A166) );
a5979a <=( a5978a and a5975a );
a5982a <=( (not A265) and A201 );
a5986a <=( A301 and (not A268) );
a5987a <=( (not A266) and a5986a );
a5988a <=( a5987a and a5982a );
a5991a <=( (not A167) and (not A169) );
a5994a <=( A200 and (not A166) );
a5995a <=( a5994a and a5991a );
a5998a <=( (not A267) and A201 );
a6002a <=( A301 and (not A269) );
a6003a <=( (not A268) and a6002a );
a6004a <=( a6003a and a5998a );
a6007a <=( (not A167) and (not A169) );
a6010a <=( A200 and (not A166) );
a6011a <=( a6010a and a6007a );
a6014a <=( (not A265) and A201 );
a6018a <=( A301 and (not A268) );
a6019a <=( (not A266) and a6018a );
a6020a <=( a6019a and a6014a );
a6023a <=( (not A168) and (not A169) );
a6026a <=( A166 and A167 );
a6027a <=( a6026a and a6023a );
a6030a <=( (not A267) and A202 );
a6034a <=( A301 and (not A269) );
a6035a <=( (not A268) and a6034a );
a6036a <=( a6035a and a6030a );
a6039a <=( (not A168) and (not A169) );
a6042a <=( A166 and A167 );
a6043a <=( a6042a and a6039a );
a6046a <=( (not A265) and A202 );
a6050a <=( A301 and (not A268) );
a6051a <=( (not A266) and a6050a );
a6052a <=( a6051a and a6046a );
a6055a <=( (not A169) and (not A170) );
a6058a <=( A202 and (not A168) );
a6059a <=( a6058a and a6055a );
a6062a <=( (not A268) and (not A267) );
a6066a <=( A300 and A299 );
a6067a <=( (not A269) and a6066a );
a6068a <=( a6067a and a6062a );
a6071a <=( (not A169) and (not A170) );
a6074a <=( A202 and (not A168) );
a6075a <=( a6074a and a6071a );
a6078a <=( (not A268) and (not A267) );
a6082a <=( A300 and A298 );
a6083a <=( (not A269) and a6082a );
a6084a <=( a6083a and a6078a );
a6087a <=( (not A169) and (not A170) );
a6090a <=( A202 and (not A168) );
a6091a <=( a6090a and a6087a );
a6094a <=( A266 and A265 );
a6098a <=( A301 and (not A268) );
a6099a <=( (not A267) and a6098a );
a6100a <=( a6099a and a6094a );
a6103a <=( (not A169) and (not A170) );
a6106a <=( A202 and (not A168) );
a6107a <=( a6106a and a6103a );
a6110a <=( (not A266) and (not A265) );
a6114a <=( A300 and A299 );
a6115a <=( (not A268) and a6114a );
a6116a <=( a6115a and a6110a );
a6119a <=( (not A169) and (not A170) );
a6122a <=( A202 and (not A168) );
a6123a <=( a6122a and a6119a );
a6126a <=( (not A266) and (not A265) );
a6130a <=( A300 and A298 );
a6131a <=( (not A268) and a6130a );
a6132a <=( a6131a and a6126a );
a6135a <=( (not A169) and (not A170) );
a6138a <=( A199 and (not A168) );
a6139a <=( a6138a and a6135a );
a6142a <=( (not A267) and A201 );
a6146a <=( A301 and (not A269) );
a6147a <=( (not A268) and a6146a );
a6148a <=( a6147a and a6142a );
a6151a <=( (not A169) and (not A170) );
a6154a <=( A199 and (not A168) );
a6155a <=( a6154a and a6151a );
a6158a <=( (not A265) and A201 );
a6162a <=( A301 and (not A268) );
a6163a <=( (not A266) and a6162a );
a6164a <=( a6163a and a6158a );
a6167a <=( (not A169) and (not A170) );
a6170a <=( A200 and (not A168) );
a6171a <=( a6170a and a6167a );
a6174a <=( (not A267) and A201 );
a6178a <=( A301 and (not A269) );
a6179a <=( (not A268) and a6178a );
a6180a <=( a6179a and a6174a );
a6183a <=( (not A169) and (not A170) );
a6186a <=( A200 and (not A168) );
a6187a <=( a6186a and a6183a );
a6190a <=( (not A265) and A201 );
a6194a <=( A301 and (not A268) );
a6195a <=( (not A266) and a6194a );
a6196a <=( a6195a and a6190a );
a6199a <=( A166 and A168 );
a6203a <=( A266 and (not A265) );
a6204a <=( A202 and a6203a );
a6205a <=( a6204a and a6199a );
a6208a <=( A298 and A269 );
a6212a <=( (not A301) and (not A300) );
a6213a <=( A299 and a6212a );
a6214a <=( a6213a and a6208a );
a6217a <=( A166 and A168 );
a6221a <=( (not A266) and A265 );
a6222a <=( A202 and a6221a );
a6223a <=( a6222a and a6217a );
a6226a <=( A298 and A269 );
a6230a <=( (not A301) and (not A300) );
a6231a <=( A299 and a6230a );
a6232a <=( a6231a and a6226a );
a6235a <=( A166 and A168 );
a6239a <=( (not A203) and (not A202) );
a6240a <=( (not A201) and a6239a );
a6241a <=( a6240a and a6235a );
a6244a <=( (not A268) and (not A267) );
a6248a <=( A300 and A299 );
a6249a <=( (not A269) and a6248a );
a6250a <=( a6249a and a6244a );
a6253a <=( A166 and A168 );
a6257a <=( (not A203) and (not A202) );
a6258a <=( (not A201) and a6257a );
a6259a <=( a6258a and a6253a );
a6262a <=( (not A268) and (not A267) );
a6266a <=( A300 and A298 );
a6267a <=( (not A269) and a6266a );
a6268a <=( a6267a and a6262a );
a6271a <=( A166 and A168 );
a6275a <=( (not A203) and (not A202) );
a6276a <=( (not A201) and a6275a );
a6277a <=( a6276a and a6271a );
a6280a <=( A266 and A265 );
a6284a <=( A301 and (not A268) );
a6285a <=( (not A267) and a6284a );
a6286a <=( a6285a and a6280a );
a6289a <=( A166 and A168 );
a6293a <=( (not A203) and (not A202) );
a6294a <=( (not A201) and a6293a );
a6295a <=( a6294a and a6289a );
a6298a <=( (not A266) and (not A265) );
a6302a <=( A300 and A299 );
a6303a <=( (not A268) and a6302a );
a6304a <=( a6303a and a6298a );
a6307a <=( A166 and A168 );
a6311a <=( (not A203) and (not A202) );
a6312a <=( (not A201) and a6311a );
a6313a <=( a6312a and a6307a );
a6316a <=( (not A266) and (not A265) );
a6320a <=( A300 and A298 );
a6321a <=( (not A268) and a6320a );
a6322a <=( a6321a and a6316a );
a6325a <=( A166 and A168 );
a6329a <=( A265 and A201 );
a6330a <=( A199 and a6329a );
a6331a <=( a6330a and a6325a );
a6334a <=( A298 and A267 );
a6338a <=( (not A301) and (not A300) );
a6339a <=( A299 and a6338a );
a6340a <=( a6339a and a6334a );
a6343a <=( A166 and A168 );
a6347a <=( A266 and A201 );
a6348a <=( A199 and a6347a );
a6349a <=( a6348a and a6343a );
a6352a <=( A298 and A267 );
a6356a <=( (not A301) and (not A300) );
a6357a <=( A299 and a6356a );
a6358a <=( a6357a and a6352a );
a6361a <=( A166 and A168 );
a6365a <=( (not A265) and A201 );
a6366a <=( A199 and a6365a );
a6367a <=( a6366a and a6361a );
a6370a <=( A269 and A266 );
a6374a <=( (not A302) and (not A301) );
a6375a <=( (not A300) and a6374a );
a6376a <=( a6375a and a6370a );
a6379a <=( A166 and A168 );
a6383a <=( (not A265) and A201 );
a6384a <=( A199 and a6383a );
a6385a <=( a6384a and a6379a );
a6388a <=( A269 and A266 );
a6392a <=( (not A301) and (not A299) );
a6393a <=( (not A298) and a6392a );
a6394a <=( a6393a and a6388a );
a6397a <=( A166 and A168 );
a6401a <=( A265 and A201 );
a6402a <=( A199 and a6401a );
a6403a <=( a6402a and a6397a );
a6406a <=( A269 and (not A266) );
a6410a <=( (not A302) and (not A301) );
a6411a <=( (not A300) and a6410a );
a6412a <=( a6411a and a6406a );
a6415a <=( A166 and A168 );
a6419a <=( A265 and A201 );
a6420a <=( A199 and a6419a );
a6421a <=( a6420a and a6415a );
a6424a <=( A269 and (not A266) );
a6428a <=( (not A301) and (not A299) );
a6429a <=( (not A298) and a6428a );
a6430a <=( a6429a and a6424a );
a6433a <=( A166 and A168 );
a6437a <=( A265 and A201 );
a6438a <=( A200 and a6437a );
a6439a <=( a6438a and a6433a );
a6442a <=( A298 and A267 );
a6446a <=( (not A301) and (not A300) );
a6447a <=( A299 and a6446a );
a6448a <=( a6447a and a6442a );
a6451a <=( A166 and A168 );
a6455a <=( A266 and A201 );
a6456a <=( A200 and a6455a );
a6457a <=( a6456a and a6451a );
a6460a <=( A298 and A267 );
a6464a <=( (not A301) and (not A300) );
a6465a <=( A299 and a6464a );
a6466a <=( a6465a and a6460a );
a6469a <=( A166 and A168 );
a6473a <=( (not A265) and A201 );
a6474a <=( A200 and a6473a );
a6475a <=( a6474a and a6469a );
a6478a <=( A269 and A266 );
a6482a <=( (not A302) and (not A301) );
a6483a <=( (not A300) and a6482a );
a6484a <=( a6483a and a6478a );
a6487a <=( A166 and A168 );
a6491a <=( (not A265) and A201 );
a6492a <=( A200 and a6491a );
a6493a <=( a6492a and a6487a );
a6496a <=( A269 and A266 );
a6500a <=( (not A301) and (not A299) );
a6501a <=( (not A298) and a6500a );
a6502a <=( a6501a and a6496a );
a6505a <=( A166 and A168 );
a6509a <=( A265 and A201 );
a6510a <=( A200 and a6509a );
a6511a <=( a6510a and a6505a );
a6514a <=( A269 and (not A266) );
a6518a <=( (not A302) and (not A301) );
a6519a <=( (not A300) and a6518a );
a6520a <=( a6519a and a6514a );
a6523a <=( A166 and A168 );
a6527a <=( A265 and A201 );
a6528a <=( A200 and a6527a );
a6529a <=( a6528a and a6523a );
a6532a <=( A269 and (not A266) );
a6536a <=( (not A301) and (not A299) );
a6537a <=( (not A298) and a6536a );
a6538a <=( a6537a and a6532a );
a6541a <=( A166 and A168 );
a6545a <=( (not A201) and A200 );
a6546a <=( A199 and a6545a );
a6547a <=( a6546a and a6541a );
a6550a <=( (not A267) and (not A202) );
a6554a <=( A301 and (not A269) );
a6555a <=( (not A268) and a6554a );
a6556a <=( a6555a and a6550a );
a6559a <=( A166 and A168 );
a6563a <=( (not A201) and A200 );
a6564a <=( A199 and a6563a );
a6565a <=( a6564a and a6559a );
a6568a <=( (not A265) and (not A202) );
a6572a <=( A301 and (not A268) );
a6573a <=( (not A266) and a6572a );
a6574a <=( a6573a and a6568a );
a6577a <=( A166 and A168 );
a6581a <=( A203 and A200 );
a6582a <=( (not A199) and a6581a );
a6583a <=( a6582a and a6577a );
a6586a <=( A298 and A268 );
a6590a <=( (not A301) and (not A300) );
a6591a <=( A299 and a6590a );
a6592a <=( a6591a and a6586a );
a6595a <=( A166 and A168 );
a6599a <=( A203 and A200 );
a6600a <=( (not A199) and a6599a );
a6601a <=( a6600a and a6595a );
a6604a <=( A267 and A265 );
a6608a <=( (not A302) and (not A301) );
a6609a <=( (not A300) and a6608a );
a6610a <=( a6609a and a6604a );
a6613a <=( A166 and A168 );
a6617a <=( A203 and A200 );
a6618a <=( (not A199) and a6617a );
a6619a <=( a6618a and a6613a );
a6622a <=( A267 and A265 );
a6626a <=( (not A301) and (not A299) );
a6627a <=( (not A298) and a6626a );
a6628a <=( a6627a and a6622a );
a6631a <=( A166 and A168 );
a6635a <=( A203 and A200 );
a6636a <=( (not A199) and a6635a );
a6637a <=( a6636a and a6631a );
a6640a <=( A267 and A266 );
a6644a <=( (not A302) and (not A301) );
a6645a <=( (not A300) and a6644a );
a6646a <=( a6645a and a6640a );
a6649a <=( A166 and A168 );
a6653a <=( A203 and A200 );
a6654a <=( (not A199) and a6653a );
a6655a <=( a6654a and a6649a );
a6658a <=( A267 and A266 );
a6662a <=( (not A301) and (not A299) );
a6663a <=( (not A298) and a6662a );
a6664a <=( a6663a and a6658a );
a6667a <=( A166 and A168 );
a6671a <=( A203 and (not A200) );
a6672a <=( A199 and a6671a );
a6673a <=( a6672a and a6667a );
a6676a <=( A298 and A268 );
a6680a <=( (not A301) and (not A300) );
a6681a <=( A299 and a6680a );
a6682a <=( a6681a and a6676a );
a6685a <=( A166 and A168 );
a6689a <=( A203 and (not A200) );
a6690a <=( A199 and a6689a );
a6691a <=( a6690a and a6685a );
a6694a <=( A267 and A265 );
a6698a <=( (not A302) and (not A301) );
a6699a <=( (not A300) and a6698a );
a6700a <=( a6699a and a6694a );
a6703a <=( A166 and A168 );
a6707a <=( A203 and (not A200) );
a6708a <=( A199 and a6707a );
a6709a <=( a6708a and a6703a );
a6712a <=( A267 and A265 );
a6716a <=( (not A301) and (not A299) );
a6717a <=( (not A298) and a6716a );
a6718a <=( a6717a and a6712a );
a6721a <=( A166 and A168 );
a6725a <=( A203 and (not A200) );
a6726a <=( A199 and a6725a );
a6727a <=( a6726a and a6721a );
a6730a <=( A267 and A266 );
a6734a <=( (not A302) and (not A301) );
a6735a <=( (not A300) and a6734a );
a6736a <=( a6735a and a6730a );
a6739a <=( A166 and A168 );
a6743a <=( A203 and (not A200) );
a6744a <=( A199 and a6743a );
a6745a <=( a6744a and a6739a );
a6748a <=( A267 and A266 );
a6752a <=( (not A301) and (not A299) );
a6753a <=( (not A298) and a6752a );
a6754a <=( a6753a and a6748a );
a6757a <=( A166 and A168 );
a6761a <=( (not A202) and (not A200) );
a6762a <=( (not A199) and a6761a );
a6763a <=( a6762a and a6757a );
a6766a <=( (not A268) and (not A267) );
a6770a <=( A300 and A299 );
a6771a <=( (not A269) and a6770a );
a6772a <=( a6771a and a6766a );
a6775a <=( A166 and A168 );
a6779a <=( (not A202) and (not A200) );
a6780a <=( (not A199) and a6779a );
a6781a <=( a6780a and a6775a );
a6784a <=( (not A268) and (not A267) );
a6788a <=( A300 and A298 );
a6789a <=( (not A269) and a6788a );
a6790a <=( a6789a and a6784a );
a6793a <=( A166 and A168 );
a6797a <=( (not A202) and (not A200) );
a6798a <=( (not A199) and a6797a );
a6799a <=( a6798a and a6793a );
a6802a <=( A266 and A265 );
a6806a <=( A301 and (not A268) );
a6807a <=( (not A267) and a6806a );
a6808a <=( a6807a and a6802a );
a6811a <=( A166 and A168 );
a6815a <=( (not A202) and (not A200) );
a6816a <=( (not A199) and a6815a );
a6817a <=( a6816a and a6811a );
a6820a <=( (not A266) and (not A265) );
a6824a <=( A300 and A299 );
a6825a <=( (not A268) and a6824a );
a6826a <=( a6825a and a6820a );
a6829a <=( A166 and A168 );
a6833a <=( (not A202) and (not A200) );
a6834a <=( (not A199) and a6833a );
a6835a <=( a6834a and a6829a );
a6838a <=( (not A266) and (not A265) );
a6842a <=( A300 and A298 );
a6843a <=( (not A268) and a6842a );
a6844a <=( a6843a and a6838a );
a6847a <=( A167 and A168 );
a6851a <=( A266 and (not A265) );
a6852a <=( A202 and a6851a );
a6853a <=( a6852a and a6847a );
a6856a <=( A298 and A269 );
a6860a <=( (not A301) and (not A300) );
a6861a <=( A299 and a6860a );
a6862a <=( a6861a and a6856a );
a6865a <=( A167 and A168 );
a6869a <=( (not A266) and A265 );
a6870a <=( A202 and a6869a );
a6871a <=( a6870a and a6865a );
a6874a <=( A298 and A269 );
a6878a <=( (not A301) and (not A300) );
a6879a <=( A299 and a6878a );
a6880a <=( a6879a and a6874a );
a6883a <=( A167 and A168 );
a6887a <=( (not A203) and (not A202) );
a6888a <=( (not A201) and a6887a );
a6889a <=( a6888a and a6883a );
a6892a <=( (not A268) and (not A267) );
a6896a <=( A300 and A299 );
a6897a <=( (not A269) and a6896a );
a6898a <=( a6897a and a6892a );
a6901a <=( A167 and A168 );
a6905a <=( (not A203) and (not A202) );
a6906a <=( (not A201) and a6905a );
a6907a <=( a6906a and a6901a );
a6910a <=( (not A268) and (not A267) );
a6914a <=( A300 and A298 );
a6915a <=( (not A269) and a6914a );
a6916a <=( a6915a and a6910a );
a6919a <=( A167 and A168 );
a6923a <=( (not A203) and (not A202) );
a6924a <=( (not A201) and a6923a );
a6925a <=( a6924a and a6919a );
a6928a <=( A266 and A265 );
a6932a <=( A301 and (not A268) );
a6933a <=( (not A267) and a6932a );
a6934a <=( a6933a and a6928a );
a6937a <=( A167 and A168 );
a6941a <=( (not A203) and (not A202) );
a6942a <=( (not A201) and a6941a );
a6943a <=( a6942a and a6937a );
a6946a <=( (not A266) and (not A265) );
a6950a <=( A300 and A299 );
a6951a <=( (not A268) and a6950a );
a6952a <=( a6951a and a6946a );
a6955a <=( A167 and A168 );
a6959a <=( (not A203) and (not A202) );
a6960a <=( (not A201) and a6959a );
a6961a <=( a6960a and a6955a );
a6964a <=( (not A266) and (not A265) );
a6968a <=( A300 and A298 );
a6969a <=( (not A268) and a6968a );
a6970a <=( a6969a and a6964a );
a6973a <=( A167 and A168 );
a6977a <=( A265 and A201 );
a6978a <=( A199 and a6977a );
a6979a <=( a6978a and a6973a );
a6982a <=( A298 and A267 );
a6986a <=( (not A301) and (not A300) );
a6987a <=( A299 and a6986a );
a6988a <=( a6987a and a6982a );
a6991a <=( A167 and A168 );
a6995a <=( A266 and A201 );
a6996a <=( A199 and a6995a );
a6997a <=( a6996a and a6991a );
a7000a <=( A298 and A267 );
a7004a <=( (not A301) and (not A300) );
a7005a <=( A299 and a7004a );
a7006a <=( a7005a and a7000a );
a7009a <=( A167 and A168 );
a7013a <=( (not A265) and A201 );
a7014a <=( A199 and a7013a );
a7015a <=( a7014a and a7009a );
a7018a <=( A269 and A266 );
a7022a <=( (not A302) and (not A301) );
a7023a <=( (not A300) and a7022a );
a7024a <=( a7023a and a7018a );
a7027a <=( A167 and A168 );
a7031a <=( (not A265) and A201 );
a7032a <=( A199 and a7031a );
a7033a <=( a7032a and a7027a );
a7036a <=( A269 and A266 );
a7040a <=( (not A301) and (not A299) );
a7041a <=( (not A298) and a7040a );
a7042a <=( a7041a and a7036a );
a7045a <=( A167 and A168 );
a7049a <=( A265 and A201 );
a7050a <=( A199 and a7049a );
a7051a <=( a7050a and a7045a );
a7054a <=( A269 and (not A266) );
a7058a <=( (not A302) and (not A301) );
a7059a <=( (not A300) and a7058a );
a7060a <=( a7059a and a7054a );
a7063a <=( A167 and A168 );
a7067a <=( A265 and A201 );
a7068a <=( A199 and a7067a );
a7069a <=( a7068a and a7063a );
a7072a <=( A269 and (not A266) );
a7076a <=( (not A301) and (not A299) );
a7077a <=( (not A298) and a7076a );
a7078a <=( a7077a and a7072a );
a7081a <=( A167 and A168 );
a7085a <=( A265 and A201 );
a7086a <=( A200 and a7085a );
a7087a <=( a7086a and a7081a );
a7090a <=( A298 and A267 );
a7094a <=( (not A301) and (not A300) );
a7095a <=( A299 and a7094a );
a7096a <=( a7095a and a7090a );
a7099a <=( A167 and A168 );
a7103a <=( A266 and A201 );
a7104a <=( A200 and a7103a );
a7105a <=( a7104a and a7099a );
a7108a <=( A298 and A267 );
a7112a <=( (not A301) and (not A300) );
a7113a <=( A299 and a7112a );
a7114a <=( a7113a and a7108a );
a7117a <=( A167 and A168 );
a7121a <=( (not A265) and A201 );
a7122a <=( A200 and a7121a );
a7123a <=( a7122a and a7117a );
a7126a <=( A269 and A266 );
a7130a <=( (not A302) and (not A301) );
a7131a <=( (not A300) and a7130a );
a7132a <=( a7131a and a7126a );
a7135a <=( A167 and A168 );
a7139a <=( (not A265) and A201 );
a7140a <=( A200 and a7139a );
a7141a <=( a7140a and a7135a );
a7144a <=( A269 and A266 );
a7148a <=( (not A301) and (not A299) );
a7149a <=( (not A298) and a7148a );
a7150a <=( a7149a and a7144a );
a7153a <=( A167 and A168 );
a7157a <=( A265 and A201 );
a7158a <=( A200 and a7157a );
a7159a <=( a7158a and a7153a );
a7162a <=( A269 and (not A266) );
a7166a <=( (not A302) and (not A301) );
a7167a <=( (not A300) and a7166a );
a7168a <=( a7167a and a7162a );
a7171a <=( A167 and A168 );
a7175a <=( A265 and A201 );
a7176a <=( A200 and a7175a );
a7177a <=( a7176a and a7171a );
a7180a <=( A269 and (not A266) );
a7184a <=( (not A301) and (not A299) );
a7185a <=( (not A298) and a7184a );
a7186a <=( a7185a and a7180a );
a7189a <=( A167 and A168 );
a7193a <=( (not A201) and A200 );
a7194a <=( A199 and a7193a );
a7195a <=( a7194a and a7189a );
a7198a <=( (not A267) and (not A202) );
a7202a <=( A301 and (not A269) );
a7203a <=( (not A268) and a7202a );
a7204a <=( a7203a and a7198a );
a7207a <=( A167 and A168 );
a7211a <=( (not A201) and A200 );
a7212a <=( A199 and a7211a );
a7213a <=( a7212a and a7207a );
a7216a <=( (not A265) and (not A202) );
a7220a <=( A301 and (not A268) );
a7221a <=( (not A266) and a7220a );
a7222a <=( a7221a and a7216a );
a7225a <=( A167 and A168 );
a7229a <=( A203 and A200 );
a7230a <=( (not A199) and a7229a );
a7231a <=( a7230a and a7225a );
a7234a <=( A298 and A268 );
a7238a <=( (not A301) and (not A300) );
a7239a <=( A299 and a7238a );
a7240a <=( a7239a and a7234a );
a7243a <=( A167 and A168 );
a7247a <=( A203 and A200 );
a7248a <=( (not A199) and a7247a );
a7249a <=( a7248a and a7243a );
a7252a <=( A267 and A265 );
a7256a <=( (not A302) and (not A301) );
a7257a <=( (not A300) and a7256a );
a7258a <=( a7257a and a7252a );
a7261a <=( A167 and A168 );
a7265a <=( A203 and A200 );
a7266a <=( (not A199) and a7265a );
a7267a <=( a7266a and a7261a );
a7270a <=( A267 and A265 );
a7274a <=( (not A301) and (not A299) );
a7275a <=( (not A298) and a7274a );
a7276a <=( a7275a and a7270a );
a7279a <=( A167 and A168 );
a7283a <=( A203 and A200 );
a7284a <=( (not A199) and a7283a );
a7285a <=( a7284a and a7279a );
a7288a <=( A267 and A266 );
a7292a <=( (not A302) and (not A301) );
a7293a <=( (not A300) and a7292a );
a7294a <=( a7293a and a7288a );
a7297a <=( A167 and A168 );
a7301a <=( A203 and A200 );
a7302a <=( (not A199) and a7301a );
a7303a <=( a7302a and a7297a );
a7306a <=( A267 and A266 );
a7310a <=( (not A301) and (not A299) );
a7311a <=( (not A298) and a7310a );
a7312a <=( a7311a and a7306a );
a7315a <=( A167 and A168 );
a7319a <=( A203 and (not A200) );
a7320a <=( A199 and a7319a );
a7321a <=( a7320a and a7315a );
a7324a <=( A298 and A268 );
a7328a <=( (not A301) and (not A300) );
a7329a <=( A299 and a7328a );
a7330a <=( a7329a and a7324a );
a7333a <=( A167 and A168 );
a7337a <=( A203 and (not A200) );
a7338a <=( A199 and a7337a );
a7339a <=( a7338a and a7333a );
a7342a <=( A267 and A265 );
a7346a <=( (not A302) and (not A301) );
a7347a <=( (not A300) and a7346a );
a7348a <=( a7347a and a7342a );
a7351a <=( A167 and A168 );
a7355a <=( A203 and (not A200) );
a7356a <=( A199 and a7355a );
a7357a <=( a7356a and a7351a );
a7360a <=( A267 and A265 );
a7364a <=( (not A301) and (not A299) );
a7365a <=( (not A298) and a7364a );
a7366a <=( a7365a and a7360a );
a7369a <=( A167 and A168 );
a7373a <=( A203 and (not A200) );
a7374a <=( A199 and a7373a );
a7375a <=( a7374a and a7369a );
a7378a <=( A267 and A266 );
a7382a <=( (not A302) and (not A301) );
a7383a <=( (not A300) and a7382a );
a7384a <=( a7383a and a7378a );
a7387a <=( A167 and A168 );
a7391a <=( A203 and (not A200) );
a7392a <=( A199 and a7391a );
a7393a <=( a7392a and a7387a );
a7396a <=( A267 and A266 );
a7400a <=( (not A301) and (not A299) );
a7401a <=( (not A298) and a7400a );
a7402a <=( a7401a and a7396a );
a7405a <=( A167 and A168 );
a7409a <=( (not A202) and (not A200) );
a7410a <=( (not A199) and a7409a );
a7411a <=( a7410a and a7405a );
a7414a <=( (not A268) and (not A267) );
a7418a <=( A300 and A299 );
a7419a <=( (not A269) and a7418a );
a7420a <=( a7419a and a7414a );
a7423a <=( A167 and A168 );
a7427a <=( (not A202) and (not A200) );
a7428a <=( (not A199) and a7427a );
a7429a <=( a7428a and a7423a );
a7432a <=( (not A268) and (not A267) );
a7436a <=( A300 and A298 );
a7437a <=( (not A269) and a7436a );
a7438a <=( a7437a and a7432a );
a7441a <=( A167 and A168 );
a7445a <=( (not A202) and (not A200) );
a7446a <=( (not A199) and a7445a );
a7447a <=( a7446a and a7441a );
a7450a <=( A266 and A265 );
a7454a <=( A301 and (not A268) );
a7455a <=( (not A267) and a7454a );
a7456a <=( a7455a and a7450a );
a7459a <=( A167 and A168 );
a7463a <=( (not A202) and (not A200) );
a7464a <=( (not A199) and a7463a );
a7465a <=( a7464a and a7459a );
a7468a <=( (not A266) and (not A265) );
a7472a <=( A300 and A299 );
a7473a <=( (not A268) and a7472a );
a7474a <=( a7473a and a7468a );
a7477a <=( A167 and A168 );
a7481a <=( (not A202) and (not A200) );
a7482a <=( (not A199) and a7481a );
a7483a <=( a7482a and a7477a );
a7486a <=( (not A266) and (not A265) );
a7490a <=( A300 and A298 );
a7491a <=( (not A268) and a7490a );
a7492a <=( a7491a and a7486a );
a7495a <=( A167 and A170 );
a7499a <=( A265 and A202 );
a7500a <=( (not A166) and a7499a );
a7501a <=( a7500a and a7495a );
a7504a <=( A298 and A267 );
a7508a <=( (not A301) and (not A300) );
a7509a <=( A299 and a7508a );
a7510a <=( a7509a and a7504a );
a7513a <=( A167 and A170 );
a7517a <=( A266 and A202 );
a7518a <=( (not A166) and a7517a );
a7519a <=( a7518a and a7513a );
a7522a <=( A298 and A267 );
a7526a <=( (not A301) and (not A300) );
a7527a <=( A299 and a7526a );
a7528a <=( a7527a and a7522a );
a7531a <=( A167 and A170 );
a7535a <=( (not A265) and A202 );
a7536a <=( (not A166) and a7535a );
a7537a <=( a7536a and a7531a );
a7540a <=( A269 and A266 );
a7544a <=( (not A302) and (not A301) );
a7545a <=( (not A300) and a7544a );
a7546a <=( a7545a and a7540a );
a7549a <=( A167 and A170 );
a7553a <=( (not A265) and A202 );
a7554a <=( (not A166) and a7553a );
a7555a <=( a7554a and a7549a );
a7558a <=( A269 and A266 );
a7562a <=( (not A301) and (not A299) );
a7563a <=( (not A298) and a7562a );
a7564a <=( a7563a and a7558a );
a7567a <=( A167 and A170 );
a7571a <=( A265 and A202 );
a7572a <=( (not A166) and a7571a );
a7573a <=( a7572a and a7567a );
a7576a <=( A269 and (not A266) );
a7580a <=( (not A302) and (not A301) );
a7581a <=( (not A300) and a7580a );
a7582a <=( a7581a and a7576a );
a7585a <=( A167 and A170 );
a7589a <=( A265 and A202 );
a7590a <=( (not A166) and a7589a );
a7591a <=( a7590a and a7585a );
a7594a <=( A269 and (not A266) );
a7598a <=( (not A301) and (not A299) );
a7599a <=( (not A298) and a7598a );
a7600a <=( a7599a and a7594a );
a7603a <=( A167 and A170 );
a7607a <=( (not A202) and (not A201) );
a7608a <=( (not A166) and a7607a );
a7609a <=( a7608a and a7603a );
a7612a <=( (not A267) and (not A203) );
a7616a <=( A301 and (not A269) );
a7617a <=( (not A268) and a7616a );
a7618a <=( a7617a and a7612a );
a7621a <=( A167 and A170 );
a7625a <=( (not A202) and (not A201) );
a7626a <=( (not A166) and a7625a );
a7627a <=( a7626a and a7621a );
a7630a <=( (not A265) and (not A203) );
a7634a <=( A301 and (not A268) );
a7635a <=( (not A266) and a7634a );
a7636a <=( a7635a and a7630a );
a7639a <=( A167 and A170 );
a7643a <=( A201 and A199 );
a7644a <=( (not A166) and a7643a );
a7645a <=( a7644a and a7639a );
a7648a <=( A298 and A268 );
a7652a <=( (not A301) and (not A300) );
a7653a <=( A299 and a7652a );
a7654a <=( a7653a and a7648a );
a7657a <=( A167 and A170 );
a7661a <=( A201 and A199 );
a7662a <=( (not A166) and a7661a );
a7663a <=( a7662a and a7657a );
a7666a <=( A267 and A265 );
a7670a <=( (not A302) and (not A301) );
a7671a <=( (not A300) and a7670a );
a7672a <=( a7671a and a7666a );
a7675a <=( A167 and A170 );
a7679a <=( A201 and A199 );
a7680a <=( (not A166) and a7679a );
a7681a <=( a7680a and a7675a );
a7684a <=( A267 and A265 );
a7688a <=( (not A301) and (not A299) );
a7689a <=( (not A298) and a7688a );
a7690a <=( a7689a and a7684a );
a7693a <=( A167 and A170 );
a7697a <=( A201 and A199 );
a7698a <=( (not A166) and a7697a );
a7699a <=( a7698a and a7693a );
a7702a <=( A267 and A266 );
a7706a <=( (not A302) and (not A301) );
a7707a <=( (not A300) and a7706a );
a7708a <=( a7707a and a7702a );
a7711a <=( A167 and A170 );
a7715a <=( A201 and A199 );
a7716a <=( (not A166) and a7715a );
a7717a <=( a7716a and a7711a );
a7720a <=( A267 and A266 );
a7724a <=( (not A301) and (not A299) );
a7725a <=( (not A298) and a7724a );
a7726a <=( a7725a and a7720a );
a7729a <=( A167 and A170 );
a7733a <=( A201 and A200 );
a7734a <=( (not A166) and a7733a );
a7735a <=( a7734a and a7729a );
a7738a <=( A298 and A268 );
a7742a <=( (not A301) and (not A300) );
a7743a <=( A299 and a7742a );
a7744a <=( a7743a and a7738a );
a7747a <=( A167 and A170 );
a7751a <=( A201 and A200 );
a7752a <=( (not A166) and a7751a );
a7753a <=( a7752a and a7747a );
a7756a <=( A267 and A265 );
a7760a <=( (not A302) and (not A301) );
a7761a <=( (not A300) and a7760a );
a7762a <=( a7761a and a7756a );
a7765a <=( A167 and A170 );
a7769a <=( A201 and A200 );
a7770a <=( (not A166) and a7769a );
a7771a <=( a7770a and a7765a );
a7774a <=( A267 and A265 );
a7778a <=( (not A301) and (not A299) );
a7779a <=( (not A298) and a7778a );
a7780a <=( a7779a and a7774a );
a7783a <=( A167 and A170 );
a7787a <=( A201 and A200 );
a7788a <=( (not A166) and a7787a );
a7789a <=( a7788a and a7783a );
a7792a <=( A267 and A266 );
a7796a <=( (not A302) and (not A301) );
a7797a <=( (not A300) and a7796a );
a7798a <=( a7797a and a7792a );
a7801a <=( A167 and A170 );
a7805a <=( A201 and A200 );
a7806a <=( (not A166) and a7805a );
a7807a <=( a7806a and a7801a );
a7810a <=( A267 and A266 );
a7814a <=( (not A301) and (not A299) );
a7815a <=( (not A298) and a7814a );
a7816a <=( a7815a and a7810a );
a7819a <=( A167 and A170 );
a7823a <=( A200 and (not A199) );
a7824a <=( (not A166) and a7823a );
a7825a <=( a7824a and a7819a );
a7828a <=( A268 and A203 );
a7832a <=( (not A302) and (not A301) );
a7833a <=( (not A300) and a7832a );
a7834a <=( a7833a and a7828a );
a7837a <=( A167 and A170 );
a7841a <=( A200 and (not A199) );
a7842a <=( (not A166) and a7841a );
a7843a <=( a7842a and a7837a );
a7846a <=( A268 and A203 );
a7850a <=( (not A301) and (not A299) );
a7851a <=( (not A298) and a7850a );
a7852a <=( a7851a and a7846a );
a7855a <=( A167 and A170 );
a7859a <=( (not A200) and A199 );
a7860a <=( (not A166) and a7859a );
a7861a <=( a7860a and a7855a );
a7864a <=( A268 and A203 );
a7868a <=( (not A302) and (not A301) );
a7869a <=( (not A300) and a7868a );
a7870a <=( a7869a and a7864a );
a7873a <=( A167 and A170 );
a7877a <=( (not A200) and A199 );
a7878a <=( (not A166) and a7877a );
a7879a <=( a7878a and a7873a );
a7882a <=( A268 and A203 );
a7886a <=( (not A301) and (not A299) );
a7887a <=( (not A298) and a7886a );
a7888a <=( a7887a and a7882a );
a7891a <=( A167 and A170 );
a7895a <=( (not A200) and (not A199) );
a7896a <=( (not A166) and a7895a );
a7897a <=( a7896a and a7891a );
a7900a <=( (not A267) and (not A202) );
a7904a <=( A301 and (not A269) );
a7905a <=( (not A268) and a7904a );
a7906a <=( a7905a and a7900a );
a7909a <=( A167 and A170 );
a7913a <=( (not A200) and (not A199) );
a7914a <=( (not A166) and a7913a );
a7915a <=( a7914a and a7909a );
a7918a <=( (not A265) and (not A202) );
a7922a <=( A301 and (not A268) );
a7923a <=( (not A266) and a7922a );
a7924a <=( a7923a and a7918a );
a7927a <=( (not A167) and A170 );
a7931a <=( A265 and A202 );
a7932a <=( A166 and a7931a );
a7933a <=( a7932a and a7927a );
a7936a <=( A298 and A267 );
a7940a <=( (not A301) and (not A300) );
a7941a <=( A299 and a7940a );
a7942a <=( a7941a and a7936a );
a7945a <=( (not A167) and A170 );
a7949a <=( A266 and A202 );
a7950a <=( A166 and a7949a );
a7951a <=( a7950a and a7945a );
a7954a <=( A298 and A267 );
a7958a <=( (not A301) and (not A300) );
a7959a <=( A299 and a7958a );
a7960a <=( a7959a and a7954a );
a7963a <=( (not A167) and A170 );
a7967a <=( (not A265) and A202 );
a7968a <=( A166 and a7967a );
a7969a <=( a7968a and a7963a );
a7972a <=( A269 and A266 );
a7976a <=( (not A302) and (not A301) );
a7977a <=( (not A300) and a7976a );
a7978a <=( a7977a and a7972a );
a7981a <=( (not A167) and A170 );
a7985a <=( (not A265) and A202 );
a7986a <=( A166 and a7985a );
a7987a <=( a7986a and a7981a );
a7990a <=( A269 and A266 );
a7994a <=( (not A301) and (not A299) );
a7995a <=( (not A298) and a7994a );
a7996a <=( a7995a and a7990a );
a7999a <=( (not A167) and A170 );
a8003a <=( A265 and A202 );
a8004a <=( A166 and a8003a );
a8005a <=( a8004a and a7999a );
a8008a <=( A269 and (not A266) );
a8012a <=( (not A302) and (not A301) );
a8013a <=( (not A300) and a8012a );
a8014a <=( a8013a and a8008a );
a8017a <=( (not A167) and A170 );
a8021a <=( A265 and A202 );
a8022a <=( A166 and a8021a );
a8023a <=( a8022a and a8017a );
a8026a <=( A269 and (not A266) );
a8030a <=( (not A301) and (not A299) );
a8031a <=( (not A298) and a8030a );
a8032a <=( a8031a and a8026a );
a8035a <=( (not A167) and A170 );
a8039a <=( (not A202) and (not A201) );
a8040a <=( A166 and a8039a );
a8041a <=( a8040a and a8035a );
a8044a <=( (not A267) and (not A203) );
a8048a <=( A301 and (not A269) );
a8049a <=( (not A268) and a8048a );
a8050a <=( a8049a and a8044a );
a8053a <=( (not A167) and A170 );
a8057a <=( (not A202) and (not A201) );
a8058a <=( A166 and a8057a );
a8059a <=( a8058a and a8053a );
a8062a <=( (not A265) and (not A203) );
a8066a <=( A301 and (not A268) );
a8067a <=( (not A266) and a8066a );
a8068a <=( a8067a and a8062a );
a8071a <=( (not A167) and A170 );
a8075a <=( A201 and A199 );
a8076a <=( A166 and a8075a );
a8077a <=( a8076a and a8071a );
a8080a <=( A298 and A268 );
a8084a <=( (not A301) and (not A300) );
a8085a <=( A299 and a8084a );
a8086a <=( a8085a and a8080a );
a8089a <=( (not A167) and A170 );
a8093a <=( A201 and A199 );
a8094a <=( A166 and a8093a );
a8095a <=( a8094a and a8089a );
a8098a <=( A267 and A265 );
a8102a <=( (not A302) and (not A301) );
a8103a <=( (not A300) and a8102a );
a8104a <=( a8103a and a8098a );
a8107a <=( (not A167) and A170 );
a8111a <=( A201 and A199 );
a8112a <=( A166 and a8111a );
a8113a <=( a8112a and a8107a );
a8116a <=( A267 and A265 );
a8120a <=( (not A301) and (not A299) );
a8121a <=( (not A298) and a8120a );
a8122a <=( a8121a and a8116a );
a8125a <=( (not A167) and A170 );
a8129a <=( A201 and A199 );
a8130a <=( A166 and a8129a );
a8131a <=( a8130a and a8125a );
a8134a <=( A267 and A266 );
a8138a <=( (not A302) and (not A301) );
a8139a <=( (not A300) and a8138a );
a8140a <=( a8139a and a8134a );
a8143a <=( (not A167) and A170 );
a8147a <=( A201 and A199 );
a8148a <=( A166 and a8147a );
a8149a <=( a8148a and a8143a );
a8152a <=( A267 and A266 );
a8156a <=( (not A301) and (not A299) );
a8157a <=( (not A298) and a8156a );
a8158a <=( a8157a and a8152a );
a8161a <=( (not A167) and A170 );
a8165a <=( A201 and A200 );
a8166a <=( A166 and a8165a );
a8167a <=( a8166a and a8161a );
a8170a <=( A298 and A268 );
a8174a <=( (not A301) and (not A300) );
a8175a <=( A299 and a8174a );
a8176a <=( a8175a and a8170a );
a8179a <=( (not A167) and A170 );
a8183a <=( A201 and A200 );
a8184a <=( A166 and a8183a );
a8185a <=( a8184a and a8179a );
a8188a <=( A267 and A265 );
a8192a <=( (not A302) and (not A301) );
a8193a <=( (not A300) and a8192a );
a8194a <=( a8193a and a8188a );
a8197a <=( (not A167) and A170 );
a8201a <=( A201 and A200 );
a8202a <=( A166 and a8201a );
a8203a <=( a8202a and a8197a );
a8206a <=( A267 and A265 );
a8210a <=( (not A301) and (not A299) );
a8211a <=( (not A298) and a8210a );
a8212a <=( a8211a and a8206a );
a8215a <=( (not A167) and A170 );
a8219a <=( A201 and A200 );
a8220a <=( A166 and a8219a );
a8221a <=( a8220a and a8215a );
a8224a <=( A267 and A266 );
a8228a <=( (not A302) and (not A301) );
a8229a <=( (not A300) and a8228a );
a8230a <=( a8229a and a8224a );
a8233a <=( (not A167) and A170 );
a8237a <=( A201 and A200 );
a8238a <=( A166 and a8237a );
a8239a <=( a8238a and a8233a );
a8242a <=( A267 and A266 );
a8246a <=( (not A301) and (not A299) );
a8247a <=( (not A298) and a8246a );
a8248a <=( a8247a and a8242a );
a8251a <=( (not A167) and A170 );
a8255a <=( A200 and (not A199) );
a8256a <=( A166 and a8255a );
a8257a <=( a8256a and a8251a );
a8260a <=( A268 and A203 );
a8264a <=( (not A302) and (not A301) );
a8265a <=( (not A300) and a8264a );
a8266a <=( a8265a and a8260a );
a8269a <=( (not A167) and A170 );
a8273a <=( A200 and (not A199) );
a8274a <=( A166 and a8273a );
a8275a <=( a8274a and a8269a );
a8278a <=( A268 and A203 );
a8282a <=( (not A301) and (not A299) );
a8283a <=( (not A298) and a8282a );
a8284a <=( a8283a and a8278a );
a8287a <=( (not A167) and A170 );
a8291a <=( (not A200) and A199 );
a8292a <=( A166 and a8291a );
a8293a <=( a8292a and a8287a );
a8296a <=( A268 and A203 );
a8300a <=( (not A302) and (not A301) );
a8301a <=( (not A300) and a8300a );
a8302a <=( a8301a and a8296a );
a8305a <=( (not A167) and A170 );
a8309a <=( (not A200) and A199 );
a8310a <=( A166 and a8309a );
a8311a <=( a8310a and a8305a );
a8314a <=( A268 and A203 );
a8318a <=( (not A301) and (not A299) );
a8319a <=( (not A298) and a8318a );
a8320a <=( a8319a and a8314a );
a8323a <=( (not A167) and A170 );
a8327a <=( (not A200) and (not A199) );
a8328a <=( A166 and a8327a );
a8329a <=( a8328a and a8323a );
a8332a <=( (not A267) and (not A202) );
a8336a <=( A301 and (not A269) );
a8337a <=( (not A268) and a8336a );
a8338a <=( a8337a and a8332a );
a8341a <=( (not A167) and A170 );
a8345a <=( (not A200) and (not A199) );
a8346a <=( A166 and a8345a );
a8347a <=( a8346a and a8341a );
a8350a <=( (not A265) and (not A202) );
a8354a <=( A301 and (not A268) );
a8355a <=( (not A266) and a8354a );
a8356a <=( a8355a and a8350a );
a8359a <=( (not A201) and A169 );
a8363a <=( (not A267) and (not A203) );
a8364a <=( (not A202) and a8363a );
a8365a <=( a8364a and a8359a );
a8368a <=( (not A269) and (not A268) );
a8372a <=( A302 and (not A299) );
a8373a <=( A298 and a8372a );
a8374a <=( a8373a and a8368a );
a8377a <=( (not A201) and A169 );
a8381a <=( (not A267) and (not A203) );
a8382a <=( (not A202) and a8381a );
a8383a <=( a8382a and a8377a );
a8386a <=( (not A269) and (not A268) );
a8390a <=( A302 and A299 );
a8391a <=( (not A298) and a8390a );
a8392a <=( a8391a and a8386a );
a8395a <=( (not A201) and A169 );
a8399a <=( A265 and (not A203) );
a8400a <=( (not A202) and a8399a );
a8401a <=( a8400a and a8395a );
a8404a <=( (not A267) and A266 );
a8408a <=( A300 and A299 );
a8409a <=( (not A268) and a8408a );
a8410a <=( a8409a and a8404a );
a8413a <=( (not A201) and A169 );
a8417a <=( A265 and (not A203) );
a8418a <=( (not A202) and a8417a );
a8419a <=( a8418a and a8413a );
a8422a <=( (not A267) and A266 );
a8426a <=( A300 and A298 );
a8427a <=( (not A268) and a8426a );
a8428a <=( a8427a and a8422a );
a8431a <=( (not A201) and A169 );
a8435a <=( (not A265) and (not A203) );
a8436a <=( (not A202) and a8435a );
a8437a <=( a8436a and a8431a );
a8440a <=( (not A268) and (not A266) );
a8444a <=( A302 and (not A299) );
a8445a <=( A298 and a8444a );
a8446a <=( a8445a and a8440a );
a8449a <=( (not A201) and A169 );
a8453a <=( (not A265) and (not A203) );
a8454a <=( (not A202) and a8453a );
a8455a <=( a8454a and a8449a );
a8458a <=( (not A268) and (not A266) );
a8462a <=( A302 and A299 );
a8463a <=( (not A298) and a8462a );
a8464a <=( a8463a and a8458a );
a8467a <=( A199 and A169 );
a8471a <=( A266 and (not A265) );
a8472a <=( A201 and a8471a );
a8473a <=( a8472a and a8467a );
a8476a <=( A298 and A269 );
a8480a <=( (not A301) and (not A300) );
a8481a <=( A299 and a8480a );
a8482a <=( a8481a and a8476a );
a8485a <=( A199 and A169 );
a8489a <=( (not A266) and A265 );
a8490a <=( A201 and a8489a );
a8491a <=( a8490a and a8485a );
a8494a <=( A298 and A269 );
a8498a <=( (not A301) and (not A300) );
a8499a <=( A299 and a8498a );
a8500a <=( a8499a and a8494a );
a8503a <=( A200 and A169 );
a8507a <=( A266 and (not A265) );
a8508a <=( A201 and a8507a );
a8509a <=( a8508a and a8503a );
a8512a <=( A298 and A269 );
a8516a <=( (not A301) and (not A300) );
a8517a <=( A299 and a8516a );
a8518a <=( a8517a and a8512a );
a8521a <=( A200 and A169 );
a8525a <=( (not A266) and A265 );
a8526a <=( A201 and a8525a );
a8527a <=( a8526a and a8521a );
a8530a <=( A298 and A269 );
a8534a <=( (not A301) and (not A300) );
a8535a <=( A299 and a8534a );
a8536a <=( a8535a and a8530a );
a8539a <=( A199 and A169 );
a8543a <=( (not A202) and (not A201) );
a8544a <=( A200 and a8543a );
a8545a <=( a8544a and a8539a );
a8548a <=( (not A268) and (not A267) );
a8552a <=( A300 and A299 );
a8553a <=( (not A269) and a8552a );
a8554a <=( a8553a and a8548a );
a8557a <=( A199 and A169 );
a8561a <=( (not A202) and (not A201) );
a8562a <=( A200 and a8561a );
a8563a <=( a8562a and a8557a );
a8566a <=( (not A268) and (not A267) );
a8570a <=( A300 and A298 );
a8571a <=( (not A269) and a8570a );
a8572a <=( a8571a and a8566a );
a8575a <=( A199 and A169 );
a8579a <=( (not A202) and (not A201) );
a8580a <=( A200 and a8579a );
a8581a <=( a8580a and a8575a );
a8584a <=( A266 and A265 );
a8588a <=( A301 and (not A268) );
a8589a <=( (not A267) and a8588a );
a8590a <=( a8589a and a8584a );
a8593a <=( A199 and A169 );
a8597a <=( (not A202) and (not A201) );
a8598a <=( A200 and a8597a );
a8599a <=( a8598a and a8593a );
a8602a <=( (not A266) and (not A265) );
a8606a <=( A300 and A299 );
a8607a <=( (not A268) and a8606a );
a8608a <=( a8607a and a8602a );
a8611a <=( A199 and A169 );
a8615a <=( (not A202) and (not A201) );
a8616a <=( A200 and a8615a );
a8617a <=( a8616a and a8611a );
a8620a <=( (not A266) and (not A265) );
a8624a <=( A300 and A298 );
a8625a <=( (not A268) and a8624a );
a8626a <=( a8625a and a8620a );
a8629a <=( (not A199) and A169 );
a8633a <=( A265 and A203 );
a8634a <=( A200 and a8633a );
a8635a <=( a8634a and a8629a );
a8638a <=( A298 and A267 );
a8642a <=( (not A301) and (not A300) );
a8643a <=( A299 and a8642a );
a8644a <=( a8643a and a8638a );
a8647a <=( (not A199) and A169 );
a8651a <=( A266 and A203 );
a8652a <=( A200 and a8651a );
a8653a <=( a8652a and a8647a );
a8656a <=( A298 and A267 );
a8660a <=( (not A301) and (not A300) );
a8661a <=( A299 and a8660a );
a8662a <=( a8661a and a8656a );
a8665a <=( (not A199) and A169 );
a8669a <=( (not A265) and A203 );
a8670a <=( A200 and a8669a );
a8671a <=( a8670a and a8665a );
a8674a <=( A269 and A266 );
a8678a <=( (not A302) and (not A301) );
a8679a <=( (not A300) and a8678a );
a8680a <=( a8679a and a8674a );
a8683a <=( (not A199) and A169 );
a8687a <=( (not A265) and A203 );
a8688a <=( A200 and a8687a );
a8689a <=( a8688a and a8683a );
a8692a <=( A269 and A266 );
a8696a <=( (not A301) and (not A299) );
a8697a <=( (not A298) and a8696a );
a8698a <=( a8697a and a8692a );
a8701a <=( (not A199) and A169 );
a8705a <=( A265 and A203 );
a8706a <=( A200 and a8705a );
a8707a <=( a8706a and a8701a );
a8710a <=( A269 and (not A266) );
a8714a <=( (not A302) and (not A301) );
a8715a <=( (not A300) and a8714a );
a8716a <=( a8715a and a8710a );
a8719a <=( (not A199) and A169 );
a8723a <=( A265 and A203 );
a8724a <=( A200 and a8723a );
a8725a <=( a8724a and a8719a );
a8728a <=( A269 and (not A266) );
a8732a <=( (not A301) and (not A299) );
a8733a <=( (not A298) and a8732a );
a8734a <=( a8733a and a8728a );
a8737a <=( A199 and A169 );
a8741a <=( A265 and A203 );
a8742a <=( (not A200) and a8741a );
a8743a <=( a8742a and a8737a );
a8746a <=( A298 and A267 );
a8750a <=( (not A301) and (not A300) );
a8751a <=( A299 and a8750a );
a8752a <=( a8751a and a8746a );
a8755a <=( A199 and A169 );
a8759a <=( A266 and A203 );
a8760a <=( (not A200) and a8759a );
a8761a <=( a8760a and a8755a );
a8764a <=( A298 and A267 );
a8768a <=( (not A301) and (not A300) );
a8769a <=( A299 and a8768a );
a8770a <=( a8769a and a8764a );
a8773a <=( A199 and A169 );
a8777a <=( (not A265) and A203 );
a8778a <=( (not A200) and a8777a );
a8779a <=( a8778a and a8773a );
a8782a <=( A269 and A266 );
a8786a <=( (not A302) and (not A301) );
a8787a <=( (not A300) and a8786a );
a8788a <=( a8787a and a8782a );
a8791a <=( A199 and A169 );
a8795a <=( (not A265) and A203 );
a8796a <=( (not A200) and a8795a );
a8797a <=( a8796a and a8791a );
a8800a <=( A269 and A266 );
a8804a <=( (not A301) and (not A299) );
a8805a <=( (not A298) and a8804a );
a8806a <=( a8805a and a8800a );
a8809a <=( A199 and A169 );
a8813a <=( A265 and A203 );
a8814a <=( (not A200) and a8813a );
a8815a <=( a8814a and a8809a );
a8818a <=( A269 and (not A266) );
a8822a <=( (not A302) and (not A301) );
a8823a <=( (not A300) and a8822a );
a8824a <=( a8823a and a8818a );
a8827a <=( A199 and A169 );
a8831a <=( A265 and A203 );
a8832a <=( (not A200) and a8831a );
a8833a <=( a8832a and a8827a );
a8836a <=( A269 and (not A266) );
a8840a <=( (not A301) and (not A299) );
a8841a <=( (not A298) and a8840a );
a8842a <=( a8841a and a8836a );
a8845a <=( (not A199) and A169 );
a8849a <=( (not A267) and (not A202) );
a8850a <=( (not A200) and a8849a );
a8851a <=( a8850a and a8845a );
a8854a <=( (not A269) and (not A268) );
a8858a <=( A302 and (not A299) );
a8859a <=( A298 and a8858a );
a8860a <=( a8859a and a8854a );
a8863a <=( (not A199) and A169 );
a8867a <=( (not A267) and (not A202) );
a8868a <=( (not A200) and a8867a );
a8869a <=( a8868a and a8863a );
a8872a <=( (not A269) and (not A268) );
a8876a <=( A302 and A299 );
a8877a <=( (not A298) and a8876a );
a8878a <=( a8877a and a8872a );
a8881a <=( (not A199) and A169 );
a8885a <=( A265 and (not A202) );
a8886a <=( (not A200) and a8885a );
a8887a <=( a8886a and a8881a );
a8890a <=( (not A267) and A266 );
a8894a <=( A300 and A299 );
a8895a <=( (not A268) and a8894a );
a8896a <=( a8895a and a8890a );
a8899a <=( (not A199) and A169 );
a8903a <=( A265 and (not A202) );
a8904a <=( (not A200) and a8903a );
a8905a <=( a8904a and a8899a );
a8908a <=( (not A267) and A266 );
a8912a <=( A300 and A298 );
a8913a <=( (not A268) and a8912a );
a8914a <=( a8913a and a8908a );
a8917a <=( (not A199) and A169 );
a8921a <=( (not A265) and (not A202) );
a8922a <=( (not A200) and a8921a );
a8923a <=( a8922a and a8917a );
a8926a <=( (not A268) and (not A266) );
a8930a <=( A302 and (not A299) );
a8931a <=( A298 and a8930a );
a8932a <=( a8931a and a8926a );
a8935a <=( (not A199) and A169 );
a8939a <=( (not A265) and (not A202) );
a8940a <=( (not A200) and a8939a );
a8941a <=( a8940a and a8935a );
a8944a <=( (not A268) and (not A266) );
a8948a <=( A302 and A299 );
a8949a <=( (not A298) and a8948a );
a8950a <=( a8949a and a8944a );
a8953a <=( (not A167) and (not A169) );
a8957a <=( (not A267) and A202 );
a8958a <=( (not A166) and a8957a );
a8959a <=( a8958a and a8953a );
a8962a <=( (not A269) and (not A268) );
a8966a <=( A302 and (not A299) );
a8967a <=( A298 and a8966a );
a8968a <=( a8967a and a8962a );
a8971a <=( (not A167) and (not A169) );
a8975a <=( (not A267) and A202 );
a8976a <=( (not A166) and a8975a );
a8977a <=( a8976a and a8971a );
a8980a <=( (not A269) and (not A268) );
a8984a <=( A302 and A299 );
a8985a <=( (not A298) and a8984a );
a8986a <=( a8985a and a8980a );
a8989a <=( (not A167) and (not A169) );
a8993a <=( A265 and A202 );
a8994a <=( (not A166) and a8993a );
a8995a <=( a8994a and a8989a );
a8998a <=( (not A267) and A266 );
a9002a <=( A300 and A299 );
a9003a <=( (not A268) and a9002a );
a9004a <=( a9003a and a8998a );
a9007a <=( (not A167) and (not A169) );
a9011a <=( A265 and A202 );
a9012a <=( (not A166) and a9011a );
a9013a <=( a9012a and a9007a );
a9016a <=( (not A267) and A266 );
a9020a <=( A300 and A298 );
a9021a <=( (not A268) and a9020a );
a9022a <=( a9021a and a9016a );
a9025a <=( (not A167) and (not A169) );
a9029a <=( (not A265) and A202 );
a9030a <=( (not A166) and a9029a );
a9031a <=( a9030a and a9025a );
a9034a <=( (not A268) and (not A266) );
a9038a <=( A302 and (not A299) );
a9039a <=( A298 and a9038a );
a9040a <=( a9039a and a9034a );
a9043a <=( (not A167) and (not A169) );
a9047a <=( (not A265) and A202 );
a9048a <=( (not A166) and a9047a );
a9049a <=( a9048a and a9043a );
a9052a <=( (not A268) and (not A266) );
a9056a <=( A302 and A299 );
a9057a <=( (not A298) and a9056a );
a9058a <=( a9057a and a9052a );
a9061a <=( (not A167) and (not A169) );
a9065a <=( (not A202) and (not A201) );
a9066a <=( (not A166) and a9065a );
a9067a <=( a9066a and a9061a );
a9070a <=( A268 and (not A203) );
a9074a <=( (not A302) and (not A301) );
a9075a <=( (not A300) and a9074a );
a9076a <=( a9075a and a9070a );
a9079a <=( (not A167) and (not A169) );
a9083a <=( (not A202) and (not A201) );
a9084a <=( (not A166) and a9083a );
a9085a <=( a9084a and a9079a );
a9088a <=( A268 and (not A203) );
a9092a <=( (not A301) and (not A299) );
a9093a <=( (not A298) and a9092a );
a9094a <=( a9093a and a9088a );
a9097a <=( (not A167) and (not A169) );
a9101a <=( A201 and A199 );
a9102a <=( (not A166) and a9101a );
a9103a <=( a9102a and a9097a );
a9106a <=( (not A268) and (not A267) );
a9110a <=( A300 and A299 );
a9111a <=( (not A269) and a9110a );
a9112a <=( a9111a and a9106a );
a9115a <=( (not A167) and (not A169) );
a9119a <=( A201 and A199 );
a9120a <=( (not A166) and a9119a );
a9121a <=( a9120a and a9115a );
a9124a <=( (not A268) and (not A267) );
a9128a <=( A300 and A298 );
a9129a <=( (not A269) and a9128a );
a9130a <=( a9129a and a9124a );
a9133a <=( (not A167) and (not A169) );
a9137a <=( A201 and A199 );
a9138a <=( (not A166) and a9137a );
a9139a <=( a9138a and a9133a );
a9142a <=( A266 and A265 );
a9146a <=( A301 and (not A268) );
a9147a <=( (not A267) and a9146a );
a9148a <=( a9147a and a9142a );
a9151a <=( (not A167) and (not A169) );
a9155a <=( A201 and A199 );
a9156a <=( (not A166) and a9155a );
a9157a <=( a9156a and a9151a );
a9160a <=( (not A266) and (not A265) );
a9164a <=( A300 and A299 );
a9165a <=( (not A268) and a9164a );
a9166a <=( a9165a and a9160a );
a9169a <=( (not A167) and (not A169) );
a9173a <=( A201 and A199 );
a9174a <=( (not A166) and a9173a );
a9175a <=( a9174a and a9169a );
a9178a <=( (not A266) and (not A265) );
a9182a <=( A300 and A298 );
a9183a <=( (not A268) and a9182a );
a9184a <=( a9183a and a9178a );
a9187a <=( (not A167) and (not A169) );
a9191a <=( A201 and A200 );
a9192a <=( (not A166) and a9191a );
a9193a <=( a9192a and a9187a );
a9196a <=( (not A268) and (not A267) );
a9200a <=( A300 and A299 );
a9201a <=( (not A269) and a9200a );
a9202a <=( a9201a and a9196a );
a9205a <=( (not A167) and (not A169) );
a9209a <=( A201 and A200 );
a9210a <=( (not A166) and a9209a );
a9211a <=( a9210a and a9205a );
a9214a <=( (not A268) and (not A267) );
a9218a <=( A300 and A298 );
a9219a <=( (not A269) and a9218a );
a9220a <=( a9219a and a9214a );
a9223a <=( (not A167) and (not A169) );
a9227a <=( A201 and A200 );
a9228a <=( (not A166) and a9227a );
a9229a <=( a9228a and a9223a );
a9232a <=( A266 and A265 );
a9236a <=( A301 and (not A268) );
a9237a <=( (not A267) and a9236a );
a9238a <=( a9237a and a9232a );
a9241a <=( (not A167) and (not A169) );
a9245a <=( A201 and A200 );
a9246a <=( (not A166) and a9245a );
a9247a <=( a9246a and a9241a );
a9250a <=( (not A266) and (not A265) );
a9254a <=( A300 and A299 );
a9255a <=( (not A268) and a9254a );
a9256a <=( a9255a and a9250a );
a9259a <=( (not A167) and (not A169) );
a9263a <=( A201 and A200 );
a9264a <=( (not A166) and a9263a );
a9265a <=( a9264a and a9259a );
a9268a <=( (not A266) and (not A265) );
a9272a <=( A300 and A298 );
a9273a <=( (not A268) and a9272a );
a9274a <=( a9273a and a9268a );
a9277a <=( (not A167) and (not A169) );
a9281a <=( A200 and (not A199) );
a9282a <=( (not A166) and a9281a );
a9283a <=( a9282a and a9277a );
a9286a <=( (not A267) and A203 );
a9290a <=( A301 and (not A269) );
a9291a <=( (not A268) and a9290a );
a9292a <=( a9291a and a9286a );
a9295a <=( (not A167) and (not A169) );
a9299a <=( A200 and (not A199) );
a9300a <=( (not A166) and a9299a );
a9301a <=( a9300a and a9295a );
a9304a <=( (not A265) and A203 );
a9308a <=( A301 and (not A268) );
a9309a <=( (not A266) and a9308a );
a9310a <=( a9309a and a9304a );
a9313a <=( (not A167) and (not A169) );
a9317a <=( (not A200) and A199 );
a9318a <=( (not A166) and a9317a );
a9319a <=( a9318a and a9313a );
a9322a <=( (not A267) and A203 );
a9326a <=( A301 and (not A269) );
a9327a <=( (not A268) and a9326a );
a9328a <=( a9327a and a9322a );
a9331a <=( (not A167) and (not A169) );
a9335a <=( (not A200) and A199 );
a9336a <=( (not A166) and a9335a );
a9337a <=( a9336a and a9331a );
a9340a <=( (not A265) and A203 );
a9344a <=( A301 and (not A268) );
a9345a <=( (not A266) and a9344a );
a9346a <=( a9345a and a9340a );
a9349a <=( (not A167) and (not A169) );
a9353a <=( (not A200) and (not A199) );
a9354a <=( (not A166) and a9353a );
a9355a <=( a9354a and a9349a );
a9358a <=( A268 and (not A202) );
a9362a <=( (not A302) and (not A301) );
a9363a <=( (not A300) and a9362a );
a9364a <=( a9363a and a9358a );
a9367a <=( (not A167) and (not A169) );
a9371a <=( (not A200) and (not A199) );
a9372a <=( (not A166) and a9371a );
a9373a <=( a9372a and a9367a );
a9376a <=( A268 and (not A202) );
a9380a <=( (not A301) and (not A299) );
a9381a <=( (not A298) and a9380a );
a9382a <=( a9381a and a9376a );
a9385a <=( (not A168) and (not A169) );
a9389a <=( A202 and A166 );
a9390a <=( A167 and a9389a );
a9391a <=( a9390a and a9385a );
a9394a <=( (not A268) and (not A267) );
a9398a <=( A300 and A299 );
a9399a <=( (not A269) and a9398a );
a9400a <=( a9399a and a9394a );
a9403a <=( (not A168) and (not A169) );
a9407a <=( A202 and A166 );
a9408a <=( A167 and a9407a );
a9409a <=( a9408a and a9403a );
a9412a <=( (not A268) and (not A267) );
a9416a <=( A300 and A298 );
a9417a <=( (not A269) and a9416a );
a9418a <=( a9417a and a9412a );
a9421a <=( (not A168) and (not A169) );
a9425a <=( A202 and A166 );
a9426a <=( A167 and a9425a );
a9427a <=( a9426a and a9421a );
a9430a <=( A266 and A265 );
a9434a <=( A301 and (not A268) );
a9435a <=( (not A267) and a9434a );
a9436a <=( a9435a and a9430a );
a9439a <=( (not A168) and (not A169) );
a9443a <=( A202 and A166 );
a9444a <=( A167 and a9443a );
a9445a <=( a9444a and a9439a );
a9448a <=( (not A266) and (not A265) );
a9452a <=( A300 and A299 );
a9453a <=( (not A268) and a9452a );
a9454a <=( a9453a and a9448a );
a9457a <=( (not A168) and (not A169) );
a9461a <=( A202 and A166 );
a9462a <=( A167 and a9461a );
a9463a <=( a9462a and a9457a );
a9466a <=( (not A266) and (not A265) );
a9470a <=( A300 and A298 );
a9471a <=( (not A268) and a9470a );
a9472a <=( a9471a and a9466a );
a9475a <=( (not A168) and (not A169) );
a9479a <=( A199 and A166 );
a9480a <=( A167 and a9479a );
a9481a <=( a9480a and a9475a );
a9484a <=( (not A267) and A201 );
a9488a <=( A301 and (not A269) );
a9489a <=( (not A268) and a9488a );
a9490a <=( a9489a and a9484a );
a9493a <=( (not A168) and (not A169) );
a9497a <=( A199 and A166 );
a9498a <=( A167 and a9497a );
a9499a <=( a9498a and a9493a );
a9502a <=( (not A265) and A201 );
a9506a <=( A301 and (not A268) );
a9507a <=( (not A266) and a9506a );
a9508a <=( a9507a and a9502a );
a9511a <=( (not A168) and (not A169) );
a9515a <=( A200 and A166 );
a9516a <=( A167 and a9515a );
a9517a <=( a9516a and a9511a );
a9520a <=( (not A267) and A201 );
a9524a <=( A301 and (not A269) );
a9525a <=( (not A268) and a9524a );
a9526a <=( a9525a and a9520a );
a9529a <=( (not A168) and (not A169) );
a9533a <=( A200 and A166 );
a9534a <=( A167 and a9533a );
a9535a <=( a9534a and a9529a );
a9538a <=( (not A265) and A201 );
a9542a <=( A301 and (not A268) );
a9543a <=( (not A266) and a9542a );
a9544a <=( a9543a and a9538a );
a9547a <=( (not A169) and (not A170) );
a9551a <=( (not A267) and A202 );
a9552a <=( (not A168) and a9551a );
a9553a <=( a9552a and a9547a );
a9556a <=( (not A269) and (not A268) );
a9560a <=( A302 and (not A299) );
a9561a <=( A298 and a9560a );
a9562a <=( a9561a and a9556a );
a9565a <=( (not A169) and (not A170) );
a9569a <=( (not A267) and A202 );
a9570a <=( (not A168) and a9569a );
a9571a <=( a9570a and a9565a );
a9574a <=( (not A269) and (not A268) );
a9578a <=( A302 and A299 );
a9579a <=( (not A298) and a9578a );
a9580a <=( a9579a and a9574a );
a9583a <=( (not A169) and (not A170) );
a9587a <=( A265 and A202 );
a9588a <=( (not A168) and a9587a );
a9589a <=( a9588a and a9583a );
a9592a <=( (not A267) and A266 );
a9596a <=( A300 and A299 );
a9597a <=( (not A268) and a9596a );
a9598a <=( a9597a and a9592a );
a9601a <=( (not A169) and (not A170) );
a9605a <=( A265 and A202 );
a9606a <=( (not A168) and a9605a );
a9607a <=( a9606a and a9601a );
a9610a <=( (not A267) and A266 );
a9614a <=( A300 and A298 );
a9615a <=( (not A268) and a9614a );
a9616a <=( a9615a and a9610a );
a9619a <=( (not A169) and (not A170) );
a9623a <=( (not A265) and A202 );
a9624a <=( (not A168) and a9623a );
a9625a <=( a9624a and a9619a );
a9628a <=( (not A268) and (not A266) );
a9632a <=( A302 and (not A299) );
a9633a <=( A298 and a9632a );
a9634a <=( a9633a and a9628a );
a9637a <=( (not A169) and (not A170) );
a9641a <=( (not A265) and A202 );
a9642a <=( (not A168) and a9641a );
a9643a <=( a9642a and a9637a );
a9646a <=( (not A268) and (not A266) );
a9650a <=( A302 and A299 );
a9651a <=( (not A298) and a9650a );
a9652a <=( a9651a and a9646a );
a9655a <=( (not A169) and (not A170) );
a9659a <=( (not A202) and (not A201) );
a9660a <=( (not A168) and a9659a );
a9661a <=( a9660a and a9655a );
a9664a <=( A268 and (not A203) );
a9668a <=( (not A302) and (not A301) );
a9669a <=( (not A300) and a9668a );
a9670a <=( a9669a and a9664a );
a9673a <=( (not A169) and (not A170) );
a9677a <=( (not A202) and (not A201) );
a9678a <=( (not A168) and a9677a );
a9679a <=( a9678a and a9673a );
a9682a <=( A268 and (not A203) );
a9686a <=( (not A301) and (not A299) );
a9687a <=( (not A298) and a9686a );
a9688a <=( a9687a and a9682a );
a9691a <=( (not A169) and (not A170) );
a9695a <=( A201 and A199 );
a9696a <=( (not A168) and a9695a );
a9697a <=( a9696a and a9691a );
a9700a <=( (not A268) and (not A267) );
a9704a <=( A300 and A299 );
a9705a <=( (not A269) and a9704a );
a9706a <=( a9705a and a9700a );
a9709a <=( (not A169) and (not A170) );
a9713a <=( A201 and A199 );
a9714a <=( (not A168) and a9713a );
a9715a <=( a9714a and a9709a );
a9718a <=( (not A268) and (not A267) );
a9722a <=( A300 and A298 );
a9723a <=( (not A269) and a9722a );
a9724a <=( a9723a and a9718a );
a9727a <=( (not A169) and (not A170) );
a9731a <=( A201 and A199 );
a9732a <=( (not A168) and a9731a );
a9733a <=( a9732a and a9727a );
a9736a <=( A266 and A265 );
a9740a <=( A301 and (not A268) );
a9741a <=( (not A267) and a9740a );
a9742a <=( a9741a and a9736a );
a9745a <=( (not A169) and (not A170) );
a9749a <=( A201 and A199 );
a9750a <=( (not A168) and a9749a );
a9751a <=( a9750a and a9745a );
a9754a <=( (not A266) and (not A265) );
a9758a <=( A300 and A299 );
a9759a <=( (not A268) and a9758a );
a9760a <=( a9759a and a9754a );
a9763a <=( (not A169) and (not A170) );
a9767a <=( A201 and A199 );
a9768a <=( (not A168) and a9767a );
a9769a <=( a9768a and a9763a );
a9772a <=( (not A266) and (not A265) );
a9776a <=( A300 and A298 );
a9777a <=( (not A268) and a9776a );
a9778a <=( a9777a and a9772a );
a9781a <=( (not A169) and (not A170) );
a9785a <=( A201 and A200 );
a9786a <=( (not A168) and a9785a );
a9787a <=( a9786a and a9781a );
a9790a <=( (not A268) and (not A267) );
a9794a <=( A300 and A299 );
a9795a <=( (not A269) and a9794a );
a9796a <=( a9795a and a9790a );
a9799a <=( (not A169) and (not A170) );
a9803a <=( A201 and A200 );
a9804a <=( (not A168) and a9803a );
a9805a <=( a9804a and a9799a );
a9808a <=( (not A268) and (not A267) );
a9812a <=( A300 and A298 );
a9813a <=( (not A269) and a9812a );
a9814a <=( a9813a and a9808a );
a9817a <=( (not A169) and (not A170) );
a9821a <=( A201 and A200 );
a9822a <=( (not A168) and a9821a );
a9823a <=( a9822a and a9817a );
a9826a <=( A266 and A265 );
a9830a <=( A301 and (not A268) );
a9831a <=( (not A267) and a9830a );
a9832a <=( a9831a and a9826a );
a9835a <=( (not A169) and (not A170) );
a9839a <=( A201 and A200 );
a9840a <=( (not A168) and a9839a );
a9841a <=( a9840a and a9835a );
a9844a <=( (not A266) and (not A265) );
a9848a <=( A300 and A299 );
a9849a <=( (not A268) and a9848a );
a9850a <=( a9849a and a9844a );
a9853a <=( (not A169) and (not A170) );
a9857a <=( A201 and A200 );
a9858a <=( (not A168) and a9857a );
a9859a <=( a9858a and a9853a );
a9862a <=( (not A266) and (not A265) );
a9866a <=( A300 and A298 );
a9867a <=( (not A268) and a9866a );
a9868a <=( a9867a and a9862a );
a9871a <=( (not A169) and (not A170) );
a9875a <=( A200 and (not A199) );
a9876a <=( (not A168) and a9875a );
a9877a <=( a9876a and a9871a );
a9880a <=( (not A267) and A203 );
a9884a <=( A301 and (not A269) );
a9885a <=( (not A268) and a9884a );
a9886a <=( a9885a and a9880a );
a9889a <=( (not A169) and (not A170) );
a9893a <=( A200 and (not A199) );
a9894a <=( (not A168) and a9893a );
a9895a <=( a9894a and a9889a );
a9898a <=( (not A265) and A203 );
a9902a <=( A301 and (not A268) );
a9903a <=( (not A266) and a9902a );
a9904a <=( a9903a and a9898a );
a9907a <=( (not A169) and (not A170) );
a9911a <=( (not A200) and A199 );
a9912a <=( (not A168) and a9911a );
a9913a <=( a9912a and a9907a );
a9916a <=( (not A267) and A203 );
a9920a <=( A301 and (not A269) );
a9921a <=( (not A268) and a9920a );
a9922a <=( a9921a and a9916a );
a9925a <=( (not A169) and (not A170) );
a9929a <=( (not A200) and A199 );
a9930a <=( (not A168) and a9929a );
a9931a <=( a9930a and a9925a );
a9934a <=( (not A265) and A203 );
a9938a <=( A301 and (not A268) );
a9939a <=( (not A266) and a9938a );
a9940a <=( a9939a and a9934a );
a9943a <=( (not A169) and (not A170) );
a9947a <=( (not A200) and (not A199) );
a9948a <=( (not A168) and a9947a );
a9949a <=( a9948a and a9943a );
a9952a <=( A268 and (not A202) );
a9956a <=( (not A302) and (not A301) );
a9957a <=( (not A300) and a9956a );
a9958a <=( a9957a and a9952a );
a9961a <=( (not A169) and (not A170) );
a9965a <=( (not A200) and (not A199) );
a9966a <=( (not A168) and a9965a );
a9967a <=( a9966a and a9961a );
a9970a <=( A268 and (not A202) );
a9974a <=( (not A301) and (not A299) );
a9975a <=( (not A298) and a9974a );
a9976a <=( a9975a and a9970a );
a9979a <=( A166 and A168 );
a9983a <=( (not A203) and (not A202) );
a9984a <=( (not A201) and a9983a );
a9985a <=( a9984a and a9979a );
a9989a <=( (not A269) and (not A268) );
a9990a <=( (not A267) and a9989a );
a9994a <=( A302 and (not A299) );
a9995a <=( A298 and a9994a );
a9996a <=( a9995a and a9990a );
a9999a <=( A166 and A168 );
a10003a <=( (not A203) and (not A202) );
a10004a <=( (not A201) and a10003a );
a10005a <=( a10004a and a9999a );
a10009a <=( (not A269) and (not A268) );
a10010a <=( (not A267) and a10009a );
a10014a <=( A302 and A299 );
a10015a <=( (not A298) and a10014a );
a10016a <=( a10015a and a10010a );
a10019a <=( A166 and A168 );
a10023a <=( (not A203) and (not A202) );
a10024a <=( (not A201) and a10023a );
a10025a <=( a10024a and a10019a );
a10029a <=( (not A267) and A266 );
a10030a <=( A265 and a10029a );
a10034a <=( A300 and A299 );
a10035a <=( (not A268) and a10034a );
a10036a <=( a10035a and a10030a );
a10039a <=( A166 and A168 );
a10043a <=( (not A203) and (not A202) );
a10044a <=( (not A201) and a10043a );
a10045a <=( a10044a and a10039a );
a10049a <=( (not A267) and A266 );
a10050a <=( A265 and a10049a );
a10054a <=( A300 and A298 );
a10055a <=( (not A268) and a10054a );
a10056a <=( a10055a and a10050a );
a10059a <=( A166 and A168 );
a10063a <=( (not A203) and (not A202) );
a10064a <=( (not A201) and a10063a );
a10065a <=( a10064a and a10059a );
a10069a <=( (not A268) and (not A266) );
a10070a <=( (not A265) and a10069a );
a10074a <=( A302 and (not A299) );
a10075a <=( A298 and a10074a );
a10076a <=( a10075a and a10070a );
a10079a <=( A166 and A168 );
a10083a <=( (not A203) and (not A202) );
a10084a <=( (not A201) and a10083a );
a10085a <=( a10084a and a10079a );
a10089a <=( (not A268) and (not A266) );
a10090a <=( (not A265) and a10089a );
a10094a <=( A302 and A299 );
a10095a <=( (not A298) and a10094a );
a10096a <=( a10095a and a10090a );
a10099a <=( A166 and A168 );
a10103a <=( (not A265) and A201 );
a10104a <=( A199 and a10103a );
a10105a <=( a10104a and a10099a );
a10109a <=( A298 and A269 );
a10110a <=( A266 and a10109a );
a10114a <=( (not A301) and (not A300) );
a10115a <=( A299 and a10114a );
a10116a <=( a10115a and a10110a );
a10119a <=( A166 and A168 );
a10123a <=( A265 and A201 );
a10124a <=( A199 and a10123a );
a10125a <=( a10124a and a10119a );
a10129a <=( A298 and A269 );
a10130a <=( (not A266) and a10129a );
a10134a <=( (not A301) and (not A300) );
a10135a <=( A299 and a10134a );
a10136a <=( a10135a and a10130a );
a10139a <=( A166 and A168 );
a10143a <=( (not A265) and A201 );
a10144a <=( A200 and a10143a );
a10145a <=( a10144a and a10139a );
a10149a <=( A298 and A269 );
a10150a <=( A266 and a10149a );
a10154a <=( (not A301) and (not A300) );
a10155a <=( A299 and a10154a );
a10156a <=( a10155a and a10150a );
a10159a <=( A166 and A168 );
a10163a <=( A265 and A201 );
a10164a <=( A200 and a10163a );
a10165a <=( a10164a and a10159a );
a10169a <=( A298 and A269 );
a10170a <=( (not A266) and a10169a );
a10174a <=( (not A301) and (not A300) );
a10175a <=( A299 and a10174a );
a10176a <=( a10175a and a10170a );
a10179a <=( A166 and A168 );
a10183a <=( (not A201) and A200 );
a10184a <=( A199 and a10183a );
a10185a <=( a10184a and a10179a );
a10189a <=( (not A268) and (not A267) );
a10190a <=( (not A202) and a10189a );
a10194a <=( A300 and A299 );
a10195a <=( (not A269) and a10194a );
a10196a <=( a10195a and a10190a );
a10199a <=( A166 and A168 );
a10203a <=( (not A201) and A200 );
a10204a <=( A199 and a10203a );
a10205a <=( a10204a and a10199a );
a10209a <=( (not A268) and (not A267) );
a10210a <=( (not A202) and a10209a );
a10214a <=( A300 and A298 );
a10215a <=( (not A269) and a10214a );
a10216a <=( a10215a and a10210a );
a10219a <=( A166 and A168 );
a10223a <=( (not A201) and A200 );
a10224a <=( A199 and a10223a );
a10225a <=( a10224a and a10219a );
a10229a <=( A266 and A265 );
a10230a <=( (not A202) and a10229a );
a10234a <=( A301 and (not A268) );
a10235a <=( (not A267) and a10234a );
a10236a <=( a10235a and a10230a );
a10239a <=( A166 and A168 );
a10243a <=( (not A201) and A200 );
a10244a <=( A199 and a10243a );
a10245a <=( a10244a and a10239a );
a10249a <=( (not A266) and (not A265) );
a10250a <=( (not A202) and a10249a );
a10254a <=( A300 and A299 );
a10255a <=( (not A268) and a10254a );
a10256a <=( a10255a and a10250a );
a10259a <=( A166 and A168 );
a10263a <=( (not A201) and A200 );
a10264a <=( A199 and a10263a );
a10265a <=( a10264a and a10259a );
a10269a <=( (not A266) and (not A265) );
a10270a <=( (not A202) and a10269a );
a10274a <=( A300 and A298 );
a10275a <=( (not A268) and a10274a );
a10276a <=( a10275a and a10270a );
a10279a <=( A166 and A168 );
a10283a <=( A203 and A200 );
a10284a <=( (not A199) and a10283a );
a10285a <=( a10284a and a10279a );
a10289a <=( A298 and A267 );
a10290a <=( A265 and a10289a );
a10294a <=( (not A301) and (not A300) );
a10295a <=( A299 and a10294a );
a10296a <=( a10295a and a10290a );
a10299a <=( A166 and A168 );
a10303a <=( A203 and A200 );
a10304a <=( (not A199) and a10303a );
a10305a <=( a10304a and a10299a );
a10309a <=( A298 and A267 );
a10310a <=( A266 and a10309a );
a10314a <=( (not A301) and (not A300) );
a10315a <=( A299 and a10314a );
a10316a <=( a10315a and a10310a );
a10319a <=( A166 and A168 );
a10323a <=( A203 and A200 );
a10324a <=( (not A199) and a10323a );
a10325a <=( a10324a and a10319a );
a10329a <=( A269 and A266 );
a10330a <=( (not A265) and a10329a );
a10334a <=( (not A302) and (not A301) );
a10335a <=( (not A300) and a10334a );
a10336a <=( a10335a and a10330a );
a10339a <=( A166 and A168 );
a10343a <=( A203 and A200 );
a10344a <=( (not A199) and a10343a );
a10345a <=( a10344a and a10339a );
a10349a <=( A269 and A266 );
a10350a <=( (not A265) and a10349a );
a10354a <=( (not A301) and (not A299) );
a10355a <=( (not A298) and a10354a );
a10356a <=( a10355a and a10350a );
a10359a <=( A166 and A168 );
a10363a <=( A203 and A200 );
a10364a <=( (not A199) and a10363a );
a10365a <=( a10364a and a10359a );
a10369a <=( A269 and (not A266) );
a10370a <=( A265 and a10369a );
a10374a <=( (not A302) and (not A301) );
a10375a <=( (not A300) and a10374a );
a10376a <=( a10375a and a10370a );
a10379a <=( A166 and A168 );
a10383a <=( A203 and A200 );
a10384a <=( (not A199) and a10383a );
a10385a <=( a10384a and a10379a );
a10389a <=( A269 and (not A266) );
a10390a <=( A265 and a10389a );
a10394a <=( (not A301) and (not A299) );
a10395a <=( (not A298) and a10394a );
a10396a <=( a10395a and a10390a );
a10399a <=( A166 and A168 );
a10403a <=( A203 and (not A200) );
a10404a <=( A199 and a10403a );
a10405a <=( a10404a and a10399a );
a10409a <=( A298 and A267 );
a10410a <=( A265 and a10409a );
a10414a <=( (not A301) and (not A300) );
a10415a <=( A299 and a10414a );
a10416a <=( a10415a and a10410a );
a10419a <=( A166 and A168 );
a10423a <=( A203 and (not A200) );
a10424a <=( A199 and a10423a );
a10425a <=( a10424a and a10419a );
a10429a <=( A298 and A267 );
a10430a <=( A266 and a10429a );
a10434a <=( (not A301) and (not A300) );
a10435a <=( A299 and a10434a );
a10436a <=( a10435a and a10430a );
a10439a <=( A166 and A168 );
a10443a <=( A203 and (not A200) );
a10444a <=( A199 and a10443a );
a10445a <=( a10444a and a10439a );
a10449a <=( A269 and A266 );
a10450a <=( (not A265) and a10449a );
a10454a <=( (not A302) and (not A301) );
a10455a <=( (not A300) and a10454a );
a10456a <=( a10455a and a10450a );
a10459a <=( A166 and A168 );
a10463a <=( A203 and (not A200) );
a10464a <=( A199 and a10463a );
a10465a <=( a10464a and a10459a );
a10469a <=( A269 and A266 );
a10470a <=( (not A265) and a10469a );
a10474a <=( (not A301) and (not A299) );
a10475a <=( (not A298) and a10474a );
a10476a <=( a10475a and a10470a );
a10479a <=( A166 and A168 );
a10483a <=( A203 and (not A200) );
a10484a <=( A199 and a10483a );
a10485a <=( a10484a and a10479a );
a10489a <=( A269 and (not A266) );
a10490a <=( A265 and a10489a );
a10494a <=( (not A302) and (not A301) );
a10495a <=( (not A300) and a10494a );
a10496a <=( a10495a and a10490a );
a10499a <=( A166 and A168 );
a10503a <=( A203 and (not A200) );
a10504a <=( A199 and a10503a );
a10505a <=( a10504a and a10499a );
a10509a <=( A269 and (not A266) );
a10510a <=( A265 and a10509a );
a10514a <=( (not A301) and (not A299) );
a10515a <=( (not A298) and a10514a );
a10516a <=( a10515a and a10510a );
a10519a <=( A166 and A168 );
a10523a <=( (not A202) and (not A200) );
a10524a <=( (not A199) and a10523a );
a10525a <=( a10524a and a10519a );
a10529a <=( (not A269) and (not A268) );
a10530a <=( (not A267) and a10529a );
a10534a <=( A302 and (not A299) );
a10535a <=( A298 and a10534a );
a10536a <=( a10535a and a10530a );
a10539a <=( A166 and A168 );
a10543a <=( (not A202) and (not A200) );
a10544a <=( (not A199) and a10543a );
a10545a <=( a10544a and a10539a );
a10549a <=( (not A269) and (not A268) );
a10550a <=( (not A267) and a10549a );
a10554a <=( A302 and A299 );
a10555a <=( (not A298) and a10554a );
a10556a <=( a10555a and a10550a );
a10559a <=( A166 and A168 );
a10563a <=( (not A202) and (not A200) );
a10564a <=( (not A199) and a10563a );
a10565a <=( a10564a and a10559a );
a10569a <=( (not A267) and A266 );
a10570a <=( A265 and a10569a );
a10574a <=( A300 and A299 );
a10575a <=( (not A268) and a10574a );
a10576a <=( a10575a and a10570a );
a10579a <=( A166 and A168 );
a10583a <=( (not A202) and (not A200) );
a10584a <=( (not A199) and a10583a );
a10585a <=( a10584a and a10579a );
a10589a <=( (not A267) and A266 );
a10590a <=( A265 and a10589a );
a10594a <=( A300 and A298 );
a10595a <=( (not A268) and a10594a );
a10596a <=( a10595a and a10590a );
a10599a <=( A166 and A168 );
a10603a <=( (not A202) and (not A200) );
a10604a <=( (not A199) and a10603a );
a10605a <=( a10604a and a10599a );
a10609a <=( (not A268) and (not A266) );
a10610a <=( (not A265) and a10609a );
a10614a <=( A302 and (not A299) );
a10615a <=( A298 and a10614a );
a10616a <=( a10615a and a10610a );
a10619a <=( A166 and A168 );
a10623a <=( (not A202) and (not A200) );
a10624a <=( (not A199) and a10623a );
a10625a <=( a10624a and a10619a );
a10629a <=( (not A268) and (not A266) );
a10630a <=( (not A265) and a10629a );
a10634a <=( A302 and A299 );
a10635a <=( (not A298) and a10634a );
a10636a <=( a10635a and a10630a );
a10639a <=( A167 and A168 );
a10643a <=( (not A203) and (not A202) );
a10644a <=( (not A201) and a10643a );
a10645a <=( a10644a and a10639a );
a10649a <=( (not A269) and (not A268) );
a10650a <=( (not A267) and a10649a );
a10654a <=( A302 and (not A299) );
a10655a <=( A298 and a10654a );
a10656a <=( a10655a and a10650a );
a10659a <=( A167 and A168 );
a10663a <=( (not A203) and (not A202) );
a10664a <=( (not A201) and a10663a );
a10665a <=( a10664a and a10659a );
a10669a <=( (not A269) and (not A268) );
a10670a <=( (not A267) and a10669a );
a10674a <=( A302 and A299 );
a10675a <=( (not A298) and a10674a );
a10676a <=( a10675a and a10670a );
a10679a <=( A167 and A168 );
a10683a <=( (not A203) and (not A202) );
a10684a <=( (not A201) and a10683a );
a10685a <=( a10684a and a10679a );
a10689a <=( (not A267) and A266 );
a10690a <=( A265 and a10689a );
a10694a <=( A300 and A299 );
a10695a <=( (not A268) and a10694a );
a10696a <=( a10695a and a10690a );
a10699a <=( A167 and A168 );
a10703a <=( (not A203) and (not A202) );
a10704a <=( (not A201) and a10703a );
a10705a <=( a10704a and a10699a );
a10709a <=( (not A267) and A266 );
a10710a <=( A265 and a10709a );
a10714a <=( A300 and A298 );
a10715a <=( (not A268) and a10714a );
a10716a <=( a10715a and a10710a );
a10719a <=( A167 and A168 );
a10723a <=( (not A203) and (not A202) );
a10724a <=( (not A201) and a10723a );
a10725a <=( a10724a and a10719a );
a10729a <=( (not A268) and (not A266) );
a10730a <=( (not A265) and a10729a );
a10734a <=( A302 and (not A299) );
a10735a <=( A298 and a10734a );
a10736a <=( a10735a and a10730a );
a10739a <=( A167 and A168 );
a10743a <=( (not A203) and (not A202) );
a10744a <=( (not A201) and a10743a );
a10745a <=( a10744a and a10739a );
a10749a <=( (not A268) and (not A266) );
a10750a <=( (not A265) and a10749a );
a10754a <=( A302 and A299 );
a10755a <=( (not A298) and a10754a );
a10756a <=( a10755a and a10750a );
a10759a <=( A167 and A168 );
a10763a <=( (not A265) and A201 );
a10764a <=( A199 and a10763a );
a10765a <=( a10764a and a10759a );
a10769a <=( A298 and A269 );
a10770a <=( A266 and a10769a );
a10774a <=( (not A301) and (not A300) );
a10775a <=( A299 and a10774a );
a10776a <=( a10775a and a10770a );
a10779a <=( A167 and A168 );
a10783a <=( A265 and A201 );
a10784a <=( A199 and a10783a );
a10785a <=( a10784a and a10779a );
a10789a <=( A298 and A269 );
a10790a <=( (not A266) and a10789a );
a10794a <=( (not A301) and (not A300) );
a10795a <=( A299 and a10794a );
a10796a <=( a10795a and a10790a );
a10799a <=( A167 and A168 );
a10803a <=( (not A265) and A201 );
a10804a <=( A200 and a10803a );
a10805a <=( a10804a and a10799a );
a10809a <=( A298 and A269 );
a10810a <=( A266 and a10809a );
a10814a <=( (not A301) and (not A300) );
a10815a <=( A299 and a10814a );
a10816a <=( a10815a and a10810a );
a10819a <=( A167 and A168 );
a10823a <=( A265 and A201 );
a10824a <=( A200 and a10823a );
a10825a <=( a10824a and a10819a );
a10829a <=( A298 and A269 );
a10830a <=( (not A266) and a10829a );
a10834a <=( (not A301) and (not A300) );
a10835a <=( A299 and a10834a );
a10836a <=( a10835a and a10830a );
a10839a <=( A167 and A168 );
a10843a <=( (not A201) and A200 );
a10844a <=( A199 and a10843a );
a10845a <=( a10844a and a10839a );
a10849a <=( (not A268) and (not A267) );
a10850a <=( (not A202) and a10849a );
a10854a <=( A300 and A299 );
a10855a <=( (not A269) and a10854a );
a10856a <=( a10855a and a10850a );
a10859a <=( A167 and A168 );
a10863a <=( (not A201) and A200 );
a10864a <=( A199 and a10863a );
a10865a <=( a10864a and a10859a );
a10869a <=( (not A268) and (not A267) );
a10870a <=( (not A202) and a10869a );
a10874a <=( A300 and A298 );
a10875a <=( (not A269) and a10874a );
a10876a <=( a10875a and a10870a );
a10879a <=( A167 and A168 );
a10883a <=( (not A201) and A200 );
a10884a <=( A199 and a10883a );
a10885a <=( a10884a and a10879a );
a10889a <=( A266 and A265 );
a10890a <=( (not A202) and a10889a );
a10894a <=( A301 and (not A268) );
a10895a <=( (not A267) and a10894a );
a10896a <=( a10895a and a10890a );
a10899a <=( A167 and A168 );
a10903a <=( (not A201) and A200 );
a10904a <=( A199 and a10903a );
a10905a <=( a10904a and a10899a );
a10909a <=( (not A266) and (not A265) );
a10910a <=( (not A202) and a10909a );
a10914a <=( A300 and A299 );
a10915a <=( (not A268) and a10914a );
a10916a <=( a10915a and a10910a );
a10919a <=( A167 and A168 );
a10923a <=( (not A201) and A200 );
a10924a <=( A199 and a10923a );
a10925a <=( a10924a and a10919a );
a10929a <=( (not A266) and (not A265) );
a10930a <=( (not A202) and a10929a );
a10934a <=( A300 and A298 );
a10935a <=( (not A268) and a10934a );
a10936a <=( a10935a and a10930a );
a10939a <=( A167 and A168 );
a10943a <=( A203 and A200 );
a10944a <=( (not A199) and a10943a );
a10945a <=( a10944a and a10939a );
a10949a <=( A298 and A267 );
a10950a <=( A265 and a10949a );
a10954a <=( (not A301) and (not A300) );
a10955a <=( A299 and a10954a );
a10956a <=( a10955a and a10950a );
a10959a <=( A167 and A168 );
a10963a <=( A203 and A200 );
a10964a <=( (not A199) and a10963a );
a10965a <=( a10964a and a10959a );
a10969a <=( A298 and A267 );
a10970a <=( A266 and a10969a );
a10974a <=( (not A301) and (not A300) );
a10975a <=( A299 and a10974a );
a10976a <=( a10975a and a10970a );
a10979a <=( A167 and A168 );
a10983a <=( A203 and A200 );
a10984a <=( (not A199) and a10983a );
a10985a <=( a10984a and a10979a );
a10989a <=( A269 and A266 );
a10990a <=( (not A265) and a10989a );
a10994a <=( (not A302) and (not A301) );
a10995a <=( (not A300) and a10994a );
a10996a <=( a10995a and a10990a );
a10999a <=( A167 and A168 );
a11003a <=( A203 and A200 );
a11004a <=( (not A199) and a11003a );
a11005a <=( a11004a and a10999a );
a11009a <=( A269 and A266 );
a11010a <=( (not A265) and a11009a );
a11014a <=( (not A301) and (not A299) );
a11015a <=( (not A298) and a11014a );
a11016a <=( a11015a and a11010a );
a11019a <=( A167 and A168 );
a11023a <=( A203 and A200 );
a11024a <=( (not A199) and a11023a );
a11025a <=( a11024a and a11019a );
a11029a <=( A269 and (not A266) );
a11030a <=( A265 and a11029a );
a11034a <=( (not A302) and (not A301) );
a11035a <=( (not A300) and a11034a );
a11036a <=( a11035a and a11030a );
a11039a <=( A167 and A168 );
a11043a <=( A203 and A200 );
a11044a <=( (not A199) and a11043a );
a11045a <=( a11044a and a11039a );
a11049a <=( A269 and (not A266) );
a11050a <=( A265 and a11049a );
a11054a <=( (not A301) and (not A299) );
a11055a <=( (not A298) and a11054a );
a11056a <=( a11055a and a11050a );
a11059a <=( A167 and A168 );
a11063a <=( A203 and (not A200) );
a11064a <=( A199 and a11063a );
a11065a <=( a11064a and a11059a );
a11069a <=( A298 and A267 );
a11070a <=( A265 and a11069a );
a11074a <=( (not A301) and (not A300) );
a11075a <=( A299 and a11074a );
a11076a <=( a11075a and a11070a );
a11079a <=( A167 and A168 );
a11083a <=( A203 and (not A200) );
a11084a <=( A199 and a11083a );
a11085a <=( a11084a and a11079a );
a11089a <=( A298 and A267 );
a11090a <=( A266 and a11089a );
a11094a <=( (not A301) and (not A300) );
a11095a <=( A299 and a11094a );
a11096a <=( a11095a and a11090a );
a11099a <=( A167 and A168 );
a11103a <=( A203 and (not A200) );
a11104a <=( A199 and a11103a );
a11105a <=( a11104a and a11099a );
a11109a <=( A269 and A266 );
a11110a <=( (not A265) and a11109a );
a11114a <=( (not A302) and (not A301) );
a11115a <=( (not A300) and a11114a );
a11116a <=( a11115a and a11110a );
a11119a <=( A167 and A168 );
a11123a <=( A203 and (not A200) );
a11124a <=( A199 and a11123a );
a11125a <=( a11124a and a11119a );
a11129a <=( A269 and A266 );
a11130a <=( (not A265) and a11129a );
a11134a <=( (not A301) and (not A299) );
a11135a <=( (not A298) and a11134a );
a11136a <=( a11135a and a11130a );
a11139a <=( A167 and A168 );
a11143a <=( A203 and (not A200) );
a11144a <=( A199 and a11143a );
a11145a <=( a11144a and a11139a );
a11149a <=( A269 and (not A266) );
a11150a <=( A265 and a11149a );
a11154a <=( (not A302) and (not A301) );
a11155a <=( (not A300) and a11154a );
a11156a <=( a11155a and a11150a );
a11159a <=( A167 and A168 );
a11163a <=( A203 and (not A200) );
a11164a <=( A199 and a11163a );
a11165a <=( a11164a and a11159a );
a11169a <=( A269 and (not A266) );
a11170a <=( A265 and a11169a );
a11174a <=( (not A301) and (not A299) );
a11175a <=( (not A298) and a11174a );
a11176a <=( a11175a and a11170a );
a11179a <=( A167 and A168 );
a11183a <=( (not A202) and (not A200) );
a11184a <=( (not A199) and a11183a );
a11185a <=( a11184a and a11179a );
a11189a <=( (not A269) and (not A268) );
a11190a <=( (not A267) and a11189a );
a11194a <=( A302 and (not A299) );
a11195a <=( A298 and a11194a );
a11196a <=( a11195a and a11190a );
a11199a <=( A167 and A168 );
a11203a <=( (not A202) and (not A200) );
a11204a <=( (not A199) and a11203a );
a11205a <=( a11204a and a11199a );
a11209a <=( (not A269) and (not A268) );
a11210a <=( (not A267) and a11209a );
a11214a <=( A302 and A299 );
a11215a <=( (not A298) and a11214a );
a11216a <=( a11215a and a11210a );
a11219a <=( A167 and A168 );
a11223a <=( (not A202) and (not A200) );
a11224a <=( (not A199) and a11223a );
a11225a <=( a11224a and a11219a );
a11229a <=( (not A267) and A266 );
a11230a <=( A265 and a11229a );
a11234a <=( A300 and A299 );
a11235a <=( (not A268) and a11234a );
a11236a <=( a11235a and a11230a );
a11239a <=( A167 and A168 );
a11243a <=( (not A202) and (not A200) );
a11244a <=( (not A199) and a11243a );
a11245a <=( a11244a and a11239a );
a11249a <=( (not A267) and A266 );
a11250a <=( A265 and a11249a );
a11254a <=( A300 and A298 );
a11255a <=( (not A268) and a11254a );
a11256a <=( a11255a and a11250a );
a11259a <=( A167 and A168 );
a11263a <=( (not A202) and (not A200) );
a11264a <=( (not A199) and a11263a );
a11265a <=( a11264a and a11259a );
a11269a <=( (not A268) and (not A266) );
a11270a <=( (not A265) and a11269a );
a11274a <=( A302 and (not A299) );
a11275a <=( A298 and a11274a );
a11276a <=( a11275a and a11270a );
a11279a <=( A167 and A168 );
a11283a <=( (not A202) and (not A200) );
a11284a <=( (not A199) and a11283a );
a11285a <=( a11284a and a11279a );
a11289a <=( (not A268) and (not A266) );
a11290a <=( (not A265) and a11289a );
a11294a <=( A302 and A299 );
a11295a <=( (not A298) and a11294a );
a11296a <=( a11295a and a11290a );
a11299a <=( A167 and A170 );
a11303a <=( (not A265) and A202 );
a11304a <=( (not A166) and a11303a );
a11305a <=( a11304a and a11299a );
a11309a <=( A298 and A269 );
a11310a <=( A266 and a11309a );
a11314a <=( (not A301) and (not A300) );
a11315a <=( A299 and a11314a );
a11316a <=( a11315a and a11310a );
a11319a <=( A167 and A170 );
a11323a <=( A265 and A202 );
a11324a <=( (not A166) and a11323a );
a11325a <=( a11324a and a11319a );
a11329a <=( A298 and A269 );
a11330a <=( (not A266) and a11329a );
a11334a <=( (not A301) and (not A300) );
a11335a <=( A299 and a11334a );
a11336a <=( a11335a and a11330a );
a11339a <=( A167 and A170 );
a11343a <=( (not A202) and (not A201) );
a11344a <=( (not A166) and a11343a );
a11345a <=( a11344a and a11339a );
a11349a <=( (not A268) and (not A267) );
a11350a <=( (not A203) and a11349a );
a11354a <=( A300 and A299 );
a11355a <=( (not A269) and a11354a );
a11356a <=( a11355a and a11350a );
a11359a <=( A167 and A170 );
a11363a <=( (not A202) and (not A201) );
a11364a <=( (not A166) and a11363a );
a11365a <=( a11364a and a11359a );
a11369a <=( (not A268) and (not A267) );
a11370a <=( (not A203) and a11369a );
a11374a <=( A300 and A298 );
a11375a <=( (not A269) and a11374a );
a11376a <=( a11375a and a11370a );
a11379a <=( A167 and A170 );
a11383a <=( (not A202) and (not A201) );
a11384a <=( (not A166) and a11383a );
a11385a <=( a11384a and a11379a );
a11389a <=( A266 and A265 );
a11390a <=( (not A203) and a11389a );
a11394a <=( A301 and (not A268) );
a11395a <=( (not A267) and a11394a );
a11396a <=( a11395a and a11390a );
a11399a <=( A167 and A170 );
a11403a <=( (not A202) and (not A201) );
a11404a <=( (not A166) and a11403a );
a11405a <=( a11404a and a11399a );
a11409a <=( (not A266) and (not A265) );
a11410a <=( (not A203) and a11409a );
a11414a <=( A300 and A299 );
a11415a <=( (not A268) and a11414a );
a11416a <=( a11415a and a11410a );
a11419a <=( A167 and A170 );
a11423a <=( (not A202) and (not A201) );
a11424a <=( (not A166) and a11423a );
a11425a <=( a11424a and a11419a );
a11429a <=( (not A266) and (not A265) );
a11430a <=( (not A203) and a11429a );
a11434a <=( A300 and A298 );
a11435a <=( (not A268) and a11434a );
a11436a <=( a11435a and a11430a );
a11439a <=( A167 and A170 );
a11443a <=( A201 and A199 );
a11444a <=( (not A166) and a11443a );
a11445a <=( a11444a and a11439a );
a11449a <=( A298 and A267 );
a11450a <=( A265 and a11449a );
a11454a <=( (not A301) and (not A300) );
a11455a <=( A299 and a11454a );
a11456a <=( a11455a and a11450a );
a11459a <=( A167 and A170 );
a11463a <=( A201 and A199 );
a11464a <=( (not A166) and a11463a );
a11465a <=( a11464a and a11459a );
a11469a <=( A298 and A267 );
a11470a <=( A266 and a11469a );
a11474a <=( (not A301) and (not A300) );
a11475a <=( A299 and a11474a );
a11476a <=( a11475a and a11470a );
a11479a <=( A167 and A170 );
a11483a <=( A201 and A199 );
a11484a <=( (not A166) and a11483a );
a11485a <=( a11484a and a11479a );
a11489a <=( A269 and A266 );
a11490a <=( (not A265) and a11489a );
a11494a <=( (not A302) and (not A301) );
a11495a <=( (not A300) and a11494a );
a11496a <=( a11495a and a11490a );
a11499a <=( A167 and A170 );
a11503a <=( A201 and A199 );
a11504a <=( (not A166) and a11503a );
a11505a <=( a11504a and a11499a );
a11509a <=( A269 and A266 );
a11510a <=( (not A265) and a11509a );
a11514a <=( (not A301) and (not A299) );
a11515a <=( (not A298) and a11514a );
a11516a <=( a11515a and a11510a );
a11519a <=( A167 and A170 );
a11523a <=( A201 and A199 );
a11524a <=( (not A166) and a11523a );
a11525a <=( a11524a and a11519a );
a11529a <=( A269 and (not A266) );
a11530a <=( A265 and a11529a );
a11534a <=( (not A302) and (not A301) );
a11535a <=( (not A300) and a11534a );
a11536a <=( a11535a and a11530a );
a11539a <=( A167 and A170 );
a11543a <=( A201 and A199 );
a11544a <=( (not A166) and a11543a );
a11545a <=( a11544a and a11539a );
a11549a <=( A269 and (not A266) );
a11550a <=( A265 and a11549a );
a11554a <=( (not A301) and (not A299) );
a11555a <=( (not A298) and a11554a );
a11556a <=( a11555a and a11550a );
a11559a <=( A167 and A170 );
a11563a <=( A201 and A200 );
a11564a <=( (not A166) and a11563a );
a11565a <=( a11564a and a11559a );
a11569a <=( A298 and A267 );
a11570a <=( A265 and a11569a );
a11574a <=( (not A301) and (not A300) );
a11575a <=( A299 and a11574a );
a11576a <=( a11575a and a11570a );
a11579a <=( A167 and A170 );
a11583a <=( A201 and A200 );
a11584a <=( (not A166) and a11583a );
a11585a <=( a11584a and a11579a );
a11589a <=( A298 and A267 );
a11590a <=( A266 and a11589a );
a11594a <=( (not A301) and (not A300) );
a11595a <=( A299 and a11594a );
a11596a <=( a11595a and a11590a );
a11599a <=( A167 and A170 );
a11603a <=( A201 and A200 );
a11604a <=( (not A166) and a11603a );
a11605a <=( a11604a and a11599a );
a11609a <=( A269 and A266 );
a11610a <=( (not A265) and a11609a );
a11614a <=( (not A302) and (not A301) );
a11615a <=( (not A300) and a11614a );
a11616a <=( a11615a and a11610a );
a11619a <=( A167 and A170 );
a11623a <=( A201 and A200 );
a11624a <=( (not A166) and a11623a );
a11625a <=( a11624a and a11619a );
a11629a <=( A269 and A266 );
a11630a <=( (not A265) and a11629a );
a11634a <=( (not A301) and (not A299) );
a11635a <=( (not A298) and a11634a );
a11636a <=( a11635a and a11630a );
a11639a <=( A167 and A170 );
a11643a <=( A201 and A200 );
a11644a <=( (not A166) and a11643a );
a11645a <=( a11644a and a11639a );
a11649a <=( A269 and (not A266) );
a11650a <=( A265 and a11649a );
a11654a <=( (not A302) and (not A301) );
a11655a <=( (not A300) and a11654a );
a11656a <=( a11655a and a11650a );
a11659a <=( A167 and A170 );
a11663a <=( A201 and A200 );
a11664a <=( (not A166) and a11663a );
a11665a <=( a11664a and a11659a );
a11669a <=( A269 and (not A266) );
a11670a <=( A265 and a11669a );
a11674a <=( (not A301) and (not A299) );
a11675a <=( (not A298) and a11674a );
a11676a <=( a11675a and a11670a );
a11679a <=( A167 and A170 );
a11683a <=( A200 and A199 );
a11684a <=( (not A166) and a11683a );
a11685a <=( a11684a and a11679a );
a11689a <=( (not A267) and (not A202) );
a11690a <=( (not A201) and a11689a );
a11694a <=( A301 and (not A269) );
a11695a <=( (not A268) and a11694a );
a11696a <=( a11695a and a11690a );
a11699a <=( A167 and A170 );
a11703a <=( A200 and A199 );
a11704a <=( (not A166) and a11703a );
a11705a <=( a11704a and a11699a );
a11709a <=( (not A265) and (not A202) );
a11710a <=( (not A201) and a11709a );
a11714a <=( A301 and (not A268) );
a11715a <=( (not A266) and a11714a );
a11716a <=( a11715a and a11710a );
a11719a <=( A167 and A170 );
a11723a <=( A200 and (not A199) );
a11724a <=( (not A166) and a11723a );
a11725a <=( a11724a and a11719a );
a11729a <=( A298 and A268 );
a11730a <=( A203 and a11729a );
a11734a <=( (not A301) and (not A300) );
a11735a <=( A299 and a11734a );
a11736a <=( a11735a and a11730a );
a11739a <=( A167 and A170 );
a11743a <=( A200 and (not A199) );
a11744a <=( (not A166) and a11743a );
a11745a <=( a11744a and a11739a );
a11749a <=( A267 and A265 );
a11750a <=( A203 and a11749a );
a11754a <=( (not A302) and (not A301) );
a11755a <=( (not A300) and a11754a );
a11756a <=( a11755a and a11750a );
a11759a <=( A167 and A170 );
a11763a <=( A200 and (not A199) );
a11764a <=( (not A166) and a11763a );
a11765a <=( a11764a and a11759a );
a11769a <=( A267 and A265 );
a11770a <=( A203 and a11769a );
a11774a <=( (not A301) and (not A299) );
a11775a <=( (not A298) and a11774a );
a11776a <=( a11775a and a11770a );
a11779a <=( A167 and A170 );
a11783a <=( A200 and (not A199) );
a11784a <=( (not A166) and a11783a );
a11785a <=( a11784a and a11779a );
a11789a <=( A267 and A266 );
a11790a <=( A203 and a11789a );
a11794a <=( (not A302) and (not A301) );
a11795a <=( (not A300) and a11794a );
a11796a <=( a11795a and a11790a );
a11799a <=( A167 and A170 );
a11803a <=( A200 and (not A199) );
a11804a <=( (not A166) and a11803a );
a11805a <=( a11804a and a11799a );
a11809a <=( A267 and A266 );
a11810a <=( A203 and a11809a );
a11814a <=( (not A301) and (not A299) );
a11815a <=( (not A298) and a11814a );
a11816a <=( a11815a and a11810a );
a11819a <=( A167 and A170 );
a11823a <=( (not A200) and A199 );
a11824a <=( (not A166) and a11823a );
a11825a <=( a11824a and a11819a );
a11829a <=( A298 and A268 );
a11830a <=( A203 and a11829a );
a11834a <=( (not A301) and (not A300) );
a11835a <=( A299 and a11834a );
a11836a <=( a11835a and a11830a );
a11839a <=( A167 and A170 );
a11843a <=( (not A200) and A199 );
a11844a <=( (not A166) and a11843a );
a11845a <=( a11844a and a11839a );
a11849a <=( A267 and A265 );
a11850a <=( A203 and a11849a );
a11854a <=( (not A302) and (not A301) );
a11855a <=( (not A300) and a11854a );
a11856a <=( a11855a and a11850a );
a11859a <=( A167 and A170 );
a11863a <=( (not A200) and A199 );
a11864a <=( (not A166) and a11863a );
a11865a <=( a11864a and a11859a );
a11869a <=( A267 and A265 );
a11870a <=( A203 and a11869a );
a11874a <=( (not A301) and (not A299) );
a11875a <=( (not A298) and a11874a );
a11876a <=( a11875a and a11870a );
a11879a <=( A167 and A170 );
a11883a <=( (not A200) and A199 );
a11884a <=( (not A166) and a11883a );
a11885a <=( a11884a and a11879a );
a11889a <=( A267 and A266 );
a11890a <=( A203 and a11889a );
a11894a <=( (not A302) and (not A301) );
a11895a <=( (not A300) and a11894a );
a11896a <=( a11895a and a11890a );
a11899a <=( A167 and A170 );
a11903a <=( (not A200) and A199 );
a11904a <=( (not A166) and a11903a );
a11905a <=( a11904a and a11899a );
a11909a <=( A267 and A266 );
a11910a <=( A203 and a11909a );
a11914a <=( (not A301) and (not A299) );
a11915a <=( (not A298) and a11914a );
a11916a <=( a11915a and a11910a );
a11919a <=( A167 and A170 );
a11923a <=( (not A200) and (not A199) );
a11924a <=( (not A166) and a11923a );
a11925a <=( a11924a and a11919a );
a11929a <=( (not A268) and (not A267) );
a11930a <=( (not A202) and a11929a );
a11934a <=( A300 and A299 );
a11935a <=( (not A269) and a11934a );
a11936a <=( a11935a and a11930a );
a11939a <=( A167 and A170 );
a11943a <=( (not A200) and (not A199) );
a11944a <=( (not A166) and a11943a );
a11945a <=( a11944a and a11939a );
a11949a <=( (not A268) and (not A267) );
a11950a <=( (not A202) and a11949a );
a11954a <=( A300 and A298 );
a11955a <=( (not A269) and a11954a );
a11956a <=( a11955a and a11950a );
a11959a <=( A167 and A170 );
a11963a <=( (not A200) and (not A199) );
a11964a <=( (not A166) and a11963a );
a11965a <=( a11964a and a11959a );
a11969a <=( A266 and A265 );
a11970a <=( (not A202) and a11969a );
a11974a <=( A301 and (not A268) );
a11975a <=( (not A267) and a11974a );
a11976a <=( a11975a and a11970a );
a11979a <=( A167 and A170 );
a11983a <=( (not A200) and (not A199) );
a11984a <=( (not A166) and a11983a );
a11985a <=( a11984a and a11979a );
a11989a <=( (not A266) and (not A265) );
a11990a <=( (not A202) and a11989a );
a11994a <=( A300 and A299 );
a11995a <=( (not A268) and a11994a );
a11996a <=( a11995a and a11990a );
a11999a <=( A167 and A170 );
a12003a <=( (not A200) and (not A199) );
a12004a <=( (not A166) and a12003a );
a12005a <=( a12004a and a11999a );
a12009a <=( (not A266) and (not A265) );
a12010a <=( (not A202) and a12009a );
a12014a <=( A300 and A298 );
a12015a <=( (not A268) and a12014a );
a12016a <=( a12015a and a12010a );
a12019a <=( (not A167) and A170 );
a12023a <=( (not A265) and A202 );
a12024a <=( A166 and a12023a );
a12025a <=( a12024a and a12019a );
a12029a <=( A298 and A269 );
a12030a <=( A266 and a12029a );
a12034a <=( (not A301) and (not A300) );
a12035a <=( A299 and a12034a );
a12036a <=( a12035a and a12030a );
a12039a <=( (not A167) and A170 );
a12043a <=( A265 and A202 );
a12044a <=( A166 and a12043a );
a12045a <=( a12044a and a12039a );
a12049a <=( A298 and A269 );
a12050a <=( (not A266) and a12049a );
a12054a <=( (not A301) and (not A300) );
a12055a <=( A299 and a12054a );
a12056a <=( a12055a and a12050a );
a12059a <=( (not A167) and A170 );
a12063a <=( (not A202) and (not A201) );
a12064a <=( A166 and a12063a );
a12065a <=( a12064a and a12059a );
a12069a <=( (not A268) and (not A267) );
a12070a <=( (not A203) and a12069a );
a12074a <=( A300 and A299 );
a12075a <=( (not A269) and a12074a );
a12076a <=( a12075a and a12070a );
a12079a <=( (not A167) and A170 );
a12083a <=( (not A202) and (not A201) );
a12084a <=( A166 and a12083a );
a12085a <=( a12084a and a12079a );
a12089a <=( (not A268) and (not A267) );
a12090a <=( (not A203) and a12089a );
a12094a <=( A300 and A298 );
a12095a <=( (not A269) and a12094a );
a12096a <=( a12095a and a12090a );
a12099a <=( (not A167) and A170 );
a12103a <=( (not A202) and (not A201) );
a12104a <=( A166 and a12103a );
a12105a <=( a12104a and a12099a );
a12109a <=( A266 and A265 );
a12110a <=( (not A203) and a12109a );
a12114a <=( A301 and (not A268) );
a12115a <=( (not A267) and a12114a );
a12116a <=( a12115a and a12110a );
a12119a <=( (not A167) and A170 );
a12123a <=( (not A202) and (not A201) );
a12124a <=( A166 and a12123a );
a12125a <=( a12124a and a12119a );
a12129a <=( (not A266) and (not A265) );
a12130a <=( (not A203) and a12129a );
a12134a <=( A300 and A299 );
a12135a <=( (not A268) and a12134a );
a12136a <=( a12135a and a12130a );
a12139a <=( (not A167) and A170 );
a12143a <=( (not A202) and (not A201) );
a12144a <=( A166 and a12143a );
a12145a <=( a12144a and a12139a );
a12149a <=( (not A266) and (not A265) );
a12150a <=( (not A203) and a12149a );
a12154a <=( A300 and A298 );
a12155a <=( (not A268) and a12154a );
a12156a <=( a12155a and a12150a );
a12159a <=( (not A167) and A170 );
a12163a <=( A201 and A199 );
a12164a <=( A166 and a12163a );
a12165a <=( a12164a and a12159a );
a12169a <=( A298 and A267 );
a12170a <=( A265 and a12169a );
a12174a <=( (not A301) and (not A300) );
a12175a <=( A299 and a12174a );
a12176a <=( a12175a and a12170a );
a12179a <=( (not A167) and A170 );
a12183a <=( A201 and A199 );
a12184a <=( A166 and a12183a );
a12185a <=( a12184a and a12179a );
a12189a <=( A298 and A267 );
a12190a <=( A266 and a12189a );
a12194a <=( (not A301) and (not A300) );
a12195a <=( A299 and a12194a );
a12196a <=( a12195a and a12190a );
a12199a <=( (not A167) and A170 );
a12203a <=( A201 and A199 );
a12204a <=( A166 and a12203a );
a12205a <=( a12204a and a12199a );
a12209a <=( A269 and A266 );
a12210a <=( (not A265) and a12209a );
a12214a <=( (not A302) and (not A301) );
a12215a <=( (not A300) and a12214a );
a12216a <=( a12215a and a12210a );
a12219a <=( (not A167) and A170 );
a12223a <=( A201 and A199 );
a12224a <=( A166 and a12223a );
a12225a <=( a12224a and a12219a );
a12229a <=( A269 and A266 );
a12230a <=( (not A265) and a12229a );
a12234a <=( (not A301) and (not A299) );
a12235a <=( (not A298) and a12234a );
a12236a <=( a12235a and a12230a );
a12239a <=( (not A167) and A170 );
a12243a <=( A201 and A199 );
a12244a <=( A166 and a12243a );
a12245a <=( a12244a and a12239a );
a12249a <=( A269 and (not A266) );
a12250a <=( A265 and a12249a );
a12254a <=( (not A302) and (not A301) );
a12255a <=( (not A300) and a12254a );
a12256a <=( a12255a and a12250a );
a12259a <=( (not A167) and A170 );
a12263a <=( A201 and A199 );
a12264a <=( A166 and a12263a );
a12265a <=( a12264a and a12259a );
a12269a <=( A269 and (not A266) );
a12270a <=( A265 and a12269a );
a12274a <=( (not A301) and (not A299) );
a12275a <=( (not A298) and a12274a );
a12276a <=( a12275a and a12270a );
a12279a <=( (not A167) and A170 );
a12283a <=( A201 and A200 );
a12284a <=( A166 and a12283a );
a12285a <=( a12284a and a12279a );
a12289a <=( A298 and A267 );
a12290a <=( A265 and a12289a );
a12294a <=( (not A301) and (not A300) );
a12295a <=( A299 and a12294a );
a12296a <=( a12295a and a12290a );
a12299a <=( (not A167) and A170 );
a12303a <=( A201 and A200 );
a12304a <=( A166 and a12303a );
a12305a <=( a12304a and a12299a );
a12309a <=( A298 and A267 );
a12310a <=( A266 and a12309a );
a12314a <=( (not A301) and (not A300) );
a12315a <=( A299 and a12314a );
a12316a <=( a12315a and a12310a );
a12319a <=( (not A167) and A170 );
a12323a <=( A201 and A200 );
a12324a <=( A166 and a12323a );
a12325a <=( a12324a and a12319a );
a12329a <=( A269 and A266 );
a12330a <=( (not A265) and a12329a );
a12334a <=( (not A302) and (not A301) );
a12335a <=( (not A300) and a12334a );
a12336a <=( a12335a and a12330a );
a12339a <=( (not A167) and A170 );
a12343a <=( A201 and A200 );
a12344a <=( A166 and a12343a );
a12345a <=( a12344a and a12339a );
a12349a <=( A269 and A266 );
a12350a <=( (not A265) and a12349a );
a12354a <=( (not A301) and (not A299) );
a12355a <=( (not A298) and a12354a );
a12356a <=( a12355a and a12350a );
a12359a <=( (not A167) and A170 );
a12363a <=( A201 and A200 );
a12364a <=( A166 and a12363a );
a12365a <=( a12364a and a12359a );
a12369a <=( A269 and (not A266) );
a12370a <=( A265 and a12369a );
a12374a <=( (not A302) and (not A301) );
a12375a <=( (not A300) and a12374a );
a12376a <=( a12375a and a12370a );
a12379a <=( (not A167) and A170 );
a12383a <=( A201 and A200 );
a12384a <=( A166 and a12383a );
a12385a <=( a12384a and a12379a );
a12389a <=( A269 and (not A266) );
a12390a <=( A265 and a12389a );
a12394a <=( (not A301) and (not A299) );
a12395a <=( (not A298) and a12394a );
a12396a <=( a12395a and a12390a );
a12399a <=( (not A167) and A170 );
a12403a <=( A200 and A199 );
a12404a <=( A166 and a12403a );
a12405a <=( a12404a and a12399a );
a12409a <=( (not A267) and (not A202) );
a12410a <=( (not A201) and a12409a );
a12414a <=( A301 and (not A269) );
a12415a <=( (not A268) and a12414a );
a12416a <=( a12415a and a12410a );
a12419a <=( (not A167) and A170 );
a12423a <=( A200 and A199 );
a12424a <=( A166 and a12423a );
a12425a <=( a12424a and a12419a );
a12429a <=( (not A265) and (not A202) );
a12430a <=( (not A201) and a12429a );
a12434a <=( A301 and (not A268) );
a12435a <=( (not A266) and a12434a );
a12436a <=( a12435a and a12430a );
a12439a <=( (not A167) and A170 );
a12443a <=( A200 and (not A199) );
a12444a <=( A166 and a12443a );
a12445a <=( a12444a and a12439a );
a12449a <=( A298 and A268 );
a12450a <=( A203 and a12449a );
a12454a <=( (not A301) and (not A300) );
a12455a <=( A299 and a12454a );
a12456a <=( a12455a and a12450a );
a12459a <=( (not A167) and A170 );
a12463a <=( A200 and (not A199) );
a12464a <=( A166 and a12463a );
a12465a <=( a12464a and a12459a );
a12469a <=( A267 and A265 );
a12470a <=( A203 and a12469a );
a12474a <=( (not A302) and (not A301) );
a12475a <=( (not A300) and a12474a );
a12476a <=( a12475a and a12470a );
a12479a <=( (not A167) and A170 );
a12483a <=( A200 and (not A199) );
a12484a <=( A166 and a12483a );
a12485a <=( a12484a and a12479a );
a12489a <=( A267 and A265 );
a12490a <=( A203 and a12489a );
a12494a <=( (not A301) and (not A299) );
a12495a <=( (not A298) and a12494a );
a12496a <=( a12495a and a12490a );
a12499a <=( (not A167) and A170 );
a12503a <=( A200 and (not A199) );
a12504a <=( A166 and a12503a );
a12505a <=( a12504a and a12499a );
a12509a <=( A267 and A266 );
a12510a <=( A203 and a12509a );
a12514a <=( (not A302) and (not A301) );
a12515a <=( (not A300) and a12514a );
a12516a <=( a12515a and a12510a );
a12519a <=( (not A167) and A170 );
a12523a <=( A200 and (not A199) );
a12524a <=( A166 and a12523a );
a12525a <=( a12524a and a12519a );
a12529a <=( A267 and A266 );
a12530a <=( A203 and a12529a );
a12534a <=( (not A301) and (not A299) );
a12535a <=( (not A298) and a12534a );
a12536a <=( a12535a and a12530a );
a12539a <=( (not A167) and A170 );
a12543a <=( (not A200) and A199 );
a12544a <=( A166 and a12543a );
a12545a <=( a12544a and a12539a );
a12549a <=( A298 and A268 );
a12550a <=( A203 and a12549a );
a12554a <=( (not A301) and (not A300) );
a12555a <=( A299 and a12554a );
a12556a <=( a12555a and a12550a );
a12559a <=( (not A167) and A170 );
a12563a <=( (not A200) and A199 );
a12564a <=( A166 and a12563a );
a12565a <=( a12564a and a12559a );
a12569a <=( A267 and A265 );
a12570a <=( A203 and a12569a );
a12574a <=( (not A302) and (not A301) );
a12575a <=( (not A300) and a12574a );
a12576a <=( a12575a and a12570a );
a12579a <=( (not A167) and A170 );
a12583a <=( (not A200) and A199 );
a12584a <=( A166 and a12583a );
a12585a <=( a12584a and a12579a );
a12589a <=( A267 and A265 );
a12590a <=( A203 and a12589a );
a12594a <=( (not A301) and (not A299) );
a12595a <=( (not A298) and a12594a );
a12596a <=( a12595a and a12590a );
a12599a <=( (not A167) and A170 );
a12603a <=( (not A200) and A199 );
a12604a <=( A166 and a12603a );
a12605a <=( a12604a and a12599a );
a12609a <=( A267 and A266 );
a12610a <=( A203 and a12609a );
a12614a <=( (not A302) and (not A301) );
a12615a <=( (not A300) and a12614a );
a12616a <=( a12615a and a12610a );
a12619a <=( (not A167) and A170 );
a12623a <=( (not A200) and A199 );
a12624a <=( A166 and a12623a );
a12625a <=( a12624a and a12619a );
a12629a <=( A267 and A266 );
a12630a <=( A203 and a12629a );
a12634a <=( (not A301) and (not A299) );
a12635a <=( (not A298) and a12634a );
a12636a <=( a12635a and a12630a );
a12639a <=( (not A167) and A170 );
a12643a <=( (not A200) and (not A199) );
a12644a <=( A166 and a12643a );
a12645a <=( a12644a and a12639a );
a12649a <=( (not A268) and (not A267) );
a12650a <=( (not A202) and a12649a );
a12654a <=( A300 and A299 );
a12655a <=( (not A269) and a12654a );
a12656a <=( a12655a and a12650a );
a12659a <=( (not A167) and A170 );
a12663a <=( (not A200) and (not A199) );
a12664a <=( A166 and a12663a );
a12665a <=( a12664a and a12659a );
a12669a <=( (not A268) and (not A267) );
a12670a <=( (not A202) and a12669a );
a12674a <=( A300 and A298 );
a12675a <=( (not A269) and a12674a );
a12676a <=( a12675a and a12670a );
a12679a <=( (not A167) and A170 );
a12683a <=( (not A200) and (not A199) );
a12684a <=( A166 and a12683a );
a12685a <=( a12684a and a12679a );
a12689a <=( A266 and A265 );
a12690a <=( (not A202) and a12689a );
a12694a <=( A301 and (not A268) );
a12695a <=( (not A267) and a12694a );
a12696a <=( a12695a and a12690a );
a12699a <=( (not A167) and A170 );
a12703a <=( (not A200) and (not A199) );
a12704a <=( A166 and a12703a );
a12705a <=( a12704a and a12699a );
a12709a <=( (not A266) and (not A265) );
a12710a <=( (not A202) and a12709a );
a12714a <=( A300 and A299 );
a12715a <=( (not A268) and a12714a );
a12716a <=( a12715a and a12710a );
a12719a <=( (not A167) and A170 );
a12723a <=( (not A200) and (not A199) );
a12724a <=( A166 and a12723a );
a12725a <=( a12724a and a12719a );
a12729a <=( (not A266) and (not A265) );
a12730a <=( (not A202) and a12729a );
a12734a <=( A300 and A298 );
a12735a <=( (not A268) and a12734a );
a12736a <=( a12735a and a12730a );
a12739a <=( (not A201) and A169 );
a12743a <=( A265 and (not A203) );
a12744a <=( (not A202) and a12743a );
a12745a <=( a12744a and a12739a );
a12749a <=( (not A268) and (not A267) );
a12750a <=( A266 and a12749a );
a12754a <=( A302 and (not A299) );
a12755a <=( A298 and a12754a );
a12756a <=( a12755a and a12750a );
a12759a <=( (not A201) and A169 );
a12763a <=( A265 and (not A203) );
a12764a <=( (not A202) and a12763a );
a12765a <=( a12764a and a12759a );
a12769a <=( (not A268) and (not A267) );
a12770a <=( A266 and a12769a );
a12774a <=( A302 and A299 );
a12775a <=( (not A298) and a12774a );
a12776a <=( a12775a and a12770a );
a12779a <=( A199 and A169 );
a12783a <=( (not A202) and (not A201) );
a12784a <=( A200 and a12783a );
a12785a <=( a12784a and a12779a );
a12789a <=( (not A269) and (not A268) );
a12790a <=( (not A267) and a12789a );
a12794a <=( A302 and (not A299) );
a12795a <=( A298 and a12794a );
a12796a <=( a12795a and a12790a );
a12799a <=( A199 and A169 );
a12803a <=( (not A202) and (not A201) );
a12804a <=( A200 and a12803a );
a12805a <=( a12804a and a12799a );
a12809a <=( (not A269) and (not A268) );
a12810a <=( (not A267) and a12809a );
a12814a <=( A302 and A299 );
a12815a <=( (not A298) and a12814a );
a12816a <=( a12815a and a12810a );
a12819a <=( A199 and A169 );
a12823a <=( (not A202) and (not A201) );
a12824a <=( A200 and a12823a );
a12825a <=( a12824a and a12819a );
a12829a <=( (not A267) and A266 );
a12830a <=( A265 and a12829a );
a12834a <=( A300 and A299 );
a12835a <=( (not A268) and a12834a );
a12836a <=( a12835a and a12830a );
a12839a <=( A199 and A169 );
a12843a <=( (not A202) and (not A201) );
a12844a <=( A200 and a12843a );
a12845a <=( a12844a and a12839a );
a12849a <=( (not A267) and A266 );
a12850a <=( A265 and a12849a );
a12854a <=( A300 and A298 );
a12855a <=( (not A268) and a12854a );
a12856a <=( a12855a and a12850a );
a12859a <=( A199 and A169 );
a12863a <=( (not A202) and (not A201) );
a12864a <=( A200 and a12863a );
a12865a <=( a12864a and a12859a );
a12869a <=( (not A268) and (not A266) );
a12870a <=( (not A265) and a12869a );
a12874a <=( A302 and (not A299) );
a12875a <=( A298 and a12874a );
a12876a <=( a12875a and a12870a );
a12879a <=( A199 and A169 );
a12883a <=( (not A202) and (not A201) );
a12884a <=( A200 and a12883a );
a12885a <=( a12884a and a12879a );
a12889a <=( (not A268) and (not A266) );
a12890a <=( (not A265) and a12889a );
a12894a <=( A302 and A299 );
a12895a <=( (not A298) and a12894a );
a12896a <=( a12895a and a12890a );
a12899a <=( (not A199) and A169 );
a12903a <=( (not A265) and A203 );
a12904a <=( A200 and a12903a );
a12905a <=( a12904a and a12899a );
a12909a <=( A298 and A269 );
a12910a <=( A266 and a12909a );
a12914a <=( (not A301) and (not A300) );
a12915a <=( A299 and a12914a );
a12916a <=( a12915a and a12910a );
a12919a <=( (not A199) and A169 );
a12923a <=( A265 and A203 );
a12924a <=( A200 and a12923a );
a12925a <=( a12924a and a12919a );
a12929a <=( A298 and A269 );
a12930a <=( (not A266) and a12929a );
a12934a <=( (not A301) and (not A300) );
a12935a <=( A299 and a12934a );
a12936a <=( a12935a and a12930a );
a12939a <=( A199 and A169 );
a12943a <=( (not A265) and A203 );
a12944a <=( (not A200) and a12943a );
a12945a <=( a12944a and a12939a );
a12949a <=( A298 and A269 );
a12950a <=( A266 and a12949a );
a12954a <=( (not A301) and (not A300) );
a12955a <=( A299 and a12954a );
a12956a <=( a12955a and a12950a );
a12959a <=( A199 and A169 );
a12963a <=( A265 and A203 );
a12964a <=( (not A200) and a12963a );
a12965a <=( a12964a and a12959a );
a12969a <=( A298 and A269 );
a12970a <=( (not A266) and a12969a );
a12974a <=( (not A301) and (not A300) );
a12975a <=( A299 and a12974a );
a12976a <=( a12975a and a12970a );
a12979a <=( (not A199) and A169 );
a12983a <=( A265 and (not A202) );
a12984a <=( (not A200) and a12983a );
a12985a <=( a12984a and a12979a );
a12989a <=( (not A268) and (not A267) );
a12990a <=( A266 and a12989a );
a12994a <=( A302 and (not A299) );
a12995a <=( A298 and a12994a );
a12996a <=( a12995a and a12990a );
a12999a <=( (not A199) and A169 );
a13003a <=( A265 and (not A202) );
a13004a <=( (not A200) and a13003a );
a13005a <=( a13004a and a12999a );
a13009a <=( (not A268) and (not A267) );
a13010a <=( A266 and a13009a );
a13014a <=( A302 and A299 );
a13015a <=( (not A298) and a13014a );
a13016a <=( a13015a and a13010a );
a13019a <=( (not A167) and (not A169) );
a13023a <=( A265 and A202 );
a13024a <=( (not A166) and a13023a );
a13025a <=( a13024a and a13019a );
a13029a <=( (not A268) and (not A267) );
a13030a <=( A266 and a13029a );
a13034a <=( A302 and (not A299) );
a13035a <=( A298 and a13034a );
a13036a <=( a13035a and a13030a );
a13039a <=( (not A167) and (not A169) );
a13043a <=( A265 and A202 );
a13044a <=( (not A166) and a13043a );
a13045a <=( a13044a and a13039a );
a13049a <=( (not A268) and (not A267) );
a13050a <=( A266 and a13049a );
a13054a <=( A302 and A299 );
a13055a <=( (not A298) and a13054a );
a13056a <=( a13055a and a13050a );
a13059a <=( (not A167) and (not A169) );
a13063a <=( (not A202) and (not A201) );
a13064a <=( (not A166) and a13063a );
a13065a <=( a13064a and a13059a );
a13069a <=( A298 and A268 );
a13070a <=( (not A203) and a13069a );
a13074a <=( (not A301) and (not A300) );
a13075a <=( A299 and a13074a );
a13076a <=( a13075a and a13070a );
a13079a <=( (not A167) and (not A169) );
a13083a <=( (not A202) and (not A201) );
a13084a <=( (not A166) and a13083a );
a13085a <=( a13084a and a13079a );
a13089a <=( A267 and A265 );
a13090a <=( (not A203) and a13089a );
a13094a <=( (not A302) and (not A301) );
a13095a <=( (not A300) and a13094a );
a13096a <=( a13095a and a13090a );
a13099a <=( (not A167) and (not A169) );
a13103a <=( (not A202) and (not A201) );
a13104a <=( (not A166) and a13103a );
a13105a <=( a13104a and a13099a );
a13109a <=( A267 and A265 );
a13110a <=( (not A203) and a13109a );
a13114a <=( (not A301) and (not A299) );
a13115a <=( (not A298) and a13114a );
a13116a <=( a13115a and a13110a );
a13119a <=( (not A167) and (not A169) );
a13123a <=( (not A202) and (not A201) );
a13124a <=( (not A166) and a13123a );
a13125a <=( a13124a and a13119a );
a13129a <=( A267 and A266 );
a13130a <=( (not A203) and a13129a );
a13134a <=( (not A302) and (not A301) );
a13135a <=( (not A300) and a13134a );
a13136a <=( a13135a and a13130a );
a13139a <=( (not A167) and (not A169) );
a13143a <=( (not A202) and (not A201) );
a13144a <=( (not A166) and a13143a );
a13145a <=( a13144a and a13139a );
a13149a <=( A267 and A266 );
a13150a <=( (not A203) and a13149a );
a13154a <=( (not A301) and (not A299) );
a13155a <=( (not A298) and a13154a );
a13156a <=( a13155a and a13150a );
a13159a <=( (not A167) and (not A169) );
a13163a <=( A201 and A199 );
a13164a <=( (not A166) and a13163a );
a13165a <=( a13164a and a13159a );
a13169a <=( (not A269) and (not A268) );
a13170a <=( (not A267) and a13169a );
a13174a <=( A302 and (not A299) );
a13175a <=( A298 and a13174a );
a13176a <=( a13175a and a13170a );
a13179a <=( (not A167) and (not A169) );
a13183a <=( A201 and A199 );
a13184a <=( (not A166) and a13183a );
a13185a <=( a13184a and a13179a );
a13189a <=( (not A269) and (not A268) );
a13190a <=( (not A267) and a13189a );
a13194a <=( A302 and A299 );
a13195a <=( (not A298) and a13194a );
a13196a <=( a13195a and a13190a );
a13199a <=( (not A167) and (not A169) );
a13203a <=( A201 and A199 );
a13204a <=( (not A166) and a13203a );
a13205a <=( a13204a and a13199a );
a13209a <=( (not A267) and A266 );
a13210a <=( A265 and a13209a );
a13214a <=( A300 and A299 );
a13215a <=( (not A268) and a13214a );
a13216a <=( a13215a and a13210a );
a13219a <=( (not A167) and (not A169) );
a13223a <=( A201 and A199 );
a13224a <=( (not A166) and a13223a );
a13225a <=( a13224a and a13219a );
a13229a <=( (not A267) and A266 );
a13230a <=( A265 and a13229a );
a13234a <=( A300 and A298 );
a13235a <=( (not A268) and a13234a );
a13236a <=( a13235a and a13230a );
a13239a <=( (not A167) and (not A169) );
a13243a <=( A201 and A199 );
a13244a <=( (not A166) and a13243a );
a13245a <=( a13244a and a13239a );
a13249a <=( (not A268) and (not A266) );
a13250a <=( (not A265) and a13249a );
a13254a <=( A302 and (not A299) );
a13255a <=( A298 and a13254a );
a13256a <=( a13255a and a13250a );
a13259a <=( (not A167) and (not A169) );
a13263a <=( A201 and A199 );
a13264a <=( (not A166) and a13263a );
a13265a <=( a13264a and a13259a );
a13269a <=( (not A268) and (not A266) );
a13270a <=( (not A265) and a13269a );
a13274a <=( A302 and A299 );
a13275a <=( (not A298) and a13274a );
a13276a <=( a13275a and a13270a );
a13279a <=( (not A167) and (not A169) );
a13283a <=( A201 and A200 );
a13284a <=( (not A166) and a13283a );
a13285a <=( a13284a and a13279a );
a13289a <=( (not A269) and (not A268) );
a13290a <=( (not A267) and a13289a );
a13294a <=( A302 and (not A299) );
a13295a <=( A298 and a13294a );
a13296a <=( a13295a and a13290a );
a13299a <=( (not A167) and (not A169) );
a13303a <=( A201 and A200 );
a13304a <=( (not A166) and a13303a );
a13305a <=( a13304a and a13299a );
a13309a <=( (not A269) and (not A268) );
a13310a <=( (not A267) and a13309a );
a13314a <=( A302 and A299 );
a13315a <=( (not A298) and a13314a );
a13316a <=( a13315a and a13310a );
a13319a <=( (not A167) and (not A169) );
a13323a <=( A201 and A200 );
a13324a <=( (not A166) and a13323a );
a13325a <=( a13324a and a13319a );
a13329a <=( (not A267) and A266 );
a13330a <=( A265 and a13329a );
a13334a <=( A300 and A299 );
a13335a <=( (not A268) and a13334a );
a13336a <=( a13335a and a13330a );
a13339a <=( (not A167) and (not A169) );
a13343a <=( A201 and A200 );
a13344a <=( (not A166) and a13343a );
a13345a <=( a13344a and a13339a );
a13349a <=( (not A267) and A266 );
a13350a <=( A265 and a13349a );
a13354a <=( A300 and A298 );
a13355a <=( (not A268) and a13354a );
a13356a <=( a13355a and a13350a );
a13359a <=( (not A167) and (not A169) );
a13363a <=( A201 and A200 );
a13364a <=( (not A166) and a13363a );
a13365a <=( a13364a and a13359a );
a13369a <=( (not A268) and (not A266) );
a13370a <=( (not A265) and a13369a );
a13374a <=( A302 and (not A299) );
a13375a <=( A298 and a13374a );
a13376a <=( a13375a and a13370a );
a13379a <=( (not A167) and (not A169) );
a13383a <=( A201 and A200 );
a13384a <=( (not A166) and a13383a );
a13385a <=( a13384a and a13379a );
a13389a <=( (not A268) and (not A266) );
a13390a <=( (not A265) and a13389a );
a13394a <=( A302 and A299 );
a13395a <=( (not A298) and a13394a );
a13396a <=( a13395a and a13390a );
a13399a <=( (not A167) and (not A169) );
a13403a <=( A200 and A199 );
a13404a <=( (not A166) and a13403a );
a13405a <=( a13404a and a13399a );
a13409a <=( A268 and (not A202) );
a13410a <=( (not A201) and a13409a );
a13414a <=( (not A302) and (not A301) );
a13415a <=( (not A300) and a13414a );
a13416a <=( a13415a and a13410a );
a13419a <=( (not A167) and (not A169) );
a13423a <=( A200 and A199 );
a13424a <=( (not A166) and a13423a );
a13425a <=( a13424a and a13419a );
a13429a <=( A268 and (not A202) );
a13430a <=( (not A201) and a13429a );
a13434a <=( (not A301) and (not A299) );
a13435a <=( (not A298) and a13434a );
a13436a <=( a13435a and a13430a );
a13439a <=( (not A167) and (not A169) );
a13443a <=( A200 and (not A199) );
a13444a <=( (not A166) and a13443a );
a13445a <=( a13444a and a13439a );
a13449a <=( (not A268) and (not A267) );
a13450a <=( A203 and a13449a );
a13454a <=( A300 and A299 );
a13455a <=( (not A269) and a13454a );
a13456a <=( a13455a and a13450a );
a13459a <=( (not A167) and (not A169) );
a13463a <=( A200 and (not A199) );
a13464a <=( (not A166) and a13463a );
a13465a <=( a13464a and a13459a );
a13469a <=( (not A268) and (not A267) );
a13470a <=( A203 and a13469a );
a13474a <=( A300 and A298 );
a13475a <=( (not A269) and a13474a );
a13476a <=( a13475a and a13470a );
a13479a <=( (not A167) and (not A169) );
a13483a <=( A200 and (not A199) );
a13484a <=( (not A166) and a13483a );
a13485a <=( a13484a and a13479a );
a13489a <=( A266 and A265 );
a13490a <=( A203 and a13489a );
a13494a <=( A301 and (not A268) );
a13495a <=( (not A267) and a13494a );
a13496a <=( a13495a and a13490a );
a13499a <=( (not A167) and (not A169) );
a13503a <=( A200 and (not A199) );
a13504a <=( (not A166) and a13503a );
a13505a <=( a13504a and a13499a );
a13509a <=( (not A266) and (not A265) );
a13510a <=( A203 and a13509a );
a13514a <=( A300 and A299 );
a13515a <=( (not A268) and a13514a );
a13516a <=( a13515a and a13510a );
a13519a <=( (not A167) and (not A169) );
a13523a <=( A200 and (not A199) );
a13524a <=( (not A166) and a13523a );
a13525a <=( a13524a and a13519a );
a13529a <=( (not A266) and (not A265) );
a13530a <=( A203 and a13529a );
a13534a <=( A300 and A298 );
a13535a <=( (not A268) and a13534a );
a13536a <=( a13535a and a13530a );
a13539a <=( (not A167) and (not A169) );
a13543a <=( (not A200) and A199 );
a13544a <=( (not A166) and a13543a );
a13545a <=( a13544a and a13539a );
a13549a <=( (not A268) and (not A267) );
a13550a <=( A203 and a13549a );
a13554a <=( A300 and A299 );
a13555a <=( (not A269) and a13554a );
a13556a <=( a13555a and a13550a );
a13559a <=( (not A167) and (not A169) );
a13563a <=( (not A200) and A199 );
a13564a <=( (not A166) and a13563a );
a13565a <=( a13564a and a13559a );
a13569a <=( (not A268) and (not A267) );
a13570a <=( A203 and a13569a );
a13574a <=( A300 and A298 );
a13575a <=( (not A269) and a13574a );
a13576a <=( a13575a and a13570a );
a13579a <=( (not A167) and (not A169) );
a13583a <=( (not A200) and A199 );
a13584a <=( (not A166) and a13583a );
a13585a <=( a13584a and a13579a );
a13589a <=( A266 and A265 );
a13590a <=( A203 and a13589a );
a13594a <=( A301 and (not A268) );
a13595a <=( (not A267) and a13594a );
a13596a <=( a13595a and a13590a );
a13599a <=( (not A167) and (not A169) );
a13603a <=( (not A200) and A199 );
a13604a <=( (not A166) and a13603a );
a13605a <=( a13604a and a13599a );
a13609a <=( (not A266) and (not A265) );
a13610a <=( A203 and a13609a );
a13614a <=( A300 and A299 );
a13615a <=( (not A268) and a13614a );
a13616a <=( a13615a and a13610a );
a13619a <=( (not A167) and (not A169) );
a13623a <=( (not A200) and A199 );
a13624a <=( (not A166) and a13623a );
a13625a <=( a13624a and a13619a );
a13629a <=( (not A266) and (not A265) );
a13630a <=( A203 and a13629a );
a13634a <=( A300 and A298 );
a13635a <=( (not A268) and a13634a );
a13636a <=( a13635a and a13630a );
a13639a <=( (not A167) and (not A169) );
a13643a <=( (not A200) and (not A199) );
a13644a <=( (not A166) and a13643a );
a13645a <=( a13644a and a13639a );
a13649a <=( A298 and A268 );
a13650a <=( (not A202) and a13649a );
a13654a <=( (not A301) and (not A300) );
a13655a <=( A299 and a13654a );
a13656a <=( a13655a and a13650a );
a13659a <=( (not A167) and (not A169) );
a13663a <=( (not A200) and (not A199) );
a13664a <=( (not A166) and a13663a );
a13665a <=( a13664a and a13659a );
a13669a <=( A267 and A265 );
a13670a <=( (not A202) and a13669a );
a13674a <=( (not A302) and (not A301) );
a13675a <=( (not A300) and a13674a );
a13676a <=( a13675a and a13670a );
a13679a <=( (not A167) and (not A169) );
a13683a <=( (not A200) and (not A199) );
a13684a <=( (not A166) and a13683a );
a13685a <=( a13684a and a13679a );
a13689a <=( A267 and A265 );
a13690a <=( (not A202) and a13689a );
a13694a <=( (not A301) and (not A299) );
a13695a <=( (not A298) and a13694a );
a13696a <=( a13695a and a13690a );
a13699a <=( (not A167) and (not A169) );
a13703a <=( (not A200) and (not A199) );
a13704a <=( (not A166) and a13703a );
a13705a <=( a13704a and a13699a );
a13709a <=( A267 and A266 );
a13710a <=( (not A202) and a13709a );
a13714a <=( (not A302) and (not A301) );
a13715a <=( (not A300) and a13714a );
a13716a <=( a13715a and a13710a );
a13719a <=( (not A167) and (not A169) );
a13723a <=( (not A200) and (not A199) );
a13724a <=( (not A166) and a13723a );
a13725a <=( a13724a and a13719a );
a13729a <=( A267 and A266 );
a13730a <=( (not A202) and a13729a );
a13734a <=( (not A301) and (not A299) );
a13735a <=( (not A298) and a13734a );
a13736a <=( a13735a and a13730a );
a13739a <=( (not A168) and (not A169) );
a13743a <=( A202 and A166 );
a13744a <=( A167 and a13743a );
a13745a <=( a13744a and a13739a );
a13749a <=( (not A269) and (not A268) );
a13750a <=( (not A267) and a13749a );
a13754a <=( A302 and (not A299) );
a13755a <=( A298 and a13754a );
a13756a <=( a13755a and a13750a );
a13759a <=( (not A168) and (not A169) );
a13763a <=( A202 and A166 );
a13764a <=( A167 and a13763a );
a13765a <=( a13764a and a13759a );
a13769a <=( (not A269) and (not A268) );
a13770a <=( (not A267) and a13769a );
a13774a <=( A302 and A299 );
a13775a <=( (not A298) and a13774a );
a13776a <=( a13775a and a13770a );
a13779a <=( (not A168) and (not A169) );
a13783a <=( A202 and A166 );
a13784a <=( A167 and a13783a );
a13785a <=( a13784a and a13779a );
a13789a <=( (not A267) and A266 );
a13790a <=( A265 and a13789a );
a13794a <=( A300 and A299 );
a13795a <=( (not A268) and a13794a );
a13796a <=( a13795a and a13790a );
a13799a <=( (not A168) and (not A169) );
a13803a <=( A202 and A166 );
a13804a <=( A167 and a13803a );
a13805a <=( a13804a and a13799a );
a13809a <=( (not A267) and A266 );
a13810a <=( A265 and a13809a );
a13814a <=( A300 and A298 );
a13815a <=( (not A268) and a13814a );
a13816a <=( a13815a and a13810a );
a13819a <=( (not A168) and (not A169) );
a13823a <=( A202 and A166 );
a13824a <=( A167 and a13823a );
a13825a <=( a13824a and a13819a );
a13829a <=( (not A268) and (not A266) );
a13830a <=( (not A265) and a13829a );
a13834a <=( A302 and (not A299) );
a13835a <=( A298 and a13834a );
a13836a <=( a13835a and a13830a );
a13839a <=( (not A168) and (not A169) );
a13843a <=( A202 and A166 );
a13844a <=( A167 and a13843a );
a13845a <=( a13844a and a13839a );
a13849a <=( (not A268) and (not A266) );
a13850a <=( (not A265) and a13849a );
a13854a <=( A302 and A299 );
a13855a <=( (not A298) and a13854a );
a13856a <=( a13855a and a13850a );
a13859a <=( (not A168) and (not A169) );
a13863a <=( (not A201) and A166 );
a13864a <=( A167 and a13863a );
a13865a <=( a13864a and a13859a );
a13869a <=( A268 and (not A203) );
a13870a <=( (not A202) and a13869a );
a13874a <=( (not A302) and (not A301) );
a13875a <=( (not A300) and a13874a );
a13876a <=( a13875a and a13870a );
a13879a <=( (not A168) and (not A169) );
a13883a <=( (not A201) and A166 );
a13884a <=( A167 and a13883a );
a13885a <=( a13884a and a13879a );
a13889a <=( A268 and (not A203) );
a13890a <=( (not A202) and a13889a );
a13894a <=( (not A301) and (not A299) );
a13895a <=( (not A298) and a13894a );
a13896a <=( a13895a and a13890a );
a13899a <=( (not A168) and (not A169) );
a13903a <=( A199 and A166 );
a13904a <=( A167 and a13903a );
a13905a <=( a13904a and a13899a );
a13909a <=( (not A268) and (not A267) );
a13910a <=( A201 and a13909a );
a13914a <=( A300 and A299 );
a13915a <=( (not A269) and a13914a );
a13916a <=( a13915a and a13910a );
a13919a <=( (not A168) and (not A169) );
a13923a <=( A199 and A166 );
a13924a <=( A167 and a13923a );
a13925a <=( a13924a and a13919a );
a13929a <=( (not A268) and (not A267) );
a13930a <=( A201 and a13929a );
a13934a <=( A300 and A298 );
a13935a <=( (not A269) and a13934a );
a13936a <=( a13935a and a13930a );
a13939a <=( (not A168) and (not A169) );
a13943a <=( A199 and A166 );
a13944a <=( A167 and a13943a );
a13945a <=( a13944a and a13939a );
a13949a <=( A266 and A265 );
a13950a <=( A201 and a13949a );
a13954a <=( A301 and (not A268) );
a13955a <=( (not A267) and a13954a );
a13956a <=( a13955a and a13950a );
a13959a <=( (not A168) and (not A169) );
a13963a <=( A199 and A166 );
a13964a <=( A167 and a13963a );
a13965a <=( a13964a and a13959a );
a13969a <=( (not A266) and (not A265) );
a13970a <=( A201 and a13969a );
a13974a <=( A300 and A299 );
a13975a <=( (not A268) and a13974a );
a13976a <=( a13975a and a13970a );
a13979a <=( (not A168) and (not A169) );
a13983a <=( A199 and A166 );
a13984a <=( A167 and a13983a );
a13985a <=( a13984a and a13979a );
a13989a <=( (not A266) and (not A265) );
a13990a <=( A201 and a13989a );
a13994a <=( A300 and A298 );
a13995a <=( (not A268) and a13994a );
a13996a <=( a13995a and a13990a );
a13999a <=( (not A168) and (not A169) );
a14003a <=( A200 and A166 );
a14004a <=( A167 and a14003a );
a14005a <=( a14004a and a13999a );
a14009a <=( (not A268) and (not A267) );
a14010a <=( A201 and a14009a );
a14014a <=( A300 and A299 );
a14015a <=( (not A269) and a14014a );
a14016a <=( a14015a and a14010a );
a14019a <=( (not A168) and (not A169) );
a14023a <=( A200 and A166 );
a14024a <=( A167 and a14023a );
a14025a <=( a14024a and a14019a );
a14029a <=( (not A268) and (not A267) );
a14030a <=( A201 and a14029a );
a14034a <=( A300 and A298 );
a14035a <=( (not A269) and a14034a );
a14036a <=( a14035a and a14030a );
a14039a <=( (not A168) and (not A169) );
a14043a <=( A200 and A166 );
a14044a <=( A167 and a14043a );
a14045a <=( a14044a and a14039a );
a14049a <=( A266 and A265 );
a14050a <=( A201 and a14049a );
a14054a <=( A301 and (not A268) );
a14055a <=( (not A267) and a14054a );
a14056a <=( a14055a and a14050a );
a14059a <=( (not A168) and (not A169) );
a14063a <=( A200 and A166 );
a14064a <=( A167 and a14063a );
a14065a <=( a14064a and a14059a );
a14069a <=( (not A266) and (not A265) );
a14070a <=( A201 and a14069a );
a14074a <=( A300 and A299 );
a14075a <=( (not A268) and a14074a );
a14076a <=( a14075a and a14070a );
a14079a <=( (not A168) and (not A169) );
a14083a <=( A200 and A166 );
a14084a <=( A167 and a14083a );
a14085a <=( a14084a and a14079a );
a14089a <=( (not A266) and (not A265) );
a14090a <=( A201 and a14089a );
a14094a <=( A300 and A298 );
a14095a <=( (not A268) and a14094a );
a14096a <=( a14095a and a14090a );
a14099a <=( (not A168) and (not A169) );
a14103a <=( (not A199) and A166 );
a14104a <=( A167 and a14103a );
a14105a <=( a14104a and a14099a );
a14109a <=( (not A267) and A203 );
a14110a <=( A200 and a14109a );
a14114a <=( A301 and (not A269) );
a14115a <=( (not A268) and a14114a );
a14116a <=( a14115a and a14110a );
a14119a <=( (not A168) and (not A169) );
a14123a <=( (not A199) and A166 );
a14124a <=( A167 and a14123a );
a14125a <=( a14124a and a14119a );
a14129a <=( (not A265) and A203 );
a14130a <=( A200 and a14129a );
a14134a <=( A301 and (not A268) );
a14135a <=( (not A266) and a14134a );
a14136a <=( a14135a and a14130a );
a14139a <=( (not A168) and (not A169) );
a14143a <=( A199 and A166 );
a14144a <=( A167 and a14143a );
a14145a <=( a14144a and a14139a );
a14149a <=( (not A267) and A203 );
a14150a <=( (not A200) and a14149a );
a14154a <=( A301 and (not A269) );
a14155a <=( (not A268) and a14154a );
a14156a <=( a14155a and a14150a );
a14159a <=( (not A168) and (not A169) );
a14163a <=( A199 and A166 );
a14164a <=( A167 and a14163a );
a14165a <=( a14164a and a14159a );
a14169a <=( (not A265) and A203 );
a14170a <=( (not A200) and a14169a );
a14174a <=( A301 and (not A268) );
a14175a <=( (not A266) and a14174a );
a14176a <=( a14175a and a14170a );
a14179a <=( (not A168) and (not A169) );
a14183a <=( (not A199) and A166 );
a14184a <=( A167 and a14183a );
a14185a <=( a14184a and a14179a );
a14189a <=( A268 and (not A202) );
a14190a <=( (not A200) and a14189a );
a14194a <=( (not A302) and (not A301) );
a14195a <=( (not A300) and a14194a );
a14196a <=( a14195a and a14190a );
a14199a <=( (not A168) and (not A169) );
a14203a <=( (not A199) and A166 );
a14204a <=( A167 and a14203a );
a14205a <=( a14204a and a14199a );
a14209a <=( A268 and (not A202) );
a14210a <=( (not A200) and a14209a );
a14214a <=( (not A301) and (not A299) );
a14215a <=( (not A298) and a14214a );
a14216a <=( a14215a and a14210a );
a14219a <=( (not A169) and (not A170) );
a14223a <=( A265 and A202 );
a14224a <=( (not A168) and a14223a );
a14225a <=( a14224a and a14219a );
a14229a <=( (not A268) and (not A267) );
a14230a <=( A266 and a14229a );
a14234a <=( A302 and (not A299) );
a14235a <=( A298 and a14234a );
a14236a <=( a14235a and a14230a );
a14239a <=( (not A169) and (not A170) );
a14243a <=( A265 and A202 );
a14244a <=( (not A168) and a14243a );
a14245a <=( a14244a and a14239a );
a14249a <=( (not A268) and (not A267) );
a14250a <=( A266 and a14249a );
a14254a <=( A302 and A299 );
a14255a <=( (not A298) and a14254a );
a14256a <=( a14255a and a14250a );
a14259a <=( (not A169) and (not A170) );
a14263a <=( (not A202) and (not A201) );
a14264a <=( (not A168) and a14263a );
a14265a <=( a14264a and a14259a );
a14269a <=( A298 and A268 );
a14270a <=( (not A203) and a14269a );
a14274a <=( (not A301) and (not A300) );
a14275a <=( A299 and a14274a );
a14276a <=( a14275a and a14270a );
a14279a <=( (not A169) and (not A170) );
a14283a <=( (not A202) and (not A201) );
a14284a <=( (not A168) and a14283a );
a14285a <=( a14284a and a14279a );
a14289a <=( A267 and A265 );
a14290a <=( (not A203) and a14289a );
a14294a <=( (not A302) and (not A301) );
a14295a <=( (not A300) and a14294a );
a14296a <=( a14295a and a14290a );
a14299a <=( (not A169) and (not A170) );
a14303a <=( (not A202) and (not A201) );
a14304a <=( (not A168) and a14303a );
a14305a <=( a14304a and a14299a );
a14309a <=( A267 and A265 );
a14310a <=( (not A203) and a14309a );
a14314a <=( (not A301) and (not A299) );
a14315a <=( (not A298) and a14314a );
a14316a <=( a14315a and a14310a );
a14319a <=( (not A169) and (not A170) );
a14323a <=( (not A202) and (not A201) );
a14324a <=( (not A168) and a14323a );
a14325a <=( a14324a and a14319a );
a14329a <=( A267 and A266 );
a14330a <=( (not A203) and a14329a );
a14334a <=( (not A302) and (not A301) );
a14335a <=( (not A300) and a14334a );
a14336a <=( a14335a and a14330a );
a14339a <=( (not A169) and (not A170) );
a14343a <=( (not A202) and (not A201) );
a14344a <=( (not A168) and a14343a );
a14345a <=( a14344a and a14339a );
a14349a <=( A267 and A266 );
a14350a <=( (not A203) and a14349a );
a14354a <=( (not A301) and (not A299) );
a14355a <=( (not A298) and a14354a );
a14356a <=( a14355a and a14350a );
a14359a <=( (not A169) and (not A170) );
a14363a <=( A201 and A199 );
a14364a <=( (not A168) and a14363a );
a14365a <=( a14364a and a14359a );
a14369a <=( (not A269) and (not A268) );
a14370a <=( (not A267) and a14369a );
a14374a <=( A302 and (not A299) );
a14375a <=( A298 and a14374a );
a14376a <=( a14375a and a14370a );
a14379a <=( (not A169) and (not A170) );
a14383a <=( A201 and A199 );
a14384a <=( (not A168) and a14383a );
a14385a <=( a14384a and a14379a );
a14389a <=( (not A269) and (not A268) );
a14390a <=( (not A267) and a14389a );
a14394a <=( A302 and A299 );
a14395a <=( (not A298) and a14394a );
a14396a <=( a14395a and a14390a );
a14399a <=( (not A169) and (not A170) );
a14403a <=( A201 and A199 );
a14404a <=( (not A168) and a14403a );
a14405a <=( a14404a and a14399a );
a14409a <=( (not A267) and A266 );
a14410a <=( A265 and a14409a );
a14414a <=( A300 and A299 );
a14415a <=( (not A268) and a14414a );
a14416a <=( a14415a and a14410a );
a14419a <=( (not A169) and (not A170) );
a14423a <=( A201 and A199 );
a14424a <=( (not A168) and a14423a );
a14425a <=( a14424a and a14419a );
a14429a <=( (not A267) and A266 );
a14430a <=( A265 and a14429a );
a14434a <=( A300 and A298 );
a14435a <=( (not A268) and a14434a );
a14436a <=( a14435a and a14430a );
a14439a <=( (not A169) and (not A170) );
a14443a <=( A201 and A199 );
a14444a <=( (not A168) and a14443a );
a14445a <=( a14444a and a14439a );
a14449a <=( (not A268) and (not A266) );
a14450a <=( (not A265) and a14449a );
a14454a <=( A302 and (not A299) );
a14455a <=( A298 and a14454a );
a14456a <=( a14455a and a14450a );
a14459a <=( (not A169) and (not A170) );
a14463a <=( A201 and A199 );
a14464a <=( (not A168) and a14463a );
a14465a <=( a14464a and a14459a );
a14469a <=( (not A268) and (not A266) );
a14470a <=( (not A265) and a14469a );
a14474a <=( A302 and A299 );
a14475a <=( (not A298) and a14474a );
a14476a <=( a14475a and a14470a );
a14479a <=( (not A169) and (not A170) );
a14483a <=( A201 and A200 );
a14484a <=( (not A168) and a14483a );
a14485a <=( a14484a and a14479a );
a14489a <=( (not A269) and (not A268) );
a14490a <=( (not A267) and a14489a );
a14494a <=( A302 and (not A299) );
a14495a <=( A298 and a14494a );
a14496a <=( a14495a and a14490a );
a14499a <=( (not A169) and (not A170) );
a14503a <=( A201 and A200 );
a14504a <=( (not A168) and a14503a );
a14505a <=( a14504a and a14499a );
a14509a <=( (not A269) and (not A268) );
a14510a <=( (not A267) and a14509a );
a14514a <=( A302 and A299 );
a14515a <=( (not A298) and a14514a );
a14516a <=( a14515a and a14510a );
a14519a <=( (not A169) and (not A170) );
a14523a <=( A201 and A200 );
a14524a <=( (not A168) and a14523a );
a14525a <=( a14524a and a14519a );
a14529a <=( (not A267) and A266 );
a14530a <=( A265 and a14529a );
a14534a <=( A300 and A299 );
a14535a <=( (not A268) and a14534a );
a14536a <=( a14535a and a14530a );
a14539a <=( (not A169) and (not A170) );
a14543a <=( A201 and A200 );
a14544a <=( (not A168) and a14543a );
a14545a <=( a14544a and a14539a );
a14549a <=( (not A267) and A266 );
a14550a <=( A265 and a14549a );
a14554a <=( A300 and A298 );
a14555a <=( (not A268) and a14554a );
a14556a <=( a14555a and a14550a );
a14559a <=( (not A169) and (not A170) );
a14563a <=( A201 and A200 );
a14564a <=( (not A168) and a14563a );
a14565a <=( a14564a and a14559a );
a14569a <=( (not A268) and (not A266) );
a14570a <=( (not A265) and a14569a );
a14574a <=( A302 and (not A299) );
a14575a <=( A298 and a14574a );
a14576a <=( a14575a and a14570a );
a14579a <=( (not A169) and (not A170) );
a14583a <=( A201 and A200 );
a14584a <=( (not A168) and a14583a );
a14585a <=( a14584a and a14579a );
a14589a <=( (not A268) and (not A266) );
a14590a <=( (not A265) and a14589a );
a14594a <=( A302 and A299 );
a14595a <=( (not A298) and a14594a );
a14596a <=( a14595a and a14590a );
a14599a <=( (not A169) and (not A170) );
a14603a <=( A200 and A199 );
a14604a <=( (not A168) and a14603a );
a14605a <=( a14604a and a14599a );
a14609a <=( A268 and (not A202) );
a14610a <=( (not A201) and a14609a );
a14614a <=( (not A302) and (not A301) );
a14615a <=( (not A300) and a14614a );
a14616a <=( a14615a and a14610a );
a14619a <=( (not A169) and (not A170) );
a14623a <=( A200 and A199 );
a14624a <=( (not A168) and a14623a );
a14625a <=( a14624a and a14619a );
a14629a <=( A268 and (not A202) );
a14630a <=( (not A201) and a14629a );
a14634a <=( (not A301) and (not A299) );
a14635a <=( (not A298) and a14634a );
a14636a <=( a14635a and a14630a );
a14639a <=( (not A169) and (not A170) );
a14643a <=( A200 and (not A199) );
a14644a <=( (not A168) and a14643a );
a14645a <=( a14644a and a14639a );
a14649a <=( (not A268) and (not A267) );
a14650a <=( A203 and a14649a );
a14654a <=( A300 and A299 );
a14655a <=( (not A269) and a14654a );
a14656a <=( a14655a and a14650a );
a14659a <=( (not A169) and (not A170) );
a14663a <=( A200 and (not A199) );
a14664a <=( (not A168) and a14663a );
a14665a <=( a14664a and a14659a );
a14669a <=( (not A268) and (not A267) );
a14670a <=( A203 and a14669a );
a14674a <=( A300 and A298 );
a14675a <=( (not A269) and a14674a );
a14676a <=( a14675a and a14670a );
a14679a <=( (not A169) and (not A170) );
a14683a <=( A200 and (not A199) );
a14684a <=( (not A168) and a14683a );
a14685a <=( a14684a and a14679a );
a14689a <=( A266 and A265 );
a14690a <=( A203 and a14689a );
a14694a <=( A301 and (not A268) );
a14695a <=( (not A267) and a14694a );
a14696a <=( a14695a and a14690a );
a14699a <=( (not A169) and (not A170) );
a14703a <=( A200 and (not A199) );
a14704a <=( (not A168) and a14703a );
a14705a <=( a14704a and a14699a );
a14709a <=( (not A266) and (not A265) );
a14710a <=( A203 and a14709a );
a14714a <=( A300 and A299 );
a14715a <=( (not A268) and a14714a );
a14716a <=( a14715a and a14710a );
a14719a <=( (not A169) and (not A170) );
a14723a <=( A200 and (not A199) );
a14724a <=( (not A168) and a14723a );
a14725a <=( a14724a and a14719a );
a14729a <=( (not A266) and (not A265) );
a14730a <=( A203 and a14729a );
a14734a <=( A300 and A298 );
a14735a <=( (not A268) and a14734a );
a14736a <=( a14735a and a14730a );
a14739a <=( (not A169) and (not A170) );
a14743a <=( (not A200) and A199 );
a14744a <=( (not A168) and a14743a );
a14745a <=( a14744a and a14739a );
a14749a <=( (not A268) and (not A267) );
a14750a <=( A203 and a14749a );
a14754a <=( A300 and A299 );
a14755a <=( (not A269) and a14754a );
a14756a <=( a14755a and a14750a );
a14759a <=( (not A169) and (not A170) );
a14763a <=( (not A200) and A199 );
a14764a <=( (not A168) and a14763a );
a14765a <=( a14764a and a14759a );
a14769a <=( (not A268) and (not A267) );
a14770a <=( A203 and a14769a );
a14774a <=( A300 and A298 );
a14775a <=( (not A269) and a14774a );
a14776a <=( a14775a and a14770a );
a14779a <=( (not A169) and (not A170) );
a14783a <=( (not A200) and A199 );
a14784a <=( (not A168) and a14783a );
a14785a <=( a14784a and a14779a );
a14789a <=( A266 and A265 );
a14790a <=( A203 and a14789a );
a14794a <=( A301 and (not A268) );
a14795a <=( (not A267) and a14794a );
a14796a <=( a14795a and a14790a );
a14799a <=( (not A169) and (not A170) );
a14803a <=( (not A200) and A199 );
a14804a <=( (not A168) and a14803a );
a14805a <=( a14804a and a14799a );
a14809a <=( (not A266) and (not A265) );
a14810a <=( A203 and a14809a );
a14814a <=( A300 and A299 );
a14815a <=( (not A268) and a14814a );
a14816a <=( a14815a and a14810a );
a14819a <=( (not A169) and (not A170) );
a14823a <=( (not A200) and A199 );
a14824a <=( (not A168) and a14823a );
a14825a <=( a14824a and a14819a );
a14829a <=( (not A266) and (not A265) );
a14830a <=( A203 and a14829a );
a14834a <=( A300 and A298 );
a14835a <=( (not A268) and a14834a );
a14836a <=( a14835a and a14830a );
a14839a <=( (not A169) and (not A170) );
a14843a <=( (not A200) and (not A199) );
a14844a <=( (not A168) and a14843a );
a14845a <=( a14844a and a14839a );
a14849a <=( A298 and A268 );
a14850a <=( (not A202) and a14849a );
a14854a <=( (not A301) and (not A300) );
a14855a <=( A299 and a14854a );
a14856a <=( a14855a and a14850a );
a14859a <=( (not A169) and (not A170) );
a14863a <=( (not A200) and (not A199) );
a14864a <=( (not A168) and a14863a );
a14865a <=( a14864a and a14859a );
a14869a <=( A267 and A265 );
a14870a <=( (not A202) and a14869a );
a14874a <=( (not A302) and (not A301) );
a14875a <=( (not A300) and a14874a );
a14876a <=( a14875a and a14870a );
a14879a <=( (not A169) and (not A170) );
a14883a <=( (not A200) and (not A199) );
a14884a <=( (not A168) and a14883a );
a14885a <=( a14884a and a14879a );
a14889a <=( A267 and A265 );
a14890a <=( (not A202) and a14889a );
a14894a <=( (not A301) and (not A299) );
a14895a <=( (not A298) and a14894a );
a14896a <=( a14895a and a14890a );
a14899a <=( (not A169) and (not A170) );
a14903a <=( (not A200) and (not A199) );
a14904a <=( (not A168) and a14903a );
a14905a <=( a14904a and a14899a );
a14909a <=( A267 and A266 );
a14910a <=( (not A202) and a14909a );
a14914a <=( (not A302) and (not A301) );
a14915a <=( (not A300) and a14914a );
a14916a <=( a14915a and a14910a );
a14919a <=( (not A169) and (not A170) );
a14923a <=( (not A200) and (not A199) );
a14924a <=( (not A168) and a14923a );
a14925a <=( a14924a and a14919a );
a14929a <=( A267 and A266 );
a14930a <=( (not A202) and a14929a );
a14934a <=( (not A301) and (not A299) );
a14935a <=( (not A298) and a14934a );
a14936a <=( a14935a and a14930a );
a14940a <=( (not A201) and A166 );
a14941a <=( A168 and a14940a );
a14945a <=( A265 and (not A203) );
a14946a <=( (not A202) and a14945a );
a14947a <=( a14946a and a14941a );
a14951a <=( (not A268) and (not A267) );
a14952a <=( A266 and a14951a );
a14956a <=( A302 and (not A299) );
a14957a <=( A298 and a14956a );
a14958a <=( a14957a and a14952a );
a14962a <=( (not A201) and A166 );
a14963a <=( A168 and a14962a );
a14967a <=( A265 and (not A203) );
a14968a <=( (not A202) and a14967a );
a14969a <=( a14968a and a14963a );
a14973a <=( (not A268) and (not A267) );
a14974a <=( A266 and a14973a );
a14978a <=( A302 and A299 );
a14979a <=( (not A298) and a14978a );
a14980a <=( a14979a and a14974a );
a14984a <=( A199 and A166 );
a14985a <=( A168 and a14984a );
a14989a <=( (not A202) and (not A201) );
a14990a <=( A200 and a14989a );
a14991a <=( a14990a and a14985a );
a14995a <=( (not A269) and (not A268) );
a14996a <=( (not A267) and a14995a );
a15000a <=( A302 and (not A299) );
a15001a <=( A298 and a15000a );
a15002a <=( a15001a and a14996a );
a15006a <=( A199 and A166 );
a15007a <=( A168 and a15006a );
a15011a <=( (not A202) and (not A201) );
a15012a <=( A200 and a15011a );
a15013a <=( a15012a and a15007a );
a15017a <=( (not A269) and (not A268) );
a15018a <=( (not A267) and a15017a );
a15022a <=( A302 and A299 );
a15023a <=( (not A298) and a15022a );
a15024a <=( a15023a and a15018a );
a15028a <=( A199 and A166 );
a15029a <=( A168 and a15028a );
a15033a <=( (not A202) and (not A201) );
a15034a <=( A200 and a15033a );
a15035a <=( a15034a and a15029a );
a15039a <=( (not A267) and A266 );
a15040a <=( A265 and a15039a );
a15044a <=( A300 and A299 );
a15045a <=( (not A268) and a15044a );
a15046a <=( a15045a and a15040a );
a15050a <=( A199 and A166 );
a15051a <=( A168 and a15050a );
a15055a <=( (not A202) and (not A201) );
a15056a <=( A200 and a15055a );
a15057a <=( a15056a and a15051a );
a15061a <=( (not A267) and A266 );
a15062a <=( A265 and a15061a );
a15066a <=( A300 and A298 );
a15067a <=( (not A268) and a15066a );
a15068a <=( a15067a and a15062a );
a15072a <=( A199 and A166 );
a15073a <=( A168 and a15072a );
a15077a <=( (not A202) and (not A201) );
a15078a <=( A200 and a15077a );
a15079a <=( a15078a and a15073a );
a15083a <=( (not A268) and (not A266) );
a15084a <=( (not A265) and a15083a );
a15088a <=( A302 and (not A299) );
a15089a <=( A298 and a15088a );
a15090a <=( a15089a and a15084a );
a15094a <=( A199 and A166 );
a15095a <=( A168 and a15094a );
a15099a <=( (not A202) and (not A201) );
a15100a <=( A200 and a15099a );
a15101a <=( a15100a and a15095a );
a15105a <=( (not A268) and (not A266) );
a15106a <=( (not A265) and a15105a );
a15110a <=( A302 and A299 );
a15111a <=( (not A298) and a15110a );
a15112a <=( a15111a and a15106a );
a15116a <=( (not A199) and A166 );
a15117a <=( A168 and a15116a );
a15121a <=( (not A265) and A203 );
a15122a <=( A200 and a15121a );
a15123a <=( a15122a and a15117a );
a15127a <=( A298 and A269 );
a15128a <=( A266 and a15127a );
a15132a <=( (not A301) and (not A300) );
a15133a <=( A299 and a15132a );
a15134a <=( a15133a and a15128a );
a15138a <=( (not A199) and A166 );
a15139a <=( A168 and a15138a );
a15143a <=( A265 and A203 );
a15144a <=( A200 and a15143a );
a15145a <=( a15144a and a15139a );
a15149a <=( A298 and A269 );
a15150a <=( (not A266) and a15149a );
a15154a <=( (not A301) and (not A300) );
a15155a <=( A299 and a15154a );
a15156a <=( a15155a and a15150a );
a15160a <=( A199 and A166 );
a15161a <=( A168 and a15160a );
a15165a <=( (not A265) and A203 );
a15166a <=( (not A200) and a15165a );
a15167a <=( a15166a and a15161a );
a15171a <=( A298 and A269 );
a15172a <=( A266 and a15171a );
a15176a <=( (not A301) and (not A300) );
a15177a <=( A299 and a15176a );
a15178a <=( a15177a and a15172a );
a15182a <=( A199 and A166 );
a15183a <=( A168 and a15182a );
a15187a <=( A265 and A203 );
a15188a <=( (not A200) and a15187a );
a15189a <=( a15188a and a15183a );
a15193a <=( A298 and A269 );
a15194a <=( (not A266) and a15193a );
a15198a <=( (not A301) and (not A300) );
a15199a <=( A299 and a15198a );
a15200a <=( a15199a and a15194a );
a15204a <=( (not A199) and A166 );
a15205a <=( A168 and a15204a );
a15209a <=( A265 and (not A202) );
a15210a <=( (not A200) and a15209a );
a15211a <=( a15210a and a15205a );
a15215a <=( (not A268) and (not A267) );
a15216a <=( A266 and a15215a );
a15220a <=( A302 and (not A299) );
a15221a <=( A298 and a15220a );
a15222a <=( a15221a and a15216a );
a15226a <=( (not A199) and A166 );
a15227a <=( A168 and a15226a );
a15231a <=( A265 and (not A202) );
a15232a <=( (not A200) and a15231a );
a15233a <=( a15232a and a15227a );
a15237a <=( (not A268) and (not A267) );
a15238a <=( A266 and a15237a );
a15242a <=( A302 and A299 );
a15243a <=( (not A298) and a15242a );
a15244a <=( a15243a and a15238a );
a15248a <=( (not A201) and A167 );
a15249a <=( A168 and a15248a );
a15253a <=( A265 and (not A203) );
a15254a <=( (not A202) and a15253a );
a15255a <=( a15254a and a15249a );
a15259a <=( (not A268) and (not A267) );
a15260a <=( A266 and a15259a );
a15264a <=( A302 and (not A299) );
a15265a <=( A298 and a15264a );
a15266a <=( a15265a and a15260a );
a15270a <=( (not A201) and A167 );
a15271a <=( A168 and a15270a );
a15275a <=( A265 and (not A203) );
a15276a <=( (not A202) and a15275a );
a15277a <=( a15276a and a15271a );
a15281a <=( (not A268) and (not A267) );
a15282a <=( A266 and a15281a );
a15286a <=( A302 and A299 );
a15287a <=( (not A298) and a15286a );
a15288a <=( a15287a and a15282a );
a15292a <=( A199 and A167 );
a15293a <=( A168 and a15292a );
a15297a <=( (not A202) and (not A201) );
a15298a <=( A200 and a15297a );
a15299a <=( a15298a and a15293a );
a15303a <=( (not A269) and (not A268) );
a15304a <=( (not A267) and a15303a );
a15308a <=( A302 and (not A299) );
a15309a <=( A298 and a15308a );
a15310a <=( a15309a and a15304a );
a15314a <=( A199 and A167 );
a15315a <=( A168 and a15314a );
a15319a <=( (not A202) and (not A201) );
a15320a <=( A200 and a15319a );
a15321a <=( a15320a and a15315a );
a15325a <=( (not A269) and (not A268) );
a15326a <=( (not A267) and a15325a );
a15330a <=( A302 and A299 );
a15331a <=( (not A298) and a15330a );
a15332a <=( a15331a and a15326a );
a15336a <=( A199 and A167 );
a15337a <=( A168 and a15336a );
a15341a <=( (not A202) and (not A201) );
a15342a <=( A200 and a15341a );
a15343a <=( a15342a and a15337a );
a15347a <=( (not A267) and A266 );
a15348a <=( A265 and a15347a );
a15352a <=( A300 and A299 );
a15353a <=( (not A268) and a15352a );
a15354a <=( a15353a and a15348a );
a15358a <=( A199 and A167 );
a15359a <=( A168 and a15358a );
a15363a <=( (not A202) and (not A201) );
a15364a <=( A200 and a15363a );
a15365a <=( a15364a and a15359a );
a15369a <=( (not A267) and A266 );
a15370a <=( A265 and a15369a );
a15374a <=( A300 and A298 );
a15375a <=( (not A268) and a15374a );
a15376a <=( a15375a and a15370a );
a15380a <=( A199 and A167 );
a15381a <=( A168 and a15380a );
a15385a <=( (not A202) and (not A201) );
a15386a <=( A200 and a15385a );
a15387a <=( a15386a and a15381a );
a15391a <=( (not A268) and (not A266) );
a15392a <=( (not A265) and a15391a );
a15396a <=( A302 and (not A299) );
a15397a <=( A298 and a15396a );
a15398a <=( a15397a and a15392a );
a15402a <=( A199 and A167 );
a15403a <=( A168 and a15402a );
a15407a <=( (not A202) and (not A201) );
a15408a <=( A200 and a15407a );
a15409a <=( a15408a and a15403a );
a15413a <=( (not A268) and (not A266) );
a15414a <=( (not A265) and a15413a );
a15418a <=( A302 and A299 );
a15419a <=( (not A298) and a15418a );
a15420a <=( a15419a and a15414a );
a15424a <=( (not A199) and A167 );
a15425a <=( A168 and a15424a );
a15429a <=( (not A265) and A203 );
a15430a <=( A200 and a15429a );
a15431a <=( a15430a and a15425a );
a15435a <=( A298 and A269 );
a15436a <=( A266 and a15435a );
a15440a <=( (not A301) and (not A300) );
a15441a <=( A299 and a15440a );
a15442a <=( a15441a and a15436a );
a15446a <=( (not A199) and A167 );
a15447a <=( A168 and a15446a );
a15451a <=( A265 and A203 );
a15452a <=( A200 and a15451a );
a15453a <=( a15452a and a15447a );
a15457a <=( A298 and A269 );
a15458a <=( (not A266) and a15457a );
a15462a <=( (not A301) and (not A300) );
a15463a <=( A299 and a15462a );
a15464a <=( a15463a and a15458a );
a15468a <=( A199 and A167 );
a15469a <=( A168 and a15468a );
a15473a <=( (not A265) and A203 );
a15474a <=( (not A200) and a15473a );
a15475a <=( a15474a and a15469a );
a15479a <=( A298 and A269 );
a15480a <=( A266 and a15479a );
a15484a <=( (not A301) and (not A300) );
a15485a <=( A299 and a15484a );
a15486a <=( a15485a and a15480a );
a15490a <=( A199 and A167 );
a15491a <=( A168 and a15490a );
a15495a <=( A265 and A203 );
a15496a <=( (not A200) and a15495a );
a15497a <=( a15496a and a15491a );
a15501a <=( A298 and A269 );
a15502a <=( (not A266) and a15501a );
a15506a <=( (not A301) and (not A300) );
a15507a <=( A299 and a15506a );
a15508a <=( a15507a and a15502a );
a15512a <=( (not A199) and A167 );
a15513a <=( A168 and a15512a );
a15517a <=( A265 and (not A202) );
a15518a <=( (not A200) and a15517a );
a15519a <=( a15518a and a15513a );
a15523a <=( (not A268) and (not A267) );
a15524a <=( A266 and a15523a );
a15528a <=( A302 and (not A299) );
a15529a <=( A298 and a15528a );
a15530a <=( a15529a and a15524a );
a15534a <=( (not A199) and A167 );
a15535a <=( A168 and a15534a );
a15539a <=( A265 and (not A202) );
a15540a <=( (not A200) and a15539a );
a15541a <=( a15540a and a15535a );
a15545a <=( (not A268) and (not A267) );
a15546a <=( A266 and a15545a );
a15550a <=( A302 and A299 );
a15551a <=( (not A298) and a15550a );
a15552a <=( a15551a and a15546a );
a15556a <=( (not A166) and A167 );
a15557a <=( A170 and a15556a );
a15561a <=( (not A203) and (not A202) );
a15562a <=( (not A201) and a15561a );
a15563a <=( a15562a and a15557a );
a15567a <=( (not A269) and (not A268) );
a15568a <=( (not A267) and a15567a );
a15572a <=( A302 and (not A299) );
a15573a <=( A298 and a15572a );
a15574a <=( a15573a and a15568a );
a15578a <=( (not A166) and A167 );
a15579a <=( A170 and a15578a );
a15583a <=( (not A203) and (not A202) );
a15584a <=( (not A201) and a15583a );
a15585a <=( a15584a and a15579a );
a15589a <=( (not A269) and (not A268) );
a15590a <=( (not A267) and a15589a );
a15594a <=( A302 and A299 );
a15595a <=( (not A298) and a15594a );
a15596a <=( a15595a and a15590a );
a15600a <=( (not A166) and A167 );
a15601a <=( A170 and a15600a );
a15605a <=( (not A203) and (not A202) );
a15606a <=( (not A201) and a15605a );
a15607a <=( a15606a and a15601a );
a15611a <=( (not A267) and A266 );
a15612a <=( A265 and a15611a );
a15616a <=( A300 and A299 );
a15617a <=( (not A268) and a15616a );
a15618a <=( a15617a and a15612a );
a15622a <=( (not A166) and A167 );
a15623a <=( A170 and a15622a );
a15627a <=( (not A203) and (not A202) );
a15628a <=( (not A201) and a15627a );
a15629a <=( a15628a and a15623a );
a15633a <=( (not A267) and A266 );
a15634a <=( A265 and a15633a );
a15638a <=( A300 and A298 );
a15639a <=( (not A268) and a15638a );
a15640a <=( a15639a and a15634a );
a15644a <=( (not A166) and A167 );
a15645a <=( A170 and a15644a );
a15649a <=( (not A203) and (not A202) );
a15650a <=( (not A201) and a15649a );
a15651a <=( a15650a and a15645a );
a15655a <=( (not A268) and (not A266) );
a15656a <=( (not A265) and a15655a );
a15660a <=( A302 and (not A299) );
a15661a <=( A298 and a15660a );
a15662a <=( a15661a and a15656a );
a15666a <=( (not A166) and A167 );
a15667a <=( A170 and a15666a );
a15671a <=( (not A203) and (not A202) );
a15672a <=( (not A201) and a15671a );
a15673a <=( a15672a and a15667a );
a15677a <=( (not A268) and (not A266) );
a15678a <=( (not A265) and a15677a );
a15682a <=( A302 and A299 );
a15683a <=( (not A298) and a15682a );
a15684a <=( a15683a and a15678a );
a15688a <=( (not A166) and A167 );
a15689a <=( A170 and a15688a );
a15693a <=( (not A265) and A201 );
a15694a <=( A199 and a15693a );
a15695a <=( a15694a and a15689a );
a15699a <=( A298 and A269 );
a15700a <=( A266 and a15699a );
a15704a <=( (not A301) and (not A300) );
a15705a <=( A299 and a15704a );
a15706a <=( a15705a and a15700a );
a15710a <=( (not A166) and A167 );
a15711a <=( A170 and a15710a );
a15715a <=( A265 and A201 );
a15716a <=( A199 and a15715a );
a15717a <=( a15716a and a15711a );
a15721a <=( A298 and A269 );
a15722a <=( (not A266) and a15721a );
a15726a <=( (not A301) and (not A300) );
a15727a <=( A299 and a15726a );
a15728a <=( a15727a and a15722a );
a15732a <=( (not A166) and A167 );
a15733a <=( A170 and a15732a );
a15737a <=( (not A265) and A201 );
a15738a <=( A200 and a15737a );
a15739a <=( a15738a and a15733a );
a15743a <=( A298 and A269 );
a15744a <=( A266 and a15743a );
a15748a <=( (not A301) and (not A300) );
a15749a <=( A299 and a15748a );
a15750a <=( a15749a and a15744a );
a15754a <=( (not A166) and A167 );
a15755a <=( A170 and a15754a );
a15759a <=( A265 and A201 );
a15760a <=( A200 and a15759a );
a15761a <=( a15760a and a15755a );
a15765a <=( A298 and A269 );
a15766a <=( (not A266) and a15765a );
a15770a <=( (not A301) and (not A300) );
a15771a <=( A299 and a15770a );
a15772a <=( a15771a and a15766a );
a15776a <=( (not A166) and A167 );
a15777a <=( A170 and a15776a );
a15781a <=( (not A201) and A200 );
a15782a <=( A199 and a15781a );
a15783a <=( a15782a and a15777a );
a15787a <=( (not A268) and (not A267) );
a15788a <=( (not A202) and a15787a );
a15792a <=( A300 and A299 );
a15793a <=( (not A269) and a15792a );
a15794a <=( a15793a and a15788a );
a15798a <=( (not A166) and A167 );
a15799a <=( A170 and a15798a );
a15803a <=( (not A201) and A200 );
a15804a <=( A199 and a15803a );
a15805a <=( a15804a and a15799a );
a15809a <=( (not A268) and (not A267) );
a15810a <=( (not A202) and a15809a );
a15814a <=( A300 and A298 );
a15815a <=( (not A269) and a15814a );
a15816a <=( a15815a and a15810a );
a15820a <=( (not A166) and A167 );
a15821a <=( A170 and a15820a );
a15825a <=( (not A201) and A200 );
a15826a <=( A199 and a15825a );
a15827a <=( a15826a and a15821a );
a15831a <=( A266 and A265 );
a15832a <=( (not A202) and a15831a );
a15836a <=( A301 and (not A268) );
a15837a <=( (not A267) and a15836a );
a15838a <=( a15837a and a15832a );
a15842a <=( (not A166) and A167 );
a15843a <=( A170 and a15842a );
a15847a <=( (not A201) and A200 );
a15848a <=( A199 and a15847a );
a15849a <=( a15848a and a15843a );
a15853a <=( (not A266) and (not A265) );
a15854a <=( (not A202) and a15853a );
a15858a <=( A300 and A299 );
a15859a <=( (not A268) and a15858a );
a15860a <=( a15859a and a15854a );
a15864a <=( (not A166) and A167 );
a15865a <=( A170 and a15864a );
a15869a <=( (not A201) and A200 );
a15870a <=( A199 and a15869a );
a15871a <=( a15870a and a15865a );
a15875a <=( (not A266) and (not A265) );
a15876a <=( (not A202) and a15875a );
a15880a <=( A300 and A298 );
a15881a <=( (not A268) and a15880a );
a15882a <=( a15881a and a15876a );
a15886a <=( (not A166) and A167 );
a15887a <=( A170 and a15886a );
a15891a <=( A203 and A200 );
a15892a <=( (not A199) and a15891a );
a15893a <=( a15892a and a15887a );
a15897a <=( A298 and A267 );
a15898a <=( A265 and a15897a );
a15902a <=( (not A301) and (not A300) );
a15903a <=( A299 and a15902a );
a15904a <=( a15903a and a15898a );
a15908a <=( (not A166) and A167 );
a15909a <=( A170 and a15908a );
a15913a <=( A203 and A200 );
a15914a <=( (not A199) and a15913a );
a15915a <=( a15914a and a15909a );
a15919a <=( A298 and A267 );
a15920a <=( A266 and a15919a );
a15924a <=( (not A301) and (not A300) );
a15925a <=( A299 and a15924a );
a15926a <=( a15925a and a15920a );
a15930a <=( (not A166) and A167 );
a15931a <=( A170 and a15930a );
a15935a <=( A203 and A200 );
a15936a <=( (not A199) and a15935a );
a15937a <=( a15936a and a15931a );
a15941a <=( A269 and A266 );
a15942a <=( (not A265) and a15941a );
a15946a <=( (not A302) and (not A301) );
a15947a <=( (not A300) and a15946a );
a15948a <=( a15947a and a15942a );
a15952a <=( (not A166) and A167 );
a15953a <=( A170 and a15952a );
a15957a <=( A203 and A200 );
a15958a <=( (not A199) and a15957a );
a15959a <=( a15958a and a15953a );
a15963a <=( A269 and A266 );
a15964a <=( (not A265) and a15963a );
a15968a <=( (not A301) and (not A299) );
a15969a <=( (not A298) and a15968a );
a15970a <=( a15969a and a15964a );
a15974a <=( (not A166) and A167 );
a15975a <=( A170 and a15974a );
a15979a <=( A203 and A200 );
a15980a <=( (not A199) and a15979a );
a15981a <=( a15980a and a15975a );
a15985a <=( A269 and (not A266) );
a15986a <=( A265 and a15985a );
a15990a <=( (not A302) and (not A301) );
a15991a <=( (not A300) and a15990a );
a15992a <=( a15991a and a15986a );
a15996a <=( (not A166) and A167 );
a15997a <=( A170 and a15996a );
a16001a <=( A203 and A200 );
a16002a <=( (not A199) and a16001a );
a16003a <=( a16002a and a15997a );
a16007a <=( A269 and (not A266) );
a16008a <=( A265 and a16007a );
a16012a <=( (not A301) and (not A299) );
a16013a <=( (not A298) and a16012a );
a16014a <=( a16013a and a16008a );
a16018a <=( (not A166) and A167 );
a16019a <=( A170 and a16018a );
a16023a <=( A203 and (not A200) );
a16024a <=( A199 and a16023a );
a16025a <=( a16024a and a16019a );
a16029a <=( A298 and A267 );
a16030a <=( A265 and a16029a );
a16034a <=( (not A301) and (not A300) );
a16035a <=( A299 and a16034a );
a16036a <=( a16035a and a16030a );
a16040a <=( (not A166) and A167 );
a16041a <=( A170 and a16040a );
a16045a <=( A203 and (not A200) );
a16046a <=( A199 and a16045a );
a16047a <=( a16046a and a16041a );
a16051a <=( A298 and A267 );
a16052a <=( A266 and a16051a );
a16056a <=( (not A301) and (not A300) );
a16057a <=( A299 and a16056a );
a16058a <=( a16057a and a16052a );
a16062a <=( (not A166) and A167 );
a16063a <=( A170 and a16062a );
a16067a <=( A203 and (not A200) );
a16068a <=( A199 and a16067a );
a16069a <=( a16068a and a16063a );
a16073a <=( A269 and A266 );
a16074a <=( (not A265) and a16073a );
a16078a <=( (not A302) and (not A301) );
a16079a <=( (not A300) and a16078a );
a16080a <=( a16079a and a16074a );
a16084a <=( (not A166) and A167 );
a16085a <=( A170 and a16084a );
a16089a <=( A203 and (not A200) );
a16090a <=( A199 and a16089a );
a16091a <=( a16090a and a16085a );
a16095a <=( A269 and A266 );
a16096a <=( (not A265) and a16095a );
a16100a <=( (not A301) and (not A299) );
a16101a <=( (not A298) and a16100a );
a16102a <=( a16101a and a16096a );
a16106a <=( (not A166) and A167 );
a16107a <=( A170 and a16106a );
a16111a <=( A203 and (not A200) );
a16112a <=( A199 and a16111a );
a16113a <=( a16112a and a16107a );
a16117a <=( A269 and (not A266) );
a16118a <=( A265 and a16117a );
a16122a <=( (not A302) and (not A301) );
a16123a <=( (not A300) and a16122a );
a16124a <=( a16123a and a16118a );
a16128a <=( (not A166) and A167 );
a16129a <=( A170 and a16128a );
a16133a <=( A203 and (not A200) );
a16134a <=( A199 and a16133a );
a16135a <=( a16134a and a16129a );
a16139a <=( A269 and (not A266) );
a16140a <=( A265 and a16139a );
a16144a <=( (not A301) and (not A299) );
a16145a <=( (not A298) and a16144a );
a16146a <=( a16145a and a16140a );
a16150a <=( (not A166) and A167 );
a16151a <=( A170 and a16150a );
a16155a <=( (not A202) and (not A200) );
a16156a <=( (not A199) and a16155a );
a16157a <=( a16156a and a16151a );
a16161a <=( (not A269) and (not A268) );
a16162a <=( (not A267) and a16161a );
a16166a <=( A302 and (not A299) );
a16167a <=( A298 and a16166a );
a16168a <=( a16167a and a16162a );
a16172a <=( (not A166) and A167 );
a16173a <=( A170 and a16172a );
a16177a <=( (not A202) and (not A200) );
a16178a <=( (not A199) and a16177a );
a16179a <=( a16178a and a16173a );
a16183a <=( (not A269) and (not A268) );
a16184a <=( (not A267) and a16183a );
a16188a <=( A302 and A299 );
a16189a <=( (not A298) and a16188a );
a16190a <=( a16189a and a16184a );
a16194a <=( (not A166) and A167 );
a16195a <=( A170 and a16194a );
a16199a <=( (not A202) and (not A200) );
a16200a <=( (not A199) and a16199a );
a16201a <=( a16200a and a16195a );
a16205a <=( (not A267) and A266 );
a16206a <=( A265 and a16205a );
a16210a <=( A300 and A299 );
a16211a <=( (not A268) and a16210a );
a16212a <=( a16211a and a16206a );
a16216a <=( (not A166) and A167 );
a16217a <=( A170 and a16216a );
a16221a <=( (not A202) and (not A200) );
a16222a <=( (not A199) and a16221a );
a16223a <=( a16222a and a16217a );
a16227a <=( (not A267) and A266 );
a16228a <=( A265 and a16227a );
a16232a <=( A300 and A298 );
a16233a <=( (not A268) and a16232a );
a16234a <=( a16233a and a16228a );
a16238a <=( (not A166) and A167 );
a16239a <=( A170 and a16238a );
a16243a <=( (not A202) and (not A200) );
a16244a <=( (not A199) and a16243a );
a16245a <=( a16244a and a16239a );
a16249a <=( (not A268) and (not A266) );
a16250a <=( (not A265) and a16249a );
a16254a <=( A302 and (not A299) );
a16255a <=( A298 and a16254a );
a16256a <=( a16255a and a16250a );
a16260a <=( (not A166) and A167 );
a16261a <=( A170 and a16260a );
a16265a <=( (not A202) and (not A200) );
a16266a <=( (not A199) and a16265a );
a16267a <=( a16266a and a16261a );
a16271a <=( (not A268) and (not A266) );
a16272a <=( (not A265) and a16271a );
a16276a <=( A302 and A299 );
a16277a <=( (not A298) and a16276a );
a16278a <=( a16277a and a16272a );
a16282a <=( A166 and (not A167) );
a16283a <=( A170 and a16282a );
a16287a <=( (not A203) and (not A202) );
a16288a <=( (not A201) and a16287a );
a16289a <=( a16288a and a16283a );
a16293a <=( (not A269) and (not A268) );
a16294a <=( (not A267) and a16293a );
a16298a <=( A302 and (not A299) );
a16299a <=( A298 and a16298a );
a16300a <=( a16299a and a16294a );
a16304a <=( A166 and (not A167) );
a16305a <=( A170 and a16304a );
a16309a <=( (not A203) and (not A202) );
a16310a <=( (not A201) and a16309a );
a16311a <=( a16310a and a16305a );
a16315a <=( (not A269) and (not A268) );
a16316a <=( (not A267) and a16315a );
a16320a <=( A302 and A299 );
a16321a <=( (not A298) and a16320a );
a16322a <=( a16321a and a16316a );
a16326a <=( A166 and (not A167) );
a16327a <=( A170 and a16326a );
a16331a <=( (not A203) and (not A202) );
a16332a <=( (not A201) and a16331a );
a16333a <=( a16332a and a16327a );
a16337a <=( (not A267) and A266 );
a16338a <=( A265 and a16337a );
a16342a <=( A300 and A299 );
a16343a <=( (not A268) and a16342a );
a16344a <=( a16343a and a16338a );
a16348a <=( A166 and (not A167) );
a16349a <=( A170 and a16348a );
a16353a <=( (not A203) and (not A202) );
a16354a <=( (not A201) and a16353a );
a16355a <=( a16354a and a16349a );
a16359a <=( (not A267) and A266 );
a16360a <=( A265 and a16359a );
a16364a <=( A300 and A298 );
a16365a <=( (not A268) and a16364a );
a16366a <=( a16365a and a16360a );
a16370a <=( A166 and (not A167) );
a16371a <=( A170 and a16370a );
a16375a <=( (not A203) and (not A202) );
a16376a <=( (not A201) and a16375a );
a16377a <=( a16376a and a16371a );
a16381a <=( (not A268) and (not A266) );
a16382a <=( (not A265) and a16381a );
a16386a <=( A302 and (not A299) );
a16387a <=( A298 and a16386a );
a16388a <=( a16387a and a16382a );
a16392a <=( A166 and (not A167) );
a16393a <=( A170 and a16392a );
a16397a <=( (not A203) and (not A202) );
a16398a <=( (not A201) and a16397a );
a16399a <=( a16398a and a16393a );
a16403a <=( (not A268) and (not A266) );
a16404a <=( (not A265) and a16403a );
a16408a <=( A302 and A299 );
a16409a <=( (not A298) and a16408a );
a16410a <=( a16409a and a16404a );
a16414a <=( A166 and (not A167) );
a16415a <=( A170 and a16414a );
a16419a <=( (not A265) and A201 );
a16420a <=( A199 and a16419a );
a16421a <=( a16420a and a16415a );
a16425a <=( A298 and A269 );
a16426a <=( A266 and a16425a );
a16430a <=( (not A301) and (not A300) );
a16431a <=( A299 and a16430a );
a16432a <=( a16431a and a16426a );
a16436a <=( A166 and (not A167) );
a16437a <=( A170 and a16436a );
a16441a <=( A265 and A201 );
a16442a <=( A199 and a16441a );
a16443a <=( a16442a and a16437a );
a16447a <=( A298 and A269 );
a16448a <=( (not A266) and a16447a );
a16452a <=( (not A301) and (not A300) );
a16453a <=( A299 and a16452a );
a16454a <=( a16453a and a16448a );
a16458a <=( A166 and (not A167) );
a16459a <=( A170 and a16458a );
a16463a <=( (not A265) and A201 );
a16464a <=( A200 and a16463a );
a16465a <=( a16464a and a16459a );
a16469a <=( A298 and A269 );
a16470a <=( A266 and a16469a );
a16474a <=( (not A301) and (not A300) );
a16475a <=( A299 and a16474a );
a16476a <=( a16475a and a16470a );
a16480a <=( A166 and (not A167) );
a16481a <=( A170 and a16480a );
a16485a <=( A265 and A201 );
a16486a <=( A200 and a16485a );
a16487a <=( a16486a and a16481a );
a16491a <=( A298 and A269 );
a16492a <=( (not A266) and a16491a );
a16496a <=( (not A301) and (not A300) );
a16497a <=( A299 and a16496a );
a16498a <=( a16497a and a16492a );
a16502a <=( A166 and (not A167) );
a16503a <=( A170 and a16502a );
a16507a <=( (not A201) and A200 );
a16508a <=( A199 and a16507a );
a16509a <=( a16508a and a16503a );
a16513a <=( (not A268) and (not A267) );
a16514a <=( (not A202) and a16513a );
a16518a <=( A300 and A299 );
a16519a <=( (not A269) and a16518a );
a16520a <=( a16519a and a16514a );
a16524a <=( A166 and (not A167) );
a16525a <=( A170 and a16524a );
a16529a <=( (not A201) and A200 );
a16530a <=( A199 and a16529a );
a16531a <=( a16530a and a16525a );
a16535a <=( (not A268) and (not A267) );
a16536a <=( (not A202) and a16535a );
a16540a <=( A300 and A298 );
a16541a <=( (not A269) and a16540a );
a16542a <=( a16541a and a16536a );
a16546a <=( A166 and (not A167) );
a16547a <=( A170 and a16546a );
a16551a <=( (not A201) and A200 );
a16552a <=( A199 and a16551a );
a16553a <=( a16552a and a16547a );
a16557a <=( A266 and A265 );
a16558a <=( (not A202) and a16557a );
a16562a <=( A301 and (not A268) );
a16563a <=( (not A267) and a16562a );
a16564a <=( a16563a and a16558a );
a16568a <=( A166 and (not A167) );
a16569a <=( A170 and a16568a );
a16573a <=( (not A201) and A200 );
a16574a <=( A199 and a16573a );
a16575a <=( a16574a and a16569a );
a16579a <=( (not A266) and (not A265) );
a16580a <=( (not A202) and a16579a );
a16584a <=( A300 and A299 );
a16585a <=( (not A268) and a16584a );
a16586a <=( a16585a and a16580a );
a16590a <=( A166 and (not A167) );
a16591a <=( A170 and a16590a );
a16595a <=( (not A201) and A200 );
a16596a <=( A199 and a16595a );
a16597a <=( a16596a and a16591a );
a16601a <=( (not A266) and (not A265) );
a16602a <=( (not A202) and a16601a );
a16606a <=( A300 and A298 );
a16607a <=( (not A268) and a16606a );
a16608a <=( a16607a and a16602a );
a16612a <=( A166 and (not A167) );
a16613a <=( A170 and a16612a );
a16617a <=( A203 and A200 );
a16618a <=( (not A199) and a16617a );
a16619a <=( a16618a and a16613a );
a16623a <=( A298 and A267 );
a16624a <=( A265 and a16623a );
a16628a <=( (not A301) and (not A300) );
a16629a <=( A299 and a16628a );
a16630a <=( a16629a and a16624a );
a16634a <=( A166 and (not A167) );
a16635a <=( A170 and a16634a );
a16639a <=( A203 and A200 );
a16640a <=( (not A199) and a16639a );
a16641a <=( a16640a and a16635a );
a16645a <=( A298 and A267 );
a16646a <=( A266 and a16645a );
a16650a <=( (not A301) and (not A300) );
a16651a <=( A299 and a16650a );
a16652a <=( a16651a and a16646a );
a16656a <=( A166 and (not A167) );
a16657a <=( A170 and a16656a );
a16661a <=( A203 and A200 );
a16662a <=( (not A199) and a16661a );
a16663a <=( a16662a and a16657a );
a16667a <=( A269 and A266 );
a16668a <=( (not A265) and a16667a );
a16672a <=( (not A302) and (not A301) );
a16673a <=( (not A300) and a16672a );
a16674a <=( a16673a and a16668a );
a16678a <=( A166 and (not A167) );
a16679a <=( A170 and a16678a );
a16683a <=( A203 and A200 );
a16684a <=( (not A199) and a16683a );
a16685a <=( a16684a and a16679a );
a16689a <=( A269 and A266 );
a16690a <=( (not A265) and a16689a );
a16694a <=( (not A301) and (not A299) );
a16695a <=( (not A298) and a16694a );
a16696a <=( a16695a and a16690a );
a16700a <=( A166 and (not A167) );
a16701a <=( A170 and a16700a );
a16705a <=( A203 and A200 );
a16706a <=( (not A199) and a16705a );
a16707a <=( a16706a and a16701a );
a16711a <=( A269 and (not A266) );
a16712a <=( A265 and a16711a );
a16716a <=( (not A302) and (not A301) );
a16717a <=( (not A300) and a16716a );
a16718a <=( a16717a and a16712a );
a16722a <=( A166 and (not A167) );
a16723a <=( A170 and a16722a );
a16727a <=( A203 and A200 );
a16728a <=( (not A199) and a16727a );
a16729a <=( a16728a and a16723a );
a16733a <=( A269 and (not A266) );
a16734a <=( A265 and a16733a );
a16738a <=( (not A301) and (not A299) );
a16739a <=( (not A298) and a16738a );
a16740a <=( a16739a and a16734a );
a16744a <=( A166 and (not A167) );
a16745a <=( A170 and a16744a );
a16749a <=( A203 and (not A200) );
a16750a <=( A199 and a16749a );
a16751a <=( a16750a and a16745a );
a16755a <=( A298 and A267 );
a16756a <=( A265 and a16755a );
a16760a <=( (not A301) and (not A300) );
a16761a <=( A299 and a16760a );
a16762a <=( a16761a and a16756a );
a16766a <=( A166 and (not A167) );
a16767a <=( A170 and a16766a );
a16771a <=( A203 and (not A200) );
a16772a <=( A199 and a16771a );
a16773a <=( a16772a and a16767a );
a16777a <=( A298 and A267 );
a16778a <=( A266 and a16777a );
a16782a <=( (not A301) and (not A300) );
a16783a <=( A299 and a16782a );
a16784a <=( a16783a and a16778a );
a16788a <=( A166 and (not A167) );
a16789a <=( A170 and a16788a );
a16793a <=( A203 and (not A200) );
a16794a <=( A199 and a16793a );
a16795a <=( a16794a and a16789a );
a16799a <=( A269 and A266 );
a16800a <=( (not A265) and a16799a );
a16804a <=( (not A302) and (not A301) );
a16805a <=( (not A300) and a16804a );
a16806a <=( a16805a and a16800a );
a16810a <=( A166 and (not A167) );
a16811a <=( A170 and a16810a );
a16815a <=( A203 and (not A200) );
a16816a <=( A199 and a16815a );
a16817a <=( a16816a and a16811a );
a16821a <=( A269 and A266 );
a16822a <=( (not A265) and a16821a );
a16826a <=( (not A301) and (not A299) );
a16827a <=( (not A298) and a16826a );
a16828a <=( a16827a and a16822a );
a16832a <=( A166 and (not A167) );
a16833a <=( A170 and a16832a );
a16837a <=( A203 and (not A200) );
a16838a <=( A199 and a16837a );
a16839a <=( a16838a and a16833a );
a16843a <=( A269 and (not A266) );
a16844a <=( A265 and a16843a );
a16848a <=( (not A302) and (not A301) );
a16849a <=( (not A300) and a16848a );
a16850a <=( a16849a and a16844a );
a16854a <=( A166 and (not A167) );
a16855a <=( A170 and a16854a );
a16859a <=( A203 and (not A200) );
a16860a <=( A199 and a16859a );
a16861a <=( a16860a and a16855a );
a16865a <=( A269 and (not A266) );
a16866a <=( A265 and a16865a );
a16870a <=( (not A301) and (not A299) );
a16871a <=( (not A298) and a16870a );
a16872a <=( a16871a and a16866a );
a16876a <=( A166 and (not A167) );
a16877a <=( A170 and a16876a );
a16881a <=( (not A202) and (not A200) );
a16882a <=( (not A199) and a16881a );
a16883a <=( a16882a and a16877a );
a16887a <=( (not A269) and (not A268) );
a16888a <=( (not A267) and a16887a );
a16892a <=( A302 and (not A299) );
a16893a <=( A298 and a16892a );
a16894a <=( a16893a and a16888a );
a16898a <=( A166 and (not A167) );
a16899a <=( A170 and a16898a );
a16903a <=( (not A202) and (not A200) );
a16904a <=( (not A199) and a16903a );
a16905a <=( a16904a and a16899a );
a16909a <=( (not A269) and (not A268) );
a16910a <=( (not A267) and a16909a );
a16914a <=( A302 and A299 );
a16915a <=( (not A298) and a16914a );
a16916a <=( a16915a and a16910a );
a16920a <=( A166 and (not A167) );
a16921a <=( A170 and a16920a );
a16925a <=( (not A202) and (not A200) );
a16926a <=( (not A199) and a16925a );
a16927a <=( a16926a and a16921a );
a16931a <=( (not A267) and A266 );
a16932a <=( A265 and a16931a );
a16936a <=( A300 and A299 );
a16937a <=( (not A268) and a16936a );
a16938a <=( a16937a and a16932a );
a16942a <=( A166 and (not A167) );
a16943a <=( A170 and a16942a );
a16947a <=( (not A202) and (not A200) );
a16948a <=( (not A199) and a16947a );
a16949a <=( a16948a and a16943a );
a16953a <=( (not A267) and A266 );
a16954a <=( A265 and a16953a );
a16958a <=( A300 and A298 );
a16959a <=( (not A268) and a16958a );
a16960a <=( a16959a and a16954a );
a16964a <=( A166 and (not A167) );
a16965a <=( A170 and a16964a );
a16969a <=( (not A202) and (not A200) );
a16970a <=( (not A199) and a16969a );
a16971a <=( a16970a and a16965a );
a16975a <=( (not A268) and (not A266) );
a16976a <=( (not A265) and a16975a );
a16980a <=( A302 and (not A299) );
a16981a <=( A298 and a16980a );
a16982a <=( a16981a and a16976a );
a16986a <=( A166 and (not A167) );
a16987a <=( A170 and a16986a );
a16991a <=( (not A202) and (not A200) );
a16992a <=( (not A199) and a16991a );
a16993a <=( a16992a and a16987a );
a16997a <=( (not A268) and (not A266) );
a16998a <=( (not A265) and a16997a );
a17002a <=( A302 and A299 );
a17003a <=( (not A298) and a17002a );
a17004a <=( a17003a and a16998a );
a17008a <=( A200 and A199 );
a17009a <=( A169 and a17008a );
a17013a <=( A265 and (not A202) );
a17014a <=( (not A201) and a17013a );
a17015a <=( a17014a and a17009a );
a17019a <=( (not A268) and (not A267) );
a17020a <=( A266 and a17019a );
a17024a <=( A302 and (not A299) );
a17025a <=( A298 and a17024a );
a17026a <=( a17025a and a17020a );
a17030a <=( A200 and A199 );
a17031a <=( A169 and a17030a );
a17035a <=( A265 and (not A202) );
a17036a <=( (not A201) and a17035a );
a17037a <=( a17036a and a17031a );
a17041a <=( (not A268) and (not A267) );
a17042a <=( A266 and a17041a );
a17046a <=( A302 and A299 );
a17047a <=( (not A298) and a17046a );
a17048a <=( a17047a and a17042a );
a17052a <=( (not A166) and (not A167) );
a17053a <=( (not A169) and a17052a );
a17057a <=( (not A203) and (not A202) );
a17058a <=( (not A201) and a17057a );
a17059a <=( a17058a and a17053a );
a17063a <=( A298 and A267 );
a17064a <=( A265 and a17063a );
a17068a <=( (not A301) and (not A300) );
a17069a <=( A299 and a17068a );
a17070a <=( a17069a and a17064a );
a17074a <=( (not A166) and (not A167) );
a17075a <=( (not A169) and a17074a );
a17079a <=( (not A203) and (not A202) );
a17080a <=( (not A201) and a17079a );
a17081a <=( a17080a and a17075a );
a17085a <=( A298 and A267 );
a17086a <=( A266 and a17085a );
a17090a <=( (not A301) and (not A300) );
a17091a <=( A299 and a17090a );
a17092a <=( a17091a and a17086a );
a17096a <=( (not A166) and (not A167) );
a17097a <=( (not A169) and a17096a );
a17101a <=( (not A203) and (not A202) );
a17102a <=( (not A201) and a17101a );
a17103a <=( a17102a and a17097a );
a17107a <=( A269 and A266 );
a17108a <=( (not A265) and a17107a );
a17112a <=( (not A302) and (not A301) );
a17113a <=( (not A300) and a17112a );
a17114a <=( a17113a and a17108a );
a17118a <=( (not A166) and (not A167) );
a17119a <=( (not A169) and a17118a );
a17123a <=( (not A203) and (not A202) );
a17124a <=( (not A201) and a17123a );
a17125a <=( a17124a and a17119a );
a17129a <=( A269 and A266 );
a17130a <=( (not A265) and a17129a );
a17134a <=( (not A301) and (not A299) );
a17135a <=( (not A298) and a17134a );
a17136a <=( a17135a and a17130a );
a17140a <=( (not A166) and (not A167) );
a17141a <=( (not A169) and a17140a );
a17145a <=( (not A203) and (not A202) );
a17146a <=( (not A201) and a17145a );
a17147a <=( a17146a and a17141a );
a17151a <=( A269 and (not A266) );
a17152a <=( A265 and a17151a );
a17156a <=( (not A302) and (not A301) );
a17157a <=( (not A300) and a17156a );
a17158a <=( a17157a and a17152a );
a17162a <=( (not A166) and (not A167) );
a17163a <=( (not A169) and a17162a );
a17167a <=( (not A203) and (not A202) );
a17168a <=( (not A201) and a17167a );
a17169a <=( a17168a and a17163a );
a17173a <=( A269 and (not A266) );
a17174a <=( A265 and a17173a );
a17178a <=( (not A301) and (not A299) );
a17179a <=( (not A298) and a17178a );
a17180a <=( a17179a and a17174a );
a17184a <=( (not A166) and (not A167) );
a17185a <=( (not A169) and a17184a );
a17189a <=( A265 and A201 );
a17190a <=( A199 and a17189a );
a17191a <=( a17190a and a17185a );
a17195a <=( (not A268) and (not A267) );
a17196a <=( A266 and a17195a );
a17200a <=( A302 and (not A299) );
a17201a <=( A298 and a17200a );
a17202a <=( a17201a and a17196a );
a17206a <=( (not A166) and (not A167) );
a17207a <=( (not A169) and a17206a );
a17211a <=( A265 and A201 );
a17212a <=( A199 and a17211a );
a17213a <=( a17212a and a17207a );
a17217a <=( (not A268) and (not A267) );
a17218a <=( A266 and a17217a );
a17222a <=( A302 and A299 );
a17223a <=( (not A298) and a17222a );
a17224a <=( a17223a and a17218a );
a17228a <=( (not A166) and (not A167) );
a17229a <=( (not A169) and a17228a );
a17233a <=( A265 and A201 );
a17234a <=( A200 and a17233a );
a17235a <=( a17234a and a17229a );
a17239a <=( (not A268) and (not A267) );
a17240a <=( A266 and a17239a );
a17244a <=( A302 and (not A299) );
a17245a <=( A298 and a17244a );
a17246a <=( a17245a and a17240a );
a17250a <=( (not A166) and (not A167) );
a17251a <=( (not A169) and a17250a );
a17255a <=( A265 and A201 );
a17256a <=( A200 and a17255a );
a17257a <=( a17256a and a17251a );
a17261a <=( (not A268) and (not A267) );
a17262a <=( A266 and a17261a );
a17266a <=( A302 and A299 );
a17267a <=( (not A298) and a17266a );
a17268a <=( a17267a and a17262a );
a17272a <=( (not A166) and (not A167) );
a17273a <=( (not A169) and a17272a );
a17277a <=( (not A201) and A200 );
a17278a <=( A199 and a17277a );
a17279a <=( a17278a and a17273a );
a17283a <=( A298 and A268 );
a17284a <=( (not A202) and a17283a );
a17288a <=( (not A301) and (not A300) );
a17289a <=( A299 and a17288a );
a17290a <=( a17289a and a17284a );
a17294a <=( (not A166) and (not A167) );
a17295a <=( (not A169) and a17294a );
a17299a <=( (not A201) and A200 );
a17300a <=( A199 and a17299a );
a17301a <=( a17300a and a17295a );
a17305a <=( A267 and A265 );
a17306a <=( (not A202) and a17305a );
a17310a <=( (not A302) and (not A301) );
a17311a <=( (not A300) and a17310a );
a17312a <=( a17311a and a17306a );
a17316a <=( (not A166) and (not A167) );
a17317a <=( (not A169) and a17316a );
a17321a <=( (not A201) and A200 );
a17322a <=( A199 and a17321a );
a17323a <=( a17322a and a17317a );
a17327a <=( A267 and A265 );
a17328a <=( (not A202) and a17327a );
a17332a <=( (not A301) and (not A299) );
a17333a <=( (not A298) and a17332a );
a17334a <=( a17333a and a17328a );
a17338a <=( (not A166) and (not A167) );
a17339a <=( (not A169) and a17338a );
a17343a <=( (not A201) and A200 );
a17344a <=( A199 and a17343a );
a17345a <=( a17344a and a17339a );
a17349a <=( A267 and A266 );
a17350a <=( (not A202) and a17349a );
a17354a <=( (not A302) and (not A301) );
a17355a <=( (not A300) and a17354a );
a17356a <=( a17355a and a17350a );
a17360a <=( (not A166) and (not A167) );
a17361a <=( (not A169) and a17360a );
a17365a <=( (not A201) and A200 );
a17366a <=( A199 and a17365a );
a17367a <=( a17366a and a17361a );
a17371a <=( A267 and A266 );
a17372a <=( (not A202) and a17371a );
a17376a <=( (not A301) and (not A299) );
a17377a <=( (not A298) and a17376a );
a17378a <=( a17377a and a17372a );
a17382a <=( (not A166) and (not A167) );
a17383a <=( (not A169) and a17382a );
a17387a <=( A203 and A200 );
a17388a <=( (not A199) and a17387a );
a17389a <=( a17388a and a17383a );
a17393a <=( (not A269) and (not A268) );
a17394a <=( (not A267) and a17393a );
a17398a <=( A302 and (not A299) );
a17399a <=( A298 and a17398a );
a17400a <=( a17399a and a17394a );
a17404a <=( (not A166) and (not A167) );
a17405a <=( (not A169) and a17404a );
a17409a <=( A203 and A200 );
a17410a <=( (not A199) and a17409a );
a17411a <=( a17410a and a17405a );
a17415a <=( (not A269) and (not A268) );
a17416a <=( (not A267) and a17415a );
a17420a <=( A302 and A299 );
a17421a <=( (not A298) and a17420a );
a17422a <=( a17421a and a17416a );
a17426a <=( (not A166) and (not A167) );
a17427a <=( (not A169) and a17426a );
a17431a <=( A203 and A200 );
a17432a <=( (not A199) and a17431a );
a17433a <=( a17432a and a17427a );
a17437a <=( (not A267) and A266 );
a17438a <=( A265 and a17437a );
a17442a <=( A300 and A299 );
a17443a <=( (not A268) and a17442a );
a17444a <=( a17443a and a17438a );
a17448a <=( (not A166) and (not A167) );
a17449a <=( (not A169) and a17448a );
a17453a <=( A203 and A200 );
a17454a <=( (not A199) and a17453a );
a17455a <=( a17454a and a17449a );
a17459a <=( (not A267) and A266 );
a17460a <=( A265 and a17459a );
a17464a <=( A300 and A298 );
a17465a <=( (not A268) and a17464a );
a17466a <=( a17465a and a17460a );
a17470a <=( (not A166) and (not A167) );
a17471a <=( (not A169) and a17470a );
a17475a <=( A203 and A200 );
a17476a <=( (not A199) and a17475a );
a17477a <=( a17476a and a17471a );
a17481a <=( (not A268) and (not A266) );
a17482a <=( (not A265) and a17481a );
a17486a <=( A302 and (not A299) );
a17487a <=( A298 and a17486a );
a17488a <=( a17487a and a17482a );
a17492a <=( (not A166) and (not A167) );
a17493a <=( (not A169) and a17492a );
a17497a <=( A203 and A200 );
a17498a <=( (not A199) and a17497a );
a17499a <=( a17498a and a17493a );
a17503a <=( (not A268) and (not A266) );
a17504a <=( (not A265) and a17503a );
a17508a <=( A302 and A299 );
a17509a <=( (not A298) and a17508a );
a17510a <=( a17509a and a17504a );
a17514a <=( (not A166) and (not A167) );
a17515a <=( (not A169) and a17514a );
a17519a <=( A203 and (not A200) );
a17520a <=( A199 and a17519a );
a17521a <=( a17520a and a17515a );
a17525a <=( (not A269) and (not A268) );
a17526a <=( (not A267) and a17525a );
a17530a <=( A302 and (not A299) );
a17531a <=( A298 and a17530a );
a17532a <=( a17531a and a17526a );
a17536a <=( (not A166) and (not A167) );
a17537a <=( (not A169) and a17536a );
a17541a <=( A203 and (not A200) );
a17542a <=( A199 and a17541a );
a17543a <=( a17542a and a17537a );
a17547a <=( (not A269) and (not A268) );
a17548a <=( (not A267) and a17547a );
a17552a <=( A302 and A299 );
a17553a <=( (not A298) and a17552a );
a17554a <=( a17553a and a17548a );
a17558a <=( (not A166) and (not A167) );
a17559a <=( (not A169) and a17558a );
a17563a <=( A203 and (not A200) );
a17564a <=( A199 and a17563a );
a17565a <=( a17564a and a17559a );
a17569a <=( (not A267) and A266 );
a17570a <=( A265 and a17569a );
a17574a <=( A300 and A299 );
a17575a <=( (not A268) and a17574a );
a17576a <=( a17575a and a17570a );
a17580a <=( (not A166) and (not A167) );
a17581a <=( (not A169) and a17580a );
a17585a <=( A203 and (not A200) );
a17586a <=( A199 and a17585a );
a17587a <=( a17586a and a17581a );
a17591a <=( (not A267) and A266 );
a17592a <=( A265 and a17591a );
a17596a <=( A300 and A298 );
a17597a <=( (not A268) and a17596a );
a17598a <=( a17597a and a17592a );
a17602a <=( (not A166) and (not A167) );
a17603a <=( (not A169) and a17602a );
a17607a <=( A203 and (not A200) );
a17608a <=( A199 and a17607a );
a17609a <=( a17608a and a17603a );
a17613a <=( (not A268) and (not A266) );
a17614a <=( (not A265) and a17613a );
a17618a <=( A302 and (not A299) );
a17619a <=( A298 and a17618a );
a17620a <=( a17619a and a17614a );
a17624a <=( (not A166) and (not A167) );
a17625a <=( (not A169) and a17624a );
a17629a <=( A203 and (not A200) );
a17630a <=( A199 and a17629a );
a17631a <=( a17630a and a17625a );
a17635a <=( (not A268) and (not A266) );
a17636a <=( (not A265) and a17635a );
a17640a <=( A302 and A299 );
a17641a <=( (not A298) and a17640a );
a17642a <=( a17641a and a17636a );
a17646a <=( (not A166) and (not A167) );
a17647a <=( (not A169) and a17646a );
a17651a <=( (not A202) and (not A200) );
a17652a <=( (not A199) and a17651a );
a17653a <=( a17652a and a17647a );
a17657a <=( A298 and A267 );
a17658a <=( A265 and a17657a );
a17662a <=( (not A301) and (not A300) );
a17663a <=( A299 and a17662a );
a17664a <=( a17663a and a17658a );
a17668a <=( (not A166) and (not A167) );
a17669a <=( (not A169) and a17668a );
a17673a <=( (not A202) and (not A200) );
a17674a <=( (not A199) and a17673a );
a17675a <=( a17674a and a17669a );
a17679a <=( A298 and A267 );
a17680a <=( A266 and a17679a );
a17684a <=( (not A301) and (not A300) );
a17685a <=( A299 and a17684a );
a17686a <=( a17685a and a17680a );
a17690a <=( (not A166) and (not A167) );
a17691a <=( (not A169) and a17690a );
a17695a <=( (not A202) and (not A200) );
a17696a <=( (not A199) and a17695a );
a17697a <=( a17696a and a17691a );
a17701a <=( A269 and A266 );
a17702a <=( (not A265) and a17701a );
a17706a <=( (not A302) and (not A301) );
a17707a <=( (not A300) and a17706a );
a17708a <=( a17707a and a17702a );
a17712a <=( (not A166) and (not A167) );
a17713a <=( (not A169) and a17712a );
a17717a <=( (not A202) and (not A200) );
a17718a <=( (not A199) and a17717a );
a17719a <=( a17718a and a17713a );
a17723a <=( A269 and A266 );
a17724a <=( (not A265) and a17723a );
a17728a <=( (not A301) and (not A299) );
a17729a <=( (not A298) and a17728a );
a17730a <=( a17729a and a17724a );
a17734a <=( (not A166) and (not A167) );
a17735a <=( (not A169) and a17734a );
a17739a <=( (not A202) and (not A200) );
a17740a <=( (not A199) and a17739a );
a17741a <=( a17740a and a17735a );
a17745a <=( A269 and (not A266) );
a17746a <=( A265 and a17745a );
a17750a <=( (not A302) and (not A301) );
a17751a <=( (not A300) and a17750a );
a17752a <=( a17751a and a17746a );
a17756a <=( (not A166) and (not A167) );
a17757a <=( (not A169) and a17756a );
a17761a <=( (not A202) and (not A200) );
a17762a <=( (not A199) and a17761a );
a17763a <=( a17762a and a17757a );
a17767a <=( A269 and (not A266) );
a17768a <=( A265 and a17767a );
a17772a <=( (not A301) and (not A299) );
a17773a <=( (not A298) and a17772a );
a17774a <=( a17773a and a17768a );
a17778a <=( A167 and (not A168) );
a17779a <=( (not A169) and a17778a );
a17783a <=( A265 and A202 );
a17784a <=( A166 and a17783a );
a17785a <=( a17784a and a17779a );
a17789a <=( (not A268) and (not A267) );
a17790a <=( A266 and a17789a );
a17794a <=( A302 and (not A299) );
a17795a <=( A298 and a17794a );
a17796a <=( a17795a and a17790a );
a17800a <=( A167 and (not A168) );
a17801a <=( (not A169) and a17800a );
a17805a <=( A265 and A202 );
a17806a <=( A166 and a17805a );
a17807a <=( a17806a and a17801a );
a17811a <=( (not A268) and (not A267) );
a17812a <=( A266 and a17811a );
a17816a <=( A302 and A299 );
a17817a <=( (not A298) and a17816a );
a17818a <=( a17817a and a17812a );
a17822a <=( A167 and (not A168) );
a17823a <=( (not A169) and a17822a );
a17827a <=( (not A202) and (not A201) );
a17828a <=( A166 and a17827a );
a17829a <=( a17828a and a17823a );
a17833a <=( A298 and A268 );
a17834a <=( (not A203) and a17833a );
a17838a <=( (not A301) and (not A300) );
a17839a <=( A299 and a17838a );
a17840a <=( a17839a and a17834a );
a17844a <=( A167 and (not A168) );
a17845a <=( (not A169) and a17844a );
a17849a <=( (not A202) and (not A201) );
a17850a <=( A166 and a17849a );
a17851a <=( a17850a and a17845a );
a17855a <=( A267 and A265 );
a17856a <=( (not A203) and a17855a );
a17860a <=( (not A302) and (not A301) );
a17861a <=( (not A300) and a17860a );
a17862a <=( a17861a and a17856a );
a17866a <=( A167 and (not A168) );
a17867a <=( (not A169) and a17866a );
a17871a <=( (not A202) and (not A201) );
a17872a <=( A166 and a17871a );
a17873a <=( a17872a and a17867a );
a17877a <=( A267 and A265 );
a17878a <=( (not A203) and a17877a );
a17882a <=( (not A301) and (not A299) );
a17883a <=( (not A298) and a17882a );
a17884a <=( a17883a and a17878a );
a17888a <=( A167 and (not A168) );
a17889a <=( (not A169) and a17888a );
a17893a <=( (not A202) and (not A201) );
a17894a <=( A166 and a17893a );
a17895a <=( a17894a and a17889a );
a17899a <=( A267 and A266 );
a17900a <=( (not A203) and a17899a );
a17904a <=( (not A302) and (not A301) );
a17905a <=( (not A300) and a17904a );
a17906a <=( a17905a and a17900a );
a17910a <=( A167 and (not A168) );
a17911a <=( (not A169) and a17910a );
a17915a <=( (not A202) and (not A201) );
a17916a <=( A166 and a17915a );
a17917a <=( a17916a and a17911a );
a17921a <=( A267 and A266 );
a17922a <=( (not A203) and a17921a );
a17926a <=( (not A301) and (not A299) );
a17927a <=( (not A298) and a17926a );
a17928a <=( a17927a and a17922a );
a17932a <=( A167 and (not A168) );
a17933a <=( (not A169) and a17932a );
a17937a <=( A201 and A199 );
a17938a <=( A166 and a17937a );
a17939a <=( a17938a and a17933a );
a17943a <=( (not A269) and (not A268) );
a17944a <=( (not A267) and a17943a );
a17948a <=( A302 and (not A299) );
a17949a <=( A298 and a17948a );
a17950a <=( a17949a and a17944a );
a17954a <=( A167 and (not A168) );
a17955a <=( (not A169) and a17954a );
a17959a <=( A201 and A199 );
a17960a <=( A166 and a17959a );
a17961a <=( a17960a and a17955a );
a17965a <=( (not A269) and (not A268) );
a17966a <=( (not A267) and a17965a );
a17970a <=( A302 and A299 );
a17971a <=( (not A298) and a17970a );
a17972a <=( a17971a and a17966a );
a17976a <=( A167 and (not A168) );
a17977a <=( (not A169) and a17976a );
a17981a <=( A201 and A199 );
a17982a <=( A166 and a17981a );
a17983a <=( a17982a and a17977a );
a17987a <=( (not A267) and A266 );
a17988a <=( A265 and a17987a );
a17992a <=( A300 and A299 );
a17993a <=( (not A268) and a17992a );
a17994a <=( a17993a and a17988a );
a17998a <=( A167 and (not A168) );
a17999a <=( (not A169) and a17998a );
a18003a <=( A201 and A199 );
a18004a <=( A166 and a18003a );
a18005a <=( a18004a and a17999a );
a18009a <=( (not A267) and A266 );
a18010a <=( A265 and a18009a );
a18014a <=( A300 and A298 );
a18015a <=( (not A268) and a18014a );
a18016a <=( a18015a and a18010a );
a18020a <=( A167 and (not A168) );
a18021a <=( (not A169) and a18020a );
a18025a <=( A201 and A199 );
a18026a <=( A166 and a18025a );
a18027a <=( a18026a and a18021a );
a18031a <=( (not A268) and (not A266) );
a18032a <=( (not A265) and a18031a );
a18036a <=( A302 and (not A299) );
a18037a <=( A298 and a18036a );
a18038a <=( a18037a and a18032a );
a18042a <=( A167 and (not A168) );
a18043a <=( (not A169) and a18042a );
a18047a <=( A201 and A199 );
a18048a <=( A166 and a18047a );
a18049a <=( a18048a and a18043a );
a18053a <=( (not A268) and (not A266) );
a18054a <=( (not A265) and a18053a );
a18058a <=( A302 and A299 );
a18059a <=( (not A298) and a18058a );
a18060a <=( a18059a and a18054a );
a18064a <=( A167 and (not A168) );
a18065a <=( (not A169) and a18064a );
a18069a <=( A201 and A200 );
a18070a <=( A166 and a18069a );
a18071a <=( a18070a and a18065a );
a18075a <=( (not A269) and (not A268) );
a18076a <=( (not A267) and a18075a );
a18080a <=( A302 and (not A299) );
a18081a <=( A298 and a18080a );
a18082a <=( a18081a and a18076a );
a18086a <=( A167 and (not A168) );
a18087a <=( (not A169) and a18086a );
a18091a <=( A201 and A200 );
a18092a <=( A166 and a18091a );
a18093a <=( a18092a and a18087a );
a18097a <=( (not A269) and (not A268) );
a18098a <=( (not A267) and a18097a );
a18102a <=( A302 and A299 );
a18103a <=( (not A298) and a18102a );
a18104a <=( a18103a and a18098a );
a18108a <=( A167 and (not A168) );
a18109a <=( (not A169) and a18108a );
a18113a <=( A201 and A200 );
a18114a <=( A166 and a18113a );
a18115a <=( a18114a and a18109a );
a18119a <=( (not A267) and A266 );
a18120a <=( A265 and a18119a );
a18124a <=( A300 and A299 );
a18125a <=( (not A268) and a18124a );
a18126a <=( a18125a and a18120a );
a18130a <=( A167 and (not A168) );
a18131a <=( (not A169) and a18130a );
a18135a <=( A201 and A200 );
a18136a <=( A166 and a18135a );
a18137a <=( a18136a and a18131a );
a18141a <=( (not A267) and A266 );
a18142a <=( A265 and a18141a );
a18146a <=( A300 and A298 );
a18147a <=( (not A268) and a18146a );
a18148a <=( a18147a and a18142a );
a18152a <=( A167 and (not A168) );
a18153a <=( (not A169) and a18152a );
a18157a <=( A201 and A200 );
a18158a <=( A166 and a18157a );
a18159a <=( a18158a and a18153a );
a18163a <=( (not A268) and (not A266) );
a18164a <=( (not A265) and a18163a );
a18168a <=( A302 and (not A299) );
a18169a <=( A298 and a18168a );
a18170a <=( a18169a and a18164a );
a18174a <=( A167 and (not A168) );
a18175a <=( (not A169) and a18174a );
a18179a <=( A201 and A200 );
a18180a <=( A166 and a18179a );
a18181a <=( a18180a and a18175a );
a18185a <=( (not A268) and (not A266) );
a18186a <=( (not A265) and a18185a );
a18190a <=( A302 and A299 );
a18191a <=( (not A298) and a18190a );
a18192a <=( a18191a and a18186a );
a18196a <=( A167 and (not A168) );
a18197a <=( (not A169) and a18196a );
a18201a <=( A200 and A199 );
a18202a <=( A166 and a18201a );
a18203a <=( a18202a and a18197a );
a18207a <=( A268 and (not A202) );
a18208a <=( (not A201) and a18207a );
a18212a <=( (not A302) and (not A301) );
a18213a <=( (not A300) and a18212a );
a18214a <=( a18213a and a18208a );
a18218a <=( A167 and (not A168) );
a18219a <=( (not A169) and a18218a );
a18223a <=( A200 and A199 );
a18224a <=( A166 and a18223a );
a18225a <=( a18224a and a18219a );
a18229a <=( A268 and (not A202) );
a18230a <=( (not A201) and a18229a );
a18234a <=( (not A301) and (not A299) );
a18235a <=( (not A298) and a18234a );
a18236a <=( a18235a and a18230a );
a18240a <=( A167 and (not A168) );
a18241a <=( (not A169) and a18240a );
a18245a <=( A200 and (not A199) );
a18246a <=( A166 and a18245a );
a18247a <=( a18246a and a18241a );
a18251a <=( (not A268) and (not A267) );
a18252a <=( A203 and a18251a );
a18256a <=( A300 and A299 );
a18257a <=( (not A269) and a18256a );
a18258a <=( a18257a and a18252a );
a18262a <=( A167 and (not A168) );
a18263a <=( (not A169) and a18262a );
a18267a <=( A200 and (not A199) );
a18268a <=( A166 and a18267a );
a18269a <=( a18268a and a18263a );
a18273a <=( (not A268) and (not A267) );
a18274a <=( A203 and a18273a );
a18278a <=( A300 and A298 );
a18279a <=( (not A269) and a18278a );
a18280a <=( a18279a and a18274a );
a18284a <=( A167 and (not A168) );
a18285a <=( (not A169) and a18284a );
a18289a <=( A200 and (not A199) );
a18290a <=( A166 and a18289a );
a18291a <=( a18290a and a18285a );
a18295a <=( A266 and A265 );
a18296a <=( A203 and a18295a );
a18300a <=( A301 and (not A268) );
a18301a <=( (not A267) and a18300a );
a18302a <=( a18301a and a18296a );
a18306a <=( A167 and (not A168) );
a18307a <=( (not A169) and a18306a );
a18311a <=( A200 and (not A199) );
a18312a <=( A166 and a18311a );
a18313a <=( a18312a and a18307a );
a18317a <=( (not A266) and (not A265) );
a18318a <=( A203 and a18317a );
a18322a <=( A300 and A299 );
a18323a <=( (not A268) and a18322a );
a18324a <=( a18323a and a18318a );
a18328a <=( A167 and (not A168) );
a18329a <=( (not A169) and a18328a );
a18333a <=( A200 and (not A199) );
a18334a <=( A166 and a18333a );
a18335a <=( a18334a and a18329a );
a18339a <=( (not A266) and (not A265) );
a18340a <=( A203 and a18339a );
a18344a <=( A300 and A298 );
a18345a <=( (not A268) and a18344a );
a18346a <=( a18345a and a18340a );
a18350a <=( A167 and (not A168) );
a18351a <=( (not A169) and a18350a );
a18355a <=( (not A200) and A199 );
a18356a <=( A166 and a18355a );
a18357a <=( a18356a and a18351a );
a18361a <=( (not A268) and (not A267) );
a18362a <=( A203 and a18361a );
a18366a <=( A300 and A299 );
a18367a <=( (not A269) and a18366a );
a18368a <=( a18367a and a18362a );
a18372a <=( A167 and (not A168) );
a18373a <=( (not A169) and a18372a );
a18377a <=( (not A200) and A199 );
a18378a <=( A166 and a18377a );
a18379a <=( a18378a and a18373a );
a18383a <=( (not A268) and (not A267) );
a18384a <=( A203 and a18383a );
a18388a <=( A300 and A298 );
a18389a <=( (not A269) and a18388a );
a18390a <=( a18389a and a18384a );
a18394a <=( A167 and (not A168) );
a18395a <=( (not A169) and a18394a );
a18399a <=( (not A200) and A199 );
a18400a <=( A166 and a18399a );
a18401a <=( a18400a and a18395a );
a18405a <=( A266 and A265 );
a18406a <=( A203 and a18405a );
a18410a <=( A301 and (not A268) );
a18411a <=( (not A267) and a18410a );
a18412a <=( a18411a and a18406a );
a18416a <=( A167 and (not A168) );
a18417a <=( (not A169) and a18416a );
a18421a <=( (not A200) and A199 );
a18422a <=( A166 and a18421a );
a18423a <=( a18422a and a18417a );
a18427a <=( (not A266) and (not A265) );
a18428a <=( A203 and a18427a );
a18432a <=( A300 and A299 );
a18433a <=( (not A268) and a18432a );
a18434a <=( a18433a and a18428a );
a18438a <=( A167 and (not A168) );
a18439a <=( (not A169) and a18438a );
a18443a <=( (not A200) and A199 );
a18444a <=( A166 and a18443a );
a18445a <=( a18444a and a18439a );
a18449a <=( (not A266) and (not A265) );
a18450a <=( A203 and a18449a );
a18454a <=( A300 and A298 );
a18455a <=( (not A268) and a18454a );
a18456a <=( a18455a and a18450a );
a18460a <=( A167 and (not A168) );
a18461a <=( (not A169) and a18460a );
a18465a <=( (not A200) and (not A199) );
a18466a <=( A166 and a18465a );
a18467a <=( a18466a and a18461a );
a18471a <=( A298 and A268 );
a18472a <=( (not A202) and a18471a );
a18476a <=( (not A301) and (not A300) );
a18477a <=( A299 and a18476a );
a18478a <=( a18477a and a18472a );
a18482a <=( A167 and (not A168) );
a18483a <=( (not A169) and a18482a );
a18487a <=( (not A200) and (not A199) );
a18488a <=( A166 and a18487a );
a18489a <=( a18488a and a18483a );
a18493a <=( A267 and A265 );
a18494a <=( (not A202) and a18493a );
a18498a <=( (not A302) and (not A301) );
a18499a <=( (not A300) and a18498a );
a18500a <=( a18499a and a18494a );
a18504a <=( A167 and (not A168) );
a18505a <=( (not A169) and a18504a );
a18509a <=( (not A200) and (not A199) );
a18510a <=( A166 and a18509a );
a18511a <=( a18510a and a18505a );
a18515a <=( A267 and A265 );
a18516a <=( (not A202) and a18515a );
a18520a <=( (not A301) and (not A299) );
a18521a <=( (not A298) and a18520a );
a18522a <=( a18521a and a18516a );
a18526a <=( A167 and (not A168) );
a18527a <=( (not A169) and a18526a );
a18531a <=( (not A200) and (not A199) );
a18532a <=( A166 and a18531a );
a18533a <=( a18532a and a18527a );
a18537a <=( A267 and A266 );
a18538a <=( (not A202) and a18537a );
a18542a <=( (not A302) and (not A301) );
a18543a <=( (not A300) and a18542a );
a18544a <=( a18543a and a18538a );
a18548a <=( A167 and (not A168) );
a18549a <=( (not A169) and a18548a );
a18553a <=( (not A200) and (not A199) );
a18554a <=( A166 and a18553a );
a18555a <=( a18554a and a18549a );
a18559a <=( A267 and A266 );
a18560a <=( (not A202) and a18559a );
a18564a <=( (not A301) and (not A299) );
a18565a <=( (not A298) and a18564a );
a18566a <=( a18565a and a18560a );
a18570a <=( (not A168) and (not A169) );
a18571a <=( (not A170) and a18570a );
a18575a <=( (not A203) and (not A202) );
a18576a <=( (not A201) and a18575a );
a18577a <=( a18576a and a18571a );
a18581a <=( A298 and A267 );
a18582a <=( A265 and a18581a );
a18586a <=( (not A301) and (not A300) );
a18587a <=( A299 and a18586a );
a18588a <=( a18587a and a18582a );
a18592a <=( (not A168) and (not A169) );
a18593a <=( (not A170) and a18592a );
a18597a <=( (not A203) and (not A202) );
a18598a <=( (not A201) and a18597a );
a18599a <=( a18598a and a18593a );
a18603a <=( A298 and A267 );
a18604a <=( A266 and a18603a );
a18608a <=( (not A301) and (not A300) );
a18609a <=( A299 and a18608a );
a18610a <=( a18609a and a18604a );
a18614a <=( (not A168) and (not A169) );
a18615a <=( (not A170) and a18614a );
a18619a <=( (not A203) and (not A202) );
a18620a <=( (not A201) and a18619a );
a18621a <=( a18620a and a18615a );
a18625a <=( A269 and A266 );
a18626a <=( (not A265) and a18625a );
a18630a <=( (not A302) and (not A301) );
a18631a <=( (not A300) and a18630a );
a18632a <=( a18631a and a18626a );
a18636a <=( (not A168) and (not A169) );
a18637a <=( (not A170) and a18636a );
a18641a <=( (not A203) and (not A202) );
a18642a <=( (not A201) and a18641a );
a18643a <=( a18642a and a18637a );
a18647a <=( A269 and A266 );
a18648a <=( (not A265) and a18647a );
a18652a <=( (not A301) and (not A299) );
a18653a <=( (not A298) and a18652a );
a18654a <=( a18653a and a18648a );
a18658a <=( (not A168) and (not A169) );
a18659a <=( (not A170) and a18658a );
a18663a <=( (not A203) and (not A202) );
a18664a <=( (not A201) and a18663a );
a18665a <=( a18664a and a18659a );
a18669a <=( A269 and (not A266) );
a18670a <=( A265 and a18669a );
a18674a <=( (not A302) and (not A301) );
a18675a <=( (not A300) and a18674a );
a18676a <=( a18675a and a18670a );
a18680a <=( (not A168) and (not A169) );
a18681a <=( (not A170) and a18680a );
a18685a <=( (not A203) and (not A202) );
a18686a <=( (not A201) and a18685a );
a18687a <=( a18686a and a18681a );
a18691a <=( A269 and (not A266) );
a18692a <=( A265 and a18691a );
a18696a <=( (not A301) and (not A299) );
a18697a <=( (not A298) and a18696a );
a18698a <=( a18697a and a18692a );
a18702a <=( (not A168) and (not A169) );
a18703a <=( (not A170) and a18702a );
a18707a <=( A265 and A201 );
a18708a <=( A199 and a18707a );
a18709a <=( a18708a and a18703a );
a18713a <=( (not A268) and (not A267) );
a18714a <=( A266 and a18713a );
a18718a <=( A302 and (not A299) );
a18719a <=( A298 and a18718a );
a18720a <=( a18719a and a18714a );
a18724a <=( (not A168) and (not A169) );
a18725a <=( (not A170) and a18724a );
a18729a <=( A265 and A201 );
a18730a <=( A199 and a18729a );
a18731a <=( a18730a and a18725a );
a18735a <=( (not A268) and (not A267) );
a18736a <=( A266 and a18735a );
a18740a <=( A302 and A299 );
a18741a <=( (not A298) and a18740a );
a18742a <=( a18741a and a18736a );
a18746a <=( (not A168) and (not A169) );
a18747a <=( (not A170) and a18746a );
a18751a <=( A265 and A201 );
a18752a <=( A200 and a18751a );
a18753a <=( a18752a and a18747a );
a18757a <=( (not A268) and (not A267) );
a18758a <=( A266 and a18757a );
a18762a <=( A302 and (not A299) );
a18763a <=( A298 and a18762a );
a18764a <=( a18763a and a18758a );
a18768a <=( (not A168) and (not A169) );
a18769a <=( (not A170) and a18768a );
a18773a <=( A265 and A201 );
a18774a <=( A200 and a18773a );
a18775a <=( a18774a and a18769a );
a18779a <=( (not A268) and (not A267) );
a18780a <=( A266 and a18779a );
a18784a <=( A302 and A299 );
a18785a <=( (not A298) and a18784a );
a18786a <=( a18785a and a18780a );
a18790a <=( (not A168) and (not A169) );
a18791a <=( (not A170) and a18790a );
a18795a <=( (not A201) and A200 );
a18796a <=( A199 and a18795a );
a18797a <=( a18796a and a18791a );
a18801a <=( A298 and A268 );
a18802a <=( (not A202) and a18801a );
a18806a <=( (not A301) and (not A300) );
a18807a <=( A299 and a18806a );
a18808a <=( a18807a and a18802a );
a18812a <=( (not A168) and (not A169) );
a18813a <=( (not A170) and a18812a );
a18817a <=( (not A201) and A200 );
a18818a <=( A199 and a18817a );
a18819a <=( a18818a and a18813a );
a18823a <=( A267 and A265 );
a18824a <=( (not A202) and a18823a );
a18828a <=( (not A302) and (not A301) );
a18829a <=( (not A300) and a18828a );
a18830a <=( a18829a and a18824a );
a18834a <=( (not A168) and (not A169) );
a18835a <=( (not A170) and a18834a );
a18839a <=( (not A201) and A200 );
a18840a <=( A199 and a18839a );
a18841a <=( a18840a and a18835a );
a18845a <=( A267 and A265 );
a18846a <=( (not A202) and a18845a );
a18850a <=( (not A301) and (not A299) );
a18851a <=( (not A298) and a18850a );
a18852a <=( a18851a and a18846a );
a18856a <=( (not A168) and (not A169) );
a18857a <=( (not A170) and a18856a );
a18861a <=( (not A201) and A200 );
a18862a <=( A199 and a18861a );
a18863a <=( a18862a and a18857a );
a18867a <=( A267 and A266 );
a18868a <=( (not A202) and a18867a );
a18872a <=( (not A302) and (not A301) );
a18873a <=( (not A300) and a18872a );
a18874a <=( a18873a and a18868a );
a18878a <=( (not A168) and (not A169) );
a18879a <=( (not A170) and a18878a );
a18883a <=( (not A201) and A200 );
a18884a <=( A199 and a18883a );
a18885a <=( a18884a and a18879a );
a18889a <=( A267 and A266 );
a18890a <=( (not A202) and a18889a );
a18894a <=( (not A301) and (not A299) );
a18895a <=( (not A298) and a18894a );
a18896a <=( a18895a and a18890a );
a18900a <=( (not A168) and (not A169) );
a18901a <=( (not A170) and a18900a );
a18905a <=( A203 and A200 );
a18906a <=( (not A199) and a18905a );
a18907a <=( a18906a and a18901a );
a18911a <=( (not A269) and (not A268) );
a18912a <=( (not A267) and a18911a );
a18916a <=( A302 and (not A299) );
a18917a <=( A298 and a18916a );
a18918a <=( a18917a and a18912a );
a18922a <=( (not A168) and (not A169) );
a18923a <=( (not A170) and a18922a );
a18927a <=( A203 and A200 );
a18928a <=( (not A199) and a18927a );
a18929a <=( a18928a and a18923a );
a18933a <=( (not A269) and (not A268) );
a18934a <=( (not A267) and a18933a );
a18938a <=( A302 and A299 );
a18939a <=( (not A298) and a18938a );
a18940a <=( a18939a and a18934a );
a18944a <=( (not A168) and (not A169) );
a18945a <=( (not A170) and a18944a );
a18949a <=( A203 and A200 );
a18950a <=( (not A199) and a18949a );
a18951a <=( a18950a and a18945a );
a18955a <=( (not A267) and A266 );
a18956a <=( A265 and a18955a );
a18960a <=( A300 and A299 );
a18961a <=( (not A268) and a18960a );
a18962a <=( a18961a and a18956a );
a18966a <=( (not A168) and (not A169) );
a18967a <=( (not A170) and a18966a );
a18971a <=( A203 and A200 );
a18972a <=( (not A199) and a18971a );
a18973a <=( a18972a and a18967a );
a18977a <=( (not A267) and A266 );
a18978a <=( A265 and a18977a );
a18982a <=( A300 and A298 );
a18983a <=( (not A268) and a18982a );
a18984a <=( a18983a and a18978a );
a18988a <=( (not A168) and (not A169) );
a18989a <=( (not A170) and a18988a );
a18993a <=( A203 and A200 );
a18994a <=( (not A199) and a18993a );
a18995a <=( a18994a and a18989a );
a18999a <=( (not A268) and (not A266) );
a19000a <=( (not A265) and a18999a );
a19004a <=( A302 and (not A299) );
a19005a <=( A298 and a19004a );
a19006a <=( a19005a and a19000a );
a19010a <=( (not A168) and (not A169) );
a19011a <=( (not A170) and a19010a );
a19015a <=( A203 and A200 );
a19016a <=( (not A199) and a19015a );
a19017a <=( a19016a and a19011a );
a19021a <=( (not A268) and (not A266) );
a19022a <=( (not A265) and a19021a );
a19026a <=( A302 and A299 );
a19027a <=( (not A298) and a19026a );
a19028a <=( a19027a and a19022a );
a19032a <=( (not A168) and (not A169) );
a19033a <=( (not A170) and a19032a );
a19037a <=( A203 and (not A200) );
a19038a <=( A199 and a19037a );
a19039a <=( a19038a and a19033a );
a19043a <=( (not A269) and (not A268) );
a19044a <=( (not A267) and a19043a );
a19048a <=( A302 and (not A299) );
a19049a <=( A298 and a19048a );
a19050a <=( a19049a and a19044a );
a19054a <=( (not A168) and (not A169) );
a19055a <=( (not A170) and a19054a );
a19059a <=( A203 and (not A200) );
a19060a <=( A199 and a19059a );
a19061a <=( a19060a and a19055a );
a19065a <=( (not A269) and (not A268) );
a19066a <=( (not A267) and a19065a );
a19070a <=( A302 and A299 );
a19071a <=( (not A298) and a19070a );
a19072a <=( a19071a and a19066a );
a19076a <=( (not A168) and (not A169) );
a19077a <=( (not A170) and a19076a );
a19081a <=( A203 and (not A200) );
a19082a <=( A199 and a19081a );
a19083a <=( a19082a and a19077a );
a19087a <=( (not A267) and A266 );
a19088a <=( A265 and a19087a );
a19092a <=( A300 and A299 );
a19093a <=( (not A268) and a19092a );
a19094a <=( a19093a and a19088a );
a19098a <=( (not A168) and (not A169) );
a19099a <=( (not A170) and a19098a );
a19103a <=( A203 and (not A200) );
a19104a <=( A199 and a19103a );
a19105a <=( a19104a and a19099a );
a19109a <=( (not A267) and A266 );
a19110a <=( A265 and a19109a );
a19114a <=( A300 and A298 );
a19115a <=( (not A268) and a19114a );
a19116a <=( a19115a and a19110a );
a19120a <=( (not A168) and (not A169) );
a19121a <=( (not A170) and a19120a );
a19125a <=( A203 and (not A200) );
a19126a <=( A199 and a19125a );
a19127a <=( a19126a and a19121a );
a19131a <=( (not A268) and (not A266) );
a19132a <=( (not A265) and a19131a );
a19136a <=( A302 and (not A299) );
a19137a <=( A298 and a19136a );
a19138a <=( a19137a and a19132a );
a19142a <=( (not A168) and (not A169) );
a19143a <=( (not A170) and a19142a );
a19147a <=( A203 and (not A200) );
a19148a <=( A199 and a19147a );
a19149a <=( a19148a and a19143a );
a19153a <=( (not A268) and (not A266) );
a19154a <=( (not A265) and a19153a );
a19158a <=( A302 and A299 );
a19159a <=( (not A298) and a19158a );
a19160a <=( a19159a and a19154a );
a19164a <=( (not A168) and (not A169) );
a19165a <=( (not A170) and a19164a );
a19169a <=( (not A202) and (not A200) );
a19170a <=( (not A199) and a19169a );
a19171a <=( a19170a and a19165a );
a19175a <=( A298 and A267 );
a19176a <=( A265 and a19175a );
a19180a <=( (not A301) and (not A300) );
a19181a <=( A299 and a19180a );
a19182a <=( a19181a and a19176a );
a19186a <=( (not A168) and (not A169) );
a19187a <=( (not A170) and a19186a );
a19191a <=( (not A202) and (not A200) );
a19192a <=( (not A199) and a19191a );
a19193a <=( a19192a and a19187a );
a19197a <=( A298 and A267 );
a19198a <=( A266 and a19197a );
a19202a <=( (not A301) and (not A300) );
a19203a <=( A299 and a19202a );
a19204a <=( a19203a and a19198a );
a19208a <=( (not A168) and (not A169) );
a19209a <=( (not A170) and a19208a );
a19213a <=( (not A202) and (not A200) );
a19214a <=( (not A199) and a19213a );
a19215a <=( a19214a and a19209a );
a19219a <=( A269 and A266 );
a19220a <=( (not A265) and a19219a );
a19224a <=( (not A302) and (not A301) );
a19225a <=( (not A300) and a19224a );
a19226a <=( a19225a and a19220a );
a19230a <=( (not A168) and (not A169) );
a19231a <=( (not A170) and a19230a );
a19235a <=( (not A202) and (not A200) );
a19236a <=( (not A199) and a19235a );
a19237a <=( a19236a and a19231a );
a19241a <=( A269 and A266 );
a19242a <=( (not A265) and a19241a );
a19246a <=( (not A301) and (not A299) );
a19247a <=( (not A298) and a19246a );
a19248a <=( a19247a and a19242a );
a19252a <=( (not A168) and (not A169) );
a19253a <=( (not A170) and a19252a );
a19257a <=( (not A202) and (not A200) );
a19258a <=( (not A199) and a19257a );
a19259a <=( a19258a and a19253a );
a19263a <=( A269 and (not A266) );
a19264a <=( A265 and a19263a );
a19268a <=( (not A302) and (not A301) );
a19269a <=( (not A300) and a19268a );
a19270a <=( a19269a and a19264a );
a19274a <=( (not A168) and (not A169) );
a19275a <=( (not A170) and a19274a );
a19279a <=( (not A202) and (not A200) );
a19280a <=( (not A199) and a19279a );
a19281a <=( a19280a and a19275a );
a19285a <=( A269 and (not A266) );
a19286a <=( A265 and a19285a );
a19290a <=( (not A301) and (not A299) );
a19291a <=( (not A298) and a19290a );
a19292a <=( a19291a and a19286a );
a19296a <=( A199 and A166 );
a19297a <=( A168 and a19296a );
a19301a <=( (not A202) and (not A201) );
a19302a <=( A200 and a19301a );
a19303a <=( a19302a and a19297a );
a19307a <=( (not A267) and A266 );
a19308a <=( A265 and a19307a );
a19311a <=( A298 and (not A268) );
a19314a <=( A302 and (not A299) );
a19315a <=( a19314a and a19311a );
a19316a <=( a19315a and a19308a );
a19320a <=( A199 and A166 );
a19321a <=( A168 and a19320a );
a19325a <=( (not A202) and (not A201) );
a19326a <=( A200 and a19325a );
a19327a <=( a19326a and a19321a );
a19331a <=( (not A267) and A266 );
a19332a <=( A265 and a19331a );
a19335a <=( (not A298) and (not A268) );
a19338a <=( A302 and A299 );
a19339a <=( a19338a and a19335a );
a19340a <=( a19339a and a19332a );
a19344a <=( A199 and A167 );
a19345a <=( A168 and a19344a );
a19349a <=( (not A202) and (not A201) );
a19350a <=( A200 and a19349a );
a19351a <=( a19350a and a19345a );
a19355a <=( (not A267) and A266 );
a19356a <=( A265 and a19355a );
a19359a <=( A298 and (not A268) );
a19362a <=( A302 and (not A299) );
a19363a <=( a19362a and a19359a );
a19364a <=( a19363a and a19356a );
a19368a <=( A199 and A167 );
a19369a <=( A168 and a19368a );
a19373a <=( (not A202) and (not A201) );
a19374a <=( A200 and a19373a );
a19375a <=( a19374a and a19369a );
a19379a <=( (not A267) and A266 );
a19380a <=( A265 and a19379a );
a19383a <=( (not A298) and (not A268) );
a19386a <=( A302 and A299 );
a19387a <=( a19386a and a19383a );
a19388a <=( a19387a and a19380a );
a19392a <=( (not A166) and A167 );
a19393a <=( A170 and a19392a );
a19397a <=( (not A203) and (not A202) );
a19398a <=( (not A201) and a19397a );
a19399a <=( a19398a and a19393a );
a19403a <=( (not A267) and A266 );
a19404a <=( A265 and a19403a );
a19407a <=( A298 and (not A268) );
a19410a <=( A302 and (not A299) );
a19411a <=( a19410a and a19407a );
a19412a <=( a19411a and a19404a );
a19416a <=( (not A166) and A167 );
a19417a <=( A170 and a19416a );
a19421a <=( (not A203) and (not A202) );
a19422a <=( (not A201) and a19421a );
a19423a <=( a19422a and a19417a );
a19427a <=( (not A267) and A266 );
a19428a <=( A265 and a19427a );
a19431a <=( (not A298) and (not A268) );
a19434a <=( A302 and A299 );
a19435a <=( a19434a and a19431a );
a19436a <=( a19435a and a19428a );
a19440a <=( (not A166) and A167 );
a19441a <=( A170 and a19440a );
a19445a <=( (not A201) and A200 );
a19446a <=( A199 and a19445a );
a19447a <=( a19446a and a19441a );
a19451a <=( (not A268) and (not A267) );
a19452a <=( (not A202) and a19451a );
a19455a <=( A298 and (not A269) );
a19458a <=( A302 and (not A299) );
a19459a <=( a19458a and a19455a );
a19460a <=( a19459a and a19452a );
a19464a <=( (not A166) and A167 );
a19465a <=( A170 and a19464a );
a19469a <=( (not A201) and A200 );
a19470a <=( A199 and a19469a );
a19471a <=( a19470a and a19465a );
a19475a <=( (not A268) and (not A267) );
a19476a <=( (not A202) and a19475a );
a19479a <=( (not A298) and (not A269) );
a19482a <=( A302 and A299 );
a19483a <=( a19482a and a19479a );
a19484a <=( a19483a and a19476a );
a19488a <=( (not A166) and A167 );
a19489a <=( A170 and a19488a );
a19493a <=( (not A201) and A200 );
a19494a <=( A199 and a19493a );
a19495a <=( a19494a and a19489a );
a19499a <=( A266 and A265 );
a19500a <=( (not A202) and a19499a );
a19503a <=( (not A268) and (not A267) );
a19506a <=( A300 and A299 );
a19507a <=( a19506a and a19503a );
a19508a <=( a19507a and a19500a );
a19512a <=( (not A166) and A167 );
a19513a <=( A170 and a19512a );
a19517a <=( (not A201) and A200 );
a19518a <=( A199 and a19517a );
a19519a <=( a19518a and a19513a );
a19523a <=( A266 and A265 );
a19524a <=( (not A202) and a19523a );
a19527a <=( (not A268) and (not A267) );
a19530a <=( A300 and A298 );
a19531a <=( a19530a and a19527a );
a19532a <=( a19531a and a19524a );
a19536a <=( (not A166) and A167 );
a19537a <=( A170 and a19536a );
a19541a <=( (not A201) and A200 );
a19542a <=( A199 and a19541a );
a19543a <=( a19542a and a19537a );
a19547a <=( (not A266) and (not A265) );
a19548a <=( (not A202) and a19547a );
a19551a <=( A298 and (not A268) );
a19554a <=( A302 and (not A299) );
a19555a <=( a19554a and a19551a );
a19556a <=( a19555a and a19548a );
a19560a <=( (not A166) and A167 );
a19561a <=( A170 and a19560a );
a19565a <=( (not A201) and A200 );
a19566a <=( A199 and a19565a );
a19567a <=( a19566a and a19561a );
a19571a <=( (not A266) and (not A265) );
a19572a <=( (not A202) and a19571a );
a19575a <=( (not A298) and (not A268) );
a19578a <=( A302 and A299 );
a19579a <=( a19578a and a19575a );
a19580a <=( a19579a and a19572a );
a19584a <=( (not A166) and A167 );
a19585a <=( A170 and a19584a );
a19589a <=( A203 and A200 );
a19590a <=( (not A199) and a19589a );
a19591a <=( a19590a and a19585a );
a19595a <=( A269 and A266 );
a19596a <=( (not A265) and a19595a );
a19599a <=( A299 and A298 );
a19602a <=( (not A301) and (not A300) );
a19603a <=( a19602a and a19599a );
a19604a <=( a19603a and a19596a );
a19608a <=( (not A166) and A167 );
a19609a <=( A170 and a19608a );
a19613a <=( A203 and A200 );
a19614a <=( (not A199) and a19613a );
a19615a <=( a19614a and a19609a );
a19619a <=( A269 and (not A266) );
a19620a <=( A265 and a19619a );
a19623a <=( A299 and A298 );
a19626a <=( (not A301) and (not A300) );
a19627a <=( a19626a and a19623a );
a19628a <=( a19627a and a19620a );
a19632a <=( (not A166) and A167 );
a19633a <=( A170 and a19632a );
a19637a <=( A203 and (not A200) );
a19638a <=( A199 and a19637a );
a19639a <=( a19638a and a19633a );
a19643a <=( A269 and A266 );
a19644a <=( (not A265) and a19643a );
a19647a <=( A299 and A298 );
a19650a <=( (not A301) and (not A300) );
a19651a <=( a19650a and a19647a );
a19652a <=( a19651a and a19644a );
a19656a <=( (not A166) and A167 );
a19657a <=( A170 and a19656a );
a19661a <=( A203 and (not A200) );
a19662a <=( A199 and a19661a );
a19663a <=( a19662a and a19657a );
a19667a <=( A269 and (not A266) );
a19668a <=( A265 and a19667a );
a19671a <=( A299 and A298 );
a19674a <=( (not A301) and (not A300) );
a19675a <=( a19674a and a19671a );
a19676a <=( a19675a and a19668a );
a19680a <=( (not A166) and A167 );
a19681a <=( A170 and a19680a );
a19685a <=( (not A202) and (not A200) );
a19686a <=( (not A199) and a19685a );
a19687a <=( a19686a and a19681a );
a19691a <=( (not A267) and A266 );
a19692a <=( A265 and a19691a );
a19695a <=( A298 and (not A268) );
a19698a <=( A302 and (not A299) );
a19699a <=( a19698a and a19695a );
a19700a <=( a19699a and a19692a );
a19704a <=( (not A166) and A167 );
a19705a <=( A170 and a19704a );
a19709a <=( (not A202) and (not A200) );
a19710a <=( (not A199) and a19709a );
a19711a <=( a19710a and a19705a );
a19715a <=( (not A267) and A266 );
a19716a <=( A265 and a19715a );
a19719a <=( (not A298) and (not A268) );
a19722a <=( A302 and A299 );
a19723a <=( a19722a and a19719a );
a19724a <=( a19723a and a19716a );
a19728a <=( A166 and (not A167) );
a19729a <=( A170 and a19728a );
a19733a <=( (not A203) and (not A202) );
a19734a <=( (not A201) and a19733a );
a19735a <=( a19734a and a19729a );
a19739a <=( (not A267) and A266 );
a19740a <=( A265 and a19739a );
a19743a <=( A298 and (not A268) );
a19746a <=( A302 and (not A299) );
a19747a <=( a19746a and a19743a );
a19748a <=( a19747a and a19740a );
a19752a <=( A166 and (not A167) );
a19753a <=( A170 and a19752a );
a19757a <=( (not A203) and (not A202) );
a19758a <=( (not A201) and a19757a );
a19759a <=( a19758a and a19753a );
a19763a <=( (not A267) and A266 );
a19764a <=( A265 and a19763a );
a19767a <=( (not A298) and (not A268) );
a19770a <=( A302 and A299 );
a19771a <=( a19770a and a19767a );
a19772a <=( a19771a and a19764a );
a19776a <=( A166 and (not A167) );
a19777a <=( A170 and a19776a );
a19781a <=( (not A201) and A200 );
a19782a <=( A199 and a19781a );
a19783a <=( a19782a and a19777a );
a19787a <=( (not A268) and (not A267) );
a19788a <=( (not A202) and a19787a );
a19791a <=( A298 and (not A269) );
a19794a <=( A302 and (not A299) );
a19795a <=( a19794a and a19791a );
a19796a <=( a19795a and a19788a );
a19800a <=( A166 and (not A167) );
a19801a <=( A170 and a19800a );
a19805a <=( (not A201) and A200 );
a19806a <=( A199 and a19805a );
a19807a <=( a19806a and a19801a );
a19811a <=( (not A268) and (not A267) );
a19812a <=( (not A202) and a19811a );
a19815a <=( (not A298) and (not A269) );
a19818a <=( A302 and A299 );
a19819a <=( a19818a and a19815a );
a19820a <=( a19819a and a19812a );
a19824a <=( A166 and (not A167) );
a19825a <=( A170 and a19824a );
a19829a <=( (not A201) and A200 );
a19830a <=( A199 and a19829a );
a19831a <=( a19830a and a19825a );
a19835a <=( A266 and A265 );
a19836a <=( (not A202) and a19835a );
a19839a <=( (not A268) and (not A267) );
a19842a <=( A300 and A299 );
a19843a <=( a19842a and a19839a );
a19844a <=( a19843a and a19836a );
a19848a <=( A166 and (not A167) );
a19849a <=( A170 and a19848a );
a19853a <=( (not A201) and A200 );
a19854a <=( A199 and a19853a );
a19855a <=( a19854a and a19849a );
a19859a <=( A266 and A265 );
a19860a <=( (not A202) and a19859a );
a19863a <=( (not A268) and (not A267) );
a19866a <=( A300 and A298 );
a19867a <=( a19866a and a19863a );
a19868a <=( a19867a and a19860a );
a19872a <=( A166 and (not A167) );
a19873a <=( A170 and a19872a );
a19877a <=( (not A201) and A200 );
a19878a <=( A199 and a19877a );
a19879a <=( a19878a and a19873a );
a19883a <=( (not A266) and (not A265) );
a19884a <=( (not A202) and a19883a );
a19887a <=( A298 and (not A268) );
a19890a <=( A302 and (not A299) );
a19891a <=( a19890a and a19887a );
a19892a <=( a19891a and a19884a );
a19896a <=( A166 and (not A167) );
a19897a <=( A170 and a19896a );
a19901a <=( (not A201) and A200 );
a19902a <=( A199 and a19901a );
a19903a <=( a19902a and a19897a );
a19907a <=( (not A266) and (not A265) );
a19908a <=( (not A202) and a19907a );
a19911a <=( (not A298) and (not A268) );
a19914a <=( A302 and A299 );
a19915a <=( a19914a and a19911a );
a19916a <=( a19915a and a19908a );
a19920a <=( A166 and (not A167) );
a19921a <=( A170 and a19920a );
a19925a <=( A203 and A200 );
a19926a <=( (not A199) and a19925a );
a19927a <=( a19926a and a19921a );
a19931a <=( A269 and A266 );
a19932a <=( (not A265) and a19931a );
a19935a <=( A299 and A298 );
a19938a <=( (not A301) and (not A300) );
a19939a <=( a19938a and a19935a );
a19940a <=( a19939a and a19932a );
a19944a <=( A166 and (not A167) );
a19945a <=( A170 and a19944a );
a19949a <=( A203 and A200 );
a19950a <=( (not A199) and a19949a );
a19951a <=( a19950a and a19945a );
a19955a <=( A269 and (not A266) );
a19956a <=( A265 and a19955a );
a19959a <=( A299 and A298 );
a19962a <=( (not A301) and (not A300) );
a19963a <=( a19962a and a19959a );
a19964a <=( a19963a and a19956a );
a19968a <=( A166 and (not A167) );
a19969a <=( A170 and a19968a );
a19973a <=( A203 and (not A200) );
a19974a <=( A199 and a19973a );
a19975a <=( a19974a and a19969a );
a19979a <=( A269 and A266 );
a19980a <=( (not A265) and a19979a );
a19983a <=( A299 and A298 );
a19986a <=( (not A301) and (not A300) );
a19987a <=( a19986a and a19983a );
a19988a <=( a19987a and a19980a );
a19992a <=( A166 and (not A167) );
a19993a <=( A170 and a19992a );
a19997a <=( A203 and (not A200) );
a19998a <=( A199 and a19997a );
a19999a <=( a19998a and a19993a );
a20003a <=( A269 and (not A266) );
a20004a <=( A265 and a20003a );
a20007a <=( A299 and A298 );
a20010a <=( (not A301) and (not A300) );
a20011a <=( a20010a and a20007a );
a20012a <=( a20011a and a20004a );
a20016a <=( A166 and (not A167) );
a20017a <=( A170 and a20016a );
a20021a <=( (not A202) and (not A200) );
a20022a <=( (not A199) and a20021a );
a20023a <=( a20022a and a20017a );
a20027a <=( (not A267) and A266 );
a20028a <=( A265 and a20027a );
a20031a <=( A298 and (not A268) );
a20034a <=( A302 and (not A299) );
a20035a <=( a20034a and a20031a );
a20036a <=( a20035a and a20028a );
a20040a <=( A166 and (not A167) );
a20041a <=( A170 and a20040a );
a20045a <=( (not A202) and (not A200) );
a20046a <=( (not A199) and a20045a );
a20047a <=( a20046a and a20041a );
a20051a <=( (not A267) and A266 );
a20052a <=( A265 and a20051a );
a20055a <=( (not A298) and (not A268) );
a20058a <=( A302 and A299 );
a20059a <=( a20058a and a20055a );
a20060a <=( a20059a and a20052a );
a20064a <=( (not A166) and (not A167) );
a20065a <=( (not A169) and a20064a );
a20069a <=( (not A203) and (not A202) );
a20070a <=( (not A201) and a20069a );
a20071a <=( a20070a and a20065a );
a20075a <=( A269 and A266 );
a20076a <=( (not A265) and a20075a );
a20079a <=( A299 and A298 );
a20082a <=( (not A301) and (not A300) );
a20083a <=( a20082a and a20079a );
a20084a <=( a20083a and a20076a );
a20088a <=( (not A166) and (not A167) );
a20089a <=( (not A169) and a20088a );
a20093a <=( (not A203) and (not A202) );
a20094a <=( (not A201) and a20093a );
a20095a <=( a20094a and a20089a );
a20099a <=( A269 and (not A266) );
a20100a <=( A265 and a20099a );
a20103a <=( A299 and A298 );
a20106a <=( (not A301) and (not A300) );
a20107a <=( a20106a and a20103a );
a20108a <=( a20107a and a20100a );
a20112a <=( (not A166) and (not A167) );
a20113a <=( (not A169) and a20112a );
a20117a <=( (not A201) and A200 );
a20118a <=( A199 and a20117a );
a20119a <=( a20118a and a20113a );
a20123a <=( A267 and A265 );
a20124a <=( (not A202) and a20123a );
a20127a <=( A299 and A298 );
a20130a <=( (not A301) and (not A300) );
a20131a <=( a20130a and a20127a );
a20132a <=( a20131a and a20124a );
a20136a <=( (not A166) and (not A167) );
a20137a <=( (not A169) and a20136a );
a20141a <=( (not A201) and A200 );
a20142a <=( A199 and a20141a );
a20143a <=( a20142a and a20137a );
a20147a <=( A267 and A266 );
a20148a <=( (not A202) and a20147a );
a20151a <=( A299 and A298 );
a20154a <=( (not A301) and (not A300) );
a20155a <=( a20154a and a20151a );
a20156a <=( a20155a and a20148a );
a20160a <=( (not A166) and (not A167) );
a20161a <=( (not A169) and a20160a );
a20165a <=( (not A201) and A200 );
a20166a <=( A199 and a20165a );
a20167a <=( a20166a and a20161a );
a20171a <=( A266 and (not A265) );
a20172a <=( (not A202) and a20171a );
a20175a <=( (not A300) and A269 );
a20178a <=( (not A302) and (not A301) );
a20179a <=( a20178a and a20175a );
a20180a <=( a20179a and a20172a );
a20184a <=( (not A166) and (not A167) );
a20185a <=( (not A169) and a20184a );
a20189a <=( (not A201) and A200 );
a20190a <=( A199 and a20189a );
a20191a <=( a20190a and a20185a );
a20195a <=( A266 and (not A265) );
a20196a <=( (not A202) and a20195a );
a20199a <=( (not A298) and A269 );
a20202a <=( (not A301) and (not A299) );
a20203a <=( a20202a and a20199a );
a20204a <=( a20203a and a20196a );
a20208a <=( (not A166) and (not A167) );
a20209a <=( (not A169) and a20208a );
a20213a <=( (not A201) and A200 );
a20214a <=( A199 and a20213a );
a20215a <=( a20214a and a20209a );
a20219a <=( (not A266) and A265 );
a20220a <=( (not A202) and a20219a );
a20223a <=( (not A300) and A269 );
a20226a <=( (not A302) and (not A301) );
a20227a <=( a20226a and a20223a );
a20228a <=( a20227a and a20220a );
a20232a <=( (not A166) and (not A167) );
a20233a <=( (not A169) and a20232a );
a20237a <=( (not A201) and A200 );
a20238a <=( A199 and a20237a );
a20239a <=( a20238a and a20233a );
a20243a <=( (not A266) and A265 );
a20244a <=( (not A202) and a20243a );
a20247a <=( (not A298) and A269 );
a20250a <=( (not A301) and (not A299) );
a20251a <=( a20250a and a20247a );
a20252a <=( a20251a and a20244a );
a20256a <=( (not A166) and (not A167) );
a20257a <=( (not A169) and a20256a );
a20261a <=( A203 and A200 );
a20262a <=( (not A199) and a20261a );
a20263a <=( a20262a and a20257a );
a20267a <=( (not A267) and A266 );
a20268a <=( A265 and a20267a );
a20271a <=( A298 and (not A268) );
a20274a <=( A302 and (not A299) );
a20275a <=( a20274a and a20271a );
a20276a <=( a20275a and a20268a );
a20280a <=( (not A166) and (not A167) );
a20281a <=( (not A169) and a20280a );
a20285a <=( A203 and A200 );
a20286a <=( (not A199) and a20285a );
a20287a <=( a20286a and a20281a );
a20291a <=( (not A267) and A266 );
a20292a <=( A265 and a20291a );
a20295a <=( (not A298) and (not A268) );
a20298a <=( A302 and A299 );
a20299a <=( a20298a and a20295a );
a20300a <=( a20299a and a20292a );
a20304a <=( (not A166) and (not A167) );
a20305a <=( (not A169) and a20304a );
a20309a <=( A203 and (not A200) );
a20310a <=( A199 and a20309a );
a20311a <=( a20310a and a20305a );
a20315a <=( (not A267) and A266 );
a20316a <=( A265 and a20315a );
a20319a <=( A298 and (not A268) );
a20322a <=( A302 and (not A299) );
a20323a <=( a20322a and a20319a );
a20324a <=( a20323a and a20316a );
a20328a <=( (not A166) and (not A167) );
a20329a <=( (not A169) and a20328a );
a20333a <=( A203 and (not A200) );
a20334a <=( A199 and a20333a );
a20335a <=( a20334a and a20329a );
a20339a <=( (not A267) and A266 );
a20340a <=( A265 and a20339a );
a20343a <=( (not A298) and (not A268) );
a20346a <=( A302 and A299 );
a20347a <=( a20346a and a20343a );
a20348a <=( a20347a and a20340a );
a20352a <=( (not A166) and (not A167) );
a20353a <=( (not A169) and a20352a );
a20357a <=( (not A202) and (not A200) );
a20358a <=( (not A199) and a20357a );
a20359a <=( a20358a and a20353a );
a20363a <=( A269 and A266 );
a20364a <=( (not A265) and a20363a );
a20367a <=( A299 and A298 );
a20370a <=( (not A301) and (not A300) );
a20371a <=( a20370a and a20367a );
a20372a <=( a20371a and a20364a );
a20376a <=( (not A166) and (not A167) );
a20377a <=( (not A169) and a20376a );
a20381a <=( (not A202) and (not A200) );
a20382a <=( (not A199) and a20381a );
a20383a <=( a20382a and a20377a );
a20387a <=( A269 and (not A266) );
a20388a <=( A265 and a20387a );
a20391a <=( A299 and A298 );
a20394a <=( (not A301) and (not A300) );
a20395a <=( a20394a and a20391a );
a20396a <=( a20395a and a20388a );
a20400a <=( A167 and (not A168) );
a20401a <=( (not A169) and a20400a );
a20405a <=( (not A202) and (not A201) );
a20406a <=( A166 and a20405a );
a20407a <=( a20406a and a20401a );
a20411a <=( A267 and A265 );
a20412a <=( (not A203) and a20411a );
a20415a <=( A299 and A298 );
a20418a <=( (not A301) and (not A300) );
a20419a <=( a20418a and a20415a );
a20420a <=( a20419a and a20412a );
a20424a <=( A167 and (not A168) );
a20425a <=( (not A169) and a20424a );
a20429a <=( (not A202) and (not A201) );
a20430a <=( A166 and a20429a );
a20431a <=( a20430a and a20425a );
a20435a <=( A267 and A266 );
a20436a <=( (not A203) and a20435a );
a20439a <=( A299 and A298 );
a20442a <=( (not A301) and (not A300) );
a20443a <=( a20442a and a20439a );
a20444a <=( a20443a and a20436a );
a20448a <=( A167 and (not A168) );
a20449a <=( (not A169) and a20448a );
a20453a <=( (not A202) and (not A201) );
a20454a <=( A166 and a20453a );
a20455a <=( a20454a and a20449a );
a20459a <=( A266 and (not A265) );
a20460a <=( (not A203) and a20459a );
a20463a <=( (not A300) and A269 );
a20466a <=( (not A302) and (not A301) );
a20467a <=( a20466a and a20463a );
a20468a <=( a20467a and a20460a );
a20472a <=( A167 and (not A168) );
a20473a <=( (not A169) and a20472a );
a20477a <=( (not A202) and (not A201) );
a20478a <=( A166 and a20477a );
a20479a <=( a20478a and a20473a );
a20483a <=( A266 and (not A265) );
a20484a <=( (not A203) and a20483a );
a20487a <=( (not A298) and A269 );
a20490a <=( (not A301) and (not A299) );
a20491a <=( a20490a and a20487a );
a20492a <=( a20491a and a20484a );
a20496a <=( A167 and (not A168) );
a20497a <=( (not A169) and a20496a );
a20501a <=( (not A202) and (not A201) );
a20502a <=( A166 and a20501a );
a20503a <=( a20502a and a20497a );
a20507a <=( (not A266) and A265 );
a20508a <=( (not A203) and a20507a );
a20511a <=( (not A300) and A269 );
a20514a <=( (not A302) and (not A301) );
a20515a <=( a20514a and a20511a );
a20516a <=( a20515a and a20508a );
a20520a <=( A167 and (not A168) );
a20521a <=( (not A169) and a20520a );
a20525a <=( (not A202) and (not A201) );
a20526a <=( A166 and a20525a );
a20527a <=( a20526a and a20521a );
a20531a <=( (not A266) and A265 );
a20532a <=( (not A203) and a20531a );
a20535a <=( (not A298) and A269 );
a20538a <=( (not A301) and (not A299) );
a20539a <=( a20538a and a20535a );
a20540a <=( a20539a and a20532a );
a20544a <=( A167 and (not A168) );
a20545a <=( (not A169) and a20544a );
a20549a <=( A201 and A199 );
a20550a <=( A166 and a20549a );
a20551a <=( a20550a and a20545a );
a20555a <=( (not A267) and A266 );
a20556a <=( A265 and a20555a );
a20559a <=( A298 and (not A268) );
a20562a <=( A302 and (not A299) );
a20563a <=( a20562a and a20559a );
a20564a <=( a20563a and a20556a );
a20568a <=( A167 and (not A168) );
a20569a <=( (not A169) and a20568a );
a20573a <=( A201 and A199 );
a20574a <=( A166 and a20573a );
a20575a <=( a20574a and a20569a );
a20579a <=( (not A267) and A266 );
a20580a <=( A265 and a20579a );
a20583a <=( (not A298) and (not A268) );
a20586a <=( A302 and A299 );
a20587a <=( a20586a and a20583a );
a20588a <=( a20587a and a20580a );
a20592a <=( A167 and (not A168) );
a20593a <=( (not A169) and a20592a );
a20597a <=( A201 and A200 );
a20598a <=( A166 and a20597a );
a20599a <=( a20598a and a20593a );
a20603a <=( (not A267) and A266 );
a20604a <=( A265 and a20603a );
a20607a <=( A298 and (not A268) );
a20610a <=( A302 and (not A299) );
a20611a <=( a20610a and a20607a );
a20612a <=( a20611a and a20604a );
a20616a <=( A167 and (not A168) );
a20617a <=( (not A169) and a20616a );
a20621a <=( A201 and A200 );
a20622a <=( A166 and a20621a );
a20623a <=( a20622a and a20617a );
a20627a <=( (not A267) and A266 );
a20628a <=( A265 and a20627a );
a20631a <=( (not A298) and (not A268) );
a20634a <=( A302 and A299 );
a20635a <=( a20634a and a20631a );
a20636a <=( a20635a and a20628a );
a20640a <=( A167 and (not A168) );
a20641a <=( (not A169) and a20640a );
a20645a <=( A200 and A199 );
a20646a <=( A166 and a20645a );
a20647a <=( a20646a and a20641a );
a20651a <=( A268 and (not A202) );
a20652a <=( (not A201) and a20651a );
a20655a <=( A299 and A298 );
a20658a <=( (not A301) and (not A300) );
a20659a <=( a20658a and a20655a );
a20660a <=( a20659a and a20652a );
a20664a <=( A167 and (not A168) );
a20665a <=( (not A169) and a20664a );
a20669a <=( A200 and A199 );
a20670a <=( A166 and a20669a );
a20671a <=( a20670a and a20665a );
a20675a <=( A265 and (not A202) );
a20676a <=( (not A201) and a20675a );
a20679a <=( (not A300) and A267 );
a20682a <=( (not A302) and (not A301) );
a20683a <=( a20682a and a20679a );
a20684a <=( a20683a and a20676a );
a20688a <=( A167 and (not A168) );
a20689a <=( (not A169) and a20688a );
a20693a <=( A200 and A199 );
a20694a <=( A166 and a20693a );
a20695a <=( a20694a and a20689a );
a20699a <=( A265 and (not A202) );
a20700a <=( (not A201) and a20699a );
a20703a <=( (not A298) and A267 );
a20706a <=( (not A301) and (not A299) );
a20707a <=( a20706a and a20703a );
a20708a <=( a20707a and a20700a );
a20712a <=( A167 and (not A168) );
a20713a <=( (not A169) and a20712a );
a20717a <=( A200 and A199 );
a20718a <=( A166 and a20717a );
a20719a <=( a20718a and a20713a );
a20723a <=( A266 and (not A202) );
a20724a <=( (not A201) and a20723a );
a20727a <=( (not A300) and A267 );
a20730a <=( (not A302) and (not A301) );
a20731a <=( a20730a and a20727a );
a20732a <=( a20731a and a20724a );
a20736a <=( A167 and (not A168) );
a20737a <=( (not A169) and a20736a );
a20741a <=( A200 and A199 );
a20742a <=( A166 and a20741a );
a20743a <=( a20742a and a20737a );
a20747a <=( A266 and (not A202) );
a20748a <=( (not A201) and a20747a );
a20751a <=( (not A298) and A267 );
a20754a <=( (not A301) and (not A299) );
a20755a <=( a20754a and a20751a );
a20756a <=( a20755a and a20748a );
a20760a <=( A167 and (not A168) );
a20761a <=( (not A169) and a20760a );
a20765a <=( A200 and (not A199) );
a20766a <=( A166 and a20765a );
a20767a <=( a20766a and a20761a );
a20771a <=( (not A268) and (not A267) );
a20772a <=( A203 and a20771a );
a20775a <=( A298 and (not A269) );
a20778a <=( A302 and (not A299) );
a20779a <=( a20778a and a20775a );
a20780a <=( a20779a and a20772a );
a20784a <=( A167 and (not A168) );
a20785a <=( (not A169) and a20784a );
a20789a <=( A200 and (not A199) );
a20790a <=( A166 and a20789a );
a20791a <=( a20790a and a20785a );
a20795a <=( (not A268) and (not A267) );
a20796a <=( A203 and a20795a );
a20799a <=( (not A298) and (not A269) );
a20802a <=( A302 and A299 );
a20803a <=( a20802a and a20799a );
a20804a <=( a20803a and a20796a );
a20808a <=( A167 and (not A168) );
a20809a <=( (not A169) and a20808a );
a20813a <=( A200 and (not A199) );
a20814a <=( A166 and a20813a );
a20815a <=( a20814a and a20809a );
a20819a <=( A266 and A265 );
a20820a <=( A203 and a20819a );
a20823a <=( (not A268) and (not A267) );
a20826a <=( A300 and A299 );
a20827a <=( a20826a and a20823a );
a20828a <=( a20827a and a20820a );
a20832a <=( A167 and (not A168) );
a20833a <=( (not A169) and a20832a );
a20837a <=( A200 and (not A199) );
a20838a <=( A166 and a20837a );
a20839a <=( a20838a and a20833a );
a20843a <=( A266 and A265 );
a20844a <=( A203 and a20843a );
a20847a <=( (not A268) and (not A267) );
a20850a <=( A300 and A298 );
a20851a <=( a20850a and a20847a );
a20852a <=( a20851a and a20844a );
a20856a <=( A167 and (not A168) );
a20857a <=( (not A169) and a20856a );
a20861a <=( A200 and (not A199) );
a20862a <=( A166 and a20861a );
a20863a <=( a20862a and a20857a );
a20867a <=( (not A266) and (not A265) );
a20868a <=( A203 and a20867a );
a20871a <=( A298 and (not A268) );
a20874a <=( A302 and (not A299) );
a20875a <=( a20874a and a20871a );
a20876a <=( a20875a and a20868a );
a20880a <=( A167 and (not A168) );
a20881a <=( (not A169) and a20880a );
a20885a <=( A200 and (not A199) );
a20886a <=( A166 and a20885a );
a20887a <=( a20886a and a20881a );
a20891a <=( (not A266) and (not A265) );
a20892a <=( A203 and a20891a );
a20895a <=( (not A298) and (not A268) );
a20898a <=( A302 and A299 );
a20899a <=( a20898a and a20895a );
a20900a <=( a20899a and a20892a );
a20904a <=( A167 and (not A168) );
a20905a <=( (not A169) and a20904a );
a20909a <=( (not A200) and A199 );
a20910a <=( A166 and a20909a );
a20911a <=( a20910a and a20905a );
a20915a <=( (not A268) and (not A267) );
a20916a <=( A203 and a20915a );
a20919a <=( A298 and (not A269) );
a20922a <=( A302 and (not A299) );
a20923a <=( a20922a and a20919a );
a20924a <=( a20923a and a20916a );
a20928a <=( A167 and (not A168) );
a20929a <=( (not A169) and a20928a );
a20933a <=( (not A200) and A199 );
a20934a <=( A166 and a20933a );
a20935a <=( a20934a and a20929a );
a20939a <=( (not A268) and (not A267) );
a20940a <=( A203 and a20939a );
a20943a <=( (not A298) and (not A269) );
a20946a <=( A302 and A299 );
a20947a <=( a20946a and a20943a );
a20948a <=( a20947a and a20940a );
a20952a <=( A167 and (not A168) );
a20953a <=( (not A169) and a20952a );
a20957a <=( (not A200) and A199 );
a20958a <=( A166 and a20957a );
a20959a <=( a20958a and a20953a );
a20963a <=( A266 and A265 );
a20964a <=( A203 and a20963a );
a20967a <=( (not A268) and (not A267) );
a20970a <=( A300 and A299 );
a20971a <=( a20970a and a20967a );
a20972a <=( a20971a and a20964a );
a20976a <=( A167 and (not A168) );
a20977a <=( (not A169) and a20976a );
a20981a <=( (not A200) and A199 );
a20982a <=( A166 and a20981a );
a20983a <=( a20982a and a20977a );
a20987a <=( A266 and A265 );
a20988a <=( A203 and a20987a );
a20991a <=( (not A268) and (not A267) );
a20994a <=( A300 and A298 );
a20995a <=( a20994a and a20991a );
a20996a <=( a20995a and a20988a );
a21000a <=( A167 and (not A168) );
a21001a <=( (not A169) and a21000a );
a21005a <=( (not A200) and A199 );
a21006a <=( A166 and a21005a );
a21007a <=( a21006a and a21001a );
a21011a <=( (not A266) and (not A265) );
a21012a <=( A203 and a21011a );
a21015a <=( A298 and (not A268) );
a21018a <=( A302 and (not A299) );
a21019a <=( a21018a and a21015a );
a21020a <=( a21019a and a21012a );
a21024a <=( A167 and (not A168) );
a21025a <=( (not A169) and a21024a );
a21029a <=( (not A200) and A199 );
a21030a <=( A166 and a21029a );
a21031a <=( a21030a and a21025a );
a21035a <=( (not A266) and (not A265) );
a21036a <=( A203 and a21035a );
a21039a <=( (not A298) and (not A268) );
a21042a <=( A302 and A299 );
a21043a <=( a21042a and a21039a );
a21044a <=( a21043a and a21036a );
a21048a <=( A167 and (not A168) );
a21049a <=( (not A169) and a21048a );
a21053a <=( (not A200) and (not A199) );
a21054a <=( A166 and a21053a );
a21055a <=( a21054a and a21049a );
a21059a <=( A267 and A265 );
a21060a <=( (not A202) and a21059a );
a21063a <=( A299 and A298 );
a21066a <=( (not A301) and (not A300) );
a21067a <=( a21066a and a21063a );
a21068a <=( a21067a and a21060a );
a21072a <=( A167 and (not A168) );
a21073a <=( (not A169) and a21072a );
a21077a <=( (not A200) and (not A199) );
a21078a <=( A166 and a21077a );
a21079a <=( a21078a and a21073a );
a21083a <=( A267 and A266 );
a21084a <=( (not A202) and a21083a );
a21087a <=( A299 and A298 );
a21090a <=( (not A301) and (not A300) );
a21091a <=( a21090a and a21087a );
a21092a <=( a21091a and a21084a );
a21096a <=( A167 and (not A168) );
a21097a <=( (not A169) and a21096a );
a21101a <=( (not A200) and (not A199) );
a21102a <=( A166 and a21101a );
a21103a <=( a21102a and a21097a );
a21107a <=( A266 and (not A265) );
a21108a <=( (not A202) and a21107a );
a21111a <=( (not A300) and A269 );
a21114a <=( (not A302) and (not A301) );
a21115a <=( a21114a and a21111a );
a21116a <=( a21115a and a21108a );
a21120a <=( A167 and (not A168) );
a21121a <=( (not A169) and a21120a );
a21125a <=( (not A200) and (not A199) );
a21126a <=( A166 and a21125a );
a21127a <=( a21126a and a21121a );
a21131a <=( A266 and (not A265) );
a21132a <=( (not A202) and a21131a );
a21135a <=( (not A298) and A269 );
a21138a <=( (not A301) and (not A299) );
a21139a <=( a21138a and a21135a );
a21140a <=( a21139a and a21132a );
a21144a <=( A167 and (not A168) );
a21145a <=( (not A169) and a21144a );
a21149a <=( (not A200) and (not A199) );
a21150a <=( A166 and a21149a );
a21151a <=( a21150a and a21145a );
a21155a <=( (not A266) and A265 );
a21156a <=( (not A202) and a21155a );
a21159a <=( (not A300) and A269 );
a21162a <=( (not A302) and (not A301) );
a21163a <=( a21162a and a21159a );
a21164a <=( a21163a and a21156a );
a21168a <=( A167 and (not A168) );
a21169a <=( (not A169) and a21168a );
a21173a <=( (not A200) and (not A199) );
a21174a <=( A166 and a21173a );
a21175a <=( a21174a and a21169a );
a21179a <=( (not A266) and A265 );
a21180a <=( (not A202) and a21179a );
a21183a <=( (not A298) and A269 );
a21186a <=( (not A301) and (not A299) );
a21187a <=( a21186a and a21183a );
a21188a <=( a21187a and a21180a );
a21192a <=( (not A168) and (not A169) );
a21193a <=( (not A170) and a21192a );
a21197a <=( (not A203) and (not A202) );
a21198a <=( (not A201) and a21197a );
a21199a <=( a21198a and a21193a );
a21203a <=( A269 and A266 );
a21204a <=( (not A265) and a21203a );
a21207a <=( A299 and A298 );
a21210a <=( (not A301) and (not A300) );
a21211a <=( a21210a and a21207a );
a21212a <=( a21211a and a21204a );
a21216a <=( (not A168) and (not A169) );
a21217a <=( (not A170) and a21216a );
a21221a <=( (not A203) and (not A202) );
a21222a <=( (not A201) and a21221a );
a21223a <=( a21222a and a21217a );
a21227a <=( A269 and (not A266) );
a21228a <=( A265 and a21227a );
a21231a <=( A299 and A298 );
a21234a <=( (not A301) and (not A300) );
a21235a <=( a21234a and a21231a );
a21236a <=( a21235a and a21228a );
a21240a <=( (not A168) and (not A169) );
a21241a <=( (not A170) and a21240a );
a21245a <=( (not A201) and A200 );
a21246a <=( A199 and a21245a );
a21247a <=( a21246a and a21241a );
a21251a <=( A267 and A265 );
a21252a <=( (not A202) and a21251a );
a21255a <=( A299 and A298 );
a21258a <=( (not A301) and (not A300) );
a21259a <=( a21258a and a21255a );
a21260a <=( a21259a and a21252a );
a21264a <=( (not A168) and (not A169) );
a21265a <=( (not A170) and a21264a );
a21269a <=( (not A201) and A200 );
a21270a <=( A199 and a21269a );
a21271a <=( a21270a and a21265a );
a21275a <=( A267 and A266 );
a21276a <=( (not A202) and a21275a );
a21279a <=( A299 and A298 );
a21282a <=( (not A301) and (not A300) );
a21283a <=( a21282a and a21279a );
a21284a <=( a21283a and a21276a );
a21288a <=( (not A168) and (not A169) );
a21289a <=( (not A170) and a21288a );
a21293a <=( (not A201) and A200 );
a21294a <=( A199 and a21293a );
a21295a <=( a21294a and a21289a );
a21299a <=( A266 and (not A265) );
a21300a <=( (not A202) and a21299a );
a21303a <=( (not A300) and A269 );
a21306a <=( (not A302) and (not A301) );
a21307a <=( a21306a and a21303a );
a21308a <=( a21307a and a21300a );
a21312a <=( (not A168) and (not A169) );
a21313a <=( (not A170) and a21312a );
a21317a <=( (not A201) and A200 );
a21318a <=( A199 and a21317a );
a21319a <=( a21318a and a21313a );
a21323a <=( A266 and (not A265) );
a21324a <=( (not A202) and a21323a );
a21327a <=( (not A298) and A269 );
a21330a <=( (not A301) and (not A299) );
a21331a <=( a21330a and a21327a );
a21332a <=( a21331a and a21324a );
a21336a <=( (not A168) and (not A169) );
a21337a <=( (not A170) and a21336a );
a21341a <=( (not A201) and A200 );
a21342a <=( A199 and a21341a );
a21343a <=( a21342a and a21337a );
a21347a <=( (not A266) and A265 );
a21348a <=( (not A202) and a21347a );
a21351a <=( (not A300) and A269 );
a21354a <=( (not A302) and (not A301) );
a21355a <=( a21354a and a21351a );
a21356a <=( a21355a and a21348a );
a21360a <=( (not A168) and (not A169) );
a21361a <=( (not A170) and a21360a );
a21365a <=( (not A201) and A200 );
a21366a <=( A199 and a21365a );
a21367a <=( a21366a and a21361a );
a21371a <=( (not A266) and A265 );
a21372a <=( (not A202) and a21371a );
a21375a <=( (not A298) and A269 );
a21378a <=( (not A301) and (not A299) );
a21379a <=( a21378a and a21375a );
a21380a <=( a21379a and a21372a );
a21384a <=( (not A168) and (not A169) );
a21385a <=( (not A170) and a21384a );
a21389a <=( A203 and A200 );
a21390a <=( (not A199) and a21389a );
a21391a <=( a21390a and a21385a );
a21395a <=( (not A267) and A266 );
a21396a <=( A265 and a21395a );
a21399a <=( A298 and (not A268) );
a21402a <=( A302 and (not A299) );
a21403a <=( a21402a and a21399a );
a21404a <=( a21403a and a21396a );
a21408a <=( (not A168) and (not A169) );
a21409a <=( (not A170) and a21408a );
a21413a <=( A203 and A200 );
a21414a <=( (not A199) and a21413a );
a21415a <=( a21414a and a21409a );
a21419a <=( (not A267) and A266 );
a21420a <=( A265 and a21419a );
a21423a <=( (not A298) and (not A268) );
a21426a <=( A302 and A299 );
a21427a <=( a21426a and a21423a );
a21428a <=( a21427a and a21420a );
a21432a <=( (not A168) and (not A169) );
a21433a <=( (not A170) and a21432a );
a21437a <=( A203 and (not A200) );
a21438a <=( A199 and a21437a );
a21439a <=( a21438a and a21433a );
a21443a <=( (not A267) and A266 );
a21444a <=( A265 and a21443a );
a21447a <=( A298 and (not A268) );
a21450a <=( A302 and (not A299) );
a21451a <=( a21450a and a21447a );
a21452a <=( a21451a and a21444a );
a21456a <=( (not A168) and (not A169) );
a21457a <=( (not A170) and a21456a );
a21461a <=( A203 and (not A200) );
a21462a <=( A199 and a21461a );
a21463a <=( a21462a and a21457a );
a21467a <=( (not A267) and A266 );
a21468a <=( A265 and a21467a );
a21471a <=( (not A298) and (not A268) );
a21474a <=( A302 and A299 );
a21475a <=( a21474a and a21471a );
a21476a <=( a21475a and a21468a );
a21480a <=( (not A168) and (not A169) );
a21481a <=( (not A170) and a21480a );
a21485a <=( (not A202) and (not A200) );
a21486a <=( (not A199) and a21485a );
a21487a <=( a21486a and a21481a );
a21491a <=( A269 and A266 );
a21492a <=( (not A265) and a21491a );
a21495a <=( A299 and A298 );
a21498a <=( (not A301) and (not A300) );
a21499a <=( a21498a and a21495a );
a21500a <=( a21499a and a21492a );
a21504a <=( (not A168) and (not A169) );
a21505a <=( (not A170) and a21504a );
a21509a <=( (not A202) and (not A200) );
a21510a <=( (not A199) and a21509a );
a21511a <=( a21510a and a21505a );
a21515a <=( A269 and (not A266) );
a21516a <=( A265 and a21515a );
a21519a <=( A299 and A298 );
a21522a <=( (not A301) and (not A300) );
a21523a <=( a21522a and a21519a );
a21524a <=( a21523a and a21516a );
a21528a <=( (not A166) and A167 );
a21529a <=( A170 and a21528a );
a21532a <=( A200 and A199 );
a21535a <=( (not A202) and (not A201) );
a21536a <=( a21535a and a21532a );
a21537a <=( a21536a and a21529a );
a21541a <=( (not A267) and A266 );
a21542a <=( A265 and a21541a );
a21545a <=( A298 and (not A268) );
a21548a <=( A302 and (not A299) );
a21549a <=( a21548a and a21545a );
a21550a <=( a21549a and a21542a );
a21554a <=( (not A166) and A167 );
a21555a <=( A170 and a21554a );
a21558a <=( A200 and A199 );
a21561a <=( (not A202) and (not A201) );
a21562a <=( a21561a and a21558a );
a21563a <=( a21562a and a21555a );
a21567a <=( (not A267) and A266 );
a21568a <=( A265 and a21567a );
a21571a <=( (not A298) and (not A268) );
a21574a <=( A302 and A299 );
a21575a <=( a21574a and a21571a );
a21576a <=( a21575a and a21568a );
a21580a <=( A166 and (not A167) );
a21581a <=( A170 and a21580a );
a21584a <=( A200 and A199 );
a21587a <=( (not A202) and (not A201) );
a21588a <=( a21587a and a21584a );
a21589a <=( a21588a and a21581a );
a21593a <=( (not A267) and A266 );
a21594a <=( A265 and a21593a );
a21597a <=( A298 and (not A268) );
a21600a <=( A302 and (not A299) );
a21601a <=( a21600a and a21597a );
a21602a <=( a21601a and a21594a );
a21606a <=( A166 and (not A167) );
a21607a <=( A170 and a21606a );
a21610a <=( A200 and A199 );
a21613a <=( (not A202) and (not A201) );
a21614a <=( a21613a and a21610a );
a21615a <=( a21614a and a21607a );
a21619a <=( (not A267) and A266 );
a21620a <=( A265 and a21619a );
a21623a <=( (not A298) and (not A268) );
a21626a <=( A302 and A299 );
a21627a <=( a21626a and a21623a );
a21628a <=( a21627a and a21620a );
a21632a <=( (not A166) and (not A167) );
a21633a <=( (not A169) and a21632a );
a21636a <=( A200 and A199 );
a21639a <=( (not A202) and (not A201) );
a21640a <=( a21639a and a21636a );
a21641a <=( a21640a and a21633a );
a21645a <=( A269 and A266 );
a21646a <=( (not A265) and a21645a );
a21649a <=( A299 and A298 );
a21652a <=( (not A301) and (not A300) );
a21653a <=( a21652a and a21649a );
a21654a <=( a21653a and a21646a );
a21658a <=( (not A166) and (not A167) );
a21659a <=( (not A169) and a21658a );
a21662a <=( A200 and A199 );
a21665a <=( (not A202) and (not A201) );
a21666a <=( a21665a and a21662a );
a21667a <=( a21666a and a21659a );
a21671a <=( A269 and (not A266) );
a21672a <=( A265 and a21671a );
a21675a <=( A299 and A298 );
a21678a <=( (not A301) and (not A300) );
a21679a <=( a21678a and a21675a );
a21680a <=( a21679a and a21672a );
a21684a <=( A167 and (not A168) );
a21685a <=( (not A169) and a21684a );
a21688a <=( (not A201) and A166 );
a21691a <=( (not A203) and (not A202) );
a21692a <=( a21691a and a21688a );
a21693a <=( a21692a and a21685a );
a21697a <=( A269 and A266 );
a21698a <=( (not A265) and a21697a );
a21701a <=( A299 and A298 );
a21704a <=( (not A301) and (not A300) );
a21705a <=( a21704a and a21701a );
a21706a <=( a21705a and a21698a );
a21710a <=( A167 and (not A168) );
a21711a <=( (not A169) and a21710a );
a21714a <=( (not A201) and A166 );
a21717a <=( (not A203) and (not A202) );
a21718a <=( a21717a and a21714a );
a21719a <=( a21718a and a21711a );
a21723a <=( A269 and (not A266) );
a21724a <=( A265 and a21723a );
a21727a <=( A299 and A298 );
a21730a <=( (not A301) and (not A300) );
a21731a <=( a21730a and a21727a );
a21732a <=( a21731a and a21724a );
a21736a <=( A167 and (not A168) );
a21737a <=( (not A169) and a21736a );
a21740a <=( A199 and A166 );
a21743a <=( (not A201) and A200 );
a21744a <=( a21743a and a21740a );
a21745a <=( a21744a and a21737a );
a21749a <=( A267 and A265 );
a21750a <=( (not A202) and a21749a );
a21753a <=( A299 and A298 );
a21756a <=( (not A301) and (not A300) );
a21757a <=( a21756a and a21753a );
a21758a <=( a21757a and a21750a );
a21762a <=( A167 and (not A168) );
a21763a <=( (not A169) and a21762a );
a21766a <=( A199 and A166 );
a21769a <=( (not A201) and A200 );
a21770a <=( a21769a and a21766a );
a21771a <=( a21770a and a21763a );
a21775a <=( A267 and A266 );
a21776a <=( (not A202) and a21775a );
a21779a <=( A299 and A298 );
a21782a <=( (not A301) and (not A300) );
a21783a <=( a21782a and a21779a );
a21784a <=( a21783a and a21776a );
a21788a <=( A167 and (not A168) );
a21789a <=( (not A169) and a21788a );
a21792a <=( A199 and A166 );
a21795a <=( (not A201) and A200 );
a21796a <=( a21795a and a21792a );
a21797a <=( a21796a and a21789a );
a21801a <=( A266 and (not A265) );
a21802a <=( (not A202) and a21801a );
a21805a <=( (not A300) and A269 );
a21808a <=( (not A302) and (not A301) );
a21809a <=( a21808a and a21805a );
a21810a <=( a21809a and a21802a );
a21814a <=( A167 and (not A168) );
a21815a <=( (not A169) and a21814a );
a21818a <=( A199 and A166 );
a21821a <=( (not A201) and A200 );
a21822a <=( a21821a and a21818a );
a21823a <=( a21822a and a21815a );
a21827a <=( A266 and (not A265) );
a21828a <=( (not A202) and a21827a );
a21831a <=( (not A298) and A269 );
a21834a <=( (not A301) and (not A299) );
a21835a <=( a21834a and a21831a );
a21836a <=( a21835a and a21828a );
a21840a <=( A167 and (not A168) );
a21841a <=( (not A169) and a21840a );
a21844a <=( A199 and A166 );
a21847a <=( (not A201) and A200 );
a21848a <=( a21847a and a21844a );
a21849a <=( a21848a and a21841a );
a21853a <=( (not A266) and A265 );
a21854a <=( (not A202) and a21853a );
a21857a <=( (not A300) and A269 );
a21860a <=( (not A302) and (not A301) );
a21861a <=( a21860a and a21857a );
a21862a <=( a21861a and a21854a );
a21866a <=( A167 and (not A168) );
a21867a <=( (not A169) and a21866a );
a21870a <=( A199 and A166 );
a21873a <=( (not A201) and A200 );
a21874a <=( a21873a and a21870a );
a21875a <=( a21874a and a21867a );
a21879a <=( (not A266) and A265 );
a21880a <=( (not A202) and a21879a );
a21883a <=( (not A298) and A269 );
a21886a <=( (not A301) and (not A299) );
a21887a <=( a21886a and a21883a );
a21888a <=( a21887a and a21880a );
a21892a <=( A167 and (not A168) );
a21893a <=( (not A169) and a21892a );
a21896a <=( (not A199) and A166 );
a21899a <=( A203 and A200 );
a21900a <=( a21899a and a21896a );
a21901a <=( a21900a and a21893a );
a21905a <=( (not A267) and A266 );
a21906a <=( A265 and a21905a );
a21909a <=( A298 and (not A268) );
a21912a <=( A302 and (not A299) );
a21913a <=( a21912a and a21909a );
a21914a <=( a21913a and a21906a );
a21918a <=( A167 and (not A168) );
a21919a <=( (not A169) and a21918a );
a21922a <=( (not A199) and A166 );
a21925a <=( A203 and A200 );
a21926a <=( a21925a and a21922a );
a21927a <=( a21926a and a21919a );
a21931a <=( (not A267) and A266 );
a21932a <=( A265 and a21931a );
a21935a <=( (not A298) and (not A268) );
a21938a <=( A302 and A299 );
a21939a <=( a21938a and a21935a );
a21940a <=( a21939a and a21932a );
a21944a <=( A167 and (not A168) );
a21945a <=( (not A169) and a21944a );
a21948a <=( A199 and A166 );
a21951a <=( A203 and (not A200) );
a21952a <=( a21951a and a21948a );
a21953a <=( a21952a and a21945a );
a21957a <=( (not A267) and A266 );
a21958a <=( A265 and a21957a );
a21961a <=( A298 and (not A268) );
a21964a <=( A302 and (not A299) );
a21965a <=( a21964a and a21961a );
a21966a <=( a21965a and a21958a );
a21970a <=( A167 and (not A168) );
a21971a <=( (not A169) and a21970a );
a21974a <=( A199 and A166 );
a21977a <=( A203 and (not A200) );
a21978a <=( a21977a and a21974a );
a21979a <=( a21978a and a21971a );
a21983a <=( (not A267) and A266 );
a21984a <=( A265 and a21983a );
a21987a <=( (not A298) and (not A268) );
a21990a <=( A302 and A299 );
a21991a <=( a21990a and a21987a );
a21992a <=( a21991a and a21984a );
a21996a <=( A167 and (not A168) );
a21997a <=( (not A169) and a21996a );
a22000a <=( (not A199) and A166 );
a22003a <=( (not A202) and (not A200) );
a22004a <=( a22003a and a22000a );
a22005a <=( a22004a and a21997a );
a22009a <=( A269 and A266 );
a22010a <=( (not A265) and a22009a );
a22013a <=( A299 and A298 );
a22016a <=( (not A301) and (not A300) );
a22017a <=( a22016a and a22013a );
a22018a <=( a22017a and a22010a );
a22022a <=( A167 and (not A168) );
a22023a <=( (not A169) and a22022a );
a22026a <=( (not A199) and A166 );
a22029a <=( (not A202) and (not A200) );
a22030a <=( a22029a and a22026a );
a22031a <=( a22030a and a22023a );
a22035a <=( A269 and (not A266) );
a22036a <=( A265 and a22035a );
a22039a <=( A299 and A298 );
a22042a <=( (not A301) and (not A300) );
a22043a <=( a22042a and a22039a );
a22044a <=( a22043a and a22036a );
a22048a <=( (not A168) and (not A169) );
a22049a <=( (not A170) and a22048a );
a22052a <=( A200 and A199 );
a22055a <=( (not A202) and (not A201) );
a22056a <=( a22055a and a22052a );
a22057a <=( a22056a and a22049a );
a22061a <=( A269 and A266 );
a22062a <=( (not A265) and a22061a );
a22065a <=( A299 and A298 );
a22068a <=( (not A301) and (not A300) );
a22069a <=( a22068a and a22065a );
a22070a <=( a22069a and a22062a );
a22074a <=( (not A168) and (not A169) );
a22075a <=( (not A170) and a22074a );
a22078a <=( A200 and A199 );
a22081a <=( (not A202) and (not A201) );
a22082a <=( a22081a and a22078a );
a22083a <=( a22082a and a22075a );
a22087a <=( A269 and (not A266) );
a22088a <=( A265 and a22087a );
a22091a <=( A299 and A298 );
a22094a <=( (not A301) and (not A300) );
a22095a <=( a22094a and a22091a );
a22096a <=( a22095a and a22088a );
a22100a <=( A167 and (not A168) );
a22101a <=( (not A169) and a22100a );
a22104a <=( A199 and A166 );
a22107a <=( (not A201) and A200 );
a22108a <=( a22107a and a22104a );
a22109a <=( a22108a and a22101a );
a22112a <=( (not A265) and (not A202) );
a22115a <=( A269 and A266 );
a22116a <=( a22115a and a22112a );
a22119a <=( A299 and A298 );
a22122a <=( (not A301) and (not A300) );
a22123a <=( a22122a and a22119a );
a22124a <=( a22123a and a22116a );
a22128a <=( A167 and (not A168) );
a22129a <=( (not A169) and a22128a );
a22132a <=( A199 and A166 );
a22135a <=( (not A201) and A200 );
a22136a <=( a22135a and a22132a );
a22137a <=( a22136a and a22129a );
a22140a <=( A265 and (not A202) );
a22143a <=( A269 and (not A266) );
a22144a <=( a22143a and a22140a );
a22147a <=( A299 and A298 );
a22150a <=( (not A301) and (not A300) );
a22151a <=( a22150a and a22147a );
a22152a <=( a22151a and a22144a );
end x25_14x_behav;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/4-MPEG-MV/asap-alap-random/mpegmv_asap.vhd
|
1
|
3468
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:02)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_asap_entity;
ARCHITECTURE mpegmv_asap_description OF mpegmv_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register14: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
register6 := input6 * 6;
register7 := input7 * 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 * 11;
register12 := input12 * 12;
register13 := input13 * 13;
register14 := input14 * 14;
WHEN "00000010" =>
register1 := register1 + 16;
register6 := register6 + 18;
register7 := register7 + 20;
register9 := register9 + 22;
register13 := register13 + 24;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := register4 + register6;
output1 <= register3 + register7;
register3 := register8 + register9;
register4 := register12 + register13;
WHEN "00000100" =>
register1 := register14 + register1;
register2 := register5 + register2;
register3 := register10 + register3;
register4 := register11 + register4;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register4 := ((NOT register4) + 1) XOR register4;
WHEN "00000110" =>
output2 <= register1(0 TO 15) & register3(0 TO 15);
output3 <= register4(0 TO 15) & register2(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_asap_description;
|
gpl-3.0
|
rhexsel/xinu-cMIPS
|
vhdl/packageMemory_simu.vhd
|
1
|
17588
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
package p_MEMORY is
-- To simplify (and accelerate) the RAM address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address which is at a different power of two than the ROM base.
-- Otherwise, the base must be subtracted from the address on every
-- reference, which means having an adder in the critical path.
-- Not good at all.
-- The address ranges for ROM, RAM and I/O must be distinct in the
-- uppermost 16 bits of the address (bits 31..16).
constant HI_SEL_BITS : integer := 31;
constant LO_SEL_BITS : integer := 16;
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00020000";
constant x_DATA_BASE_ADDR : reg32 := x"00080000";
constant x_DATA_MEM_SZ : reg32 := x"00080000";
constant x_IO_BASE_ADDR : reg32 := x"3c000000";
constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_SDRAM_BASE_ADDR : reg32 := x"04000000";
constant x_SDRAM_MEM_SZ : reg32 := x"02000000";
constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLBrefill
constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- CacheError
constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- generalExcpHandler
constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separInterrHandler
constant x_EXCEPTION_BFC0 : reg32 := x"00000680"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000700"; -- main()
-- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
constant SDRAM_BASE_ADDR : integer := to_integer(signed(x_SDRAM_BASE_ADDR));
constant SDRAM_MEM_SZ : integer := to_integer(signed(x_SDRAM_MEM_SZ));
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
-- maximum number of IO devices, must be a power of two.
constant IO_MAX_NUM_DEVS : integer := 16;
constant IO_ADDR_BITS : integer := log2_ceil(IO_MAX_NUM_DEVS * IO_ADDR_RANGE);
-- I/O addresses are IO_ADDR_RANGE apart
constant IO_PRINT_ADDR : integer := IO_BASE_ADDR;
constant IO_STDOUT_ADDR : integer := IO_BASE_ADDR + 1*IO_ADDR_RANGE;
constant IO_STDIN_ADDR : integer := IO_BASE_ADDR + 2*IO_ADDR_RANGE;
constant IO_READ_ADDR : integer := IO_BASE_ADDR + 3*IO_ADDR_RANGE;
constant IO_WRITE_ADDR : integer := IO_BASE_ADDR + 4*IO_ADDR_RANGE;
constant IO_COUNT_ADDR : integer := IO_BASE_ADDR + 5*IO_ADDR_RANGE;
constant IO_FPU_ADDR : integer := IO_BASE_ADDR + 6*IO_ADDR_RANGE;
constant IO_UART_ADDR : integer := IO_BASE_ADDR + 7*IO_ADDR_RANGE;
constant IO_STATS_ADDR : integer := IO_BASE_ADDR + 8*IO_ADDR_RANGE;
constant IO_DSP7SEG_ADDR : integer := IO_BASE_ADDR + 9*IO_ADDR_RANGE;
constant IO_KEYBD_ADDR : integer := IO_BASE_ADDR + 10*IO_ADDR_RANGE;
constant IO_LCD_ADDR : integer := IO_BASE_ADDR + 11*IO_ADDR_RANGE;
constant IO_SDC_ADDR : integer := IO_BASE_ADDR + 12*IO_ADDR_RANGE;
constant IO_DMA_ADDR : integer := IO_BASE_ADDR + 13*IO_ADDR_RANGE;
constant IO_HIGHEST_ADDR : integer :=
IO_BASE_ADDR + (IO_MAX_NUM_DEVS - 1)*IO_ADDR_RANGE;
-- DATA CACHE parameters ================================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that DC_INDEX_BITS >= 6 (64 sets/way)
constant DC_TOTAL_CAPACITY : natural := 2*1024;
constant DC_NUM_WAYS : natural := 1; -- direct mapped
constant DC_VIA_CAPACITY : natural := DC_TOTAL_CAPACITY / DC_NUM_WAYS;
constant DC_BTS_PER_WORD : natural := 32;
constant DC_BYTES_PER_WORD : natural := 4;
constant DC_WORDS_PER_BLOCK : natural := 4;
constant DC_NUM_WORDS : natural := DC_VIA_CAPACITY / DC_BYTES_PER_WORD;
constant DC_NUM_BLOCKS : natural := DC_NUM_WORDS / DC_WORDS_PER_BLOCK;
constant DC_INDEX_BITS : natural := log2_ceil( DC_NUM_BLOCKS );
constant DC_WORD_SEL_BITS : natural := log2_ceil( DC_WORDS_PER_BLOCK );
constant DC_BYTE_SEL_BITS : natural := log2_ceil( DC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant DC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(DC_INDEX_BITS - 6, 3));
constant DC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(DC_WORD_SEL_BITS + 1, 3));
constant DC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(DC_NUM_WAYS - 1, 3));
-- INSTRUCTION CACHE parameters =========================================
-- The combination of capacity, associativity and block/line size
-- MUST be such that IC_INDEX_BITS >= 6 (64 sets/via)
constant IC_TOTAL_CAPACITY : natural := 1024; -- 2*1024;
constant IC_NUM_WAYS : natural := 1; -- direct mapped
constant IC_VIA_CAPACITY : natural := IC_TOTAL_CAPACITY / IC_NUM_WAYS;
constant IC_BTS_PER_WORD : natural := 32;
constant IC_BYTES_PER_WORD : natural := 4;
constant IC_WORDS_PER_BLOCK : natural := 4;
constant IC_NUM_WORDS : natural := IC_VIA_CAPACITY / IC_BYTES_PER_WORD;
constant IC_NUM_BLOCKS : natural := IC_NUM_WORDS / IC_WORDS_PER_BLOCK;
constant IC_INDEX_BITS : natural := log2_ceil( IC_NUM_BLOCKS );
constant IC_WORD_SEL_BITS : natural := log2_ceil( IC_WORDS_PER_BLOCK );
constant IC_BYTE_SEL_BITS : natural := log2_ceil( IC_BYTES_PER_WORD );
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant IC_SETS_PER_WAY: reg3 :=
std_logic_vector(to_signed(IC_INDEX_BITS - 6, 3));
constant IC_LINE_SIZE: reg3 :=
std_logic_vector(to_signed(IC_WORD_SEL_BITS + 1, 3));
constant IC_ASSOCIATIVITY: reg3 :=
std_logic_vector(to_signed(IC_NUM_WAYS - 1, 3));
-- constants to access the cache statistics counters
constant dcache_Stats_ref : reg3 := "000";
constant dcache_Stats_rdhit : reg3 := "001";
constant dcache_Stats_wrhit : reg3 := "010";
constant dcache_Stats_flush : reg3 := "011";
constant icache_Stats_ref : reg3 := "100";
constant icache_Stats_hit : reg3 := "101";
-- MMU parameters ========================================================
-- constants for CONFIG1 cop0 register (Table 8-24 pg 103)
constant MMU_CAPACITY : natural := 8;
constant MMU_CAPACITY_BITS : natural := log2_ceil( MMU_CAPACITY );
constant MMU_SIZE: reg6 :=
std_logic_vector(to_signed( (MMU_CAPACITY-1), 6) );
constant MMU_WIRED_INIT : reg32 := x"00000000";
constant VABITS : natural := 32;
constant PABITS : natural := 32;
constant PAGE_SZ : natural := 4096; -- 4k pages
constant PAGE_SZ_BITS : natural := log2_ceil( PAGE_SZ );
constant PPN_BITS : natural := PABITS - PAGE_SZ_BITS;
constant VA_HI_BIT : natural := 31; -- VAaddr in EntryHi 31..PG_size
constant VA_LO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant ASID_HI_BIT : natural := 7; -- ASID in EntryHi 7..0
constant ASID_LO_BIT : natural := 0;
constant EHI_ASIDLO_BIT : natural := 0;
constant EHI_ASIDHI_BIT : natural := 7;
constant EHI_G_BIT : natural := 8;
constant EHI_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant EHI_AHI_BIT : natural := 31;
constant EHI_ZEROS : std_logic_vector(PAGE_SZ_BITS-EHI_G_BIT-1 downto 0) := (others => '0');
constant TAG_ASIDLO_BIT : natural := 0;
constant TAG_ASIDHI_BIT : natural := 7;
constant TAG_G_BIT : natural := 8;
constant TAG_Z_BIT : natural := 9;
constant TAG_ALO_BIT : natural := PAGE_SZ_BITS + 1; -- maps 2 phy-pages
constant TAG_AHI_BIT : natural := 31;
constant ELO_G_BIT : natural := 0;
constant ELO_V_BIT : natural := 1;
constant ELO_D_BIT : natural := 2;
constant ELO_CLO_BIT : natural := 3;
constant ELO_CHI_BIT : natural := 5;
constant ELO_ALO_BIT : natural := 6;
constant ELO_AHI_BIT : natural := ELO_ALO_BIT + PPN_BITS - 1;
constant DAT_G_BIT : natural := 0;
constant DAT_V_BIT : natural := 1;
constant DAT_D_BIT : natural := 2;
constant DAT_CLO_BIT : natural := 3;
constant DAT_CHI_BIT : natural := 5;
constant DAT_ALO_BIT : natural := 6;
constant DAT_AHI_BIT : natural := DAT_ALO_BIT + PPN_BITS - 1;
constant DAT_REG_BITS : natural := DAT_ALO_BIT + PPN_BITS;
constant ContextPTE_init : reg9 := b"000000000";
constant mmu_PageMask : reg32 := x"00001800"; -- pg 68, 4k pages only
subtype mmu_dat_reg is std_logic_vector (DAT_AHI_BIT downto 0);
subtype MMU_idx_bits is std_logic_vector(MMU_CAPACITY_BITS-1 downto 0);
constant MMU_idx_0s : std_logic_vector(30 downto MMU_CAPACITY_BITS) :=
(others => '0');
constant MMU_IDX_BIT : natural := 31; -- probe hit=1, miss=0
-- VA tags map a pair of PHY pages, thus VAddr is 1 bit less than (VABITS-1..PAGE_SZ_BITS)
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
constant x_ROM_PPN_0 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_ROM_PPN_1 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_ROM_PPN_2 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_ROM_PPN_3 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_ROM_PPN_4 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_ROM_PPN_5 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
x_ROM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 RAM pages
constant x_RAM_PPN_0 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_RAM_PPN_1 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_RAM_PPN_2 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_RAM_PPN_3 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_RAM_PPN_4 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_RAM_PPN_5 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
x_RAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 2 pages reserved for I/O devices
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 1*PAGE_SZ, 32));
constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
x_IO_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
-- physical addresses for 8 SDRAM pages
constant x_SDRAM_PPN_0 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_SDRAM_PPN_1 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 1*PAGE_SZ, 32));
constant x_SDRAM_PPN_2 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 2*PAGE_SZ, 32));
constant x_SDRAM_PPN_3 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 3*PAGE_SZ, 32));
constant x_SDRAM_PPN_4 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 4*PAGE_SZ, 32));
constant x_SDRAM_PPN_5 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 5*PAGE_SZ, 32));
constant x_SDRAM_PPN_6 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_SDRAM_PPN_7 : reg32 := std_logic_vector(to_signed(SDRAM_BASE_ADDR + 7*PAGE_SZ, 32));
constant MMU_ini_tag_SDR0 : reg32 := (x_SDRAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR0 : mmu_dat_reg :=
x_SDRAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR1 : mmu_dat_reg :=
x_SDRAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR2 : reg32 := (x_SDRAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR2 : mmu_dat_reg :=
x_SDRAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR3 : mmu_dat_reg :=
x_SDRAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR4 : reg32 := (x_SDRAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR4 : mmu_dat_reg :=
x_SDRAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR5 : mmu_dat_reg :=
x_SDRAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_tag_SDR6 : reg32 := (x_SDRAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_SDR6 : mmu_dat_reg :=
x_SDRAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_SDR7 : mmu_dat_reg :=
x_SDRAM_PPN_7(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
end p_MEMORY;
-- package body p_MEMORY is
-- end p_MEMORY;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_20.vhd
|
1
|
6899
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_16x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A39: buffer std_logic
);
end x25_16x;
architecture x25_16x_behav of x25_16x is
signal n_32,n_33,n_37,n_38,n_39,n_40,n_46,n_47,n_48,n_49,n_55,n_56,n_57,n_58,n_59,n_60,n_66,n_67,n_68,n_69,n_72,n_73,n_74,n_81,n_82,n_83,n_84,n_87,n_88,n_91,n_94,n_97,n_98,n_99,n_104,n_105,n_106,n_107,n_108,n_109,n_114,n_120,n_121,n_122,n_123,n_126,n_127,n_128,n_129,n_130,n_135,n_136,n_140,n_141,n_142,n_143,n_149,n_150,n_151,n_152,n_158,n_159,n_160,n_161,n_165,n_168,n_171,n_172,n_173,n_178,n_179,n_180,n_181,n_182,n_187,n_188,n_189,n_190,n_191,n_192,n_193,n_197,n_200,n_203,n_204,n_205,n_210,n_211,n_212,n_213,n_214,n_219,n_220,n_221,n_222,n_223,n_228,n_229,n_233,n_234,n_235,n_236,n_242,n_243,n_244,n_245,n_251,n_252,n_253,n_254,n_255,n_256,n_262,n_263,n_267,n_268,n_269,n_270,n_276,n_277,n_278,n_279,n_285,n_286,n_287,n_288,n_289,n_290,n_293,n_296,n_299,n_300,n_301,n_306,n_307,n_308,n_309,n_310,n_311,n_316,n_321,n_322,n_326,n_327,n_328,n_329,n_335,n_336,n_337,n_338,n_344,n_345,n_346,n_347,n_348,n_349,n_350,n_351,n_352,n_353,n_354,n_355,n_356,n_357,n_358: std_logic;
begin
A39 <=( (not n_358) );
n_32 <=( (not A202) and A203 );
n_33 <=( A200 and n_32 );
n_37 <=( A202 and (not A203) );
n_38 <=( (not A200) and n_37 );
n_39 <=( n_38 ) or ( n_33 );
n_40 <=( (not A199) and n_39 );
n_46 <=( A202 and (not A203) );
n_47 <=( A199 and n_46 );
n_48 <=( n_47 ) or ( A201 );
n_49 <=( A200 and n_48 );
n_55 <=( (not A202) and A203 );
n_56 <=( (not A200) and n_55 );
n_57 <=( n_56 ) or ( A201 );
n_58 <=( A199 and n_57 );
n_59 <=( n_58 ) or ( n_49 );
n_60 <=( n_59 ) or ( n_40 );
n_66 <=( A170 ) or ( A169 );
n_67 <=( A168 and n_66 );
n_68 <=( (not A167) and n_67 );
n_69 <=( A166 and n_68 );
n_72 <=( (not A166) and A167 );
n_73 <=( n_72 ) or ( n_69 );
n_74 <=( n_60 and n_73 );
n_81 <=( (not A169) and (not A170) );
n_82 <=( n_81 ) or ( (not A168) );
n_83 <=( n_82 ) or ( (not A166) );
n_84 <=( (not A167) and n_83 );
n_87 <=( A166 and A167 );
n_88 <=( n_87 ) or ( n_84 );
n_91 <=( (not A203) ) or ( A202 );
n_94 <=( (not A199) and A200 );
n_97 <=( A199 and (not A200) );
n_98 <=( n_97 ) or ( n_94 );
n_99 <=( n_91 and n_98 );
n_104 <=( A203 ) or ( (not A202) );
n_105 <=( A200 and n_104 );
n_106 <=( A199 and n_105 );
n_107 <=( n_106 ) or ( n_99 );
n_108 <=( n_88 and n_107 );
n_109 <=( (not A201) and n_108 );
n_114 <=( A203 ) or ( (not A202) );
n_120 <=( (not A169) and (not A170) );
n_121 <=( n_120 ) or ( (not A168) );
n_122 <=( n_121 ) or ( (not A166) );
n_123 <=( (not A167) and n_122 );
n_126 <=( A166 and A167 );
n_127 <=( n_126 ) or ( n_123 );
n_128 <=( n_114 and n_127 );
n_129 <=( (not A200) and n_128 );
n_130 <=( (not A199) and n_129 );
n_135 <=( (not A268) and A269 );
n_136 <=( A266 and n_135 );
n_140 <=( A268 and (not A269) );
n_141 <=( (not A266) and n_140 );
n_142 <=( n_141 ) or ( n_136 );
n_143 <=( (not A265) and n_142 );
n_149 <=( A268 and (not A269) );
n_150 <=( A265 and n_149 );
n_151 <=( n_150 ) or ( A267 );
n_152 <=( A266 and n_151 );
n_158 <=( (not A268) and A269 );
n_159 <=( (not A266) and n_158 );
n_160 <=( n_159 ) or ( A267 );
n_161 <=( A265 and n_160 );
n_165 <=( (not A302) ) or ( A301 );
n_168 <=( (not A298) and A299 );
n_171 <=( A298 and (not A299) );
n_172 <=( n_171 ) or ( n_168 );
n_173 <=( n_165 and n_172 );
n_178 <=( A302 ) or ( (not A301) );
n_179 <=( A299 and n_178 );
n_180 <=( A298 and n_179 );
n_181 <=( n_180 ) or ( n_173 );
n_182 <=( (not A300) and n_181 );
n_187 <=( A302 ) or ( (not A301) );
n_188 <=( (not A299) and n_187 );
n_189 <=( (not A298) and n_188 );
n_190 <=( n_189 ) or ( n_182 );
n_191 <=( n_190 ) or ( n_161 );
n_192 <=( n_191 ) or ( n_152 );
n_193 <=( n_192 ) or ( n_143 );
n_197 <=( (not A236) ) or ( A235 );
n_200 <=( (not A232) and A233 );
n_203 <=( A232 and (not A233) );
n_204 <=( n_203 ) or ( n_200 );
n_205 <=( n_197 and n_204 );
n_210 <=( A236 ) or ( (not A235) );
n_211 <=( A233 and n_210 );
n_212 <=( A232 and n_211 );
n_213 <=( n_212 ) or ( n_205 );
n_214 <=( (not A234) and n_213 );
n_219 <=( A236 ) or ( (not A235) );
n_220 <=( (not A233) and n_219 );
n_221 <=( (not A232) and n_220 );
n_222 <=( n_221 ) or ( n_214 );
n_223 <=( n_193 and n_222 );
n_228 <=( (not A301) and A302 );
n_229 <=( A299 and n_228 );
n_233 <=( A301 and (not A302) );
n_234 <=( (not A299) and n_233 );
n_235 <=( n_234 ) or ( n_229 );
n_236 <=( (not A298) and n_235 );
n_242 <=( A301 and (not A302) );
n_243 <=( A298 and n_242 );
n_244 <=( n_243 ) or ( A300 );
n_245 <=( A299 and n_244 );
n_251 <=( (not A301) and A302 );
n_252 <=( (not A299) and n_251 );
n_253 <=( n_252 ) or ( A300 );
n_254 <=( A298 and n_253 );
n_255 <=( n_254 ) or ( n_245 );
n_256 <=( n_255 ) or ( n_236 );
n_262 <=( (not A235) and A236 );
n_263 <=( A233 and n_262 );
n_267 <=( A235 and (not A236) );
n_268 <=( (not A233) and n_267 );
n_269 <=( n_268 ) or ( n_263 );
n_270 <=( (not A232) and n_269 );
n_276 <=( A235 and (not A236) );
n_277 <=( A232 and n_276 );
n_278 <=( n_277 ) or ( A234 );
n_279 <=( A233 and n_278 );
n_285 <=( (not A235) and A236 );
n_286 <=( (not A233) and n_285 );
n_287 <=( n_286 ) or ( A234 );
n_288 <=( A232 and n_287 );
n_289 <=( n_288 ) or ( n_279 );
n_290 <=( n_289 ) or ( n_270 );
n_293 <=( (not A269) ) or ( A268 );
n_296 <=( (not A265) and A266 );
n_299 <=( A265 and (not A266) );
n_300 <=( n_299 ) or ( n_296 );
n_301 <=( n_293 and n_300 );
n_306 <=( A269 ) or ( (not A268) );
n_307 <=( A266 and n_306 );
n_308 <=( A265 and n_307 );
n_309 <=( n_308 ) or ( n_301 );
n_310 <=( n_290 and n_309 );
n_311 <=( (not A267) and n_310 );
n_316 <=( A269 ) or ( (not A268) );
n_321 <=( (not A235) and A236 );
n_322 <=( A233 and n_321 );
n_326 <=( A235 and (not A236) );
n_327 <=( (not A233) and n_326 );
n_328 <=( n_327 ) or ( n_322 );
n_329 <=( (not A232) and n_328 );
n_335 <=( A235 and (not A236) );
n_336 <=( A232 and n_335 );
n_337 <=( n_336 ) or ( A234 );
n_338 <=( A233 and n_337 );
n_344 <=( (not A235) and A236 );
n_345 <=( (not A233) and n_344 );
n_346 <=( n_345 ) or ( A234 );
n_347 <=( A232 and n_346 );
n_348 <=( n_347 ) or ( n_338 );
n_349 <=( n_348 ) or ( n_329 );
n_350 <=( n_316 and n_349 );
n_351 <=( (not A266) and n_350 );
n_352 <=( (not A265) and n_351 );
n_353 <=( n_352 ) or ( n_311 );
n_354 <=( n_256 and n_353 );
n_355 <=( n_354 ) or ( n_223 );
n_356 <=( n_355 ) or ( n_130 );
n_357 <=( n_356 ) or ( n_109 );
n_358 <=( n_357 ) or ( n_74 );
end x25_16x_behav;
|
gpl-3.0
|
jouyang3/FMCW
|
DSP/Radar_DSP/FPGA/Individual Modules/Working_FFT/Working_FFT/FFT_Mag/simulation/modelsim/work/dft_top/_primary.vhd
|
2
|
766
|
library verilog;
use verilog.vl_types.all;
entity dft_top is
port(
clk : in vl_logic;
reset : in vl_logic;
\next\ : in vl_logic;
next_out : out vl_logic;
X0 : in vl_logic_vector(11 downto 0);
Y0 : out vl_logic_vector(11 downto 0);
X1 : in vl_logic_vector(11 downto 0);
Y1 : out vl_logic_vector(11 downto 0);
X2 : in vl_logic_vector(11 downto 0);
Y2 : out vl_logic_vector(11 downto 0);
X3 : in vl_logic_vector(11 downto 0);
Y3 : out vl_logic_vector(11 downto 0)
);
end dft_top;
|
gpl-3.0
|
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