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aospan/NetUP_Dual_Universal_CI-fpga
|
pcie_compiler_0_serdes.vhd
|
1
|
107048
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- megafunction wizard: %ALTGX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt_c3gxb
-- ============================================================
-- File Name: pcie_compiler_0_serdes.vhd
-- Megafunction Name(s):
-- alt_c3gxb
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" equalization_setting=1 equalizer_dcgain_setting=1 gxb_powerdown_width=1 hip_enable="true" loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="2" pll_inclk_period=10000 pll_multiply_by="25" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=1 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="pipe" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="false" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="pcie_compiler_0_serdes" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_bonding="indv" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="low" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_areset pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle intended_device_family="Cyclone IV GX"
--VERSION_BEGIN 11.1SP2 cbx_alt_c3gxb 2012:01:25:21:13:53:SJ cbx_altclkbuf 2012:01:25:21:13:53:SJ cbx_altiobuf_bidir 2012:01:25:21:13:53:SJ cbx_altiobuf_in 2012:01:25:21:13:53:SJ cbx_altiobuf_out 2012:01:25:21:13:53:SJ cbx_altpll 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stingray 2012:01:25:21:13:52:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY altera_mf;
USE altera_mf.all;
LIBRARY cycloneiv_hssi;
USE cycloneiv_hssi.all;
--synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pcie_compiler_0_serdes_alt_c3gxb_euf8 IS
GENERIC
(
starting_channel_number : NATURAL := 0
);
PORT
(
cal_blk_clk : IN STD_LOGIC := '0';
fixedclk : IN STD_LOGIC := '0';
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
reconfig_clk : IN STD_LOGIC := '0';
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => 'Z');
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => 'Z');
rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
);
END pcie_compiler_0_serdes_alt_c3gxb_euf8;
ARCHITECTURE RTL OF pcie_compiler_0_serdes_alt_c3gxb_euf8 IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "suppress_da_rule_internal=c104";
SIGNAL wire_pll0_areset : STD_LOGIC;
SIGNAL wire_w_lg_w_pll_areset_range32w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pll0_clk : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_pll0_fref : STD_LOGIC;
SIGNAL wire_pll0_icdrclk : STD_LOGIC;
SIGNAL wire_pll0_inclk : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_pll0_locked : STD_LOGIC;
SIGNAL wire_cal_blk0_nonusertocmu : STD_LOGIC;
SIGNAL wire_cent_unit0_adet : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_dpriodisableout : STD_LOGIC;
SIGNAL wire_cent_unit0_dprioout : STD_LOGIC;
SIGNAL wire_cent_unit0_fixedclk : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_quadresetout : STD_LOGIC;
SIGNAL wire_cent_unit0_rdalign : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_cent_unit0_rxanalogreset : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxanalogresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxcrupowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxctrl : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdatain : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdatavalid : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdigitalreset : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxdigitalresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxibpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpcsdprioin : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpcsdprioout : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_cent_unit0_rxpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_rxrunningdisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_syncstatus : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txanalogresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txctrl : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdatain : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_cent_unit0_txdetectrxpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdigitalreset : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdigitalresetout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txdividerpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txobpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_cent_unit0_txpcsdprioin : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL wire_cent_unit0_txpcsdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL wire_cent_unit0_txpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_cent_unit0_txpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL wire_receive_pcs0_cdrctrlearlyeios : STD_LOGIC;
SIGNAL wire_receive_pcs0_cdrctrllocktorefclkout : STD_LOGIC;
SIGNAL wire_receive_pcs0_dprioout : STD_LOGIC_VECTOR (399 DOWNTO 0);
SIGNAL wire_receive_pcs0_hipdataout : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_receive_pcs0_hipdatavalid : STD_LOGIC;
SIGNAL wire_receive_pcs0_hipelecidle : STD_LOGIC;
SIGNAL wire_receive_pcs0_hipelecidleinfersel : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_receive_pcs0_hipphydonestatus : STD_LOGIC;
SIGNAL wire_receive_pcs0_hipstatus : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_receive_pcs0_parallelfdbk : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs0_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs0_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_receive_pma0_w_lg_freqlocked337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_receive_pma0_analogtestbus : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_receive_pma0_clockout : STD_LOGIC;
SIGNAL wire_receive_pma0_diagnosticlpbkout : STD_LOGIC;
SIGNAL wire_receive_pma0_dprioout : STD_LOGIC_VECTOR (299 DOWNTO 0);
SIGNAL wire_receive_pma0_freqlocked : STD_LOGIC;
SIGNAL wire_receive_pma0_locktodata : STD_LOGIC;
SIGNAL wire_w_lg_w_lg_reconfig_togxb_busy267w326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_receive_pma0_locktorefout : STD_LOGIC;
SIGNAL wire_receive_pma0_recoverdataout : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_receive_pma0_reverselpbkout : STD_LOGIC;
SIGNAL wire_receive_pma0_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pma0_testbussel : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_clkout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_ctrlenable : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_datainfull : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dataout : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dispval : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forcedisp : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forceelecidleout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_transmit_pcs0_hipdatain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs0_hiptxclkout : STD_LOGIC;
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_transmit_pcs0_pipeenrevparallellpbkout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_pipepowerdownout : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_transmit_pcs0_pipepowerstateout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_txdetectrx : STD_LOGIC;
SIGNAL wire_transmit_pma0_clockout : STD_LOGIC;
SIGNAL wire_transmit_pma0_datain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pma0_dataout : STD_LOGIC;
SIGNAL wire_transmit_pma0_dprioout : STD_LOGIC_VECTOR (299 DOWNTO 0);
SIGNAL wire_transmit_pma0_rxdetectvalidout : STD_LOGIC;
SIGNAL wire_transmit_pma0_rxfoundout : STD_LOGIC;
SIGNAL wire_transmit_pma0_seriallpbkout : STD_LOGIC;
SIGNAL fixedclk_div : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL reconfig_togxb_busy_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel39w56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_fixedclk_sel35w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_reconfig_togxb_busy267w268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_fixedclk_sel39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_fixedclk_enable34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_fixedclk_sel35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_reconfig_togxb_busy267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_rx_analogreset_range266w336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cal_blk_powerdown : STD_LOGIC;
SIGNAL cent_unit_quadresetout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cent_unit_rxcrupowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_rxibpowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_rxpcsdprioin : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL cent_unit_rxpcsdprioout : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL cent_unit_rxpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL cent_unit_rxpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL cent_unit_tx_dprioin : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL cent_unit_txdetectrxpowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_txdividerpowerdown : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_txdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL cent_unit_txobpowerdn : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cent_unit_txpmadprioin : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL cent_unit_txpmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL fixedclk_div_in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fixedclk_enable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fixedclk_fast : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL fixedclk_sel : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fixedclk_to_cmu : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL int_pipeenrevparallellpbkfromtx : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL nonusertocmu_out : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL pipedatavalid_out : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL pipeelecidle_out : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL pll_powerdown : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_busy : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_disable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reconfig_togxb_load : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL refclk_pma : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_analogreset_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_analogreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_deserclock_in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_digitalreset_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_digitalreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_enapatternalign : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_locktodata : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_locktorefclk_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_out_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL rx_pcs_rxfound_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL rx_pcsdprioin_wire : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL rx_pcsdprioout : STD_LOGIC_VECTOR (1599 DOWNTO 0);
SIGNAL rx_phfifordenable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_phfiforeset : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_phfifowrdisable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_pll_pfdrefclkout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_pma_analogtestbus : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rx_pma_clockout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_pma_recoverdataout_wire : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL rx_pmadprioin_wire : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL rx_pmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL rx_powerdown : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_powerdown_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL rx_prbscidenable : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_reverselpbkout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL rx_rmfiforeset : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL rx_signaldetect_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_analogreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_clkout_int_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_core_clkout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_datain_wire : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL tx_dataout_pcs_to_pma : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL tx_diagnosticlpbkin : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_digitalreset_in : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_digitalreset_out : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_dprioin_wire : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL tx_invpolarity : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_localrefclk : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pcs_forceelecidleout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_phfiforeset : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pipepowerdownout : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL tx_pipepowerstateout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL tx_pma_fastrefclk0in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pma_refclk0in : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pma_refclk0inpulse : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_pmadprioin_wire : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL tx_pmadprioout : STD_LOGIC_VECTOR (1199 DOWNTO 0);
SIGNAL tx_revparallellpbken : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_rxdetectvalidout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_rxfoundout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_serialloopbackout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tx_txdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL txdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL txdetectrxout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL w_cent_unit_dpriodisableout1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_fast_range55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_rx_analogreset_range266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC
(
bandwidth_type : STRING := "AUTO";
clk0_divide_by : NATURAL := 1;
clk0_multiply_by : NATURAL := 1;
clk1_divide_by : NATURAL := 1;
clk1_multiply_by : NATURAL := 1;
clk2_divide_by : NATURAL := 1;
clk2_duty_cycle : NATURAL := 50;
clk2_multiply_by : NATURAL := 1;
DPA_DIVIDE_BY : NATURAL := 1;
DPA_MULTIPLY_BY : NATURAL := 0;
inclk0_input_frequency : NATURAL := 0;
operation_mode : STRING := "normal";
INTENDED_DEVICE_FAMILY : STRING := "Cyclone IV GX"
);
PORT
(
areset : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
fref : OUT STD_LOGIC;
icdrclk : OUT STD_LOGIC;
inclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiv_hssi_calibration_block
GENERIC
(
cont_cal_mode : STRING := "false";
enable_rx_cal_tw : STRING := "false";
enable_tx_cal_tw : STRING := "false";
rtest : STRING := "false";
rx_cal_wt_value : NATURAL := 0;
send_rx_cal_status : STRING := "false";
tx_cal_wt_value : NATURAL := 1;
lpm_type : STRING := "cycloneiv_hssi_calibration_block"
);
PORT
(
calibrationstatus : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
clk : IN STD_LOGIC := '0';
nonusertocmu : OUT STD_LOGIC;
powerdn : IN STD_LOGIC := '0';
testctrl : IN STD_LOGIC := '0'
);
END COMPONENT;
COMPONENT cycloneiv_hssi_cmu
GENERIC
(
auto_spd_deassert_ph_fifo_rst_count : NATURAL := 0;
auto_spd_phystatus_notify_count : NATURAL := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
devaddr : NATURAL := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
portaddr : NATURAL := 1;
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_logical_to_physical_mapping : NATURAL := 0;
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx1_logical_to_physical_mapping : NATURAL := 1;
rx2_logical_to_physical_mapping : NATURAL := 2;
rx3_logical_to_physical_mapping : NATURAL := 3;
rx_xaui_sm_backward_compatible_enable : STRING := "false";
select_refclk_dig : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_logical_to_physical_mapping : NATURAL := 0;
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "local";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx1_logical_to_physical_mapping : NATURAL := 1;
tx2_logical_to_physical_mapping : NATURAL := 2;
tx3_logical_to_physical_mapping : NATURAL := 3;
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_coreclk_out_post_divider : STRING := "false";
use_deskew_fifo : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_cmu"
);
PORT
(
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
alignstatus : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dpriodisableout : OUT STD_LOGIC;
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
fixedclk : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
quadresetout : OUT STD_LOGIC;
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rdenablesync : IN STD_LOGIC := '1';
recovclk : IN STD_LOGIC := '0';
refclkdig : IN STD_LOGIC := '0';
refclkout : OUT STD_LOGIC;
rxanalogreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcoreclk : IN STD_LOGIC := '0';
rxcrupowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (OTHERS => '0');
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifordenable : IN STD_LOGIC := '1';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (OTHERS => '0');
rxpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0);
rxpowerdown : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
scanclk : IN STD_LOGIC := '0';
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
testin : IN STD_LOGIC_VECTOR(1999 DOWNTO 0) := (OTHERS => '0');
testout : OUT STD_LOGIC_VECTOR(2399 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (OTHERS => '0');
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioin : IN STD_LOGIC_VECTOR(1199 DOWNTO 0) := (OTHERS => '0');
txpmadprioout : OUT STD_LOGIC_VECTOR(1199 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiv_hssi_rx_pcs
GENERIC
(
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "UNUSED";
align_pattern_length : NATURAL := 7;
align_to_deskew_pattern_pos_disp_only : STRING := "false";
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : NATURAL := 0;
auto_spd_phystatus_notify_count : NATURAL := 0;
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none";
byte_order_pad_pattern : STRING := "UNUSED";
byte_order_pattern : STRING := "UNUSED";
byte_order_pld_ctrl_enable : STRING := "false";
cdrctrl_bypass_ppm_detector_cycle : NATURAL := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : NATURAL := 0;
cdrctrl_min_lock_to_ref_cycle : NATURAL := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none";
channel_number : NATURAL := 0;
channel_width : NATURAL := 8;
clk1_mux_select : STRING := "recovered clock";
clk2_mux_select : STRING := "recovered clock";
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic";
dec_8b_10b_compatibility_mode : STRING := "false";
dec_8b_10b_mode : STRING := "none";
deskew_pattern : STRING := "UNUSED";
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_num_com_detect : NATURAL := 0;
enable_bit_reversal : STRING := "false";
enable_self_test_mode : STRING := "false";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : NATURAL := 0;
insert_pad_on_underflow : STRING := "false";
logical_channel_address : NATURAL := 0;
num_align_code_groups_in_ordered_set : NATURAL := 0;
num_align_cons_good_data : NATURAL := 1;
num_align_cons_pat : NATURAL := 1;
num_align_loss_sync_error : NATURAL := 1;
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
phystatus_delay : NATURAL := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : NATURAL := 0;
protocol_hint : STRING := "basic";
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : NATURAL := 0;
rate_match_empty_threshold : NATURAL := 0;
rate_match_fifo_mode : STRING := "false";
rate_match_full_threshold : NATURAL := 0;
rate_match_insert_threshold : NATURAL := 0;
rate_match_ordered_set_based : STRING := "false";
rate_match_pattern1 : STRING := "UNUSED";
rate_match_pattern2 : STRING := "UNUSED";
rate_match_pattern_size : NATURAL := 10;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "false";
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : NATURAL := 0;
rd_clk_mux_select : STRING := "int clock";
recovered_clk_mux_select : STRING := "recovered clock";
reset_clock_output_during_digital_reset : STRING := "false";
run_length : NATURAL := 4;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : NATURAL := 0;
rxstatus_error_report_mode : NATURAL := 0;
self_test_mode : STRING := "prbs7";
test_bus_sel : NATURAL := 0;
use_alignment_state_machine : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_rx_pcs"
);
PORT
(
a1a2size : IN STD_LOGIC := '0';
a1a2sizeout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a1detect : OUT STD_LOGIC;
a2detect : OUT STD_LOGIC;
adetectdeskew : OUT STD_LOGIC;
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
alignstatussyncout : OUT STD_LOGIC;
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslip : IN STD_LOGIC := '0';
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC;
cdrctrllocktorefcl : IN STD_LOGIC := '0';
cdrctrllocktorefclkout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC;
coreclk : IN STD_LOGIC := '0';
coreclkout : OUT STD_LOGIC;
ctrldetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
digitalreset : IN STD_LOGIC := '0';
disperr : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
errdetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
fifordin : IN STD_LOGIC := '0';
fifordout : OUT STD_LOGIC;
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0';
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
hipdatavalid : OUT STD_LOGIC;
hipelecidle : OUT STD_LOGIC;
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
hipphydonestatus : OUT STD_LOGIC;
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
invpol : IN STD_LOGIC := '0';
k1detect : OUT STD_LOGIC;
k2detect : OUT STD_LOGIC;
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
patterndetect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfifordenable : IN STD_LOGIC := '1';
phfifordenableout : OUT STD_LOGIC;
phfiforeset : IN STD_LOGIC := '0';
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrdisable : IN STD_LOGIC := '0';
phfifowrdisableout : OUT STD_LOGIC;
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipephydonestatus : OUT STD_LOGIC;
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
pipestatetransdoneout : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rdalign : OUT STD_LOGIC;
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
rmfifordena : IN STD_LOGIC := '1';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '1';
runningdisp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxdetectvalid : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
signaldetect : OUT STD_LOGIC;
signaldetected : IN STD_LOGIC := '0';
syncstatus : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
wareset : IN STD_LOGIC := '0';
xauidelcondmet : IN STD_LOGIC := '0';
xauidelcondmetout : OUT STD_LOGIC;
xauififoovr : IN STD_LOGIC := '0';
xauififoovrout : OUT STD_LOGIC;
xauiinsertincomplete : IN STD_LOGIC := '0';
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycomp : IN STD_LOGIC := '0';
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiv_hssi_rx_pma
GENERIC
(
allow_serial_loopback : STRING := "false";
channel_number : NATURAL := 0;
common_mode : STRING := "0.82V";
deserialization_factor : NATURAL := 8;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "UNUSED";
enable_dpa_shift : STRING := "false";
enable_initial_phase_selection : STRING := "true";
enable_local_divider : STRING := "false";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
enable_pd_counter_accumulate_mode : STRING := "true";
enable_second_order_loop : STRING := "false";
eq_dc_gain : NATURAL := 0;
eq_setting : NATURAL := 1;
force_signal_detect : STRING := "false";
initial_phase_value : NATURAL := 0;
logical_channel_address : NATURAL := 0;
loop_1_digital_filter : NATURAL := 8;
offset_cancellation : NATURAL := 0;
pd1_counter_setting : NATURAL := 3;
pd2_counter_setting : NATURAL := 2;
pd_rising_edge_only : STRING := "false";
phase_step_add_setting : NATURAL := 2;
phase_step_sub_setting : NATURAL := 1;
pi_frequency_selector : NATURAL := 0;
ppm_gen1_2_xcnt_en : NATURAL := 0;
ppm_post_eidle : NATURAL := 0;
ppmselect : NATURAL := 0;
protocol_hint : STRING := "basic";
send_reverse_serial_loopback_data : STRING := "false";
send_reverse_serial_loopback_recovered_clk : STRING := "false";
signal_detect_hysteresis : NATURAL := 4;
signal_detect_hysteresis_valid_threshold : NATURAL := 14;
signal_detect_loss_threshold : NATURAL := 3;
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
lpm_type : STRING := "cycloneiv_hssi_rx_pma"
);
PORT
(
analogtestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clockout : OUT STD_LOGIC;
crupowerdn : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
datastrobeout : OUT STD_LOGIC;
deserclock : IN STD_LOGIC := '0';
diagnosticlpbkout : OUT STD_LOGIC;
dpashift : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(299 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(299 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
locktorefout : OUT STD_LOGIC;
powerdn : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
rxpmareset : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
signaldetect : OUT STD_LOGIC;
testbussel : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT cycloneiv_hssi_tx_pcs
GENERIC
(
allow_polarity_inversion : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none";
channel_number : NATURAL := 0;
channel_width : NATURAL := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic";
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : NATURAL := 3;
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "false";
enc_8b_10b_mode : STRING := "none";
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
logical_channel_address : NATURAL := 0;
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
pipe_voltage_swing_control : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : NATURAL := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local";
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "crpat";
use_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "int_clk";
lpm_type : STRING := "cycloneiv_hssi_tx_pcs"
);
PORT
(
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
clkout : OUT STD_LOGIC;
coreclk : IN STD_LOGIC := '0';
coreclkout : OUT STD_LOGIC;
ctrlenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
datainfull : IN STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
hiptxclkout : OUT STD_LOGIC;
invpol : IN STD_LOGIC := '0';
localrefclk : IN STD_LOGIC := '0';
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifooverflow : OUT STD_LOGIC;
phfiforddisable : IN STD_LOGIC := '0';
phfiforddisableout : OUT STD_LOGIC;
phfiforeset : IN STD_LOGIC := '0';
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenable : IN STD_LOGIC := '1';
phfifowrenableout : OUT STD_LOGIC;
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipestatetransdone : IN STD_LOGIC := '0';
pipetxswing : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rdenablesync : OUT STD_LOGIC;
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
txdetectrx : OUT STD_LOGIC;
xgmctrl : IN STD_LOGIC := '0';
xgmctrlenable : OUT STD_LOGIC;
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiv_hssi_tx_pma
GENERIC
(
channel_number : NATURAL := 0;
common_mode : STRING := "0.65V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "UNUSED";
enable_diagnostic_loopback : STRING := "false";
enable_reverse_serial_loopback : STRING := "false";
enable_txclkout_loopback : STRING := "false";
logical_channel_address : NATURAL := 0;
preemp_tap_1 : NATURAL := 0;
protocol_hint : STRING := "basic";
rx_detect : NATURAL := 0;
serialization_factor : NATURAL := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_rx_detect : STRING := "false";
vod_selection : NATURAL := 0;
lpm_type : STRING := "cycloneiv_hssi_tx_pma"
);
PORT
(
cgbpowerdn : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC;
detectrxpowerdown : IN STD_LOGIC := '0';
diagnosticlpbkin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '0';
dprioin : IN STD_LOGIC_VECTOR(299 DOWNTO 0) := (OTHERS => '0');
dprioout : OUT STD_LOGIC_VECTOR(299 DOWNTO 0);
fastrefclk0in : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC := '0';
refclk0inpulse : IN STD_LOGIC := '0';
reverselpbkin : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC;
txpmareset : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w(0) <= wire_w_lg_w_lg_fixedclk_sel39w40w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w(0) <= wire_w_lg_w_lg_fixedclk_sel39w46w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w(0) <= wire_w_lg_w_lg_fixedclk_sel39w51w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w(0) <= wire_w_lg_w_lg_fixedclk_sel39w56w(0) AND fixedclk_div_in(0);
wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0) <= wire_w_lg_w_lg_fixedclk_sel35w36w(0) AND fixedclk;
wire_w_lg_w_lg_fixedclk_sel39w40w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range38w(0);
wire_w_lg_w_lg_fixedclk_sel39w46w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range45w(0);
wire_w_lg_w_lg_fixedclk_sel39w51w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range50w(0);
wire_w_lg_w_lg_fixedclk_sel39w56w(0) <= wire_w_lg_fixedclk_sel39w(0) AND wire_w_fixedclk_fast_range55w(0);
wire_w_lg_w_lg_fixedclk_sel35w36w(0) <= wire_w_lg_fixedclk_sel35w(0) AND wire_w_lg_fixedclk_enable34w(0);
wire_w_lg_w_lg_reconfig_togxb_busy267w268w(0) <= wire_w_lg_reconfig_togxb_busy267w(0) AND wire_w_rx_analogreset_range266w(0);
wire_w_lg_fixedclk_sel39w(0) <= fixedclk_sel(0) AND fixedclk_enable(0);
wire_w_lg_fixedclk_enable34w(0) <= NOT fixedclk_enable(0);
wire_w_lg_fixedclk_sel35w(0) <= NOT fixedclk_sel(0);
wire_w_lg_reconfig_togxb_busy267w(0) <= NOT reconfig_togxb_busy(0);
wire_w_lg_w_rx_analogreset_range266w336w(0) <= NOT wire_w_rx_analogreset_range266w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w42w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w48w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w53w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w58w(0) <= wire_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w(0) OR wire_w_lg_w_lg_w_lg_fixedclk_sel35w36w37w(0);
cal_blk_powerdown <= '0';
cent_unit_quadresetout(0) <= ( wire_cent_unit0_quadresetout);
cent_unit_rxcrupowerdn <= ( wire_cent_unit0_rxcrupowerdown(3 DOWNTO 0));
cent_unit_rxibpowerdn <= ( wire_cent_unit0_rxibpowerdown(3 DOWNTO 0));
cent_unit_rxpcsdprioin <= ( "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& rx_pcsdprioout(399 DOWNTO 0));
cent_unit_rxpcsdprioout <= ( wire_cent_unit0_rxpcsdprioout(1599 DOWNTO 0));
cent_unit_rxpmadprioin <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & rx_pmadprioout(299 DOWNTO 0));
cent_unit_rxpmadprioout <= ( wire_cent_unit0_rxpmadprioout(1199 DOWNTO 0));
cent_unit_tx_dprioin <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & tx_txdprioout(149 DOWNTO 0));
cent_unit_txdetectrxpowerdn <= ( wire_cent_unit0_txdetectrxpowerdown(3 DOWNTO 0));
cent_unit_txdividerpowerdown <= ( wire_cent_unit0_txdividerpowerdown(3 DOWNTO 0));
cent_unit_txdprioout <= ( wire_cent_unit0_txpcsdprioout(599 DOWNTO 0));
cent_unit_txobpowerdn <= ( wire_cent_unit0_txobpowerdown(3 DOWNTO 0));
cent_unit_txpmadprioin <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & tx_pmadprioout(299 DOWNTO 0));
cent_unit_txpmadprioout <= ( wire_cent_unit0_txpmadprioout(1199 DOWNTO 0));
fixedclk_div_in <= fixedclk_div;
fixedclk_enable(0) <= reconfig_togxb_busy_reg(0);
fixedclk_fast <= (OTHERS => '1');
fixedclk_sel(0) <= reconfig_togxb_busy_reg(1);
fixedclk_to_cmu <= ( wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w56w57w58w & wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w51w52w53w & wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w46w47w48w & wire_w_lg_w_lg_w_lg_w_lg_fixedclk_sel39w40w41w42w);
hip_tx_clkout(0) <= ( wire_transmit_pcs0_hiptxclkout);
int_pipeenrevparallellpbkfromtx(0) <= ( wire_transmit_pcs0_pipeenrevparallellpbkout);
nonusertocmu_out(0) <= ( wire_cal_blk0_nonusertocmu);
pipedatavalid(0) <= ( pipedatavalid_out(0));
pipedatavalid_out(0) <= ( wire_receive_pcs0_hipdatavalid);
pipeelecidle(0) <= ( pipeelecidle_out(0));
pipeelecidle_out(0) <= ( wire_receive_pcs0_hipelecidle);
pipephydonestatus(0) <= ( wire_receive_pcs0_hipphydonestatus);
pipestatus <= ( wire_receive_pcs0_hipstatus);
pll_locked(0) <= ( wire_pll0_locked);
pll_powerdown <= (OTHERS => '0');
reconfig_fromgxb <= ( rx_pma_analogtestbus(4 DOWNTO 1) & wire_cent_unit0_dprioout);
reconfig_togxb_busy(0) <= reconfig_togxb(3);
reconfig_togxb_disable(0) <= reconfig_togxb(1);
reconfig_togxb_in(0) <= reconfig_togxb(0);
reconfig_togxb_load(0) <= reconfig_togxb(2);
rx_analogreset_in <= ( "000" & wire_w_lg_w_lg_reconfig_togxb_busy267w268w);
rx_analogreset_out <= ( wire_cent_unit0_rxanalogresetout(3 DOWNTO 0));
rx_ctrldetect(0) <= ( wire_receive_pcs0_hipdataout(8));
rx_dataout <= ( rx_out_wire(7 DOWNTO 0));
rx_deserclock_in(0) <= ( wire_pll0_icdrclk);
rx_digitalreset_in <= ( "000" & rx_digitalreset(0));
rx_digitalreset_out <= ( wire_cent_unit0_rxdigitalresetout(3 DOWNTO 0));
rx_enapatternalign <= (OTHERS => '0');
rx_freqlocked <= ( wire_receive_pma0_w_lg_freqlocked337w);
rx_locktodata <= (OTHERS => '0');
rx_locktorefclk_wire(0) <= ( wire_receive_pcs0_cdrctrllocktorefclkout);
rx_out_wire <= ( wire_receive_pcs0_hipdataout(7 DOWNTO 0));
rx_pcs_rxfound_wire <= ( txdetectrxout(0) & tx_rxfoundout(0));
rx_pcsdprioin_wire <= ( "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& cent_unit_rxpcsdprioout(399 DOWNTO 0));
rx_pcsdprioout <= ( "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
& wire_receive_pcs0_dprioout);
rx_phfifordenable <= (OTHERS => '1');
rx_phfiforeset <= (OTHERS => '0');
rx_phfifowrdisable <= (OTHERS => '0');
rx_pll_pfdrefclkout_wire(0) <= ( wire_pll0_fref);
rx_pma_analogtestbus <= ( "0000" & wire_receive_pma0_analogtestbus(6));
rx_pma_clockout(0) <= ( wire_receive_pma0_clockout);
rx_pma_recoverdataout_wire <= ( wire_receive_pma0_recoverdataout(9 DOWNTO 0));
rx_pmadprioin_wire <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & cent_unit_rxpmadprioout(299 DOWNTO 0));
rx_pmadprioout <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_receive_pma0_dprioout);
rx_powerdown <= (OTHERS => '0');
rx_powerdown_in <= ( "000" & rx_powerdown(0));
rx_prbscidenable <= (OTHERS => '0');
rx_reverselpbkout(0) <= ( wire_receive_pma0_reverselpbkout);
rx_revparallelfdbkdata <= ( wire_receive_pcs0_revparallelfdbkdata);
rx_rmfiforeset <= (OTHERS => '0');
rx_signaldetect_wire(0) <= ( wire_receive_pma0_signaldetect);
tx_analogreset_out <= ( wire_cent_unit0_txanalogresetout(3 DOWNTO 0));
tx_clkout(0) <= ( tx_core_clkout_wire(0));
tx_clkout_int_wire(0) <= ( wire_transmit_pcs0_clkout);
tx_core_clkout_wire(0) <= ( tx_clkout_int_wire(0));
tx_datain_wire <= ( tx_datain(7 DOWNTO 0));
tx_dataout(0) <= ( txdataout(0));
tx_dataout_pcs_to_pma <= ( wire_transmit_pcs0_dataout(9 DOWNTO 0));
tx_diagnosticlpbkin(0) <= ( wire_receive_pma0_diagnosticlpbkout);
tx_digitalreset_in <= ( "000" & tx_digitalreset(0));
tx_digitalreset_out <= ( wire_cent_unit0_txdigitalresetout(3 DOWNTO 0));
tx_dprioin_wire <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & cent_unit_txdprioout(149 DOWNTO 0));
tx_invpolarity <= (OTHERS => '0');
tx_localrefclk(0) <= ( wire_transmit_pma0_clockout);
tx_pcs_forceelecidleout(0) <= ( wire_transmit_pcs0_forceelecidleout);
tx_phfiforeset <= (OTHERS => '0');
tx_pipepowerdownout <= ( wire_transmit_pcs0_pipepowerdownout);
tx_pipepowerstateout <= ( wire_transmit_pcs0_pipepowerstateout);
tx_pma_fastrefclk0in(0) <= ( wire_pll0_clk(0));
tx_pma_refclk0in(0) <= ( wire_pll0_clk(1));
tx_pma_refclk0inpulse(0) <= ( wire_pll0_clk(2));
tx_pmadprioin_wire <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & cent_unit_txpmadprioout(299 DOWNTO 0));
tx_pmadprioout <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_transmit_pma0_dprioout);
tx_revparallellpbken <= (OTHERS => '0');
tx_rxdetectvalidout(0) <= ( wire_transmit_pma0_rxdetectvalidout);
tx_rxfoundout(0) <= ( wire_transmit_pma0_rxfoundout);
tx_serialloopbackout(0) <= ( wire_transmit_pma0_seriallpbkout);
tx_txdprioout <= ( "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" & wire_transmit_pcs0_dprioout);
txdataout(0) <= ( wire_transmit_pma0_dataout);
txdetectrxout(0) <= ( wire_transmit_pcs0_txdetectrx);
w_cent_unit_dpriodisableout1w(0) <= ( wire_cent_unit0_dpriodisableout);
wire_w_fixedclk_fast_range38w(0) <= fixedclk_fast(0);
wire_w_fixedclk_fast_range45w(0) <= fixedclk_fast(1);
wire_w_fixedclk_fast_range50w(0) <= fixedclk_fast(2);
wire_w_fixedclk_fast_range55w(0) <= fixedclk_fast(3);
wire_w_rx_analogreset_range266w(0) <= rx_analogreset(0);
wire_pll0_areset <= wire_w_lg_w_pll_areset_range32w33w(0);
wire_w_lg_w_pll_areset_range32w33w(0) <= pll_areset(0) OR pll_powerdown(0);
wire_pll0_inclk <= ( "0" & pll_inclk(0));
pll0 : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_multiply_by => 25,
clk1_divide_by => 10,
clk1_multiply_by => 25,
clk2_divide_by => 10,
clk2_duty_cycle => 20,
clk2_multiply_by => 25,
DPA_DIVIDE_BY => 2,
DPA_MULTIPLY_BY => 25,
inclk0_input_frequency => 10000,
operation_mode => "no_compensation",
INTENDED_DEVICE_FAMILY => "Cyclone IV GX"
)
PORT MAP (
areset => wire_pll0_areset,
clk => wire_pll0_clk,
fref => wire_pll0_fref,
icdrclk => wire_pll0_icdrclk,
inclk => wire_pll0_inclk,
locked => wire_pll0_locked
);
cal_blk0 : cycloneiv_hssi_calibration_block
PORT MAP (
clk => cal_blk_clk,
nonusertocmu => wire_cal_blk0_nonusertocmu,
powerdn => cal_blk_powerdown
);
wire_cent_unit0_adet <= (OTHERS => '0');
wire_cent_unit0_fixedclk <= ( "000" & fixedclk_to_cmu(0));
wire_cent_unit0_rdalign <= (OTHERS => '0');
wire_cent_unit0_rxanalogreset <= ( rx_analogreset_in(3 DOWNTO 0));
wire_cent_unit0_rxctrl <= (OTHERS => '0');
wire_cent_unit0_rxdatain <= (OTHERS => '0');
wire_cent_unit0_rxdatavalid <= (OTHERS => '0');
wire_cent_unit0_rxdigitalreset <= ( rx_digitalreset_in(3 DOWNTO 0));
wire_cent_unit0_rxpcsdprioin <= ( cent_unit_rxpcsdprioin(1599 DOWNTO 0));
wire_cent_unit0_rxpmadprioin <= ( cent_unit_rxpmadprioin(1199 DOWNTO 0));
wire_cent_unit0_rxpowerdown <= ( rx_powerdown_in(3 DOWNTO 0));
wire_cent_unit0_rxrunningdisp <= (OTHERS => '0');
wire_cent_unit0_syncstatus <= (OTHERS => '0');
wire_cent_unit0_txctrl <= (OTHERS => '0');
wire_cent_unit0_txdatain <= (OTHERS => '0');
wire_cent_unit0_txdigitalreset <= ( tx_digitalreset_in(3 DOWNTO 0));
wire_cent_unit0_txpcsdprioin <= ( cent_unit_tx_dprioin(599 DOWNTO 0));
wire_cent_unit0_txpmadprioin <= ( cent_unit_txpmadprioin(1199 DOWNTO 0));
cent_unit0 : cycloneiv_hssi_cmu
GENERIC MAP (
auto_spd_deassert_ph_fifo_rst_count => 8,
auto_spd_phystatus_notify_count => 14,
devaddr => ((((starting_channel_number / 4) + 0) MOD 32) + 1),
dprio_config_mode => "000001",
in_xaui_mode => "false",
portaddr => (((starting_channel_number + 0) / 128) + 1),
rx0_channel_bonding => "none",
rx0_clk1_mux_select => "recovered clock",
rx0_clk2_mux_select => "local reference clock",
rx0_ph_fifo_reg_mode => "true",
rx0_rd_clk_mux_select => "int clock",
rx0_recovered_clk_mux_select => "recovered clock",
rx0_reset_clock_output_during_digital_reset => "false",
rx0_use_double_data_mode => "false",
tx0_channel_bonding => "none",
tx0_rd_clk_mux_select => "central",
tx0_reset_clock_output_during_digital_reset => "false",
tx0_use_double_data_mode => "false",
tx0_wr_clk_mux_select => "int_clk",
use_coreclk_out_post_divider => "false",
use_deskew_fifo => "false"
)
PORT MAP (
adet => wire_cent_unit0_adet,
dpclk => reconfig_clk,
dpriodisable => reconfig_togxb_disable(0),
dpriodisableout => wire_cent_unit0_dpriodisableout,
dprioin => reconfig_togxb_in(0),
dprioload => reconfig_togxb_load(0),
dprioout => wire_cent_unit0_dprioout,
fixedclk => wire_cent_unit0_fixedclk,
nonuserfromcal => nonusertocmu_out(0),
quadreset => gxb_powerdown(0),
quadresetout => wire_cent_unit0_quadresetout,
rdalign => wire_cent_unit0_rdalign,
rdenablesync => wire_gnd,
recovclk => wire_gnd,
rxanalogreset => wire_cent_unit0_rxanalogreset,
rxanalogresetout => wire_cent_unit0_rxanalogresetout,
rxcrupowerdown => wire_cent_unit0_rxcrupowerdown,
rxctrl => wire_cent_unit0_rxctrl,
rxdatain => wire_cent_unit0_rxdatain,
rxdatavalid => wire_cent_unit0_rxdatavalid,
rxdigitalreset => wire_cent_unit0_rxdigitalreset,
rxdigitalresetout => wire_cent_unit0_rxdigitalresetout,
rxibpowerdown => wire_cent_unit0_rxibpowerdown,
rxpcsdprioin => wire_cent_unit0_rxpcsdprioin,
rxpcsdprioout => wire_cent_unit0_rxpcsdprioout,
rxpmadprioin => wire_cent_unit0_rxpmadprioin,
rxpmadprioout => wire_cent_unit0_rxpmadprioout,
rxpowerdown => wire_cent_unit0_rxpowerdown,
rxrunningdisp => wire_cent_unit0_rxrunningdisp,
syncstatus => wire_cent_unit0_syncstatus,
txanalogresetout => wire_cent_unit0_txanalogresetout,
txctrl => wire_cent_unit0_txctrl,
txdatain => wire_cent_unit0_txdatain,
txdetectrxpowerdown => wire_cent_unit0_txdetectrxpowerdown,
txdigitalreset => wire_cent_unit0_txdigitalreset,
txdigitalresetout => wire_cent_unit0_txdigitalresetout,
txdividerpowerdown => wire_cent_unit0_txdividerpowerdown,
txobpowerdown => wire_cent_unit0_txobpowerdown,
txpcsdprioin => wire_cent_unit0_txpcsdprioin,
txpcsdprioout => wire_cent_unit0_txpcsdprioout,
txpmadprioin => wire_cent_unit0_txpmadprioin,
txpmadprioout => wire_cent_unit0_txpmadprioout
);
wire_receive_pcs0_hipelecidleinfersel <= (OTHERS => '0');
wire_receive_pcs0_parallelfdbk <= (OTHERS => '0');
wire_receive_pcs0_xgmdatain <= (OTHERS => '0');
receive_pcs0 : cycloneiv_hssi_rx_pcs
GENERIC MAP (
align_pattern => "0101111100",
align_pattern_length => 10,
allow_align_polarity_inversion => "false",
allow_pipe_polarity_inversion => "true",
auto_spd_deassert_ph_fifo_rst_count => 8,
auto_spd_phystatus_notify_count => 14,
bit_slip_enable => "false",
byte_order_invalid_code_or_run_disp_error => "true",
byte_order_mode => "none",
byte_order_pad_pattern => "0",
byte_order_pattern => "0",
byte_order_pld_ctrl_enable => "false",
cdrctrl_bypass_ppm_detector_cycle => 1000,
cdrctrl_cid_mode_enable => "true",
cdrctrl_enable => "true",
cdrctrl_mask_cycle => 800,
cdrctrl_min_lock_to_ref_cycle => 63,
cdrctrl_rxvalid_mask => "true",
channel_bonding => "none",
channel_number => ((starting_channel_number + 0) MOD 4),
channel_width => 8,
clk1_mux_select => "recovered clock",
clk2_mux_select => "local reference clock",
core_clock_0ppm => "false",
datapath_low_latency_mode => "false",
datapath_protocol => "pipe",
dec_8b_10b_compatibility_mode => "true",
dec_8b_10b_mode => "normal",
deskew_pattern => "0",
disable_auto_idle_insertion => "false",
disable_running_disp_in_word_align => "false",
disallow_kchar_after_pattern_ordered_set => "false",
dprio_config_mode => "000001",
elec_idle_gen1_sigdet_enable => "true",
elec_idle_infer_enable => "false",
elec_idle_num_com_detect => 3,
enable_bit_reversal => "false",
enable_self_test_mode => "false",
force_signal_detect_dig => "true",
hip_enable => "true",
infiniband_invalid_code => 0,
insert_pad_on_underflow => "false",
num_align_code_groups_in_ordered_set => 0,
num_align_cons_good_data => 16,
num_align_cons_pat => 4,
num_align_loss_sync_error => 17,
ph_fifo_low_latency_enable => "true",
ph_fifo_reg_mode => "true",
protocol_hint => "pcie",
rate_match_back_to_back => "false",
rate_match_delete_threshold => 13,
rate_match_empty_threshold => 5,
rate_match_fifo_mode => "true",
rate_match_full_threshold => 20,
rate_match_insert_threshold => 11,
rate_match_ordered_set_based => "false",
rate_match_pattern1 => "11010000111010000011",
rate_match_pattern2 => "00101111000101111100",
rate_match_pattern_size => 20,
rate_match_pipe_enable => "true",
rate_match_reset_enable => "false",
rate_match_skip_set_based => "true",
rate_match_start_threshold => 7,
rd_clk_mux_select => "int clock",
recovered_clk_mux_select => "recovered clock",
run_length => 40,
run_length_enable => "true",
rx_detect_bypass => "false",
rx_phfifo_wait_cnt => 32,
rxstatus_error_report_mode => 1,
self_test_mode => "incremental",
use_alignment_state_machine => "true",
use_deskew_fifo => "false",
use_double_data_mode => "false",
use_parallel_loopback => "false"
)
PORT MAP (
a1a2size => wire_gnd,
alignstatus => wire_gnd,
alignstatussync => wire_gnd,
cdrctrlearlyeios => wire_receive_pcs0_cdrctrlearlyeios,
cdrctrllocktorefclkout => wire_receive_pcs0_cdrctrllocktorefclkout,
datain => rx_pma_recoverdataout_wire(9 DOWNTO 0),
digitalreset => rx_digitalreset_out(0),
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => rx_pcsdprioin_wire(399 DOWNTO 0),
dprioout => wire_receive_pcs0_dprioout,
enabledeskew => wire_gnd,
enabyteord => wire_gnd,
enapatternalign => rx_enapatternalign(0),
fifordin => wire_gnd,
fiforesetrd => wire_gnd,
hip8b10binvpolarity => pipe8b10binvpolarity(0),
hipdataout => wire_receive_pcs0_hipdataout,
hipdatavalid => wire_receive_pcs0_hipdatavalid,
hipelecidle => wire_receive_pcs0_hipelecidle,
hipelecidleinfersel => wire_receive_pcs0_hipelecidleinfersel,
hipphydonestatus => wire_receive_pcs0_hipphydonestatus,
hippowerdown => powerdn(1 DOWNTO 0),
hipstatus => wire_receive_pcs0_hipstatus,
invpol => wire_gnd,
localrefclk => tx_localrefclk(0),
masterclk => wire_gnd,
parallelfdbk => wire_receive_pcs0_parallelfdbk,
phfifordenable => rx_phfifordenable(0),
phfiforeset => rx_phfiforeset(0),
phfifowrdisable => rx_phfifowrdisable(0),
pipeenrevparallellpbkfromtx => int_pipeenrevparallellpbkfromtx(0),
pipepowerdown => tx_pipepowerdownout(1 DOWNTO 0),
pipepowerstate => tx_pipepowerstateout(3 DOWNTO 0),
prbscidenable => rx_prbscidenable(0),
quadreset => cent_unit_quadresetout(0),
recoveredclk => rx_pma_clockout(0),
refclk => refclk_pma(0),
revbitorderwa => wire_gnd,
revparallelfdbkdata => wire_receive_pcs0_revparallelfdbkdata,
rmfifordena => wire_gnd,
rmfiforeset => rx_rmfiforeset(0),
rmfifowrena => wire_gnd,
rxdetectvalid => tx_rxdetectvalidout(0),
rxfound => rx_pcs_rxfound_wire(1 DOWNTO 0),
signaldetected => rx_signaldetect_wire(0),
xgmctrlin => wire_gnd,
xgmdatain => wire_receive_pcs0_xgmdatain
);
wire_receive_pma0_w_lg_freqlocked337w(0) <= wire_receive_pma0_freqlocked AND wire_w_lg_w_rx_analogreset_range266w336w(0);
wire_receive_pma0_locktodata <= wire_w_lg_w_lg_reconfig_togxb_busy267w326w(0);
wire_w_lg_w_lg_reconfig_togxb_busy267w326w(0) <= wire_w_lg_reconfig_togxb_busy267w(0) AND rx_locktodata(0);
wire_receive_pma0_testbussel <= "0110";
receive_pma0 : cycloneiv_hssi_rx_pma
GENERIC MAP (
allow_serial_loopback => "false",
channel_number => ((starting_channel_number + 0) MOD 4),
common_mode => "0.82V",
deserialization_factor => 10,
dprio_config_mode => "000001",
effective_data_rate => "2500 Mbps",
enable_local_divider => "false",
enable_ltd => "false",
enable_ltr => "false",
enable_second_order_loop => "false",
eq_dc_gain => 3,
eq_setting => 1,
force_signal_detect => "false",
logical_channel_address => (starting_channel_number + 0),
loop_1_digital_filter => 8,
offset_cancellation => 1,
ppm_gen1_2_xcnt_en => 1,
ppm_post_eidle => 0,
ppmselect => 8,
protocol_hint => "pcie",
signal_detect_hysteresis => 4,
signal_detect_hysteresis_valid_threshold => 14,
signal_detect_loss_threshold => 3,
termination => "OCT 100 Ohms",
use_external_termination => "false"
)
PORT MAP (
analogtestbus => wire_receive_pma0_analogtestbus,
clockout => wire_receive_pma0_clockout,
crupowerdn => cent_unit_rxcrupowerdn(0),
datain => rx_datain(0),
deserclock => rx_deserclock_in(0),
diagnosticlpbkout => wire_receive_pma0_diagnosticlpbkout,
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => rx_pmadprioin_wire(299 DOWNTO 0),
dprioout => wire_receive_pma0_dprioout,
freqlocked => wire_receive_pma0_freqlocked,
locktodata => wire_receive_pma0_locktodata,
locktoref => rx_locktorefclk_wire(0),
locktorefout => wire_receive_pma0_locktorefout,
powerdn => cent_unit_rxibpowerdn(0),
ppmdetectrefclk => rx_pll_pfdrefclkout_wire(0),
recoverdataout => wire_receive_pma0_recoverdataout,
reverselpbkout => wire_receive_pma0_reverselpbkout,
rxpmareset => rx_analogreset_out(0),
seriallpbkin => tx_serialloopbackout(0),
signaldetect => wire_receive_pma0_signaldetect,
testbussel => wire_receive_pma0_testbussel
);
wire_transmit_pcs0_ctrlenable <= ( "0" & "0");
wire_transmit_pcs0_datainfull <= (OTHERS => '0');
wire_transmit_pcs0_dispval <= ( "0" & "0");
wire_transmit_pcs0_forcedisp <= ( "0" & "0");
wire_transmit_pcs0_hipdatain <= ( tx_forcedispcompliance(0) & tx_ctrlenable(0) & tx_datain_wire(7 DOWNTO 0));
transmit_pcs0 : cycloneiv_hssi_tx_pcs
GENERIC MAP (
allow_polarity_inversion => "false",
bitslip_enable => "false",
channel_bonding => "none",
channel_number => ((starting_channel_number + 0) MOD 4),
channel_width => 8,
core_clock_0ppm => "false",
datapath_low_latency_mode => "false",
datapath_protocol => "pipe",
disable_ph_low_latency_mode => "false",
disparity_mode => "new",
dprio_config_mode => "000001",
elec_idle_delay => 4,
enable_bit_reversal => "false",
enable_idle_selection => "false",
enable_reverse_parallel_loopback => "true",
enable_self_test_mode => "false",
enc_8b_10b_compatibility_mode => "true",
enc_8b_10b_mode => "normal",
hip_enable => "true",
ph_fifo_reg_mode => "true",
prbs_cid_pattern => "false",
protocol_hint => "pcie",
refclk_select => "local",
self_test_mode => "incremental",
use_double_data_mode => "false",
wr_clk_mux_select => "int_clk"
)
PORT MAP (
clkout => wire_transmit_pcs0_clkout,
ctrlenable => wire_transmit_pcs0_ctrlenable,
datainfull => wire_transmit_pcs0_datainfull,
dataout => wire_transmit_pcs0_dataout,
digitalreset => tx_digitalreset_out(0),
dispval => wire_transmit_pcs0_dispval,
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => tx_dprioin_wire(149 DOWNTO 0),
dprioout => wire_transmit_pcs0_dprioout,
enrevparallellpbk => tx_revparallellpbken(0),
forcedisp => wire_transmit_pcs0_forcedisp,
forceelecidleout => wire_transmit_pcs0_forceelecidleout,
grayelecidleinferselout => wire_transmit_pcs0_grayelecidleinferselout,
hipdatain => wire_transmit_pcs0_hipdatain,
hipdetectrxloop => tx_detectrxloop(0),
hipelecidleinfersel => rx_elecidleinfersel(2 DOWNTO 0),
hipforceelecidle => tx_forceelecidle(0),
hippowerdn => powerdn(1 DOWNTO 0),
hiptxclkout => wire_transmit_pcs0_hiptxclkout,
invpol => tx_invpolarity(0),
localrefclk => tx_localrefclk(0),
phfiforddisable => wire_gnd,
phfiforeset => tx_phfiforeset(0),
phfifowrenable => wire_vcc,
pipeenrevparallellpbkout => wire_transmit_pcs0_pipeenrevparallellpbkout,
pipepowerdownout => wire_transmit_pcs0_pipepowerdownout,
pipepowerstateout => wire_transmit_pcs0_pipepowerstateout,
pipestatetransdone => wire_gnd,
quadreset => cent_unit_quadresetout(0),
refclk => refclk_pma(0),
revparallelfdbk => rx_revparallelfdbkdata(19 DOWNTO 0),
txdetectrx => wire_transmit_pcs0_txdetectrx
);
wire_transmit_pma0_datain <= ( tx_dataout_pcs_to_pma(9 DOWNTO 0));
transmit_pma0 : cycloneiv_hssi_tx_pma
GENERIC MAP (
channel_number => ((starting_channel_number + 0) MOD 4),
common_mode => "0.65V",
dprio_config_mode => "000001",
effective_data_rate => "2500 Mbps",
enable_diagnostic_loopback => "false",
enable_reverse_serial_loopback => "false",
logical_channel_address => (starting_channel_number + 0),
preemp_tap_1 => 1,
protocol_hint => "pcie",
rx_detect => 0,
serialization_factor => 10,
slew_rate => "low",
termination => "OCT 100 Ohms",
use_external_termination => "false",
use_rx_detect => "true",
vod_selection => 4
)
PORT MAP (
cgbpowerdn => cent_unit_txdividerpowerdown(0),
clockout => wire_transmit_pma0_clockout,
datain => wire_transmit_pma0_datain,
dataout => wire_transmit_pma0_dataout,
detectrxpowerdown => cent_unit_txdetectrxpowerdn(0),
diagnosticlpbkin => tx_diagnosticlpbkin(0),
dpriodisable => w_cent_unit_dpriodisableout1w(0),
dprioin => tx_pmadprioin_wire(299 DOWNTO 0),
dprioout => wire_transmit_pma0_dprioout,
fastrefclk0in => tx_pma_fastrefclk0in(0),
forceelecidle => tx_pcs_forceelecidleout(0),
powerdn => cent_unit_txobpowerdn(0),
refclk0in => tx_pma_refclk0in(0),
refclk0inpulse => tx_pma_refclk0inpulse(0),
reverselpbkin => rx_reverselpbkout(0),
rxdetecten => txdetectrxout(0),
rxdetectvalidout => wire_transmit_pma0_rxdetectvalidout,
rxfoundout => wire_transmit_pma0_rxfoundout,
seriallpbkout => wire_transmit_pma0_seriallpbkout,
txpmareset => tx_analogreset_out(0)
);
PROCESS (fixedclk)
BEGIN
IF (fixedclk = '1' AND fixedclk'event) THEN fixedclk_div <= (NOT fixedclk_div_in);
END IF;
END PROCESS;
PROCESS (fixedclk)
BEGIN
IF (fixedclk = '0' AND fixedclk'event) THEN reconfig_togxb_busy_reg <= ( reconfig_togxb_busy_reg(0) & reconfig_togxb_busy);
END IF;
END PROCESS;
END RTL; --pcie_compiler_0_serdes_alt_c3gxb_euf8
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pcie_compiler_0_serdes IS
GENERIC
(
starting_channel_number : NATURAL := 0
);
PORT
(
cal_blk_clk : IN STD_LOGIC ;
fixedclk : IN STD_LOGIC ;
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END pcie_compiler_0_serdes;
ARCHITECTURE RTL OF pcie_compiler_0_serdes IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt_c3gxb";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "effective_data_rate=2500 Mbps;enable_lc_tx_pll=false;enable_pll_inclk_alt_drive_rx_cru=true;enable_pll_inclk_drive_rx_cru=true;equalizer_dcgain_setting=1;gen_reconfig_pll=false;gx_channel_type=;input_clock_frequency=100.0 MHz;intended_device_family=Cyclone IV GX;intended_device_speed_grade=6;intended_device_variant=ANY;loopback_mode=none;lpm_type=alt_c3gxb;number_of_channels=1;operation_mode=duplex;pll_bandwidth_type=Auto;pll_control_width=1;pll_inclk_period=10000;pll_pfd_fb_mode=internal;preemphasis_ctrl_1stposttap_setting=1;protocol=pcie;receiver_termination=oct_100_ohms;reconfig_dprio_mode=0;rx_8b_10b_mode=normal;rx_align_pattern=0101111100;rx_align_pattern_length=10;rx_allow_align_polarity_inversion=false;rx_allow_pipe_polarity_inversion=true;rx_bitslip_enable=false;rx_byte_ordering_mode=NONE;rx_channel_bonding=indv;rx_channel_width=8;rx_common_mode=0.82v;rx_cru_inclock0_period=10000;rx_datapath_protocol=pipe;rx_data_rate=2500;rx_data_rate_remainder=0;rx_digitalreset_port_width=1;rx_enable_bit_reversal=false;rx_enable_lock_to_data_sig=false;rx_enable_lock_to_refclk_sig=false;rx_enable_self_test_mode=false;rx_force_signal_detect=false;rx_ppmselect=8;rx_rate_match_fifo_mode=normal;rx_rate_match_pattern1=11010000111010000011;rx_rate_match_pattern2=00101111000101111100;rx_rate_match_pattern_size=20;rx_run_length=40;rx_run_length_enable=true;rx_signal_detect_threshold=4;rx_use_align_state_machine=true;rx_use_clkout=false;rx_use_coreclk=false;" &
"rx_use_deserializer_double_data_mode=false;rx_use_deskew_fifo=false;rx_use_double_data_mode=false;rx_use_pipe8b10binvpolarity=true;rx_use_rate_match_pattern1_only=false;transmitter_termination=oct_100_ohms;tx_8b_10b_mode=normal;tx_allow_polarity_inversion=false;tx_channel_bonding=indv;tx_channel_width=8;tx_clkout_width=1;tx_common_mode=0.65v;tx_data_rate=2500;tx_data_rate_remainder=0;tx_digitalreset_port_width=1;tx_enable_bit_reversal=false;tx_enable_self_test_mode=false;tx_pll_bandwidth_type=Auto;tx_pll_inclk0_period=10000;tx_pll_type=CMU;tx_slew_rate=low;tx_transmit_protocol=pipe;tx_use_coreclk=false;tx_use_double_data_mode=false;tx_use_serializer_double_data_mode=false;use_calibration_block=true;vod_ctrl_setting=4;elec_idle_infer_enable=false;enable_0ppm=false;equalization_setting=1;gxb_powerdown_width=1;hip_enable=true;iqtxrxclk_allowed=;number_of_quads=1;pll_divide_by=2;pll_multiply_by=25;reconfig_calibration=true;reconfig_fromgxb_port_width=5;reconfig_pll_control_width=1;reconfig_togxb_port_width=4;rx_cdrctrl_enable=true;rx_deskew_pattern=0;rx_dwidth_factor=1;rx_enable_second_order_loop=false;rx_loop_1_digital_filter=8;rx_signal_detect_loss_threshold=3;rx_signal_detect_valid_threshold=14;rx_use_external_termination=false;rx_word_aligner_num_byte=1;top_module_name=pcie_compiler_0_serdes;tx_bitslip_enable=FALSE;tx_dwidth_factor=1;tx_use_external_termination=false;";
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT pcie_compiler_0_serdes_alt_c3gxb_euf8
GENERIC (
starting_channel_number : NATURAL
);
PORT (
reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rx_patterndetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
cal_blk_clk : IN STD_LOGIC ;
pipephydonestatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_locked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_fromgxb : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
rx_freqlocked : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forceelecidle : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
fixedclk : IN STD_LOGIC ;
pipestatus : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
rx_datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_syncstatus : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_areset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
pipe8b10binvpolarity : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_datain : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
tx_digitalreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
gxb_powerdown : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
hip_tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pipeelecidle : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_clkout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_forcedispcompliance : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
reconfig_clk : IN STD_LOGIC ;
rx_analogreset : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
powerdn : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
rx_ctrldetect : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
tx_ctrlenable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
pll_inclk : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rx_elecidleinfersel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
tx_detectrxloop : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
rx_patterndetect <= sub_wire0(0 DOWNTO 0);
pipephydonestatus <= sub_wire1(0 DOWNTO 0);
pll_locked <= sub_wire2(0 DOWNTO 0);
reconfig_fromgxb <= sub_wire3(4 DOWNTO 0);
rx_freqlocked <= sub_wire4(0 DOWNTO 0);
pipestatus <= sub_wire5(2 DOWNTO 0);
rx_syncstatus <= sub_wire6(0 DOWNTO 0);
rx_dataout <= sub_wire7(7 DOWNTO 0);
hip_tx_clkout <= sub_wire8(0 DOWNTO 0);
pipeelecidle <= sub_wire9(0 DOWNTO 0);
tx_clkout <= sub_wire10(0 DOWNTO 0);
tx_dataout <= sub_wire11(0 DOWNTO 0);
rx_ctrldetect <= sub_wire12(0 DOWNTO 0);
pipedatavalid <= sub_wire13(0 DOWNTO 0);
pcie_compiler_0_serdes_alt_c3gxb_euf8_component : pcie_compiler_0_serdes_alt_c3gxb_euf8
GENERIC MAP (
starting_channel_number => starting_channel_number
)
PORT MAP (
reconfig_togxb => reconfig_togxb,
cal_blk_clk => cal_blk_clk,
tx_forceelecidle => tx_forceelecidle,
fixedclk => fixedclk,
rx_datain => rx_datain,
rx_digitalreset => rx_digitalreset,
pll_areset => pll_areset,
pipe8b10binvpolarity => pipe8b10binvpolarity,
tx_datain => tx_datain,
tx_digitalreset => tx_digitalreset,
gxb_powerdown => gxb_powerdown,
tx_forcedispcompliance => tx_forcedispcompliance,
reconfig_clk => reconfig_clk,
rx_analogreset => rx_analogreset,
powerdn => powerdn,
tx_ctrlenable => tx_ctrlenable,
pll_inclk => pll_inclk,
rx_elecidleinfersel => rx_elecidleinfersel,
tx_detectrxloop => tx_detectrxloop,
rx_patterndetect => sub_wire0,
pipephydonestatus => sub_wire1,
pll_locked => sub_wire2,
reconfig_fromgxb => sub_wire3,
rx_freqlocked => sub_wire4,
pipestatus => sub_wire5,
rx_syncstatus => sub_wire6,
rx_dataout => sub_wire7,
hip_tx_clkout => sub_wire8,
pipeelecidle => sub_wire9,
tx_clkout => sub_wire10,
tx_dataout => sub_wire11,
rx_ctrldetect => sub_wire12,
pipedatavalid => sub_wire13
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: IP_MODE STRING "PCIE_HIP_8"
-- Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE"
-- Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
-- Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
-- Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
-- Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500"
-- Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
-- Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100.0"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
-- Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
-- Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "1"
-- Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "5"
-- Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100.0"
-- Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100.0 125.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
-- Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
-- Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100.0"
-- Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
-- Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
-- Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
-- Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
-- Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
-- Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
-- Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
-- Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
-- Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
-- Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
-- Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
-- Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
-- Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100.0 MHz"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
-- Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
-- Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
-- Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "10000"
-- Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
-- Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "1"
-- Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
-- Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
-- Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
-- Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
-- Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
-- Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
-- Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
-- Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
-- Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
-- Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
-- Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
-- Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
-- Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
-- Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
-- Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
-- Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
-- Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "false"
-- Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
-- Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
-- Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
-- Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
-- Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "4"
-- Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
-- Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
-- Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
-- Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
-- Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
-- Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
-- Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
-- Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
-- Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
-- Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
-- Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
-- Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
-- Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
-- Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
-- Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
-- Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
-- Retrieval info: CONSTANT: TX_SLEW_RATE STRING "low"
-- Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
-- Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
-- Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
-- Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
-- Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
-- Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
-- Retrieval info: CONSTANT: enable_0ppm STRING "false"
-- Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
-- Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
-- Retrieval info: CONSTANT: hip_enable STRING "true"
-- Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
-- Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
-- Retrieval info: CONSTANT: pll_divide_by STRING "2"
-- Retrieval info: CONSTANT: pll_multiply_by STRING "25"
-- Retrieval info: CONSTANT: reconfig_calibration STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
-- Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
-- Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
-- Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
-- Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
-- Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
-- Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
-- Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
-- Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "3"
-- Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
-- Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
-- Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
-- Retrieval info: CONSTANT: top_module_name STRING "pcie_compiler_0_serdes"
-- Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
-- Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
-- Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
-- Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
-- Retrieval info: USED_PORT: fixedclk 0 0 0 0 INPUT NODEFVAL "fixedclk"
-- Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
-- Retrieval info: USED_PORT: hip_tx_clkout 0 0 1 0 OUTPUT NODEFVAL "hip_tx_clkout[0..0]"
-- Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
-- Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
-- Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
-- Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
-- Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
-- Retrieval info: USED_PORT: pll_areset 0 0 1 0 INPUT NODEFVAL "pll_areset[0..0]"
-- Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
-- Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
-- Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
-- Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
-- Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
-- Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
-- Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
-- Retrieval info: USED_PORT: rx_elecidleinfersel 0 0 3 0 INPUT NODEFVAL "rx_elecidleinfersel[2..0]"
-- Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
-- Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
-- Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
-- Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
-- Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
-- Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
-- Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
-- Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
-- Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
-- Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
-- Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
-- Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
-- Retrieval info: CONNECT: @fixedclk 0 0 0 0 fixedclk 0 0 0 0
-- Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
-- Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
-- Retrieval info: CONNECT: @pll_areset 0 0 1 0 pll_areset 0 0 1 0
-- Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
-- Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
-- Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
-- Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
-- Retrieval info: CONNECT: @rx_elecidleinfersel 0 0 3 0 rx_elecidleinfersel 0 0 3 0
-- Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
-- Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
-- Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
-- Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
-- Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
-- Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
-- Retrieval info: CONNECT: hip_tx_clkout 0 0 1 0 @hip_tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
-- Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
-- Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
-- Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
-- Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
-- Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
-- Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
-- Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
-- Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
-- Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
-- Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
-- Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
-- Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pcie_compiler_0_serdes_inst.vhd FALSE
|
gpl-3.0
|
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/tb_7seg.vhd
|
2
|
1513
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_7seg IS
END tb_7seg;
ARCHITECTURE behavior OF tb_7seg IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT seven_seg
PORT(
display1 : IN std_logic_vector(3 downto 0);
display2 : IN std_logic_vector(3 downto 0);
display3 : IN std_logic_vector(3 downto 0);
display4 : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
anodes : INOUT std_logic_vector(4 downto 0);
sevenseg : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--BiDirs
signal anodes : std_logic_vector(4 downto 0);
--Outputs
signal sevenseg : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: seven_seg PORT MAP (
display1 => x"1",
display2 => x"2",
display3 => x"3",
display4 => x"4",
clk => clk,
anodes => anodes,
sevenseg => sevenseg
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
arthurbenemann/fpga-bits
|
undocumented/serial_out/tb_top.vhd
|
1
|
5183
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:59:29 02/23/2016
-- Design Name:
-- Module Name: C:/Users/Arthur/Documents/FPGA_temp/serial_out/tb_top.vhd
-- Project Name: serial_out
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: topModule
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT topModule
PORT(
CLK : IN std_logic;
GPIO0 : OUT std_logic;
GPIO1 : OUT std_logic;
RX : IN std_logic;
TX : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RX : std_logic := '1';
--Outputs
signal GPIO0 : std_logic;
signal GPIO1 : std_logic;
signal TX : std_logic;
-- Clock period definitions
constant clk_period : time := 31.25 ns;
constant bit_period : time := 8.68 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: topModule PORT MAP (
CLK => CLK,
GPIO0 => GPIO0,
GPIO1 => GPIO1,
RX => RX,
TX => TX
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait for 10 us;
-- send '0000000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11111111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period*8;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '11110000'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '00001111'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 50 us;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '10101010'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
-- send '01010101'
rx <= '0'; -- start bit
wait for bit_period*1;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- data
wait for bit_period;
rx <= '0'; -- data
wait for bit_period;
rx <= '1'; -- stop bit
wait for bit_period*1;
wait for 200 us;
end process;
END;
|
gpl-3.0
|
aospan/NetUP_Dual_Universal_CI-fpga
|
dvb_ts.vhd
|
1
|
5434
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts is
port (
rst : in std_logic;
clk : in std_logic;
-- control
address : in std_logic_vector(8 downto 0);
byteenable : in std_logic_vector(3 downto 0);
writedata : in std_logic_vector(31 downto 0);
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
read : in std_logic;
waitrequest : out std_logic;
--
interrupt : out std_logic;
cam_bypass : in std_logic;
-- input port 1
dvb_in0_dsop : in std_logic;
dvb_in0_data : in std_logic_vector(7 downto 0);
dvb_in0_dval : in std_logic;
-- input port 2
dvb_in1_dsop : in std_logic;
dvb_in1_data : in std_logic_vector(7 downto 0);
dvb_in1_dval : in std_logic;
-- input port 3
dvb_in2_dsop : in std_logic;
dvb_in2_data : in std_logic_vector(7 downto 0);
dvb_in2_dval : in std_logic;
-- CAM port
cam_baseclk : in std_logic;
cam_mclki : out std_logic;
cam_mdi : out std_logic_vector(7 downto 0);
cam_mival : out std_logic;
cam_mistrt : out std_logic;
cam_mclko : in std_logic;
cam_mdo : in std_logic_vector(7 downto 0);
cam_moval : in std_logic;
cam_mostrt : in std_logic;
-- output port (DMA)
dvb_out_dsop : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic
);
end entity;
architecture rtl of dvb_ts is
constant REG_CLKDIV : natural := 0;
constant REG_SRCSEL : natural := 1;
signal clkdiv : std_logic_vector(3 downto 0);
signal srcsel : std_logic_vector(1 downto 0);
signal cam_dsop : std_logic;
signal cam_data : std_logic_vector(7 downto 0);
signal cam_dval : std_logic;
signal swts_dsop : std_logic;
signal swts_data : std_logic_vector(7 downto 0);
signal swts_dval : std_logic;
signal mux_dsop : std_logic;
signal mux_data : std_logic_vector(7 downto 0);
signal mux_dval : std_logic;
signal filter_dsop : std_logic;
signal filter_data : std_logic_vector(7 downto 0);
signal filter_dval : std_logic;
signal pid_tbl_read : std_logic;
signal pid_tbl_write : std_logic;
signal pid_tbl_rddata : std_logic_vector(31 downto 0);
signal pid_tbl_waitreq : std_logic;
begin
-- control
pid_tbl_write <= write and address(8);
pid_tbl_read <= read and address(8);
waitrequest <= pid_tbl_waitreq;
readdata <= pid_tbl_rddata when address(8) else
X"0000000" & clkdiv when not address(0) else
X"0000000" & "00" & srcsel;
interrupt <= '0';
process (rst, clk)
begin
if rising_edge(clk) then
if write and byteenable(0) then
if not address(0) and not address(8) then
clkdiv <= writedata(clkdiv'range);
end if;
if address(0) and not address(8) then
srcsel <= writedata(srcsel'range);
end if;
end if;
end if;
if rst then
clkdiv <= (others => '0');
srcsel <= (others => '0');
end if;
end process;
-- input demux
process (rst, clk)
begin
if rising_edge(clk) then
case srcsel is
when "00" =>
mux_dsop <= dvb_in0_dsop;
mux_data <= dvb_in0_data;
mux_dval <= dvb_in0_dval;
when "01" =>
mux_dsop <= dvb_in1_dsop;
mux_data <= dvb_in1_data;
mux_dval <= dvb_in1_dval;
when "10" =>
mux_dsop <= dvb_in2_dsop;
mux_data <= dvb_in2_data;
mux_dval <= dvb_in2_dval;
when others =>
mux_dsop <= swts_dsop;
mux_data <= swts_data;
mux_dval <= swts_dval;
end case;
end if;
if rst then
mux_dsop <= '0';
mux_data <= (others => '0');
mux_dval <= '0';
end if;
end process;
FILTER_0 : entity work.dvb_ts_filter
port map (
rst => rst,
clk => clk,
--
pid_tbl_addr => address(7 downto 0),
pid_tbl_be => byteenable,
pid_tbl_wrdata => writedata,
pid_tbl_write => pid_tbl_write,
pid_tbl_rddata => pid_tbl_rddata,
pid_tbl_read => pid_tbl_read,
pid_tbl_waitreq => pid_tbl_waitreq,
--
dvb_in_dsop => mux_dsop,
dvb_in_data => mux_data,
dvb_in_dval => mux_dval,
--
dvb_out_dsop => filter_dsop,
dvb_out_data => filter_data,
dvb_out_dval => filter_dval
);
CAM_OUT_0 : entity work.dvb_ts_shaper
port map (
rst => rst,
clk => clk,
--
bypass_test => cam_bypass,
--
clkdiv => X"2",
--
dvb_indrdy => open,
dvb_indata => filter_data,
dvb_indsop => filter_dsop,
dvb_indval => filter_dval,
-- stream domain
dvb_clk => cam_baseclk,
--
dvb_out_clk => cam_mclki,
dvb_out_data => cam_mdi,
dvb_out_dval => cam_mival,
dvb_out_dsop => cam_mistrt
);
CAM_IN_0 : entity work.dvb_ts_sync
port map (
ts_clk => cam_mclko,
ts_strt => cam_mostrt,
ts_dval => cam_moval,
ts_data => cam_mdo,
--
rst => rst,
clk => clk,
--
strt => cam_dsop,
data => cam_data,
dval => cam_dval
);
-- CAM bypass cotrol
process (rst, clk)
begin
if rising_edge(clk) then
if cam_bypass then
dvb_out_dsop <= filter_dsop;
dvb_out_data <= filter_data;
dvb_out_dval <= filter_dval;
else
dvb_out_dsop <= cam_dsop;
dvb_out_data <= cam_data;
dvb_out_dval <= cam_dval;
end if;
end if;
if rst then
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
dvb_out_dval <= '0';
end if;
end process;
end architecture;
|
gpl-3.0
|
jotego/jt12
|
doc/other/operator.vhd
|
2
|
17163
|
--------======== operator.vhd ========--------
-- YM2203 / YM2612 (OPN / OPN2) Operator Unit
-- Reverse engineered from YM2203 (and YM2612) die shots
-- Copyright (C) 2015 Sauraen
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- NOTICE:
-- This is an UNTESTED implementation!
--
-- I attempted to get the overall architecture of this unit correct,
-- especially the position and number of registers in the pipeline. I
-- am confident that this is correct at a large-scale level. I am not,
-- however, confident that this description is free from errors. In
-- particular, it is very likely that one or more bits are wrong in the
-- sine or exponential tables. Also, since the chip uses both positive
-- and negative logic throughout, it is easy to miss an inverter, and
-- so there may be an error where a particular signal or variable should
-- be inverted from how it is written here. I tried my best to trace
-- adders, etc. completely, but this is not error-proof.
--
-- The benefit of this situation is that if anyone does test an
-- implementation based on this code, the errors that may exist here are
-- likely to produce obviously wrong results. In previous implementations,
-- authors tried to get the right sound 99% of the time, but had no idea
-- of the pipelined architecture or certain other details here which became
-- important in the other cases. Thus it is much harder to make a perfect
-- implementation.
--------======== EXTERNALLY DEFINED ENTITIES ========--------
-- circular_buffer
-- A simple circular buffer, used for most of the YM2612's registers.
library ieee;
use ieee.std_logic_1164.all;
entity circular_buffer is
generic (
DATA_WIDTH: positive := 8; --arbitrary default value
BUFFER_DEPTH: positive := 3; --arbitrary default value
CLEAR_ON_RESET: boolean := false
);
port (
clk, rst_bar: in std_logic;
din: in std_logic_vector(DATA_WIDTH-1 downto 0);
dout: out std_logic_vector(DATA_WIDTH-1 downto 0);
load: in std_logic
);
end entity;
--------======== FILE BODY ========--------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity opn_operator is
generic (
NUM_VOICES : positive := 6
);
port (
-- Global control
clk, rst_bar: in std_logic;
-- Operator inputs, not all applying to the same operator at the same time
pg_phase: in unsigned(9 downto 0);
eg_atten: in unsigned(9 downto 0);
voice_fb: in unsigned(2 downto 0);
op_fb_enable: in std_logic;
op_algorithm_ctl: in std_logic_vector(5 downto 0);
test_214: in std_logic;
-- Operator output
op_result: out unsigned(13 downto 0)
);
end entity;
architecture arch of opn_operator is
type pipeline_delayer_t is array(natural range <>) of unsigned(9 downto 0);
signal prev1, prevprev1, prev2: unsigned(13 downto 0);
signal fm_preshift: unsigned(14 downto 0);
signal pipeline_delayer : pipeline_delayer_t(2*NUM_VOICES - 7 downto 0);
signal phaselo: unsigned(7 downto 0);
signal signbit, signbit_1, signbit_2: std_logic;
signal totalatten: unsigned(11 downto 0);
signal mantissa: unsigned(9 downto 0);
signal exponent: unsigned(3 downto 0);
signal op_result_pre: unsigned(13 downto 0);
signal op_result_internal: unsigned(13 downto 0);
begin
-- REGISTER/CYCLE 1
-- Creation of phase modulation (FM) feedback signal, before shifting
make_fm_preshift: process(clk) is
variable x, y: unsigned(13 downto 0);
variable xs, ys: unsigned(14 downto 0);
begin
if rising_edge(clk) then
x := (prevprev1 and op_algorithm_ctl(0))
or (prev2 and op_algorithm_ctl(1))
or (op_result_internal and op_algorithm_ctl(2));
y := (op_result_internal and op_algorithm_ctl(3))
or (prev1 and op_algorithm_ctl(4));
xs := x(13) & x(13 downto 0); -- sign-extend
ys := y(13) & y(13 downto 0); -- sign-extend
fm_preshift <= xs + ys; -- carry is discarded
end if;
end process;
-- REGISTER/CYCLE 2 (also YM2612 extra cycles 1-6)
-- Shifting of FM feedback signal, adding phase from PG to FM phase
-- In YM2203, fm_feedback is not registered at all, it is latched on the first edge
-- in add_pg_phase and the second edge is the output of add_pg_phase. In the YM2612, there
-- are 6 cycles worth of registers between the generated (non-registered) fm_feedback signal
-- and the input to add_pg_phase.
shift_fb_and_add_pg_phase: process(clk) is
variable fm_feedback: unsigned(9 downto 0);
variable fm_feedback_delayed: unsigned(9 downto 0);
variable phase: unsigned(9 downto 0);
begin
if rising_edge(clk) then
-- Shift FM feedback signal
if op_fb_enable = '1' then
fm_feedback := fm_preshift(10 downto 1); -- Bit 0 of fm_preshift is never used
else
case to_integer(voice_fb) is
when 1 => fm_feedback :=
(9 downto 6 => fm_preshift(14), 5 downto 0 => fm_preshift(14 downto 9));
when 2 => fm_feedback :=
(9 downto 7 => fm_preshift(14), 6 downto 0 => fm_preshift(14 downto 8));
when 3 => fm_feedback :=
(9 downto 8 => fm_preshift(14), 7 downto 0 => fm_preshift(14 downto 7));
when 4 => fm_feedback :=
(9 => fm_preshift(14), 8 downto 0 => fm_preshift(14 downto 6));
when 5 => fm_feedback := fm_preshift(14 downto 5);
when 6 => fm_feedback := fm_preshift(13 downto 4);
when 7 => fm_feedback := fm_preshift(12 downto 3);
when others => fm_feedback := (others => '0');
end case;
end if;
-- Delay pipeline by 6 cycles if this is a YM2612
if NUM_VOICES <= 3 then
fm_feedback_delayed := fm_feedback; -- Don't delay, don't register at all
else
pipeline_delayer((2*NUM_VOICES)-7) <= fm_feedback;
for i in (2*NUM_VOICES-8) downto 0 loop
pipeline_delayer(i) <= pipeline_delayer(i+1);
end loop;
fm_feedback_delayed := pipeline_delayer(0);
end if;
-- Add in PG phase
add_pg_phase:
phase := fm_feedback_delayed + pg_phase;
phaselo <= phase(7 downto 0) xor phase(8);
signbit <= phase(9);
end if;
end process;
-- REGISTER/CYCLE 3
-- Sine table
sine_table: process(clk) is
type sinetable_t is array(31 downto 0) of std_logic_vector(45 downto 0);
constant sinetable: sinetable_t := (
"0001100000100100010001000010101010101001010010",
"0001100000110100000100000010010001001101000001",
"0001100000110100000100110010001011001101100000",
"0001110000010000000000110010110001001101110010",
"0001110000010000001100000010111010001101101001",
"0001110000010100001001100010000000101101111010",
"0001110000010100001101100010010011001101011010",
"0001110000011100000101010010111000101111111100",
"0001110000111000000001110010101110001101110111",
"0001110000111000010100111000011101011010100110",
"0001110000111100011000011000111100001001111010",
"0001110000111100011100111001101011001001110111",
"0100100001010000010001011001001000111010110111",
"0100100001010100010001001001110001111100101010",
"0100100001010100010101101101111110100101000110",
"0100100011100000001000011001010110101101111001",
"0100100011100100001000101011100101001011101111",
"0100100011101100000111011010000001011010110001",
"0100110011001000000111101010000010111010111111",
"0100110011001100001011011110101110110110000001",
"0100110011101000011010111011001010001101110001",
"0100110011101101011010110101111001010100001111",
"0111000010000001010111000101010101010110010111",
"0111000010000101010111110111110101010010111011",
"0111000010110101101000101100001000010000011001",
"0111010010011001100100011110100100010010010010",
"0111010010111010100101100101000000110100100011",
"1010000010011010101101011101100001110010011010",
"1010000010111111111100100111010100010000111001",
"1010010111110100110010001100111001010110100000",
"1011010111010011111011011110000100110010100001",
"1110011011110001111011100111100001110110100111"
);
variable sta : std_logic_vector(45 downto 0);
variable stb : std_logic_vector(18 downto 0);
variable stf, stg : std_logic_vector(10 downto 0);
variable logsin : unsigned(11 downto 0);
variable subtresult : unsigned(10 downto 0);
variable atten_internal : unsigned(11 downto 0);
begin
if rising_edge(clk) then
-- Main sine table body
sta := sinetable(to_integer(phaselo(5 downto 1)));
-- 2-bit row chooser
case std_logic_vector(phaselo(7 downto 6)) is
when "00" => stb :=
"0000000000" & sta(29) & sta(25)
& "00" & sta(18) & sta(14)
& "0" & sta(7) & sta(3);
when "01" => stb :=
"000000" & sta(37) & sta(34)
& "00" & sta(28) & sta(24)
& "00" & sta(17) & sta(13)
& sta(10) & sta(6) & sta(2);
when "10" => stb :=
"00" & sta(43) & sta(41)
& "00" & sta(36) & sta(33)
& "00" & sta(27) & sta(23)
& "0" & sta(20) & sta(16)
& sta(12) & sta(9) & sta(5) & sta(1);
when others => stb :=
sta(45) & sta(44) & sta(42) & sta(40)
& sta(39) & sta(38) & sta(35) & sta(32)
& sta(31) & sta(30) & sta(26) & sta(22)
& sta(21) & sta(19) & sta(15) & sta(11)
& sta(8) & sta(4) & sta(0);
end case;
-- Fixed value to sum
stf := stb(18 downto 15) & stb(12 downto 11) & stb(8 downto 7) & stb(4 downto 3) & stb(0);
-- Gated value to sum; bit 14 is indeed used twice
stg := "00" & stb(14) & stb(14 downto 13) & stb(10 downto 9) & stb(6 downto 5) & stb(2 downto 1);
stg := stg and phaselo(0);
-- Sum to produce final logsin value
logsin := unsigned('0' & stf) + unsigned('0' & stg); -- Carry-out of 11-bit addition becomes 12th bit
-- Invert-subtract logsin value from EG attenuation value, with inverted carry
-- In the actual chip, the output of the above logsin sum is already inverted.
-- The two LSBs go through inverters (so they're non-inverted); the eg_atten signal goes through inverters.
-- The adder is normal except the carry-in is 1. It's a 10-bit adder.
-- The outputs are inverted outputs, including the carry bit.
--subtresult := not (('0' & not eg_atten) - ('1' & logsin(11 downto 2)));
-- After a little pencil-and-paper, turns out this is equivalent to a regular adder!
subtresult := ('0' & eg_atten) + ('0' & logsin(11 downto 2));
-- Place all but carry bit into result; also two LSBs of logsin
atten_internal := subtresult(9 downto 0) & logsin(1 downto 0);
-- If addition overflowed, make it the largest value (saturate)
atten_internal := atten_internal or subtresult(10);
totalatten <= atten_internal;
signbit_1 <= signbit;
end if;
end process;
-- REGISTER/CYCLE 4
-- Exponential table
exp_table: process(clk) is
type exptable_t is array(31 downto 0) of std_logic_vector(44 downto 0);
constant exptable: exptable_t := (
"101110011001000000110100010111111000111111011",
"110011011100001100000011111001011000111111011",
"010110111001011101110101101111000000111111011",
"011010101010000001110110000111000000111111011",
"110110101010000001010001100001000000111111011",
"101110111001111000110110111010101010010111011",
"000000110000110100111001011110111011010011011",
"011110111001100100010110100100111011010011011",
"010110111000101000110101100010110011010011011",
"001010111001010011110011001110000011010011011",
"101010011001011011010100111101000111000011011",
"110110011000011111110011110011001111100001011",
"101111011101100111100100000011001111100001011",
"100010101010101011010111101101111100100001011",
"110010011001100011010000001101111100100001011",
"101010111000011100110101011010110100100001011",
"111011011101010100100010110000110100100001011",
"100011011100111000000001010100100100100001011",
"110011011101110000000110101110001100000001011",
"101011111100001110100001101000001100000001011",
"101010011001000110110110010001001000000001011",
"101011011100101010000101110111010001000101110",
"110011111101100010000010011111110011001100110",
"100011011100001100100111001001110011001100110",
"010101011100000000100100101011111011101110100",
"000111011101101000000011000111101011101110100",
"010110011000100100010100110100101011101110100",
"000010011001000110010011011000001011101110100",
"100011011100101010100000011010000011101110100",
"110111011101100010100111100100010010101110100",
"000000001001000100110000000100010010101110100",
"000011011100101000000001100010011010001110100"
);
variable eta : std_logic_vector(44 downto 0);
variable etb : std_logic_vector(12 downto 0);
variable etf, etg : std_logic_vector(9 downto 0);
begin
if rising_edge(clk) then
-- Main sine table body
eta := exptable(to_integer(totalatten(5 downto 1)));
-- 2-bit row chooser
case std_logic_vector(totalatten(7 downto 6)) is
when "00" => etb := "1" & eta(43) & eta(40) & eta(36) & eta(32) & eta(28)
& eta(24) & "1" & eta(18) & eta(14) & eta(10) & eta(7) & eta(3);
when "01" => etb := eta(44) & eta(42) & eta(39) & eta(35) & eta(31) & eta(27)
& eta(23) & "1" & eta(17) & eta(13) & "0" & eta(6) & eta(2);
when "10" => etb := "0" & eta(41) & eta(38) & eta(34) & eta(30) & eta(26)
& eta(22) & eta(19) & eta(16) & eta(12) & eta(9) & eta(5) & eta(1);
when others => etb := "00" & eta(37) & eta(33) & eta(29) & eta(25)
& eta(21) & eta(20) & eta(15) & eta(11) & eta(8) & eta(4) & eta(0);
end case;
-- Fixed value to sum
etf := etb(12 downto 6) & etb(4) & etb(3) & etb(0);
-- Gated value to sum
etg := "0000000" & etb(5) & etb(2) & etb(1);
etg := etg and not totalatten(0);
--RESULT
mantissa <= unsigned(etf) + unsigned(etg); --carry-out discarded
exponent <= totalatten(11 downto 8);
signbit_2 <= signbit_1;
end if;
end process;
-- REGISTER/CYCLE 5
-- Floating-point to integer, and incorporating sign bit
shift_and_flip: process(clk) is
variable shifter : unsigned(12 downto 0);
variable result : unsigned(13 downto 0);
begin
if rising_edge(clk) then
-- Two-stage shifting of mantissa by exponent
shifter := "001" & mantissa;
case std_logic_vector(exponent(1 downto 0)) is
when "00" => shifter := '0' & shifter(12 downto 1); -- LSB discarded
-- when "01" => shifter := shifter; -- no change
when "10" => shifter := shifter(11 downto 0) & '0';
when "11" => shifter := shifter(10 downto 0) & "00";
when others => null;
end case;
case std_logic_vector(exponent(3 downto 2)) is
when "00" => shifter := "000000000000" & shifter(12);
when "01" => shifter := "00000000" & shifter(12 downto 8);
when "10" => shifter := "0000" & shifter(12 downto 4);
-- when "11" => shifter := shifter; -- no change
when others => null;
end case;
result := test_214 & shifter; -- Introduce test bit as MSB
-- 2's complement
result := result xor signbit_2;
result := result + signbit_2; -- Carry-out discarded
op_result_pre <= result;
end if;
end process;
-- REGISTER/CYCLE 6
-- Extra register, take output after here
register_output: process(clk) is begin
if rising_edge(clk) then
op_result_internal <= op_result_pre;
end if;
end process;
op_result <= op_result_internal;
-- Circular buffers for old operator output values
-- These latch op_result_internal on the clock after
-- it is generated in register_output, and they provide
-- their output (prev1, etc.) on the same cycle as
-- op_result_internal is available.
prev1_buffer: entity circular_buffer
generic map(
DATA_WIDTH => 14,
BUFFER_DEPTH => NUM_VOICES,
CLEAR_ON_RESET => false)
port map(
clk => clk,
rst_bar => rst_bar,
din => std_logic_vector(op_result_internal),
std_logic_vector(dout) => prev1,
load => op_algorithm_ctl(5)
);
prevprev1_buffer: entity circular_buffer
generic map(
DATA_WIDTH => 14,
BUFFER_DEPTH => NUM_VOICES,
CLEAR_ON_RESET => false)
port map(
clk => clk,
rst_bar => rst_bar,
din => std_logic_vector(prev1),
std_logic_vector(dout) => prevprev1,
load => op_algorithm_ctl(5)
);
prev2_buffer: entity circular_buffer
generic map(
DATA_WIDTH => 14,
BUFFER_DEPTH => NUM_VOICES,
CLEAR_ON_RESET => false)
port map(
clk => clk,
rst_bar => rst_bar,
din => std_logic_vector(op_result_internal),
std_logic_vector(dout) => prev2,
load => op_algorithm_ctl(0)
);
end architecture;
|
gpl-3.0
|
Dragonturtle/SHERPA
|
HDL/I2C/i2c_master.vhd
|
1
|
14466
|
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 Scott Larson
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
|
gpl-3.0
|
Dragonturtle/SHERPA
|
HDL/SHERPA/max2830_handler.vhd
|
1
|
4717
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity max2830_handler is
port (
clock_in : in std_logic;
reset_in : in std_logic;
sw_in : in std_logic_vector(7 downto 0);
din_out : out std_logic;
sclk_out : out std_logic;
cs_out : out std_logic
);
end max2830_handler;
architecture Behavioral of max2830_handler is
type state_type is (idle,fetching,sending,finishing,updating);
type spi_type is (starting, ending);
signal state : state_type := fetching;
signal spi_state : spi_type := starting;
signal max2830_config_addra : std_logic_vector(3 downto 0) := "0000";
signal max2830_config_data : std_logic_vector(17 downto 0);
signal spi_ena : std_logic := '0';
signal spi_valid : std_logic;
signal delay_counter : integer range 0 to 101 := 0;
signal swState_current : std_logic_vector(7 downto 0) := "00111111";
signal swState_old : std_logic_vector(7 downto 0) := "00111111";
alias clk : std_logic is clock_in;
alias rst : std_logic is reset_in;
alias din : std_logic is din_out;
alias sclk : std_logic is sclk_out;
alias cs : std_logic is cs_out;
begin
spi_interface : entity work.spi_master
generic map ( N => 18 )
port map (
sclk_i => clk,
pclk_i => clk,
rst_i => rst,
spi_ssel_o => cs,
spi_sck_o => sclk,
spi_mosi_o => din,
spi_miso_i => open,
di_req_o => open,
di_i => max2830_config_data,
wren_i => spi_ena,
wr_ack_o => open,
do_valid_o => spi_valid,
do_o => open
);
state_machine : process(clk, rst, max2830_config_addra)
constant delay_threshold : integer := 100;
type max2839_config_data is array (15 downto 0) of std_logic_vector(17 downto 0);
variable max2839_config : max2839_config_data :=
("010" & "1" & "1101000000" & "0000",
"0" & "1" & "000110011010" & "0001",
"01000000000011" & "0010",
"10011" & "001111010" & "0011",
"01100110011001" & "0100",
"0000" & "0" & "010" & "0" & "00" & "1" & "00" & "0101",
"0" & "00" & "0000" & "0" & "1000" & "0" & "0" & "0110",
"01" & "000000" & "010" & "010" & "0111",
"1" & "1" & "0" & "0" & "00" & "001000" & "00" & "1000",
"000" & "1" & "1110110101" & "1001",
"0111" & "011" & "0100" & "100" & "1010",
"0000000" & "00" & "00000" & "1011",
"00000101" & "000000" & "1100",
"0011" & "1010" & "010010" & "1101",
"000" & "0" & "0" & "10" & "0111011" & "1110",
"00" & "01" & "0101000101" & "1111");
begin
if (rst = '1') then
max2830_config_addra <= "0000";
delay_counter <= 0;
state <= fetching;
elsif (rising_edge(clk)) then
case state is
when fetching =>
delay_counter <= delay_counter + 1;
spi_ena <= '0';
if (delay_counter = delay_threshold) then
max2830_config_data <= max2839_config(to_integer(15-unsigned(max2830_config_addra)));
elsif (delay_counter = delay_threshold + 1) then
delay_counter <= 0;
state <= sending;
spi_state <= starting;
end if;
when sending =>
case spi_state is
when starting =>
spi_ena <= '1';
spi_state <= ending;
when ending =>
spi_ena <= '0';
if (spi_valid = '1') then
if (to_integer(unsigned(max2830_config_addra)) = 15) then
state <= finishing;
else
state <= fetching;
max2830_config_addra <= std_logic_vector(unsigned(max2830_config_addra) + 1);
end if;
end if;
when others => null;
end case;
when finishing =>
delay_counter <= delay_counter + 1;
spi_ena <= '0';
if (delay_counter = delay_threshold) then
delay_counter <= 0;
state <= idle;
end if;
when idle =>
spi_ena <= '0';
swState_current <= sw_in;
swState_old <= swState_current;
if (swState_current /= swState_old) then
state <= updating;
spi_state <= starting;
if (swState_current(7) = '1') then
max2830_config_data <= "00000101" & swState_current(5 downto 0) & "1100";
else
max2830_config_data <= "0000000" & swState_current(6 downto 0) & "1011";
end if;
end if;
when updating =>
case spi_state is
when starting =>
spi_ena <= '1';
spi_state <= ending;
when ending =>
spi_ena <= '0';
if (spi_valid = '1') then
state <= idle;
end if;
end case;
when others => null;
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
Dragonturtle/SHERPA
|
HDL/SHERPA/Memory/si5351c_config_rom.vhd
|
1
|
5494
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2017 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file si5351c_config_rom.vhd when simulating
-- the core, si5351c_config_rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY si5351c_config_rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END si5351c_config_rom;
ARCHITECTURE si5351c_config_rom_a OF si5351c_config_rom IS
-- synthesis translate_off
COMPONENT wrapped_si5351c_config_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_si5351c_config_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 7,
c_addrb_width => 7,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "si5351c_config_rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 128,
c_read_depth_b => 128,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 128,
c_write_depth_b => 128,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_si5351c_config_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END si5351c_config_rom_a;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/arch_defs.vhdl
|
1
|
10347
|
library ieee;
use ieee.std_logic_1164.all;
package arch_defs is
subtype byte_t is std_logic_vector( 7 downto 0);
subtype half_t is std_logic_vector(15 downto 0);
subtype word_t is std_logic_vector(31 downto 0);
subtype addr_t is std_logic_vector(31 downto 0);
subtype intaddr_t is std_logic_vector(31 downto 0);
subtype addrdiff_t is std_logic_vector(31 downto 0);
subtype ctrl_t is std_logic;
subtype ctrl_memwidth_t is std_logic_vector(1 downto 0);
subtype instruction_t is word_t;
subtype mask_t is word_t;
subtype reg_t is std_logic_vector(4 downto 0);
subtype opcode_t is std_logic_vector(5 downto 0);
subtype func_t is std_logic_vector(5 downto 0);
function is_type_r(instr: instruction_t) return boolean;
function is_type_j(instr: instruction_t) return boolean;
function is_type_I(instr: instruction_t) return boolean;
function J(op : std_logic_vector) return std_logic_vector;
function I(op : std_logic_vector; rs : std_logic_vector := "-----"; rt :std_logic_vector := "-----") return std_logic_vector;
function R(op : std_logic_vector := "000000"; rs : std_logic_vector := "-----"; rt : std_logic_vector := "-----"; rd : std_logic_vector := "-----";shift : std_logic_vector := "00000"; func : std_logic_vector(5 downto 0)) return std_logic_vector;
function word(w : word_t) return word_t;
function half(w : word_t) return half_t;
function byte(w : word_t) return byte_t;
constant WIDTH_NONE : ctrl_memwidth_t := "00";
constant WIDTH_BYTE : ctrl_memwidth_t := "01";
constant WIDTH_HALF : ctrl_memwidth_t := "10";
constant WIDTH_WORD : ctrl_memwidth_t := "11";
type alu_op_t is (
ALU_ADD, ALU_ADDU, ALU_SUB, ALU_SUBU,
ALU_AND, ALU_OR, ALU_NOR, ALU_XOR, ALU_LU,
ALU_SLL, ALU_SRL, ALU_SRA,
ALU_MULT, ALU_MULTU, ALU_DIV, ALU_DIVU,
ALU_MFHI, ALU_MFLO, ALU_MTHI, ALU_MTLO,
ALU_SLT, ALU_SLTU, -- TODO zero extend or sign extent?
ALU_EQ, ALU_NE, ALU_LEZ, ALU_LTZ, ALU_GTZ, ALU_GEZ
);
subtype traps_t is std_logic_vector(7 downto 0);
constant TRAP_NONE : traps_t := X"00";
constant TRAP_DIVERROR : traps_t := X"01";
constant TRAP_OVERFLOW : traps_t := X"02";
constant TRAP_SEGFAULT : traps_t := X"04";
constant TRAP_BREAKPOINT : traps_t := X"08";
constant TRAP_SYSCALL : traps_t := X"10";
constant TRAP_EPE : traps_t := X"20";
constant TRAP_UNIMPLEMENTED : traps_t := X"40";
type exception_config_t is (
EXCEPTIONS_IGNORE -- Bad idea!
--EXCEPTIONS_HALT,-- e.g. light a red LED and stop fetching new instructions
--EXCEPTIONS_RESET-- reboot
--EXCEPTIONS_TRAP -- invoke user-programmable exception handlers
);
-- Taken from https://opencores.org/project,plasma,opcodes
-- And http://web.cse.ohio-state.edu/~crawfis.3/cse675-02/Slides/MIPS%20Instruction%20Set.pdf
-- 32 bit defines
constant ZERO : word_t := X"00000000";
constant HI_Z : word_t := (others => 'Z');
constant NEG_ONE : word_t := not ZERO;
constant INT_MIN : word_t := X"8000_0000";
constant INT_MAX : word_t := X"7fff_ffff";
constant DONT_CARE : word_t := (others => 'X');
-- Register file
constant R0 : reg_t := B"0_0000"; -- $zero
constant R1 : reg_t := B"0_0001"; alias AT is R1;
constant R2 : reg_t := B"0_0010"; alias v0 is R2;
constant R3 : reg_t := B"0_0011"; alias v1 is R3;
constant R4 : reg_t := B"0_0100"; alias a0 is R4;
constant R5 : reg_t := B"0_0101"; alias a1 is R5;
constant R6 : reg_t := B"0_0110"; alias a2 is R6;
constant R7 : reg_t := B"0_0111"; alias a3 is R7;
constant R8 : reg_t := B"0_1000"; alias t0 is R8;
constant R9 : reg_t := B"0_1001"; alias t1 is R9;
constant R10 : reg_t := B"0_1010"; alias t2 is R10;
constant R11 : reg_t := B"0_1011"; alias t3 is R11;
constant R12 : reg_t := B"0_1100"; alias t4 is R12;
constant R13 : reg_t := B"0_1101"; alias t5 is R13;
constant R14 : reg_t := B"0_1110"; alias t6 is R14;
constant R15 : reg_t := B"0_1111"; alias t7 is R15;
constant R16 : reg_t := B"1_0000"; alias s0 is R16;
constant R17 : reg_t := B"1_0001"; alias s1 is R17;
constant R18 : reg_t := B"1_0010"; alias s2 is R18;
constant R19 : reg_t := B"1_0011"; alias s3 is R19;
constant R20 : reg_t := B"1_0100"; alias s4 is R20;
constant R21 : reg_t := B"1_0101"; alias s5 is R21;
constant R22 : reg_t := B"1_0110"; alias s6 is R22;
constant R23 : reg_t := B"1_0111"; alias s7 is R23;
constant R24 : reg_t := B"1_1000"; alias t8 is R24;
constant R25 : reg_t := B"1_1001"; alias t9 is R25;
constant R26 : reg_t := B"1_1010"; alias k0 is R26;
constant R27 : reg_t := B"1_1011"; alias k1 is R27;
constant R28 : reg_t := B"1_1100"; alias gp is R28;
constant R29 : reg_t := B"1_1101"; alias sp is R29;
constant R30 : reg_t := B"1_1110"; alias fp is R30;
constant R31 : reg_t := B"1_1111"; alias ra is R31;
constant VGA_PIXELFREQ : natural := 25175*1000;
end arch_defs;
package body arch_defs is
function is_type_r(instr: instruction_t) return boolean is
begin
return instr(31 downto 26) = "000000";
end is_type_r;
function is_type_j(instr: instruction_t) return boolean is
begin
return instr(31 downto 26) = "000010"
or instr(31 downto 26) = "000011";
end is_type_j;
function is_type_i(instr: instruction_t) return boolean is
begin
return not is_type_j(instr) and not is_type_r(instr);
end is_type_i;
function J(op : std_logic_vector) return std_logic_vector is
begin return op & (31-6 downto 0 => '-');
end J;
function I(op : std_logic_vector; rs : std_logic_vector := "-----"; rt :std_logic_vector := "-----") return std_logic_vector is
begin return op & rs & rt & (15 downto 0 => '-');
end I;
function R(op : std_logic_vector := "000000"; rs : std_logic_vector := "-----"; rt : std_logic_vector := "-----"; rd : std_logic_vector := "-----";shift : std_logic_vector := "00000"; func : std_logic_vector(5 downto 0)) return std_logic_vector is
begin return op & (14 downto 0 => '-') & shift & func;
end R;
function word(w : word_t) return word_t is
begin
return w(31 downto 0);
end function;
function half(w : word_t) return half_t is
begin
return w(15 downto 0);
end function;
function byte(w : word_t) return byte_t is
begin
return w( 7 downto 0);
end function;
-- ALU
constant OP_ADD : mask_t := R(func => "100000");
constant OP_ADDU : mask_t := R(func => "100001");
constant OP_AND : mask_t := R(func => "100100");
constant OP_NOR : mask_t := R(func => "100111");
constant OP_OR : mask_t := R(func => "100101");
constant OP_SLT : mask_t := R(func => "101010");
constant OP_SLTU : mask_t := R(func => "101011");
constant OP_SUB : mask_t := R(func => "100010");
constant OP_SUBU : mask_t := R(func => "100011");
constant OP_XOR : mask_t := R(func => "100110");
constant OP_ADDI : mask_t := I(op => "001000");
constant OP_ADDIU : mask_t := I(op => "001001");
constant OP_ANDI : mask_t := I(op => "001100");
constant OP_LUI : mask_t := I(op => "001111");
constant OP_ORI : mask_t := I(op => "001101");
constant OP_SLTI : mask_t := I(op => "001010");
constant OP_SLTIU : mask_t := I(op => "001011");
constant OP_XORI : mask_t := I(op => "001110");
-- Shifter
constant OP_SLL : mask_t := R(shift => "-----", func => "000000");
constant OP_SLLV : mask_t := R(shift => "00000", func => "000100");
constant OP_SRA : mask_t := R(shift => "-----", func => "000011");
constant OP_SRAV : mask_t := R(shift => "00000", func => "000111");
constant OP_SRL : mask_t := R(shift => "-----", func => "000010");
constant OP_SRLV : mask_t := R(shift => "00000", func => "000110");
-- Multiply and Divide
constant OP_DIV : mask_t := R(rd => "00000", func => "011010");
constant OP_DIVU : mask_t := R(rd => "00000", func => "011011");
constant OP_MFHI : mask_t := R(rs => "00000", rt => "00000", func => "010000");
constant OP_MFLO : mask_t := R(rs => "00000", rt => "00000", func => "010010");
constant OP_MTHI : mask_t := R(rt => "00000", rd => "00000", func => "010001");
constant OP_MTLO : mask_t := R(rt => "00000", rd => "00000", func => "010011");
constant OP_MULT : mask_t := R(rd => "00000", func => "011000");
constant OP_MULTU : mask_t := R(rd => "00000", func => "011001");
-- Branch
constant OP_BEQ : mask_t := I(op => "000100");
constant OP_BGEZ : mask_t := I(op => "000001", rt => "00001");
constant OP_BGEZAL: mask_t := I(op => "000001", rt => "10001");
constant OP_BGTZ : mask_t := I(op => "000111", rt => "00000");
constant OP_BLEZ : mask_t := I(op => "000110", rt => "00000");
constant OP_BLTZ : mask_t := I(op => "000001", rt => "00000");
constant OP_BLTZAL: mask_t := I(op => "000001", rt => "10000");
constant OP_BNE : mask_t := I(op => "000101");
constant OP_J : mask_t := J(op => "000010");
constant OP_JAL : mask_t := J(op => "000011");
constant OP_JR : mask_t := R(rt => R0, func => "001000", rd => R0);
constant OP_JALR : mask_t := R(rt => R0, func => "100010");
constant OP_BREAK : mask_t := "000000"&(19 downto 0 => '-')&"001101";
constant OP_MFC0 : mask_t := "010000"&"00000"&(9 downto 0 => '-')&(10 downto 0 => '0');
constant OP_MTC0 : mask_t := "010000"&"00100"&(9 downto 0 => '-')&(10 downto 0 => '0');
constant OP_SYSCALL : mask_t := "000000"&(19 downto 0 => '-')&"001100";
-- Memory Access
constant OP_LB : mask_t := I(op => "100000");
constant OP_LBU : mask_t := I(op => "100100");
constant OP_LH : mask_t := I(op => "100001");
constant OP_LHU : mask_t := I(op => "100101");
constant OP_LW : mask_t := I(op => "100011");
constant OP_SB : mask_t := I(op => "101000");
constant OP_SH : mask_t := I(op => "101001");
constant OP_SW : mask_t := I(op => "101011");
end arch_defs;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/txt_utils.vhdl
|
1
|
14808
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all; --defines line, output
package txt_utils is
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
function TO_BSTRING (value : STD_LOGIC_VECTOR) return STRING;
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
-- can't resolve overload for function call, slice or indexed name, otherwise
--alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
--alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
--function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
--alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
--function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
--alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
--function TO_HSTRING (VALUE : UNSIGNED) return STRING;
--alias TO_HEX_STRING is TO_HSTRING [UNSIGNED return STRING];
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
--pragma synthesis_off
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
--pragma synthesis_on
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- File: debugio_h.vhd
-- Version: 3.0 (June 6, 2004)
-- Source: http://bear.ces.cwru.edu/vhdl
-- Date: June 6, 2004 (Copyright)
-- Author: Francis G. Wolff Email: [email protected]
-- Author: Michael J. Knieser Email: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version: http://www.gnu.org/licenses/gpl.html
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
function sprintf(fmt: string; s0, s1, s2, s3: string; i0: integer) return string;
procedure printf(fmt: string; s0, s1, s2, s3: string; i0: integer);
procedure printf(fmt: string);
procedure printf(fmt: string; s1: string);
procedure printf(fmt: string; s1, s2: string);
procedure printf(fmt: string; i1: integer);
procedure printf(fmt: string; i1: integer; s2: string);
procedure printf(fmt: string; i1: integer; s2, s3: string);
procedure printf(fmt: string; v0: std_logic_vector);
procedure printf(fmt: string; v0, v1: std_logic_vector);
procedure printf(fmt: string; v0, v1, v2: std_logic_vector);
procedure printf(fmt: string; v0, v1, v2, v3: std_logic_vector);
procedure printf(fmt: string; s0 : string; v0: std_logic_vector);
procedure printf(fmt: string; v0 : std_logic_vector; s0: string);
function pf(arg1: in boolean) return string;
constant ANSI_NONE : string := ESC & "[m";
constant ANSI_RED : string := ESC & "[31m";
constant ANSI_GREEN : string := ESC & "[32m";
constant ANSI_BLUE : string := ESC & "[34m";
end txt_utils;
package body txt_utils is
--synth
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1) := "!";
begin
--pragma synthesis_off
result (1) := MVL9_to_char (value);
--pragma synthesis_on
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_string;
-- ISE chokes on function aliases, so duplicating the code here
function to_bstring (value : STD_LOGIC_VECTOR) return STRING is
alias ivalue : STD_LOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_bstring;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_hstring;
function to_hstring (VALUE : UNSIGNED) return STRING is
begin
return TO_HSTRING(std_logic_vector(VALUE));
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
--pragma synthesis_off
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
--pragma synthesis_on
return NUS;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
function sprintf(fmt: string; s0, s1, s2, s3: string; i0: integer) return string is
variable W: line; variable i, fi, di: integer:=0;
begin
--pragma synthesis_off
loop
--write(W, string'("n=")); write(W, s0'length);
--write(W, string'(" L=")); write(W, s0'left);
--write(W, string'(" R=")); write(W, s0'right);
--writeline(output, W);
fi:=fi+1; if fi>fmt'length then exit; end if;
if fmt(fi)='%' then
fi:=fi+1; if fi>fmt'length then exit; end if;
if fmt(fi)='s' then
case di is
when 0 => i:=s0'left;
while i<=s0'right loop
if s0(i)=NUL then exit; end if;
write(W, s0(i)); i:=i+1;
end loop;
when 1 => i:=s1'left;
while i<=s1'right loop
if s1(i)=NUL then exit; end if;
write(W, s1(i)); i:=i+1;
end loop;
when 2 => i:=s2'left;
while i<=s2'length loop
if s2(i)=NUL then exit; end if;
write(W, s2(i)); i:=i+1;
end loop;
when 3 => i:=s3'left;
while i<=s3'length loop
if s3(i)=NUL then exit; end if;
write(W, s3(i)); i:=i+1;
end loop;
when others =>
end case;
di:=di+1;
elsif fmt(fi)='d' or fmt(fi)='i' then
case di is
when 0 => write(W, i0); when others => end case;
di:=di+1;
end if;
elsif fmt(fi)='\' then
fi:=fi+1; if fi>fmt'length then exit; end if;
case fmt(fi) is
when 'n' => write(W, LF);
when others => write(W, fmt(fi));
end case;
else write(W, fmt(fi));
end if;
end loop;
return W.all;
--pragma synthesis_on
return "";
end sprintf;
procedure printf(fmt: string; s0, s1, s2, s3: string; i0: integer) is
variable W: line;
variable lastch : string(1 to 2) := fmt(fmt'high-1 to fmt'high);
begin
--pragma synthesis_off
Write(W, ANSI_BLUE);
Write(W, sprintf(fmt(fmt'low to fmt'high-1), s0, s1, s2, s3, i0));
if not (fmt(fmt'high) = 'n' and fmt(fmt'high -1) = '\') then
Write(W, fmt(fmt'high-1 to fmt'high-2));
end if;
Write(W, ANSI_NONE);
writeline(output, W);
--pragma synthesis_on
end printf;
procedure printf(fmt: string) is
begin printf(fmt, "", "", "", "", 0); end printf;
procedure printf(fmt: string; s1: string) is
begin printf(fmt, s1, "", "", "", 0); end printf;
procedure printf(fmt: string; s1, s2: string) is
begin printf(fmt, s1, s2, "", "", 0); end printf;
procedure printf(fmt: string; i1: integer) is
begin printf(fmt, "", "", "", "", i1); end printf;
procedure printf(fmt: string; i1: integer; s2: string) is
begin printf(fmt, "", s2, "", "", i1); end printf;
procedure printf(fmt: string; i1: integer; s2, s3: string) is
begin printf(fmt, "", s2, s3, "", i1); end printf;
procedure printf(fmt: string; v0, v1, v2, v3: std_logic_vector) is
begin printf(fmt, to_hstring(v0), to_hstring(v1), to_hstring(v2), to_hstring(v3), 0); end printf;
procedure printf(fmt: string; v0, v1, v2: std_logic_vector) is
begin printf(fmt, v0, v1, v2, ""); end printf;
procedure printf(fmt: string; v0: std_logic_vector) is
begin printf(fmt, to_hstring(v0), "", "", "", 0); end printf;
procedure printf(fmt: string; v0, v1: std_logic_vector) is
begin printf(fmt, to_hstring(v0), to_hstring(v1), "", "", 0); end printf;
procedure printf(fmt: string; s0 : string; v0: std_logic_vector) is
begin printf(fmt, s0, to_hstring(v0), "", "", 0); end printf;
procedure printf(fmt: string; v0 : std_logic_vector; s0: string) is
begin printf(fmt, to_hstring(v0), s0, "", "", 0); end printf;
function pf(arg1: in boolean) return string is
begin
if arg1 then return "true"; else return "false"; end if;
end pf;
end txt_utils;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/arch/cpu.vhdl
|
1
|
14194
|
-- The CPU, only the stateless parts
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.memory_map.all;
-- We keep keep all state (registers, memory) out of the CPU
-- This allows for testbenches that can instantiate them internally
-- and check whether everything works as expected
entity cpu is
generic(PC_ADD : natural := 4;
SINGLE_ADDRESS_SPACE : boolean := true);
port(
clk : in std_logic;
rst : in std_logic;
-- Register File
readreg1, readreg2 : out reg_t;
writereg: out reg_t;
regWriteData: out word_t;
regReadData1, regReadData2 : in word_t;
regwrite : out std_logic;
-- Memory
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t;
-- Debug info
instruction : out instruction_t
);
end;
architecture struct of cpu is
component Pipeliner is
port(
clk, rst : in std_logic;
ID_en, IF_en, EX_en, MEM_en, MEM_read, WB_en : out std_logic;
Instruction_done : out std_logic
);
end component;
component PipeReg is
generic (BITS : natural := 32);
port(
data : in std_logic_vector(BITS-1 downto 0);
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out std_logic_vector(BITS-1 downto 0) -- output.
);
end component;
component CtrlReg is port(
data : in std_logic;
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out std_logic
);
end component;
component AluOpReg is port(
data : in alu_op_t;
enable : in std_logic; -- load/enable.
clr : in std_logic; -- async. clear.
clk : in std_logic; -- clock.
output : out alu_op_t
);
end component;
component MUX is
generic (BITS : natural := 32);
port (
sel: in ctrl_t;
input0 : in std_logic_vector(BITS-1 downto 0);
input1 : in std_logic_vector(BITS-1 downto 0);
output : out std_logic_vector(BITS-1 downto 0)
);
end component;
component MUX1bit is
port (
sel: in ctrl_t;
input0 : in std_logic;
input1 : in std_logic;
output : out std_logic
);
end component;
component InstructionFetch is
generic(PC_ADD : natural := PC_ADD;
SINGLE_ADDRESS_SPACE : boolean := SINGLE_ADDRESS_SPACE);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
signal IF_en : std_logic := '0';
signal ID_en : std_logic := '0';
signal EX_en : std_logic := '0';
signal MEM_en : std_logic := '0';
signal MEM_read : std_logic := '0';
signal WB_en : std_logic := '0';
signal Instruction_done : std_logic := '0';
signal regwrite_no_wb : std_logic := '0';
signal regwrite_pre_reg : ctrl_t;
signal Link, JumpReg, JumpDir, Branch, MemToReg, Shift, ALUSrc, MemSex : ctrl_t;
signal Link_pre_reg, JumpReg_pre_reg, JumpDir_pre_reg, Branch_pre_reg, MemToReg_pre_reg, Shift_pre_reg, ALUSrc_pre_reg, MemSex_pre_reg : ctrl_t;
signal TakeBranch, TakeBranch_pre_reg : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal MemRead_pre_reg, MemWrite_pre_reg : ctrl_memwidth_t;
signal memReadData, memReadData_pre_reg : word_t;
signal new_pc, new_pc_pre_reg : addr_t := BOOT_ADDR;
signal pc_plus_4, pc_plus_4_pre_reg, jump_addr, jump_addr_pre_reg, branch_addr : addr_t;
signal instr, instr_pre_reg : instruction_t;
signal zeroxed, sexed, zeroxed_pre_reg, sexed_pre_reg, aluResult, aluResult_pre_reg: word_t;
signal readreg1_pre_reg, readreg2_pre_reg, writereg_pre_reg : reg_t;
signal regwritedata_pre_reg : word_t;
signal aluop : alu_op_t;
signal aluop_slv : natural; -- debug only;
signal aluop_pre_reg : alu_op_t;
signal selMEM : ctrl_t := '0';
signal top_addr_mem, top_addr_if : addr_t;
signal top_din_mem, top_din_if : word_t;
signal top_size_mem, top_size_if : ctrl_memwidth_t;
signal top_wr_mem, top_wr_if : ctrl_t;
begin
aluop_slv <= alu_op_t'pos(aluop);
if1: InstructionFetch
generic map (PC_ADD => PC_ADD)
port map(
clk => clk,
rst => rst,
new_pc => new_pc,
pc_plus_4 => pc_plus_4_pre_reg,
instr => instr_pre_reg,
top_addr => top_addr_if,
top_dout => top_dout,
top_din => top_din_if,
top_size => top_size_if,
top_wr => top_wr_if
);
regwrite <= WB_en and regwrite_no_wb;
new_pc_reg: PipeReg
generic map(32)
port map (
data => new_pc_pre_reg,
enable => WB_en,
clr => rst,
clk => clk,
output => new_pc
);
pc_plus_4_reg: PipeReg
generic map(32)
port map (
data => pc_plus_4_pre_reg,
enable => IF_en,
clr => rst,
clk => clk,
output => pc_plus_4
);
instr_reg: PipeReg
generic map(32)
port map (
data => instr_pre_reg,
enable => IF_en,
clr => rst,
clk => clk,
output => instr
);
instruction <= instr;
id1: InstructionDecode
port map(
instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr_pre_reg,
regwrite => regwrite_pre_reg, link => link_pre_reg, jumpreg => jumpreg_pre_reg, jumpdirect => jumpDir_pre_reg, branch => Branch_pre_reg,
memread => memRead_pre_reg, memwrite => memWrite_pre_reg,
memtoreg => memToReg_pre_reg, memsex => memSex_pre_reg,
shift => shift_pre_reg, alusrc => aluSrc_pre_reg,
aluop => aluOp_pre_reg,
readreg1 => readReg1_pre_reg, readreg2 => readReg2_pre_reg, writeReg => writeReg_pre_reg,
zeroxed => zeroxed_pre_reg, sexed => sexed_pre_reg,
clk => clk,
rst => rst
);
readreg1_reg: PipeReg
generic map(5)
port map (
data => readreg1_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => readreg1
);
readreg2_reg: PipeReg
generic map(5)
port map (
data => readreg2_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => readreg2
);
writereg_reg: PipeReg
generic map(5)
port map (
data => writereg_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => writereg
);
pipeliner1: pipeliner port map (
clk => clk,
rst => rst,
IF_en => IF_en,
ID_en => ID_en,
EX_en => EX_en,
MEM_en => MEM_en,
MEM_read => MEM_read,
WB_en => WB_en,
Instruction_done => Instruction_done
);
ctrlvec_regwrite_reg : CtrlReg port map (data => regwrite_pre_reg, enable => ID_en, clr => rst, clk => clk, output => regwrite_no_wb);
--ctrlvec_regdst_reg : CtrlReg port map (data => regdst_pre_reg, enable => ID_en, clr => rst, clk => clk, output => regdst);
ctrlvec_link_reg : CtrlReg port map (data => link_pre_reg, enable => ID_en, clr => rst, clk => clk, output => link);
ctrlvec_jumpreg_reg : CtrlReg port map (data => jumpreg_pre_reg, enable => ID_en, clr => rst, clk => clk, output => jumpreg);
ctrlvec_jumpdirect_reg : CtrlReg port map (data => jumpdir_pre_reg, enable => ID_en, clr => rst, clk => clk, output => jumpdir);
ctrlvec_branch_reg : CtrlReg port map (data => branch_pre_reg, enable => ID_en, clr => rst, clk => clk, output => branch);
ctrlvec_memread_reg : PipeReg generic map(2) port map (data => memread_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memread);
ctrlvec_memtoreg_reg : CtrlReg port map (data => memtoreg_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memtoreg);
ctrlvec_memsex_reg : CtrlReg port map (data => memsex_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memsex);
ctrlvec_memwrite_reg : PipeReg generic map (2) port map (data => memwrite_pre_reg, enable => ID_en, clr => rst, clk => clk, output => memwrite);
ctrlvec_shift_reg : CtrlReg port map (data => shift_pre_reg, enable => ID_en, clr => rst, clk => clk, output => shift);
ctrlvec_alusrc_reg : CtrlReg port map (data => alusrc_pre_reg, enable => ID_en, clr => rst, clk => clk, output => alusrc);
ctrlvec_aluop_reg : AluOpReg port map (data => aluop_pre_reg, enable => ID_en, clr => rst, clk => clk, output => aluop);
jump_addr_reg: PipeReg
generic map(32)
port map (
data => jump_addr_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => jump_addr
);
zeroxed_reg: PipeReg
generic map(32)
port map (
data => zeroxed_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => zeroxed
);
sexed_reg: PipeReg
generic map(32)
port map (
data => sexed_pre_reg,
enable => ID_en,
clr => rst,
clk => clk,
output => sexed
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch_pre_reg,
ALUResult => ALUResult_pre_reg,
clk => clk,
rst => rst
);
takeBranch_reg: CtrlReg
port map (
data =>takeBranch_pre_reg,
enable => EX_en,
clr => rst,
clk => clk,
output => takeBranch
);
aluResult_reg: PipeReg
generic map(32)
port map (
data => aluResult_pre_reg,
enable => EX_en,
clr => rst,
clk => clk,
output => aluResult
);
process (clk)
begin
if rising_edge(clk) and (EX_en = '1' or WB_en = '1') then
selMEM <= not selMEM;
end if;
end process;
addrMux: MUX port map(sel=>selMEM,input0=>top_addr_if,input1=>top_addr_mem,output=>top_addr);
dinMux: MUX port map(sel=>selMEM,input0=>top_din_if, input1=>top_din_mem,output=>top_din);
sizeMux: MUX generic map(2) port map(sel=>selMEM,input0=>top_size_if,input1=>top_size_mem,output=>top_size);
wrMux: MUX1bit port map(sel=>selMEM,input0=>top_wr_if, input1=>top_wr_mem,output=>top_wr);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData_pre_reg,
MemRead_in => memRead,
MemWrite_in => memWrite,
MemSex_in => MemSex,
clk => clk,
-- outbound to top level module
top_addr => top_addr_mem,
top_dout => top_dout,
top_din => top_din_mem,
top_size => top_size_mem,
top_wr => top_wr_mem);
memReadData_reg: PipeReg
generic map (32)
port map (
data => memReadData_pre_reg,
enable => MEM_en,
clr => rst,
clk => clk,
output => memReadData
);
-- TODO: Remove this?
regWrite_data_reg: PipeReg
generic map(32)
port map (
data => regwritedata_pre_reg,
enable => '1',
clr => rst,
clk => clk,
output => regwritedata
);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData_pre_reg,
new_pc => new_pc_pre_reg);
end struct;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/arch/PC.vhdl
|
1
|
736
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.memory_map.all;
-- Remove for synthesize?
use work.txt_utils.all;
entity PC is
port (
next_addr : in addr_t;
clk : in std_logic;
rst : in std_logic;
addr : out addr_t
);
end PC;
architecture behav of PC is
constant bootaddr : addr_t := BOOT_ADDR; -- X"bfc0_0000";
begin process(next_addr, clk, rst)
begin
if rst = '1' then
addr <= bootaddr;
printf("[RESET] Next PC: %s\n", bootaddr);
elsif rising_edge(clk) then
addr <= next_addr;
printf(ANSI_RED & "Next PC: %s\n", next_addr);
end if;
end process;
end behav;
|
gpl-3.0
|
makestuff/dvr-connectors
|
conv-72to8/vhdl/conv_72to8.vhdl
|
1
|
4307
|
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_72to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 72-bit data coming in
data72_in : in std_logic_vector(71 downto 0);
valid72_in : in std_logic;
ready72_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_72to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4,
S_WRITE5,
S_WRITE6,
S_WRITE7,
S_WRITE8
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(63 downto 0) := (others => '0');
signal wip_next : std_logic_vector(63 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data72_in, valid72_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(63 downto 56);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(55 downto 48);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3
when S_WRITE3 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(47 downto 40);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE4;
end if;
-- Write byte 4
when S_WRITE4 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(39 downto 32);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE5;
end if;
-- Write byte 5
when S_WRITE5 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(31 downto 24);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE6;
end if;
-- Write byte 6
when S_WRITE6 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE7;
end if;
-- Write byte 7
when S_WRITE7 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE8;
end if;
-- Write byte 8 (LSB)
when S_WRITE8 =>
ready72_out <= '0'; -- not ready for data from 72-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready72_out <= ready8_in; -- ready for data from 72-bit side
data8_out <= data72_in(71 downto 64);
valid8_out <= valid72_in;
if ( valid72_in = '1' and ready8_in = '1' ) then
wip_next <= data72_in(63 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/tb/cpu_tb.vhdl
|
1
|
8806
|
-- SKIP because I still have to get it working
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
use work.memory_map.all;
entity cpu_tb is
end;
architecture struct of cpu_tb is
component regFile is
port (
readreg1, readreg2 : in reg_t;
writereg: in reg_t;
writedata: in word_t;
readData1, readData2 : out word_t;
clk : in std_logic;
rst : in std_logic;
regWrite : in std_logic
);
end component;
signal readreg1, readreg2 : reg_t := R0;
signal writereg: reg_t := R0;
signal regReadData1, regReadData2, regWriteData : word_t := ZERO;
signal regWrite : ctrl_t := '0';
component mem is
port (
addr : in addr_t;
din : in word_t;
dout : out word_t;
size : in ctrl_memwidth_t;
wr : in std_logic;
clk : in std_logic
);
end component;
component InstructionFetch is
generic(PC_ADD, CPI : natural; SINGLE_ADDRESS_SPACE : boolean);
port (
clk : in std_logic;
rst : in std_logic;
new_pc : in addr_t;
pc_plus_4 : out addr_t;
instr : out instruction_t;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t
);
end component;
component InstructionDecode is
port(
instr : in instruction_t;
pc_plus_4 : in addr_t;
jump_addr : out addr_t;
regwrite, link, jumpreg, jumpdirect, branch : out ctrl_t;
memread, memwrite : out ctrl_memwidth_t;
memtoreg, memsex : out ctrl_t;
shift, alusrc : out ctrl_t;
aluop : out alu_op_t;
readreg1, readreg2, writereg : out reg_t;
zeroxed, sexed : out word_t;
clk : in std_logic;
rst : in std_logic);
end component;
component Execute is
port (
pc_plus_4 : in addr_t;
regReadData1, regReadData2 : in word_t;
branch_addr : out addr_t;
branch_in : in ctrl_t;
shift_in, alusrc_in : in ctrl_t;
aluop_in : in alu_op_t;
zeroxed, sexed : in word_t;
takeBranch : out ctrl_t;
AluResult : out word_t;
clk : in std_logic;
rst : in std_logic
);
end component;
component MemoryAccess is
port(
-- inbound
Address_in : in addr_t;
WriteData_in : in word_t;
ReadData_in : out word_t;
MemRead_in, MemWrite_in : in ctrl_memwidth_t;
MemSex_in : in std_logic;
clk : in std_logic;
-- outbound to top level module
top_addr : out addr_t;
top_dout : in word_t;
top_din : out word_t;
top_size : out ctrl_memwidth_t;
top_wr : out ctrl_t);
end component;
component WriteBack is
port(
Link, JumpReg, JumpDir, MemToReg, TakeBranch : in ctrl_t;
pc_plus_4, branch_addr, jump_addr: in addr_t;
aluResult, memReadData, regReadData1 : in word_t;
regWriteData : out word_t;
new_pc : out addr_t);
end component;
-- control signals
signal Link, Branch, JumpReg, JumpDir, memToreg, TakeBranch, Shift, ALUSrc, MemSex : ctrl_t;
signal MemRead, MemWrite : ctrl_memwidth_t;
signal memReadData : word_t;
signal new_pc : addr_t;
signal pc_plus_4, jump_addr, branch_addr : addr_t;
signal instr : instruction_t;
signal zeroxed, sexed, aluResult: word_t;
signal aluop : alu_op_t;
signal cpuclk : std_logic := '0';
signal regclk : std_logic := '0';
signal halt_cpu : boolean := false;
signal cpurst : std_logic := '0';
signal regrst : std_logic := '0';
signal done : boolean := false;
constant ESC : Character := Character'val(27);
signal addr : addr_t;
signal din : word_t;
signal dout : word_t;
signal size : ctrl_memwidth_t;
signal wr : std_logic;
begin
regFile1: regFile
port map(
readreg1 => readreg1, readreg2 => readreg2,
writereg => writereg, writedata => regWriteData,
readData1 => regReadData1, readData2 => regReadData2,
clk => regclk, rst => regrst,
regWrite => regWrite
);
if1: InstructionFetch
generic map (PC_ADD => 4, CPI => 4, SINGLE_ADDRESS_SPACE => true)
port map(
clk => cpuclk,
rst => cpurst,
new_pc => new_pc,
pc_plus_4 => pc_plus_4,
instr => instr,
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr
);
mem_bus: mem port map (
addr => addr,
din => din,
dout => dout,
size => size,
wr => wr,
clk => cpuclk
);
id1: InstructionDecode
port map(instr => instr,
pc_plus_4 => pc_plus_4,
jump_addr => jump_addr,
regwrite => regwrite, link => link, jumpreg => jumpreg, jumpdirect => jumpdir, branch => Branch,
memread => memread, memwrite => memwrite,
memtoreg => memtoreg, memsex => memsex,
shift => shift, alusrc => aluSrc,
aluop => aluOp,
readreg1 => readReg1, readreg2 => readReg2, writeReg => writeReg,
zeroxed => zeroxed, sexed => sexed,
clk => cpuclk,
rst => cpurst
);
ex1: Execute
port map(
pc_plus_4 => pc_plus_4,
regReadData1 => regReadData1, regReadData2 => regReadData2,
branch_addr => branch_addr,
branch_in => Branch,
shift_in => shift, alusrc_in => ALUSrc,
aluop_in => ALUOp,
zeroxed => zeroxed, sexed => sexed,
takeBranch => takeBranch,
ALUResult => ALUResult,
clk => cpuclk,
rst => cpurst
);
ma1: memoryAccess
port map(
-- inbound
Address_in => AluResult,
WriteData_in => regReadData2,
ReadData_in => memReadData,
MemRead_in => memRead, MemWrite_in => memWrite,
MemSex_in => memSex,
clk => cpuclk,
-- outbound to top level module
top_addr => addr,
top_dout => dout,
top_din => din,
top_size => size,
top_wr => wr);
wb1: WriteBack
port map(
Link => Link,
JumpReg => JumpReg,
JumpDir => JumpDir,
MemToReg => MemToReg,
TakeBranch => TakeBranch,
pc_plus_4 => pc_plus_4,
branch_addr => branch_addr,
jump_addr => jump_addr,
aluResult => aluResult,
memReadData => memReadData,
regReadData1 => regReadData1,
regWriteData => regWriteData,
new_pc => new_pc);
test : process
begin
-- This halt_cpu thing doesn't work yet
--halt_cpu <= true;
--regrst <= '0';
--wait for 2 ns;
--regrst <= '1';
--wait for 2 ns;
--regrst <= '0';
--wait for 20 ns;
--readreg1 <= R1;
--wait for 2 ns;
--assert regReadData1 = ZERO report
-- ANSI_RED "Failed to reset. 0 /= " & to_hstring(regReadData1) & ANSI_NONE
--severity error;
--halt_cpu <= false;
cpurst <= '0';
wait for 2 ns;
cpurst <= '1';
wait for 2 ns;
cpurst <= '0';
wait for 55 ns;
readreg1 <= R1;
wait for 2 ns;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData1) & ANSI_NONE
severity error;
readreg1 <= R1;
readreg2 <= R2;
wait for 2 ns;
assert regReadData2 = X"0000_FBAD" report
ANSI_RED & "Failed to ori. 0xFBAD /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
assert regReadData1 = X"0000_F000" report
ANSI_RED & "Failed to ori. 0xF000 /= " & to_hstring(regReadData2) & ANSI_NONE
severity error;
done <= true;
wait;
end process;
clkproc: process
begin
regclk <= not regclk;
if not halt_cpu then
cpuclk <= not cpuclk;
end if;
wait for 1 ns;
if done then wait; end if;
end process;
end struct;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/io/addrdec.vhdl
|
1
|
1203
|
-- Address decoder
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.memory_map.all;
entity addrdec is
port(A : in addr_t;
cs : out memchipsel_t);
end addrdec;
architecture behav of addrdec is
begin
-- FIXME use a loop over the mmap array instead
cs <= mmap(0).chip_select when inside(A, mmap(0).base, mmap(0).size) else -- RAM
mmap(1).chip_select when inside(A, mmap(1).base, mmap(1).size) else -- ROM
mmap(2).chip_select when inside(A, mmap(2).base, mmap(2).size) else -- LEDs
mmap(3).chip_select when inside(A, mmap(3).base, mmap(3).size) else -- DIP-Switch
mmap(4).chip_select when inside(A, mmap(4).base, mmap(4).size) else -- Pushbuttons
mmap(5).chip_select when inside(A, mmap(5).base, mmap(5).size) else -- UART
mmap(6).chip_select when inside(A, mmap(6).base, mmap(6).size) else -- VRAM
mmap(7).chip_select when inside(A, mmap(7).base, mmap(7).size); -- Video configuration
-- We need dual-ported RAM for the framebuffer,
-- lest we've to deal with bus arbitration.
-- That's why the VRAM is separate from the RAM
end behav;
|
gpl-3.0
|
makestuff/dvr-connectors
|
fifo/vhdl/fifo_rtl.vhdl
|
1
|
4248
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of fifo is
-- Register file for storing FIFO contents
constant DEPTH_UBOUND : natural := 2**DEPTH-1;
constant WIDTH_UBOUND : natural := WIDTH-1;
type RegFileType is array(DEPTH_UBOUND downto 0) of std_logic_vector(WIDTH_UBOUND downto 0);
signal fifoData : RegFileType; -- := (others => (others => '0'));
signal fifoData_next : RegFileType;
-- Read & write pointers, with auto-wrap incremented versions
signal rdPtr : unsigned(DEPTH-1 downto 0) := (others => '0');
signal rdPtr_next : unsigned(DEPTH-1 downto 0);
signal rdPtr_inc : unsigned(DEPTH-1 downto 0);
signal wrPtr : unsigned(DEPTH-1 downto 0) := (others => '0');
signal wrPtr_next : unsigned(DEPTH-1 downto 0);
signal wrPtr_inc : unsigned(DEPTH-1 downto 0);
-- Full flag
signal isFull : std_logic := '0';
signal isFull_next : std_logic;
-- Signals to drive inputReady_out & outputValid_out
signal inputReady : std_logic;
signal outputValid : std_logic;
-- Signals that are asserted during the cycle before a write or read, respectively
signal isWriting : std_logic;
signal isReading : std_logic;
-- FIFO depth stuff
constant DEPTH_ZEROS : std_logic_vector(DEPTH-1 downto 0) := (others => '0');
constant FULL_DEPTH : std_logic_vector(DEPTH downto 0) := '1' & DEPTH_ZEROS;
constant EMPTY_DEPTH : std_logic_vector(DEPTH downto 0) := '0' & DEPTH_ZEROS;
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
fifoData <= (others => (others => '0'));
rdPtr <= (others => '0');
wrPtr <= (others => '0');
isFull <= '0';
else
fifoData <= fifoData_next;
rdPtr <= rdPtr_next;
wrPtr <= wrPtr_next;
isFull <= isFull_next;
end if;
end if;
end process;
-- Update reg file, write pointer & isFull flag
process(fifoData, wrPtr, inputData_in, isWriting)
begin
fifoData_next <= fifoData;
if ( isWriting = '1' ) then
fifoData_next(to_integer(wrPtr)) <= inputData_in;
end if;
end process;
-- The FIFO only has three outputs, inputReady_out, outputData_out and outputValid_out:
inputReady_out <= inputReady;
inputReady <=
'0' when isFull = '1' else
'1';
outputData_out <=
fifoData(to_integer(rdPtr)) when outputValid = '1'
else (others => 'X');
outputValid_out <= outputValid;
outputValid <=
'0' when rdPtr = wrPtr and isFull = '0' else
'1';
-- The isReading and isWriting signals make it easier to check whether we're in a cycle that
-- ends in a read and/or a write, respectively
isReading <=
'1' when outputValid = '1' and outputReady_in = '1' else
'0';
isWriting <=
'1' when inputValid_in = '1' and inputReady = '1' else
'0';
-- Infer pointer-increment adders:
rdPtr_inc <= rdPtr + 1;
wrPtr_inc <= wrPtr + 1;
-- Full when a write makes the two pointers coincide, without a read to balance it
isFull_next <=
'0' when isReading = '1' and rdPtr_inc /= wrPtr else
'1' when isWriting = '1' and wrPtr_inc = rdPtr else
isFull;
-- Pointer increments
rdPtr_next <=
rdPtr_inc when isReading = '1'
else rdPtr;
wrPtr_next <=
wrPtr_inc when isWriting = '1'
else wrPtr;
-- FIFO depth
depth_out <=
EMPTY_DEPTH when wrPtr = rdPtr and isFull = '0' else
FULL_DEPTH when wrPtr = rdPtr and isFull = '1' else
'0' & std_logic_vector(wrPtr - rdPtr) when wrPtr > rdPtr else
std_logic_vector(('1' & wrPtr) - ('0' & rdPtr));
end architecture;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/arch/regDstMux.vhdl
|
1
|
398
|
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity regDstMux is
port (
RegDst: in ctrl_t;
rt : in reg_t; --Instruction 20-16
rd : in reg_t; --Instruction 15-11
output : out reg_t
);
end regDstMux;
architecture behav of regDstMux is
begin
output <= rd when RegDst = '1' else rt;
end architecture behav;
|
gpl-3.0
|
makestuff/dvr-connectors
|
conv-40to8/vhdl/conv_40to8.vhdl
|
1
|
3295
|
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_40to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 40-bit data coming in
data40_in : in std_logic_vector(39 downto 0);
valid40_in : in std_logic;
ready40_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_40to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3,
S_WRITE4
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(31 downto 0) := (others => '0');
signal wip_next : std_logic_vector(31 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data40_in, valid40_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(31 downto 24);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3
when S_WRITE3 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE4;
end if;
-- Write byte 4 (LSB)
when S_WRITE4 =>
ready40_out <= '0'; -- not ready for data from 40-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready40_out <= ready8_in; -- ready for data from 40-bit side
data8_out <= data40_in(39 downto 32);
valid8_out <= valid40_in;
if ( valid40_in = '1' and ready8_in = '1' ) then
wip_next <= data40_in(31 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
gpl-3.0
|
a3f/r3k.vhdl
|
vhdl/io/dipswitch.vhdl
|
1
|
1073
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_dipswitch is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- dip switch
switch : in std_logic_vector(7 downto 0)
);
end mmio_dipswitch;
architecture mmio of mmio_dipswitch is
constant reading : std_logic := '0';
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk)
begin
if rising_edge(clk) and en = '1' and size /= "00" then
case wr is
when reading => zeroextend(data_out, switch);
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end;
|
gpl-3.0
|
makestuff/dvr-connectors
|
conv-8to16/vhdl/tb_unit/conv_8to16_tb.vhdl
|
1
|
3212
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_8to16_tb is
end entity;
architecture behavioural of conv_8to16_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
-- 16-bit interface signals
signal data16 : std_logic_vector(15 downto 0);
signal valid16 : std_logic;
signal ready16 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_8to16
port map(
clk_in => sysClk,
reset_in => '0',
data8_in => data8,
valid8_in => valid8,
ready8_out => ready8,
data16_out => data16,
valid16_out => valid16,
ready16_in => ready16
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data8 <= (others => 'Z');
valid8 <= '0';
ready16 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data8 <= to_4(inLine.all(1)) & to_4(inLine.all(2));
valid8 <= to_1(inLine.all(4));
ready16 <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(data16(15 downto 12)) & from_4(data16(11 downto 8)) & from_4(data16(7 downto 4)) & from_4(data16(3 downto 0)));
write(outLine, ' ');
write(outLine, valid16);
write(outLine, ' ');
write(outLine, ready8);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data8 <= (others => 'Z');
valid8 <= '0';
ready16 <= '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/RESOURCE_CUSTOM_A.vhd
|
1
|
9995
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
--type sequential32_in_type is record
-- op1 : std_logic_vector(32 downto 0); -- operand 1
-- op2 : std_logic_vector(32 downto 0); -- operand 2
-- flush : std_logic;
-- signed : std_logic;
-- start : std_logic;
--end record;
--type sequential32_out_type is record
-- ready : std_logic;
-- nready : std_logic;
-- icc : std_logic_vector(3 downto 0);
-- result : std_logic_vector(31 downto 0);
--end record;
entity RESOURCE_CUSTOM_A is
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end;
architecture rtl of RESOURCE_CUSTOM_A is
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal state : std_logic_vector(2 downto 0);
signal gated_clock : std_logic;
signal nIdle : std_logic;
begin
-------------------------------------------------------------------------
-- synthesis translate_off
process
begin
wait for 1 ns;
printmsg("(IMS) RESOURCE_CUSTOM_1 : ALLOCATION OK !");
wait;
end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
process(clk)
variable gated : std_logic;
begin
if clk'event and clk = '1' then
gated := '0';
--IF ( (inp.dInstr(31 downto 30) & inp.dInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE REGISTER SELECTION PIPELINE STAGE";
--gated := '1';
--END IF;
IF ( (inp.aInstr(31 downto 30) & inp.aInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE REGISTER SELECTION PIPELINE STAGE";
gated := '1';
END IF;
IF ( (inp.eInstr(31 downto 30) & inp.eInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE EXECUTION PIPELINE STAGE";
gated := '1';
END IF;
--IF ( (inp.mInstr(31 downto 30) & inp.mInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE MEMORY PIPELINE STAGE";
-- gated := '1';
--END IF;
--IF ( (inp.xInstr(31 downto 30) & inp.xInstr(24 downto 19)) = "10101111" ) THEN
-- REPORT "(PGDC) PGDC IS IN THE EXCEPTION PIPELINE STAGE";
--gated := '1';
--END IF;
-- synthesis translate_off
IF ( (nIdle = '0') AND (gated = '1') ) THEN
--printmsg( "(PGDC) ENABLING THE PGDC CLOCK GENERATION" );
ELSIF( (nIdle = '1') AND (gated = '0') ) THEN
--printmsg( "(PGDC) DISABLING THE PGDC CLOCK GENERATION" );
END IF;
-- synthesis translate_on
nIdle <= gated;
end if;
end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
gated_clock <= clk AND nIdle;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--process(inp.op1, inp.op2)
--begin
--At <= inp.op1(31 downto 0);
--Bt <= inp.op2(31 downto 0);
--if( nIdle = '1' )then
-- REPORT "(PGDC) (At, Bt) MEMORISATION PROCESS";
-- if ( (At(30) /= '-') AND (At(30) /= 'X') AND (At(30) /= 'U')) then
-- printmsg("(PGDC) =====> (At) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
-- end if;
-- if ( (Bt(30) /= '-') AND (Bt(30) /= 'X') AND (Bt(30) /= 'U')) then
-- printmsg("(PGDC) =====>(Bt) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
-- end if;
-- --printmsg("(PGDC) (At, Bt) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & " & " & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
--process(inp.start)
--begin
-- if (inp.start = '1') then
-- REPORT "(PGDC) (START) THE START SIGNAL BECOME UP";
-- else
-- REPORT "(PGDC) (START) THE START SIGNAL BECOME DOWN";
-- end if;
--end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- DESCRIPTION ORIGINALE QUI FONCTIONNE TRES TRES BIEN
-- reg : process(clk)
-- variable vready, vnready : std_logic;
-- begin
-- vready := '0';
-- vnready := '0';
-- if clk'event and clk = '1' then
-- if (rst = '0') then
-- state <= "000";
-- elsif (inp.flush = '1') then
-- state <= "000";
-- elsif (holdn = '0') then
-- state <= state;
-- else
-- case state is
--ON ATTEND LA COMMANDE DE START
-- when "000" =>
-- if (inp.start = '1') then
-- A <= inp.op1(31 downto 0);
-- B <= inp.op2(31 downto 0);
-- state <= "001";
-- else
-- state <= "000";
-- A <= A;
-- B <= B;
-- end if;
--ON COMMENCE LE CALCUL
-- when "001" =>
-- A <= inp.op1(31 downto 0);
-- B <= inp.op2(31 downto 0);
-- state <= "011";
--ON COMMENCE LE CALCUL
-- when "010" =>
-- if( SIGNED(A) > SIGNED(B) ) then
-- A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
-- else
-- B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
-- end if;
-- state <= "011";
--ON TEST LES DONNEES (FIN D'ITERATION)
-- when "011" =>
-- if(SIGNED(A) = SIGNED(B)) then
-- state <= "100";
-- vnready := '1';
-- elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
-- state <= "100";
-- vnready := '1';
-- elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
-- A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
-- state <= "100";
-- vnready := '1';
-- else
-- state <= "010";
-- end if;
-- when "100" =>
--ON INDIQUE QUE LE RESULTAT EST PRET
-- vready := '1';
--ON RETOURNE DANS L'ETAT INTIAL
-- state <= "000";
-- when others =>
-- state <= "000";
-- end case;
-- outp.ready <= vready;
-- outp.nready <= vnready;
-- end if; -- if reset
-- end if; -- if clock
-- end process;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
reg : process(clk, rst)
variable vready, vnready : std_logic;
begin
vready := '0';
vnready := '0';
if (rst = '0') then
state <= "000";
outp.ready <= vready;
outp.nready <= vnready;
elsif clk'event and clk = '1' then
if (inp.flush = '1') then
state <= "000";
elsif (holdn = '0') then
state <= state;
else
case state is
-- ON ATTEND LA COMMANDE DE START
when "000" =>
if (inp.start = '1') then
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "001";
--printmsg("(PGDC) THE START SIGNAL IS UP");
--if ( (inp.op1(30) /= '-') AND (inp.op1(30) /= 'X') AND (inp.op1(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--if ( (inp.op2(30) /= '-') AND (inp.op2(30) /= 'X') AND (inp.op2(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
--end if;
else
state <= "000";
A <= A;
B <= B;
end if;
-- ON COMMENCE LE CALCUL
when "001" =>
--printmsg("(PGDC) INPUT DATA READING");
--if ( (inp.op1(30) /= '-') AND (inp.op1(30) /= 'X') AND (inp.op1(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(inp.op1(31 downto 0),6) & ")");
--end if;
--if ( (inp.op2(30) /= '-') AND (inp.op2(30) /= 'X') AND (inp.op2(30) /= 'U')) then
-- printmsg("(PGDC) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(inp.op2(31 downto 0),6) & ")");
--end if;
A <= inp.op1(31 downto 0);
B <= inp.op2(31 downto 0);
state <= "011";
-- ON COMMENCE LE CALCUL
when "010" =>
if( SIGNED(A) > SIGNED(B) ) then
A <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
else
B <= STD_LOGIC_VECTOR(SIGNED(B) - SIGNED(A));
end if;
state <= "011";
-- ON TEST LES DONNEES (FIN D'ITERATION)
when "011" =>
if(SIGNED(A) = SIGNED(B)) then
state <= "100";
vnready := '1';
elsif( SIGNED(A) = TO_SIGNED(0,32) ) then
state <= "100";
vnready := '1';
elsif( SIGNED(B) = TO_SIGNED(0,32) ) then
A <= STD_LOGIC_VECTOR(TO_SIGNED(0,32));
state <= "100";
vnready := '1';
else
state <= "010";
end if;
when "100" =>
--printmsg("(PGDC) ===> COMPUTATION IS NOW FINISHED (" & to_int_str(A,6) & ")");
-- ON INDIQUE QUE LE RESULTAT EST PRET
vready := '1';
-- ON RETOURNE DANS L'ETAT INTIAL
state <= "000";
when others =>
state <= "000";
end case;
outp.ready <= vready;
outp.nready <= vnready;
end if; -- if reset
end if; -- if clock
end process;
-------------------------------------------------------------------------
outp.result <= A;
outp.icc <= "0000";
end;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_SUB.vhd
|
1
|
1667
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
entity Q16_8_SUB is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q16_8_SUB is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_SUB : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(16 downto 0);
VARIABLE OP2 : SIGNED(16 downto 0);
VARIABLE OP3 : SIGNED(16 downto 0);
begin
OP1 := SIGNED( INPUT_1(15) & INPUT_1(15 downto 0) );
OP2 := SIGNED( INPUT_2(15) & INPUT_2(15 downto 0) );
OP3 := OP1 - OP2;
if( OP3 > TO_SIGNED(32767, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED( 32767, 16));
elsif( OP3 < TO_SIGNED(-32768, 17) ) THEN
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR(TO_SIGNED(-32768, 16));
else
OUTPUT_1 <= "0000000000000000" & STD_LOGIC_VECTOR( OP3(15 downto 0) );
end if;
END PROCESS;
-------------------------------------------------------------------------
end;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/simulation/txt_util.vhd
|
1
|
12748
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
--procedure str_write(file out_file: TEXT;
-- new_string: in string) is
-- begin
--
-- for i in new_string'range loop
-- print(out_file, new_string(i));
-- if new_string(i) = LF then -- end of string
-- exit;
-- end if;
-- end loop;
--
--end str_write;
end txt_util;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/mem_ctrl.vhd
|
1
|
8120
|
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector( 3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := data_r;
-- BEGIN ENABLE_(LHU)
when MEM_READ16 =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
--if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
--else
-- data_read_var(31 downto 16) := ONES(31 downto 16);
--end if;
-- END ENABLE_(LHU)
-- BEGIN ENABLE_(LH)
when MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
--if mem_source = MEM_READ16 or data_read_var(15) = '0' then
if data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
-- END ENABLE_(LH)
-- BEGIN ENABLE_(LBU)
when MEM_READ8 =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
--if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
--else
-- data_read_var(31 downto 8) := ONES(31 downto 8);
--end if;
-- END ENABLE_(LBU)
-- BEGIN ENABLE_(LB)
when MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
--if mem_source = MEM_READ8 or data_read_var(7) = '0' then
if data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
-- END ENABLE_(LB)
-- BEGIN ENABLE_(SW,SWL)
when MEM_WRITE32 =>
data_write_var := data_write;
byte_we_var := "1111";
-- END ENABLE_(SW,SWL)
-- BEGIN ENABLE_(SH)
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_we_var := "1100";
else
byte_we_var := "0011";
end if;
-- END ENABLE_(SH)
-- BEGIN ENABLE_(SB)
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_we_var := "1000";
when "01" =>
byte_we_var := "0100";
when "10" =>
byte_we_var := "0010";
when others =>
byte_we_var := "0001";
end case;
-- END ENABLE_(SB)
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_we_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= data_r;
end if;
end if;
end if;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
address_next <= address_var;
byte_we_next <= byte_we_var;
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
end process; --data_proc
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/filtre/function_6.vhd
|
5
|
1045
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_6 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_6 is
begin
-------------------------------------------------------------------------
OUTPUT_1 <= std_logic_vector(signed(INPUT_1)+signed(INPUT_2));
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/tuto_plasma/function_2.vhd
|
1
|
1137
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_2 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_2 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
begin
if(INPUT_1 < INPUT_2) then
OUTPUT_1 <= INPUT_1;
else
OUTPUT_1 <= INPUT_2;
end if;
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter6/exercise6_8_dir/exercise6_8.vhd
|
1
|
1472
|
--!
--! @file: exercise6_8.vhd
--! @brief: Signal Generator
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity signal_generator is
--generic declarations
port (
clk: in std_logic; -- clk
x, y: out std_logic); --output
end entity signal_generator;
--------------------------------------
architecture circuit of signal_generator is
signal even: std_logic := '0';
begin
proc: process (clk)
begin
if (clk'event and clk = '1') then
if (even = '0') then
x <= clk;
y <= '0';
else
x <= '0';
y <= clk;
end if;
if (even = '0') then
even <= '1';
else
even <= '0';
end if;
end if;
end process proc;
end architecture circuit;
--------------------------------------
architecture arch of signal_generator is
--signals and declarations
begin
proc: process (clk)
variable a, b: std_logic;
begin
if (clk'event and clk = '1') then
a <= not a;
else if (clk'event and clk = '0') then
b <= not a;
end if;
x <= a and b;
y <= a nor b;
end process proc;
end architecture arch;
--------------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/coproc_4.vhd
|
2
|
1408
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter3/circuit_dontcares_dir/circuit_dontcares.vhd
|
1
|
524
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity circuit is
--generic declarations
port (
x: in std_logic_vector(1 downto 0) ;
y: out std_logic_vector(1 downto 0) );
end entity;
------------------------------
architecture circuit of circuit is
--signals and declarations
begin
y <= "00" when x = "00" else
"10" when x = "01" else
"01" when x = "10" else
"--";
end architecture;
------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/mandelbrot/function_3.vhd
|
1
|
1401
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.constants.all;
entity function_3 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_3 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(63 downto 0);
variable rTemp2 : SIGNED(63 downto 0);
variable rTemp3 : SIGNED(63 downto 0);
begin
rTemp1 := (signed(INPUT_1) * signed(INPUT_1));
rTemp2 := (signed(INPUT_2) * signed(INPUT_2));
rTemp3 := rTemp1+rTemp2;
OUTPUT_1 <= std_logic_vector(rTemp3(32+(FIXED-1) downto FIXED)); --x1²+y1²
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
src_vhd/Colorgen.vhd
|
2
|
74636
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Colorgen is
Port ( iters : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
itermax : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0);
color : out STD_LOGIC_VECTOR (bit_per_pixel-1 downto 0));
end Colorgen;
architecture Behavioral of Colorgen is -- TODO : Améliorer colorgen (comparaison OpenGL)
type rom_type is array (0 to ITER_MAX-1) of std_logic_vector (bit_per_pixel-1 downto 0);
constant color_scheme : rom_type := (
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000001",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000010",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000011",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000100",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
"000000000101",
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"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000",
"000000000000"
);
begin
process(iters, itermax)
begin
--color <= not iters;
if (iters = itermax) then
color<= (others=>'0');
else
color <= not color_scheme(to_integer(unsigned(iters)));
end if;
end process;end Behavioral;
--Cut and paste following lines into Shared.vhd.
-- constant ITER_MAX : integer := 4095;
-- constant ITER_RANGE : integer := 12;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/tuto_plasma/function_10.vhd
|
5
|
1336
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/ray_tracer_v3/function_10.vhd
|
5
|
1336
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_10 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_10 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(10, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/tuto_plasma/function_7.vhd
|
5
|
1334
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/plasma.vhd
|
1
|
24383
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB) - 0000 0000 0000
-- 0x10000000 - 0x100fffff External RAM (1MB) - 0001 0000 0000
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- 0x30000000 FIFO IN EMPTY
-- 0x30000010 FIFO OUT EMPTY
-- 0x30000020 FIFO IN VALID
-- 0x30000030 FIFO OUT VALID
-- 0x30000040 FIFO IN FULL
-- 0x30000050 FIFO IN FULL
-- 0x30000060 FIFO IN COUNTER
-- 0x30000070 FIFO OUT COUNTER
-- 0x30000080 FIFO IN READ DATA
-- 0x30000090 FIFO OUT WRITE DATA
-- 0x40000000 COPROCESSOR 1 (reset)
-- 0x40000010 COPROCESSOR 1 (input/output)
-- 0x40000030 COPROCESSOR 2 (reset)
-- 0x40000040 COPROCESSOR 2 (input/output)
-- 0x40000060 COPROCESSOR 3 (reset)
-- 0x40000070 COPROCESSOR 3 (input/output)
-- 0x40000090 COPROCESSOR 4 (reset)
-- 0x400000A0 COPROCESSOR 4 (input/output)
-- 0x80000000 DMA ENGINE (NOT WORKING YET)
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '0';
use_cache : std_logic := '0';
plasma_code : string
);
port(clk : in std_logic;
--clk_VGA : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
--data_write : out std_logic_vector(31 downto 0);
--data_read : in std_logic_vector(31 downto 0);
---mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
-- BLG START
fifo_1_out_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_read_en : OUT STD_LOGIC;
fifo_1_empty : IN STD_LOGIC;
fifo_2_in_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_1_write_en : OUT STD_LOGIC;
fifo_2_full : IN STD_LOGIC;
fifo_1_full : IN STD_LOGIC;
fifo_1_valid : IN STD_LOGIC;
fifo_2_empty : IN STD_LOGIC;
fifo_2_valid : IN STD_LOGIC;
fifo_1_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
fifo_2_compteur : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-- BLG END
--VGA_hs : out std_logic; -- horisontal vga syncr.
-- VGA_vs : out std_logic; -- vertical vga syncr.
data_enable :out std_logic;
ADDR : out std_logic_vector(16 downto 0);
data_out : out std_logic_vector(11 downto 0);
--VGA_green : out std_logic_vector(3 downto 0); -- green output
--VGA_blue : out std_logic_vector(3 downto 0); -- blue output
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal ppcie_rdata : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal enable_local_mem : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_boot_enable : std_logic;
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector( 3 downto 0);
signal ram_address : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r : std_logic_vector(31 downto 0);
signal ram_data_lm : std_logic_vector(31 downto 0);
signal dma_address : std_logic_vector(31 downto 0);
signal dma_byte_we : std_logic_vector( 3 downto 0);
signal dma_data_write : std_logic_vector(31 downto 0);
signal dma_data_read : std_logic_vector(31 downto 0);
signal dma_start : std_logic;
signal cop_1_reset : std_logic;
signal cop_1_valid : std_logic;
signal cop_1_output : std_logic_vector(31 downto 0);
signal cop_2_reset : std_logic;
signal cop_2_valid : std_logic;
signal cop_2_output : std_logic_vector(31 downto 0);
signal cop_3_reset : std_logic;
signal cop_3_valid : std_logic;
signal cop_3_output : std_logic_vector(31 downto 0);
signal cop_4_reset : std_logic;
signal cop_4_valid : std_logic;
signal cop_4_output : std_logic_vector(31 downto 0);
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
COMPONENT memory_64k
Port ( clk : in STD_LOGIC;
addr_in : in STD_LOGIC_VECTOR (31 downto 2);
data_in : in STD_LOGIC_VECTOR (31 downto 0);
enable : in STD_LOGIC;
we_select : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (31 downto 0));
end COMPONENT;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause;-- or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) --UART busy
-- or cache_miss --Cache wait
-- or (cpu_address(31) and not cache_hit and mem_busy); --DDR or flash
or (eth_pause); -- DMA ENGINE FREEZE ALL (BLG)
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
--
-- ON GENERE LES SIGNAUX DE COMMANDE EN DIRECTION DU PORT PCIe
--
--fifo_1_read_en <= '1' when ((cpu_address(31 downto 28) = "0011") AND (cpu_address(7 downto 4) = "1000") ) else '0';
--fifo_1_write_en <= '1' when ((cpu_address(31 downto 28) = "0011") AND (cpu_address(7 downto 4) = "1001") AND (write_enable = '1')) else '0';
fifo_1_read_en <= '1' when (cpu_address = x"30000080") AND (cpu_pause = '0') else '0';
fifo_1_write_en <= '1' when (cpu_address = x"30000090") AND (cpu_pause = '0') AND(write_enable = '1') else '0';
cop_1_reset <= '1' when (cpu_address = x"40000000") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_1_valid <= '1' when (cpu_address = x"40000004") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_2_reset <= '1' when (cpu_address = x"40000030") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_2_valid <= '1' when (cpu_address = x"40000034") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_3_reset <= '1' when (cpu_address = x"40000060") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_3_valid <= '1' when (cpu_address = x"40000064") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_4_reset <= '1' when (cpu_address = x"40000090") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
cop_4_valid <= '1' when (cpu_address = x"40000094") AND (cpu_pause = '0') AND (write_enable = '1') else '0';
-- assert cop_4_valid /= '1' severity failure;
--
-- ON LIT/ECRIT DANS LA MEMOIRE LOCALE UNIQUEMENT LORSQUE LE BUS
-- D'ADRESSE (MSB) = "001". SINON ON ADRESSE UN AUTRE PERIPHERIQUE
--
--dram_procr: process(clk)
--begin
-- if rising_edge(clk) then
-- ppcie_rdata <= pcie_rdata;
-- end if;
--end process;
--
-- INTERNAL RAM MEMORY (64ko)
--
-- enable_local_mem <= '1' when (cpu_address(31 downto 28) = "0001") else '0';
-- enable_local_mem <= '1' when (ram_address(31 downto 28) = "0001") else '0';
local_memory: memory_64k
port map (
clk => clk,
addr_in => ram_address, --cpu_data_r,
data_in => ram_data_w,
enable => enable_local_mem,
we_select => ram_byte_we,
data_out => ram_data_lm
);
--
--
--
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
--
--
--
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
--
--
--
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= (not eth_pause and cache_miss and not cache_checking);
--
--
--
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w, ram_data_lm,
fifo_1_empty, fifo_2_empty, fifo_1_full, fifo_2_full,
fifo_1_valid, fifo_2_valid, fifo_1_compteur, fifo_2_compteur, fifo_1_out_data, cop_1_output)
begin
case cpu_address(30 downto 28) is
-- ON LIT LES DONNEES DE LA MEMOIRE INTERNE
when "000" => --internal ROM
cpu_data_r <= ram_data_r;
-- ON LIT LES DONNEES DE LA MEMOIRE EXTERNE (LOCAL RAM)
when "001" => --external (local) RAM
--if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
--else
--cpu_data_r <= data_read; --DDR
--end if;
cpu_data_r <= ram_data_lm;
-- ON LIT LES DONNEES DES PERIPHERIQUES MISC.
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others => -- ce n'est pas pr\E9vu...
cpu_data_r <= x"FFFFFFFF";
end case;
-- ON LIT LES DONNEES EN PROVENANCE DU PCIe 0x3....XX
when "011" =>
case cpu_address(7 downto 4) is
when "0000" => cpu_data_r <= ZERO(31 downto 1) & fifo_1_empty;
when "0001" => cpu_data_r <= ZERO(31 downto 1) & fifo_2_empty;
when "0010" => cpu_data_r <= ZERO(31 downto 1) & fifo_1_full;
when "0011" => cpu_data_r <= ZERO(31 downto 1) & fifo_2_full;
when "0100" => cpu_data_r <= ZERO(31 downto 1) & fifo_1_valid;
when "0101" => cpu_data_r <= ZERO(31 downto 1) & fifo_2_valid;
when "0110" => cpu_data_r <= fifo_1_compteur;
when "0111" => cpu_data_r <= fifo_2_compteur;
when "1000" => cpu_data_r <= fifo_1_out_data;
when others => -- ce n'est pas pr\E9vu...
cpu_data_r <= x"FFFFFFFF";
end case;
--
-- LECTURE DES RESULTATS DES COPROCESSEURS
--
when "100" =>
case cpu_address(7 downto 0) is
when "00000100" => cpu_data_r <= cop_1_output; -- COPROCESSOR 1 (OUTPUT)
when "00110100" => cpu_data_r <= cop_2_output; -- COPROCESSOR 2 (OUTPUT)
when "01100100" => cpu_data_r <= cop_3_output; -- COPROCESSOR 3 (OUTPUT)
when "10010100" => cpu_data_r <= cop_4_output; -- COPROCESSOR 4 (OUTPUT)
when others => cpu_data_r <= x"FFFFFFFF";
end case;
--when "011" => --flash
-- cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO(31 downto 8) & x"FF";
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
end if;
end if;
end if;
counter_reg <= bv_inc(counter_reg);
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w,
dma_address,
dma_byte_we, eth_pause,
dma_data_write,
dma_start, eth_pause)
begin
if eth_pause = '1' then --Check if cache hit or write through
if dma_address(31 downto 28) = "0000" then
ram_boot_enable <= '1';
else
ram_boot_enable <= '0';
end if;
if dma_address(31 downto 28) = "0001" then
enable_local_mem <= '1';
else
enable_local_mem <= '0';
end if;
ram_address <= dma_address(31 downto 2); -- adr from ram
ram_byte_we <= dma_byte_we;
ram_data_w <= dma_data_write;
else --Normal non-cache access
if address_next(31 downto 28) = "0000" then
ram_boot_enable <= '1';
else
ram_boot_enable <= '0';
end if;
if address_next(31 downto 28) = "0001" then
enable_local_mem <= '1';
else
enable_local_mem <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
--
-- RAM DATA CONTROLLER
--
--ram_boot_enable <= '1' WHEN (ram_enable = '1') AND eth_pause = '0' ELSE '0';
u2_boot: ram
generic map (memory_type => memory_type,
plasma_code => plasma_code)
port map (
clk => clk,
enable => ram_boot_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
-- ON RELIT L'ENTREE DU PCIe (port de sortie) AU BUS DE DONNEE DU PROCESSEUR
-- PLASMA
fifo_2_in_data <= cpu_data_w;
--
-- UART CONTROLLER CAN BE REMOVED (FOR ASIC DESIGN)
--
uart_gen: if eUart = '1' generate
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail
);
end generate;
uart_gen2: if eUart = '0' generate
data_read_uart <= "00000000";
uart_write_busy <= '0';
uart_data_avail <= '0';
end generate;
--
-- ETHERNET CONTROLLER CAN BE REMOVED (FOR ASIC DESIGN)
--
-- dma_gen: if ethernet = '2' generate
-- address <= cpu_address(31 downto 2);
-- byte_we <= cpu_byte_we;
-- data_write <= cpu_data_w;
-- eth_pause <= '0';
-- irq_eth_rec <= '0';
-- irq_eth_send <= '0';
-- gpio0_out(28 downto 24) <= ZERO(28 downto 24);
-- end generate;
-- dma_gen2: if ethernet = '1' generate
-- u4_eth: eth_dma
-- port map(
-- clk => clk,
-- reset => reset,
-- enable_eth => gpio0_reg(24),
-- select_eth => enable_eth,
-- rec_isr => irq_eth_rec,
-- send_isr => irq_eth_send,
--
-- address => address, --to DDR
-- byte_we => byte_we,
-- data_write => data_write,
-- data_read => data_read,
-- pause_in => eth_pause_in,
--
-- mem_address => cpu_address(31 downto 2), --from CPU
-- mem_byte_we => cpu_byte_we,
-- data_w => cpu_data_w,
-- pause_out => eth_pause,
--
-- E_RX_CLK => gpioA_in(20),
-- E_RX_DV => gpioA_in(19),
-- E_RXD => gpioA_in(18 downto 15),
-- E_TX_CLK => gpioA_in(14),
-- E_TX_EN => gpio0_out(28),
-- E_TXD => gpio0_out(27 downto 24));
-- end generate;
dma_start <= '1' when ((cpu_address(31 downto 28) = "1000") and (cpu_byte_we = "1111")) else '0';
------------------------------------------------------------------------------------------------------
--
--
--
--
--
------------------------------------------------------------------------------------------------------
dma_input_mux_proc: process(clk, reset, dma_address, enable_misc,
ram_data_r, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w, ram_data_lm,
fifo_1_empty, fifo_2_empty, fifo_1_full, fifo_2_full,
fifo_1_valid, fifo_2_valid, fifo_1_compteur, fifo_2_compteur, fifo_1_out_data)
begin
case dma_address(30 downto 28) is
when "000" => --internal ROM
dma_data_read <= ram_data_r;
when "001" => --external (local) RAM
dma_data_read <= ram_data_lm;
when "010" => --misc
case dma_address(6 downto 4) is
when "000" => dma_data_read <= ZERO(31 downto 8) & data_read_uart;
when "001" => dma_data_read <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => dma_data_read <= ZERO(31 downto 8) & irq_status;
when "011" => dma_data_read <= gpio0_reg;
when "101" => dma_data_read <= gpioA_in;
when "110" => dma_data_read <= counter_reg;
when others => dma_data_read <= x"FFFFFFFF";
end case;
when "011" =>
case dma_address(7 downto 4) is
when "0000" => dma_data_read <= ZERO(31 downto 1) & fifo_1_empty;
when "0001" => dma_data_read <= ZERO(31 downto 1) & fifo_2_empty;
when "0010" => dma_data_read <= ZERO(31 downto 1) & fifo_1_full;
when "0011" => dma_data_read <= ZERO(31 downto 1) & fifo_2_full;
when "0100" => dma_data_read <= ZERO(31 downto 1) & fifo_1_valid;
when "0101" => dma_data_read <= ZERO(31 downto 1) & fifo_2_valid;
when "0110" => dma_data_read <= fifo_1_compteur;
when "0111" => dma_data_read <= fifo_2_compteur;
when "1000" => dma_data_read <= fifo_1_out_data;
when others => dma_data_read <= x"FFFFFFFF";
end case;
when others =>
dma_data_read <= ZERO(31 downto 8) & x"FF";
end case;
end process;
u4_dma: entity WORK.dma_engine
port map(
clk => clk,
reset => reset,
start_dma => dma_start,
--
address => dma_address, -- adr from ram
byte_we => dma_byte_we,
data_write => dma_data_write,
data_read => dma_data_read,
--
mem_address => cpu_address, -- adr from cpu
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause
);
------------------------------------------------------------------------------------------------------
--
--
--
--
--
------------------------------------------------------------------------------------------------------
u5a_coproc: entity WORK.coproc_1 port map(
clock => clk,
reset => cop_1_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_1_valid,
OUTPUT_1 => cop_1_output
);
u5b_coproc: entity WORK.coproc_2 port map(
clock => clk,
reset => cop_2_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_2_valid,
OUTPUT_1 => cop_2_output
);
u5c_coproc: entity WORK.coproc_3 port map(
clock => clk,
reset => cop_3_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_3_valid,
OUTPUT_1 => cop_3_output
);
u5d_coproc: entity WORK.coproc_4
port map(
clock => clk,
--clock_VGA => clk_VGA,
reset => cop_4_reset,
INPUT_1 => cpu_data_w,
INPUT_1_valid => cop_4_valid,
OUTPUT_1 => cop_4_output,
data_out => data_out,
data_write => data_enable,
ADDR => ADDR
-- VGA_hs => VGA_hs,
-- VGA_vs => VGA_vs,
--iter => iter
--VGA_green => VGA_green,
--VGA_blue => VGA_blue
);
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/mandelbrot/function_18.vhd
|
5
|
3027
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_18 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_18 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/tuto_plasma/function_18.vhd
|
5
|
3027
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_18 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_18 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter11/example3_dir/testbench/counter_tb.vhd
|
1
|
2135
|
--!
--! Copyright (C) 2010 - 2013 Creonic GmbH
--!
--! @file: counter_tb.vhd
--! @brief: tb of counter
--! @author: Antonio Gutierrez
--! @date: 2014-05-23
--!
--!
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------
entity counter_tb is
generic (PERIOD: time := 40 ns;
PD: time := 3 ns);
end entity counter_tb;
--------------------------------------------------------
architecture circuit of counter_tb is
--------------------------------------------------------
-- component declaration
--------------------------------------------------------
component counter is
port (
clk, rst: in std_logic;
output: out natural range 0 to 9);
end component counter;
--------------------------------------------------------
-- signal declaration
--------------------------------------------------------
signal clk_tb: std_logic := '0';
signal rst_tb: std_logic := '1';
signal output_tb: natural range 0 to 9 := 0;
begin
--------------------------------------------------------
-- component instantiation
--------------------------------------------------------
dut: counter port map (
clk => clk_tb,
rst => rst_tb,
output => output_tb
);
--------------------------------------------------------
-- stimuli generation
--------------------------------------------------------
-- rst
process
begin
rst_tb <= '1';
wait for PERIOD;
rst_tb <= '0';
wait;
end process;
-- clk
clk_tb <= not clk_tb after PERIOD / 2;
--------------------------------------------------------------------------------------
-- stop simulation
--------------------------------------------------------------------------------------
process
begin
wait for PERIOD * 10;
assert false
report "simulation end"
severity failure;
end process;
end architecture circuit;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter8/example8_4_dir/example8_4.vhd
|
1
|
1616
|
--!
--! @file: example8_4.vhd
--! @brief: Shift register with Component and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_components.all;
--------------------------------------
entity shift_register is
generic (M: positive := 4; -- num. of stages
N: positive := 8); -- bits per stage
port (
clk, load: in std_logic;
x: in std_logic_vector(N-1 downto 0);
d: in twoD(0 to M-1, N-1 downto 0);
y: out std_logic_vector(N-1 downto 0));
end entity shift_register;
--------------------------------------
architecture circuit of shift_register is
signal u: twoD(0 to M, N-1 downto 0);
signal v: twoD(0 to M-1, N-1 downto 0);
begin
-- transfer of x -> u and u -> y
gen1: for i in N-1 downto 0 generate
u(0,i) <= x(i); -- mapping input of entity to input of first stage
y(i) <= u(M, i); -- mapping the output of the last stage to the output of entity
end generate gen1;
-- update internal stages
gen2: for i in 0 to M-1 generate
gen3: for j in N-1 downto 0 generate
mux1: mux port map (
a => u(i, j),
b => d(i, j),
sel => load,
x => v(i, j)
);
dff1: flipflop port map (
d => v(i,j),
clk => clk,
q => u(i + 1, j)
);
end generate gen3;
end generate gen2;
end architecture circuit;
|
gpl-3.0
|
lugnitdgp/codecracker
|
assets/js/ace-builds/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter3/multiplexer_1dx1d_port_dir/multiplexer_1dx1d_port.vhd
|
1
|
386
|
use work.my_data_types.all;
------------------------------
entity mux is
--generic declarations
port (
x: in oneDoneD ;
sel: in integer range 0 to 3;
y: out bit_vector(7 downto 0) ;);
end entity;
------------------------------
architecture circuit of mux is
--signals and declarations
begin
y <= x(sel);
end architecture;
------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/txt_util.vhd
|
1
|
14512
|
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/TRIGO/COSINUS_SINUS_32b.vhd
|
1
|
30141
|
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Cordic Top --
-- --
-- Simple SIN/COS Cordic example --
-- 32 bits fixed format Sign,2^0, 2^-1,2^-2 etc. --
-- angle input +/-0.5phi --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity COSINUS_SINUS_32b is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
angle : in std_logic_vector(31 downto 0); -- input radian
sin : out std_logic_vector(31 downto 0); -- THIS OUTPUT ¨PROVIDES THE SINUS RESULT
cos : out std_logic_vector(31 downto 0);
start : in std_logic;
done : out std_logic);
end COSINUS_SINUS_32b;
architecture synthesis of COSINUS_SINUS_32b is
constant xinit_c : std_logic_vector(31 downto 0):=X"26dd3b44";
constant yinit_c : std_logic_vector(31 downto 0):=X"00000000";
component addsub is
port(abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end component;
component shiftn is
port(ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end component;
component atan32 is --ARCTAN(x) lut
port (ZA : in Std_Logic_Vector(4 downto 0);
ZData : out Std_Logic_Vector(31 downto 0));
end component;
component fsm is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
start : in std_logic;
cnt : in std_logic_vector(4 downto 0);
init : out std_logic;
load : out std_logic;
done : out std_logic);
end component;
signal cnt_s : std_logic_vector(4 downto 0); -- bit counter, 2^5
signal newx_s : std_logic_vector(31 downto 0);
signal newy_s : std_logic_vector(31 downto 0);
signal newz_s : std_logic_vector(31 downto 0);
signal xreg_s : std_logic_vector(31 downto 0);
signal yreg_s : std_logic_vector(31 downto 0);
signal zreg_s : std_logic_vector(31 downto 0);
signal sxreg_s: std_logic_vector(31 downto 0);
signal syreg_s: std_logic_vector(31 downto 0);
signal atan_s : std_logic_vector(31 downto 0); -- arctan LUT
signal init_s : std_logic;
signal load_s : std_logic;
signal as_s : std_logic;
signal nas_s : std_logic;
begin
SHIFT1: shiftn port map (xreg_s,sxreg_s,cnt_s);
SHIFT2: shiftn port map (yreg_s,syreg_s,cnt_s);
nas_s <= not as_s;
ADD1 : addsub port map (xreg_s,syreg_s,newx_s,as_s); -- xreg
ADD2 : addsub port map (yreg_s,sxreg_s,newy_s,nas_s); -- yreg
LUT : atan32 port map(cnt_s,atan_s);
ADD3 : addsub port map (zreg_s,atan_s(31 downto 0),newz_s,as_s); -- zreg
FSM1 : fsm port map (clk,reset,start,cnt_s,init_s,load_s,done);
-- COS(X) Register
process (clk,newx_s)
begin
if (rising_edge(clk)) then
if init_s='1' then xreg_s(31 downto 0) <= xinit_c; -- fails in vh2sc xinit_c(31 downto 0); -- 0.607
elsif load_s='1' then xreg_s <= newx_s;
end if;
end if;
end process;
-- SIN(Y) Register
process (clk,newy_s)
begin
if (rising_edge(clk)) then
if init_s='1' then yreg_s <= yinit_c; -- 0.0000 fails in vh2sc yinit_c(31 downto 0)
elsif load_s='1' then yreg_s <= newy_s;
end if;
end if;
end process;
-- Z Register
process (clk,newz_s,angle)
begin
if (rising_edge(clk)) then
if init_s='1' then zreg_s <= angle; -- x
elsif load_s='1' then zreg_s <= newz_s;
end if;
end if;
end process;
as_s <= zreg_s(31); -- MSB=Sign bit
process (clk,load_s,init_s) -- bit counter
begin
if (rising_edge(clk)) then
if init_s='1' then cnt_s<=(others=> '0');
elsif (load_s='1') then cnt_s <= cnt_s + '1';
end if;
end if;
end process;
sin <= yreg_s;
cos <= xreg_s;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Adder/Subtracter --
-- no overflow. --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port (abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end addsub;
architecture synthesis of addsub is
begin
process(as,abus,bbus)
begin
if as='1' then
obus <= abus + bbus;
else
obus <= abus - bbus;
end if;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity atan32 is
port ( za : in std_logic_vector(4 downto 0);
zdata : out std_logic_vector(31 downto 0));
end atan32;
Architecture synthesis of atan32 Is
Begin
process(ZA)
begin
Case ZA is
when "00000" => ZData <= X"3243f6a8";
when "00001" => ZData <= X"1dac6705";
when "00010" => ZData <= X"0fadbafc";
when "00011" => ZData <= X"07f56ea6";
when "00100" => ZData <= X"03feab76";
when "00101" => ZData <= X"01ffd55b";
when "00110" => ZData <= X"00fffaaa";
when "00111" => ZData <= X"007fff55";
when "01000" => ZData <= X"003fffea";
when "01001" => ZData <= X"001ffffd";
when "01010" => ZData <= X"000fffff";
when "01011" => ZData <= X"0007ffff";
when "01100" => ZData <= X"0003ffff";
when "01101" => ZData <= X"0001ffff";
when "01110" => ZData <= X"0000ffff";
when "01111" => ZData <= X"00007fff";
when "10000" => ZData <= X"00003fff";
when "10001" => ZData <= X"00001fff";
when "10010" => ZData <= X"00000fff";
when "10011" => ZData <= X"000007ff";
when "10100" => ZData <= X"000003ff";
when "10101" => ZData <= X"000001ff";
when "10110" => ZData <= X"000000ff";
when "10111" => ZData <= X"0000007f";
when "11000" => ZData <= X"0000003f";
when "11001" => ZData <= X"0000001f";
when "11010" => ZData <= X"0000000f";
when "11011" => ZData <= X"00000007";
when "11100" => ZData <= X"00000003";
when "11101" => ZData <= X"00000001";
when "11110" => ZData <= X"00000000";
when "11111" => ZData <= X"00000000";
When others => ZData <= "--------------------------------";
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fsm IS
PORT(
clk : IN std_logic;
reset : IN std_logic; -- Active low reset
start : IN std_logic;
cnt : IN std_logic_vector (4 DOWNTO 0);
init : OUT std_logic;
load : OUT std_logic;
done : OUT std_logic);
END fsm ;
architecture synthesis of fsm is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
begin
Process (clk,reset) -- Process to create current state variables
begin
if (reset='0') then -- Reset State
state <= s0;
elsif (rising_edge(clk)) then
state <= nextstate; -- Set Current state
end if;
end process;
process(state,start,cnt)
begin
case state is
when s0 => -- Step 1 load regs
if start='1' then nextstate <= s1;
else nextstate <= s0; -- Wait for start signal
end if;
when s1 => -- latch result register
if cnt="11111" then nextstate <= s2; -- done
else nextstate <= s1; -- wait
end if;
when s2 =>
if start='0' then nextstate <= s0;
else nextstate <= s2; -- Wait for start signal
end if;
when others => nextstate <= s0;
end case;
end process;
process(state)
begin
case state is
when s0 =>done <= '0'; init <= '1'; load <= '0';
when s1 =>done <= '0'; init <= '0'; load <= '1';
when s2 =>done <= '1'; init <= '0'; load <= '0';
when others => done <= '-'; init <= '-'; load <= '-';
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shiftn is
port (ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end shiftn;
architecture synthesis of shiftn is
begin
process(n,ibus)
begin
case n is
when "00000" => obus <= ibus(31)&ibus(30 downto 0); -- ibus
when "00001" => obus <= ibus(31)&ibus(31)&ibus(30 downto 1);
when "00010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 2);
when "00011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 3);
when "00100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 4);
when "00101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 5);
when "00110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 6);
when "00111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 7);
when "01000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 8);
when "01001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 9);
when "01010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 10);
when "01011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 11);
when "01100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 12);
when "01101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 13);
when "01110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 14);
when "01111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 15);
when "10000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 16);
when "10001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 17);
when "10010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 18);
when "10011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 19);
when "10100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 20);
when "10101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 21);
when "10110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 22);
when "10111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 23);
when "11000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 24);
when "11001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 25);
when "11010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 26);
when "11011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 27);
when "11100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 28);
when "11101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 29);
when "11110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30);
when others => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31);
end case;
end process;
end synthesis;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/MAXIMUM_MINIMUM_32b.vhd
|
1
|
1788
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:19:12 02/17/2011
-- Design Name:
-- Module Name: MINIMUM_MAXIMUM_32b - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MINIMUM_MAXIMUM_32b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
FONCTION : in STD_LOGIC_VECTOR( 1 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end MINIMUM_MAXIMUM_32b;
architecture rtl of MINIMUM_MAXIMUM_32b is
begin
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
wait for 1 ns;
REPORT "(IMS) MINIMUM RESOURCE : ALLOCATION OK !";
wait;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2, FONCTION)
variable decision : std_logic;
begin
if( SIGNED(INPUT_1) < SIGNED(INPUT_2) ) then
decision := '1';
else
decision := '0';
end if;
-- SI LE BIT DE POIDS FAIBLE = 1 CE SIGNIFIE QUE L'ON
-- VEUT CALCULER LE MINIMUM DES 2 NOMBRES
decision := decision xor FONCTION(1);
if( decision = '1' ) then
OUTPUT_1 <= INPUT_1;
else
OUTPUT_1 <= INPUT_2;
end if;
end process;
-------------------------------------------------------------------------
end;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/filtre/function_12.vhd
|
5
|
1336
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_12 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_12 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(12, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter7/exercise7_13_dir/exercise7_13.vhd
|
1
|
806
|
--!
--! @file: exercise7_12.vhd
--! @brief: generic nand with concurrent code
--! @author: Antonio Gutierrez
--! @date: 2013-10-29
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity generic_and is
generic (N: integer := 5);
port (
x: in std_logic_vector(N-1 downto 0);
y: out std_logic);
end entity generic_and;
--------------------------------------
architecture circuit of generic_and is
type matrix is array (0 to N-1) of std_logic;
signal temp: matrix;
begin
temp(0) <= x(0);
gen: for i in 1 to N-1 generate
temp(i) <= temp(i-1) and x(i);
end generate gen;
y <= not temp(N-1);
end architecture circuit;
--------------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/LDPC/Q16_8_IndexLUT.vhd
|
1
|
45086
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_IndexLUT is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture ROM of Q16_8_IndexLUT is
type rom_type is array (0 to 1824-1) of UNSIGNED (11 downto 0);
signal ROM : rom_type:= (
TO_UNSIGNED(75, 12), TO_UNSIGNED(618, 12),
TO_UNSIGNED(732, 12), TO_UNSIGNED(1425, 12),
TO_UNSIGNED(1500, 12), TO_UNSIGNED(1683, 12),
TO_UNSIGNED(84, 12), TO_UNSIGNED(621, 12),
TO_UNSIGNED(738, 12), TO_UNSIGNED(1428, 12),
TO_UNSIGNED(1506, 12), TO_UNSIGNED(1614, 12),
TO_UNSIGNED(86, 12), TO_UNSIGNED(624, 12),
TO_UNSIGNED(744, 12), TO_UNSIGNED(1437, 12),
TO_UNSIGNED(1488, 12), TO_UNSIGNED(1819, 12),
TO_UNSIGNED(12, 12), TO_UNSIGNED(88, 12),
TO_UNSIGNED(627, 12), TO_UNSIGNED(750, 12),
TO_UNSIGNED(1440, 12), TO_UNSIGNED(1512, 12),
TO_UNSIGNED(15, 12), TO_UNSIGNED(90, 12),
TO_UNSIGNED(630, 12), TO_UNSIGNED(756, 12),
TO_UNSIGNED(1443, 12), TO_UNSIGNED(1524, 12),
TO_UNSIGNED(18, 12), TO_UNSIGNED(92, 12),
TO_UNSIGNED(633, 12), TO_UNSIGNED(762, 12),
TO_UNSIGNED(1446, 12), TO_UNSIGNED(1518, 12),
TO_UNSIGNED(21, 12), TO_UNSIGNED(94, 12),
TO_UNSIGNED(636, 12), TO_UNSIGNED(768, 12),
TO_UNSIGNED(1449, 12), TO_UNSIGNED(1542, 12),
TO_UNSIGNED(24, 12), TO_UNSIGNED(96, 12),
TO_UNSIGNED(639, 12), TO_UNSIGNED(774, 12),
TO_UNSIGNED(1452, 12), TO_UNSIGNED(1548, 12),
TO_UNSIGNED(27, 12), TO_UNSIGNED(98, 12),
TO_UNSIGNED(642, 12), TO_UNSIGNED(780, 12),
TO_UNSIGNED(1455, 12), TO_UNSIGNED(1530, 12),
TO_UNSIGNED(30, 12), TO_UNSIGNED(100, 12),
TO_UNSIGNED(645, 12), TO_UNSIGNED(786, 12),
TO_UNSIGNED(1461, 12), TO_UNSIGNED(1536, 12),
TO_UNSIGNED(33, 12), TO_UNSIGNED(102, 12),
TO_UNSIGNED(648, 12), TO_UNSIGNED(792, 12),
TO_UNSIGNED(1458, 12), TO_UNSIGNED(1554, 12),
TO_UNSIGNED(36, 12), TO_UNSIGNED(104, 12),
TO_UNSIGNED(651, 12), TO_UNSIGNED(798, 12),
TO_UNSIGNED(1485, 12), TO_UNSIGNED(1560, 12),
TO_UNSIGNED(39, 12), TO_UNSIGNED(106, 12),
TO_UNSIGNED(654, 12), TO_UNSIGNED(804, 12),
TO_UNSIGNED(1572, 12), TO_UNSIGNED(1617, 12),
TO_UNSIGNED(42, 12), TO_UNSIGNED(108, 12),
TO_UNSIGNED(657, 12), TO_UNSIGNED(810, 12),
TO_UNSIGNED(1398, 12), TO_UNSIGNED(1566, 12),
TO_UNSIGNED(45, 12), TO_UNSIGNED(110, 12),
TO_UNSIGNED(660, 12), TO_UNSIGNED(816, 12),
TO_UNSIGNED(1401, 12), TO_UNSIGNED(1584, 12),
TO_UNSIGNED(48, 12), TO_UNSIGNED(112, 12),
TO_UNSIGNED(663, 12), TO_UNSIGNED(822, 12),
TO_UNSIGNED(1404, 12), TO_UNSIGNED(1578, 12),
TO_UNSIGNED(51, 12), TO_UNSIGNED(114, 12),
TO_UNSIGNED(666, 12), TO_UNSIGNED(828, 12),
TO_UNSIGNED(1413, 12), TO_UNSIGNED(1596, 12),
TO_UNSIGNED(54, 12), TO_UNSIGNED(116, 12),
TO_UNSIGNED(669, 12), TO_UNSIGNED(690, 12),
TO_UNSIGNED(1416, 12), TO_UNSIGNED(1602, 12),
TO_UNSIGNED(57, 12), TO_UNSIGNED(118, 12),
TO_UNSIGNED(672, 12), TO_UNSIGNED(696, 12),
TO_UNSIGNED(1419, 12), TO_UNSIGNED(1590, 12),
TO_UNSIGNED(0, 12), TO_UNSIGNED(60, 12),
TO_UNSIGNED(120, 12), TO_UNSIGNED(675, 12),
TO_UNSIGNED(702, 12), TO_UNSIGNED(1407, 12),
TO_UNSIGNED(63, 12), TO_UNSIGNED(122, 12),
TO_UNSIGNED(678, 12), TO_UNSIGNED(708, 12),
TO_UNSIGNED(1410, 12), TO_UNSIGNED(1476, 12),
TO_UNSIGNED(66, 12), TO_UNSIGNED(124, 12),
TO_UNSIGNED(681, 12), TO_UNSIGNED(714, 12),
TO_UNSIGNED(1434, 12), TO_UNSIGNED(1464, 12),
TO_UNSIGNED(69, 12), TO_UNSIGNED(126, 12),
TO_UNSIGNED(684, 12), TO_UNSIGNED(720, 12),
TO_UNSIGNED(1431, 12), TO_UNSIGNED(1470, 12),
TO_UNSIGNED(72, 12), TO_UNSIGNED(128, 12),
TO_UNSIGNED(687, 12), TO_UNSIGNED(726, 12),
TO_UNSIGNED(1422, 12), TO_UNSIGNED(1494, 12),
TO_UNSIGNED(186, 12), TO_UNSIGNED(234, 12),
TO_UNSIGNED(775, 12), TO_UNSIGNED(906, 12),
TO_UNSIGNED(1435, 12), TO_UNSIGNED(1585, 12),
TO_UNSIGNED(188, 12), TO_UNSIGNED(236, 12),
TO_UNSIGNED(781, 12), TO_UNSIGNED(909, 12),
TO_UNSIGNED(1432, 12), TO_UNSIGNED(1579, 12),
TO_UNSIGNED(190, 12), TO_UNSIGNED(238, 12),
TO_UNSIGNED(787, 12), TO_UNSIGNED(912, 12),
TO_UNSIGNED(1423, 12), TO_UNSIGNED(1597, 12),
TO_UNSIGNED(192, 12), TO_UNSIGNED(240, 12),
TO_UNSIGNED(793, 12), TO_UNSIGNED(915, 12),
TO_UNSIGNED(1426, 12), TO_UNSIGNED(1603, 12),
TO_UNSIGNED(194, 12), TO_UNSIGNED(242, 12),
TO_UNSIGNED(799, 12), TO_UNSIGNED(918, 12),
TO_UNSIGNED(1429, 12), TO_UNSIGNED(1591, 12),
TO_UNSIGNED(1, 12), TO_UNSIGNED(196, 12),
TO_UNSIGNED(244, 12), TO_UNSIGNED(805, 12),
TO_UNSIGNED(921, 12), TO_UNSIGNED(1438, 12),
TO_UNSIGNED(198, 12), TO_UNSIGNED(246, 12),
TO_UNSIGNED(811, 12), TO_UNSIGNED(924, 12),
TO_UNSIGNED(1441, 12), TO_UNSIGNED(1477, 12),
TO_UNSIGNED(200, 12), TO_UNSIGNED(248, 12),
TO_UNSIGNED(817, 12), TO_UNSIGNED(927, 12),
TO_UNSIGNED(1444, 12), TO_UNSIGNED(1465, 12),
TO_UNSIGNED(202, 12), TO_UNSIGNED(250, 12),
TO_UNSIGNED(823, 12), TO_UNSIGNED(930, 12),
TO_UNSIGNED(1447, 12), TO_UNSIGNED(1471, 12),
TO_UNSIGNED(204, 12), TO_UNSIGNED(252, 12),
TO_UNSIGNED(829, 12), TO_UNSIGNED(933, 12),
TO_UNSIGNED(1450, 12), TO_UNSIGNED(1495, 12),
TO_UNSIGNED(206, 12), TO_UNSIGNED(254, 12),
TO_UNSIGNED(691, 12), TO_UNSIGNED(936, 12),
TO_UNSIGNED(1453, 12), TO_UNSIGNED(1501, 12),
TO_UNSIGNED(208, 12), TO_UNSIGNED(256, 12),
TO_UNSIGNED(697, 12), TO_UNSIGNED(939, 12),
TO_UNSIGNED(1456, 12), TO_UNSIGNED(1507, 12),
TO_UNSIGNED(210, 12), TO_UNSIGNED(258, 12),
TO_UNSIGNED(703, 12), TO_UNSIGNED(942, 12),
TO_UNSIGNED(1462, 12), TO_UNSIGNED(1489, 12),
TO_UNSIGNED(212, 12), TO_UNSIGNED(260, 12),
TO_UNSIGNED(709, 12), TO_UNSIGNED(945, 12),
TO_UNSIGNED(1459, 12), TO_UNSIGNED(1513, 12),
TO_UNSIGNED(214, 12), TO_UNSIGNED(262, 12),
TO_UNSIGNED(715, 12), TO_UNSIGNED(948, 12),
TO_UNSIGNED(1486, 12), TO_UNSIGNED(1525, 12),
TO_UNSIGNED(216, 12), TO_UNSIGNED(264, 12),
TO_UNSIGNED(721, 12), TO_UNSIGNED(951, 12),
TO_UNSIGNED(1519, 12), TO_UNSIGNED(1618, 12),
TO_UNSIGNED(218, 12), TO_UNSIGNED(266, 12),
TO_UNSIGNED(727, 12), TO_UNSIGNED(954, 12),
TO_UNSIGNED(1399, 12), TO_UNSIGNED(1543, 12),
TO_UNSIGNED(220, 12), TO_UNSIGNED(268, 12),
TO_UNSIGNED(733, 12), TO_UNSIGNED(957, 12),
TO_UNSIGNED(1402, 12), TO_UNSIGNED(1549, 12),
TO_UNSIGNED(222, 12), TO_UNSIGNED(270, 12),
TO_UNSIGNED(739, 12), TO_UNSIGNED(960, 12),
TO_UNSIGNED(1405, 12), TO_UNSIGNED(1531, 12),
TO_UNSIGNED(224, 12), TO_UNSIGNED(272, 12),
TO_UNSIGNED(745, 12), TO_UNSIGNED(963, 12),
TO_UNSIGNED(1414, 12), TO_UNSIGNED(1537, 12),
TO_UNSIGNED(226, 12), TO_UNSIGNED(274, 12),
TO_UNSIGNED(751, 12), TO_UNSIGNED(966, 12),
TO_UNSIGNED(1417, 12), TO_UNSIGNED(1555, 12),
TO_UNSIGNED(228, 12), TO_UNSIGNED(276, 12),
TO_UNSIGNED(757, 12), TO_UNSIGNED(969, 12),
TO_UNSIGNED(1420, 12), TO_UNSIGNED(1561, 12),
TO_UNSIGNED(230, 12), TO_UNSIGNED(278, 12),
TO_UNSIGNED(763, 12), TO_UNSIGNED(972, 12),
TO_UNSIGNED(1408, 12), TO_UNSIGNED(1573, 12),
TO_UNSIGNED(232, 12), TO_UNSIGNED(280, 12),
TO_UNSIGNED(769, 12), TO_UNSIGNED(975, 12),
TO_UNSIGNED(1411, 12), TO_UNSIGNED(1567, 12),
TO_UNSIGNED(235, 12), TO_UNSIGNED(282, 12),
TO_UNSIGNED(788, 12), TO_UNSIGNED(1206, 12),
TO_UNSIGNED(1556, 12), TO_UNSIGNED(1635, 12),
TO_UNSIGNED(237, 12), TO_UNSIGNED(284, 12),
TO_UNSIGNED(794, 12), TO_UNSIGNED(1209, 12),
TO_UNSIGNED(1562, 12), TO_UNSIGNED(1629, 12),
TO_UNSIGNED(239, 12), TO_UNSIGNED(286, 12),
TO_UNSIGNED(800, 12), TO_UNSIGNED(1194, 12),
TO_UNSIGNED(1574, 12), TO_UNSIGNED(1632, 12),
TO_UNSIGNED(241, 12), TO_UNSIGNED(288, 12),
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TO_UNSIGNED(1788, 12), TO_UNSIGNED(11, 12),
TO_UNSIGNED(83, 12), TO_UNSIGNED(445, 12),
TO_UNSIGNED(493, 12), TO_UNSIGNED(971, 12),
TO_UNSIGNED(1079, 12), TO_UNSIGNED(1124, 12),
TO_UNSIGNED(447, 12), TO_UNSIGNED(495, 12),
TO_UNSIGNED(974, 12), TO_UNSIGNED(1085, 12),
TO_UNSIGNED(1127, 12), TO_UNSIGNED(1277, 12),
TO_UNSIGNED(1818, 12), TO_UNSIGNED(141, 12),
TO_UNSIGNED(449, 12), TO_UNSIGNED(497, 12),
TO_UNSIGNED(977, 12), TO_UNSIGNED(1091, 12),
TO_UNSIGNED(1130, 12), TO_UNSIGNED(1283, 12),
TO_UNSIGNED(451, 12), TO_UNSIGNED(499, 12),
TO_UNSIGNED(908, 12), TO_UNSIGNED(1097, 12),
TO_UNSIGNED(1133, 12), TO_UNSIGNED(1289, 12),
TO_UNSIGNED(1692, 12), TO_UNSIGNED(453, 12),
TO_UNSIGNED(501, 12), TO_UNSIGNED(911, 12),
TO_UNSIGNED(1103, 12), TO_UNSIGNED(1136, 12),
TO_UNSIGNED(1271, 12), TO_UNSIGNED(1716, 12),
TO_UNSIGNED(455, 12), TO_UNSIGNED(503, 12),
TO_UNSIGNED(914, 12), TO_UNSIGNED(1109, 12),
TO_UNSIGNED(1139, 12), TO_UNSIGNED(1301, 12),
TO_UNSIGNED(1704, 12), TO_UNSIGNED(457, 12),
TO_UNSIGNED(505, 12), TO_UNSIGNED(917, 12),
TO_UNSIGNED(1115, 12), TO_UNSIGNED(1142, 12),
TO_UNSIGNED(1295, 12), TO_UNSIGNED(1710, 12),
TO_UNSIGNED(459, 12), TO_UNSIGNED(507, 12),
TO_UNSIGNED(920, 12), TO_UNSIGNED(1121, 12),
TO_UNSIGNED(1145, 12), TO_UNSIGNED(1313, 12),
TO_UNSIGNED(1698, 12), TO_UNSIGNED(461, 12),
TO_UNSIGNED(509, 12), TO_UNSIGNED(923, 12),
TO_UNSIGNED(983, 12), TO_UNSIGNED(1148, 12),
TO_UNSIGNED(1307, 12), TO_UNSIGNED(1722, 12),
TO_UNSIGNED(463, 12), TO_UNSIGNED(511, 12),
TO_UNSIGNED(926, 12), TO_UNSIGNED(989, 12),
TO_UNSIGNED(1151, 12), TO_UNSIGNED(1319, 12),
TO_UNSIGNED(1734, 12), TO_UNSIGNED(465, 12),
TO_UNSIGNED(513, 12), TO_UNSIGNED(929, 12),
TO_UNSIGNED(995, 12), TO_UNSIGNED(1154, 12),
TO_UNSIGNED(1325, 12), TO_UNSIGNED(1728, 12),
TO_UNSIGNED(467, 12), TO_UNSIGNED(515, 12),
TO_UNSIGNED(932, 12), TO_UNSIGNED(1001, 12),
TO_UNSIGNED(1157, 12), TO_UNSIGNED(1337, 12),
TO_UNSIGNED(1740, 12), TO_UNSIGNED(469, 12),
TO_UNSIGNED(517, 12), TO_UNSIGNED(935, 12),
TO_UNSIGNED(1007, 12), TO_UNSIGNED(1160, 12),
TO_UNSIGNED(1331, 12), TO_UNSIGNED(1776, 12),
TO_UNSIGNED(471, 12), TO_UNSIGNED(519, 12),
TO_UNSIGNED(938, 12), TO_UNSIGNED(1013, 12),
TO_UNSIGNED(1163, 12), TO_UNSIGNED(1355, 12),
TO_UNSIGNED(1782, 12), TO_UNSIGNED(473, 12),
TO_UNSIGNED(521, 12), TO_UNSIGNED(941, 12),
TO_UNSIGNED(1019, 12), TO_UNSIGNED(1166, 12),
TO_UNSIGNED(1361, 12), TO_UNSIGNED(1746, 12)
);
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_IndexLUT : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS ( INPUT_1 )
VARIABLE OP1 : UNSIGNED(10 downto 0);
BEGIN
OP1 := UNSIGNED( INPUT_1(10 downto 0) );
-- synthesis translate_off
if ( OP1 > TO_UNSIGNED(1823, 11) ) THEN
OP1 := TO_UNSIGNED(1823, 11);
END IF;
-- synthesis translate_on
OUTPUT_1 <= "00000000000000000000" & STD_LOGIC_VECTOR(ROM( TO_integer( OP1 ) ));
END PROCESS;
-------------------------------------------------------------------------
END ROM;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter10/example10_1_dir/example10_1/example10_1.vhd
|
1
|
1064
|
--!
--! @file: example10_1.vhd
--! @brief: writing values to a file
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
use std.textio.all;
--------------------------------------
entity write_to_file is
end entity write_to_file;
--------------------------------------
architecture circuit of write_to_file is
constant period: time := 100 ns;
signal clk: bit := '0';
file f: text open write_mode is "test_file.txt";
begin
proc: process
constant str1: string(1 to 2) := "t=";
constant str2: string(1 to 3) := " i=";
variable l: line;
variable t: time := 0 ns;
variable i: natural range 0 to 7 := 0;
begin
wait for period/2;
clk <= '1';
t := period/2 + i * period;
write(l, str1);
write(l, t);
write(l, str2);
write(l, i);
writeline(f, l);
i := i + 1;
wait for period/2;
clk <= '0';
end process proc;
end architecture circuit;
--------------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/coprocessor/coprocessor.vhd
|
2
|
5791
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2010, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: arith
-- File: arith.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Declaration of mul/div components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package coprocessor is
type sequential32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
dInstr : std_logic_vector(31 downto 0);
aInstr : std_logic_vector(31 downto 0);
eInstr : std_logic_vector(31 downto 0);
mInstr : std_logic_vector(31 downto 0);
xInstr : std_logic_vector(31 downto 0);
end record;
type sequential32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0);
result : std_logic_vector(31 downto 0);
mResult : std_logic_vector(31 downto 0);
end record;
type async32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
signed : std_logic;
write_data : std_logic;
read_data : std_logic;
end record;
type async32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0);
result : std_logic_vector(31 downto 0);
end record;
-- definition d'un type de base pour les operateurs arithmetiques pouvant se
-- realiser en un cycle d'horloge
type custom32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
instr : std_logic_vector(31 downto 0); -- operand 2
end record;
type custom32_out_type is record
result : std_logic_vector(31 downto 0);
end record;
-- fin de declaration
component RESOURCE_CUSTOM_1
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_2
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_3
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_4
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_5
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_6
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in async32_in_type;
outp : out async32_out_type
);
end component;
component RESOURCE_CUSTOM_7
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_8
port (
inp : in custom32_in_type;
outp : out custom32_out_type
);
end component;
component RESOURCE_CUSTOM_A
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end component;
component RESOURCE_CUSTOM_B
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
end component;
COMPONENT INTERFACE_COMB_1
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END COMPONENT;
COMPONENT INTERFACE_COMB_2
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END COMPONENT;
COMPONENT INTERFACE_COMB_3
PORT (
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END COMPONENT;
COMPONENT INTERFACE_COMB_4
PORT (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
cancel : IN std_ulogic;
inp : IN custom32_in_type;
outp : OUT custom32_out_type
);
END COMPONENT;
COMPONENT INTERFACE_SEQU_1
PORT (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in sequential32_in_type;
outp : out sequential32_out_type
);
END COMPONENT;
COMPONENT INTERFACE_ASYN_1
PORT (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
inp : in async32_in_type;
outp : out async32_out_type
);
END COMPONENT;
-- synthesis translate_off
procedure printmsg(s : string);
-- synthesis translate_on
end;
package body coprocessor is
-- synthesis translate_off
PROCEDURE printmsg(s : string) is
variable L : line;
BEGIN
L := new string'(s);
writeline(output, L);
END;
-- synthesis translate_on
END;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ram_boot_for_simu.vhd
|
1
|
6637
|
-- The libraries ieee.std_logic_unsigned and std.textio will need to be included
-- with this example
-- The following code will infer a Single port Block RAM and initialize it using a FILE
-- Place the following code before the begin of the architecture
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.ALL;
ENTITY RAM IS
GENERIC(
memory_type : string := "DEFAULT";
block_count : integer := 03);
PORT(
clk : IN std_logic;
enable : IN std_logic;
write_byte_enable : IN std_logic_vector(3 DOWNTO 0);
address : IN std_logic_vector(31 DOWNTO 2);
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0)
);
END;
ARCHITECTURE logic OF RAM IS
CONSTANT TAILLE_LOADER : INTEGER := 64*1024; -- TAILLE EN OCTETS (NORMALEMENT)
TYPE memoire IS ARRAY(0 TO TAILLE_LOADER-1) OF bit_vector(7 DOWNTO 0);
IMPURE FUNCTION load_memoire (filename : IN string; byte : IN integer) RETURN memoire IS
FILE ram_file : text IS IN filename;
VARIABLE line_name : line;
VARIABLE line_temp : bit_vector(31 DOWNTO 0);
VARIABLE ram_name : memoire;
BEGIN
FOR I IN memoire'range LOOP
IF (NOT endfile(ram_file)) THEN
readline(ram_file, line_name);
read (line_name, line_temp);
IF(byte = 1) THEN
ram_name(I) := line_temp(31 DOWNTO 24);
ELSIF(byte = 2) THEN
ram_name(I) := line_temp(23 DOWNTO 16);
ELSIF(byte = 3) THEN
ram_name(I) := line_temp(15 DOWNTO 8);
ELSIF(byte = 4) THEN
ram_name(I) := line_temp(7 DOWNTO 0);
END IF;
END IF;
END LOOP;
RETURN ram_name;
END FUNCTION;
SIGNAL laRAM1 : memoire := load_memoire("../code_bin.txt", 1);
SIGNAL laRAM2 : memoire := load_memoire("../code_bin.txt", 2);
SIGNAL laRAM3 : memoire := load_memoire("../code_bin.txt", 3);
SIGNAL laRAM4 : memoire := load_memoire("../code_bin.txt", 4);
--
-- CETTE MEMOIRE EST MICROSCOPIQUE... PAS LA PEINE D'UTILISER UN BLOC RAM POUR
-- SON IMPLANTATION...
--
-- attribute RAM_STYLE : string;
-- attribute RAM_STYLE of laRAM1: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM2: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM3: signal is "PIPE_DISTRIBUTED";
-- attribute RAM_STYLE of laRAM4: signal is "PIPE_DISTRIBUTED";
BEGIN
--
-- ON GERE LES BITS (31 => 24)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(3) = '1' THEN
laRAM1(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(31 DOWNTO 24));
data_read(31 DOWNTO 24) <= data_write(31 DOWNTO 24);
ELSE
data_read(31 DOWNTO 24) <= to_stdlogicvector(laRAM1(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (23 => 16)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(2) = '1' THEN
laRAM2(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(23 DOWNTO 16));
data_read(23 DOWNTO 16) <= data_write(23 DOWNTO 16);
ELSE
data_read(23 DOWNTO 16) <= to_stdlogicvector(laRAM2(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (15 => 8)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(1) = '1' THEN
laRAM3(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(15 DOWNTO 8));
data_read(15 DOWNTO 8) <= data_write(15 DOWNTO 8);
ELSE
data_read(15 DOWNTO 8) <= to_stdlogicvector(laRAM3(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
--
-- ON GERE LES BITS (7 => 0)
--
PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enable = '1' THEN
IF write_byte_enable(0) = '1' THEN
laRAM4(conv_integer(address(16 DOWNTO 2))) <= to_bitvector(data_write(7 DOWNTO 0));
data_read(7 DOWNTO 0) <= data_write(7 DOWNTO 0);
ELSE
data_read(7 DOWNTO 0) <= to_stdlogicvector(laRAM4(conv_integer(address(16 DOWNTO 2))));
END IF;
END IF;
END IF;
END PROCESS;
END; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/top_sp605.vhd
|
1
|
12496
|
-- Top-level design for ipbus demo
--
-- This version is for xc6vlx240t on Xilinx ML605 eval board
-- Uses the v6 hard EMAC core with GMII interface to an external Gb PHY
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, May 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use work.ipbus.ALL;
--use work.bus_arb_decl.all;
--use work.mac_arbiter_decl.all;
library unisim;
use unisim.VComponents.all;
entity top_ml605_extphy is port(
clk100: in std_logic;
rst: in std_logic;
sw : in std_logic;
--led: out std_logic_vector(7 downto 0);
led: out std_logic;
i_uart : in std_logic;
o_uart : out std_logic;
o_uart2 : out std_logic;
buttons : in std_logic_vector( 2 downto 0 );
BTNU : in std_logic;
BTNC : in std_logic;
BTND : in std_logic;
BTNL : in std_logic;
BTNR : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end top_ml605_extphy;
architecture rtl of top_ml605_extphy is
component pulse_filter
Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16);
Port (
SIGNAL_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SIGNAL_O : out STD_LOGIC
);
end component;
component Colorgen
Port ( iter : in STD_LOGIC_VECTOR (11 downto 0);
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0)); -- blue output
end component;
component VGA_bitmap_640x480
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(11 downto 0); -- iter output
ADDR1 : in std_logic_vector(16 downto 0);
data_in1 : in std_logic_vector(11 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(16 downto 0);
data_in2 : in std_logic_vector(11 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(16 downto 0);
data_in3 : in std_logic_vector(11 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(16 downto 0);
data_in4 : in std_logic_vector(11 downto 0);
data_write4 : in std_logic);
end component;
signal BTNUB, BTNCB, BTNDB, BTNRB, BTNLB, data_write1, data_write2,data_write3, data_write4,data_write5, data_write6,data_write7, data_write8, clk50, clk100_sig: std_logic;
signal iterS, data_out1,data_out2, data_out3 ,data_out4, data_out5,data_out6, data_out7 ,data_out8 : std_logic_vector(11 downto 0);
signal ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR6, ADDR7, ADDR8 : std_logic_vector(16 downto 0);
--component clk_wiz_0 is -- vivado
-- component clkgen is --ise
-- port
-- (-- Clock in ports
-- clk_in1 : in std_logic;
-- -- Clock out ports
-- clk_out1 : out std_logic;
-- clk_out2 : out std_logic
-- );
-- end component;
begin
process(rst, clk50)
begin
if(rst='1') then
--o_uart <= '0';
led <= '0';
elsif(clk50'event and clk50='1') then
--o_uart <= i_uart;
led <= sw;
end if;
end process;
clk_div : process(clk100, rst)
begin
if(rst='1') then
clk50 <= '0';
elsif(clk100'event and clk100 = '1') then
clk50 <= not(clk50);
end if;
end process;
-- leds(7 downto 0) <= ('0','0','0','0','0','0', locked, onehz);
-- Inst_plasma8: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin8.txt"
-- )
-- PORT MAP(
-- clk => clk50,
---- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write8,
-- ADDR => ADDR8,
-- data_out => data_out8,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB
-- );
--Inst_plasma7: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin7.txt"
-- )
-- PORT MAP(
-- clk => clk50,
---- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write7,
-- ADDR => ADDR7,
-- data_out => data_out7,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
-- );
--
--
-- Inst_plasma5: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin5.txt"
-- )
-- PORT MAP(
-- clk => clk50,
-- -- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write5,
-- ADDR => ADDR5,
-- data_out => data_out5,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB--open
-- );
Inst_plasma4: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin4.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => open,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write4,
ADDR => ADDR4,
data_out => data_out4,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB
);
--
Inst_plasma3: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin3.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => open,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write3,
ADDR => ADDR3,
data_out => data_out3,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
);
-- Inst_plasma6: entity work.plasma
-- GENERIC MAP (
-- memory_type => "XILINX_16X",
-- log_file => "UNUSED",
-- ethernet => '0',
-- eUart => '1',
-- use_cache => '0',
-- plasma_code => "../code_bin6.txt"
-- )
-- PORT MAP(
-- clk => clk50,
---- clk_VGA => clk100,
-- reset => rst,
-- uart_write => open,
-- uart_read => i_uart,
-- fifo_1_out_data => x"00000000",
-- fifo_1_read_en => open,
-- fifo_1_empty => '0',
-- fifo_2_in_data => open,
-- fifo_1_write_en => open,
-- fifo_2_full => '0',
--
-- fifo_1_full => '0',
-- fifo_1_valid => '0',
-- fifo_2_empty => '0',
-- fifo_2_valid => '0',
-- fifo_1_compteur => x"00000000",
-- fifo_2_compteur => x"00000000",
--
-- data_enable => data_write6,
-- ADDR => ADDR6,
-- data_out => data_out6,
--
-- gpio0_out => open,
-- gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
-- );
Inst_plasma2: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin2.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => o_uart,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write2,
ADDR => ADDR2,
data_out => data_out2,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB --open
);
Inst_plasma1: entity work.plasma
GENERIC MAP (
memory_type => "XILINX_16X",
log_file => "UNUSED",
ethernet => '0',
eUart => '1',
use_cache => '0',
plasma_code => "../code_bin1.txt"
)
PORT MAP(
clk => clk50,
-- clk_VGA => clk100,
reset => rst,
uart_write => o_uart2,
uart_read => i_uart,
fifo_1_out_data => x"00000000",
fifo_1_read_en => open,
fifo_1_empty => '0',
fifo_2_in_data => open,
fifo_1_write_en => open,
fifo_2_full => '0',
fifo_1_full => '0',
fifo_1_valid => '0',
fifo_2_empty => '0',
fifo_2_valid => '0',
fifo_1_compteur => x"00000000",
fifo_2_compteur => x"00000000",
data_enable => data_write1,
ADDR => ADDR1,
data_out => data_out1,
gpio0_out => open,
gpioA_in => x"000000" & buttons & BTNDB & BTNRB & BTNLB & BTNUB & BTNCB--open
);
InstVGA: VGA_bitmap_640x480
port map(clk50,
clk100,
rst,
VGA_hs,
VGA_vs,
iterS,
ADDR1,
data_out1,
data_write1,
ADDR2,
data_out2,
data_write2,
ADDR3,
data_out3,
data_write3,
ADDR4,
data_out4,
data_write4
);
InstColorgen: Colorgen
port map(iterS,VGA_red,VGA_green,VGA_blue);
InstancepulsBTNU: pulse_filter
port map(BTNU,
clk50,
BTNUB);
InstancepulsBTND: pulse_filter
port map(BTND,
clk50,
BTNDB);
InstancepulsBTNL: pulse_filter
port map(BTNL,
clk50,
BTNLB);
InstancepulsBTNR: pulse_filter
port map(BTNR,
clk50,
BTNRB);
InstancepulsBTNC: pulse_filter
port map(BTNC,
clk50,
BTNCB);
end rtl;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/function_8.vhd
|
5
|
1334
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_8 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_8 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 8, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/mandelbrot/function_16.vhd
|
5
|
1182
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_16 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_16 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0);
begin
rTemp1 := INPUT_1( 7 downto 0);
OUTPUT_1 <= (rTemp1 & rTemp1 & rTemp1 & rTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter6/exercise6_7_dir/exercise6_7.vhd
|
1
|
1351
|
--!
--! @file: exercise6_7.vhd
--! @brief: Binary Sorter with Loop
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity binary_sorter is
generic (N: integer := 5);
port (
input: in bit_vector(N-1 downto 0);
output: out bit_vector(N-1 downto 0));
end entity binary_sorter;
--------------------------------------
architecture circuit of binary_sorter is
begin
proc: process (input)
variable count: integer range 0 to N := 0;
variable output_buffer: std_logic_vector(N-1 downto 0);
begin
-- first loop: counts the number of 1's there are in the vector
forloop: for i in 0 to N-1 loop
if (input(i) = '1') then
count = count + 1;
end if;
end loop forloop;
-- second loop: assigns 1's at the beginning and then the rest is 0
forloop1: for i in N-1 downto (N-1)-count loop
if (count = 0) then
output(i) <= '0';
else
output(i) <= '1';
end if;
count = count - 1;
end loop forloop1;
end process proc;
end architecture circuit;
--------------------------------------
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter5/exercise5_10_dir/exercise5_10.vhd
|
1
|
1600
|
--!
--! @file: exercise5_10.vhd
--! @brief: arithmetic circuit with integer
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mini_alu is
generic (N: integer := 3;);
port (
a, b: in integer range -2**(N-1) to 2**(N-1)-1;
cin: in integer range 0 to 1;
opcode: in integer range 0 to 7;
y: out integer range -2**(N-1) to 2**(N-1)-1;
end entity mini_alu;
--------------------------------------
architecture circuit of mini_alu is
signal a_sig, b_sig: signed(N-1 downto 0);
signal a_unsig, b_unsig: unsigned(N-1 downto 0);
signal y_sig: signed(N-1 downto 0);
signal y_unsig: unsigned(N-1 downto 0);
begin
a_sig <= to_signed(a, a_sig'length);
b_sig <= to_signed(b, b_sig'length);
a_unsig <= to_unsigned(a, a_unsig'length);
b_unsig <= to_unsigned(b, b_unsig'length);
-- signed
with opcode(1 downto 0) select
y_sig <= a_sig + b_sig when 0,
a_sig - b_sig when 1.
b_sig - a_sig when 2,
a_sig + b_sig + cin when others;
-- unsigned
with opcode(1 downto 0) select
y_unsig <= a_unsig + b_unsig when 0,
a_unsig - b_unsig when 1.
b_unsig - a_unsig when 2,
a_unsig + b_unsig + cin when others;
-- mux
with opcode(2) select
y <= y_unsig when 0,
y_sig when others;
end architecture circuit;
--------------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/filtre/function_1.vhd
|
2
|
1274
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_1 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_1 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(63 downto 0);
variable rTemp2 : SIGNED(31 downto 0);
variable rTemp3 : SIGNED(31 downto 0);
begin
rTemp1 := (signed(INPUT_1) * signed(INPUT_2));
OUTPUT_1 <= std_logic_vector(rTemp1(43 downto 12));
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
src_vhd/ClockManager.vhd
|
1
|
711
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
entity ClockManager is
Port ( clock : in std_logic;
reset : in std_logic;
ce_param : out std_logic);
end ClockManager;
architecture Behavioral of ClockManager is
signal cpt : integer := 0;
begin
process (clock, reset)
begin
if (reset = '1') then
cpt<=0;
elsif (rising_edge(clock)) then
if (cpt< PARAM_DELAY) then
cpt<= cpt + 1;
ce_param<='0';
else
cpt<=0;
ce_param<='1';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/plasma_config.vhd
|
1
|
7099
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package asip_config is
-- INSTRUCTION TYPE (000000)
constant ENABLE_SLL : integer := 1 ; -- "000000";
constant ENABLE_SRL : integer := 1 ; -- "000010";
constant ENABLE_SRA : integer := 1 ; -- "000011";
constant ENABLE_SLLV : integer := 1 ; -- "000100";
constant ENABLE_SRLV : integer := 1 ; -- "000110";
constant ENABLE_SRAV : integer := 1 ; -- "000111";
constant ENABLE_JR : integer := 1 ; -- "001000";
constant ENABLE_JALR : integer := 1 ; -- "001001";
constant ENABLE_MOVZ : integer := 1 ; -- "001010";
constant ENABLE_MOVN : integer := 1 ; -- "001011";
constant ENABLE_SYSCALL : integer := 1 ; -- "001100";
constant ENABLE_BREAK : integer := 1 ; -- "001101";
constant ENABLE_SYNC : integer := 1 ; -- "001111";
constant ENABLE_MFHI : integer := 1 ; -- "010000";
constant ENABLE_MTHI : integer := 1 ; -- "010001";
constant ENABLE_MFLO : integer := 1 ; -- "010010";
constant ENABLE_MTLO : integer := 1 ; -- "010011";
constant ENABLE_MULT : integer := 1 ; -- "011000";
constant ENABLE_MULTU : integer := 1 ; -- "011001";
constant ENABLE_DIV : integer := 1 ; -- "011010";
constant ENABLE_DIVU : integer := 1 ; -- "011011";
constant ENABLE_ADD : integer := 1 ; -- "100000";
constant ENABLE_ADDU : integer := 1 ; -- "100001";
constant ENABLE_SUB : integer := 1 ; -- "100010";
constant ENABLE_SUBU : integer := 1 ; -- "100011";
constant ENABLE_AND : integer := 1 ; -- "100100";
constant ENABLE_OR : integer := 1 ; -- "100101";
constant ENABLE_XOR : integer := 1 ; -- "100110";
constant ENABLE_NOR : integer := 1 ; -- "100111";
constant ENABLE_SLT : integer := 1 ; -- "101010";
constant ENABLE_SLTU : integer := 1 ; -- "101011";
constant ENABLE_DADDU : integer := 1 ; -- "101101";
constant ENABLE_TGEU : integer := 1 ; -- "110001";
constant ENABLE_TLT : integer := 1 ; -- "110010";
constant ENABLE_TLTU : integer := 1 ; -- "110011";
constant ENABLE_TEQ : integer := 1 ; -- "110100";
constant ENABLE_TNE : integer := 1 ; -- "110110";
-- INSTRUCTION TYPE (000001)
constant ENABLE_BLTZ : integer := 1 ; -- "00000";
constant ENABLE_BGEZ : integer := 1 ; -- "00001";
constant ENABLE_BLTZL : integer := 1 ; -- "00010";
constant ENABLE_BGEZL : integer := 1 ; -- "00011";
constant ENABLE_BLTZAL : integer := 1 ; -- "10000";
constant ENABLE_BGEZAL : integer := 1 ; -- "10001";
constant ENABLE_BLTZALL : integer := 1 ; -- "10010";
constant ENABLE_BGEZALL : integer := 1 ; -- "10011";
-- INSTRUCTION TYPE (000010)
constant ENABLE_J : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000011)
constant ENABLE_JAL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000100)
constant ENABLE_BEQ : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000101)
constant ENABLE_BNE : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000110)
constant ENABLE_BLEZ : integer := 1 ; -- "";
-- INSTRUCTION TYPE (000111)
constant ENABLE_BGTZ : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001000)
constant ENABLE_ADDI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001001)
constant ENABLE_ADDIU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001010)
constant ENABLE_SLTI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001011)
constant ENABLE_SLTIU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001100)
constant ENABLE_ANDI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001101)
constant ENABLE_ORI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001110)
constant ENABLE_XORI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (001111)
constant ENABLE_LUI : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010000)
constant ENABLE_COP0 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010001)
constant ENABLE_COP1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010010)
constant ENABLE_COP2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010011)
constant ENABLE_COP3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010100)
constant ENABLE_BEQL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010101)
constant ENABLE_BNEL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010110)
constant ENABLE_BLEZL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (010111)
constant ENABLE_BGTZL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100000)
constant ENABLE_LB : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100001)
constant ENABLE_LH : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100010)
constant ENABLE_LWL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100011)
constant ENABLE_LW : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100100)
constant ENABLE_LBU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100101)
constant ENABLE_LHU : integer := 1 ; -- "";
-- INSTRUCTION TYPE (100110)
constant ENABLE_LWR : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101000)
constant ENABLE_SB : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101001)
constant ENABLE_SH : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101010)
constant ENABLE_SWL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101011)
constant ENABLE_SW : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101110)
constant ENABLE_SWR : integer := 1 ; -- "";
-- INSTRUCTION TYPE (101111)
constant ENABLE_CACHE : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110000)
constant ENABLE_LL : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110001)
constant ENABLE_LWC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110010)
constant ENABLE_LWC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110011)
constant ENABLE_LWC3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110101)
constant ENABLE_LDC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110110)
constant ENABLE_LDC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (110111)
constant ENABLE_LDC3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111000)
constant ENABLE_SC : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111001)
constant ENABLE_SWC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111010)
constant ENABLE_SWC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111011)
constant ENABLE_SWC3 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111101)
constant ENABLE_SDC1 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111110)
constant ENABLE_SDC2 : integer := 1 ; -- "";
-- INSTRUCTION TYPE (111111)
constant ENABLE_SDC3 : integer := 1 ; -- "";
end;
package body asip_config is
-- NOTHING FOR NOW ;-)
end;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter6/exercise6_1_dir/exercise6_1.vhd
|
1
|
1021
|
-- author: Antonio Gutierrez
-- date: 09/10/13
-- description: exercise 1: Latch and Flip Flop
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity flip_flop_latch is
--generic declarations
port (
d: in std_logic;
clk: in std_logic;
q1, q2: out std_logic);
end entity flip_flop_latch;
--------------------------------------
architecture circuit of flip_flop_latch is
--signals and declarations
begin
-------------------
---- flip flop
-------------------
flip_flop: process (clk)
--declarativepart
begin
if (clk'event and clk = '1') then
q1 <= d;
end if;
end process flip_flop;
-------------------
---- latch
-------------------
latch: process (clk, d)
--declarativepart
begin
if (clk = '1') then
q2 <= d;
end if;
end process latch;
end architecture circuit;
--------------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/synthese/IPBus_ml605_ASIP/RAM_single_port.vhd
|
1
|
1796
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:34 05/19/2016
-- Design Name:
-- Module Name: RAM_single_port - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_single_port is
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(11 downto 0);
ADDR : in STD_LOGIC_VECTOR (16 downto 0);
data_out : out STD_LOGIC_VECTOR (11 downto 0));
end RAM_single_port;
architecture Behavioral of RAM_single_port is
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 12;
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 76799) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal screen : GRAM;-- := ram_function_name("../mandelbrot.bin"); -- the memory representation of the image
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write = '1') then
screen(to_integer(unsigned(ADDR))) <= data_in;
data_out <= data_in;
else
data_out <= screen(to_integer(unsigned(ADDR)));
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/xilinx/RAM32X1D.vhd
|
1
|
2686
|
-- $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/vhdsclibs/data/unisims/unisim/VITAL/RAM32X1D.vhd,v 1.1 2008/06/19 16:59:25 vandanad Exp $
-------------------------------------------------------------------------------
-- Copyright (c) 1995/2004 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Description : Xilinx Functional Simulation Library Component
-- / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
-- /___/ /\ Filename : RAM32X1D.vhd
-- \ \ / \ Timestamp : Thu Apr 8 10:56:48 PDT 2004
-- \___\/\___\
--
-- Revision:
-- 03/23/04 - Initial version.
----- CELL RAM32X1D -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VPKG.all;
entity RAM32X1D is
generic (
INIT : bit_vector(31 downto 0) := X"00000000"
);
port (
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
DPRA4 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic
);
end RAM32X1D;
architecture RAM32X1D_V of RAM32X1D is
signal MEM : std_logic_vector( 32 downto 0 ) := ('X' & To_StdLogicVector(INIT) );
begin
VITALReadBehavior : process(A0, A1, A2, A3, A4, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0, MEM)
Variable Index_SP : integer := 32 ;
Variable Index_DP : integer := 32 ;
variable Raddress : std_logic_vector (4 downto 0);
variable Waddress : std_logic_vector (4 downto 0);
begin
Waddress := (A4, A3, A2, A1, A0);
Raddress := (DPRA4, DPRA3, DPRA2, DPRA1, DPRA0);
Index_SP := SLV_TO_INT(SLV => Waddress);
Index_DP := SLV_TO_INT(SLV => Raddress);
SPO <= MEM(Index_SP);
DPO <= MEM(Index_DP);
end process VITALReadBehavior;
VITALWriteBehavior : process(WCLK)
variable Index_SP : integer := 32;
variable Index_DP : integer := 32;
variable Address : std_logic_vector( 4 downto 0);
begin
Address := (A4, A3, A2, A1, A0);
Index_SP := SLV_TO_INT(SLV => Address );
if ((WE = '1') and (wclk'event) and (wclk'last_value = '0') and (wclk = '1')) then
MEM(Index_SP) <= D after 100 ps;
end if;
end process VITALWriteBehavior;
end RAM32X1D_V;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/TRIGO/COSINUS_32b.vhd
|
1
|
30123
|
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Cordic Top --
-- --
-- Simple SIN/COS Cordic example --
-- 32 bits fixed format Sign,2^0, 2^-1,2^-2 etc. --
-- angle input +/-0.5phi --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity COSINUS_32b is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
angle : in std_logic_vector(31 downto 0); -- input radian
sin : out std_logic_vector(31 downto 0); -- THIS OUTPUT ¨PROVIDES THE SINUS RESULT
cos : out std_logic_vector(31 downto 0);
start : in std_logic;
done : out std_logic);
end COSINUS_32b;
architecture synthesis of COSINUS_32b is
constant xinit_c : std_logic_vector(31 downto 0):=X"26dd3b44";
constant yinit_c : std_logic_vector(31 downto 0):=X"00000000";
component addsub is
port(abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end component;
component shiftn is
port(ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end component;
component atan32 is --ARCTAN(x) lut
port (ZA : in Std_Logic_Vector(4 downto 0);
ZData : out Std_Logic_Vector(31 downto 0));
end component;
component fsm is
port(clk : in std_logic;
reset : in std_logic; -- Active low reset
start : in std_logic;
cnt : in std_logic_vector(4 downto 0);
init : out std_logic;
load : out std_logic;
done : out std_logic);
end component;
signal cnt_s : std_logic_vector(4 downto 0); -- bit counter, 2^5
signal newx_s : std_logic_vector(31 downto 0);
signal newy_s : std_logic_vector(31 downto 0);
signal newz_s : std_logic_vector(31 downto 0);
signal xreg_s : std_logic_vector(31 downto 0);
signal yreg_s : std_logic_vector(31 downto 0);
signal zreg_s : std_logic_vector(31 downto 0);
signal sxreg_s: std_logic_vector(31 downto 0);
signal syreg_s: std_logic_vector(31 downto 0);
signal atan_s : std_logic_vector(31 downto 0); -- arctan LUT
signal init_s : std_logic;
signal load_s : std_logic;
signal as_s : std_logic;
signal nas_s : std_logic;
begin
SHIFT1: shiftn port map (xreg_s,sxreg_s,cnt_s);
SHIFT2: shiftn port map (yreg_s,syreg_s,cnt_s);
nas_s <= not as_s;
ADD1 : addsub port map (xreg_s,syreg_s,newx_s,as_s); -- xreg
ADD2 : addsub port map (yreg_s,sxreg_s,newy_s,nas_s); -- yreg
LUT : atan32 port map(cnt_s,atan_s);
ADD3 : addsub port map (zreg_s,atan_s(31 downto 0),newz_s,as_s); -- zreg
FSM1 : fsm port map (clk,reset,start,cnt_s,init_s,load_s,done);
-- COS(X) Register
process (clk,newx_s)
begin
if (rising_edge(clk)) then
if init_s='1' then xreg_s(31 downto 0) <= xinit_c; -- fails in vh2sc xinit_c(31 downto 0); -- 0.607
elsif load_s='1' then xreg_s <= newx_s;
end if;
end if;
end process;
-- SIN(Y) Register
process (clk,newy_s)
begin
if (rising_edge(clk)) then
if init_s='1' then yreg_s <= yinit_c; -- 0.0000 fails in vh2sc yinit_c(31 downto 0)
elsif load_s='1' then yreg_s <= newy_s;
end if;
end if;
end process;
-- Z Register
process (clk,newz_s,angle)
begin
if (rising_edge(clk)) then
if init_s='1' then zreg_s <= angle; -- x
elsif load_s='1' then zreg_s <= newz_s;
end if;
end if;
end process;
as_s <= zreg_s(31); -- MSB=Sign bit
process (clk,load_s,init_s) -- bit counter
begin
if (rising_edge(clk)) then
if init_s='1' then cnt_s<=(others=> '0');
elsif (load_s='1') then cnt_s <= cnt_s + '1';
end if;
end if;
end process;
sin <= yreg_s;
cos <= xreg_s;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Adder/Subtracter --
-- no overflow. --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port (abus : in std_logic_vector(31 downto 0);
bbus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
as : in std_logic); --add=1, subtract=0
end addsub;
architecture synthesis of addsub is
begin
process(as,abus,bbus)
begin
if as='1' then
obus <= abus + bbus;
else
obus <= abus - bbus;
end if;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity atan32 is
port ( za : in std_logic_vector(4 downto 0);
zdata : out std_logic_vector(31 downto 0));
end atan32;
Architecture synthesis of atan32 Is
Begin
process(ZA)
begin
Case ZA is
when "00000" => ZData <= X"3243f6a8";
when "00001" => ZData <= X"1dac6705";
when "00010" => ZData <= X"0fadbafc";
when "00011" => ZData <= X"07f56ea6";
when "00100" => ZData <= X"03feab76";
when "00101" => ZData <= X"01ffd55b";
when "00110" => ZData <= X"00fffaaa";
when "00111" => ZData <= X"007fff55";
when "01000" => ZData <= X"003fffea";
when "01001" => ZData <= X"001ffffd";
when "01010" => ZData <= X"000fffff";
when "01011" => ZData <= X"0007ffff";
when "01100" => ZData <= X"0003ffff";
when "01101" => ZData <= X"0001ffff";
when "01110" => ZData <= X"0000ffff";
when "01111" => ZData <= X"00007fff";
when "10000" => ZData <= X"00003fff";
when "10001" => ZData <= X"00001fff";
when "10010" => ZData <= X"00000fff";
when "10011" => ZData <= X"000007ff";
when "10100" => ZData <= X"000003ff";
when "10101" => ZData <= X"000001ff";
when "10110" => ZData <= X"000000ff";
when "10111" => ZData <= X"0000007f";
when "11000" => ZData <= X"0000003f";
when "11001" => ZData <= X"0000001f";
when "11010" => ZData <= X"0000000f";
when "11011" => ZData <= X"00000007";
when "11100" => ZData <= X"00000003";
when "11101" => ZData <= X"00000001";
when "11110" => ZData <= X"00000000";
when "11111" => ZData <= X"00000000";
When others => ZData <= "--------------------------------";
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY fsm IS
PORT(
clk : IN std_logic;
reset : IN std_logic; -- Active low reset
start : IN std_logic;
cnt : IN std_logic_vector (4 DOWNTO 0);
init : OUT std_logic;
load : OUT std_logic;
done : OUT std_logic);
END fsm ;
architecture synthesis of fsm is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
begin
Process (clk,reset) -- Process to create current state variables
begin
if (reset='0') then -- Reset State
state <= s0;
elsif (rising_edge(clk)) then
state <= nextstate; -- Set Current state
end if;
end process;
process(state,start,cnt)
begin
case state is
when s0 => -- Step 1 load regs
if start='1' then nextstate <= s1;
else nextstate <= s0; -- Wait for start signal
end if;
when s1 => -- latch result register
if cnt="11111" then nextstate <= s2; -- done
else nextstate <= s1; -- wait
end if;
when s2 =>
if start='0' then nextstate <= s0;
else nextstate <= s2; -- Wait for start signal
end if;
when others => nextstate <= s0;
end case;
end process;
process(state)
begin
case state is
when s0 =>done <= '0'; init <= '1'; load <= '0';
when s1 =>done <= '0'; init <= '0'; load <= '1';
when s2 =>done <= '1'; init <= '0'; load <= '0';
when others => done <= '-'; init <= '-'; load <= '-';
end case;
end process;
end synthesis;
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shiftn is
port (ibus : in std_logic_vector(31 downto 0);
obus : out std_logic_vector(31 downto 0);
n : in std_logic_vector(4 downto 0)); --shift by n
end shiftn;
architecture synthesis of shiftn is
begin
process(n,ibus)
begin
case n is
when "00000" => obus <= ibus(31)&ibus(30 downto 0); -- ibus
when "00001" => obus <= ibus(31)&ibus(31)&ibus(30 downto 1);
when "00010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 2);
when "00011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 3);
when "00100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 4);
when "00101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 5);
when "00110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 6);
when "00111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 7);
when "01000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 8);
when "01001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 9);
when "01010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 10);
when "01011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 11);
when "01100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 12);
when "01101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 13);
when "01110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 14);
when "01111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 15);
when "10000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 16);
when "10001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 17);
when "10010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 18);
when "10011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 19);
when "10100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 20);
when "10101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 21);
when "10110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 22);
when "10111" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 23);
when "11000" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 24);
when "11001" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 25);
when "11010" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(30 downto 26);
when "11011" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(30 downto 27);
when "11100" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(30 downto 28);
when "11101" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(30 downto 29);
when "11110" => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(30);
when others => obus <= ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31)&
ibus(31)&ibus(31)&ibus(31)&ibus(31)&ibus(31);
end case;
end process;
end synthesis;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter8/example8_5_dir/example8_5.vhd
|
1
|
1314
|
--!
--! @file: example8_5.vhd
--! @brief: adder with compoenet and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.pkg_adder.all;
--------------------------------------
entity adder is
generic (N: integer := 8);
port (
a, b: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(N-1 downto 0);
cout: out std_logic);
end entity adder;
--------------------------------------
architecture circuit of adder is
signal cin_cout: std_logic_vector(N-1 downto 0);
begin
-- first adder has cin as cin of entity
add0: full_adder port map (
a => a(0),
b => b(0),
cin => cin,
s => s(0)
cout => cin_cout(0)
);
-- middle adder have cin as cout of previous and cout as next cin
gen1: for i in 1 to N-1 generate
add1: full_adder port map (
a => a(i),
b => b(i),
cin => cin_cout(i-1),
s => s(i)
cout => cout_cout(i)
);
end generate gen1;
-- last adder's cout is cout of entity
cout <= cout_cout(N-1);
end architecture circuit;
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/filtre/function_4.vhd
|
4
|
2074
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/mandelbrot/coproc_3.vhd
|
5
|
1408
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_3 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_3 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/custom/filtre/function_5.vhd
|
4
|
2143
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.cam_pkg.all;
entity function_5 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_5 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data1, data2, data3, data4 : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff1, diff2, diff3, diff4 : UNSIGNED(7 downto 0);
variable mult1, mult2, mult3, mult4 : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data1 := UNSIGNED( INPUT_1(7 downto 0) );
data2 := UNSIGNED( INPUT_1(15 downto 8) );
data3 := UNSIGNED( INPUT_1(23 downto 16) );
data4 := UNSIGNED( INPUT_1(31 downto 24) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff1 := data1 - mini; -- 8
diff2 := data2 - mini; -- 8
diff3 := data3 - mini; -- 8
diff4 := data4 - mini; -- 8
mult1 := diff1 * beta; -- 24
mult2 := diff2 * beta; -- 24
mult3 := diff3 * beta; -- 24
mult4 := diff4 * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult1(15 downto 8));
OUTPUT_1(15 downto 8) <= std_logic_vector(mult2(15 downto 8));
OUTPUT_1(23 downto 16) <= std_logic_vector(mult3(15 downto 8));
OUTPUT_1(31 downto 24) <= std_logic_vector(mult4(15 downto 8));
end process;
--OUTPUT_1 <= INPUT_1;
-------------------------------------------------------------------------
end; --architecture logic
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/video/RGB_2_YUV.vhd
|
1
|
6656
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ims;
use ims.coprocessor.all;
use ims.conversion.all;
--
-- LES DONNEES ARRIVENT SOUS LA FORME (0x00 & B & G & R)
-- ET ELLES RESSORTENT SOUS LA FORME (0x00 & V & U & Y)
--
entity RGB_2_YUV is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end RGB_2_YUV;
architecture rtl of RGB_2_YUV is
constant s_rgb_30 : UNSIGNED(24 downto 0) := "0010011001000101101000011";
constant s_rgb_59 : UNSIGNED(24 downto 0) := "0100101100100010110100001";
constant s_rgb_11 : UNSIGNED(24 downto 0) := "0000111010010111100011010";
constant s_rgb_17 : UNSIGNED(24 downto 0) := "0001010110011001010001011";
constant s_rgb_33 : UNSIGNED(24 downto 0) := "0010101001100110101110100";
constant s_rgb_50 : UNSIGNED(24 downto 0) := "0100000000000000000000000";
constant s_rgb_42 : UNSIGNED(24 downto 0) := "0011010110010111101000100";
constant s_rgb_08 : UNSIGNED(24 downto 0) := "0000101001101000010111011";
constant s_rgb_128 : UNSIGNED(31 downto 0) := "10000000000000000000000000000000"; -- TO_UNSIGNED(128, 32); --"10000000000000000000000000000000";
signal PIPE_START : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL INPUT_R : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_G : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_B : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_Y : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_U : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL INPUT_V : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL s_rgb_out_y : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cb : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL s_rgb_out_cr : UNSIGNED(32 downto 0) := (others => '0');
SIGNAL rgb_in_r_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Y : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cb : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_r_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_g_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
SIGNAL rgb_in_b_reg_Cr : UNSIGNED(32 downto 0):= (others => '0');
begin
INPUT_R <= INPUT_1( 7 downto 0);
INPUT_G <= INPUT_1(15 downto 8);
INPUT_B <= INPUT_1(23 downto 16);
OUTPUT_1 <= "00000000" & INPUT_V & INPUT_U & INPUT_Y;
-- NOUS NECESSITONS N CYCLES MAIS LE SIGNAL nREADY PEUT
-- ETRE SOUMIS 2 CYCLES AVANT LA FIN ;-)
nready <= PIPE_START(1);
ready <= PIPE_START(1) OR PIPE_START(0) OR start;
icc <= "0000";
process(rst, clk)
begin
if rst = '0' then
INPUT_Y <= (others => '0');
INPUT_U <= (others => '0');
INPUT_V <= (others => '0');
PIPE_START <= "0000";
elsif rising_edge(clk) then
if (flush = '1') then
PIPE_START <= "0000";
elsif (holdn = '0') then
PIPE_START <= PIPE_START;
else
-- ON NE REAGIT PAS IMMEDIATEMENT LORSQUE L'ON RECOIT LE SIGNAL
-- START CAR IL EST DELIVRE PAR L'ETAGE DE DECODAGE (LES ENTREES
-- DU CALCUL NE SERONT DISPONIBLES QU'UN CYCLE APRES).
PIPE_START <= PIPE_START(2 downto 0) & start;
--if start = '1' then
--REPORT "COMPUTATION START...";
--printmsg("(RGB) ===> (000) COMPUTATION START...");
--end if;
-- ON MULTIPLIE LES DONNEES ENTRANTES PAR LES CONSTANTES
-- CODEES EN VIRGULE FIXE
if PIPE_START(0) = '1' then
--REPORT "RUNNING FIRST SLICE...";
--printmsg("(RGB) ===> (001) RUNNING FIRST SLICE...");
--printmsg("(RGB) ===> (001) DATA ARE (" & to_int_str(INPUT_B,6) & ", " & to_int_str(INPUT_G,6) & ", " & to_int_str(INPUT_R,6) & ")");
rgb_in_r_reg_Y <= s_rgb_30 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Y <= s_rgb_59 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Y <= s_rgb_11 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cb <= s_rgb_17 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cb <= s_rgb_33 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cb <= s_rgb_50 * UNSIGNED(INPUT_B);
rgb_in_r_reg_Cr <= s_rgb_50 * UNSIGNED(INPUT_R);
rgb_in_g_reg_Cr <= s_rgb_42 * UNSIGNED(INPUT_G);
rgb_in_b_reg_Cr <= s_rgb_08 * UNSIGNED(INPUT_B);
end if;
if PIPE_START(1) = '1' then
--REPORT "RUNNING SECOND SLICE...";
--printmsg("(RGB) ===> (010) RUNNING SECOND SLICE...");
s_rgb_out_y <= rgb_in_r_reg_Y + (rgb_in_g_reg_Y + rgb_in_b_reg_Y);
s_rgb_out_cb <= (s_rgb_128 - rgb_in_r_reg_Cb) - (rgb_in_g_reg_Cb + rgb_in_b_reg_Cb);
s_rgb_out_cr <= (s_rgb_128 + rgb_in_r_reg_Cr) - (rgb_in_g_reg_Cr - rgb_in_b_reg_Cr);
end if;
if PIPE_START(2) = '1' then
--REPORT "RUNNING THIRD SLICE...";
--printmsg("(RGB) ===> (011) RUNNING THIRD SLICE...");
if (s_rgb_out_y(23)='1') then
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24) + 1);
else
INPUT_Y <= STD_LOGIC_VECTOR(s_rgb_out_y(31 downto 24));
end if;
if (s_rgb_out_cb(23)='1') then
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24) + 1);
else
INPUT_U <= STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24));
end if;
if (s_rgb_out_cr(23)='1') then
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24) + 1);
else
INPUT_V <= STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24));
end if;
--printmsg("(PGDC) ===> (011) DATA Y = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_y (31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA U = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cb(31 downto 24)),6) & ")");
--printmsg("(PGDC) ===> (011) DATA V = (" & to_int_str( STD_LOGIC_VECTOR(s_rgb_out_cr(31 downto 24)),6) & ")");
else
INPUT_Y <= INPUT_Y;
INPUT_U <= INPUT_U;
INPUT_V <= INPUT_V;
end if;
end if;
end if;
end process;
--process(INPUT_Y, INPUT_U, INPUT_V)
--BEGIN
-- printmsg("(PGDC) ===> (111) DATA ARE (" & to_int_str(INPUT_V,6) & ", " & to_int_str(INPUT_U,6) & ", " & to_int_str(INPUT_Y,6) & ")");
--END PROCESS;
end rtl;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter6/exercise6_11_dir/exercise6_11.vhd
|
1
|
3949
|
--!
--! @file: exercise6_11.vhd
--! @brief: Frequency Meter with SSDs
--! @author: Antonio Gutierrez
--! @date: 2013-10-28
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity frequency_meter is
generic (fclk: positive := 50_000_000;
clk_divider: positive := 50_000);
port (
input: in std_logic; -- signal to measure
clk: in std_logic; -- clk
ssd1: out std_logic_vector(6 downto 0);
ssd2: out std_logic_vector(6 downto 0);
ssd3: out std_logic_vector(6 downto 0));
end entity frequency_meter;
--------------------------------------
architecture circuit of frequency_meter is
signal one_sec: std_logic;
signal output1: integer range 0 to 10;
signal output2: integer range 0 to 10;
signal output3: integer range 0 to 10;
begin
-- create one second window
proc: process (clk)
variable one_sec: integer range 0 to fclk+1 := 0;
begin
if (clk'event and clk = '1') then
count := count + 1;
if (count = fclk + 1) then
count := 0;
one_sec <= '1';
else
one_sec <= '0';
end if;
end if;
end process proc;
-- count number of input pulses in that time window
proc1: process (input, one_sec)
variable count1: integer range 0 to 10;
variable count2: integer range 0 to 10;
variable count3: integer range 0 to 10;
variable count4: integer range 0 to 10;
variable count5: integer range 0 to 10;
begin
if (one_sec = '1') then
count1 := 0;
count2 := 0;
count3 := 0;
count4 := 0;
count5 := 0;
elsif (input'event and input = '1') then
count1 := count1 + 1;
if (count1 = 10) then
count1 := 0;
count2 := count2 + 1;
if (count2 = 10) then
count2 := 0;
count3 := count3 + 1;
if (count3 = 10) then
count3 := 0;
count4 := count4 + 1;
if (count4 = 10) then
count4 := 0;
count5 := count5 + 1;
end if;
end if;
end if;
end if;
end if;
-- store outputs to SSD
if (one_sec'event and one_sec = '1') then
output1 <= count5;
output2 <= count4;
output3 <= count3;
end if;
end process proc1;
-- SSD circuits
with output1 select
ssd1 <= '0000000' when 0,
'0000001' when 1,
'0000001' when 2,
'0000001' when 3,
'0000001' when 4,
'0000001' when 5,
'0000001' when 6,
'0000001' when 7,
'0000001' when 8,
'0000001' when others;
with output2 select
ssd2 <= '0000000' when 0,
'0000001' when 1,
'0000001' when 2,
'0000001' when 3,
'0000001' when 4,
'0000001' when 5,
'0000001' when 6,
'0000001' when 7,
'0000001' when 8,
'0000001' when others;
with output3 select
ssd3 <= '0000000' when 0,
'0000001' when 1,
'0000001' when 2,
'0000001' when 3,
'0000001' when 4,
'0000001' when 5,
'0000001' when 6,
'0000001' when 7,
'0000001' when 8,
'0000001' when others;
end architecture circuit;
--------------------------------------
|
gpl-3.0
|
karvonz/Mandelbrot
|
soc_plasma/vhdl/plasma_core/vhdl/ims/to_trash/OTHERS/DIVIDER_32b.vhd
|
1
|
4818
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
--library ims;
--use ims.coprocessor.all;
--use ims.conversion.all;
entity DIVIDER_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end DIVIDER_32b;
-- ready = 0 indique que le circuit est pret a calculer
-- 1 signifie que le circuit est occupe
-- nready = 1 indique que le calcul est termine (1 cycle suffit)
architecture behav of DIVIDER_32b is
signal buf : STD_LOGIC_VECTOR(63 downto 0);
signal dbuf : STD_LOGIC_VECTOR(31 downto 0);
signal sm : INTEGER range 0 to 32;
alias buf1 is buf(63 downto 32);
alias buf2 is buf(31 downto 0);
signal start_delay : std_logic;
begin
-------------------------------------------------------------------------
-- synthesis translate_off
-- process
-- begin
-- wait for 1 ns;
-- ASSERT false REPORT "(IMS) DIVIDER_32b : ALLOCATION OK !";
-- wait;
-- end process;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
reg : process(rst, clk)
variable sready, snready : std_logic;
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
start_delay <= '0';
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
start_delay <= '0';
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
start_delay <= start_delay;
-- Sinon on déroule l'execution de la division
else
start_delay <= start;
case sm is
-- Etat d'attente du signal start
when 0 =>
--buf1 <= (others => '0');
--buf2 <= INPUT_1;
--dbuf <= INPUT_2;
OUTPUT_1 <= buf2;
if start_delay = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
-- printmsg("(mDIV) ===> (000) THE START SIGNAL HAS BEEN RECEIVED !");
-- printmsg("(mDIV) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- printmsg("(mDIV) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
else
--printmsg("(mDIV) ===> (000) WAITING FOR THE START SIGNAL...");
sm <= sm;
end if;
-- when 1 =>
-- printmsg("(mDIV) ===> (001) READING THE INPUT DATA");
-- buf1 <= (others => '0');
-- buf2 <= INPUT_1;
-- dbuf <= INPUT_2;
-- sm <= sm + 1; -- le calcul est en cours
-- if ( (INPUT_1(30) /= '-') AND (INPUT_1(30) /= 'X') AND (INPUT_1(30) /= 'U')) then
-- printmsg("(mDIV) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(INPUT_1,6) & ")");
-- end if;
-- if ( (INPUT_2(30) /= '-') AND (INPUT_2(30) /= 'X') AND (INPUT_2(30) /= 'U')) then
-- printmsg("(mDIV) ===> (OP2) MEMORISATION PROCESS (" & to_int_str(INPUT_2,6) & ")");
-- end if;
-- when 34 =>
-- OUTPUT_1 <= buf2;
-- snready := '1'; -- le resultat du calcul est disponible
-- sm <= 0;
-- printmsg("(mDIV) ===> (010) THE COMPUTATION IS FINISHED :-)");
-- Tous les autres états sont utiles au calcul
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
if buf(62 downto 31) >= dbuf then
buf1 <= '0' & (buf(61 downto 31) - dbuf(30 downto 0));
buf2 <= buf2(30 downto 0) & '1';
else
buf <= buf(62 downto 0) & '0';
end if;
if sm /= 32 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
--OUTPUT_1 <= buf2(30 downto 0) & '1';
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
-- printmsg("(mDIV) ===> (OP1) MEMORISATION PROCESS (" & to_int_str(buf2(30 downto 0) & '1',6) & ")");
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if; -- Fin du process de calcul
end if;
end process;
end behav;
|
gpl-3.0
|
chibby0ne/vhdl-book
|
Chapter11/exercise2_dir/exercise2.vhd
|
12226531
|
0
|
gpl-3.0
|
|
grwlf/vsim
|
vhdl_ct/ct00433.vhd
|
1
|
5120
|
-- NEED RESULT: ARCH00433.Chk_s3: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00433.Chk_s2: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00433.Chk_s1: Guarded assignment controlled by implicit guard passed
-- NEED RESULT: ARCH00433.Chk_gs3: Guarded assignment controlled by explicit guard passed
-- NEED RESULT: ARCH00433.Chk_gs2: Guarded assignment controlled by explicit guard passed
-- NEED RESULT: ARCH00433.Chk_gs1: Guarded assignment controlled by explicit guard passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00433
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (4)
-- 9.5 (5)
-- 9.5 (9)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00433)
-- ENT00433_Test_Bench(ARCH00433_Test_Bench)
--
-- REVISION HISTORY:
--
-- 4-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00433 of E00000 is
signal Control, s1, s2, s3 : boolean := false ;
signal Guard, gs1, gs2, gs3 : boolean := false ;
begin
B1 :
block ( Control ) -- Implicit Guard Signal
begin
s1 <= guarded transport Not s1 after 5 ns ;
s2 <= guarded transport False after 5 ns when s2 else
True after 5 ns ;
with s3 select
s3 <= guarded transport False after 5 ns when True,
True after 5 ns when others ;
end block B1 ;
Control <= transport True after 10 ns, False after 11 ns ;
Chk_s1 :
process ( s1 )
variable SavTime : Time ;
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00433.Chk_s1" ,
"Guarded assignment controlled by implicit guard" ,
s1 and ((SavTime+15 ns) = Std.Standard.Now) ) ;
end if ;
end process Chk_s1 ;
Chk_s2 :
process ( s2 )
variable SavTime : Time ;
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00433.Chk_s2" ,
"Guarded assignment controlled by implicit guard" ,
s2 and ((SavTime+15 ns) = Std.Standard.Now) ) ;
end if ;
end process Chk_s2 ;
Chk_s3 :
process ( s3 )
variable SavTime : Time ;
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00433.Chk_s3" ,
"Guarded assignment controlled by implicit guard" ,
s3 and ((SavTime+15 ns) = Std.Standard.Now) ) ;
end if ;
end process Chk_s3 ;
-- The following depend on the explicit signal Guard
gs1 <= guarded transport Not gs1 after 5 ns ;
gs2 <= guarded transport False after 5 ns when gs2 else
True after 5 ns ;
with gs3 select
gs3 <= guarded transport False after 5 ns when True,
True after 5 ns when others ;
Guard <= transport True after 100 ns, False after 101 ns ;
Chk_gs1 :
process ( gs1 )
variable SavTime : Time ;
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00433.Chk_gs1" ,
"Guarded assignment controlled by explicit guard" ,
gs1 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
end if ;
end process Chk_gs1 ;
Chk_gs2 :
process ( gs2 )
variable SavTime : Time ;
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00433.Chk_gs2" ,
"Guarded assignment controlled by explicit guard" ,
gs2 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
end if ;
end process Chk_gs2 ;
Chk_gs3 :
process ( gs3 )
variable SavTime : Time ;
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00433.Chk_gs3" ,
"Guarded assignment controlled by explicit guard" ,
gs3 and ((SavTime+105 ns) = Std.Standard.Now) ) ;
end if ;
end process Chk_gs3 ;
end ARCH00433 ;
entity ENT00433_Test_Bench is
end ENT00433_Test_Bench ;
architecture ARCH00433_Test_Bench of ENT00433_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00433 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00433_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/fifo_generator_ramfifo.vhd
|
9
|
77825
|
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`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00088.vhd
|
1
|
72595
|
-- NEED RESULT: ARCH00088.P1: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P2: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P3: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P4: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P5: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P6: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P7: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P8: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P9: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P10: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P11: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P12: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P13: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P14: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P15: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P16: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088.P17: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00088: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00088
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00088(ARCH00088)
-- ENT00088_Test_Bench(ARCH00088_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00088 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_boolean_vector : inout st_boolean_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_boolean_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_bit_vector : inout st_bit_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_bit_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_severity_level_vector : inout st_severity_level_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_severity_level_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_st_string : inout st_string ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_string : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1_vector : inout st_enum1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_st_integer_vector : inout st_integer_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_integer_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1_vector : inout st_int1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_st_time_vector : inout st_time_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_time_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1_vector : inout st_phys1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_st_real_vector : inout st_real_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1_vector : inout st_real1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00088.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00088" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00088" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00088 ;
--
architecture ARCH00088 of ENT00088 is
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_boolean_vector,
counter,
correct,
savtime,
chk_st_boolean_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_bit_vector,
counter,
correct,
savtime,
chk_st_bit_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_severity_level_vector,
counter,
correct,
savtime,
chk_st_severity_level_vector
) ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_st_string,
counter,
correct,
savtime,
chk_st_string
) ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1_vector,
counter,
correct,
savtime,
chk_st_enum1_vector
) ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_st_integer_vector,
counter,
correct,
savtime,
chk_st_integer_vector
) ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1_vector,
counter,
correct,
savtime,
chk_st_int1_vector
) ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_st_time_vector,
counter,
correct,
savtime,
chk_st_time_vector
) ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1_vector,
counter,
correct,
savtime,
chk_st_phys1_vector
) ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_st_real_vector,
counter,
correct,
savtime,
chk_st_real_vector
) ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1_vector,
counter,
correct,
savtime,
chk_st_real1_vector
) ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
end process P17 ;
--
--
end ARCH00088 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00088_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00088_Test_Bench ;
--
architecture ARCH00088_Test_Bench of ENT00088_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00088 ( ARCH00088 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00088_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00305.vhd
|
1
|
3753
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00305
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.1 (9)
-- 9.1 (10)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00305_1(ARCH00305_1)
-- E00000(ARCH00305)
-- ENT00305_Test_Bench(ARCH00305_Test_Bench)
--
-- REVISION HISTORY:
--
-- 27-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
entity ENT00305_1 is
generic ( G : Integer ) ;
port ( Pout : out Integer := 1 ) ;
end ENT00305_1 ;
architecture ARCH00305_1 of ENT00305_1 is
begin
Pout <= transport G after 10 ns ;
end ARCH00305_1 ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00305 of E00000 is
begin
L1 :
block
type T is (e1,e2,e3,e4) ;
subtype ST is T;
subtype st_int1 is Integer range 0 to 3 ;
type UA is array ( Integer range <> ) of T ;
subtype CA is UA ( st_int1 ) ;
constant C : st_int1 := st_int1'Low ; -- e1
signal SA : CA := (e2, e2, e3, e3) ;
alias S0 : ST is SA(C) ;
alias S1 : ST is SA(1) ;
alias S2 : ST is SA(2) ;
alias S3 : ST is SA(st_int1'High) ;
component Comp
generic ( G : Integer ) ;
port ( Pout : out Integer := 1 ) ;
end component ;
for all : Comp use entity WORK.ENT00305_1 ( ARCH00305_1 );
attribute Attr : boolean ;
attribute Attr of SA : signal is True ;
procedure Proc ( Did_Proc : out boolean ) ;
function To_ST ( constant P : Integer ) return ST is
begin
return ST'Val (P) ;
end To_ST ;
procedure Proc ( Did_Proc : out boolean ) is
begin
Did_Proc := True ;
end Proc ;
signal Check_it, Woke_Up : boolean := false ;
begin
A_CIS : Comp
generic map ( C ) -- e1
port map ( To_ST (Pout) => S1 ) ; -- SA(1)
A_SigAsg : Check_it <= transport True after 100 ns ;
A_Process :
process ( Check_it )
variable first_time : boolean := true ;
begin
if Not first_time then
test_report ( "ARCH00305" ,
"Test Completed" ,
Woke_Up ) ;
else
first_time := false ;
end if ;
end process A_Process ;
A_Block :
block
begin
P :
process ( SA )
variable first_time : boolean := true ;
variable Did_Proc : boolean := false ;
begin
if Not first_time then
Proc (Did_Proc) ;
test_report ( "ARCH00305" ,
"Block declarations/statements test" ,
Did_Proc and
(SA(0) = e2) and
(SA(1) = e1) and
(SA(2) = e3) and
(SA(3) = e3) ) ;
Woke_Up <= transport True ;
else
first_time := false ;
end if ;
end process P ;
end block A_Block ;
A_Generate :
for I in 1 to 1 generate
process
begin
test_report ( "ARCH00305" ,
"Generate Statement" ,
True ) ;
wait ;
end process ;
end generate A_Generate ;
A_Assert : assert Not SA'Attr
report "Concurrent Assertion Passed"
severity Note ;
end block L1 ;
end ARCH00305 ;
entity ENT00305_Test_Bench is
end ENT00305_Test_Bench ;
architecture ARCH00305_Test_Bench of ENT00305_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00305 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00305_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0_defaults.vhd
|
9
|
30146
|
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1w+feXbi3Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dc_ss.vhd
|
9
|
8726
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dc_ss.vhd
|
9
|
8726
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Swj+wTEC1o3iQ9g+3ut4LlrwOvF86ePmdejwf2cl9eKar3XozVQMIgMwKSpwqzDg/1lIBWkVtymD
KO0KFKUg1g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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gifL3YEfWBDwmDaSv8w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00384.vhd
|
1
|
104055
|
-- NEED RESULT: ARCH00384.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00384: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00384
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00384(ARCH00384)
-- ENT00384_Test_Bench(ARCH00384_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00384 is
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
end ENT00384 ;
--
--
architecture ARCH00384 of ENT00384 is
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when boolean_select = 1 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 2 else
--
c_boolean_1 after 5 ns
when boolean_select = 3 else
--
c_boolean_1 after 100 ns
when boolean_select = 4 else
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when boolean_select = 5 else
--
-- Last transaction above is marked
c_boolean_1 after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when bit_select = 1 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 2 else
--
c_bit_1 after 5 ns
when bit_select = 3 else
--
c_bit_1 after 100 ns
when bit_select = 4 else
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when bit_select = 5 else
--
-- Last transaction above is marked
c_bit_1 after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when severity_level_select = 1 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 2 else
--
c_severity_level_1 after 5 ns
when severity_level_select = 3 else
--
c_severity_level_1 after 100 ns
when severity_level_select = 4 else
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when severity_level_select = 5 else
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when character_select = 1 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 2 else
--
c_character_1 after 5 ns
when character_select = 3 else
--
c_character_1 after 100 ns
when character_select = 4 else
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when character_select = 5 else
--
-- Last transaction above is marked
c_character_1 after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when st_enum1_select = 1 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 2 else
--
c_st_enum1_1 after 5 ns
when st_enum1_select = 3 else
--
c_st_enum1_1 after 100 ns
when st_enum1_select = 4 else
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when st_enum1_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when integer_select = 1 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 2 else
--
c_integer_1 after 5 ns
when integer_select = 3 else
--
c_integer_1 after 100 ns
when integer_select = 4 else
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when integer_select = 5 else
--
-- Last transaction above is marked
c_integer_1 after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when st_int1_select = 1 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 2 else
--
c_st_int1_1 after 5 ns
when st_int1_select = 3 else
--
c_st_int1_1 after 100 ns
when st_int1_select = 4 else
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when st_int1_select = 5 else
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when time_select = 1 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 2 else
--
c_time_1 after 5 ns
when time_select = 3 else
--
c_time_1 after 100 ns
when time_select = 4 else
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when time_select = 5 else
--
-- Last transaction above is marked
c_time_1 after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when st_phys1_select = 1 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 2 else
--
c_st_phys1_1 after 5 ns
when st_phys1_select = 3 else
--
c_st_phys1_1 after 100 ns
when st_phys1_select = 4 else
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when st_phys1_select = 5 else
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when real_select = 1 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 2 else
--
c_real_1 after 5 ns
when real_select = 3 else
--
c_real_1 after 100 ns
when real_select = 4 else
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when real_select = 5 else
--
-- Last transaction above is marked
c_real_1 after 40 ns ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when st_real1_select = 1 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 2 else
--
c_st_real1_1 after 5 ns
when st_real1_select = 3 else
--
c_st_real1_1 after 100 ns
when st_real1_select = 4 else
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when st_real1_select = 5 else
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when st_rec1_select = 1 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 2 else
--
c_st_rec1_1 after 5 ns
when st_rec1_select = 3 else
--
c_st_rec1_1 after 100 ns
when st_rec1_select = 4 else
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when st_rec1_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when st_rec2_select = 1 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 2 else
--
c_st_rec2_1 after 5 ns
when st_rec2_select = 3 else
--
c_st_rec2_1 after 100 ns
when st_rec2_select = 4 else
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when st_rec2_select = 5 else
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when st_arr1_select = 1 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 2 else
--
c_st_arr1_1 after 5 ns
when st_arr1_select = 3 else
--
c_st_arr1_1 after 100 ns
when st_arr1_select = 4 else
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when st_arr1_select = 5 else
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1 after 5 ns
when st_arr2_select = 3 else
--
c_st_arr2_1 after 100 ns
when st_arr2_select = 4 else
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when st_arr2_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00384" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when st_arr3_select = 1 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 2 else
--
c_st_arr3_1 after 5 ns
when st_arr3_select = 3 else
--
c_st_arr3_1 after 100 ns
when st_arr3_select = 4 else
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when st_arr3_select = 5 else
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns ;
--
end ARCH00384 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00384_Test_Bench is
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
end ENT00384_Test_Bench ;
--
--
architecture ARCH00384_Test_Bench of ENT00384_Test_Bench is
begin
L1:
block
component UUT
port (
s_boolean : inout boolean
; s_bit : inout bit
; s_severity_level : inout severity_level
; s_character : inout character
; s_st_enum1 : inout st_enum1
; s_integer : inout integer
; s_st_int1 : inout st_int1
; s_time : inout time
; s_st_phys1 : inout st_phys1
; s_real : inout real
; s_st_real1 : inout st_real1
; s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
; s_st_arr1 : inout st_arr1
; s_st_arr2 : inout st_arr2
; s_st_arr3 : inout st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00384 ( ARCH00384 ) ;
begin
CIS1 : UUT
port map (
s_boolean
, s_bit
, s_severity_level
, s_character
, s_st_enum1
, s_integer
, s_st_int1
, s_time
, s_st_phys1
, s_real
, s_st_real1
, s_st_rec1
, s_st_rec2
, s_st_rec3
, s_st_arr1
, s_st_arr2
, s_st_arr3
)
;
end block L1 ;
end ARCH00384_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00618.vhd
|
1
|
14674
|
-- NEED RESULT: ARCH00618: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00618: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00618: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00618.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00618.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00618.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00618: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00618: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00618: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00618: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00618: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00618: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00618: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00618: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00618: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00618
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00618(ARCH00618)
-- ENT00618_Test_Bench(ARCH00618_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00618 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00618 ;
--
--
architecture ARCH00618 of ENT00618 is
subtype chk_time_type is Time ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
--
procedure P1
(signal s_st_rec1 : in st_rec1 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1.f2 <= transport
-- c_st_rec1_2.f2 after 10 ns,
-- c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec1.f2 <= transport
-- c_st_rec1_2.f2 after 10 ns ,
-- c_st_rec1_1.f2 after 20 ns ,
-- c_st_rec1_2.f2 after 30 ns ,
-- c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 =
c_st_rec1_2.f2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec1.f2 <= transport
-- c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
s_st_rec1.f2 =
c_st_rec1_1.f2 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00618" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00618" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec1_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_rec2 : in st_rec2 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2.f2 <= transport
-- c_st_rec2_2.f2 after 10 ns,
-- c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec2.f2 <= transport
-- c_st_rec2_2.f2 after 10 ns ,
-- c_st_rec2_1.f2 after 20 ns ,
-- c_st_rec2_2.f2 after 30 ns ,
-- c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 =
c_st_rec2_2.f2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec2.f2 <= transport
-- c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
s_st_rec2.f2 =
c_st_rec2_1.f2 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00618" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00618" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec2_cnt + 1 ;
--
end ;
--
procedure P3
(signal s_st_rec3 : in st_rec3 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2 <= transport
-- c_st_rec3_2.f2 after 10 ns,
-- c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec3.f2 <= transport
-- c_st_rec3_2.f2 after 10 ns ,
-- c_st_rec3_1.f2 after 20 ns ,
-- c_st_rec3_2.f2 after 30 ns ,
-- c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 =
c_st_rec3_2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec3.f2 <= transport
-- c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
s_st_rec3.f2 =
c_st_rec3_1.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00618" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00618" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00618" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec3_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_rec1 ,
st_rec1_select ,
s_st_rec1_savt ,
chk_st_rec1 ,
s_st_rec1_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec1_select select
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns
when 1,
--
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns
when 2,
--
c_st_rec1_1.f2 after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_rec2 ,
st_rec2_select ,
s_st_rec2_savt ,
chk_st_rec2 ,
s_st_rec2_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_rec2_select select
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns
when 1,
--
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns
when 2,
--
c_st_rec2_1.f2 after 5 ns when 3 ;
--
CHG3 :
P3(
s_st_rec3 ,
st_rec3_select ,
s_st_rec3_savt ,
chk_st_rec3 ,
s_st_rec3_cnt ) ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_rec3_select select
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns
when 1,
--
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns
when 2,
--
c_st_rec3_1.f2 after 5 ns when 3 ;
--
end ARCH00618 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00618_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00618_Test_Bench ;
--
--
architecture ARCH00618_Test_Bench of ENT00618_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00618 ( ARCH00618 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
)
;
end block L1 ;
end ARCH00618_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00323.vhd
|
1
|
1441
|
-- NEED RESULT: *** An assertion follows with severity level WARNING
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00323
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00323)
-- ENT00323_Test_Bench(ARCH00323_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match the comment messages output.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00323 of E00000 is
signal Dummy : Boolean := false;
begin
P1 :
process ( Dummy )
begin
print ("*** An assertion follows with severity level WARNING") ;
end process P1 ;
assert Dummy
report "An assertion with severity WARNING"
severity Severity_Level'Succ (NOTE) ;
end ARCH00323 ;
entity ENT00323_Test_Bench is
end ENT00323_Test_Bench ;
architecture ARCH00323_Test_Bench of ENT00323_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00323 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00323_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo_generator_v10_0_pkg.vhd
|
9
|
129958
|
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|
gpl-3.0
|
dcliche/mdsynth
|
rtl/src/timer.vhd
|
1
|
5653
|
--===========================================================================--
-- --
-- Synthesizable 8 bit Timer --
-- --
--===========================================================================--
--
-- File name : timer.vhd
--
-- Entity name : timer
--
-- Purpose : 8 bit timer module for System09
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : None
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Registers :
--
-- IO address + 0 Read - Down Count register
-- Bits[7..0] = Counter Value
--
-- IO address + 0 Write - Preset Count register
-- Bits[7..0] = Preset Value
--
-- IO address + 1 Read - Status register
-- Bit[7] = Interrupt Flag
-- Bits[6..0] = undefined
--
-- IO address + 1 Write - Control register
-- Bit[7] = Interrupt Enable
-- Bits[6..1] = Unedfined
-- Bit[0] = Counter enable
--
-- Operation :
--
-- Write count to counter register
-- Enable counter by setting bit 0 of the control register
-- Enable interrupts by setting bit 7 of the control register
-- Counter will count down to zero
-- When it reaches zero the terminal flag is set
-- If the interrupt is enabled an interrupt is generated
-- The interrupt may be disabled by writing a 0 to bit 7
-- of the control register or by loading a new down count
-- into the counter register.
--
-- Copyright (C) 2002 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Date Author Changes
--
-- 0.1 2002-09-06 John Kent Converted to a single timer
-- Made synchronous with system clock
-- 1.0 2003-09-06 John Kent Changed Clock Edge
-- Released to opencores.org
-- 2.0 2008-02-05 John Kent Removed Timer inputs and outputs
-- Made into a simple 8 bit interrupt down counter
-- 2.1 2010-06-17 John Kent Updated header and added GPL
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
addr : in std_logic;
rw : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end;
architecture rtl of timer is
signal timer_ctrl : std_logic_vector(7 downto 0);
signal timer_stat : std_logic_vector(7 downto 0);
signal timer_count : std_logic_vector(7 downto 0);
signal timer_term : std_logic; -- Timer terminal count
--
-- control/status register bits
--
constant BIT_ENB : integer := 0; -- 0=disable, 1=enabled
constant BIT_IRQ : integer := 7; -- 0=disabled, 1-enabled
begin
--------------------------------
--
-- write control registers
--
--------------------------------
timer_control : process( clk, rst, cs, rw, addr, data_in,
timer_ctrl, timer_term, timer_count )
begin
if clk'event and clk = '0' then
if rst = '1' then
timer_count <= (others=>'0');
timer_ctrl <= (others=>'0');
timer_term <= '0';
elsif cs = '1' and rw = '0' then
if addr='0' then
timer_count <= data_in;
timer_term <= '0';
else
timer_ctrl <= data_in;
end if;
else
if (timer_ctrl(BIT_ENB) = '1') then
if (timer_count = "00000000" ) then
timer_term <= '1';
else
timer_count <= timer_count - 1;
end if;
end if;
end if;
end if;
end process;
--
-- timer status register
--
timer_status : process( timer_ctrl, timer_term )
begin
timer_stat(6 downto 0) <= timer_ctrl(6 downto 0);
timer_stat(BIT_IRQ) <= timer_term;
end process;
--
-- timer data output mux
--
timer_data_out : process( addr, timer_count, timer_stat )
begin
if addr = '0' then
data_out <= timer_count;
else
data_out <= timer_stat;
end if;
end process;
--
-- read timer strobe to reset interrupts
--
timer_interrupt : process( timer_term, timer_ctrl )
begin
irq <= timer_term and timer_ctrl(BIT_IRQ);
end process;
end rtl;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_logic_pkt_fifo.vhd
|
9
|
31657
|
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21696)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00381.vhd
|
1
|
101079
|
-- NEED RESULT: ARCH00381.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P10: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P11: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P12: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P13: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P14: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P15: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P16: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381.P17: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00381: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P17: Inertial transactions completed entirely passed
-- NEED RESULT: P16: Inertial transactions completed entirely passed
-- NEED RESULT: P15: Inertial transactions completed entirely passed
-- NEED RESULT: P14: Inertial transactions completed entirely passed
-- NEED RESULT: P13: Inertial transactions completed entirely passed
-- NEED RESULT: P12: Inertial transactions completed entirely passed
-- NEED RESULT: P11: Inertial transactions completed entirely passed
-- NEED RESULT: P10: Inertial transactions completed entirely passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00381
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00381(ARCH00381)
-- ENT00381_Test_Bench(ARCH00381_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00381 is
end ENT00381 ;
--
--
architecture ARCH00381 of ENT00381 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <=
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <=
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 4 ;
-- s_boolean <=
-- c_boolean_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 5 ;
-- s_boolean <=
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
boolean_select <= transport 6 ;
-- Last transaction above is marked
-- s_boolean <=
-- c_boolean_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
wait until (not s_boolean'Quiet) and
(s_boolean_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_boolean = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <=
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns
when 3,
--
c_boolean_1 after 100 ns
when 4,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_boolean_1 after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <=
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <=
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 4 ;
-- s_bit <=
-- c_bit_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 5 ;
-- s_bit <=
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
bit_select <= transport 6 ;
-- Last transaction above is marked
-- s_bit <=
-- c_bit_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
wait until (not s_bit'Quiet) and
(s_bit_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_bit = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <=
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns
when 3,
--
c_bit_1 after 100 ns
when 4,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_bit_1 after 40 ns when 6 ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <=
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 4 ;
-- s_severity_level <=
-- c_severity_level_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 5 ;
-- s_severity_level <=
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
severity_level_select <= transport 6 ;
-- Last transaction above is marked
-- s_severity_level <=
-- c_severity_level_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
wait until (not s_severity_level'Quiet) and
(s_severity_level_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_severity_level = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <=
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns
when 3,
--
c_severity_level_1 after 100 ns
when 4,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_severity_level_1 after 40 ns when 6 ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <=
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <=
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 4 ;
-- s_character <=
-- c_character_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 5 ;
-- s_character <=
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
character_select <= transport 6 ;
-- Last transaction above is marked
-- s_character <=
-- c_character_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
wait until (not s_character'Quiet) and
(s_character_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_character = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <=
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns
when 3,
--
c_character_1 after 100 ns
when 4,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_character_1 after 40 ns when 6 ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 4 ;
-- s_st_enum1 <=
-- c_st_enum1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 5 ;
-- s_st_enum1 <=
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1 <=
-- c_st_enum1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
wait until (not s_st_enum1'Quiet) and
(s_st_enum1_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_enum1 = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <=
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns
when 3,
--
c_st_enum1_1 after 100 ns
when 4,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_enum1_1 after 40 ns when 6 ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <=
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <=
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 4 ;
-- s_integer <=
-- c_integer_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 5 ;
-- s_integer <=
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
integer_select <= transport 6 ;
-- Last transaction above is marked
-- s_integer <=
-- c_integer_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
wait until (not s_integer'Quiet) and
(s_integer_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_integer = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <=
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns
when 3,
--
c_integer_1 after 100 ns
when 4,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_integer_1 after 40 ns when 6 ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <=
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 4 ;
-- s_st_int1 <=
-- c_st_int1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 5 ;
-- s_st_int1 <=
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_int1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_int1 <=
-- c_st_int1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
wait until (not s_st_int1'Quiet) and
(s_st_int1_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_int1 = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <=
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns
when 3,
--
c_st_int1_1 after 100 ns
when 4,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_int1_1 after 40 ns when 6 ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <=
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <=
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 4 ;
-- s_time <=
-- c_time_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 5 ;
-- s_time <=
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
time_select <= transport 6 ;
-- Last transaction above is marked
-- s_time <=
-- c_time_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
wait until (not s_time'Quiet) and
(s_time_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_time = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <=
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns
when 3,
--
c_time_1 after 100 ns
when 4,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_time_1 after 40 ns when 6 ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 4 ;
-- s_st_phys1 <=
-- c_st_phys1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 5 ;
-- s_st_phys1 <=
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_phys1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_phys1 <=
-- c_st_phys1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
wait until (not s_st_phys1'Quiet) and
(s_st_phys1_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_phys1 = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <=
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns
when 3,
--
c_st_phys1_1 after 100 ns
when 4,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_phys1_1 after 40 ns when 6 ;
--
CHG10 :
process
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <=
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P10" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <=
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 4 ;
-- s_real <=
-- c_real_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 5 ;
-- s_real <=
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
real_select <= transport 6 ;
-- Last transaction above is marked
-- s_real <=
-- c_real_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
wait until (not s_real'Quiet) and
(s_real_savt /= Std.Standard.Now) ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions completed entirely",
chk_real = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <=
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns
when 3,
--
c_real_1 after 100 ns
when 4,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_real_1 after 40 ns when 6 ;
--
CHG11 :
process
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P11" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <=
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 4 ;
-- s_st_real1 <=
-- c_st_real1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 5 ;
-- s_st_real1 <=
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real1 <=
-- c_st_real1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
wait until (not s_st_real1'Quiet) and
(s_st_real1_savt /= Std.Standard.Now) ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions completed entirely",
chk_st_real1 = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <=
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns
when 3,
--
c_st_real1_1 after 100 ns
when 4,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_real1_1 after 40 ns when 6 ;
--
CHG12 :
process
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P12" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 4 ;
-- s_st_rec1 <=
-- c_st_rec1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 5 ;
-- s_st_rec1 <=
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1 <=
-- c_st_rec1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
wait until (not s_st_rec1'Quiet) and
(s_st_rec1_savt /= Std.Standard.Now) ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions completed entirely",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <=
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns
when 3,
--
c_st_rec1_1 after 100 ns
when 4,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec1_1 after 40 ns when 6 ;
--
CHG13 :
process
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P13" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 4 ;
-- s_st_rec2 <=
-- c_st_rec2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 5 ;
-- s_st_rec2 <=
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2 <=
-- c_st_rec2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
wait until (not s_st_rec2'Quiet) and
(s_st_rec2_savt /= Std.Standard.Now) ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions completed entirely",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <=
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns
when 3,
--
c_st_rec2_1 after 100 ns
when 4,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec2_1 after 40 ns when 6 ;
--
CHG14 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P14" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3 <=
-- c_st_rec3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3 <=
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3 <=
-- c_st_rec3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <=
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns
when 3,
--
c_st_rec3_1 after 100 ns
when 4,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_rec3_1 after 40 ns when 6 ;
--
CHG15 :
process
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P15" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 4 ;
-- s_st_arr1 <=
-- c_st_arr1_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 5 ;
-- s_st_arr1 <=
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1 <=
-- c_st_arr1_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
wait until (not s_st_arr1'Quiet) and
(s_st_arr1_savt /= Std.Standard.Now) ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions completed entirely",
chk_st_arr1 = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <=
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns
when 3,
--
c_st_arr1_1 after 100 ns
when 4,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr1_1 after 40 ns when 6 ;
--
CHG16 :
process
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P16" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 4 ;
-- s_st_arr2 <=
-- c_st_arr2_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 5 ;
-- s_st_arr2 <=
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2 <=
-- c_st_arr2_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
wait until (not s_st_arr2'Quiet) and
(s_st_arr2_savt /= Std.Standard.Now) ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions completed entirely",
chk_st_arr2 = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <=
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns
when 3,
--
c_st_arr2_1 after 100 ns
when 4,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_1 after 40 ns when 6 ;
--
CHG17 :
process
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381.P17" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 4 ;
-- s_st_arr3 <=
-- c_st_arr3_1 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 5 ;
-- s_st_arr3 <=
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3 <=
-- c_st_arr3_1 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00381" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
wait until (not s_st_arr3'Quiet) and
(s_st_arr3_savt /= Std.Standard.Now) ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions completed entirely",
chk_st_arr3 = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <=
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns
when 3,
--
c_st_arr3_1 after 100 ns
when 4,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_1 after 40 ns when 6 ;
--
end ARCH00381 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00381_Test_Bench is
end ENT00381_Test_Bench ;
--
--
architecture ARCH00381_Test_Bench of ENT00381_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00381 ( ARCH00381 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00381_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00443.vhd
|
1
|
5114
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00443
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (2)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00443(ARCH00443)
-- ENT00443_Test_Bench(ARCH00443_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.ARITHMETIC.ALL ;
entity ENT00443 is
generic (
i_real_1 : real := c_real_1 ;
i_real_2 : real := c_real_2 ;
i_t_real_1 : t_real := c_t_real_1 ;
i_t_real_2 : t_real := c_t_real_2 ;
i_st_real_1 : st_real := c_st_real_1 ;
i_st_real_2 : st_real := c_st_real_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00443 ;
architecture ARCH00443 of ENT00443 is
constant c2_real_1 : real :=
(-10.4) / i_real_1 + i_real_1 / i_real_2 + i_real_1 / i_real_1 -
i_real_2 / c_real_2 ;
constant c2_t_real_1 : t_real :=
(1.0) / i_t_real_1 + (i_t_real_1) / i_t_real_2 +
(-i_t_real_1) / 2.0 -
c_t_real_2 / i_t_real_2 ;
constant c2_st_real_1 : st_real :=
(-0.0) / i_st_real_2 + i_t_real_1 / (i_st_real_1) +
(i_st_real_1 / i_t_real_2) - (c_st_real_2) / i_t_real_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_real_1, v2_real_1 : real := i_real_1 ;
variable v_real_2, v2_real_2 : real := i_real_2 ;
variable v_t_real_1, v2_t_real_1 : t_real := i_t_real_1 ;
variable v_t_real_2, v2_t_real_2 : t_real := i_t_real_2 ;
variable v_st_real_1, v2_st_real_1 : st_real := i_st_real_1 ;
variable v_st_real_2, v2_st_real_2 : st_real := i_st_real_2 ;
--
begin
-- static expression
case bool is
when (
abs(
(-10.4) / c_real_1 + c_real_1 / c_real_2 + c_real_1 / c_real_1 -
c_real_2 / c_real_2
- (-2.4288)) < acceptable_error and
abs(
(1.0) / c_t_real_1 + (c_t_real_1) / c_t_real_2 +
(-c_t_real_1) / 2.0 -
c_t_real_2 / c_t_real_2
- (-393.8552)) < t_acceptable_error and
abs(
(-0.0) / c_st_real_2 + c_t_real_1 / (c_st_real_1) +
(c_st_real_1 / c_t_real_2) - (c_st_real_2) / c_t_real_2
- (-31.2542)) < t_acceptable_error
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := abs (c2_real_1 - (-2.4288)) < acceptable_error and
abs (c2_t_real_1 - (-393.8552)) < t_acceptable_error and
abs (c2_st_real_1 - (-31.2542)) < t_acceptable_error ;
-- dynamic expression
v2_real_1 :=
(-10.4) / v_real_1 + v_real_1 / v_real_2 + v_real_1 / v_real_1 -
v_real_2 / c_real_2 ;
v2_t_real_1 :=
(1.0) / v_t_real_1 + (v_t_real_1) / v_t_real_2 +
(-v_t_real_1) / 2.0 -
v_t_real_2 / i_t_real_2 ;
v2_st_real_1 :=
(-0.0) / v_st_real_2 + v_t_real_1 / (v_st_real_1) +
(v_st_real_1 / v_t_real_2) - (v_st_real_2) / i_t_real_2 ;
dyn_correct := abs (v2_real_1 - (-2.4288)) < acceptable_error and
abs (v2_t_real_1 - (-393.8552)) < t_acceptable_error and
abs (v2_st_real_1 - (-31.2542)) < t_acceptable_error ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00443 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00443_Test_Bench is
end ENT00443_Test_Bench ;
architecture ARCH00443_Test_Bench of ENT00443_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00443 ( ARCH00443 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00443" ,
"/ predefined for floating types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00443_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00093.vhd
|
1
|
11427
|
-- NEED RESULT: ARCH00093.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093.P2: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093.P3: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00093: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00093
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00093(ARCH00093)
-- ENT00093_Test_Bench(ARCH00093_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00093 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00093 ;
--
architecture ARCH00093 of ENT00093 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00093.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= transport c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00093" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00093.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= transport c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00093" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00093.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= transport c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00093" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00093" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
--
end ARCH00093 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00093_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00093_Test_Bench ;
--
architecture ARCH00093_Test_Bench of ENT00093_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00093 ( ARCH00093 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00093_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00017.vhd
|
1
|
2196
|
-- NEED RESULT: ENT00017: An actual of any mode may be associated with a formal of mode linkage passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00017
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00017(ARCH00017)
-- ENT00017_1(ARCH00017_1)
-- ENT00017_Test_Bench(ARCH00017_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00017 is
port ( SIN, SINOUT, SOUT, SBUFFER, SLINK : linkage boolean ) ;
end ENT00017 ;
architecture ARCH00017 of ENT00017 is
begin
process
begin
test_report ( "ENT00017" ,
"An actual of any mode may be associated with a formal" &
" of mode linkage" ,
true ) ;
wait ;
end process ;
end ARCH00017 ;
entity ENT00017_1 is
port ( SIN : in boolean ;
SINOUT : inout boolean ;
SOUT : out boolean ;
SBUFFER : buffer boolean ;
SLINK : linkage boolean ) ;
end ENT00017_1 ;
architecture ARCH00017_1 of ENT00017_1 is
begin
L1:
block
component UUT
end component ;
signal SIN, SINOUT, SOUT, SBUFFER, SLINK : boolean ;
for CIS1 : UUT use entity WORK.ENT00017 ( ARCH00017 )
port map ( SIN, SINOUT, SOUT, SBUFFER, SLINK ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00017_1 ;
entity ENT00017_Test_Bench is
end ENT00017_Test_Bench ;
architecture ARCH00017_Test_Bench of ENT00017_Test_Bench is
begin
L1:
block
component UUT
end component ;
signal SIN, SINOUT, SOUT, SBUFFER, SLINK : boolean ;
for CIS1 : UUT use entity WORK.ENT00017_1 ( ARCH00017_1 )
port map ( SIN, SINOUT, SOUT, SBUFFER, SLINK ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00017_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00376.vhd
|
1
|
5197
|
-- NEED RESULT: ARCH00376.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00376: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00376: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00376
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00376(ARCH00376)
-- ENT00376_Test_Bench(ARCH00376_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00376 is
end ENT00376 ;
--
--
architecture ARCH00376 of ENT00376 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00376.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2.f2 <= transport
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00376" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00376" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00376" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f2.f2 <= transport
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2.f2 after 5 ns ;
--
end ARCH00376 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00376_Test_Bench is
end ENT00376_Test_Bench ;
--
--
architecture ARCH00376_Test_Bench of ENT00376_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00376 ( ARCH00376 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00376_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00240.vhd
|
1
|
5405
|
-- NEED RESULT: ENT00240: Associated composite linkage ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00240
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00240(ARCH00240)
-- ENT00240_Test_Bench(ARCH00240_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00240 is
port (
i_bit_vector_1, i_bit_vector_2 : linkage bit_vector
;
i_string_1, i_string_2 : linkage string
;
i_t_rec1_1, i_t_rec1_2 : linkage t_rec1
;
i_st_rec1_1, i_st_rec1_2 : linkage st_rec1
;
i_t_rec2_1, i_t_rec2_2 : linkage t_rec2
;
i_st_rec2_1, i_st_rec2_2 : linkage st_rec2
;
i_t_rec3_1, i_t_rec3_2 : linkage t_rec3
;
i_st_rec3_1, i_st_rec3_2 : linkage st_rec3
;
i_t_arr1_1, i_t_arr1_2 : linkage t_arr1
;
i_st_arr1_1, i_st_arr1_2 : linkage st_arr1
;
i_t_arr2_1, i_t_arr2_2 : linkage t_arr2
;
i_st_arr2_1, i_st_arr2_2 : linkage st_arr2
;
i_t_arr3_1, i_t_arr3_2 : linkage t_arr3
;
i_st_arr3_1, i_st_arr3_2 : linkage st_arr3
) ;
begin
end ENT00240 ;
--
architecture ARCH00240 of ENT00240 is
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00240" ,
"Associated composite linkage ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00240 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00240_Test_Bench is
end ENT00240_Test_Bench ;
--
architecture ARCH00240_Test_Bench of ENT00240_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
i_bit_vector_1, i_bit_vector_2 : linkage bit_vector
;
i_string_1, i_string_2 : linkage string
;
i_t_rec1_1, i_t_rec1_2 : linkage t_rec1
;
i_st_rec1_1, i_st_rec1_2 : linkage st_rec1
;
i_t_rec2_1, i_t_rec2_2 : linkage t_rec2
;
i_st_rec2_1, i_st_rec2_2 : linkage st_rec2
;
i_t_rec3_1, i_t_rec3_2 : linkage t_rec3
;
i_st_rec3_1, i_st_rec3_2 : linkage st_rec3
;
i_t_arr1_1, i_t_arr1_2 : linkage t_arr1
;
i_st_arr1_1, i_st_arr1_2 : linkage st_arr1
;
i_t_arr2_1, i_t_arr2_2 : linkage t_arr2
;
i_st_arr2_1, i_st_arr2_2 : linkage st_arr2
;
i_t_arr3_1, i_t_arr3_2 : linkage t_arr3
;
i_st_arr3_1, i_st_arr3_2 : linkage st_arr3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00240 ( ARCH00240 ) ;
--
begin
CIS1 : UUT
port map (
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
end block L1 ;
end ARCH00240_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00176.vhd
|
1
|
8508
|
-- NEED RESULT: ARCH00176.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00176: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00176
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00176(ARCH00176)
-- ENT00176_Test_Bench(ARCH00176_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00176 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00176 ;
--
architecture ARCH00176 of ENT00176 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00176.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00176" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00176" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00176" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00176" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00176" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00176 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00176_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00176_Test_Bench ;
--
architecture ARCH00176_Test_Bench of ENT00176_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00176 ( ARCH00176 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
) ;
end block L1 ;
end ARCH00176_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00322.vhd
|
1
|
1471
|
-- NEED RESULT: *** An assertion follows with severity level NOTE
-- NEED RESULT: An assertion with severity NOTE
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00322
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00322)
-- ENT00322_Test_Bench(ARCH00322_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match the comment messages output.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00322 of E00000 is
signal Dummy : Boolean := false;
begin
P1 :
process ( Dummy )
begin
print ("*** An assertion follows with severity level NOTE") ;
end process ;
assert Dummy
report "An assertion with severity NOTE"
severity Severity_Level'Left ;
end ARCH00322 ;
entity ENT00322_Test_Bench is
end ENT00322_Test_Bench ;
architecture ARCH00322_Test_Bench of ENT00322_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00322 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00322_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/proc3.vhd
|
1
|
634
|
-- Subtypes
entity test is
end entity test;
architecture test_arch of test is
type vector is array (integer range <>) of integer;
subtype svec1 is vector (1 to 3);
subtype svec2 is vector (4 to 7);
procedure p1(variable v1 : inout svec2) is
begin
v1(4) := 4;
end procedure;
begin
main: process
variable v : svec1 := (0=>0, 1=>1, 2=>2, 3=>3);
begin
p1(v);
report integer'image(v(0));
report integer'image(v(1));
report integer'image(v(2));
report integer'image(v(3));
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/IEEE/old/textio.vhd
|
1
|
18368
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value(value'range) := (others => 'U');
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
end STD_LOGIC_TEXTIO;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_bindec.vhd
|
9
|
10044
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Yb3D6waro/MZBsuFpvtFj6sZqrK43pekOKIGmdVLBSWL9eHgkVVs43xQ4WZ5VAQHXyaaR2UHX42l
dvtW1NtoXw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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N+W+y80oBQgwNEdA5HY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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nvEZi1LwQCGlvoDPmnaV/BuLqKXFozmkeUIKhw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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QlyY8o0ZR7RWU92LST8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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/yCsQGDaTZhTdGqhoqjU1yzBjdbqQ9tmH/C3Tg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5696)
`protect data_block
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Z9x9Xn8=
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00218.vhd
|
1
|
5433
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00218
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00218(ARCH00218)
-- ENT00218_Test_Bench(ARCH00218_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00218 is
generic (G : integer) ;
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00218 ;
--
--
architecture ARCH00218 of ENT00218 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(2)(1 to 2) <= transport
c_st_arr1_vector_2(2)(1 to 2) after 10 ns ;
wait until s_st_arr1_vector(2)(1 to 2) =
c_st_arr1_vector_2(2)(1 to 2) ;
Test_Report (
"ENT00218",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(2)(1 to 2) =
c_st_arr1_vector_2(2)(1 to 2) )) ;
--
when 1
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(G)(G-1 to G) <= transport
c_st_arr1_vector_2(G)(G-1 to G) after 10 ns ;
wait until s_st_arr1_vector(G)(G-1 to G) =
c_st_arr1_vector_2(G)(G-1 to G) ;
Test_Report (
"ENT00218",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(G)(G-1 to G) =
c_st_arr1_vector_2(G)(G-1 to G) )) ;
--
when 2
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(CG)(CG-1 to CG) <= transport
c_st_arr1_vector_2(CG)(CG-1 to CG) after 10 ns ;
wait until s_st_arr1_vector(CG)(CG-1 to CG) =
c_st_arr1_vector_2(CG)(CG-1 to CG) ;
Test_Report (
"ENT00218",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG)(CG-1 to CG) =
c_st_arr1_vector_2(CG)(CG-1 to CG) )) ;
--
when 3
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) <= transport
c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) after 10 ns ;
wait until s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) ;
Test_Report (
"ENT00218",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG'Attr)(CG'Attr-1 to CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr-1 to CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_arr1_vector
, counter
, correct
, savtime
, chk_st_arr1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_arr1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00218 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00218_Test_Bench is
end ENT00218_Test_Bench ;
--
--
architecture ARCH00218_Test_Bench of ENT00218_Test_Bench is
begin
L1:
block
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00218 ( ARCH00218 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00218_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00355.vhd
|
1
|
10319
|
-- NEED RESULT: ARCH00355.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00355.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00355: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00355: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00355: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00355: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00355
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00355(ARCH00355)
-- ENT00355_Test_Bench(ARCH00355_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00355 is
end ENT00355 ;
--
--
architecture ARCH00355 of ENT00355 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
CHG1 :
process ( s_st_arr2_vector )
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00355.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00355" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00355" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00355" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <= transport
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ;
--
CHG2 :
process ( s_st_arr3_vector )
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00355.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_vector_select <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr3_vector_select <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00355" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00355" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00355" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr3_vector_savt <= transport Std.Standard.Now ;
chk_st_arr3_vector <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_vector_cnt <= transport s_st_arr3_vector_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <= transport
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ;
--
end ARCH00355 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00355_Test_Bench is
end ENT00355_Test_Bench ;
--
--
architecture ARCH00355_Test_Bench of ENT00355_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00355 ( ARCH00355 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00355_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00690.vhd
|
1
|
5819
|
-- NEED RESULT: ARCH00690: Allocators with generic scalar qualified expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00690
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (3)
-- 7.3.6 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00690)
-- ENT00690_Test_Bench(ARCH00690_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00690 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
type a_boolean is access boolean ;
variable va_boolean_1, va_boolean_2 : a_boolean
:= new boolean ;
type a_bit is access bit ;
variable va_bit_1, va_bit_2 : a_bit
:= new bit ;
type a_severity_level is access severity_level ;
variable va_severity_level_1, va_severity_level_2 : a_severity_level
:= new severity_level ;
type a_character is access character ;
variable va_character_1, va_character_2 : a_character
:= new character ;
type a_t_enum1 is access t_enum1 ;
variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1
:= new t_enum1 ;
type a_st_enum1 is access st_enum1 ;
variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1
:= new st_enum1 ;
type a_integer is access integer ;
variable va_integer_1, va_integer_2 : a_integer
:= new integer ;
type a_t_int1 is access t_int1 ;
variable va_t_int1_1, va_t_int1_2 : a_t_int1
:= new t_int1 ;
type a_st_int1 is access st_int1 ;
variable va_st_int1_1, va_st_int1_2 : a_st_int1
:= new st_int1 ;
type a_time is access time ;
variable va_time_1, va_time_2 : a_time
:= new time ;
type a_t_phys1 is access t_phys1 ;
variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1
:= new t_phys1 ;
type a_st_phys1 is access st_phys1 ;
variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1
:= new st_phys1 ;
type a_real is access real ;
variable va_real_1, va_real_2 : a_real
:= new real ;
type a_t_real1 is access t_real1 ;
variable va_t_real1_1, va_t_real1_2 : a_t_real1
:= new t_real1 ;
type a_st_real1 is access st_real1 ;
variable va_st_real1_1, va_st_real1_2 : a_st_real1
:= new st_real1 ;
begin
va_boolean_1 := new boolean ' (c_boolean_1) ;
va_bit_1 := new bit ' (c_bit_1) ;
va_severity_level_1 := new severity_level ' (c_severity_level_1) ;
va_character_1 := new character ' (c_character_1) ;
va_t_enum1_1 := new t_enum1 ' (c_t_enum1_1) ;
va_st_enum1_1 := new st_enum1 ' (c_st_enum1_1) ;
va_integer_1 := new integer ' (c_integer_1) ;
va_t_int1_1 := new t_int1 ' (c_t_int1_1) ;
va_st_int1_1 := new st_int1 ' (c_st_int1_1) ;
va_time_1 := new time ' (c_time_1) ;
va_t_phys1_1 := new t_phys1 ' (c_t_phys1_1) ;
va_st_phys1_1 := new st_phys1 ' (c_st_phys1_1) ;
va_real_1 := new real ' (c_real_1) ;
va_t_real1_1 := new t_real1 ' (c_t_real1_1) ;
va_st_real1_1 := new st_real1 ' (c_st_real1_1) ;
correct := correct and
va_boolean_1.all = c_boolean_1 ;
correct := correct and
va_bit_1.all = c_bit_1 ;
correct := correct and
va_severity_level_1.all = c_severity_level_1 ;
correct := correct and
va_character_1.all = c_character_1 ;
correct := correct and
va_t_enum1_1.all = c_t_enum1_1 ;
correct := correct and
va_st_enum1_1.all = c_st_enum1_1 ;
correct := correct and
va_integer_1.all = c_integer_1 ;
correct := correct and
va_t_int1_1.all = c_t_int1_1 ;
correct := correct and
va_st_int1_1.all = c_st_int1_1 ;
correct := correct and
va_time_1.all = c_time_1 ;
correct := correct and
va_t_phys1_1.all = c_t_phys1_1 ;
correct := correct and
va_st_phys1_1.all = c_st_phys1_1 ;
correct := correct and
va_real_1.all = c_real_1 ;
correct := correct and
va_t_real1_1.all = c_t_real1_1 ;
correct := correct and
va_st_real1_1.all = c_st_real1_1 ;
test_report ( "ARCH00690" ,
"Allocators with generic scalar qualified expression" ,
correct) ;
wait ;
end process ;
end ARCH00690 ;
--
entity ENT00690_Test_Bench is
end ENT00690_Test_Bench ;
--
architecture ARCH00690_Test_Bench of ENT00690_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00690 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00690_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00476.vhd
|
1
|
3459
|
-- NEED RESULT: ARCH00476: Functions can return user defined types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00476
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (8)
-- 2.1 (10)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00476)
-- ENT00476_Test_Bench(ARCH00476_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
-- The various types are taken from GENERIC_STANDARD_TYPES without the
-- explicit qualifier, as is the resolution function bf_rec3.
--
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00476 of GENERIC_STANDARD_TYPES is
function t_enum1_func ( i : integer ) return t_enum1 is
begin
return t_enum1'val(i) ;
end t_enum1_func ;
function st_enum1_func ( i : integer ) return st_enum1 is
begin
return st_enum1'val(i) ;
end st_enum1_func ;
function t_int1_func ( i : t_int1 ) return t_int1 is
begin
return i + 1 ;
end t_int1_func ;
function st_int1_func ( i : st_int1 ) return st_int1 is
begin
return i + 1 ;
end st_int1_func ;
function t_phys1_func ( i : integer ) return t_phys1 is
begin
return i * phys1_2;
end t_phys1_func ;
function st_phys1_func ( i : integer ) return st_phys1 is
begin
return i * phys1_2;
end st_phys1_func ;
function t_real1_func ( r : t_real1 ) return t_real1 is
begin
return r + 1.0;
end t_real1_func ;
function st_real1_func ( r : st_real1 ) return st_real1 is
begin
return r + 1.0;
end st_real1_func ;
function t_rec1_func ( r : real ) return t_rec1 is
variable rec : t_rec1 ;
begin
rec.f1 := lowb_i2 ;
rec.f2 := 0 ns ;
rec.f3 := true ;
rec.f4 := r + 1.0 ;
return rec ;
end t_rec1_func ;
function st_arr1_func ( i : integer ) return st_arr1 is
variable arr : st_arr1 ;
begin
for j in lowb to highb loop
arr(j) := t_int1(i + j);
end loop ;
return arr ;
end st_arr1_func ;
begin
P :
process
variable vec : rec3_vector (1 to 3) ;
begin
test_report ( "ARCH00476" ,
"Functions can return user defined types" ,
(t_enum1_func(1) = en2) and
(st_enum1_func(1) = en2) and
(t_int1_func(10) = 11 ) and
(st_int1_func(10) = 11 ) and
(t_phys1_func(2) = 2 phys1_2 ) and
(st_phys1_func(2) = 2 phys1_2 ) and
(t_real1_func(10.0) = 11.0 ) and
(st_real1_func(10.0) = 11.0 ) and
(t_rec1_func(10.0).f4 = 11.0 )
) ;
wait ;
end process P ;
end ARCH00476 ;
entity ENT00476_Test_Bench is
end ENT00476_Test_Bench ;
architecture ARCH00476_Test_Bench of ENT00476_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00476 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00476_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00456.vhd
|
1
|
4419
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00456
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (8)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00456(ARCH00456)
-- ENT00456_Test_Bench(ARCH00456_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES ;
use WORK.ARITHMETIC.ALL ;
entity ENT00456 is
generic (
i_real_1 : real := c_real_1 ;
i_real_2 : real := c_real_2 ;
i_realt_1 : realt := c_realt_1 ;
i_realt_2 : realt := c_realt_2 ;
i_realst_1 : realst := c_realst_1 ;
i_realst_2 : realst := c_realst_2 ;
i_time_1 : time := c_time_1 ;
i_time_2 : time := c_time_2 ;
i_t_phys_1 : t_phys := c_t_phys_1 ;
i_t_phys_2 : t_phys := c_t_phys_2 ;
i_st_phys_1 : st_phys := c_st_phys_1 ;
i_st_phys_2 : st_phys := c_st_phys_2
) ;
constant c2_time_1 : time :=
i_time_1 / i_realst_1 + i_time_2 / i_real_1 + 0 ns / i_real_2 ;
constant c2_t_phys_1 : t_phys :=
i_t_phys_1 / i_realst_1 + c_t_phys_2 / i_real_1 +
i_t_phys_1 / i_realt_2 + i_t_phys_2 / c_real_2 ;
constant c2_st_phys_1 : st_phys :=
i_st_phys_1 / i_realst_1 + c_t_phys_2 / i_real_1 +
i_t_phys_1 / i_realt_2 + i_st_phys_2 / c_real_2 ;
end ENT00456 ;
architecture ARCH00456 of ENT00456 is
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_time_1, v2_time_1 : time := i_time_1 ;
variable v_time_2, v2_time_2 : time := i_time_2 ;
variable v_t_phys_1, v2_t_phys_1 : t_phys := i_t_phys_1 ;
variable v_t_phys_2, v2_t_phys_2 : t_phys := i_t_phys_2 ;
variable v_st_phys_1, v2_st_phys_1 : st_phys := i_st_phys_1 ;
variable v_st_phys_2, v2_st_phys_2 : st_phys := i_st_phys_2 ;
variable v_real_1 : real := i_real_1 ;
variable v_real_2 : real := i_real_2 ;
variable v_realt_1 : realt := i_realt_1 ;
variable v_realt_2 : realt := i_realt_2 ;
variable v_realst_1 : realst := i_realst_1 ;
variable v_realst_2 : realst := i_realst_2 ;
-- the following are temporary
constant p1_acceptable_error : time := 5 ns ;
constant p2_acceptable_error : t_phys := t_phys'left ;
--
begin
-- static expression
case bool is
when (
c_time_1 / c_realst_1 + c_time_2 / c_real_1 + 0 ns / c_real_2
= 169493 fs and
c_t_phys_1 / c_realst_1 + c_t_phys_2 / c_real_1 +
c_t_phys_1 / c_realt_2 + c_t_phys_2 / c_real_2
= - 58 ones and
c_st_phys_1 / c_realst_1 + c_t_phys_2 / c_real_1 +
c_t_phys_1 / c_realt_2 + c_st_phys_2 / c_real_2
= -137 ones
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_time_1 = 169493 fs and
c2_t_phys_1 = - 58 ones and
c2_st_phys_1 = - 137 ones ;
-- dynamic expression
v2_time_1 :=
i_time_1 / v_realst_1 + v_time_2 / v_real_1 + 0 ns / v_real_2 ;
v2_t_phys_1 :=
v_t_phys_1 / i_realst_1 + c_t_phys_2 / v_real_1 +
i_t_phys_1 / v_realt_2 + v_t_phys_2 / c_real_2 ;
v2_st_phys_1 :=
v_st_phys_1 / v_realst_1 + c_t_phys_2 / v_real_1 +
v_t_phys_1 / v_realt_2 + i_st_phys_2 / c_real_2 ;
dyn_correct := v2_time_1 = 169493 fs and
v2_t_phys_1 = - 58 ones and
v2_st_phys_1 = - 137 ones;
STANDARD_TYPES.test_report ( "ARCH00456" ,
"* predefined for physical and real types" ,
dyn_correct and cons_correct and gen_correct ) ;
wait ;
end process ;
end ARCH00456 ;
entity ENT00456_Test_Bench is
end ENT00456_Test_Bench ;
architecture ARCH00456_Test_Bench of ENT00456_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00456 ( ARCH00456 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00456_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00085.vhd
|
1
|
70077
|
-- NEED RESULT: ARCH00085.P1: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P2: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P3: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P4: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P5: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P6: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P7: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P8: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P9: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P10: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P11: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P12: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P13: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P14: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P15: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P16: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085.P17: Multi transport transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: One transport transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00085: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00085
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00085(ARCH00085)
-- ENT00085_Test_Bench(ARCH00085_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00085 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_boolean_vector : inout st_boolean_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_boolean_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_bit_vector : inout st_bit_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_bit_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_severity_level_vector : inout st_severity_level_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_severity_level_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_st_string : inout st_string ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_string : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1_vector : inout st_enum1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_st_integer_vector : inout st_integer_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_integer_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1_vector : inout st_int1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_st_time_vector : inout st_time_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_time_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1_vector : inout st_phys1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_st_real_vector : inout st_real_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1_vector : inout st_real1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00085.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00085" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00085" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00085 ;
--
architecture ARCH00085 of ENT00085 is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_boolean_vector,
counter,
correct,
savtime,
chk_st_boolean_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_bit_vector,
counter,
correct,
savtime,
chk_st_bit_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_severity_level_vector,
counter,
correct,
savtime,
chk_st_severity_level_vector
) ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_st_string,
counter,
correct,
savtime,
chk_st_string
) ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1_vector,
counter,
correct,
savtime,
chk_st_enum1_vector
) ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_st_integer_vector,
counter,
correct,
savtime,
chk_st_integer_vector
) ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1_vector,
counter,
correct,
savtime,
chk_st_int1_vector
) ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_st_time_vector,
counter,
correct,
savtime,
chk_st_time_vector
) ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1_vector,
counter,
correct,
savtime,
chk_st_phys1_vector
) ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_st_real_vector,
counter,
correct,
savtime,
chk_st_real_vector
) ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1_vector,
counter,
correct,
savtime,
chk_st_real1_vector
) ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
end process P17 ;
--
--
end ARCH00085 ;
--
entity ENT00085_Test_Bench is
end ENT00085_Test_Bench ;
--
architecture ARCH00085_Test_Bench of ENT00085_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00085 ( ARCH00085 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00085_Test_Bench ;
|
gpl-3.0
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