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pemsac/ANN_project
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ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/vhdl/ANN.vhd
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6
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164925
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-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ANN is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of ANN is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"ANN,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=37,HLS_SYN_FF=8935,HLS_SYN_LUT=12780}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (149 downto 0) := "000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (149 downto 0) := "000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (149 downto 0) := "000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (149 downto 0) := "000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (149 downto 0) := "000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (149 downto 0) := "000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st144_fsm_143 : STD_LOGIC_VECTOR (149 downto 0) := "000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st145_fsm_144 : STD_LOGIC_VECTOR (149 downto 0) := "000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st146_fsm_145 : STD_LOGIC_VECTOR (149 downto 0) := "000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st147_fsm_146 : STD_LOGIC_VECTOR (149 downto 0) := "000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st148_fsm_147 : STD_LOGIC_VECTOR (149 downto 0) := "001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st149_fsm_148 : STD_LOGIC_VECTOR (149 downto 0) := "010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st150_fsm_149 : STD_LOGIC_VECTOR (149 downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_58 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011000";
constant ap_const_lv32_81 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000001";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_66 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100110";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_67 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100111";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_54 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010100";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_53 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010011";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_57 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010111";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_91 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010001";
constant ap_const_lv32_93 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010011";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_92 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010010";
constant ap_const_lv32_94 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010100";
constant ap_const_lv32_BF800000 : STD_LOGIC_VECTOR (31 downto 0) := "10111111100000000000000000000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv32_62 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100010";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv14_29 : STD_LOGIC_VECTOR (13 downto 0) := "00000000101001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv32_95 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010010101";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (149 downto 0) := "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_168 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal P_index1 : STD_LOGIC_VECTOR (31 downto 0);
signal P_index2 : STD_LOGIC_VECTOR (31 downto 0);
signal P_intIn_index3 : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatIn : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce0 : STD_LOGIC;
signal ST_uOut_we0 : STD_LOGIC;
signal ST_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce1 : STD_LOGIC;
signal ST_uOut_we1 : STD_LOGIC;
signal ST_uOut_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal ANN_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal reg_490 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_253 : BOOLEAN;
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_260 : BOOLEAN;
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_268 : BOOLEAN;
signal ap_sig_cseq_ST_st89_fsm_88 : STD_LOGIC;
signal ap_sig_bdd_275 : BOOLEAN;
signal ap_sig_cseq_ST_st130_fsm_129 : STD_LOGIC;
signal ap_sig_bdd_283 : BOOLEAN;
signal reg_499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_292 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_301 : BOOLEAN;
signal grp_fu_428_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_505 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_311 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_318 : BOOLEAN;
signal grp_fu_421_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_328 : BOOLEAN;
signal ap_sig_cseq_ST_st97_fsm_96 : STD_LOGIC;
signal ap_sig_bdd_335 : BOOLEAN;
signal reg_516 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st29_fsm_28 : STD_LOGIC;
signal ap_sig_bdd_344 : BOOLEAN;
signal ap_sig_cseq_ST_st103_fsm_102 : STD_LOGIC;
signal ap_sig_bdd_351 : BOOLEAN;
signal grp_fu_447_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_521 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st30_fsm_29 : STD_LOGIC;
signal ap_sig_bdd_361 : BOOLEAN;
signal ap_sig_cseq_ST_st104_fsm_103 : STD_LOGIC;
signal ap_sig_bdd_368 : BOOLEAN;
signal grp_fu_464_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_526 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st48_fsm_47 : STD_LOGIC;
signal ap_sig_bdd_378 : BOOLEAN;
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_385 : BOOLEAN;
signal grp_fu_444_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_532 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st85_fsm_84 : STD_LOGIC;
signal ap_sig_bdd_395 : BOOLEAN;
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_402 : BOOLEAN;
signal P_floatIn_read_reg_1345 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_numLayer_load_reg_1353 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_609_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_76_reg_1378 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_1_fu_538_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_549_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_555_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_561_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_fu_619_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_1384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_683_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_reg_1394 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_fu_721_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_reg_1399 : STD_LOGIC_VECTOR (13 downto 0);
signal max_2_cast_fu_761_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal max_2_cast_reg_1407 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_458 : BOOLEAN;
signal tmp_24_fu_765_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_798_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_4_reg_1425 : STD_LOGIC_VECTOR (30 downto 0);
signal ST_uOut_load_2_reg_1430 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_881_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_63_reg_1436 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_478 : BOOLEAN;
signal max_1_fu_887_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_487 : BOOLEAN;
signal grp_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_496 : BOOLEAN;
signal tmp_28_fu_926_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_28_reg_1454 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_505 : BOOLEAN;
signal tmp_3_fu_897_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_932_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_reg_1459 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_38_fu_966_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_38_reg_1464 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_45_fu_972_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_45_reg_1469 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_56_fu_1000_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_56_reg_1474 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_58_fu_1006_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_58_reg_1479 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_fu_1010_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_64_reg_1484 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_69_fu_1043_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_reg_1489 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_1049_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_70_reg_1494 : STD_LOGIC_VECTOR (1 downto 0);
signal j_2_fu_1072_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_1502 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_535 : BOOLEAN;
signal tmp_53_fu_1078_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_1507 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_80_fu_1333_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_reg_1513 : STD_LOGIC_VECTOR (13 downto 0);
signal ST_uOut_addr_5_reg_1519 : STD_LOGIC_VECTOR (7 downto 0);
signal i_3_fu_1105_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_fu_1120_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_reg_1532 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_557 : BOOLEAN;
signal tmp_33_fu_1115_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_454_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_reg_1552 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st53_fsm_52 : STD_LOGIC;
signal ap_sig_bdd_577 : BOOLEAN;
signal grp_fu_459_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_43_reg_1557 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st84_fsm_83 : STD_LOGIC;
signal ap_sig_bdd_586 : BOOLEAN;
signal tmp_27_fu_1182_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_reg_1562 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_595 : BOOLEAN;
signal i_5_fu_1201_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_5_reg_1570 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_1207_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_reg_1575 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_1195_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_83_fu_1339_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_83_reg_1581 : STD_LOGIC_VECTOR (13 downto 0);
signal ST_uOut_addr_7_reg_1587 : STD_LOGIC_VECTOR (7 downto 0);
signal j_3_fu_1243_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_3_reg_1595 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st88_fsm_87 : STD_LOGIC;
signal ap_sig_bdd_616 : BOOLEAN;
signal tmp_34_fu_1238_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st128_fsm_127 : STD_LOGIC;
signal ap_sig_bdd_635 : BOOLEAN;
signal i_6_fu_1299_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_1623 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st129_fsm_128 : STD_LOGIC;
signal ap_sig_bdd_644 : BOOLEAN;
signal ST_uOut_addr_8_reg_1628 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_35_fu_1294_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_435_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_reg_1634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st146_fsm_145 : STD_LOGIC;
signal ap_sig_bdd_659 : BOOLEAN;
signal tmp_21_fu_1324_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_reg_1639 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st148_fsm_147 : STD_LOGIC;
signal ap_sig_bdd_668 : BOOLEAN;
signal max_2_reg_266 : STD_LOGIC_VECTOR (30 downto 0);
signal max_reg_277 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_289 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_301 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st86_fsm_85 : STD_LOGIC;
signal ap_sig_bdd_690 : BOOLEAN;
signal sum_reg_312 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_324 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_335 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_347 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_358 : STD_LOGIC_VECTOR (31 downto 0);
signal j_1_reg_370 : STD_LOGIC_VECTOR (30 downto 0);
signal i_2_reg_381 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st147_fsm_146 : STD_LOGIC;
signal ap_sig_bdd_712 : BOOLEAN;
signal p_0_reg_392 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st149_fsm_148 : STD_LOGIC;
signal ap_sig_bdd_728 : BOOLEAN;
signal tmp_66_cast_fu_673_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_678_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_779_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_793_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_cast_fu_1100_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_1139_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1149_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1162_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_84_cast_fu_1229_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1262_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_92_cast_fu_1272_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1285_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_94_cast_fu_1314_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_21_cast_fu_1329_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_727_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_818 : BOOLEAN;
signal grp_fu_421_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_421_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_837 : BOOLEAN;
signal ap_sig_cseq_ST_st25_fsm_24 : STD_LOGIC;
signal ap_sig_bdd_844 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_852 : BOOLEAN;
signal ap_sig_cseq_ST_st99_fsm_98 : STD_LOGIC;
signal ap_sig_bdd_859 : BOOLEAN;
signal grp_fu_428_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_444_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_447_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_1177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_469_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_74_fu_585_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_75_fu_597_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl12_cast_fu_589_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl13_cast_fu_601_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_619_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_72_fu_637_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_73_fu_649_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl10_cast_fu_641_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl11_cast_fu_653_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_71_fu_633_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_661_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_66_fu_667_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_691_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_703_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl_cast_fu_695_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_707_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_fu_687_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_715_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_94_fu_770_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_86_fu_774_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_95_fu_784_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_788_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ST_uOut_load_1_to_int_fu_804_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_load_2_to_int_fu_822_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_55_fu_808_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_818_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_839_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_57_fu_825_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_97_fu_835_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_863_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_869_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_875_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_fu_450_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_cast_fu_893_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_902_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_fu_914_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl8_cast_fu_906_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl9_cast_fu_918_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_15_fu_936_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_30_fu_942_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_36_fu_954_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl6_cast_fu_946_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl7_cast_fu_958_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_47_fu_976_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_51_fu_988_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl4_cast_fu_980_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_992_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_fu_1014_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_67_fu_1019_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_68_fu_1031_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1023_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl3_cast_fu_1035_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_1053_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_1091_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_79_fu_1095_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_79_fu_1095_p2 : signal is "no";
signal k_cast_fu_1111_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_fu_1130_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_88_fu_1134_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_88_fu_1134_p2 : signal is "no";
signal tmp_98_fu_1126_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_89_fu_1144_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_100_fu_1154_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_90_fu_1157_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_90_fu_1157_p2 : signal is "no";
signal tmp_39_to_int_fu_1167_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_neg_fu_1171_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_1220_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_fu_1224_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_82_fu_1224_p2 : signal is "no";
signal j_1_cast_fu_1234_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_102_fu_1253_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_91_fu_1257_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_91_fu_1257_p2 : signal is "no";
signal tmp_101_fu_1249_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_92_fu_1267_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_103_fu_1277_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_93_fu_1280_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_93_fu_1280_p2 : signal is "no";
signal i_2_cast_fu_1290_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_84_fu_1305_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_fu_1309_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1319_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_80_fu_1333_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_83_fu_1339_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_421_ce : STD_LOGIC;
signal grp_fu_428_ce : STD_LOGIC;
signal grp_fu_435_ce : STD_LOGIC;
signal grp_fu_440_ce : STD_LOGIC;
signal tmp_62_fu_450_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_454_ce : STD_LOGIC;
signal grp_fu_459_ce : STD_LOGIC;
signal grp_fu_464_ce : STD_LOGIC;
signal ap_sig_cseq_ST_st150_fsm_149 : STD_LOGIC;
signal ap_sig_bdd_1429 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (149 downto 0);
component ANN_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_sitofp_32ns_32_6 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component ANN_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_mul_mul_7ns_14s_14_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component ANN_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_ST_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (31 downto 0);
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_return : IN STD_LOGIC_VECTOR (31 downto 0);
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index1 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index2 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_intIn_index3 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_floatIn : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ST_WandB_U : component ANN_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 6560,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
ST_uOut_U : component ANN_ST_uOut
generic map (
DataWidth => 32,
AddressRange => 160,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_uOut_address0,
ce0 => ST_uOut_ce0,
we0 => ST_uOut_we0,
d0 => ST_uOut_d0,
q0 => ST_uOut_q0,
address1 => ST_uOut_address1,
ce1 => ST_uOut_ce1,
we1 => ST_uOut_we1,
d1 => ST_uOut_d1,
q1 => ST_uOut_q1);
ANN_AXILiteS_s_axi_U : component ANN_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ANN_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
ap_return => ap_return,
P_mode => P_mode,
P_index1 => P_index1,
P_index2 => P_index2,
P_intIn_index3 => P_intIn_index3,
P_floatIn => P_floatIn);
ANN_fadd_32ns_32ns_32_5_full_dsp_U0 : component ANN_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_421_p0,
din1 => grp_fu_421_p1,
ce => grp_fu_421_ce,
dout => grp_fu_421_p2);
ANN_fmul_32ns_32ns_32_4_max_dsp_U1 : component ANN_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_428_p0,
din1 => ST_WandB_q0,
ce => grp_fu_428_ce,
dout => grp_fu_428_p2);
ANN_fdiv_32ns_32ns_32_16_U2 : component ANN_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_490,
din1 => sumsoft_reg_335,
ce => grp_fu_435_ce,
dout => grp_fu_435_p2);
ANN_sitofp_32ns_32_6_U3 : component ANN_sitofp_32ns_32_6
generic map (
ID => 1,
NUM_STAGE => 6,
din0_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => max_reg_277,
ce => grp_fu_440_ce,
dout => grp_fu_440_p1);
ANN_fptrunc_64ns_32_1_U4 : component ANN_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_444_p0,
dout => grp_fu_444_p1);
ANN_fpext_32ns_64_1_U5 : component ANN_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_447_p0,
dout => grp_fu_447_p1);
ANN_fcmp_32ns_32ns_1_1_U6 : component ANN_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_490,
din1 => ST_uOut_load_2_reg_1430,
opcode => tmp_62_fu_450_opcode,
dout => tmp_62_fu_450_p2);
ANN_dadd_64ns_64ns_64_5_full_dsp_U7 : component ANN_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_526,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_454_ce,
dout => grp_fu_454_p2);
ANN_ddiv_64ns_64ns_64_31_U8 : component ANN_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_42_reg_1552,
ce => grp_fu_459_ce,
dout => grp_fu_459_p2);
ANN_dexp_64ns_64ns_64_18_full_dsp_U9 : component ANN_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_521,
ce => grp_fu_464_ce,
dout => grp_fu_464_p2);
ANN_mux_4to1_sel2_32_1_U10 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_31_fu_619_p5,
dout => tmp_31_fu_619_p6);
ANN_mux_4to1_sel2_32_1_U11 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_29_reg_1459,
dout => tmp_fu_1053_p6);
ANN_mux_4to1_sel2_32_1_U12 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_45_reg_1469,
dout => tmp_53_fu_1078_p6);
ANN_mux_4to1_sel2_32_1_U13 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_64_reg_1484,
dout => tmp_27_fu_1182_p6);
ANN_mux_4to1_sel2_32_1_U14 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_70_reg_1494,
dout => tmp_54_fu_1207_p6);
ANN_mul_mul_7ns_14s_14_1_U15 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_80_fu_1333_p0,
din1 => tmp_79_fu_1095_p2,
dout => tmp_80_fu_1333_p2);
ANN_mul_mul_7ns_14s_14_1_U16 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_83_fu_1339_p0,
din1 => tmp_82_fu_1224_p2,
dout => tmp_83_fu_1339_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i_1_reg_347 assign process. --
i_1_reg_347_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = tmp_3_fu_897_p2))) then
i_1_reg_347 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) then
i_1_reg_347 <= i_5_reg_1570;
end if;
end if;
end process;
-- i_2_reg_381 assign process. --
i_2_reg_381_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and (ap_const_lv1_0 = tmp_22_fu_1195_p2))) then
i_2_reg_381 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
i_2_reg_381 <= i_6_reg_1623;
end if;
end if;
end process;
-- i_reg_289 assign process. --
i_reg_289_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and not((ap_const_lv1_0 = tmp_s_fu_567_p2)))) then
i_reg_289 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and (ap_const_lv1_0 = tmp_20_fu_1066_p2))) then
i_reg_289 <= i_3_fu_1105_p2;
end if;
end if;
end process;
-- j_1_reg_370 assign process. --
j_1_reg_370_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and not((ap_const_lv1_0 = tmp_22_fu_1195_p2)))) then
j_1_reg_370 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) then
j_1_reg_370 <= j_3_reg_1595;
end if;
end if;
end process;
-- j_reg_301 assign process. --
j_reg_301_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_3_fu_897_p2)))) then
j_reg_301 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) then
j_reg_301 <= j_2_reg_1502;
end if;
end if;
end process;
-- k_reg_324 assign process. --
k_reg_324_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = tmp_20_fu_1066_p2)))) then
k_reg_324 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
k_reg_324 <= k_1_reg_1532;
end if;
end if;
end process;
-- max_2_reg_266 assign process. --
max_2_reg_266_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
max_2_reg_266 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_2_reg_266 <= i_4_reg_1425;
end if;
end if;
end process;
-- max_reg_277 assign process. --
max_reg_277_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
max_reg_277 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_reg_277 <= max_1_fu_887_p3;
end if;
end if;
end process;
-- p_0_reg_392 assign process. --
p_0_reg_392_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and (ap_const_lv1_0 = tmp_14_fu_579_p2))) then
p_0_reg_392 <= ap_const_lv32_BF800000;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
p_0_reg_392 <= grp_fu_440_p1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
p_0_reg_392 <= ST_uOut_q0;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_1_fu_538_p2 = ap_const_lv1_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128) and (ap_const_lv1_0 = tmp_35_fu_1294_p2)))) then
p_0_reg_392 <= ap_const_lv32_0;
end if;
end if;
end process;
-- reg_490 assign process. --
reg_490_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
reg_490 <= ST_uOut_q1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10) or (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88) or (ap_const_logic_1 = ap_sig_cseq_ST_st130_fsm_129))) then
reg_490 <= ST_uOut_q0;
end if;
end if;
end process;
-- sum_1_reg_358 assign process. --
sum_1_reg_358_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and not((ap_const_lv1_0 = tmp_22_fu_1195_p2)))) then
sum_1_reg_358 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96)) then
sum_1_reg_358 <= grp_fu_421_p2;
end if;
end if;
end process;
-- sum_reg_312 assign process. --
sum_reg_312_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = tmp_20_fu_1066_p2)))) then
sum_reg_312 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22)) then
sum_reg_312 <= grp_fu_421_p2;
end if;
end if;
end process;
-- sumsoft_reg_335 assign process. --
sumsoft_reg_335_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = tmp_3_fu_897_p2))) then
sumsoft_reg_335 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st128_fsm_127)) then
sumsoft_reg_335 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
P_floatIn_read_reg_1345 <= P_floatIn;
ST_numLayer_load_reg_1353 <= ST_numLayer;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and (tmp_5_fu_727_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and (tmp_5_fu_727_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and (tmp_5_fu_727_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_2_fu_549_p2)) and not((tmp_5_fu_727_p1 = ap_const_lv2_2)) and not((tmp_5_fu_727_p1 = ap_const_lv2_1)) and not((tmp_5_fu_727_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_1_fu_538_p2 = ap_const_lv1_0)))) then
ST_numLayer <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = tmp_20_fu_1066_p2)))) then
ST_uOut_addr_5_reg_1519 <= tmp_82_cast_fu_1100_p1(8 - 1 downto 0);
tmp_53_reg_1507 <= tmp_53_fu_1078_p6;
tmp_80_reg_1513 <= tmp_80_fu_1333_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) and not((ap_const_lv1_0 = tmp_22_fu_1195_p2)))) then
ST_uOut_addr_7_reg_1587 <= tmp_84_cast_fu_1229_p1(8 - 1 downto 0);
tmp_54_reg_1575 <= tmp_54_fu_1207_p6;
tmp_83_reg_1581 <= tmp_83_fu_1339_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128) and not((ap_const_lv1_0 = tmp_35_fu_1294_p2)))) then
ST_uOut_addr_8_reg_1628 <= tmp_94_cast_fu_1314_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ST_uOut_load_2_reg_1430 <= ST_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_24_fu_765_p2)))) then
i_4_reg_1425 <= i_4_fu_798_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86)) then
i_5_reg_1570 <= i_5_fu_1201_p2;
tmp_27_reg_1562 <= tmp_27_fu_1182_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) then
i_6_reg_1623 <= i_6_fu_1299_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12)) then
j_2_reg_1502 <= j_2_fu_1072_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
j_3_reg_1595 <= j_3_fu_1243_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
k_1_reg_1532 <= k_1_fu_1120_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
max_2_cast_reg_1407(30 downto 0) <= max_2_cast_fu_761_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88) or (ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_499 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91))) then
reg_505 <= grp_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st29_fsm_28) or (ap_const_logic_1 = ap_sig_cseq_ST_st103_fsm_102))) then
reg_516 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29) or (ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103))) then
reg_521 <= grp_fu_447_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st48_fsm_47) or (ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121))) then
reg_526 <= grp_fu_464_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84) or (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122))) then
reg_532 <= grp_fu_444_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and not((ap_const_lv1_0 = tmp_4_fu_555_p2)))) then
tmp_16_reg_1399 <= tmp_16_fu_721_p2;
tmp_6_reg_1394 <= tmp_6_fu_683_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st148_fsm_147)) then
tmp_21_reg_1639 <= tmp_21_fu_1324_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_3_fu_897_p2)))) then
tmp_28_reg_1454(13 downto 3) <= tmp_28_fu_926_p2(13 downto 3);
tmp_29_reg_1459 <= tmp_29_fu_932_p1;
tmp_38_reg_1464(8 downto 3) <= tmp_38_fu_966_p2(8 downto 3);
tmp_45_reg_1469 <= tmp_45_fu_972_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
tmp_31_reg_1384 <= tmp_31_fu_619_p6;
tmp_76_reg_1378(8 downto 3) <= tmp_76_fu_609_p2(8 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st53_fsm_52)) then
tmp_42_reg_1552 <= grp_fu_454_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st84_fsm_83)) then
tmp_43_reg_1557 <= grp_fu_459_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st146_fsm_145)) then
tmp_52_reg_1634 <= grp_fu_435_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = tmp_3_fu_897_p2))) then
tmp_56_reg_1474(13 downto 3) <= tmp_56_fu_1000_p2(13 downto 3);
tmp_58_reg_1479(8 downto 3) <= tmp_58_fu_1006_p1(8 downto 3);
tmp_64_reg_1484 <= tmp_64_fu_1010_p1;
tmp_69_reg_1489(8 downto 3) <= tmp_69_fu_1043_p2(8 downto 3);
tmp_70_reg_1494 <= tmp_70_fu_1049_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_63_reg_1436 <= tmp_63_fu_881_p2;
end if;
end if;
end process;
tmp_76_reg_1378(2 downto 0) <= "000";
max_2_cast_reg_1407(31) <= '0';
tmp_28_reg_1454(2 downto 0) <= "000";
tmp_38_reg_1464(2 downto 0) <= "000";
tmp_56_reg_1474(2 downto 0) <= "000";
tmp_58_reg_1479(2 downto 0) <= "000";
tmp_69_reg_1489(2 downto 0) <= "000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2, tmp_s_fu_567_p2, tmp_10_fu_573_p2, tmp_14_fu_579_p2, tmp_24_fu_765_p2, tmp_3_fu_897_p2, tmp_20_fu_1066_p2, tmp_33_fu_1115_p2, tmp_22_fu_1195_p2, tmp_34_fu_1238_p2, tmp_35_fu_1294_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and not((ap_const_lv1_0 = tmp_14_fu_579_p2)))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((ap_start = ap_const_logic_0)) and (not((tmp_1_fu_538_p2 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_2_fu_549_p2)) or ((ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))) or ((ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and (ap_const_lv1_0 = tmp_10_fu_573_p2) and (ap_const_lv1_0 = tmp_14_fu_579_p2))))) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and not((ap_const_lv1_0 = tmp_10_fu_573_p2)))) then
ap_NS_fsm <= ap_ST_st11_fsm_10;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and not((ap_const_lv1_0 = tmp_s_fu_567_p2)))) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and not((ap_const_lv1_0 = tmp_4_fu_555_p2)))) then
ap_NS_fsm <= ap_ST_st148_fsm_147;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((ap_const_lv1_0 = tmp_24_fu_765_p2)) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st12_fsm_11 =>
if ((ap_const_lv1_0 = tmp_3_fu_897_p2)) then
ap_NS_fsm <= ap_ST_st87_fsm_86;
else
ap_NS_fsm <= ap_ST_st13_fsm_12;
end if;
when ap_ST_st13_fsm_12 =>
if ((ap_const_lv1_0 = tmp_20_fu_1066_p2)) then
ap_NS_fsm <= ap_ST_st12_fsm_11;
else
ap_NS_fsm <= ap_ST_st14_fsm_13;
end if;
when ap_ST_st14_fsm_13 =>
if ((ap_const_lv1_0 = tmp_33_fu_1115_p2)) then
ap_NS_fsm <= ap_ST_st24_fsm_23;
else
ap_NS_fsm <= ap_ST_st15_fsm_14;
end if;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st80_fsm_79;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st81_fsm_80 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st82_fsm_81 =>
ap_NS_fsm <= ap_ST_st83_fsm_82;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st87_fsm_86 =>
if (not((ap_const_lv1_0 = tmp_22_fu_1195_p2))) then
ap_NS_fsm <= ap_ST_st88_fsm_87;
else
ap_NS_fsm <= ap_ST_st129_fsm_128;
end if;
when ap_ST_st88_fsm_87 =>
if ((ap_const_lv1_0 = tmp_34_fu_1238_p2)) then
ap_NS_fsm <= ap_ST_st98_fsm_97;
else
ap_NS_fsm <= ap_ST_st89_fsm_88;
end if;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st92_fsm_91;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st93_fsm_92;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st123_fsm_122 =>
ap_NS_fsm <= ap_ST_st124_fsm_123;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st129_fsm_128 =>
if ((ap_const_lv1_0 = tmp_35_fu_1294_p2)) then
ap_NS_fsm <= ap_ST_st150_fsm_149;
else
ap_NS_fsm <= ap_ST_st130_fsm_129;
end if;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st142_fsm_141;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st143_fsm_142 =>
ap_NS_fsm <= ap_ST_st144_fsm_143;
when ap_ST_st144_fsm_143 =>
ap_NS_fsm <= ap_ST_st145_fsm_144;
when ap_ST_st145_fsm_144 =>
ap_NS_fsm <= ap_ST_st146_fsm_145;
when ap_ST_st146_fsm_145 =>
ap_NS_fsm <= ap_ST_st147_fsm_146;
when ap_ST_st147_fsm_146 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st148_fsm_147 =>
ap_NS_fsm <= ap_ST_st149_fsm_148;
when ap_ST_st149_fsm_148 =>
ap_NS_fsm <= ap_ST_st150_fsm_149;
when ap_ST_st150_fsm_149 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ANN_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13, tmp_33_fu_1115_p2, ap_sig_cseq_ST_st88_fsm_87, tmp_34_fu_1238_p2, ap_sig_cseq_ST_st149_fsm_148, tmp_88_cast_fu_1139_p1, tmp_90_cast_fu_1162_p1, tmp_91_cast_fu_1262_p1, tmp_93_cast_fu_1285_p1, tmp_21_cast_fu_1329_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148)) then
ST_WandB_address0 <= tmp_21_cast_fu_1329_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and (ap_const_lv1_0 = tmp_34_fu_1238_p2))) then
ST_WandB_address0 <= tmp_93_cast_fu_1285_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and not((ap_const_lv1_0 = tmp_34_fu_1238_p2)))) then
ST_WandB_address0 <= tmp_91_cast_fu_1262_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and (ap_const_lv1_0 = tmp_33_fu_1115_p2))) then
ST_WandB_address0 <= tmp_90_cast_fu_1162_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and not((ap_const_lv1_0 = tmp_33_fu_1115_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_1139_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st14_fsm_13, tmp_33_fu_1115_p2, ap_sig_cseq_ST_st88_fsm_87, tmp_34_fu_1238_p2, ap_sig_cseq_ST_st149_fsm_148)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and not((ap_const_lv1_0 = tmp_33_fu_1115_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) and (ap_const_lv1_0 = tmp_33_fu_1115_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and not((ap_const_lv1_0 = tmp_34_fu_1238_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) and (ap_const_lv1_0 = tmp_34_fu_1238_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_floatIn_read_reg_1345;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st149_fsm_148)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st149_fsm_148))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_address0 assign process. --
ST_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2, tmp_s_fu_567_p2, tmp_10_fu_573_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st129_fsm_128, tmp_66_cast_fu_673_p1, tmp_9_fu_678_p1, tmp_86_cast_fu_779_p1, tmp_92_cast_fu_1272_p1, tmp_94_cast_fu_1314_p1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2)))) then
ST_uOut_address0 <= tmp_9_fu_678_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128)) then
ST_uOut_address0 <= tmp_94_cast_fu_1314_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87)) then
ST_uOut_address0 <= tmp_92_cast_fu_1272_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address0 <= tmp_86_cast_fu_779_p1(8 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and not((ap_const_lv1_0 = tmp_10_fu_573_p2)))) then
ST_uOut_address0 <= tmp_66_cast_fu_673_p1(8 - 1 downto 0);
else
ST_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_address1 assign process. --
ST_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ST_uOut_addr_5_reg_1519, ap_sig_cseq_ST_st14_fsm_13, ST_uOut_addr_7_reg_1587, ST_uOut_addr_8_reg_1628, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, tmp_87_cast_fu_793_p1, tmp_89_cast_fu_1149_p1, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
ST_uOut_address1 <= ST_uOut_addr_8_reg_1628;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
ST_uOut_address1 <= ST_uOut_addr_7_reg_1587;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85)) then
ST_uOut_address1 <= ST_uOut_addr_5_reg_1519;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
ST_uOut_address1 <= tmp_89_cast_fu_1149_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address1 <= tmp_87_cast_fu_793_p1(8 - 1 downto 0);
else
ST_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_ce0 assign process. --
ST_uOut_ce0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2, tmp_s_fu_567_p2, tmp_10_fu_573_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st88_fsm_87, ap_sig_cseq_ST_st129_fsm_128)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and (ap_const_lv1_0 = tmp_8_fu_561_p2) and (ap_const_lv1_0 = tmp_s_fu_567_p2) and not((ap_const_lv1_0 = tmp_10_fu_573_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st88_fsm_87) or (ap_const_logic_1 = ap_sig_cseq_ST_st129_fsm_128) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))))) then
ST_uOut_ce0 <= ap_const_logic_1;
else
ST_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_ce1 assign process. --
ST_uOut_ce1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st124_fsm_123)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
ST_uOut_ce1 <= ap_const_logic_1;
else
ST_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
ST_uOut_d0 <= P_floatIn;
-- ST_uOut_d1 assign process. --
ST_uOut_d1_assign_proc : process(reg_532, tmp_52_reg_1634, ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st124_fsm_123)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146)) then
ST_uOut_d1 <= tmp_52_reg_1634;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
ST_uOut_d1 <= reg_532;
else
ST_uOut_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
ST_uOut_load_1_to_int_fu_804_p1 <= reg_490;
ST_uOut_load_2_to_int_fu_822_p1 <= ST_uOut_load_2_reg_1430;
-- ST_uOut_we0 assign process. --
ST_uOut_we0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_538_p2, tmp_2_fu_549_p2, tmp_4_fu_555_p2, tmp_8_fu_561_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_538_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_2_fu_549_p2) and (ap_const_lv1_0 = tmp_4_fu_555_p2) and not((ap_const_lv1_0 = tmp_8_fu_561_p2))))) then
ST_uOut_we0 <= ap_const_logic_1;
else
ST_uOut_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_we1 assign process. --
ST_uOut_we1_assign_proc : process(ap_sig_cseq_ST_st86_fsm_85, ap_sig_cseq_ST_st147_fsm_146, ap_sig_cseq_ST_st124_fsm_123)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85) or (ap_const_logic_1 = ap_sig_cseq_ST_st147_fsm_146) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
ST_uOut_we1 <= ap_const_logic_1;
else
ST_uOut_we1 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st150_fsm_149)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st150_fsm_149)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st150_fsm_149)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_392;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_1429 assign process. --
ap_sig_bdd_1429_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_1429 <= (ap_const_lv1_1 = ap_CS_fsm(149 downto 149));
end process;
-- ap_sig_bdd_168 assign process. --
ap_sig_bdd_168_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_168 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_253 assign process. --
ap_sig_bdd_253_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_253 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_260 assign process. --
ap_sig_bdd_260_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_260 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_268 assign process. --
ap_sig_bdd_268_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_268 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_275 assign process. --
ap_sig_bdd_275_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_275 <= (ap_const_lv1_1 = ap_CS_fsm(88 downto 88));
end process;
-- ap_sig_bdd_283 assign process. --
ap_sig_bdd_283_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_283 <= (ap_const_lv1_1 = ap_CS_fsm(129 downto 129));
end process;
-- ap_sig_bdd_292 assign process. --
ap_sig_bdd_292_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_292 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_301 assign process. --
ap_sig_bdd_301_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_301 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_311 assign process. --
ap_sig_bdd_311_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_311 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_318 assign process. --
ap_sig_bdd_318_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_318 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_328 assign process. --
ap_sig_bdd_328_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_328 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_335 assign process. --
ap_sig_bdd_335_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_335 <= (ap_const_lv1_1 = ap_CS_fsm(96 downto 96));
end process;
-- ap_sig_bdd_344 assign process. --
ap_sig_bdd_344_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_344 <= (ap_const_lv1_1 = ap_CS_fsm(28 downto 28));
end process;
-- ap_sig_bdd_351 assign process. --
ap_sig_bdd_351_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_351 <= (ap_const_lv1_1 = ap_CS_fsm(102 downto 102));
end process;
-- ap_sig_bdd_361 assign process. --
ap_sig_bdd_361_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_361 <= (ap_const_lv1_1 = ap_CS_fsm(29 downto 29));
end process;
-- ap_sig_bdd_368 assign process. --
ap_sig_bdd_368_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_368 <= (ap_const_lv1_1 = ap_CS_fsm(103 downto 103));
end process;
-- ap_sig_bdd_378 assign process. --
ap_sig_bdd_378_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_378 <= (ap_const_lv1_1 = ap_CS_fsm(47 downto 47));
end process;
-- ap_sig_bdd_385 assign process. --
ap_sig_bdd_385_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_385 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_395 assign process. --
ap_sig_bdd_395_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_395 <= (ap_const_lv1_1 = ap_CS_fsm(84 downto 84));
end process;
-- ap_sig_bdd_402 assign process. --
ap_sig_bdd_402_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_402 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_458 assign process. --
ap_sig_bdd_458_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_458 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_478 assign process. --
ap_sig_bdd_478_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_478 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_487 assign process. --
ap_sig_bdd_487_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_487 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_496 assign process. --
ap_sig_bdd_496_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_496 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_505 assign process. --
ap_sig_bdd_505_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_505 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_535 assign process. --
ap_sig_bdd_535_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_535 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_557 assign process. --
ap_sig_bdd_557_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_557 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_577 assign process. --
ap_sig_bdd_577_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_577 <= (ap_const_lv1_1 = ap_CS_fsm(52 downto 52));
end process;
-- ap_sig_bdd_586 assign process. --
ap_sig_bdd_586_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_586 <= (ap_const_lv1_1 = ap_CS_fsm(83 downto 83));
end process;
-- ap_sig_bdd_595 assign process. --
ap_sig_bdd_595_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_595 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_616 assign process. --
ap_sig_bdd_616_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_616 <= (ap_const_lv1_1 = ap_CS_fsm(87 downto 87));
end process;
-- ap_sig_bdd_635 assign process. --
ap_sig_bdd_635_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_635 <= (ap_const_lv1_1 = ap_CS_fsm(127 downto 127));
end process;
-- ap_sig_bdd_644 assign process. --
ap_sig_bdd_644_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_644 <= (ap_const_lv1_1 = ap_CS_fsm(128 downto 128));
end process;
-- ap_sig_bdd_659 assign process. --
ap_sig_bdd_659_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_659 <= (ap_const_lv1_1 = ap_CS_fsm(145 downto 145));
end process;
-- ap_sig_bdd_668 assign process. --
ap_sig_bdd_668_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_668 <= (ap_const_lv1_1 = ap_CS_fsm(147 downto 147));
end process;
-- ap_sig_bdd_690 assign process. --
ap_sig_bdd_690_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_690 <= (ap_const_lv1_1 = ap_CS_fsm(85 downto 85));
end process;
-- ap_sig_bdd_712 assign process. --
ap_sig_bdd_712_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_712 <= (ap_const_lv1_1 = ap_CS_fsm(146 downto 146));
end process;
-- ap_sig_bdd_728 assign process. --
ap_sig_bdd_728_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_728 <= (ap_const_lv1_1 = ap_CS_fsm(148 downto 148));
end process;
-- ap_sig_bdd_818 assign process. --
ap_sig_bdd_818_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_818 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_837 assign process. --
ap_sig_bdd_837_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_837 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_844 assign process. --
ap_sig_bdd_844_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_844 <= (ap_const_lv1_1 = ap_CS_fsm(24 downto 24));
end process;
-- ap_sig_bdd_852 assign process. --
ap_sig_bdd_852_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_852 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_bdd_859 assign process. --
ap_sig_bdd_859_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_859 <= (ap_const_lv1_1 = ap_CS_fsm(98 downto 98));
end process;
-- ap_sig_cseq_ST_st103_fsm_102 assign process. --
ap_sig_cseq_ST_st103_fsm_102_assign_proc : process(ap_sig_bdd_351)
begin
if (ap_sig_bdd_351) then
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st103_fsm_102 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st104_fsm_103 assign process. --
ap_sig_cseq_ST_st104_fsm_103_assign_proc : process(ap_sig_bdd_368)
begin
if (ap_sig_bdd_368) then
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st104_fsm_103 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_496)
begin
if (ap_sig_bdd_496) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_385)
begin
if (ap_sig_bdd_385) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_402)
begin
if (ap_sig_bdd_402) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_818)
begin
if (ap_sig_bdd_818) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st128_fsm_127 assign process. --
ap_sig_cseq_ST_st128_fsm_127_assign_proc : process(ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) then
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st128_fsm_127 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st129_fsm_128 assign process. --
ap_sig_cseq_ST_st129_fsm_128_assign_proc : process(ap_sig_bdd_644)
begin
if (ap_sig_bdd_644) then
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st129_fsm_128 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_505)
begin
if (ap_sig_bdd_505) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st130_fsm_129 assign process. --
ap_sig_cseq_ST_st130_fsm_129_assign_proc : process(ap_sig_bdd_283)
begin
if (ap_sig_bdd_283) then
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st130_fsm_129 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_535)
begin
if (ap_sig_bdd_535) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st146_fsm_145 assign process. --
ap_sig_cseq_ST_st146_fsm_145_assign_proc : process(ap_sig_bdd_659)
begin
if (ap_sig_bdd_659) then
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st146_fsm_145 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st147_fsm_146 assign process. --
ap_sig_cseq_ST_st147_fsm_146_assign_proc : process(ap_sig_bdd_712)
begin
if (ap_sig_bdd_712) then
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st147_fsm_146 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st148_fsm_147 assign process. --
ap_sig_cseq_ST_st148_fsm_147_assign_proc : process(ap_sig_bdd_668)
begin
if (ap_sig_bdd_668) then
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st148_fsm_147 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st149_fsm_148 assign process. --
ap_sig_cseq_ST_st149_fsm_148_assign_proc : process(ap_sig_bdd_728)
begin
if (ap_sig_bdd_728) then
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st149_fsm_148 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_557)
begin
if (ap_sig_bdd_557) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st150_fsm_149 assign process. --
ap_sig_cseq_ST_st150_fsm_149_assign_proc : process(ap_sig_bdd_1429)
begin
if (ap_sig_bdd_1429) then
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st150_fsm_149 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_268)
begin
if (ap_sig_bdd_268) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_311)
begin
if (ap_sig_bdd_311) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_837)
begin
if (ap_sig_bdd_837) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_168)
begin
if (ap_sig_bdd_168) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_328)
begin
if (ap_sig_bdd_328) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_292)
begin
if (ap_sig_bdd_292) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st25_fsm_24 assign process. --
ap_sig_cseq_ST_st25_fsm_24_assign_proc : process(ap_sig_bdd_844)
begin
if (ap_sig_bdd_844) then
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st25_fsm_24 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st29_fsm_28 assign process. --
ap_sig_cseq_ST_st29_fsm_28_assign_proc : process(ap_sig_bdd_344)
begin
if (ap_sig_bdd_344) then
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st29_fsm_28 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_458)
begin
if (ap_sig_bdd_458) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st30_fsm_29 assign process. --
ap_sig_cseq_ST_st30_fsm_29_assign_proc : process(ap_sig_bdd_361)
begin
if (ap_sig_bdd_361) then
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st30_fsm_29 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_253)
begin
if (ap_sig_bdd_253) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st48_fsm_47 assign process. --
ap_sig_cseq_ST_st48_fsm_47_assign_proc : process(ap_sig_bdd_378)
begin
if (ap_sig_bdd_378) then
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st48_fsm_47 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_478)
begin
if (ap_sig_bdd_478) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st53_fsm_52 assign process. --
ap_sig_cseq_ST_st53_fsm_52_assign_proc : process(ap_sig_bdd_577)
begin
if (ap_sig_bdd_577) then
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st53_fsm_52 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_487)
begin
if (ap_sig_bdd_487) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st84_fsm_83 assign process. --
ap_sig_cseq_ST_st84_fsm_83_assign_proc : process(ap_sig_bdd_586)
begin
if (ap_sig_bdd_586) then
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st84_fsm_83 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st85_fsm_84 assign process. --
ap_sig_cseq_ST_st85_fsm_84_assign_proc : process(ap_sig_bdd_395)
begin
if (ap_sig_bdd_395) then
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st85_fsm_84 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st86_fsm_85 assign process. --
ap_sig_cseq_ST_st86_fsm_85_assign_proc : process(ap_sig_bdd_690)
begin
if (ap_sig_bdd_690) then
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_595)
begin
if (ap_sig_bdd_595) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st88_fsm_87 assign process. --
ap_sig_cseq_ST_st88_fsm_87_assign_proc : process(ap_sig_bdd_616)
begin
if (ap_sig_bdd_616) then
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st88_fsm_87 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st89_fsm_88 assign process. --
ap_sig_cseq_ST_st89_fsm_88_assign_proc : process(ap_sig_bdd_275)
begin
if (ap_sig_bdd_275) then
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st89_fsm_88 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_318)
begin
if (ap_sig_bdd_318) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_852)
begin
if (ap_sig_bdd_852) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st97_fsm_96 assign process. --
ap_sig_cseq_ST_st97_fsm_96_assign_proc : process(ap_sig_bdd_335)
begin
if (ap_sig_bdd_335) then
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_301)
begin
if (ap_sig_bdd_301) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st99_fsm_98 assign process. --
ap_sig_cseq_ST_st99_fsm_98_assign_proc : process(ap_sig_bdd_859)
begin
if (ap_sig_bdd_859) then
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st99_fsm_98 <= ap_const_logic_0;
end if;
end process;
grp_fu_421_ce <= ap_const_logic_1;
-- grp_fu_421_p0 assign process. --
grp_fu_421_p0_assign_proc : process(sum_reg_312, sumsoft_reg_335, sum_1_reg_358, ap_sig_cseq_ST_st124_fsm_123, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st93_fsm_92, ap_sig_cseq_ST_st99_fsm_98)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_421_p0 <= sumsoft_reg_335;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
grp_fu_421_p0 <= sum_1_reg_358;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24))) then
grp_fu_421_p0 <= sum_reg_312;
else
grp_fu_421_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_421_p1 assign process. --
grp_fu_421_p1_assign_proc : process(reg_499, reg_505, reg_532, ap_sig_cseq_ST_st124_fsm_123, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st25_fsm_24, ap_sig_cseq_ST_st93_fsm_92, ap_sig_cseq_ST_st99_fsm_98)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123)) then
grp_fu_421_p1 <= reg_532;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st25_fsm_24) or (ap_const_logic_1 = ap_sig_cseq_ST_st99_fsm_98))) then
grp_fu_421_p1 <= reg_499;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
grp_fu_421_p1 <= reg_505;
else
grp_fu_421_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_428_ce <= ap_const_logic_1;
-- grp_fu_428_p0 assign process. --
grp_fu_428_p0_assign_proc : process(ST_uOut_q0, ST_uOut_q1, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st89_fsm_88)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st89_fsm_88)) then
grp_fu_428_p0 <= ST_uOut_q0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
grp_fu_428_p0 <= ST_uOut_q1;
else
grp_fu_428_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_435_ce <= ap_const_logic_1;
grp_fu_440_ce <= ap_const_logic_1;
-- grp_fu_444_p0 assign process. --
grp_fu_444_p0_assign_proc : process(reg_526, ap_sig_cseq_ST_st85_fsm_84, ap_sig_cseq_ST_st123_fsm_122, tmp_43_reg_1557)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
grp_fu_444_p0 <= reg_526;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st85_fsm_84)) then
grp_fu_444_p0 <= tmp_43_reg_1557;
else
grp_fu_444_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_447_p0 assign process. --
grp_fu_447_p0_assign_proc : process(reg_516, ap_sig_cseq_ST_st30_fsm_29, ap_sig_cseq_ST_st104_fsm_103, tmp_39_fu_1177_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st104_fsm_103)) then
grp_fu_447_p0 <= reg_516;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st30_fsm_29)) then
grp_fu_447_p0 <= tmp_39_fu_1177_p1;
else
grp_fu_447_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_454_ce <= ap_const_logic_1;
grp_fu_459_ce <= ap_const_logic_1;
grp_fu_464_ce <= ap_const_logic_1;
-- grp_fu_469_p1 assign process. --
grp_fu_469_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ST_numLayer, ST_numLayer_load_reg_1353, ap_sig_cseq_ST_st12_fsm_11)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11)) then
grp_fu_469_p1 <= ST_numLayer_load_reg_1353;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_469_p1 <= ST_numLayer;
else
grp_fu_469_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_469_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(grp_fu_469_p1));
i_2_cast_fu_1290_p1 <= std_logic_vector(resize(unsigned(i_2_reg_381),32));
i_3_fu_1105_p2 <= std_logic_vector(unsigned(i_reg_289) + unsigned(ap_const_lv31_1));
i_4_fu_798_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(max_2_reg_266));
i_5_fu_1201_p2 <= std_logic_vector(unsigned(i_1_reg_347) + unsigned(ap_const_lv32_1));
i_6_fu_1299_p2 <= std_logic_vector(unsigned(i_2_reg_381) + unsigned(ap_const_lv31_1));
i_cast_fu_893_p1 <= std_logic_vector(resize(unsigned(i_reg_289),32));
j_1_cast_fu_1234_p1 <= std_logic_vector(resize(unsigned(j_1_reg_370),32));
j_2_fu_1072_p2 <= std_logic_vector(unsigned(j_reg_301) + unsigned(ap_const_lv32_1));
j_3_fu_1243_p2 <= std_logic_vector(unsigned(j_1_reg_370) + unsigned(ap_const_lv31_1));
k_1_fu_1120_p2 <= std_logic_vector(unsigned(k_reg_324) + unsigned(ap_const_lv31_1));
k_cast_fu_1111_p1 <= std_logic_vector(resize(unsigned(k_reg_324),32));
max_1_fu_887_p3 <=
max_2_cast_reg_1407 when (tmp_63_reg_1436(0) = '1') else
max_reg_277;
max_2_cast_fu_761_p1 <= std_logic_vector(resize(unsigned(max_2_reg_266),32));
notlhs1_fu_857_p2 <= "0" when (tmp_57_fu_825_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_839_p2 <= "0" when (tmp_55_fu_808_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_863_p2 <= "1" when (tmp_97_fu_835_p1 = ap_const_lv23_0) else "0";
notrhs_fu_845_p2 <= "1" when (tmp_96_fu_818_p1 = ap_const_lv23_0) else "0";
p_shl10_cast_fu_641_p3 <= (tmp_72_fu_637_p1 & ap_const_lv5_0);
p_shl11_cast_fu_653_p3 <= (tmp_73_fu_649_p1 & ap_const_lv3_0);
p_shl12_cast_fu_589_p3 <= (tmp_74_fu_585_p1 & ap_const_lv5_0);
p_shl13_cast_fu_601_p3 <= (tmp_75_fu_597_p1 & ap_const_lv3_0);
p_shl1_cast_fu_707_p3 <= (tmp_12_fu_703_p1 & ap_const_lv3_0);
p_shl2_cast_fu_1023_p3 <= (tmp_67_fu_1019_p1 & ap_const_lv5_0);
p_shl3_cast_fu_1035_p3 <= (tmp_68_fu_1031_p1 & ap_const_lv3_0);
p_shl4_cast_fu_980_p3 <= (tmp_47_fu_976_p1 & ap_const_lv5_0);
p_shl5_cast_fu_992_p3 <= (tmp_51_fu_988_p1 & ap_const_lv3_0);
p_shl6_cast_fu_946_p3 <= (tmp_30_fu_942_p1 & ap_const_lv5_0);
p_shl7_cast_fu_958_p3 <= (tmp_36_fu_954_p1 & ap_const_lv3_0);
p_shl8_cast_fu_906_p3 <= (tmp_25_fu_902_p1 & ap_const_lv5_0);
p_shl9_cast_fu_918_p3 <= (tmp_26_fu_914_p1 & ap_const_lv3_0);
p_shl_cast_fu_695_p3 <= (tmp_11_fu_691_p1 & ap_const_lv5_0);
tmp_100_fu_1154_p1 <= tmp_53_reg_1507(14 - 1 downto 0);
tmp_101_fu_1249_p1 <= j_1_reg_370(9 - 1 downto 0);
tmp_102_fu_1253_p1 <= j_1_reg_370(14 - 1 downto 0);
tmp_103_fu_1277_p1 <= tmp_54_reg_1575(14 - 1 downto 0);
tmp_10_fu_573_p2 <= "1" when (P_mode = ap_const_lv32_6) else "0";
tmp_11_fu_691_p1 <= P_index1(9 - 1 downto 0);
tmp_12_fu_703_p1 <= P_index1(11 - 1 downto 0);
tmp_13_fu_715_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_695_p3) + unsigned(p_shl1_cast_fu_707_p3));
tmp_14_fu_579_p2 <= "1" when (P_mode = ap_const_lv32_7) else "0";
tmp_15_fu_936_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_reg_289));
tmp_16_fu_721_p2 <= std_logic_vector(unsigned(tmp_7_fu_687_p1) + unsigned(tmp_13_fu_715_p2));
tmp_19_fu_1319_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv14_29) * signed(tmp_16_reg_1399))), 14));
tmp_1_fu_538_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_20_fu_1066_p2 <= "1" when (signed(j_reg_301) < signed(tmp_fu_1053_p6)) else "0";
tmp_21_cast_fu_1329_p1 <= std_logic_vector(resize(signed(tmp_21_reg_1639),64));
tmp_21_fu_1324_p2 <= std_logic_vector(unsigned(tmp_6_reg_1394) + unsigned(tmp_19_fu_1319_p2));
tmp_22_fu_1195_p2 <= "1" when (signed(i_1_reg_347) < signed(tmp_27_fu_1182_p6)) else "0";
tmp_23_fu_1014_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1353));
tmp_24_fu_765_p2 <= "1" when (signed(max_2_cast_fu_761_p1) < signed(tmp_31_reg_1384)) else "0";
tmp_25_fu_902_p1 <= i_reg_289(9 - 1 downto 0);
tmp_26_fu_914_p1 <= i_reg_289(11 - 1 downto 0);
tmp_28_fu_926_p2 <= std_logic_vector(unsigned(p_shl8_cast_fu_906_p3) + unsigned(p_shl9_cast_fu_918_p3));
tmp_29_fu_932_p1 <= i_reg_289(2 - 1 downto 0);
tmp_2_fu_549_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_30_fu_942_p1 <= tmp_15_fu_936_p2(4 - 1 downto 0);
tmp_31_fu_619_p5 <= grp_fu_469_p2(2 - 1 downto 0);
tmp_33_fu_1115_p2 <= "1" when (signed(k_cast_fu_1111_p1) < signed(tmp_53_reg_1507)) else "0";
tmp_34_fu_1238_p2 <= "1" when (signed(j_1_cast_fu_1234_p1) < signed(tmp_54_reg_1575)) else "0";
tmp_35_fu_1294_p2 <= "1" when (signed(i_2_cast_fu_1290_p1) < signed(tmp_27_reg_1562)) else "0";
tmp_36_fu_954_p1 <= tmp_15_fu_936_p2(6 - 1 downto 0);
tmp_38_fu_966_p2 <= std_logic_vector(unsigned(p_shl6_cast_fu_946_p3) + unsigned(p_shl7_cast_fu_958_p3));
tmp_39_fu_1177_p1 <= tmp_39_neg_fu_1171_p2;
tmp_39_neg_fu_1171_p2 <= (tmp_39_to_int_fu_1167_p1 xor ap_const_lv32_80000000);
tmp_39_to_int_fu_1167_p1 <= reg_516;
tmp_3_fu_897_p2 <= "1" when (signed(i_cast_fu_893_p1) < signed(ST_numLayer_load_reg_1353)) else "0";
tmp_45_fu_972_p1 <= tmp_15_fu_936_p2(2 - 1 downto 0);
tmp_47_fu_976_p1 <= grp_fu_469_p2(9 - 1 downto 0);
tmp_4_fu_555_p2 <= "1" when (P_mode = ap_const_lv32_3) else "0";
tmp_51_fu_988_p1 <= grp_fu_469_p2(11 - 1 downto 0);
tmp_55_fu_808_p4 <= ST_uOut_load_1_to_int_fu_804_p1(30 downto 23);
tmp_56_fu_1000_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_980_p3) + unsigned(p_shl5_cast_fu_992_p3));
tmp_57_fu_825_p4 <= ST_uOut_load_2_to_int_fu_822_p1(30 downto 23);
tmp_58_fu_1006_p1 <= tmp_56_fu_1000_p2(9 - 1 downto 0);
tmp_59_fu_851_p2 <= (notrhs_fu_845_p2 or notlhs_fu_839_p2);
tmp_5_fu_727_p1 <= P_index1(2 - 1 downto 0);
tmp_60_fu_869_p2 <= (notrhs2_fu_863_p2 or notlhs1_fu_857_p2);
tmp_61_fu_875_p2 <= (tmp_59_fu_851_p2 and tmp_60_fu_869_p2);
tmp_62_fu_450_opcode <= ap_const_lv5_2;
tmp_63_fu_881_p2 <= (tmp_61_fu_875_p2 and tmp_62_fu_450_p2);
tmp_64_fu_1010_p1 <= grp_fu_469_p2(2 - 1 downto 0);
tmp_65_fu_661_p2 <= std_logic_vector(unsigned(p_shl10_cast_fu_641_p3) + unsigned(p_shl11_cast_fu_653_p3));
tmp_66_cast_fu_673_p1 <= std_logic_vector(resize(signed(tmp_66_fu_667_p2),64));
tmp_66_fu_667_p2 <= std_logic_vector(unsigned(tmp_71_fu_633_p1) + unsigned(tmp_65_fu_661_p2));
tmp_67_fu_1019_p1 <= tmp_23_fu_1014_p2(4 - 1 downto 0);
tmp_68_fu_1031_p1 <= tmp_23_fu_1014_p2(6 - 1 downto 0);
tmp_69_fu_1043_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_1023_p3) + unsigned(p_shl3_cast_fu_1035_p3));
tmp_6_fu_683_p1 <= P_intIn_index3(14 - 1 downto 0);
tmp_70_fu_1049_p1 <= tmp_23_fu_1014_p2(2 - 1 downto 0);
tmp_71_fu_633_p1 <= P_index2(9 - 1 downto 0);
tmp_72_fu_637_p1 <= P_index1(4 - 1 downto 0);
tmp_73_fu_649_p1 <= P_index1(6 - 1 downto 0);
tmp_74_fu_585_p1 <= grp_fu_469_p2(4 - 1 downto 0);
tmp_75_fu_597_p1 <= grp_fu_469_p2(6 - 1 downto 0);
tmp_76_fu_609_p2 <= std_logic_vector(unsigned(p_shl12_cast_fu_589_p3) + unsigned(p_shl13_cast_fu_601_p3));
tmp_78_fu_1091_p1 <= j_reg_301(14 - 1 downto 0);
tmp_79_fu_1095_p2 <= std_logic_vector(unsigned(tmp_28_reg_1454) + unsigned(tmp_78_fu_1091_p1));
tmp_7_fu_687_p1 <= P_index2(14 - 1 downto 0);
tmp_80_fu_1333_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_81_fu_1220_p1 <= i_1_reg_347(14 - 1 downto 0);
tmp_82_cast_fu_1100_p1 <= std_logic_vector(resize(signed(tmp_79_fu_1095_p2),64));
tmp_82_fu_1224_p2 <= std_logic_vector(unsigned(tmp_56_reg_1474) + unsigned(tmp_81_fu_1220_p1));
tmp_83_fu_1339_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_84_cast_fu_1229_p1 <= std_logic_vector(resize(signed(tmp_82_fu_1224_p2),64));
tmp_84_fu_1305_p1 <= i_2_reg_381(9 - 1 downto 0);
tmp_85_fu_1309_p2 <= std_logic_vector(unsigned(tmp_58_reg_1479) + unsigned(tmp_84_fu_1305_p1));
tmp_86_cast_fu_779_p1 <= std_logic_vector(resize(signed(tmp_86_fu_774_p2),64));
tmp_86_fu_774_p2 <= std_logic_vector(unsigned(tmp_94_fu_770_p1) + unsigned(tmp_76_reg_1378));
tmp_87_cast_fu_793_p1 <= std_logic_vector(resize(signed(tmp_87_fu_788_p2),64));
tmp_87_fu_788_p2 <= std_logic_vector(unsigned(tmp_95_fu_784_p1) + unsigned(tmp_76_reg_1378));
tmp_88_cast_fu_1139_p1 <= std_logic_vector(resize(signed(tmp_88_fu_1134_p2),64));
tmp_88_fu_1134_p2 <= std_logic_vector(signed(tmp_80_reg_1513) + signed(tmp_99_fu_1130_p1));
tmp_89_cast_fu_1149_p1 <= std_logic_vector(resize(unsigned(tmp_89_fu_1144_p2),64));
tmp_89_fu_1144_p2 <= std_logic_vector(unsigned(tmp_38_reg_1464) + unsigned(tmp_98_fu_1126_p1));
tmp_8_fu_561_p2 <= "1" when (P_mode = ap_const_lv32_4) else "0";
tmp_90_cast_fu_1162_p1 <= std_logic_vector(resize(signed(tmp_90_fu_1157_p2),64));
tmp_90_fu_1157_p2 <= std_logic_vector(signed(tmp_80_reg_1513) + signed(tmp_100_fu_1154_p1));
tmp_91_cast_fu_1262_p1 <= std_logic_vector(resize(signed(tmp_91_fu_1257_p2),64));
tmp_91_fu_1257_p2 <= std_logic_vector(signed(tmp_83_reg_1581) + signed(tmp_102_fu_1253_p1));
tmp_92_cast_fu_1272_p1 <= std_logic_vector(resize(signed(tmp_92_fu_1267_p2),64));
tmp_92_fu_1267_p2 <= std_logic_vector(unsigned(tmp_69_reg_1489) + unsigned(tmp_101_fu_1249_p1));
tmp_93_cast_fu_1285_p1 <= std_logic_vector(resize(signed(tmp_93_fu_1280_p2),64));
tmp_93_fu_1280_p2 <= std_logic_vector(signed(tmp_83_reg_1581) + signed(tmp_103_fu_1277_p1));
tmp_94_cast_fu_1314_p1 <= std_logic_vector(resize(signed(tmp_85_fu_1309_p2),64));
tmp_94_fu_770_p1 <= max_2_reg_266(9 - 1 downto 0);
tmp_95_fu_784_p1 <= max_reg_277(9 - 1 downto 0);
tmp_96_fu_818_p1 <= ST_uOut_load_1_to_int_fu_804_p1(23 - 1 downto 0);
tmp_97_fu_835_p1 <= ST_uOut_load_2_to_int_fu_822_p1(23 - 1 downto 0);
tmp_98_fu_1126_p1 <= k_reg_324(9 - 1 downto 0);
tmp_99_fu_1130_p1 <= k_reg_324(14 - 1 downto 0);
tmp_9_fu_678_p1 <= std_logic_vector(resize(signed(P_index1),64));
tmp_s_fu_567_p2 <= "1" when (P_mode = ap_const_lv32_5) else "0";
end behav;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SW_standalone/ip/design_SW_standalone_axi_gpio_0_0/synth/design_SW_standalone_axi_gpio_0_0.vhd
|
1
|
10147
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_9;
USE axi_gpio_v2_0_9.axi_gpio;
ENTITY design_SW_standalone_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_SW_standalone_axi_gpio_0_0;
ARCHITECTURE design_SW_standalone_axi_gpio_0_0_arch OF design_SW_standalone_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SW_standalone_axi_gpio_0_0_arch : ARCHITECTURE IS "design_SW_standalone_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SW_standalone_axi_gpio_0_0_arch: ARCHITECTURE IS "design_SW_standalone_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_SW_standalone_axi_gpio_0_0_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/lib_srl_fifo_v1_0/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd
|
15
|
10256
|
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cntr_incr_decr_addn_f.vhd
--
-- Description: This counter can increment, decrement or skip ahead
-- by an arbitrary amount.
--
-- If Reset is active, the value Cnt synchronously resets
-- to all ones. (This reset value, different than the
-- customary reset value of zero, caters to the original
-- application of cntr_incr_decr_addn_f as the address
-- counter for srl_fifo_rbu_f.)
--
-- Otherwise, on each Clk, one is added to Cnt if Incr is
-- asserted and one is subtracted if Decr is asserted. (If
-- both are asserted, then there is no change to Cnt.)
--
-- If Decr is not asserted, then the input value,
-- Nm_to_add, is added. (Simultaneous assertion of Incr
-- would add one more.) If Decr is asserted, then
-- N_to_add, is ignored, i.e., it is possible to decrement
-- by one or add N, but not both, and Decr overrides.
--
-- The value that Cnt will take on at the next clock
-- is available as Cnt_p1.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
--
-- History:
-- FLO 12/30/05 First Version.
--
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity cntr_incr_decr_addn_f is
generic (
C_SIZE : natural;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic; -- Note: the counter resets to all ones!
Incr : in std_logic;
Decr : in std_logic;
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
);
end entity cntr_incr_decr_addn_f;
---(
library lib_srl_fifo_v1_0_2;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture imp of cntr_incr_decr_addn_f is
-- constant COUNTER_PRIMS_AVAIL : boolean :=
-- supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
constant COUNTER_PRIMS_AVAIL : boolean := false;
signal cnt_i : std_logic_vector(Cnt'range);
signal cnt_i_p1 : std_logic_vector(Cnt'range);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
begin -- architecture imp
---(
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
--
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
) is
--
function qual_n_to_add(N_to_add : std_logic_vector;
Decr : std_logic
) return UNSIGNED is
variable r: UNSIGNED(N_to_add'range);
begin
for i in r'range loop
r(i) := N_to_add(i) or Decr;
end loop;
return r;
end;
--
function to_singleton_unsigned(s : std_logic) return unsigned is
variable r : unsigned(0 to 0) := (others => s);
begin
return r;
end;
--
begin
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
+ qual_n_to_add(N_to_add, Decr)
+ to_singleton_unsigned(Incr)
);
end process;
--
CNT_I_PROC : process(Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
cnt_i <= (others => '1');
else
cnt_i <= cnt_i_p1;
end if;
end if;
end process;
--
end generate INFERRED_GEN;
---)
Cnt <= cnt_i;
Cnt_p1 <= cnt_i_p1;
end architecture imp;
---)
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/lib_pkg_v1_0/hdl/src/vhdl/lib_pkg.vhd
|
28
|
16351
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_fcmp_32ns_32ns_1_1.vhd
|
1
|
4446
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 5;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/sim_tbs/ANN.autotb.vhd
|
1
|
43549
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity apatb_ANN_top is
generic (
AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns;
AUTOTB_TVIN_P_mode : STRING := "./c.ANN.autotvin_P_mode.dat";
AUTOTB_TVIN_P_index1 : STRING := "./c.ANN.autotvin_P_index1.dat";
AUTOTB_TVIN_P_index2 : STRING := "./c.ANN.autotvin_P_index2.dat";
AUTOTB_TVIN_P_intIn_index3 : STRING := "./c.ANN.autotvin_P_intIn_index3.dat";
AUTOTB_TVIN_P_floatIn : STRING := "./c.ANN.autotvin_P_floatIn.dat";
AUTOTB_TVIN_P_mode_out_wrapc : STRING := "./rtl.ANN.autotvin_P_mode.dat";
AUTOTB_TVIN_P_index1_out_wrapc : STRING := "./rtl.ANN.autotvin_P_index1.dat";
AUTOTB_TVIN_P_index2_out_wrapc : STRING := "./rtl.ANN.autotvin_P_index2.dat";
AUTOTB_TVIN_P_intIn_index3_out_wrapc : STRING := "./rtl.ANN.autotvin_P_intIn_index3.dat";
AUTOTB_TVIN_P_floatIn_out_wrapc : STRING := "./rtl.ANN.autotvin_P_floatIn.dat";
AUTOTB_TVOUT_ap_return : STRING := "./c.ANN.autotvout_ap_return.dat";
AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "./impl_rtl.ANN.autotvout_ap_return.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "ANN.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "ANN.performance.result.transaction.xml";
LENGTH_P_mode : INTEGER := 1;
LENGTH_P_index1 : INTEGER := 1;
LENGTH_P_index2 : INTEGER := 1;
LENGTH_P_intIn_index3 : INTEGER := 1;
LENGTH_P_floatIn : INTEGER := 1;
LENGTH_ap_return : INTEGER := 1;
AUTOTB_TRANSACTION_NUM : INTEGER := 265
);
end apatb_ANN_top;
architecture behav of apatb_ANN_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal AXILiteS_AWADDR: STD_LOGIC_VECTOR (6 DOWNTO 0);
signal AXILiteS_AWVALID: STD_LOGIC;
signal AXILiteS_AWREADY: STD_LOGIC;
signal AXILiteS_WVALID: STD_LOGIC;
signal AXILiteS_WREADY: STD_LOGIC;
signal AXILiteS_WDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal AXILiteS_WSTRB: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal AXILiteS_ARADDR: STD_LOGIC_VECTOR (6 DOWNTO 0);
signal AXILiteS_ARVALID: STD_LOGIC;
signal AXILiteS_ARREADY: STD_LOGIC;
signal AXILiteS_RVALID: STD_LOGIC;
signal AXILiteS_RREADY: STD_LOGIC;
signal AXILiteS_RDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal AXILiteS_RRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal AXILiteS_BVALID: STD_LOGIC;
signal AXILiteS_BREADY: STD_LOGIC;
signal AXILiteS_BRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ap_clk : STD_LOGIC;
signal ap_rst_n : STD_LOGIC;
signal interrupt : STD_LOGIC;
signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
signal reported_stuck : STD_LOGIC := '0';
shared variable reported_stuck_cnt : INTEGER := 0;
component ANN is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
interrupt : OUT STD_LOGIC);
end component;
-- The signal of port P_mode
shared variable AESL_REG_P_mode : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_index1
shared variable AESL_REG_P_index1 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_index2
shared variable AESL_REG_P_index2 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_intIn_index3
shared variable AESL_REG_P_intIn_index3 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_floatIn
shared variable AESL_REG_P_floatIn : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal AESL_slave_output_done : STD_LOGIC;
signal AESL_slave_start : STD_LOGIC;
signal AESL_slave_write_start_in : STD_LOGIC;
signal AESL_slave_write_start_finish : STD_LOGIC;
signal AESL_slave_ready : STD_LOGIC;
signal slave_start_status : STD_LOGIC := '0';
signal start_rise : STD_LOGIC := '0';
signal ready_rise : STD_LOGIC := '0';
signal slave_done_status : STD_LOGIC := '0';
signal AXILiteS_read_data_finish : STD_LOGIC;
signal AXILiteS_write_data_finish : STD_LOGIC;
component AESL_AXI_SLAVE_AXILiteS is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_AWADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_WREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WDATA : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_WSTRB : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_ARADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_RDATA : IN STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_RRESP : IN STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_BVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_BRESP : IN STD_LOGIC_VECTOR;
TRAN_AXILiteS_read_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_write_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_ready_out : OUT STD_LOGIC;
TRAN_AXILiteS_ready_in : IN STD_LOGIC;
TRAN_AXILiteS_done_out : OUT STD_LOGIC;
TRAN_AXILiteS_idle_out : OUT STD_LOGIC;
TRAN_AXILiteS_write_start_in : IN STD_LOGIC;
TRAN_AXILiteS_write_start_finish : OUT STD_LOGIC;
TRAN_AXILiteS_transaction_done_in : IN STD_LOGIC;
TRAN_AXILiteS_interrupt : IN STD_LOGIC;
TRAN_AXILiteS_start_in : IN STD_LOGIC
);
end component;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
function esl_equal_std_lv (lv1 : STD_LOGIC_VECTOR; lv2 : STD_LOGIC_VECTOR) return BOOLEAN is
variable len : INTEGER;
variable i : INTEGER;
begin
if (lv1'length > lv2'length) then
len := lv2'length;
for i in lv1'length - 1 downto lv2'length loop
if(lv1(i) = '1') then
return false;
end if;
end loop;
else
len := lv1'length;
for i in lv2'length - 1 downto lv1'length loop
if(lv2(i) = '1') then
return false;
end if;
end loop;
end if;
for i in len - 1 downto 0 loop
if (lv1(i) = '1' and lv2(i) /= '1') or (lv1(i) = '0' and lv2(i) /= '0') then
return false;
end if;
end loop;
return true;
end function;
procedure post_check (file fp1 : TEXT; file fp2 : TEXT) is
variable token_line1 : LINE;
variable token_line2 : LINE;
variable token1 : STRING(1 to 200);
variable token2 : STRING(1 to 200);
variable golden : STD_LOGIC_VECTOR(199 downto 0);
variable result : STD_LOGIC_VECTOR(199 downto 0);
variable l1 : INTEGER;
variable l2 : INTEGER;
begin
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
if(token1(1 to 13) /= "[[[runtime]]]" or token2(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
while(token1(1 to 14) /= "[[[/runtime]]]" and token2(1 to 14) /= "[[[/runtime]]]") loop
if(token1(1 to 15) /= "[[transaction]]" and token2(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1); -- Skip transaction number
esl_read_token(fp2, token_line2, token2); -- Skip transaction number
esl_read_token(fp1, token_line1, token1, l1);
esl_read_token(fp2, token_line2, token2, l2);
while(token1(1 to 16) /= "[[/transaction]]" and token2(1 to 16) /= "[[/transaction]]") loop
golden := esl_str2lv_hex(token1, 200 );
result := esl_str2lv_hex(token2, 200 );
if(esl_equal_std_lv(golden, result) = false) then
report token1(1 to l1) & " (expected) vs. " & token2(1 to l2) & " (actual) - mismatch";
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
end loop;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
end loop;
end procedure post_check;
begin
AESL_inst_ANN : ANN port map (
s_axi_AXILiteS_AWADDR => AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID => AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => AXILiteS_AWREADY,
s_axi_AXILiteS_WVALID => AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => AXILiteS_WREADY,
s_axi_AXILiteS_WDATA => AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => AXILiteS_WSTRB,
s_axi_AXILiteS_ARADDR => AXILiteS_ARADDR,
s_axi_AXILiteS_ARVALID => AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => AXILiteS_ARREADY,
s_axi_AXILiteS_RVALID => AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => AXILiteS_RREADY,
s_axi_AXILiteS_RDATA => AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => AXILiteS_RRESP,
s_axi_AXILiteS_BVALID => AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => AXILiteS_BREADY,
s_axi_AXILiteS_BRESP => AXILiteS_BRESP,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst_n <= AESL_reset;
AESL_reset <= rst;
AESL_start <= start;
AESL_ce <= ce;
AESL_continue <= continue;
AESL_slave_write_start_in <= slave_start_status and AXILiteS_write_data_finish;
AESL_slave_start <= AESL_slave_write_start_finish;
AESL_done <= slave_done_status and AXILiteS_read_data_finish;
slave_start_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
slave_start_status <= '1';
else
if (AESL_start = '1' ) then
start_rise <= '1';
end if;
if (start_rise = '1' and AESL_done = '1' ) then
slave_start_status <= '1';
end if;
if (AESL_slave_write_start_in = '1') then
slave_start_status <= '0';
start_rise <= '0';
end if;
end if;
end if;
end process;
slave_ready_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_slave_ready <= '0';
ready_rise <= '0';
else
if (AESL_ready = '1' ) then
ready_rise <= '1';
end if;
if (ready_rise = '1' and AESL_done_delay = '1' ) then
AESL_slave_ready <= '1';
end if;
if (AESL_slave_ready = '1') then
AESL_slave_ready <= '0';
ready_rise <= '0';
end if;
end if;
end if;
end process;
slave_done_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if (AESL_done = '1') then
slave_done_status <= '0';
elsif (AESL_slave_output_done = '1' ) then
slave_done_status <= '1';
end if;
end if;
end process;
AESL_axi_slave_inst_AXILiteS : AESL_AXI_SLAVE_AXILiteS port map (
clk => AESL_clock,
reset => AESL_reset,
TRAN_s_axi_AXILiteS_AWADDR => AXILiteS_AWADDR,
TRAN_s_axi_AXILiteS_AWVALID => AXILiteS_AWVALID,
TRAN_s_axi_AXILiteS_AWREADY => AXILiteS_AWREADY,
TRAN_s_axi_AXILiteS_WVALID => AXILiteS_WVALID,
TRAN_s_axi_AXILiteS_WREADY => AXILiteS_WREADY,
TRAN_s_axi_AXILiteS_WDATA => AXILiteS_WDATA,
TRAN_s_axi_AXILiteS_WSTRB => AXILiteS_WSTRB,
TRAN_s_axi_AXILiteS_ARADDR => AXILiteS_ARADDR,
TRAN_s_axi_AXILiteS_ARVALID => AXILiteS_ARVALID,
TRAN_s_axi_AXILiteS_ARREADY => AXILiteS_ARREADY,
TRAN_s_axi_AXILiteS_RVALID => AXILiteS_RVALID,
TRAN_s_axi_AXILiteS_RREADY => AXILiteS_RREADY,
TRAN_s_axi_AXILiteS_RDATA => AXILiteS_RDATA,
TRAN_s_axi_AXILiteS_RRESP => AXILiteS_RRESP,
TRAN_s_axi_AXILiteS_BVALID => AXILiteS_BVALID,
TRAN_s_axi_AXILiteS_BREADY => AXILiteS_BREADY,
TRAN_s_axi_AXILiteS_BRESP => AXILiteS_BRESP,
TRAN_AXILiteS_read_data_finish => AXILiteS_read_data_finish,
TRAN_AXILiteS_write_data_finish => AXILiteS_write_data_finish,
TRAN_AXILiteS_ready_out => AESL_ready,
TRAN_AXILiteS_ready_in => AESL_slave_ready,
TRAN_AXILiteS_done_out => AESL_slave_output_done,
TRAN_AXILiteS_idle_out => AESL_idle,
TRAN_AXILiteS_write_start_in => AESL_slave_write_start_in,
TRAN_AXILiteS_write_start_finish => AESL_slave_write_start_finish,
TRAN_AXILiteS_transaction_done_in => AESL_done_delay,
TRAN_AXILiteS_interrupt => interrupt,
TRAN_AXILiteS_start_in => AESL_slave_start
);
-- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor
write_output_transactor_ap_return_runtime_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
begin
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
file_close(fp);
while done_cnt /= AUTOTB_TRANSACTION_NUM loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
generate_ready_cnt_proc : process(ready_initial, AESL_clock)
begin
if(AESL_clock'event and AESL_clock = '0') then
if(ready_initial = '1') then
ready_cnt <= conv_std_logic_vector(1, 32);
end if;
elsif(AESL_clock'event and AESL_clock = '1') then
if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_ready = '1') then
ready_cnt <= ready_cnt + 1;
end if;
end if;
end if;
end process;
generate_done_cnt_proc : process(AESL_reset, AESL_clock)
begin
if(AESL_reset = '0') then
done_cnt <= (others => '0');
elsif(AESL_clock'event and AESL_clock = '1') then
if(done_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_done = '1') then
done_cnt <= done_cnt + 1;
end if;
end if;
end if;
end process;
generate_sim_done_proc : process
file fp1 : TEXT;
file fp2 : TEXT;
variable fstatus1 : FILE_OPEN_STATUS;
variable fstatus2 : FILE_OPEN_STATUS;
begin
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus1, fp1, "./rtl.ANN.autotvout_ap_return.dat", READ_MODE);
file_open(fstatus2, fp2, "./impl_rtl.ANN.autotvout_ap_return.dat", READ_MODE);
if(fstatus1 /= OPEN_OK) then
assert false report string'("Open file rtl.ANN.autotvout_ap_return.dat failed!!!") severity note;
elsif(fstatus2 /= OPEN_OK) then
assert false report string'("Open file impl_rtl.ANN.autotvout_ap_return.dat failed!!!") severity note;
else
report string'("Comparing rtl.ANN.autotvout_ap_return.dat with impl_rtl.ANN.autotvout_ap_return.dat");
post_check(fp1, fp2);
end if;
file_close(fp1);
file_close(fp2);
report "Simulation Passed.";
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for AUTOTB_CLOCK_PERIOD_DIV2;
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '0';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '1';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '1';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1';
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_ready_delay;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '0') then
if(AESL_reset = '0') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
reported_stuck_cnt := 0;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
reported_stuck <= '0';
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_slave_write_start_finish = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '1');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i);
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
lattotal := lattotal + latthistime;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrthistime := latthistime;
else
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
end if;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
thrtotal := thrtotal + thrthistime;
end loop;
lataver := lattotal / AUTOTB_TRANSACTION_NUM;
thraver := thrtotal / AUTOTB_TRANSACTION_NUM;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrmax := 0;
thrmin := 0;
thraver := 0;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
else
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
end if;
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
if (AUTOTB_TRANSACTION_NUM = 1) then
i := 0;
thr_array(i) := 0;
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
else
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
end if;
file_close(fp);
wait;
end process;
end behav;
|
gpl-3.0
|
hoglet67/AtomVGAWing
|
src/DCM_B.vhd
|
1
|
2523
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM_B.vhd
-- /___/ /\ Timestamp : 03/01/2013 20:52:36
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/dmb/papilio/projects/VGATest/ipcore_dir/DCM_B.xaw -st DCM_B.vhd
--Design Name: DCM_B
--Device: xc3s500e-5vq100
--
-- Module DCM_B
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.61 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_B is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_B;
architecture BEHAVIORAL of DCM_B is
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 15,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ip/design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0/synth/design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0.vhd
|
1
|
7056
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0;
ARCHITECTURE design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/ip/ANN_ap_ddiv_29_no_dsp_64.vhd
|
6
|
12691
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_ddiv_29_no_dsp_64;
ARCHITECTURE ANN_ap_ddiv_29_no_dsp_64_arch OF ANN_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "ANN_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "ANN_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_ddiv_29_no_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_sitofp_4_no_dsp_32/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
|
24
|
73491
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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zkhz98SR0w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/bd/design_SWandHW_standalone/ipshared/xilinx.com/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
|
24
|
73491
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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QPku
`protect end_protected
|
gpl-3.0
|
bonfireprocessor/bonfire-soc
|
clkgen.vhd
|
2
|
7200
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk32Mhz_out: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_ulogic;
--signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clk3: std_ulogic;
signal clkin_i_2: std_logic;
-- signal clk_div: std_logic;
-- signal count: integer;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
--process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
process(dcmlocked, clkout_i, rstin)
begin
--if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
-- clkin_inst: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i
-- );
clkin_i <= clkin;
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
clk3_inst: BUFG port map ( I => clk3, O => clk32Mhz_out );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 30,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => clk3, -- TH 32Mhz clock
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
--DCM_inst_1mhz : DCM
-- generic map (
-- CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
-- CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
-- CLKIN_PERIOD => 31.25, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
-- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
-- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
-- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
-- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-- )
-- port map (
-- CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
-- CLK180 => open, -- 180 degree DCM CLK output
-- CLK270 => open, -- 270 degree DCM CLK output
-- CLK2X => open, -- 2X DCM CLK output
-- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-- CLK90 => open, -- 90 degree DCM CLK output
-- CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => open, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => open, -- 180 degree CLK synthesis out
-- LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
-- PSDONE => open, -- Dynamic phase adjust done output
-- STATUS => open, -- 8-bit DCM status bits output
-- CLKFB => clkfb_1mhz, -- DCM clock feedback
-- CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => '0', -- Dynamic phase adjust clock input
-- PSEN => '0', -- Dynamic phase adjust enable input
-- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
-- RST => '0' -- DCM asynchronous reset input
-- );
-- clkfx_inst_1mhz: BUFG
-- port map (
-- I => dcmclock_1mhz,
-- O => clk_1Mhz_out
-- );
--clkin_i_1mhz <= clkout_i;
end behave;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_scc_wr.vhd
|
13
|
44376
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc_wr.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc_wr is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc_wr;
architecture implementation of axi_sg_scc_wr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_cmd2addr_valid1 : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= (others => '1'); --sig_next_strt_strb; -- always F
mstr2data_last_strb <= (others => '1'); --sig_next_end_strb; -- always F
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
-- mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_cmd_valid <= sig_cmd2addr_valid1; --sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
WR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00000000" when sig_cmd_tag_reg (0) = '1'
else "00000101"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate WR_EXTRA_FIELDS;
NOWR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000000";
end generate NOWR_EXTRA_FIELDS;
-- sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd2addr_valid1 <= '1';
sig_cmd_burst_reg <= sig_next_burst;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
elsif (sig_btt_is_zero_reg = '1') then
sm_set_error <= '1';
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
-- sm_set_error <= sm_set_error_ns ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_ddiv_64ns_64ns_64_31.vhd
|
4
|
3362
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd
|
21
|
17850
|
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/ANN_dadd_64ns_64ns_64_5_full_dsp.vhd
|
6
|
3340
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 7;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dadd_3_full_dsp_64_u : component ANN_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/vhdl/ANN_fptrunc_64ns_32_1.vhd
|
6
|
1942
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fptrunc_64ns_32_1 is
generic (
ID : integer := 4;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component ANN_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fptrunc_0_no_dsp_64_u : component ANN_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd
|
4
|
21799
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library lib_fifo_v1_0_4;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1_8.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd
|
18
|
75691
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_demux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_datamover_wr_demux;
architecture implementation of axi_datamover_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/ip/ANN_ap_fcmp_0_no_dsp_32.vhd
|
6
|
12778
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fcmp_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ANN_ap_fcmp_0_no_dsp_32;
ARCHITECTURE ANN_ap_fcmp_0_no_dsp_32_arch OF ANN_ap_fcmp_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fcmp_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fcmp_0_no_dsp_32_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_queue.vhd
|
7
|
41099
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
--use axi_sg_v4_1_2.axi_sg_afifo_autord.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.sync_fifo_fg;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
-- Channel Control --
desc1_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
desc2_flush : in std_logic ; --
ftch1_active : in std_logic ; --
ftch2_active : in std_logic ; --
ftch1_queue_empty : out std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch1_queue_full : out std_logic ; --
ftch2_queue_full : out std_logic ; --
ftch1_pause : out std_logic ; --
ftch2_pause : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing1_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
sof_ftch_desc : in std_logic ;
m_axis1_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
--
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_64_cdma : in std_logic_vector --
(31 downto 0) ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
data_concat_tlast : in std_logic ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_aclk : in std_logic ; --
m_axis_ftch1_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch1_tvalid : out std_logic ; --
m_axis_ftch1_tready : in std_logic ; --
m_axis_ftch1_tlast : out std_logic ; --
m_axis_ftch1_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch1_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch1_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
m_axis_ftch2_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch2_tvalid : out std_logic ; --
m_axis_ftch2_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch2_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch2_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
m_axis_ftch2_tready : in std_logic ; --
m_axis_ftch2_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Number of words deep fifo needs to be
-- 6 is subtracted as BD address are always 16 word aligned
constant FIFO_WIDTH : integer := (128*C_ENABLE_CDMA + 97*(1-C_ENABLE_CDMA) -6);
constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2*C_ENABLE_MULTI_CHANNEL;
--constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
-- * C_SG_WORDS_TO_FETCH1));
constant FETCH_QUEUE_DEPTH : integer := 16;
-- Select between BRAM or Logic Memory Type
constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG_WORDS_TO_FETCH1 > 16);
constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1);
constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1;
constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461
constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH;
constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1));
-- Select between BRAM or Logic Memory Type
constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1 > 16);
constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1);
constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1;
constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant DESC2QUEUE_VECT_WIDTH : integer := 4;
--constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
--constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461
constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tvalid_new : std_logic := '0';
signal ftch_tdata : std_logic_vector
(31 downto 0) := (others => '0');
signal ftch_tdata_new, reg1, reg2 : std_logic_vector
(FIFO_WIDTH-1 downto 0) := (others => '0');
signal ftch_tdata_new_64, reg1_64, reg2_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal ftch_tdata_new_bd, reg2_bd_64, reg1_bd_64 : std_logic_vector (31 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tlast_new : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal ftch_tready_ch1 : std_logic := '0';
signal ftch_tready_ch2 : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-- FIFO signals
signal queue_rden2 : std_logic := '0';
signal queue_rden2_new : std_logic := '0';
signal queue_wren2 : std_logic := '0';
signal queue_wren2_new : std_logic := '0';
signal queue_empty2 : std_logic := '0';
signal queue_empty2_new : std_logic := '0';
signal queue_rden : std_logic := '0';
signal queue_rden_new : std_logic := '0';
signal queue_wren : std_logic := '0';
signal queue_wren_new : std_logic := '0';
signal queue_empty : std_logic := '0';
signal queue_empty_new : std_logic := '0';
signal queue_dout_valid : std_logic := '0';
signal queue_dout2_valid : std_logic := '0';
signal queue_full_new : std_logic := '0';
signal queue_full2_new : std_logic := '0';
signal queue_full, queue_full2 : std_logic := '0';
signal queue_din_new : std_logic_vector
(127 downto 0) := (others => '0');
signal queue_dout_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_dout2_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout2_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout2_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout2_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_din : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout2 : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_sinit : std_logic := '0';
signal queue_sinit2 : std_logic := '0';
signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal ftch_no_room : std_logic;
signal ftch_active : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal sof_ftch_desc_del : std_logic;
signal sof_ftch_desc_del1 : std_logic;
signal sof_ftch_desc_pulse : std_logic;
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal xfer_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1'))then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
ftch_active <= ftch1_active or ftch2_active;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
CURRENT_BD_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(32+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_64;
CURRENT_BD_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_32;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
m_axis_ftch1_tdata_mcdma_new <= (others => '0');
m_axis_ftch2_tdata_mcdma_new <= (others => '0');
COUNTER_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
counter <= (others => '0');
elsif (m_axis_mm2s_tvalid = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process COUNTER_PROCESS;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate
begin
CDMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (63 downto 0) <= data_concat_64_cdma & data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate CDMA_FIELDS_64;
ftch_tdata_new (95 downto 0) <= data_concat;
-- BD is always 16 word aligned
ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6);
end generate CDMA_FIELDS;
DMA_FIELDS : if C_ENABLE_CDMA = 0 generate
begin
DMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (31 downto 0) <= data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate DMA_FIELDS_64;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
-- BD is always 16 word aligned
ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6);
end generate DMA_FIELDS;
ftch_tvalid_new <= data_concat_valid and ftch_active;
ftch_tlast_new <= data_concat_tlast and ftch_active;
GEN_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_rden_new = '1') then
queue_empty_new <= '1';
queue_full_new <= '0';
elsif (queue_wren_new = '1') then
queue_empty_new <= '0';
queue_full_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
reg1 <= (others => '0');
reg1_64 <= (others => '0');
reg1_bd_64 <= (others => '0');
elsif (queue_wren_new = '1') then
reg1 <= ftch_tdata_new;
reg1_64 <= ftch_tdata_new_64;
reg1_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
queue_dout_new <= (others => '0');
queue_dout_new_64 <= (others => '0');
queue_dout_new_bd <= (others => '0');
elsif (queue_rden_new = '1') then
queue_dout_new <= reg1;
queue_dout_new_64 <= reg1_64;
queue_dout_new_bd <= reg1_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_dout_valid = '1') then
queue_dout_valid <= '0';
elsif (queue_rden_new = '1') then
queue_dout_valid <= '1';
end if;
end if;
end process;
MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH1_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren_new ,
Rd_en => queue_rden_new ,
Dout => queue_dout_mcdma_new ,
Full => open, --queue_full_new ,
Empty => open, --queue_empty_new ,
Almost_full => open ,
Data_count => open, --queue_dcount_new ,
Rd_ack => open, --queue_dout_valid, --open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new;
end generate MCDMA_MM2S;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate
begin
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_2.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
end generate GEN_MM2S;
GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_rden2_new = '1') then
queue_empty2_new <= '1';
queue_full2_new <= '0';
elsif (queue_wren2_new = '1') then
queue_empty2_new <= '0';
queue_full2_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
reg2 <= (others => '0');
reg2_64 <= (others => '0');
reg2_bd_64 <= (others => '0');
elsif (queue_wren2_new = '1') then
reg2 <= ftch_tdata_new;
reg2_64 <= ftch_tdata_new_64;
reg2_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
queue_dout2_new <= (others => '0');
queue_dout2_new_64 <= (others => '0');
queue_dout2_new_bd <= (others => '0');
elsif (queue_rden2_new = '1') then
queue_dout2_new <= reg2;
queue_dout2_new_64 <= reg2_64;
queue_dout2_new_bd <= reg2_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_dout2_valid = '1') then
queue_dout2_valid <= '0';
elsif (queue_rden2_new = '1') then
queue_dout2_valid <= '1';
end if;
end if;
end process;
MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH2_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_4.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit2 ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren2_new ,
Rd_en => queue_rden2_new ,
Dout => queue_dout2_new ,
Full => open, --queue_full2_new ,
Empty => open, --queue_empty2_new ,
Almost_full => open ,
Data_count => queue_dcount2_new ,
Rd_ack => open, --queue_dout2_valid ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new;
end generate MCDMA_S2MM;
end generate GEN_S2MM;
-----------------------------------------------------------------------
-- Internal Side
-----------------------------------------------------------------------
-- Drive tready with fifo not full
ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2;
-- Following is the APP data that goes into APP FIFO
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate
begin
--queue_full_new <= '1' when (queue_dcount_new = "00100") else '0';
queue_sinit <= desc1_flush or not m_axi_sg_aresetn;
ftch_tready_ch1 <= (not queue_full and ftch1_active);
m_axis1_mm2s_tready <= ftch_tready_ch1;
-- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched.
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch1_active;
-- Wr_en of BD FIFO
queue_wren_new <= not queue_full_new
and ftch_tvalid_new
and ftch1_active;
ftch1_queue_empty <= queue_empty_new;
ftch1_queue_full <= queue_full_new;
ftch1_pause <= queue_full_new;
-- RD_en of APP FIFO based on empty and tready
-- RD_EN of BD FIFO based on empty and tready
queue_rden_new <= not queue_empty_new
and m_axis_ftch1_tready;
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle);
-- below signal triggers the fetch of BD in MM2S Mngr
m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
FTCH_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new_bd & queue_dout_new_64 & queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64;
FTCH_FIELDS_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32;
writing1_curdesc_out <= writing_curdesc and ftch1_active;
NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NOCONTROL_STREAM_ASST;
end generate GEN_CH1_CTRL;
GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
ftch_tready_ch1 <= '0';
m_axis1_mm2s_tready <= '0';
-- Write to fifo if it is not full and data is valid
queue_wren <= '0';
ftch1_queue_empty <= '0';
ftch1_queue_full <= '0';
ftch1_pause <= '0';
queue_rden <= '0';
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
writing1_curdesc_out <= '0';
m_axis_ftch1_tdata_new <= (others => '0');
m_axis_ftch1_tvalid_new <= '0';
m_axis_ftch1_desc_available <= '0';
end generate GEN_NO_CH1_CTRL;
GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate
begin
queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn;
ftch_tready_ch2 <= (not queue_full2_new and ftch2_active);
m_axis2_mm2s_tready <= ftch_tready_ch2;
queue_wren2 <= '0';
-- Wr_en for S2MM BD FIFO
queue_wren2_new <= not queue_full2_new
and ftch_tvalid_new
and ftch2_active;
--queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
ftch2_queue_empty <= queue_empty2_new;
ftch2_queue_full <= queue_full2_new;
ftch2_pause <= queue_full2_new;
queue_rden2 <= '0';
-- Rd_en for S2MM BD FIFO
queue_rden2_new <= not queue_empty2_new
and m_axis_ftch2_tready;
m_axis_ftch2_tvalid <= '0';
m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle);
m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
FTCH_FIELDS_64_2 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new_bd & queue_dout2_new_64 & queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64_2;
FTCH_FIELDS_32_2 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32_2;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
end generate GEN_CH2_CTRL;
GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate
begin
ftch_tready_ch2 <= '0';
m_axis2_mm2s_tready <= '0';
queue_wren2 <= '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
--ftch_queue_empty <= queue_empty; CR 621600
ftch2_queue_empty <= '0';
ftch2_queue_full <= '0';
ftch2_pause <= '0';
queue_rden2 <= '0';
m_axis_ftch2_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
m_axis_ftch2_tdata_new <= (others => '0');
m_axis_ftch2_tvalid_new <= '0';
writing2_curdesc_out <= '0';
m_axis_ftch2_desc_available <= '0';
end generate GEN_NO_CH2_CTRL;
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
|
gpl-3.0
|
bonfireprocessor/bonfire-soc
|
byte_swapper.vhd
|
1
|
1345
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:28:56 12/10/2016
-- Design Name:
-- Module Name: byte_swapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity byte_swapper is
Port ( din : in STD_LOGIC_VECTOR (31 downto 0);
dout : out STD_LOGIC_VECTOR (31 downto 0));
end byte_swapper;
architecture Behavioral of byte_swapper is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "TRUE";
subtype tWord is std_logic_vector(31 downto 0);
function doSwapBytes(d : tWord) return tWord is
begin
return d(7 downto 0)&d(15 downto 8)&d(23 downto 16)&d(31 downto 24);
end;
begin
dout <= doSwapBytes(din);
end Behavioral;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/vhdl/feedforward_fptrunc_64ns_32_1.vhd
|
4
|
1982
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fptrunc_64ns_32_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component feedforward_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fptrunc_0_no_dsp_64_u : component feedforward_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
|
gpl-3.0
|
Rookfighter/aes-ss17
|
ex03/delay.vhd
|
1
|
927
|
-- delay.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
--
-- Component that delays an input signal by
-- a given amount of cycles.
library ieee;
use ieee.std_logic_1164.all;
entity delay is
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic; -- data in
dout: out std_logic); -- data out
end entity;
architecture behavioral of delay is
-- vector through which signal is chained
signal dvec : std_logic_vector (DELAYLEN-1 downto 0) := (others => '0');
begin
dout <= dvec(DELAYLEN-1);
process (rst, clk)
begin
if rst = RSTDEF then
dvec <= (others => '0');
elsif rising_edge(clk) then
dvec <= dvec(DELAYLEN-2 downto 0) & din;
end if;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_mux_4to1_sel2_32_1.vhd
|
7
|
1606
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of ANN_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/axi_utils_v2_0_1/hdl/axi_utils_v2_0_vh_rfs.vhd
|
24
|
292074
|
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/ip/feedforward_ap_fmul_2_max_dsp_32.vhd
|
4
|
12777
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
|
gpl-3.0
|
hoglet67/AtomVGAWing
|
src/DCM_C.vhd
|
1
|
2563
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM_C.vhd
-- /___/ /\ Timestamp : 03/01/2013 22:02:23
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/dmb/papilio/projects/VGATest/ipcore_dir/DCM_C.xaw -st DCM_C.vhd
--Design Name: DCM_C
--Device: xc3s500e-5vq100
--
-- Module DCM_C
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.72 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_C is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_C;
architecture BEHAVIORAL of DCM_C is
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 11,
CLKFX_MULTIPLY => 21,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 66.667,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg.vhd
|
7
|
84412
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1_2.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1_2.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1_2.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1_2.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1_2.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1_2.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cmd_status.vhd
|
7
|
19774
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/ip/ANN_ap_fpext_0_no_dsp_32.vhd
|
6
|
12143
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_fpext_0_no_dsp_32;
ARCHITECTURE ANN_ap_fpext_0_no_dsp_32_arch OF ANN_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fpext_0_no_dsp_32_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/ANN_sitofp_32ns_32_6.vhd
|
6
|
2642
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_sitofp_32ns_32_6 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_sitofp_32ns_32_6 is
--------------------- Component ---------------------
component ANN_ap_sitofp_4_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_sitofp_4_no_dsp_32_u : component ANN_ap_sitofp_4_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_dexp_16_full_dsp_64/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
24
|
157786
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
24
|
157786
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
24
|
157786
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm.vhd
|
4
|
17023
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
entity axi_dma_s2mm is
generic (
C_FAMILY : string := "virtex7"
);
port (
clk_in : in std_logic;
sg_clk : in std_logic;
resetn : in std_logic;
reset_sg : in std_logic;
s2mm_tvalid : in std_logic;
s2mm_tlast : in std_logic;
s2mm_tdest : in std_logic_vector (4 downto 0);
s2mm_tuser : in std_logic_vector (3 downto 0);
s2mm_tid : in std_logic_vector (4 downto 0);
s2mm_tready : in std_logic;
desc_available : in std_logic;
-- s2mm_eof : in std_logic;
s2mm_eof_det : in std_logic_vector (1 downto 0);
ch2_update_active : in std_logic;
tdest_out : out std_logic_vector (6 downto 0); -- to select desc
same_tdest : out std_logic; -- to select desc
-- to DM
s2mm_desc_info : out std_logic_vector (13 downto 0);
-- updt_cmpt : out std_logic;
s2mm_tvalid_out : out std_logic;
s2mm_tlast_out : out std_logic;
s2mm_tready_out : out std_logic;
s2mm_tdest_out : out std_logic_vector (4 downto 0)
);
end entity axi_dma_s2mm;
architecture implementation of axi_dma_s2mm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
signal first_data : std_logic;
signal first_stream : std_logic;
signal first_stream_del : std_logic;
signal last_received : std_logic;
signal first_received : std_logic;
signal first_received1 : std_logic;
signal open_window : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal fifo_wr : std_logic;
signal last_update_over_int : std_logic;
signal last_update_over_int1 : std_logic;
signal last_update_over : std_logic;
signal ch_updt_over_int : std_logic;
signal ch_updt_over_int_cdc_from : std_logic;
signal ch_updt_over_int_cdc_to : std_logic;
signal ch_updt_over_int_cdc_to1 : std_logic;
signal ch_updt_over_int_cdc_to2 : std_logic;
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
--ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ch_updt_over_int_cdc_to1 : SIGNAL IS "true";
signal fifo_rd : std_logic;
signal first_read : std_logic;
signal first_rd_en : std_logic;
signal fifo_rd_int : std_logic;
signal first_read_int : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal s2mm_desc_info_int : std_logic_vector (13 downto 0);
signal updt_cmpt : std_logic;
signal tdest_capture : std_logic_vector (4 downto 0);
signal noread : std_logic;
signal same_tdest_b2b : std_logic;
signal fifo_reset : std_logic;
begin
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
ch_updt_over_int_cdc_from <= '0';
else --if (sg_clk'event and sg_clk = '1') then
ch_updt_over_int_cdc_from <= ch2_update_active;
end if;
end if;
end process;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
ch_updt_over_int_cdc_to <= '0';
ch_updt_over_int_cdc_to1 <= '0';
ch_updt_over_int_cdc_to2 <= '0';
else --if (clk_in'event and clk_in = '1') then
ch_updt_over_int_cdc_to <= ch_updt_over_int_cdc_from;
ch_updt_over_int_cdc_to1 <= ch_updt_over_int_cdc_to;
ch_updt_over_int_cdc_to2 <= ch_updt_over_int_cdc_to1;
end if;
end if;
end process;
updt_cmpt <= (not ch_updt_over_int_cdc_to1) and ch_updt_over_int_cdc_to2;
-- process (sg_clk)
-- begin
-- if (resetn = '0') then
-- ch_updt_over_int <= '0';
-- elsif (sg_clk'event and sg_clk = '1') then
-- ch_updt_over_int <= ch2_update_active;
-- end if;
-- end process;
-- updt_cmpt <= (not ch2_update_active) and ch_updt_over_int;
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
last_update_over_int <= '0';
last_update_over_int1 <= '0';
noread <= '0';
-- else --if (sg_clk'event and sg_clk = '1') then
last_update_over_int1 <= last_update_over_int;
elsif (s2mm_eof_det(1) = '1' and noread = '0') then
last_update_over_int <= '1';
noread <= '1';
elsif (s2mm_eof_det(0) = '1') then
noread <= '0';
last_update_over_int <= '0';
elsif (fifo_empty = '0') then -- (updt_cmpt = '1') then
last_update_over_int <= '0';
else
last_update_over_int <= last_update_over_int;
end if;
end if;
-- end if;
end process;
last_update_over <= (not last_update_over_int) and last_update_over_int1;
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
fifo_rd_int <= '0';
first_read <= '0';
-- else --if (sg_clk'event and sg_clk = '1') then
elsif (last_update_over_int = '1' and fifo_rd_int = '0') then
fifo_rd_int <= '1';
else
fifo_rd_int <= '0';
end if;
end if;
end process;
process (sg_clk)
begin
if (sg_clk'event and sg_clk = '1') then
if (reset_sg = '0') then
first_read_int <= '0';
else --if (sg_clk'event and sg_clk = '1') then
first_read_int <= first_read;
end if;
end if;
end process;
first_rd_en <= first_read and (not first_read_int);
fifo_rd <= last_update_over_int; --(fifo_rd_int or first_rd_en);
-- process (clk_in)
-- begin
-- if (resetn = '0') then
-- first_data <= '0';
-- first_stream_del <= '0';
-- elsif (clk_in'event and clk_in = '1') then
-- if (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- no tlast
-- first_data <= '1'; -- just after the system comes out of reset
-- end if;
-- first_stream_del <= first_stream;
-- end if;
-- end process;
first_stream <= (s2mm_tvalid and (not first_data)); -- pulse when first stream comes after reset
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
first_received1 <= '0';
first_stream_del <= '0';
else --if (clk_in'event and clk_in = '1') then
first_received1 <= first_received; --'0';
first_stream_del <= first_stream;
end if;
end if;
end process;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
last_received <= '0';
first_received <= '0';
tdest_capture <= (others => '0');
first_data <= '0';
-- else --if (clk_in'event and clk_in = '1') then
elsif (s2mm_tvalid = '1' and first_data = '0' and s2mm_tready = '1') then -- first stream afetr reset
s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest;
tdest_capture <= s2mm_tdest; -- latching tdest on first beat
first_data <= '1'; -- just after the system comes out of reset
elsif (s2mm_tlast = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for last beat
last_received <= '1';
first_received <= '0';
s2mm_desc_info_int <= s2mm_desc_info_int;
elsif (last_received = '1' and s2mm_tvalid = '1' and s2mm_tready = '1') then -- catch for following first beat
last_received <= '0';
first_received <= '1';
tdest_capture <= s2mm_tdest; -- latching tdest on first beat
s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest;
else
s2mm_desc_info_int <= s2mm_desc_info_int;
last_received <= last_received;
if (updt_cmpt = '1') then
first_received <= '0';
else
first_received <= first_received; -- hold the first received until update comes for previous tlast
end if;
end if;
end if;
end process;
fifo_wr <= first_stream_del or (first_received and not (first_received1)); -- writing the tdest,tuser,tid into FIFO
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
tdest_out_int <= "0100000";
same_tdest_b2b <= '0';
-- else --if (clk_in'event and clk_in = '1') then
elsif (first_received = '1' or first_stream = '1') then
if (first_stream = '1') then -- when first stream is received, capture the tdest
tdest_out_int (6) <= not tdest_out_int (6); -- signifies a new stream has come
tdest_out_int (5 downto 0) <= '0' & s2mm_tdest;
same_tdest_b2b <= '0';
-- elsif (updt_cmpt = '1' or (first_received = '1' and first_received1 = '0')) then -- when subsequent streams are received, pass the latched value of tdest
-- elsif (first_received = '1' and first_received1 = '0') then -- when subsequent streams are received, pass the latched value of tdest
-- Following change made to allow b2b same channel pkt
elsif ((first_received = '1' and first_received1 = '0') and (tdest_out_int (4 downto 0) /= tdest_capture)) then -- when subsequent streams are received, pass the latched value of tdest
tdest_out_int (6) <= not tdest_out_int (6);
tdest_out_int (5 downto 0) <= '0' & tdest_capture; --s2mm_tdest;
elsif (first_received = '1' and first_received1 = '0') then
same_tdest_b2b <= not (same_tdest_b2b);
end if;
else
tdest_out_int <= tdest_out_int;
end if;
end if;
end process;
tdest_out <= tdest_out_int;
same_tdest <= same_tdest_b2b;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
open_window <= '0';
-- else --if (clk_in'event and clk_in = '1') then
elsif (desc_available = '1') then
open_window <= '1';
elsif (s2mm_tlast = '1') then
open_window <= '0';
else
open_window <= open_window;
end if;
end if;
end process;
process (clk_in)
begin
if (clk_in'event and clk_in = '1') then
if (resetn = '0') then
s2mm_tvalid_out <= '0';
s2mm_tready_out <= '0';
s2mm_tlast_out <= '0';
s2mm_tdest_out <= "00000";
-- else --if (clk_in'event and clk_in = '1') then
elsif (open_window = '1') then
s2mm_tvalid_out <= s2mm_tvalid;
s2mm_tready_out <= s2mm_tready;
s2mm_tlast_out <= s2mm_tlast;
s2mm_tdest_out <= s2mm_tdest;
else
s2mm_tready_out <= '0';
s2mm_tvalid_out <= '0';
s2mm_tlast_out <= '0';
s2mm_tdest_out <= "00000";
end if;
end if;
end process;
fifo_reset <= not (resetn);
-- s2mm_desc_info_int <= s2mm_tuser & s2mm_tid & s2mm_tdest;
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => 14,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => 31,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 5,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 5,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => s2mm_desc_info_int,
Wr_en => fifo_wr,
Wr_clk => clk_in,
Rd_en => fifo_rd,
Rd_clk => sg_clk,
Ainit => fifo_reset,
Dout => s2mm_desc_info,
Full => fifo_Full,
Empty => fifo_empty,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => open,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/lib_srl_fifo_v1_0/hdl/src/vhdl/dynshreg_f.vhd
|
15
|
11276
|
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
-- constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
-- constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
-- (C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
-- constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
constant W32 : boolean := (C_DEPTH > 16);
constant W16 : boolean := (not W32);
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
-- constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
-- and ( (W16 and C_DEPTH >= 16)
-- or (W32 and C_DEPTH >= 32)
-- )
-- )
-- or (not W32 and not W16);
constant USE_INFERRED : boolean := true;
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fpext_0_no_dsp_32.vhd
|
4
|
12231
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_fpext_0_no_dsp_32;
ARCHITECTURE feedforward_ap_fpext_0_no_dsp_32_arch OF feedforward_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fpext_0_no_dsp_32_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/mult_gen_v12_0/hdl/mult_gen_v12_0.vhd
|
24
|
10054
|
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd
|
32
|
49938
|
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/ip/feedforward_ap_dmul_4_max_dsp_64.vhd
|
2
|
12777
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_dmul_4_max_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_dmul_4_max_dsp_64;
ARCHITECTURE feedforward_ap_dmul_4_max_dsp_64_arch OF feedforward_ap_dmul_4_max_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_dmul_4_max_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_dmul_4_max_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_dmul_4_max_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd
|
8
|
35419
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SW_standalone/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/gpio_core.vhd
|
8
|
35419
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
24
|
24644
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
leHdrW5B1Ue8ne1t6lrNasa+bmf70P2jS0LwM3ICYgVyA4XnjXAE3KRyD/8gkAUf9C+hYFXAAz1O
1FG6BAuoEg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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/fTmuvB+FOzZni8rq+gdHLhYlyMRiO03BYjDCfBD/zLdQOQ1NXEyofWc7mAnwJPIm5EhSowItTxy
TQHaRJ21xp30JAinv8c=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
E6sLWvMufeIr/esO7MSSsfA/y4zYWP4M+i+2Kb7PjwpG78xkTchFcLuySnIvgoXNIX2IiPs4b7b0
6k7DXdJF+IvsJo80vdVtvxwqR0IHmn4j2FMQymQdlJn0ZtgS6ZxlKJeiv0CJuWZt7INuGXr5PRpU
KxIh1TXSKTGc98poTAnOPHc0Cmzw4mK+O2NxRH9j3MZpwh6G5Xm+34NV93bq6nD+A0GyLzHIBESy
++M5o5FSqgByOVRWTO4Su1otrfluotPuPO2TEjRd6FMIpUdR2ds5qii3JD4xOqSkA8egCIuy4NLR
B+Z2QdbY6DjTyMh7izZ/CqvryZp/qzsHq7yztA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CcCup7echTUWPmKCBn1gOyC1Cvqq4talnn4WK+t/foEcp3FaVfc2fhltpaZ6YHVIghZk7n/TSiwL
fPkWQUZQILJC0h0PaKdV9nZxAPSGoBifP0aeHQScywlmdjk/42WmPrDzs3TxEROSq5bxiNVtMSf7
zaL0QqT2uiy96OGZQH0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
24
|
24644
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
24
|
24644
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16112)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
makestuff/spi-talk
|
templates/fx2min/vhdl/top_level.vhdl
|
1
|
4552
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
NUM_DEVS : integer := 2
);
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2FifoSel_out : out std_logic; -- select FIFO: "0" for EP2OUT, "1" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Peripheral interface ----------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(NUM_DEVS-1 downto 0)
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
begin
-- CommFPGA module
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => open,
-- FX2LP interface
fx2FifoSel_out => fx2FifoSel_out,
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read_out,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => fx2Clk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in,
spiCS_out => spiCS_out
);
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd
|
18
|
30582
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set;
architecture implementation of axi_datamover_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_128_STRB;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd
|
18
|
30582
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set;
architecture implementation of axi_datamover_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_128_STRB;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd
|
4
|
50277
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(31 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1_8.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1_8.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1_8.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1_8.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd
|
4
|
70851
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset;
use axi_datamover_v5_1_9.axi_datamover_cmd_status;
use axi_datamover_v5_1_9.axi_datamover_pcc;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl;
use axi_datamover_v5_1_9.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_9.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_9.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1_9.axi_datamover_rd_sf;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32)); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_9.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1_9.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1_9.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1_9.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
gpl-3.0
|
hoglet67/AtomVGAWing
|
src/AtomVGAWing.vhd
|
1
|
15110
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity AtomVGAWing is
Port (
clock32 : in std_logic;
rst : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (1 downto 0);
hsync : out std_logic;
vsync : out std_logic;
clamp : out std_logic;
led : out std_logic_vector (4 downto 1);
test : out std_logic_vector (6 downto 1);
switch : in std_logic_vector (8 downto 1);
unused : in std_logic;
AL_P : in std_logic;
AL_N : in std_logic;
AH_P : in std_logic;
AH_N : in std_logic;
BL_P : in std_logic;
BL_N : in std_logic;
BH_P : in std_logic;
BH_N : in std_logic;
LUM_P : in std_logic;
LUM_N : in std_logic;
HS_N : in std_logic;
FS_N : in std_logic
);
end;
architecture Behavioral of AtomVGAWing is
constant atomClampStart : unsigned(10 downto 0) := to_unsigned(2048 - 59 * 4 - 110, 11);
constant atomClampEnd : unsigned(10 downto 0) := to_unsigned(2048 - 59 * 4 - 10, 11);
constant atomhInit : unsigned(10 downto 0) := to_unsigned(2048 - 370, 11);
constant atomvInit : unsigned(8 downto 0) := to_unsigned(512 - 39, 9);
constant atomhBorder : unsigned(10 downto 0) := to_unsigned(2048 - 16 + 3, 11);
constant atomvBorder : unsigned(8 downto 0) := to_unsigned(512 - 25, 11);
signal atomhCounter : unsigned(10 downto 0) := (others => '0');
signal atomvCounter : unsigned(8 downto 0) := (others => '0');
signal AL0: std_logic;
signal AL1: std_logic;
signal AL2: std_logic;
signal AL3: std_logic;
signal AL4: std_logic;
signal AL5: std_logic;
signal AH0: std_logic;
signal AH1: std_logic;
signal AH2: std_logic;
signal AH3: std_logic;
signal AH4: std_logic;
signal AH5: std_logic;
signal BL0: std_logic;
signal BL1: std_logic;
signal BL2: std_logic;
signal BL3: std_logic;
signal BL4: std_logic;
signal BL5: std_logic;
signal BH0: std_logic;
signal BH1: std_logic;
signal BH2: std_logic;
signal BH3: std_logic;
signal BH4: std_logic;
signal BH5: std_logic;
signal L0: std_logic;
signal L1: std_logic;
signal L2: std_logic;
signal L3: std_logic;
signal L4: std_logic;
signal L5: std_logic;
signal AL: std_logic;
signal AH: std_logic;
signal BL: std_logic;
signal BH: std_logic;
signal L: std_logic;
signal R: std_logic;
signal G1: std_logic;
signal G2: std_logic;
signal B: std_logic;
signal atomhSync0: std_logic := '0';
signal atomhSync1: std_logic := '0';
signal atomhSync2: std_logic := '0';
signal atomhSync3: std_logic := '0';
signal atomhSync4: std_logic := '0';
signal atomhSync5: std_logic := '0';
signal atomvSync0: std_logic := '0';
signal atomvSync1: std_logic := '0';
signal atomvSync2: std_logic := '0';
signal atomvSync3: std_logic := '0';
signal atomvSync4: std_logic := '0';
signal atomvSync5: std_logic := '0';
signal atomhSync: std_logic := '0';
signal atomvSync: std_logic := '0';
signal atomvSyncToggle: std_logic := '0';
signal atomhSyncToggle: std_logic := '0';
signal clock32out : std_logic;
signal pixelClock : std_logic;
signal atomClock : std_logic;
signal tmpClock : std_logic;
signal tmpVgaClock : std_logic;
signal lockeda1 : std_logic;
signal lockeda2 : std_logic;
signal lockedb1 : std_logic;
signal lockedb2 : std_logic;
signal ramWE : std_logic := '0';
signal ramAddrA : std_logic_vector (15 downto 0) := (others => '0');
signal ramAddrB : std_logic_vector (15 downto 0) := (others => '0');
signal ramDataIn : std_logic_vector (3 downto 0) := (others => '0');
signal ramDataOut : std_logic_vector (3 downto 0) := (others => '0');
signal border : std_logic_vector (3 downto 0) := (others => '0');
signal hCounter : unsigned(10 downto 0):= (others => '0');
signal vCounter : unsigned(9 downto 0) := (others => '0');
signal hCounter1 : unsigned(10 downto 0):= (others => '0');
signal vCounter1 : unsigned(9 downto 0) := (others => '0');
-- VGA Timing constants
constant hMaxCount : natural := 800;
constant hStartData : natural := 0;
constant hEndData : natural := 512;
constant hStartBlank : natural := 576;
constant hStartSync : natural := 592;
constant hEndSync : natural := 688;
constant hEndBlank : natural := 736;
constant vMaxCount : natural := 524;
constant vStartData : natural := 0;
constant vEndData : natural := 384;
constant vStartBlank : natural := 432;
constant vStartSync : natural := 444;
constant vEndSync : natural := 446;
constant vEndBlank : natural := 476;
begin
led(1) <= NOT lockeda1;
led(2) <= NOT lockeda2;
led(3) <= NOT lockedb1;
led(4) <= NOT lockedb2;
test(1) <= atomClock;
test(2) <= atomhSync;
test(3) <= unused;
test(4) <= rst;
test(5) <= atomhSyncToggle;
test(6) <= atomvSyncToggle;
BUFG_1 : BUFG port map (
O => clock32out,
I => clock32
);
Inst_DCM_A: entity work.DCM_A port map (
CLKIN_IN => clock32out,
CLKFX_OUT => tmpVgaClock,
LOCKED_OUT => lockeda1
);
Inst_DCM_A2: entity work.DCM_A2 port map (
CLKIN_IN => tmpVgaClock,
RST_IN => NOT lockeda1,
CLKFX_OUT => pixelClock,
LOCKED_OUT => lockeda2
);
Inst_DCM_B: entity work.DCM_B port map (
CLKIN_IN => clock32out,
CLKFX_OUT => tmpClock,
LOCKED_OUT => lockedb1
);
Inst_DCM_C: entity work.DCM_C port map (
CLKIN_IN => tmpClock,
RST_IN => NOT lockedb1,
CLKFX_OUT => atomClock,
LOCKED_OUT => lockedb2
);
Inst_VideoRam: entity work.VideoRam port map (
clka => atomClock,
wea => ramWE,
addra => ramAddrA,
dina => ramDataIn,
clkb => pixelClock,
addrb => ramAddrB,
doutb => ramDataOut
);
IBUFDS_1 : IBUFDS port map (
O => AL0, -- Buffer output
I => AL_P, -- Diff_p buffer input (connect directly to top-level port)
IB => AL_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_2 : IBUFDS port map (
O => AH0, -- Buffer output
I => AH_P, -- Diff_p buffer input (connect directly to top-level port)
IB => AH_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_3 : IBUFDS port map (
O => BL0, -- Buffer output
I => BL_P, -- Diff_p buffer input (connect directly to top-level port)
IB => BL_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_4 : IBUFDS port map (
O => BH0, -- Buffer output
I => BH_P, -- Diff_p buffer input (connect directly to top-level port)
IB => BH_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_5 : IBUFDS port map (
O => L0, -- Buffer output
I => LUM_P, -- Diff_p buffer input (connect directly to top-level port)
IB => LUM_N -- Diff_n buffer input (connect directly to top-level port)
);
process(atomClock)
begin
if rising_edge(atomClock) then
AL1 <= AL0;
AH1 <= AH0;
BL1 <= BL0;
BH1 <= BH0;
AL2 <= AL1;
AH2 <= AH1;
BL2 <= BL1;
BH2 <= BH1;
AL3 <= AL2;
AH3 <= AH2;
BL3 <= BL2;
BH3 <= BH2;
AL4 <= (AL1 AND AL2) OR (AL1 AND AL3) OR (AL2 AND AL3);
AH4 <= (AH1 AND AH2) OR (AH1 AND AH3) OR (AH2 AND AH3);
BL4 <= (BL1 AND BL2) OR (BL1 AND BL3) OR (BL2 AND BL3);
BH4 <= (BH1 AND BH2) OR (BH1 AND BH3) OR (BH2 AND BH3);
if (atomhcounter(2 downto 0) = unsigned(switch(7 downto 5))) then
AL5 <= AL4;
AH5 <= AH4;
BL5 <= BL4;
BH5 <= BH4;
end if;
L1 <= L0;
L2 <= L1;
L3 <= L2;
L4 <= (L1 AND L2) OR (L1 AND L3) OR (L2 AND L3);
if (atomhcounter(1 downto 0) = unsigned(switch(4 downto 3))) then
L5 <= L4;
end if;
AL <= AL5;
AH <= AH5;
BL <= BL5;
BH <= BH5;
L <= L5;
-- AL AH BL BH L R G1 G2 B
--YELLOW 1.5 1.0 0 0 1 0 X 1 1 1 0
--RED 2.0 1.5 0 1 0 0 X 1 0 1 0
--MAGENTA 2.0 2.0 0 1 0 1 X 1 0 1 1
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
R <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L) OR (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--YELLOW 1.5 1.0 0 0 1 0 X 1 1 1 0
--CYAN 1.0 1.5 1 0 0 0 X 0 1 1 1
--GREEN 1.0 1.0 1 0 1 0 1 0 1 1 0
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
G1 <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (AL AND NOT AH AND BL AND NOT BH AND L) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L) OR (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
G2 <= NOT (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--BLUE 1.5 2.0 0 0 0 1 X 0 0 1 1
--CYAN 1.0 1.5 1 0 0 0 X 0 1 1 1
--MAGENTA 2.0 2.0 0 1 0 1 X 1 0 1 1
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
B <= (NOT AL AND NOT AH AND NOT BL AND BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L);
ramDataIn <= R & G1 & G2 & B;
-- generate a 1 clock hSync signal from the falling edge of sync
atomhSync0 <= HS_N;
atomhSync1 <= NOT atomhSync0;
atomhSync2 <= atomhSync1;
atomhSync3 <= atomhSync2;
atomhSync4 <= atomhSync3;
atomhSync5 <= atomhSync4;
atomvSync0 <= FS_N;
atomvSync1 <= NOT atomvSync0;
atomvSync2 <= atomvSync1;
atomvSync3 <= atomvSync2;
atomvSync4 <= atomvSync3;
atomvSync5 <= atomvSync4;
if atomhSync5 = '1' AND atomhSync4 = '1' AND atomhSync3 = '0' AND atomhSync2 = '0' then
atomhSync <= '1';
else
atomhSync <= '0';
end if;
if atomvSync5 = '1' AND atomvSync4 = '1' AND atomvSync3 = '0' AND atomvSync2 = '0' then
atomvSync <= '1';
else
atomvSync <= '0';
end if;
-- generate
if (atomvSync = '1') then
atomvCounter <= atomvInit;
atomvSyncToggle <= NOT atomvSyncToggle;
elsif (atomhSync = '1') then
atomvCounter <= atomvCounter+1;
end if;
if (atomhSync = '1') then
atomhCounter <= atomhInit;
atomhSyncToggle <= NOT atomhSyncToggle;
else
atomhCounter <= atomhCounter+1;
end if;
ramAddrA <= std_logic_vector(atomvCounter(7 downto 0)) & std_logic_vector(atomhcounter(9 downto 2));
if (atomhcounter(1 downto 0) = unsigned(switch(2 downto 1)) AND atomhCounter < 1024 AND atomvCounter < 192) then
ramWE <= '1';
else
ramWE <= '0';
end if;
if (atomhcounter >= atomClampStart AND atomhCounter < atomClampEnd) then
clamp <= '1';
else
clamp <= '0';
end if;
if (atomhCounter = atomhBorder AND (switch(8) = '1' OR atomvCounter = atomvBorder)) then
border <= ramDataIn;
end if;
end if;
end process;
ramAddrB <= std_logic_vector(vCounter(8 downto 1)) & std_logic_vector(hcounter(8 downto 1));
process(pixelClock)
begin
if rising_edge(pixelClock) then
hsync <= '0';
vsync <= '0';
hCounter1 <= hCounter;
vCounter1 <= vCounter;
if (hCounter1 >= hStartData AND hCounter1 < hEndData AND vCounter1 >= vStartData AND vCounter1 < vEndData) then
red <= ramDataOut(3) & ramDataOut(3) & ramDataOut(3);
green <= ramDataOut(2) & (ramDataOut(2) AND ramDataOut(1)) & (ramDataOut(2) AND ramDataOut(1));
blue <= ramDataOut(0) & ramDataOut(0);
elsif (hCounter1 >= hStartBlank AND hCounter1 < hEndBlank) OR (vCounter1 >= vStartBlank AND vCounter1 < vEndBlank) then
red <= "000";
green <= "000";
blue <= "00";
else
red <= border(3) & border(3) & border(3);
green <= border(2) & (border(2) AND border(1)) & (border(2) AND border(1));
blue <= border(0) & border(0);
end if;
-- Count the lines and rows
if hCounter = (hMaxCount - 1) then
hCounter <= (others => '0');
if (vCounter = vMaxCount - 1) then
vCounter <= (others => '0');
else
vCounter <= vCounter+1;
end if;
else
hCounter <= hCounter+1;
end if;
-- Are we in the hSync pulse?
if hCounter >= hStartSync and hCounter < hEndSync then
hSync <= '1'; -- Positive hSync pulse
end if;
-- Are we in the vSync pulse?
if vCounter >= vStartSync and vCounter < vEndSync then
vSync <= '1'; -- Positive vSync pulse
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_datamover.vhd
|
7
|
51616
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1_2.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1_2.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1_2.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_datamover.vhd
|
7
|
51616
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1_2.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1_2.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1_2.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd
|
7
|
25964
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1_2.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1_2.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1_2.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd
|
18
|
16390
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_omit_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 0;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input --------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- MM2S Halt request input control-------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------------
-- Error discrete output ----------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-----------------------------------------------------------
-- Optional MM2S Command and Status clock and Reset -----------
-- Only used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
---------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
----------------------------------------------------------------
-- Address Posting contols -------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
----------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_omit_wrap;
architecture implementation of axi_datamover_mm2s_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
mm2s_dbg_data <= X"BEEF0000" ; -- 32 bit Constant indicating OMIT type
-- Just tie off output ports
mm2s_halt_cmplt <= mm2s_halt ;
mm2s_err <= '0' ;
mm2s_cmd_wready <= '0' ;
mm2s_sts_wvalid <= '0' ;
mm2s_sts_wdata <= (others => '0');
mm2s_sts_wstrb <= (others => '0');
mm2s_sts_wlast <= '0' ;
mm2s_arid <= (others => '0');
mm2s_araddr <= (others => '0');
mm2s_arlen <= (others => '0');
mm2s_arsize <= (others => '0');
mm2s_arburst <= (others => '0');
mm2s_arprot <= (others => '0');
mm2s_arcache <= (others => '0');
mm2s_aruser <= (others => '0');
mm2s_arvalid <= '0' ;
mm2s_rready <= '0' ;
mm2s_strm_wdata <= (others => '0');
mm2s_strm_wstrb <= (others => '0');
mm2s_strm_wlast <= '0' ;
mm2s_strm_wvalid <= '0' ;
mm2s_addr_req_posted <= '0' ;
mm2s_rd_xfer_cmplt <= '0' ;
-- Input ports are ignored
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_scc.vhd
|
18
|
47911
|
-------------------------------------------------------------------------------
-- axi_datamover_scc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the input command
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_scc;
architecture implementation of axi_datamover_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when 16 =>
temp_slice_width := 5;
when 8 =>
temp_slice_width := 4;
when 4 =>
temp_slice_width := 3;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 2;
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
when 64 =>
temp_btt_ls_unused := 3;
when 32 =>
temp_btt_ls_unused := 2;
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_input_eof_reg : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= sig_input_eof_reg; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty and
sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_input_eof_reg <= '0';
sig_cmd_burst_reg <= "00";
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
if (C_MICRO_DMA = 1) then
sig_input_eof_reg <= cmd2mstr_command(CMD_EOF_INDEX);
else
sig_input_eof_reg <= '1';
end if;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SCC_SM_COMB
--
-- Process Description:
-- Implements combinational portion of state machine
--
-------------------------------------------------------------
SCC_SM_COMB : process (sm_scc_state,
cmd2mstr_cmd_valid,
sig_addr_data_rdy_pending,
sig_cmd_reg_full,
sig_btt_is_zero_reg
)
begin
-- Set default State machine outputs
sm_pop_input_cmd_ns <= '0';
sm_set_push2axi_ns <= '0';
sm_scc_state_ns <= sm_scc_state;
sm_set_error_ns <= '0';
sm_scc_sm_ready_ns <= '1';
case sm_scc_state is
----------------------------------------------------
when INIT =>
-- if (sig_addr_data_rdy4cmd = '1') then
if (cmd2mstr_cmd_valid = '1') then -- wait for first cmd valid after reset
sm_scc_state_ns <= GET_NXT_CMD; -- jump to get command
else
sm_scc_sm_ready_ns <= '0';
sm_scc_state_ns <= INIT; -- Stay in Init
End if;
----------------------------------------------------
when POP_RECOVER =>
sm_scc_state_ns <= GET_NXT_CMD; -- jump to next state
----------------------------------------------------
when GET_NXT_CMD =>
if (sig_cmd_reg_full = '1') then
sm_scc_state_ns <= CHK_AND_CALC; -- jump to next state
else
sm_scc_state_ns <= GET_NXT_CMD; -- stay in this state
end if;
----------------------------------------------------
when CHK_AND_CALC =>
sm_set_push2axi_ns <= '1'; -- Push the command to ADDR and DATA
if (sig_btt_is_zero_reg = '1') then
sm_scc_state_ns <= ERROR_TRAP; -- jump to error trap
sm_set_error_ns <= '1'; -- Set internal error flag
else
sm_scc_state_ns <= PUSH_TO_AXI;
end if;
----------------------------------------------------
when PUSH_TO_AXI =>
if (sig_addr_data_rdy_pending = '1') then
sm_scc_state_ns <= PUSH_TO_AXI; -- stay in this state
-- until both Addr and Data have taken commands
else
sm_pop_input_cmd_ns <= '1';
sm_scc_state_ns <= POP_RECOVER; -- jump back to fetch new cmd input
end if;
----------------------------------------------------
when ERROR_TRAP =>
sm_scc_state_ns <= ERROR_TRAP; -- stay in this state
sm_set_error_ns <= '1';
----------------------------------------------------
when others =>
sm_scc_state_ns <= INIT; -- error so always jump to init state
end case;
end process SCC_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sm_scc_state <= INIT;
sm_pop_input_cmd <= '0' ;
sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
sm_scc_sm_ready <= '0' ;
else
sm_scc_state <= sm_scc_state_ns ;
sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= sm_set_error_ns ;
sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/ip/feedforward_ap_ddiv_29_no_dsp_64.vhd
|
6
|
12779
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_ddiv_29_no_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_ddiv_29_no_dsp_64;
ARCHITECTURE feedforward_ap_ddiv_29_no_dsp_64_arch OF feedforward_ap_ddiv_29_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_ddiv_29_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_ddiv_29_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_ddiv_29_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=29,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 29,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_ddiv_29_no_dsp_64_arch;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd
|
24
|
8323
|
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`protect end_protected
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/tmp.srcs/sources_1/ip/ANN_ap_ddiv_29_no_dsp_64/xbip_pipe_v3_0_1/hdl/xbip_pipe_v3_0.vhd
|
24
|
8323
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rd_sf.vhd
|
4
|
75596
|
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd
|
4
|
51651
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_8;
use axi_dma_v7_1_8.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_8.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_8.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_8.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_8.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_8.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_8.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_8.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.srcs/sources_1/bd/design_SW_standalone/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd
|
6
|
22296
|
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_8;
use proc_sys_reset_v5_0_8.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_8.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_8.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_8.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_8.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_dcmp_64ns_64ns_1_1.vhd
|
2
|
4486
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dcmp_64ns_64ns_1_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dcmp_64ns_64ns_1_1 is
--------------------- Component ---------------------
component feedforward_ap_dcmp_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dcmp_0_no_dsp_64_u : component feedforward_ap_dcmp_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
|
gpl-3.0
|
makestuff/spi-talk
|
vhdl/fifo-gen/fifo_wrapper_xilinx.vhdl
|
1
|
1923
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.xilinx_fifo
port map(
clk => clk_in,
-- Production end
din => inputData_in,
wr_en => inputValid_in,
full => inputFull,
-- Consumption end
dout => outputData_out,
empty => outputEmpty,
rd_en => outputReady_in
);
end architecture;
|
gpl-3.0
|
bonfireprocessor/bonfire-soc
|
spi/tb_spi_interface.vhd
|
1
|
4908
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:34 02/18/2017
-- Design Name:
-- Module Name: /home/thomas/riscv/lxp32soc/spi/tb_spi_interface.vhd
-- Project Name: bonfire
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: wb_spi_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_spi_interface IS
END tb_spi_interface;
ARCHITECTURE behavior OF tb_spi_interface IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wb_spi_interface
PORT(
clk_i : IN std_logic;
reset_i : IN std_logic;
slave_cs_o : OUT std_logic;
slave_clk_o : OUT std_logic;
slave_mosi_o : OUT std_logic;
slave_miso_i : IN std_logic;
irq : OUT std_logic;
wb_adr_in : IN std_logic_vector(7 downto 0);
wb_dat_in : IN std_logic_vector(7 downto 0);
wb_dat_out : OUT std_logic_vector(7 downto 0);
wb_we_in : IN std_logic;
wb_cyc_in : IN std_logic;
wb_stb_in : IN std_logic;
wb_ack_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal slave_miso_i : std_logic := '0';
signal wb_adr_in : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector(7 downto 0) := (others => '0');
signal wb_we_in : std_logic := '0';
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
--Outputs
signal slave_cs_o : std_logic;
signal slave_clk_o : std_logic;
signal slave_mosi_o : std_logic;
signal irq : std_logic;
signal wb_dat_out : std_logic_vector(7 downto 0);
signal wb_ack_out : std_logic;
-- Clock period definitions
constant clk_i_period : time := 10 ns;
BEGIN
slave_miso_i <= slave_mosi_o; -- loop back
-- Instantiate the Unit Under Test (UUT)
uut: wb_spi_interface PORT MAP (
clk_i => clk_i,
reset_i => reset_i,
slave_cs_o => slave_cs_o,
slave_clk_o => slave_clk_o,
slave_mosi_o => slave_mosi_o,
slave_miso_i => slave_miso_i,
irq => irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_we_in => wb_we_in,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_ack_out => wb_ack_out
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
stim_proc: process
variable d,t : std_logic_vector(7 downto 0);
procedure wb_write(address : in std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0)) is
begin
wb_adr_in <= address;
wait until rising_edge(clk_i);
wb_dat_in <= data;
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait until rising_edge(clk_i) and wb_ack_out = '1' ;
wb_stb_in <= '0';
wb_cyc_in <= '0';
end procedure;
procedure wb_read(address : in std_logic_vector(7 downto 0);
data: out std_logic_vector(7 downto 0) ) is
begin
wb_adr_in <= address;
wait until rising_edge(clk_i);
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_we_in <= '0';
wait until rising_edge(clk_i) and wb_ack_out = '1';
data:= wb_dat_out;
wb_stb_in <= '0';
wb_cyc_in <= '0';
--wait for clk_period;
end procedure;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_i_period*10;
wb_write(X"10",X"01"); -- Clock Divider
wb_write(X"00",X"FE"); -- Chip Select
-- send 10 bytes
for i in 0 to 255 loop
t:=std_logic_vector(to_unsigned(i,t'length));
wb_write(X"08",t);
wb_read(X"0C",d);
if d /= t then
report "Failure";
wait;
end if;
end loop;
report "Success";
wait;
end process;
END;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.ip_user_files/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_dexp_64ns_64ns_64_18_full_dsp.vhd
|
6
|
2769
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dexp_64ns_64ns_64_18_full_dsp is
generic (
ID : integer := 9;
NUM_STAGE : integer := 18;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dexp_64ns_64ns_64_18_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dexp_16_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dexp_16_full_dsp_64_u : component ANN_ap_dexp_16_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
makestuff/spi-talk
|
templates/eppa/vhdl/top_level.vhdl
|
1
|
5826
|
--
-- Copyright (C) 2009-2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
sysClk_in : in std_logic; -- 50MHz system clock
-- EPP interface -----------------------------------------------------------------------------
eppData_io : inout std_logic_vector(7 downto 0); -- bidirectional 8-bit data bus
eppAddrStb_in : in std_logic; -- active-low asynchronous address strobe
eppDataStb_in : in std_logic; -- active-low asynchronous data strobe
eppWrite_in : in std_logic; -- read='1'; write='0'
eppWait_out : out std_logic -- active-low asynchronous wait signal
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- SPI signals
signal spiCS : std_logic_vector(NUM_DEVS-1 downto 0);
signal spiClk : std_logic;
signal spiMOSI : std_logic;
signal spiMISO : std_logic;
--signal sendData : std_logic_vector(3 downto 0);
--signal recvData : std_logic_vector(3 downto 0);
-- Component from the Altera library to give application access to the config flash.
component altserial_flash_loader
generic (
enable_quad_spi_support : natural;
enable_shared_access : string;
enhanced_mode : natural;
intended_device_family : string;
lpm_type : string
);
port (
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
--data_in : in std_logic_vector(3 downto 0);
--data_oe : in std_logic_vector(3 downto 0);
--data_out : out std_logic_vector(3 downto 0);
asmi_access_request : out std_logic;
asmi_access_granted : in std_logic;
noe : in std_logic
);
end component;
begin
-- CommFPGA module
comm_fpga_epp : entity work.comm_fpga_epp
port map(
clk_in => sysClk_in,
reset_in => '0',
reset_out => open,
-- EPP interface
eppData_io => eppData_io,
eppAddrStb_in => eppAddrStb_in,
eppDataStb_in => eppDataStb_in,
eppWrite_in => eppWrite_in,
eppWait_out => eppWait_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => sysClk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk,
spiData_out => spiMOSI,
spiData_in => spiMISO,
spiCS_out => spiCS
);
-- Allow application access to config flash
spi_access : altserial_flash_loader
generic map (
enable_quad_spi_support => 0,
enable_shared_access => "ON",
enhanced_mode => 1,
intended_device_family => "Cyclone II",
lpm_type => "altserial_flash_loader"
)
port map (
dclkin => spiClk,
scein => spiCS(0),
sdoin => spiMOSI,
data0out => spiMISO,
--data_in => sendData,
--data_oe => "1101", -- drive D3, D2 & D0
--data_out => recvData,
asmi_access_request => open, -- ignore requests
asmi_access_granted => '0', -- application always has control
noe => '0' -- always drive
);
--sendData <= "111" & spiMOSI;
--spiMISO <= recvData(1);
end architecture;
|
gpl-3.0
|
pemsac/ANN_project
|
ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fptrunc_0_no_dsp_64/xbip_dsp48_addsub_v3_0_1/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
|
24
|
86743
|
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`protect end_protected
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/readout/select_data.vhd
|
1
|
4893
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Chandelog:
-- 19.07.2016 Reverted component to work asynchronously (Reid Pinkham)
-- 20.07.2016 Changed packet length from integer to std_logic_vector (Reid Pinkham)
-- 04.08.2016 Added XADC support (Reid Pinkham)
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity select_data is
port(
configuring : in std_logic;
data_acq : in std_logic;
xadc : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
we_xadc : in std_logic;
daq_data_in : in std_logic_vector(15 downto 0);
conf_data_in : in std_logic_vector(15 downto 0);
xadc_data_in : in std_logic_vector(15 downto 0);
data_packet_length : in std_logic_vector(11 downto 0);
xadc_packet_length : in std_logic_vector(11 downto 0);
conf_packet_length : in std_logic_vector(11 downto 0);
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
end_packet_xadc : in std_logic;
fifo_rst_daq : in std_logic;
fifo_rst_xadc : in std_logic;
rstFIFO_top : in std_logic;
data_out : out std_logic_vector(15 downto 0);
packet_length : out std_logic_vector(11 downto 0);
we : out std_logic;
end_packet : out std_logic;
fifo_rst : out std_logic
);
end select_data;
architecture Behavioral of select_data is
signal sel : std_logic_vector(2 downto 0);
signal fifo_rst_i : std_logic;
begin
data_selection: process(configuring, data_acq, xadc, we_conf, conf_data_in, conf_packet_length, end_packet_conf,
we_data, daq_data_in, data_packet_length, end_packet_daq, fifo_rst_daq,
we_xadc, xadc_data_in, xadc_packet_length, end_packet_xadc, fifo_rst_xadc)
begin
sel <= configuring & data_acq & xadc;
case sel is
when "100" => -- Configuration
we <= we_conf;
data_out <= conf_data_in;
packet_length <= conf_packet_length;
end_packet <= end_packet_conf;
fifo_rst_i <= '0';
when "010" => -- DAQ
we <= we_data;
data_out <= daq_data_in;
packet_length <= data_packet_length;
end_packet <= end_packet_daq;
fifo_rst_i <= fifo_rst_daq;
when "001" => -- XADC
we <= we_xadc;
data_out <= xadc_data_in;
packet_length <= xadc_packet_length;
end_packet <= end_packet_xadc;
fifo_rst_i <= fifo_rst_xadc;
when others =>
we <= '0';
data_out <= (others => '0');
packet_length <= x"000";
end_packet <= '0';
fifo_rst_i <= '0';
end case;
end process;
fifo_rst <= fifo_rst_i or rstFIFO_top; -- top reset always will work
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/imports/axi.vhd
|
2
|
747
|
--
-- Package File Template
--
-- Purpose: This package defines data types for AXI transfers
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package axi is
type axi_in_type is record
data_in : std_logic_vector (7 downto 0);
data_in_valid : std_logic; -- indicates data_in valid on clock
data_in_last : std_logic; -- indicates last data in frame
end record;
type axi_out_type is record
data_out_valid : std_logic; -- indicates data out is valid
data_out_last : std_logic; -- with data out valid indicates the last byte of a frame
data_out : std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
end record;
end axi;
|
gpl-3.0
|
rkrajnc/minimig-mist
|
rtl/tg68/TG68.vhd
|
3
|
7888
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- --
-- Copyright (c) 2007-2008 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.02 2008/01/23
-- bugfix Timing
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68 is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
addr : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
drive_data : out std_logic; --enable for data_out driver
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68;
ARCHITECTURE logic OF TG68 IS
COMPONENT TG68_fast
PORT (
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0);
test_IPL : in std_logic;
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
decodeOPC : buffer std_logic;
-- decodeOPC : out std_logic;
wr : out std_logic;
UDS, LDS : out std_logic;
enaRDreg : in std_logic;
enaWRreg : in std_logic
);
END COMPONENT;
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
-- SIGNAL n_clk : std_logic;
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
BEGIN
-- n_clk <= NOT clk;
TG68_fast_inst: TG68_fast
PORT MAP (
-- originally n_clk was used
-- clk => n_clk, -- : in std_logic;
clk => clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);
-- originally cpuIPL was used
-- IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);
IPL => IPL, -- : in std_logic_vector(2 downto 0);
test_IPL => '0', -- : in std_logic;
address => addr, -- : out std_logic_vector(31 downto 0);
data_write => data_out, -- : out std_logic_vector(15 downto 0);
state_out => state, -- : out std_logic_vector(1 downto 0);
decodeOPC => decode, -- : buffer std_logic;
wr => wr, -- : out std_logic;
UDS => uds_in, -- : out std_logic;
LDS => lds_in, -- : out std_logic;
enaRDreg => enaWRreg,
enaWRreg => enaRDreg
);
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN -- TODO new version is not edge sensitive (try to remove this)
IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= as_s AND as_e;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF reset='0' THEN
S_state <= "11";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN -- enaWRreg added
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
IF state/="01" OR decode='1' THEN
CASE S_state IS
WHEN "00" => as_s <= '0';
rw_s <= wr;
IF wr='1' THEN
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
S_state <= "01";
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
rw_s <= wr;
IF waitm='0' THEN
S_state <= "11";
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
cpuIPL <= "111";
drive_data <= '0';
ELSIF rising_edge(clk) THEN
-- originally it was falling_edge sensitive
-- ELSIF falling_edge(clk) THEN
IF clkena_in='1' AND enaRDreg='1' THEN -- enaRDreg added
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
drive_data <= '0';
CASE S_state IS
WHEN "00" => null;
WHEN "01" => drive_data <= NOT wr;
WHEN "10" => as_e <= '0';
uds_e <= uds_in;
lds_e <= lds_in;
cpuIPL <= IPL;
drive_data <= NOT wr;
IF state="01" THEN
clkena_e <= '1';
waitm <= '0';
ELSE
clkena_e <= NOT dtack;
waitm <= dtack;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END PROCESS;
END;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/pulse_pdxx_pwxx.vhd
|
3
|
3086
|
----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! generates a one clk-pulse pd clkss after trigger rising edge
entity pulse_pdxx_pwxx is
generic (
pd : integer := 0; -- pulse delay in clks
pw : integer := 1 -- pulse width in clks
);
port (
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end pulse_pdxx_pwxx;
architecture Behavioral of pulse_pdxx_pwxx is
------
constant shreg_pd_zeros: std_logic_vector(pd downto 0) := (others => '0');
constant shreg_pw_zeros: std_logic_vector(pw downto 0) := (others => '0');
--
signal shreg_pd: std_logic_vector(pd downto 0) := (others => '0');
signal shreg_pw: std_logic_vector(pw downto 0) := (others => '0');
--
signal on_s : std_logic := '0';
signal pulseout_s_pw_gt1_case_s : std_logic := '0';
signal trigger_1clk_delayed, t0, off_s : std_logic := '0';
------
begin
process (clk)
begin
if rising_edge(clk) then
trigger_1clk_delayed <= trigger;
end if;
end process;
t0 <= trigger and (not trigger_1clk_delayed); -- the first clk of a trigger, one clk pulse
--
----------------------------------------
-- shift register for pulse delay
----------------------------------------
pd0_case: if (pd = 0) generate
on_s <= t0;
end generate pd0_case;
--
--
pd1_case: if (pd = 1) generate
process (clk)
begin
if rising_edge(clk) then
on_s <= t0;
end if;
end process;
end generate pd1_case;
--
--
pd_gt1_case: if (pd > 1) generate
--
process (clk)
begin
if rising_edge(clk) then
if t0 = '1' then
shreg_pd <= shreg_pd_zeros(pd-1 downto 0) & '1';
else
shreg_pd <= shreg_pd(pd-1 downto 0) & '0';
end if;
end if;
end process;
--
on_s <= shreg_pd(pd-1);
end generate pd_gt1_case;
----------------------------------------
-- shift register for pulse width
----------------------------------------
pw1_case: if (pw = 1) generate
pulseout <= on_s;
end generate pw1_case;
pw_gt1_case: if (pw > 1) generate
--
process (clk)
begin
if rising_edge(clk) then
if on_s = '1' then
shreg_pw <= shreg_pw_zeros(pw-1 downto 0) & '1';
else
shreg_pw <= shreg_pw(pw-1 downto 0) & '0';
end if;
end if;
end process;
--
off_s <= shreg_pw(pw-1);
--
process (clk)
begin
if rising_edge(clk) then
if off_s = '1' then
pulseout_s_pw_gt1_case_s <= '0';
elsif on_s = '1' then
pulseout_s_pw_gt1_case_s <= '1';
end if;
end if;
end process;
--
pulseout <= (pulseout_s_pw_gt1_case_s or on_s) and (not off_s);
end generate pw_gt1_case;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN2_HDLC.vhd
|
3
|
6959
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2015
--! Module Name: EPROC_IN2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC decoder for EPROC_IN2 module
entity EPROC_IN2_HDLC is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_HDLC;
architecture Behavioral of EPROC_IN2_HDLC is
----------------------------------
----------------------------------
signal edataIN_r : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_in_sr,out_sr : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_cnt,error_bit_cnt : std_logic_vector (2 downto 0) := (others=>'0');
signal error_state,error_state_r,error_out : std_logic := '1';
signal edataIN_latch_trig,bit_in,isflag_r,isflag_rr,bit_in_r,bit_in_r_we,remove_zero_r : std_logic := '0';
signal isflag,iserror,remove_zero,out_sr_rdy,dataOUTrdy_s,error_out_rdy,remove_zero_state : std_logic;
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input serializer
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
edataIN_latch_trig <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
edataIN_latch_trig <= not edataIN_latch_trig;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
edataIN_r <= (others=>'1');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if edataIN_latch_trig = '1' then
edataIN_r <= edataIN;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if edataIN_latch_trig = '0' then
bit_in <= edataIN_r(0);
else
bit_in <= edataIN_r(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock1
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bit_in_sr <= (others=>'1');
elsif bitCLKx2'event and bitCLKx2 = '1' then
bit_in_sr <= bit_in & bit_in_sr(7 downto 1);
end if;
end process;
--
isflag <= '1' when (bit_in_sr = "01111110") else '0';
iserror <= '1' when (bit_in_sr(7 downto 1) = "1111111") else '0';
remove_zero <= '1' when (bit_in_sr(7 downto 2) = "011111" and isflag = '0' and error_state = '0') else '0';
--
-------------------------------------------------------------------------------------------
--clock2
-- latching the error state, forwarding clean bit sequence
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
error_state <= '1';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if iserror = '1' then
error_state <= '1';
elsif isflag = '1' then
error_state <= '0';
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
isflag_r <= '0';
isflag_rr <= '0';
--bit_in_r_we <= '0';
remove_zero_r <= '0';
error_state_r <= '1';
elsif bitCLKx2'event and bitCLKx2 = '1' then
isflag_r <= isflag;
isflag_rr <= isflag_r;
--bit_in_r_we <= not(error_state or remove_zero);
remove_zero_r <= remove_zero;
error_state_r <= error_state;
end if;
end process;
--
bit_in_r_we <= not(error_state or remove_zero);
--
bit_in_r <= bit_in_sr(7);
--
-------------------------------------------------------------------------------------------
--clock3
-- output shift register
-------------------------------------------------------------------------------------------
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if remove_zero = '0' then
out_sr <= bit_in_r & out_sr(7 downto 1);
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
bit_cnt <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if error_state = '1' then
bit_cnt <= (others=>'0');
else
if bit_in_r_we = '1' or isflag_r = '1' then
bit_cnt <= bit_cnt + 1;
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bit_cnt = "111" and error_state = '0' and remove_zero = '0' then
out_sr_rdy <= '1';
else
out_sr_rdy <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock3+
-- output latch
-------------------------------------------------------------------------------------------
dataOUTrdy_s <= isflag_r or out_sr_rdy or error_out_rdy;
out_rdy_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,dataOUTrdy_s,dataOUTrdy);
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bit_in_sr /= x"ff" then
error_out <= '0';
elsif error_state = '1' then
error_out <= '1';
end if;
end if;
end process;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
error_bit_cnt <= (others=>'0');
elsif bitCLKx2'event and bitCLKx2 = '1' then
if error_out = '0' then
error_bit_cnt <= (others=>'0');
else
error_bit_cnt <= error_bit_cnt + 1;
end if;
end if;
end process;
--
error_out_rdy <= '1' when (error_bit_cnt = "001" and error_out = '1') else '0';
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if error_state_r = '1' and isflag = '1' then
dataOUT(9 downto 8) <= "10"; -- sop
elsif error_state_r = '0' and isflag = '1' then
dataOUT(9 downto 8) <= "01"; -- eop
else
dataOUT(9 downto 8) <= error_out & error_out; -- 00-data, 11-error
end if;
end if;
end process;
--
dataOUT(7 downto 0) <= out_sr;
--
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN4_direct.vhd
|
4
|
3202
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_IN4_direct.vhd
|
4
|
3202
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN4_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN4_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN4_direct;
architecture Behavioral of EPROC_IN4_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic := '0';
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 1
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= '0';
elsif bitCLK'event and bitCLK = '1' then
inpcount <= not inpcount;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when '0' => word8b(3 downto 0) <= edataIN;
when '1' => word8b(7 downto 4) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word8bRdy <= inpcount;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
gpl-3.0
|
rkrajnc/minimig-mist
|
rtl/tg68/TG68_fast.vhd
|
3
|
104993
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic;
enaRDreg : in std_logic:='1';
enaWRreg : in std_logic:='1'
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal clkenareg : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t;
signal regfile_high : regfile_t;
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF clkenareg='1' THEN
-- IF falling_edge(clk) THEN
-- IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt, enaWRreg, enaRDreg)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaWRreg;
clkenareg <= clkena_in AND NOT longread AND NOT get_extendedOPC AND enaRDreg;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND enaWRreg='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur für Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC für Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist für pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --für displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig für USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' AND enaWRreg='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' AND enaWRreg='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' AND enaWRreg='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/SCDataMANAGER.vhd
|
4
|
5210
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: SCDataMANAGER - Sub-Chunk Data Manager
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
--! sub-chunk data manager,
--! inserts sub-chunk trailer at the end of the chunk/block
entity SCDataMANAGER is
Port (
CLK : in std_logic;
rst : in std_logic;
xoff : in std_logic;
maxCLEN : in std_logic_vector (2 downto 0); -- (15 downto 0);
rstCLENcount : in std_logic;
truncateCdata : out std_logic; -- maximum allowed chunk length is reached of xoff received - truncation mark
-------------
trailerMOD : in std_logic_vector (1 downto 0); -- keeps its value till the next DIN_RDY_s
trailerTYPE : in std_logic_vector (2 downto 0); -- keeps its value till the next DIN_RDY_s
trailerRSRVbit : in std_logic; --
-------------
trailerSENDtrig : in std_logic;
dataCNTena : in std_logic; -- counts only data (or 'flush' padding), no header, no trailer
-------------
trailerOUT : out std_logic_vector (15 downto 0);
trailerOUTrdy : out std_logic
);
end SCDataMANAGER;
architecture Behavioral of SCDataMANAGER is
----
signal truncate_state, sc_counter_rst, first_byte_count_rst : std_logic := '0';
signal truncate_data_flag, rst_fall, rstCLENcount_s, trailerSENDtrig_next_clk : std_logic;
signal sc_data_count : std_logic_vector(9 downto 0) := (others => '0');
signal schunk_length : std_logic_vector(9 downto 0);
signal chunk_data_count : std_logic_vector(11 downto 0);
signal trailer_s : std_logic_vector(15 downto 0);
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
----
begin
rst_fall_pulse: entity work.pulse_fall_pw01 PORT MAP(CLK, rst, rst_fall);
-----------------------------------------------------------------
-- chunk data counter,
-- counts to MAX_COUNT then rises MAX_REACHED
-- used for chunk data truncation
-----------------------------------------------------------------
rstCLENcount_s <= rstCLENcount or rst_fall;
--
CD_COUNTER_inst: entity work.CD_COUNTER
PORT MAP(
CLK => CLK,
RESET => rstCLENcount_s,
xoff => xoff,
COUNT_ENA => dataCNTena,
MAX_COUNT => maxCLEN,
count_out => chunk_data_count, -- the whole chunk data counter, used for data truncation
truncate_data => truncate_data_flag
);
--
truncate_state_latch: process(rstCLENcount, CLK)
begin
if rstCLENcount = '1' then
truncate_state <= '0';
elsif CLK'event and CLK = '1' then
if truncate_data_flag = '1' and trailerSENDtrig = '1' then -- first trigger goes through
truncate_state <= '1';
end if;
end if;
end process;
--
truncateCdata <= truncate_data_flag;
--
-----------------------------------------------------------------
-- trailer: in case of zero data (last word of a block is left)
-----------------------------------------------------------------
zero_data_case: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>2) PORT MAP(CLK, trailerSENDtrig, trailerSENDtrig_next_clk);
--process(CLK)
--begin
-- if CLK'event and CLK = '1' then
-- trailerSENDtrig_next_clk <= trailerSENDtrig;
-- end if;
--end process;
--
-----------------------------------------------------------------
-- Sub-Chunk Trailer bits
-----------------------------------------------------------------
schunk_length <= sc_data_count; -- chunk_data_count(9 downto 0); --
trailer_s <= trailerTYPE & trailerMOD & trailerRSRVbit & schunk_length;
--
process(trailerSENDtrig_next_clk, trailer_s)
begin
if trailerSENDtrig_next_clk = '1' then
trailerOUT <= zero_data_trailer; -- in case the only a space for a single 16-bit word is left, null-chunk is sent (ignored by software)
else
trailerOUT <= trailer_s;
end if;
end process;
--
trailerOUTrdy <= trailerSENDtrig and (not truncate_state); -- same clock!
-----------------------------------------------------------------
-- sub-chunk data counter
-----------------------------------------------------------------
sc_counter_rst <= rst_fall or rstCLENcount;
--
sub_chunk_counter: process(CLK)
begin
if CLK'event and CLK = '1' then
if sc_counter_rst = '1' or (dataCNTena = '0' and trailerSENDtrig = '1') then
sc_data_count <= (others => '0');
else
if dataCNTena = '1' then --and first_byte_count_rst = '0' then
if trailerSENDtrig = '1' then
sc_data_count <= "0000000001";
else
sc_data_count <= sc_data_count + 1;
end if;
end if;
end if;
end if;
end process;
--
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/MMFE8_1VMM/sources_1/readout/FIFO2UDP.vhd
|
1
|
9705
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity FIFO2UDP is
Port (
clk_200 : in std_logic;
clk_125 : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
re_out : out std_logic;
control : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in integer;
reset_DAQ_FIFO : in std_logic;
sending_o : out std_logic
);
end FIFO2UDP;
architecture Behavioral of FIFO2UDP is
signal count : integer := 0;
signal i : integer := 0;
signal count_length : integer := 0;
signal packet_length_int : integer := 0;
signal daq_fifo_re : std_logic := '0';
signal fifo_empty : std_logic := '0';
signal prog_fifo_empty : std_logic := '0';
signal daq_out : std_logic_vector(255 downto 0);
signal data_out : std_logic_vector(7 downto 0) := x"00";
signal data_out_valid : std_logic := '0';
signal packet_length : integer := 0;
signal daq_data_in_int : std_logic_vector(63 downto 0);
signal data_out_last : std_logic := '0';
signal sending : std_logic := '0';
signal end_packet_synced : std_logic := '0';
signal udp_tx_start_int : std_logic := '0';
signal wr_en_int : std_logic := '0';
signal is_trailer : integer := 0;
signal temp_buffer : std_logic_vector(63 downto 0) := (others=> '0');
signal daq_data_out : std_logic_vector(7 downto 0) := x"00";
type tx_state is (HEADER, EN_RE, WAIT_ONE, DATA, TRAILER, LAST, IDLE);
signal state : tx_state;
component readout_fifo is
port(
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
full : out std_logic;
empty : out std_logic;
prog_empty : out std_logic
);
end component;
begin
daq_FIFO_instance: readout_fifo
port map(
rst => reset_DAQ_FIFO,
wr_clk => clk_200,
rd_clk => clk_125,
din => daq_data_in,
wr_en => wr_en,
rd_en => daq_fifo_re,
dout => daq_data_out,
full => open,
empty => fifo_empty,
prog_empty => prog_fifo_empty
);
synced_end_packet: process (clk_125)
begin
if clk_125'event and clk_125 = '1' then
end_packet_synced <= end_packet;
end if;
end process;
process (clk_125, count, state, udp_tx_data_out_ready, fifo_empty, prog_fifo_empty, data_out_valid, end_packet_synced)
begin
if clk_125'event and clk_125 = '1' then
if global_reset = '1' then
sending <= '0';
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
elsif end_packet_synced = '1' and sending = '0' then
packet_length <= (packet_length_in * 8) + 4;
count_length <= packet_length_in * 8;
state <= HEADER;
sending <= '1';
else
end if;
if sending = '1' then
if count = 0 then
count <= count + 1;
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
elsif count = 1 then
udp_tx_start_int <= '1';
udp_txi.hdr.dst_ip_addr <= x"c0a80010"; -- set a generic ip adrress (192.168.0.255)
udp_txi.hdr.src_port <= x"19CB"; -- set src and dst ports
udp_txi.hdr.dst_port <= x"1778"; -- x"6af0";
udp_txi.hdr.data_length <= std_logic_vector(to_unsigned(packet_length, udp_txi.hdr.data_length'length));
daq_fifo_re <= '0';
udp_txi.hdr.checksum <= x"0000";
count <= count + 1;
elsif count = 2 then
if udp_tx_data_out_ready = '1' then
udp_tx_start_int <= '0';
daq_fifo_re <= '1';
count <= count + 1;
else
end if;
elsif count = 3 then
if udp_tx_data_out_ready = '1' then
count_length <= count_length - 1;
udp_tx_start_int <= '0';
count <= count + 1;
data_out <= daq_data_out;
end if;
elsif count = 4 then
if udp_tx_data_out_ready = '1' then
if count_length = 1 then
daq_fifo_re <= '0';
elsif count_length = 0 then
count <= count + 1;
daq_fifo_re <= '0';
end if;
count_length <= count_length - 1;
udp_tx_start_int <= '0';
data_out_valid <= '1';
control <= '0';
data_out_last <= '0';
data_out <= daq_data_out;
else
daq_fifo_re <= '0';
end if;
elsif count >= 5 and count <= 7 then
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= count + 1;
end if;
elsif count = 8 then
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '1';
data_out <= x"ff";
count <= count + 1;
end if;
elsif count = 9 then
count <= count + 1;
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
else
count <= 0;
count_length <= 0;
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
sending <= '0';
end if;
end if;
end if;
end process;
udp_tx_start <= udp_tx_start_int;
udp_txi.data.data_out_last <= data_out_last;
udp_txi.data.data_out_valid <= data_out_valid ;
udp_txi.data.data_out <= data_out;
packet_length_int <= packet_length_in;
daq_data_in_int <= daq_data_in;
wr_en_int <= wr_en;
sending_o <= sending;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/configuration/fpga_config_block.vhd
|
1
|
24485
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 30.01.2017
-- Design Name: FPGA Configuration Block
-- Module Name: fpga_config_block - RTL
-- Project Name: MMFE8 - NTUA
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description: Module that samples the data coming from the UDP/Ethernet
-- to produce various control signals for the FPGA user logic. It controls
-- the configuration of the XADC/AXI4SPI_FLASH modules and more general
-- FPGA commands.
-- Dependencies: MMFE8 NTUA Project
--
-- Changelog:
-- 07.03.2017 Changed FPGA_conf_proc to accomodate CKBC/CKTP configuration
-- and future register address configuration scheme. (Christos Bakalis)
-- 14.03.2017 Register address configuration scheme deployed. (Christos Bakalis)
-- 17.03.2017 Added synchronizers for daq and trigger signals. (Christos Bakalis)
-- 31.03.2017 Added 2 ckbc mode register (Paris)
-- 05.08.2017 Added fpga_config_router and fpga_config_buffer to optimize the
-- FPGA configuration scheme. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity fpga_config_block is
port(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
rst : in std_logic;
rst_fifo_init : in std_logic;
cnt_bytes : in unsigned(7 downto 0);
user_din_udp : in std_logic_vector(7 downto 0);
------------------------------------
-------- UDP Interface -------------
udp_rx : in udp_rx_type;
------------------------------------
---------- XADC Interface ----------
xadc_conf : in std_logic;
xadcPacket_rdy : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
------------------------------------
---------- AXI4SPI Interface -------
flash_conf : in std_logic;
flashPacket_rdy : out std_logic;
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
------------------------------------
-------- FPGA Config Interface -----
fpga_conf : in std_logic;
fpga_rst : out std_logic;
fpgaPacket_rdy : out std_logic;
latency : out std_logic_vector(15 downto 0);
tr_delay_limit : out std_logic_vector(15 downto 0);
daq_on : out std_logic;
ext_trigger : out std_logic;
ckbcMode : out std_logic
);
end fpga_config_block;
architecture RTL of fpga_config_block is
component fpga_reg_buffer
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
wr_rst_busy : out std_logic;
rd_rst_busy : out std_logic
);
end component;
component fpga_config_router
port(
------------------------------------
------ General Interface -----------
clk_125 : in std_logic;
reg_addr : in std_logic_vector(7 downto 0);
reg_rst : in std_logic;
reg_value_bit : in std_logic;
sreg_ena : in std_logic;
------------------------------------
---------- XADC Interface ----------
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
------------------------------------
---------- AXI4SPI Interface -------
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
------------------------------------
-------- FPGA Config Interface -----
latency : out std_logic_vector(15 downto 0);
tr_delay_limit : out std_logic_vector(15 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
daq_state : out std_logic_vector(7 downto 0);
trig_state : out std_logic_vector(7 downto 0);
ro_state : out std_logic_vector(7 downto 0);
fpga_rst_state : out std_logic_vector(7 downto 0)
);
end component;
-- register the address/value and valid signal from UDP packet
signal reg_address : std_logic_vector(7 downto 0) := (others => '0');
signal reg_value : std_logic_vector(31 downto 0) := (others => '0');
signal din_valid : std_logic := '0';
signal din_last : std_logic := '0';
-- FPGA reset signals
signal reg_rst : std_logic := '0';
signal rst_cnt : integer range 0 to 63 := 0;
-- other
signal fpgaPacket_rdy_i : std_logic := '0';
-- FSM, demux signals
signal wait_cnt : unsigned(4 downto 0) := (others => '0');
signal reg_index : integer range 0 to 31 := 31;
signal reg_value_bit : std_logic := '0';
signal sreg_en : std_logic := '0';
signal read_buffers : std_logic := '0';
type stateType is (ST_IDLE, ST_CHK, ST_WAIT, ST_WRH_SREG, ST_WRL_SREG, ST_DONE);
signal state : stateType := ST_IDLE;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of state : signal is "ONE_HOT";
-- signals for the FIFOs
signal wr_en : std_logic := '0';
signal rd_en : std_logic := '0';
signal rst_fifo : std_logic := '0';
signal din_regAddr : std_logic_vector(31 downto 0) := (others => '0');
signal dout_regAaddr : std_logic_vector(31 downto 0) := (others => '0');
signal dout_regValue : std_logic_vector(31 downto 0) := (others => '0');
signal addr_buffer_full : std_logic := '0';
signal addr_buffer_empty: std_logic := '0';
signal val_buffer_full : std_logic := '0';
signal val_buffer_empty : std_logic := '0';
signal addr_rdRst_busy : std_logic := '0';
signal addr_wrRst_busy : std_logic := '0';
signal val_rdRst_busy : std_logic := '0';
signal val_wrRst_busy : std_logic := '0';
-- internal registers and synchronizer signals
signal daq_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal trig_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal ro_state_reg : std_logic_vector(7 downto 0) := (others => '0');
signal fpga_rst_reg : std_logic_vector(7 downto 0) := (others => '0');
signal daq_on_i : std_logic := '0';
signal daq_on_sync : std_logic := '0';
signal ext_trg_i : std_logic := '0';
signal ext_trg_sync : std_logic := '0';
signal fpga_rst_i : std_logic := '0';
signal ckbcMode_i : std_logic := '0';
signal ckbcMode_sync : std_logic := '0';
-- async_regs
attribute ASYNC_REG : string;
attribute ASYNC_REG of daq_on : signal is "true";
attribute ASYNC_REG of daq_on_sync : signal is "true";
attribute ASYNC_REG of ext_trigger : signal is "true";
attribute ASYNC_REG of ext_trg_sync : signal is "true";
attribute ASYNC_REG of ckbcMode : signal is "true";
attribute ASYNC_REG of ckbcMode_sync : signal is "true";
begin
-- register the valid signal
reg_valid_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
din_valid <= udp_rx.data.data_in_valid;
din_last <= udp_rx.data.data_in_last;
end if;
end process;
-- sub-process that samples register addresses and values for FPGA/xADC/Flash-IP configuration
FPGA_conf_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(rst = '1')then
reg_address <= (others => '0');
reg_value <= (others => '0');
else
if((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '1')then
case cnt_bytes is
----------------------------
--- register addresses -----
when "00001100" => -- 12
reg_address <= user_din_udp;
when "00010100" => -- 20
reg_address <= user_din_udp;
when "00011100" => -- 28
reg_address <= user_din_udp;
when "00100100" => -- 36
reg_address <= user_din_udp;
when "00101100" => -- 44
reg_address <= user_din_udp;
when "00110100" => -- 52
reg_address <= user_din_udp;
when "00111100" => -- 60
reg_address <= user_din_udp;
----------------------------
--- register values --------
when "00001101" => -- 13
reg_value(31 downto 24) <= user_din_udp;
when "00001110" => -- 14
reg_value(23 downto 16) <= user_din_udp;
when "00001111" => -- 15
reg_value(15 downto 8) <= user_din_udp;
when "00010000" => -- 16
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00010101" => -- 21
reg_value(31 downto 24) <= user_din_udp;
when "00010110" => -- 22
reg_value(23 downto 16) <= user_din_udp;
when "00010111" => -- 23
reg_value(15 downto 8) <= user_din_udp;
when "00011000" => -- 24
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00011101" => -- 29
reg_value(31 downto 24) <= user_din_udp;
when "00011110" => -- 30
reg_value(23 downto 16) <= user_din_udp;
when "00011111" => -- 31
reg_value(15 downto 8) <= user_din_udp;
when "00100000" => -- 32
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00100101" => -- 37
reg_value(31 downto 24) <= user_din_udp;
when "00100110" => -- 38
reg_value(23 downto 16) <= user_din_udp;
when "00100111" => -- 39
reg_value(15 downto 8) <= user_din_udp;
when "00101000" => -- 40
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00101101" => -- 45
reg_value(31 downto 24) <= user_din_udp;
when "00101110" => -- 46
reg_value(23 downto 16) <= user_din_udp;
when "00101111" => -- 47
reg_value(15 downto 8) <= user_din_udp;
when "00110000" => -- 48
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00110101" => -- 53
reg_value(31 downto 24) <= user_din_udp;
when "00110110" => -- 54
reg_value(23 downto 16) <= user_din_udp;
when "00110111" => -- 55
reg_value(15 downto 8) <= user_din_udp;
when "00111000" => -- 56
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "00111101" => -- 61
reg_value(31 downto 24) <= user_din_udp;
when "00111110" => -- 62
reg_value(23 downto 16) <= user_din_udp;
when "00111111" => -- 63
reg_value(15 downto 8) <= user_din_udp;
when "01000000" => -- 64
reg_value(7 downto 0) <= user_din_udp;
----------------------------
when "01000100" => -- 68
read_buffers <= '1';
when others => null;
end case;
elsif((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '0')then
read_buffers <= '1';
else
read_buffers <= '0';
end if;
end if;
end if;
end process;
-- process that controls the write-enable signal
wr_ena_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '1' and din_last = '0')then
case cnt_bytes is
-- 18 26 34 42 50 58 66
when "00010010" | "00011010" | "00100010" | "00101010" | "00110010" | "00111010" | "01000010" =>
wr_en <= '1';
-- 19 27 35 43 51 59 67
when "00010011" | "00011011" | "00100011" | "00101011" | "00110011" | "00111011" | "01000011" =>
wr_en <= '0';
when others =>
wr_en <= '0';
end case;
elsif((fpga_conf = '1' or flash_conf = '1' or xadc_conf = '1') and din_valid = '1' and din_last = '1')then
wr_en <= '1';
else
wr_en <= '0';
end if;
end if;
end process;
-- FSM that reads the two FIFOs and fills the shift registers
FSM_FPGA_conf: process(clk_125)
begin
if(rising_edge(clk_125))then
--reg_value_bit <= dout_regValue(reg_index); -- userclk2 clock domain
if(fpga_conf = '0' and flash_conf = '0' and xadc_conf = '0')then
rd_en <= '0';
sreg_en <= '0';
reg_index <= 31;
fpgaPacket_rdy_i <= '0';
flashPacket_rdy <= '0';
xadcPacket_rdy <= '0';
wait_cnt <= (others => '0');
state <= ST_IDLE;
else
case state is
-- wait to be activated by registering process
when ST_IDLE =>
if(read_buffers = '1' and wait_cnt = "11111")then
wait_cnt <= (others => '0');
state <= ST_CHK;
elsif(read_buffers = '1' and wait_cnt /= "11111")then
wait_cnt <= wait_cnt + 1;
state <= ST_IDLE;
else
wait_cnt <= (others => '0');
state <= ST_IDLE;
end if;
-- check if the FIFOs are empty
when ST_CHK =>
if(addr_buffer_empty = '0' and val_buffer_empty = '0')then
rd_en <= '1';
state <= ST_WAIT;
else
rd_en <= '0';
state <= ST_DONE;
end if;
-- wait here for MUX and shift register
when ST_WAIT =>
rd_en <= '0';
wait_cnt <= wait_cnt + 1;
if(wait_cnt = "00111")then
state <= ST_WRH_SREG;
else
state <= ST_WAIT;
end if;
-- write the shift register
when ST_WRH_SREG =>
sreg_en <= '1';
state <= ST_WRL_SREG;
-- check the index
when ST_WRL_SREG =>
sreg_en <= '0';
if(reg_index = 0)then -- sent the entire register value
reg_index <= 31;
state <= ST_CHK;
else
reg_index <= reg_index - 1;
state <= ST_WAIT;
end if;
-- wait here until reset by master_handling_FSM
when ST_DONE =>
if(fpga_conf = '1')then
fpgaPacket_rdy_i <= '1';
elsif(flash_conf = '1')then
flashPacket_rdy <= '1';
elsif(xadc_conf = '1')then
xadcPacket_rdy <= '1';
else
fpgaPacket_rdy_i <= '1';
end if;
state <= ST_DONE;
when others =>
rd_en <= '0';
sreg_en <= '0';
reg_index <= 31;
fpgaPacket_rdy_i <= '0';
flashPacket_rdy <= '0';
xadcPacket_rdy <= '0';
wait_cnt <= (others => '0');
state <= ST_IDLE;
end case;
end if;
end if;
end process;
fpga_conf_router_inst: fpga_config_router
port map(
------------------------------------
------ General Interface -----------
clk_125 => clk_125,
reg_addr => dout_regAaddr(7 downto 0),
reg_rst => reg_rst,
reg_value_bit => reg_value_bit,
sreg_ena => sreg_en,
------------------------------------
---------- XADC Interface ----------
vmm_id_xadc => vmm_id_xadc,
xadc_sample_size => xadc_sample_size,
xadc_delay => xadc_delay,
------------------------------------
---------- AXI4SPI Interface -------
myIP_set => myIP_set,
myMAC_set => myMAC_set,
destIP_set => destIP_set,
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq => ckbc_freq,
cktk_max_num => cktk_max_num,
cktp_max_num => cktp_max_num,
cktp_skew => cktp_skew,
cktp_period => cktp_period,
cktp_width => cktp_width,
------------------------------------
-------- FPGA Config Interface -----
latency => latency,
tr_delay_limit => tr_delay_limit,
ckbc_max_num => ckbc_max_num,
daq_state => daq_state_reg,
trig_state => trig_state_reg,
ro_state => ro_state_reg,
fpga_rst_state => fpga_rst_reg
);
reg_addr_buffer: fpga_reg_buffer
PORT MAP (
rst => rst_fifo,
wr_clk => clk_125,
rd_clk => clk_125,
din => din_regAddr,
wr_en => wr_en,
rd_en => rd_en,
dout => dout_regAaddr,
full => addr_buffer_full,
empty => addr_buffer_empty,
wr_rst_busy => addr_rdRst_busy,
rd_rst_busy => addr_wrRst_busy
);
reg_value_buffer: fpga_reg_buffer
PORT MAP (
rst => rst_fifo,
wr_clk => clk_125,
rd_clk => clk_125,
din => reg_value,
wr_en => wr_en,
rd_en => rd_en,
dout => dout_regValue,
full => val_buffer_full,
empty => val_buffer_empty,
wr_rst_busy => val_rdRst_busy,
rd_rst_busy => val_wrRst_busy
);
-- FPGA reset asserter
rst_asserter_proc: process(clk_125)
begin
if(rising_edge(clk_125))then
if(fpga_rst_i = '1')then
case rst_cnt is
when 0 to 62 =>
fpga_rst <= '1';
rst_cnt <= rst_cnt + 1;
when 63 =>
fpga_rst <= '0';
reg_rst <= '1';
when others =>
rst_cnt <= 0;
fpga_rst <= '0';
reg_rst <= '0';
end case;
else
rst_cnt <= 0;
fpga_rst <= '0';
reg_rst <= '0';
end if;
end if;
end process;
din_regAddr <= x"000000" & reg_address;
fpgaPacket_rdy <= fpgaPacket_rdy_i;
-- process to handle daq state
daqOnOff_proc: process(daq_state_reg, daq_on_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case daq_state_reg is
when x"01" => daq_on_i <= '1';
when x"00" => daq_on_i <= '0';
when others => daq_on_i <= daq_on_i;
end case;
else
daq_on_i <= daq_on_i;
end if;
end process;
-- process to handle trigger state
triggerState_proc: process(trig_state_reg, ext_trg_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case trig_state_reg is
when x"04" => ext_trg_i <= '1';
when x"07" => ext_trg_i <= '0';
when others => ext_trg_i <= ext_trg_i;
end case;
else
ext_trg_i <= ext_trg_i;
end if;
end process;
-- process to handle readout state
readoutState_proc: process(ro_state_reg, ckbcMode_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case ro_state_reg is
when x"01" => ckbcMode_i <= '1';
when x"00" => ckbcMode_i <= '0';
when others => ckbcMode_i <= ckbcMode_i;
end case;
else
ckbcMode_i <= ckbcMode_i;
end if;
end process;
-- process to handle FPGA reset state
FPGArst_proc: process(fpga_rst_reg, fpga_rst_i, fpgaPacket_rdy_i)
begin
if(fpgaPacket_rdy_i = '1')then
case fpga_rst_reg is
when x"aa" => fpga_rst_i <= '1';
when x"00" => fpga_rst_i <= '0';
when others => fpga_rst_i <= fpga_rst_i;
end case;
else
fpga_rst_i <= fpga_rst_i;
end if;
end process;
-- synchronizing circuit
syncProc: process(clk_125)
begin
if(rising_edge(clk_125))then
daq_on_sync <= daq_on_i;
daq_on <= daq_on_sync;
ext_trg_sync <= ext_trg_i;
ext_trigger <= ext_trg_sync;
ckbcMode_sync <= ckbcMode_i;
ckbcMode <= ckbcMode_sync;
end if;
end process;
reg_value_bit <= dout_regValue(reg_index); -- userclk2 clock domain
rst_fifo <= rst or fpgaPacket_rdy_i or rst_fifo_init; -- reset the FIFOs after each configuration
end RTL;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/common/temac_10_100_1000_sync_block.vhd
|
2
|
4747
|
--------------------------------------------------------------------------------
-- Title : CDC Sync Block
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_sync_block.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to
-- another, this is a flip-flop pair, with both flops
-- placed together with RLOCs into the same slice. Thus
-- the routing delay between the two is minimum to safe-
-- guard against metastability issues.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity temac_10_100_1000_sync_block is
generic (
INITIALISE : bit_vector(1 downto 0) := "00"
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end temac_10_100_1000_sync_block;
architecture structural of temac_10_100_1000_sync_block is
-- Internal Signals
signal data_sync1 : std_logic;
signal data_sync2 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync1 : signal is "TRUE";
attribute ASYNC_REG of data_sync2 : signal is "TRUE";
attribute RLOC : string;
attribute RLOC of data_sync1 : signal is "X0Y0";
attribute RLOC of data_sync2 : signal is "X0Y0";
attribute SHREG_EXTRACT : string;
attribute SHREG_EXTRACT of data_sync1 : signal is "NO";
attribute SHREG_EXTRACT of data_sync2 : signal is "NO";
begin
data_sync : FD
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
D => data_in,
Q => data_sync1
);
data_sync_reg : FD
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
D => data_sync1,
Q => data_sync2
);
data_out <= data_sync2;
end structural;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/MMFE8_1VMM/sources_1/readout/select_data.vhd
|
1
|
2396
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity select_data is
port(
clk_in : in std_logic;
configuring : in std_logic;
data_acq : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
conf_data_in : in std_logic_vector(63 downto 0);
data_packet_length : in integer;
conf_packet_length : in integer;
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
data_out : out std_logic_vector(63 downto 0);
packet_length : out integer;
we : out std_logic;
end_packet : out std_logic
);
end select_data;
architecture Behavioral of select_data is
begin
data_selection : process(clk_in, configuring, data_acq)
begin
if rising_edge(clk_in) then
if configuring = '1' then
we <= we_conf;
data_out <= conf_data_in;
packet_length <= 2;--conf_packet_length;
end_packet <= end_packet_conf;
elsif data_acq = '1' then
we <= we_data;
data_out <= daq_data_in;
packet_length <= data_packet_length;
end_packet <= end_packet_daq;
else
we <= '0';
data_out <= (others => '0');
packet_length <= 0;
end_packet <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_IN4.vhd
|
1
|
4275
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 4bit input
entity EPROC_IN4 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4;
architecture Behavioral of EPROC_IN4 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
---
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
EPROC_IN4_direct_inst: entity work.EPROC_IN4_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN4_DEC8b10b_inst: entity work.EPROC_IN4_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/MMFE8_1VMM/sources_1/imports/sgmii_10_100_1000/ipcore_dir/i2c_top.vhd
|
2
|
1550
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity i2c_top is
generic(cnt_1ms : natural := 50_000; -- 20ns*50_000 = 1ms
cnt_10ms : natural := 500_000); --20ns*500_000 = 10ms
port(
clk_in : in std_logic; -- clk40, W19, LVCMOS33
phy_rstn_out : out std_logic
);
end i2c_top;
architecture rtl of i2c_top is
signal phy_resetn : std_logic := '0';
begin
phy_rstn_out <= phy_resetn;
phy_resetn_process : process(clk_in, phy_resetn) is
variable cnt : natural range 0 to cnt_1ms := 0; --1ms
begin
if (rising_edge(clk_in)) then
if phy_resetn = '0' then --resetn
if(cnt < cnt_1ms)then --cnt
cnt := cnt + 1;
elsif(cnt = cnt_1ms)then
cnt := 0;
phy_resetn <= '1';
else null;
end if; --cnt
else null;
end if; --resetn check
end if; --clk
end process;
end rtl;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4400/EPROC_OUT2.vhd
|
2
|
5358
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 2bit output
entity EPROC_OUT2 is
generic (
do_generate : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_outbits : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT2;
architecture Behavioral of EPROC_OUT2 is
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC0_case : std_logic_vector (1 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_case : std_logic;
signal edata_out_s : std_logic_vector (1 downto 0);
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
--
direct_case: entity work.EPROC_OUT2_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT2_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
HDLC_case: entity work.EPROC_OUT2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case010,
getDataTrig => getDataTrig_HDLC_case, -- output, data request
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_HDLC_case
);
--
-------------------------------------------------------------------------------------------
-- case 3: TTC-0
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "011")) else '1';
--
getDataTrig_TTC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "011") else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC0_case <= zeros2bit;
else
EdataOUT_TTC0_case <= TTCin;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX4_Nbit
generic map (N=>2)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC0_case,
sel => ENCODING(1 downto 0),
data_out => edata_out_s
);
--
getDataTrig <= ENA and (getDataTrig_TTC_case or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
edata_out_s <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
--
out_sel: process(swap_outbits,edata_out_s)
begin
if swap_outbits = '1' then
EDATA_OUT <= edata_out_s(0) & edata_out_s(1);
else
EDATA_OUT <= edata_out_s;
end if;
end process;
--
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/configuration/config_logic.vhd
|
1
|
33862
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Changelog:
-- 02.08.2016 Added ONLY_CONF_ONCE as a state to prevent multiple configuratoins
-- of the VMM. (Reid Pinkham)
-- 16.09.2016 Added additional elsif in state = CHECK for dynamic IP configuration
-- (Lev Kurilenko)
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity config_logic is
Port (
clk125 : in std_logic;
clk200 : in std_logic;
clk_in : in std_logic;
reset : in std_logic;
user_data_in : in std_logic_vector (7 downto 0);
user_data_out : out std_logic_vector (63 downto 0);
udp_rx : in udp_rx_type;
resp_data : out udp_response;
send_error : out std_logic;
user_conf : out std_logic;
user_wr_en : in std_logic;
user_last : in std_logic;
configuring : in std_logic;
-- we_conf : out std_logic;
vmm_id : out std_logic_vector(15 downto 0);
cfg_bit_out : out std_logic;
VMM_SCK : out std_logic;
VMM_SDO : in std_logic;
status : out std_logic_vector(3 downto 0);
start_vmm_conf : in std_logic;
conf_done : out std_logic;
ext_trigger : out std_logic;
ACQ_sync : out std_logic_vector(15 downto 0);
udp_header : in std_logic;
packet_length : in std_logic_vector (15 downto 0);
VMM_CS : out std_logic;
ena_conf : out std_logic;
xadc_busy : in std_logic;
xadc_start : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0);
myIP_set : out std_logic_vector(31 downto 0); --Lev
myMAC_set : out std_logic_vector(47 downto 0); --Lev
destIP_set : out std_logic_vector(31 downto 0); --Lev
newip_start : out std_logic --Lev
);
end config_logic;
architecture rtl of config_logic is
signal packet_length_int : integer := 0;
signal reading_packet : std_logic := '0';
signal user_last_int : std_logic := '0';
signal count, timeout : integer := 0;
signal last_synced200 : std_logic := '0';
signal i,w,del_cnt : integer := 0;
signal del_cnt2 : integer := 0;
signal counter, k, j : integer := 0;
signal sig_out : std_logic_vector(292 downto 0);
signal sn : std_logic_vector(31 downto 0);
signal vmm_id_int : std_logic_vector(15 downto 0);
signal cmd : std_logic_vector(15 downto 0);
signal user_data_in_int : std_logic_vector(7 downto 0);
signal status_int : std_logic_vector(3 downto 0);
signal user_wr_en_int : std_logic := '0';
signal cfg_bit_out_i : std_logic := '0';
signal VMM_SCK_i : std_logic := '0';
signal start_conf_process : std_logic := '0';
signal conf_done_i : std_logic := '0';
signal cnt_array, cnt_pause : integer := 0;
signal MainFSMstate : std_logic_vector(3 downto 0);
signal ConfFSMstate : std_logic_vector(3 downto 0);
signal test_data_int : std_logic_vector(31 downto 0);
signal delay_data : std_logic_vector(7 downto 0);
signal udp_header_int : std_logic := '0';
signal cs_int : std_logic := '1';
signal VMM_SDO_i : std_logic := '0';
type data_buffer is array(0 to 60) of std_logic_vector(31 downto 0);
signal conf_data : data_buffer;
signal reply_package : std_logic_vector(63 downto 0);
signal udp_response_int : udp_response;
signal start_vmm_conf_int : std_logic := '0';
signal start_vmm_conf_synced : std_logic := '0';
-- signal we_conf_int : std_logic := '0';
signal vmm_we_int : std_logic := '0';
signal cnt_cktk : integer := 0;
signal DAQ_START_STOP : std_logic_vector(31 downto 0);
signal dest_port : std_logic_vector(15 downto 0);
signal data_length : integer := 0;
signal cnt_reply : integer := 0;
signal cnt_conf_18 : integer := 0;
signal cnt_conf_96 : integer := 0;
signal delay_user_last : std_logic := '0';
signal ena_conf_i : std_logic := '1';
signal ERROR : std_logic_vector(15 downto 0);
signal vmm_id_xadc_i : std_logic_vector(15 downto 0);
signal xadc_sample_size_i : std_logic_vector(10 downto 0);
signal xadc_delay_i : std_logic_vector(17 downto 0);
-----------------------------------------------------------
-- IP Signal LEV
signal newip_counter : integer := 0; --Lev
-----------------------------------------------------------
type tx_state is (IDLE, SerialNo, VMMID, COMMAND, DATA, CHECK, VMM_CONF, DELAY, FPGA_CONF, XADC_Init, XADC, SEND_REPLY, TEST, REPLY);
signal state : tx_state;
type state_t is (START, SEND1,SEND0, PAUSE_ONE, FINISHED, ONLY_CONF_ONCE);
signal conf_state : state_t;
attribute keep : string;
attribute dont_touch : string;
attribute keep of sn : signal is "true";
attribute keep of vmm_id_int : signal is "true";
attribute keep of user_last_int : signal is "true";
attribute keep of cmd : signal is "true";
attribute keep of count : signal is "true";
attribute keep of last_synced200 : signal is "true";
attribute keep of reading_packet : signal is "true";
attribute keep of user_data_in_int : signal is "true";
attribute keep of user_wr_en_int : signal is "true";
attribute keep of packet_length_int : signal is "true";
attribute keep of cfg_bit_out_i : signal is "true";
attribute keep of status_int : signal is "true";
attribute keep of start_conf_process : signal is "true";
attribute keep of conf_done_i : signal is "true";
attribute keep of cnt_array : signal is "true";
attribute keep of DAQ_START_STOP : signal is "true";
attribute dont_touch of DAQ_START_STOP : signal is "true";
attribute keep of user_wr_en : signal is "true";
attribute dont_touch of user_wr_en : signal is "true";
attribute keep of MainFSMstate : signal is "true";
attribute keep of ConfFSMstate : signal is "true";
attribute keep of test_data_int : signal is "true";
attribute keep of delay_data : signal is "true";
attribute keep of i : signal is "true";
attribute keep of VMM_SCK_i : signal is "true";
attribute keep of udp_header_int : signal is "true";
attribute keep of j : signal is "true";
attribute keep of start_vmm_conf_int : signal is "true";
attribute keep of start_vmm_conf_synced : signal is "true";
attribute keep of dest_port : signal is "true";
attribute keep of cnt_conf_18 : signal is "true";
attribute keep of cnt_conf_96 : signal is "true";
-- attribute keep of vmm_id_xadc_i : signal is "true";
-- attribute keep of xadc_sample_size_i : signal is "true";
-- attribute keep of xadc_delay_i : signal is "true";
-- attribute keep of vmm_we_int : signal is "true";
-- attribute dont_touch of vmm_we_int : signal is "true";
attribute keep of cnt_cktk : signal is "true";
attribute dont_touch of cnt_cktk : signal is "true";
attribute keep of k : signal is "true";
attribute dont_touch of k : signal is "true";
attribute keep of cs_int : signal is "true";
attribute dont_touch of cs_int : signal is "true";
attribute keep of counter : signal is "true";
attribute dont_touch of counter : signal is "true";
attribute keep of del_cnt : signal is "true";
attribute dont_touch of del_cnt : signal is "true";
attribute keep of VMM_SDO_i : signal is "true";
attribute dont_touch of VMM_SDO_i : signal is "true";
attribute keep of ena_conf_i : signal is "true";
attribute dont_touch of ena_conf_i : signal is "true";
component ila_user_FIFO IS
PORT (
clk : IN std_logic;
probe0 : IN std_logic_vector(292 DOWNTO 0)
);
end component;
-----------------------------------------------------------
-- NEW IP Signals LEV
-----------------------------------------------------------
--attribute keep of conf_data : signal is "true"; --Lev
attribute keep of newip_counter : signal is "true"; --Lev
attribute keep of myIP_set : signal is "true"; --Lev
attribute keep of myMAC_set : signal is "true"; --Lev
attribute keep of destIP_set : signal is "true"; --Lev
begin
process (clk125)
begin
if clk125'event and clk125 = '1' then
user_wr_en_int <= user_wr_en;
delay_data <= user_data_in;
delay_user_last <= user_last;
end if;
end process;
user_last_int <= user_last;
user_data_in_int <= user_data_in;
--synced_to_125: process(clk125)
-- begin
-- if rising_edge(clk125) then
-- start_vmm_conf_synced <= start_vmm_conf_int;
-- end if;
-- end process;
------------------------ IDLE 0000
------------------------ VMM_CONF 0001
------------------------ XADC 0010
------------------------ RESET FPGA 0011
------------------------ DAQ OFF 1000
------------------------ FPGA_CONF 1001
------------------------ REPLY 1011
------------------------ DAQ ON 1111
process (clk125, state, configuring, cmd, reading_packet, count, packet_length_int, user_wr_en_int, last_synced200, user_wr_en, dest_port)
-- variable i : natural range 0 to 10 := 0; --1ms
begin
if clk125'event and clk125 = '1' then
if reset = '1' then
state <= IDLE;
else
case state is
when IDLE =>
MainFSMstate <= "0000";
status_int <= "0000";
count <= 0;
j <= 3;
cnt_array <= 0;
sn <= (others=> '0');
vmm_id_int <= x"0000";
cmd <= x"0000";
-- cs_int <= '1';
if user_wr_en = '1' then
state <= DATA;
end if;
when DATA =>
MainFSMstate <= "0001";
if j = 0 then
cnt_array <= cnt_array + 1;
conf_data(cnt_array)(8*j+ 7 downto 8*j) <= delay_data;
j <= 3;
else
conf_data(cnt_array)(8*j+ 7 downto 8*j) <= delay_data;
j <= j - 1;
end if;
if delay_user_last = '1' then
-- cnt_array <= 0;
-- count <= 4;
j <= 0;
state <= SerialNo;
end if;
when SerialNo =>
MainFSMstate <= "0010";
-- count <= count - 1;
sn <= conf_data(0);
reply_package(63 downto 32) <= sn;
state <= VMMID;
when VMMID =>
MainFSMstate <= "0011";
vmm_id_int <= conf_data(1)(31 downto 16);
packet_length_int <= to_integer(unsigned(packet_length));
data_length <= packet_length_int - 8;
reply_package(31 downto 16) <= vmm_id_int;
state <= COMMAND;
when COMMAND =>
MainFSMstate <= "0100";
cmd <= conf_data(1)(15 downto 0);
reply_package(15 downto 0) <= cmd;
state <= CHECK;
when CHECK =>
MainFSMstate <= "0101";
if dest_port = x"1778" then -- 6008 VMM CONFIGURATION
state <= VMM_CONF;
-- if vmm_id_int /= x"ffff" then
status_int <= "0001";
-- else
-- status_int <= "0010";
-- end if;
elsif dest_port = x"19C8" or dest_port = x"1777" then -- 6600 FPGA CONFIGURATION
cmd <= conf_data(1)(31 downto 16);
vmm_id_int <= conf_data(1)(15 downto 0);
state <= FPGA_CONF;
status_int <= "1001";
count <= 0;
elsif dest_port = x"19CC" then -- 6604 Flash Configuration --Lev
-- wait a few clock cycles to initatiate New IP Set --Lev
-- wait around 10 clock cycles --Lev
newip_start <= '1'; --Lev
newip_counter <= newip_counter + 1; --Lev
myIP_set <= conf_data(2)(31 downto 0); --Lev
myMAC_set(47 downto 32) <= conf_data(3)(15 downto 0); --Lev
myMAC_set(31 downto 0) <= conf_data(4)(31 downto 0); --Lev
destIP_set <= conf_data(5)(31 downto 0); --Lev
if (newip_counter = 10) then
newip_counter <= 0;
newip_start <= '0';
state <= IDLE;
end if;
elsif dest_port = x"19D0" then -- 6608 XADC
state <= XADC_Init;
status_int <= "0100";
xadc_start <= '1';
if cnt_array > 0 then -- If it is not an empty packet
vmm_id_xadc_i <= conf_data(0)(15 downto 0);
xadc_sample_size_i <= conf_data(1)(10 downto 0);
xadc_delay_i <= conf_data(2)(17 downto 0);
else -- is an empty packet
vmm_id_xadc_i <= "0000000000000000";
xadc_sample_size_i <= "01111111111"; -- 1023 packets
xadc_delay_i <= "011111111111111111"; -- 1023 samples over ~0.7 seconds
end if;
else
count <= 0;
state <= IDLE;
end if;
when VMM_CONF =>
MainFSMstate <= "0110";
if timeout = 5000000 then
state <= IDLE;
timeout <= 0;
ERROR <= x"ffff";
else
timeout <= timeout + 1;
end if;
if conf_done_i = '1' then
-- user_data_out <= reply_package;
state <= DELAY;-- SEND_REPLY;
-- reading_packet <= '0';
ERROR <= x"0000";
status_int <= "1011";
end if;
when DELAY =>
if del_cnt2 = 10 then
state <= REPLY;
del_cnt2 <= 0;
else
del_cnt2 <= del_cnt2 + 1;
end if;
when XADC_Init => -- Initialize the XADC
MainFSMstate <= "0111";
state <= XADC;
xadc_start <= '0';
when XADC => --Main XADC State
if (xadc_busy = '0') then -- if xadc is done
state <= IDLE;
else
state <= XADC;
end if;
when FPGA_CONF =>
MainFSMstate <= "1011";
-- DAQ_START_STOP <= conf_data(count+2);
-------------------------------------set this for the real configuration
-- if count*8 <= data_length then
-- if conf_data(count + 2) = x"00000000" and conf_data(count + 3) = x"00000004" then -- EXTERNAL
-- ext_trigger <= '1';
-- elsif conf_data(count + 2) = x"00000000" and conf_data(count + 3) = x"00000007" then -- PULSER
-- ext_trigger <= '0';
-- elsif conf_data(count + 2) = x"00001111" and conf_data(count + 3) = x"00000001" then -- DAQ ON
-- status_int <= "1111";
-- elsif conf_data(count + 2) = x"00001111" and conf_data(count + 3) = x"00000000" then -- DAQ OFF
-- status_int <= "1000";
-- elsif conf_data(count + 2) = x"ffffffff" and conf_data(count + 3) = x"ffff8000" then -- RESET FPGA
-- status_int <= "0011";
-- else
-- state <= IDLE;
-- end if;
-- else
-- count <= 0;
-- state <= IDLE;
-- end if;
-------------------------------------set this for the real configuration
DAQ_START_STOP <= conf_data(4);
if conf_data(5) = x"00000004" and conf_data(4) = x"00000000" then -- EXTERNAL
ext_trigger <= '1';
state <= TEST;
elsif conf_data(5) = x"00000007" and conf_data(4) = x"00000000" then -- PULSER
ext_trigger <= '0';
state <= TEST;
elsif conf_data(5) = x"00000001" and conf_data(4) = x"0000000f" then -- DAQ ON
status_int <= "1111";
state <= TEST;
elsif conf_data(5) = x"00000000" and conf_data(4) = x"0000000f" then -- DAQ OFF
status_int <= "1000";
state <= TEST;
elsif conf_data(4) = x"ffffffff" and conf_data(5) = x"ffff8000" then -- RESET FPGA
status_int <= "0011";
state <= IDLE;
elsif conf_data(4) = x"00000005" then -- Latency
ACQ_sync <= conf_data(5)(15 downto 0);
state <= IDLE;
else
state <= TEST;
end if;
when TEST =>
if count < 10 then
DAQ_START_STOP <= conf_data(count);
count <= count + 1;
else
count <= 0;
state <= IDLE;
end if;
when REPLY =>
state <= IDLE;
-- if cnt_reply = 0 then
---- user_data_out_i <= conf_data_out_i;
-- user_data_out <= reply_package;
-- cnt_reply <= cnt_reply + 1;
-- elsif cnt_reply = 1 then
-- user_data_out_i <= (others => '0');
-- cnt_reply <= cnt_reply + 1;
-- end_packet_conf_int <= '1';
-- we_conf_int <= '0';
-- elsif cnt_reply > 1 and cnt_reply < 100 then
-- cnt_reply <= cnt_reply + 1;
-- else
-- cnt_reply <= 0;
-- state <= IDLE;
---- state <= DAQ_INIT;
-- end_packet_conf_int <= '1';
-- end if;
when others =>
end case;
end if;
end if;
end process;
--synced_to_clkin: process(clk_in)
-- begin
-- if rising_edge(clk_in) then
-- start_vmm_conf_synced <= start_vmm_conf;
-- end if;
-- end process;
sync_start_vmm_conf: process(clk200)
begin
if rising_edge(clk200) then
if start_vmm_conf = '1' then
start_vmm_conf_synced <= '1';
end if;
if w = 40 then
start_vmm_conf_synced <= '0';
w <= 0;
else
w <= w + 1;
end if;
end if;
end process;
config_vmm_fsm : process( clk_in, conf_state, k, i, counter, del_cnt)
begin
if rising_edge( clk_in) then
if reset = '1' or status_int = "0011" then
conf_state <= START;
else
case conf_state is
when START =>
ConfFSMstate <= "0001";
cnt_conf_96 <= 0;
cnt_conf_18 <= 0;
cs_int <= '1';
counter <= 1728;
i <= 31;
k <= 2;
cfg_bit_out_i <= '0';
VMM_SCK_i <= '0';
test_data_int <= conf_data(k);
conf_done_i <= '0';
if start_vmm_conf = '1' then
conf_state <= SEND0;
cs_int <= '0';
ena_conf_i <= '0';
end if;
when SEND0 =>
ConfFSMstate <= "0010";
VMM_SCK_i <= '1';
cnt_cktk <= cnt_cktk + 1;
if cnt_conf_96 < 96 then
cnt_conf_96 <= cnt_conf_96 + 1;
conf_state <= SEND1;
else
cnt_conf_96 <= 0;
conf_state <= PAUSE_ONE;
VMM_SCK_i <= '0';
cnt_conf_18 <= cnt_conf_18 + 1;
cs_int <= '1';
end if;
if cnt_conf_18 = 18 then
conf_state <= FINISHED;
end if;
if k <= packet_length_int - 1 then
test_data_int <= conf_data(k);
if i /= 0 then
cfg_bit_out_i <= conf_data(k)(i);--(0);
i <= i - 1;
else
cfg_bit_out_i <= conf_data(k)(0);
k <= k + 1;
i <= 31;
end if;
end if;
when SEND1 =>
if cnt_conf_96 = 0 then
cs_int <= '0';
end if;
ConfFSMstate <= "0011";
VMM_SCK_i <= '0';
if (counter - 2) >= 0 then
if cnt_conf_96 /= 96 then
counter <= counter - 1;
end if;
conf_state <= SEND0;
else
conf_state <= FINISHED;
end if;
when PAUSE_ONE =>
ConfFSMstate <= "1111";
VMM_SCK_i <= '0';
cfg_bit_out_i <= '0';
i <= 31;
if cnt_pause = 10 then
conf_state <= SEND1;
cnt_pause <= 0;
else
cnt_pause <= cnt_pause + 1;
end if;
when FINISHED =>
cnt_conf_96 <= 0;
cnt_conf_18 <= 0;
cs_int <= '0';
ena_conf_i <= '1';
ConfFSMstate <= "0100";
cfg_bit_out_i <= '0';
if del_cnt = 5 then
conf_done_i <= '1';
del_cnt <= del_cnt + 1;
elsif del_cnt = 100 then
conf_state <= ONLY_CONF_ONCE;
del_cnt <= 0;
else
del_cnt <= del_cnt + 1;
end if;
VMM_SCK_i <= '0';
counter <= 0;
cs_int <= '1';
cnt_cktk <= 0;
when ONLY_CONF_ONCE =>
ConfFSMstate <= "0101";
if (start_vmm_conf = '0') then
conf_state <= START;
else
conf_state <= ONLY_CONF_ONCE;
end if;
end case;
end if;
end if;
end process config_vmm_fsm ;
start_vmm_conf_int <= start_vmm_conf;
vmm_id <= vmm_id_int;
dest_port <= udp_rx.hdr.dst_port;
vmm_id_xadc <=vmm_id_xadc_i;
xadc_sample_size <= xadc_sample_size_i;
xadc_delay <= xadc_delay_i;
status <= status_int;
conf_done <= conf_done_i;
cfg_bit_out <= cfg_bit_out_i;
VMM_SCK <= VMM_SCK_i;
-- ila_conf_logic : ila_user_FIFO
-- port map(
-- clk => clk125,
-- probe0 => sig_out
-- );
--we_conf <= we_conf_int;
--vmm_we_int <= vmm_we;
VMM_CS <= cs_int;
VMM_SDO_i <= VMM_SDO;
ena_conf <= ena_conf_i;
sig_out(7 downto 0) <= delay_data;
sig_out(8) <= start_vmm_conf_int;--user_fifo_empty;
sig_out(9) <= start_vmm_conf_synced;--user_fifo_en_main;--'0'; --user_fifo_en;
sig_out(10) <= udp_header_int;--send_error_int;
sig_out(11) <= user_wr_en;
sig_out(43 downto 12) <= sn;
sig_out(59 downto 44) <= vmm_id_int;
sig_out(75 downto 60) <= cmd;
sig_out(83 downto 76) <= std_logic_vector(to_unsigned(count, sig_out(83 downto 76)'length));
sig_out(91 downto 84) <= std_logic_vector(to_unsigned(cnt_array, 8));
sig_out(92) <= user_last_int;
sig_out(93) <= last_synced200;
--sig_out(110) <= reading_packet;
sig_out(101 downto 94) <= user_data_in_int;
sig_out(102) <= user_wr_en_int;
sig_out(103) <= VMM_SCK_i;--user_conf_int;
sig_out(104) <= cfg_bit_out_i;--reset_fifo_int;
sig_out(112 downto 105) <= std_logic_vector(to_unsigned(packet_length_int, sig_out(112 downto 105)'length));
sig_out(113) <= conf_done_i;--configuring_int;
sig_out(117 downto 114) <= status_int;
sig_out(118) <= start_conf_process;
sig_out(122 downto 119) <= MainFSMstate;
sig_out(126 downto 123) <= ConfFSMstate;
sig_out(134 downto 127) <= std_logic_vector(to_unsigned(i, sig_out(135 downto 128)'length));
sig_out(166 downto 135) <= test_data_int;
sig_out(174 downto 167) <= std_logic_vector(to_unsigned(j, sig_out(175 downto 168)'length));
sig_out(190 downto 175) <= std_logic_vector(to_unsigned(counter, sig_out(190 downto 175)'length));
sig_out(198 downto 191) <= std_logic_vector(to_unsigned(k, sig_out(198 downto 191)'length));
sig_out(214 downto 199) <= dest_port;
sig_out(246 downto 215) <= DAQ_START_STOP;
sig_out(247) <= cs_int;
sig_out(255 downto 248) <= std_logic_vector(to_unsigned(cnt_conf_18, sig_out(255 downto 248)'length));
sig_out(263 downto 256) <= std_logic_vector(to_unsigned(cnt_conf_96, sig_out(255 downto 248)'length));
sig_out(264) <= VMM_SDO_i;
sig_out(265) <= ena_conf_i;
--sig_out(262 downto 247) <= vmm_id_xadc_i;
--sig_out(273 downto 263) <= xadc_sample_size_i;
--sig_out(291 downto 274) <= xadc_delay_i;
sig_out(292 downto 266) <= (others => '0');
end rtl;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/imports/arp_REQ.vhd
|
2
|
12101
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_REQ - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle requests for ARP resolution
-- responds from single entry cache or searches external arp store, or asks to send a request
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created from arp.vhd 0.2
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_req is
generic (
no_default_gateway : boolean := true; -- set to false if communicating with devices accessed
-- through a "default gateway or router"
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5 -- # wrong nwk pkts received before set error
);
port (
-- lookup request signals
arp_req_req : in arp_req_req_type; -- request for a translation from IP to MAC
arp_req_rslt : out arp_req_rslt_type; -- the result
-- external arp store signals
arp_store_req : out arp_store_rdrequest_t; -- requesting a lookup or store
arp_store_result : in arp_store_result_t; -- the result
-- network request signals
arp_nwk_req : out arp_nwk_request_t; -- requesting resolution via the network
arp_nwk_result : in arp_nwk_result_t; -- the result
-- system signals
clear_cache : in std_logic; -- clear the internal cache
nwk_gateway : in std_logic_vector(31 downto 0); -- IP address of default gateway
nwk_mask : in std_logic_vector(31 downto 0); -- Net mask
clk : in std_logic;
reset : in std_logic
);
end arp_req;
architecture Behavioral of arp_req is
type req_state_t is (IDLE, LOOKUP, WAIT_REPLY, PAUSE1, PAUSE2, PAUSE3);
type set_cntr_t is (HOLD, CLR, INCR);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal req_state : req_state_t;
signal req_ip_addr : std_logic_vector (31 downto 0); -- IP address to lookup
signal arp_entry_cache : arp_entry_t; -- single entry cache for fast response
signal cache_valid : std_logic; -- single entry cache is valid
signal nwk_rx_cntr : unsigned(7 downto 0); -- counts nwk rx pkts that dont satisfy
signal freq_scaler : unsigned (31 downto 0); -- scales data_in_clk downto 1Hz
signal timer : unsigned (7 downto 0); -- counts seconds timeout
signal timeout_reg : std_logic;
-- busses
signal next_req_state : req_state_t;
signal arp_entry_val : arp_entry_t;
-- requester control signals
signal set_req_state : std_logic;
signal set_req_ip : std_logic;
signal store_arp_cache : std_logic;
signal set_nwk_rx_cntr : set_cntr_t;
signal set_timer : set_cntr_t; -- timer reset, count, hold control
signal timer_enable : std_logic; -- enable the timer counting
signal set_timeout : set_clr_type; -- control the timeout register
signal clear_cache_valid : std_logic;
signal l_arp_req_req_ip : std_logic_vector(31 downto 0); -- local network IP address for resolution
begin
default_GW: if (not no_default_gateway) generate
default_gw_comb_p: process (arp_req_req.ip, nwk_gateway, nwk_mask) is
begin -- process default_gw_comb_p
-- translate IP addresses to local IP address if necessary
if ((nwk_mask and arp_req_req.ip) = (nwk_mask and nwk_gateway)) then
-- on local network
l_arp_req_req_ip <= arp_req_req.ip;
else
-- on remote network
l_arp_req_req_ip <= nwk_gateway;
end if;
end process default_gw_comb_p;
end generate default_GW;
no_default_GW: if (no_default_gateway) generate
no_default_gw_comb_p: process (arp_req_req.ip) is
begin -- process no_default_gw_comb_p
l_arp_req_req_ip <= arp_req_req.ip;
end process no_default_gw_comb_p;
end generate no_default_GW;
req_combinatorial : process (
arp_entry_cache.ip, arp_entry_cache.mac, arp_nwk_result.entry, arp_nwk_result.entry.ip,
arp_nwk_result.entry.mac, arp_nwk_result.status, arp_req_req.lookup_req,
arp_store_result.entry, arp_store_result.entry.mac, arp_store_result.status, cache_valid,
clear_cache, freq_scaler, l_arp_req_req_ip, nwk_rx_cntr, req_ip_addr, req_state,
timeout_reg, timer)
begin
-- set output followers
arp_req_rslt.got_mac <= '0'; -- set initial value of request result outputs
arp_req_rslt.got_err <= '0';
arp_req_rslt.mac <= (others => '0');
arp_store_req.req <= '0';
arp_store_req.ip <= (others => '0');
arp_nwk_req.req <= '0';
arp_nwk_req.ip <= (others => '0');
-- zero time response to lookup request if already in cache
if arp_req_req.lookup_req = '1' and l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
elsif arp_req_req.lookup_req = '1' then
-- hold off got_mac while req is there as arp_entry will not be correct yet
arp_req_rslt.got_mac <= '0';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
arp_req_rslt.got_mac <= cache_valid;
arp_req_rslt.mac <= arp_entry_cache.mac;
end if;
if arp_req_req.lookup_req = '1' then
-- ensure any existing error report is killed at the start of a request
arp_req_rslt.got_err <= '0';
else
arp_req_rslt.got_err <= timeout_reg;
end if;
-- set signal defaults
next_req_state <= IDLE;
set_req_state <= '0';
set_req_ip <= '0';
store_arp_cache <= '0';
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
set_nwk_rx_cntr <= HOLD;
set_timer <= INCR; -- default is timer running, unless we hold or reset it
set_timeout <= HOLD;
timer_enable <= '0';
clear_cache_valid <= clear_cache;
-- combinatorial logic
if freq_scaler = x"00000000" then
timer_enable <= '1';
end if;
-- REQ FSM
case req_state is
when IDLE =>
set_timer <= CLR;
if arp_req_req.lookup_req = '1' then
-- check if we already have the info in cache
if l_arp_req_req_ip = arp_entry_cache.ip and cache_valid = '1' then
-- already have this IP - feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_entry_cache.mac;
else
clear_cache_valid <= '1'; -- remove cache entry
set_timeout <= CLR;
next_req_state <= LOOKUP;
set_req_state <= '1';
set_req_ip <= '1';
end if;
end if;
when LOOKUP =>
-- put request on the store
arp_store_req.ip <= req_ip_addr;
arp_store_req.req <= '1';
case arp_store_result.status is
when FOUND =>
-- update the cache
arp_entry_val <= arp_store_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_store_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
when NOT_FOUND =>
-- need to request from the network
set_timer <= CLR;
set_nwk_rx_cntr <= CLR;
arp_nwk_req.req <= '1';
arp_nwk_req.ip <= req_ip_addr;
next_req_state <= WAIT_REPLY;
set_req_state <= '1';
when others =>
-- just keep waiting - no timeout (assumes lookup with either succeed or fail)
end case;
when WAIT_REPLY =>
case arp_nwk_result.status is
when RECEIVED =>
if arp_nwk_result.entry.ip = req_ip_addr then
-- store into cache
arp_entry_val <= arp_nwk_result.entry;
store_arp_cache <= '1';
-- and feed output back
arp_req_rslt.got_mac <= '1';
arp_req_rslt.mac <= arp_nwk_result.entry.mac;
next_req_state <= IDLE;
set_req_state <= '1';
else
if nwk_rx_cntr > ARP_MAX_PKT_TMO then
set_timeout <= SET;
next_req_state <= IDLE;
set_req_state <= '1';
else
set_nwk_rx_cntr <= INCR;
end if;
end if;
when error =>
set_timeout <= SET;
when others =>
if timer >= ARP_TIMEOUT then
set_timeout <= SET;
next_req_state <= PAUSE1;
set_req_state <= '1';
end if;
end case;
when PAUSE1 =>
next_req_state <= PAUSE2;
set_req_state <= '1';
when PAUSE2 =>
next_req_state <= PAUSE3;
set_req_state <= '1';
when PAUSE3 =>
next_req_state <= IDLE;
set_req_state <= '1';
end case;
end process;
req_sequential : process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
req_state <= IDLE;
req_ip_addr <= (others => '0');
arp_entry_cache.ip <= (others => '0');
arp_entry_cache.mac <= (others => '0');
cache_valid <= '0';
nwk_rx_cntr <= (others => '0');
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
timer <= (others => '0');
timeout_reg <= '0';
else
-- Next req_state processing
if set_req_state = '1' then
req_state <= next_req_state;
else
req_state <= req_state;
end if;
-- Latch the requested IP address
if set_req_ip = '1' then
req_ip_addr <= l_arp_req_req_ip;
else
req_ip_addr <= req_ip_addr;
end if;
-- network received counter
case set_nwk_rx_cntr is
when CLR => nwk_rx_cntr <= (others => '0');
when INCR => nwk_rx_cntr <= nwk_rx_cntr + 1;
when HOLD => nwk_rx_cntr <= nwk_rx_cntr;
end case;
-- set the arp_entry_cache
if clear_cache_valid = '1' then
arp_entry_cache <= arp_entry_cache;
cache_valid <= '0';
elsif store_arp_cache = '1' then
arp_entry_cache <= arp_entry_val;
cache_valid <= '1';
else
arp_entry_cache <= arp_entry_cache;
cache_valid <= cache_valid;
end if;
-- freq scaling and 1-sec timer
if freq_scaler = x"00000000" then
freq_scaler <= to_unsigned(CLOCK_FREQ, 32);
else
freq_scaler <= freq_scaler - 1;
end if;
-- timer processing
case set_timer is
when CLR =>
timer <= x"00";
when INCR =>
if timer_enable = '1' then
timer <= timer + 1;
else
timer <= timer;
end if;
when HOLD =>
timer <= timer;
end case;
-- timeout latching
case set_timeout is
when CLR => timeout_reg <= '0';
when SET => timeout_reg <= '1';
when HOLD => timeout_reg <= timeout_reg;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/MMFE8_1VMM/sources_1/imports/tx_arbitrator.vhd
|
2
|
3035
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_arbitrator is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end tx_arbitrator;
architecture Behavioral of tx_arbitrator is
type grant_type is (M1,M2);
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1, valid_1, first_1, last_1,
data_2, valid_2, first_2, last_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
valid <= valid_1;
first <= first_1;
last <= last_1;
else
data <= data_2;
valid <= valid_2;
first <= first_2;
last <= last_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN4_ALIGN_BLOCK.vhd
|
2
|
5112
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_UNSIGNED.ALL;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 4bit bit-stream to two commas
entity EPROC_IN4_ALIGN_BLOCK is
Port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_2array_type; -- 8b10b encoded
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN4_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN4_ALIGN_BLOCK is
signal bytes_rdy_enabled : std_logic;
signal bytes_r, bytes_c3 : word10b_2array_type := ((others=>'0'),(others=>'0'));
signal bytes_rdy_r, send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, dataOUTrdy_c3, dataOUTrdy_s1, bytes_rdy_s : std_logic := '0';
signal byte_count, byte_count_c3 : std_logic_vector(0 downto 0) := "0";
signal dataOUT_s_fe : std_logic_vector(9 downto 0);
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
bytes_rdy_enabled <= bytes_rdy;
--
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_s <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_enabled = '1' then
bytes_rdy_s <= not bytes_rdy_s;
else
bytes_rdy_s <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_r <= ((others=>'0'),(others=>'0'));
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_enabled = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
bytes_rdy_r <= bytes_rdy_s and bytes_rdy_enabled;
--
process(bitCLKx2)
begin
if bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_r = '1' then
byte_count <= "0";
else
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "0";
end if;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif bitCLKx2'event and bitCLKx2 = '1' then
if bytes_rdy_r = '1' then
send_state <= '1';
else
if byte_count = "1" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock2
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- clock3*
-- bitCLKx2 -> bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
bytes_c3 <= bytes_r;
dataOUTrdy_c3 <= dataOUTrdy_s;
byte_count_c3 <= byte_count;
end if;
end process;
--
out_select_proc: process(byte_count_c3, bytes_c3)
begin
case (byte_count_c3) is
when "0" => dataOUT_s <= bytes_c3(0);
when "1" => dataOUT_s <= bytes_c3(1);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- clock4*
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
dataOUTrdy_s1 <= dataOUTrdy_c3;
end if;
end process;
--
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT_s_fe(7 downto 0),
ISK => dataOUT_s_fe(9 downto 8),
BUSY => busyOut
);
--
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
dataOUT <= dataOUT_s_fe;
--dataOUTrdy <= dataOUTrdy_s1;
end if;
end process;
--
dataOUTrdy <= dataOUTrdy_s1;
--
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/MMFE8_1VMM/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/fifo/temac_10_100_1000_rx_client_fifo.vhd
|
2
|
37025
|
--------------------------------------------------------------------------------
-- Title : Receiver FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_rx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the receiver side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is created from 2 Block RAMs of size 2048
-- words of 8-bits per word, giving a total frame memory capacity
-- of 4096 bytes.
--
-- Frame data received from the MAC receiver is written into the
-- FIFO on the rx_mac_aclk. An end-of-frame marker is written to
-- the BRAM parity bit on the last byte of data stored for a frame.
-- This acts as frame deliniation.
--
-- The rx_axis_mac_tvalid, rx_axis_mac_tlast, and rx_axis_mac_tuser signals
-- qualify the frame. A frame which ends with rx_axis_mac_tuser asserted
-- indicates a bad frame and will cause the FIFO write address
-- pointer to be reset to the base address of that frame. In this
-- way the bad frame will be overwritten with the next received
-- frame and is therefore dropped from the FIFO.
--
-- Frames will also be dropped from the FIFO if an overflow occurs.
-- If there is not enough memory capacity in the FIFO to store the
-- whole of an incoming frame, the write address pointer will be
-- reset and the overflow signal asserted.
--
-- When there is at least one complete frame in the FIFO,
-- the 8-bit AxiStream read interface's rx_axis_fifo_tvalid signal will
-- be enabled allowing data to be read from the FIFO.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The read clock (user side) should
-- always operate at an equal or faster frequency than the write
-- clock (MAC side).
--
-- The FIFO is designed to work with a minimum frame length of 8
-- bytes.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
-- Requirements :
-- * Minimum frame size of 8 bytes
-- * Spacing between good/bad frame signaling (encoded by
-- rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser), is at least 64
-- clock cycles
-- * Write AxiStream clock is 125MHz downto 1.25MHz
-- * Read AxiStream clock equal to or faster than write clock,
-- and downto 20MHz
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library unimacro;
use unimacro.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the Receiver FIFO
--------------------------------------------------------------------------------
entity temac_10_100_1000_rx_client_fifo is
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tready : out std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end temac_10_100_1000_rx_client_fifo;
architecture RTL of temac_10_100_1000_rx_client_fifo is
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
signal VCC : std_logic;
signal GND_BUS : std_logic_vector(8 downto 0);
signal GND : std_logic_vector(0 downto 0);
-- Encoded read state machine states
type rd_state_typ is (WAIT_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
QUEUE_SOF_s,
SOF_s,
DATA_s,
EOF_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states
type wr_state_typ is (IDLE_s,
FRAME_s,
GF_s,
BF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe_long is array(0 to 2) of std_logic;
type cntl_pipe_short is array(0 to 1) of std_logic;
signal wr_en : std_logic;
signal wr_en_u : std_logic;
signal wr_en_u_bram : std_logic_vector(0 downto 0);
signal wr_en_l : std_logic;
signal wr_en_l_bram : std_logic_vector(0 downto 0);
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_dv_pipe : cntl_pipe_long;
signal wr_gfbf_pipe : cntl_pipe_short;
signal wr_gf : std_logic;
signal wr_bf : std_logic;
signal wr_eof_bram_pipe : cntl_pipe_short;
signal wr_eof_bram : std_logic;
signal frame_in_fifo : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram_u : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_l : std_logic_vector(8 downto 0);
signal rd_data_bram_u : std_logic_vector(7 downto 0);
signal rd_data_bram_l : std_logic_vector(7 downto 0);
signal rd_data_pipe_u : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_pipe_l : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_valid_pipe : std_logic_vector(1 downto 0);
signal rd_eof_bram_u : std_logic_vector(0 downto 0);
signal rd_eof_bram_l : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_bram_u : std_logic;
signal rd_bram_u_reg : std_logic;
signal rd_pull_frame : std_logic;
signal rd_eof : std_logic;
signal rd_addr_slv : std_logic_vector(10 downto 0);
signal wr_addr_slv : std_logic_vector(10 downto 0);
signal wr_store_frame_tog : std_logic := '0';
signal rd_store_frame_sync : std_logic;
signal rd_store_frame_delay : std_logic := '0';
signal rd_store_frame : std_logic;
signal rd_frames : unsigned(8 downto 0);
signal wr_fifo_full : std_logic;
signal old_rd_addr : std_logic_vector(1 downto 0);
signal update_addr_tog : std_logic;
signal update_addr_tog_sync : std_logic;
signal update_addr_tog_sync_reg : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff_in : unsigned(12 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal wr_fifo_status : unsigned(3 downto 0);
signal rx_axis_fifo_tlast_int : std_logic;
signal doa_l_unused : std_logic_vector(8 downto 0);
signal doa_u_unused : std_logic_vector(8 downto 0);
signal rx_fifo_reset : std_logic;
signal rx_mac_reset : std_logic;
--------------------------------------------------------------------------------
-- Begin FIFO architecture
--------------------------------------------------------------------------------
begin
VCC <= '1';
GND_BUS <= (others => '0');
GND(0) <= GND_BUS(0);
-- invert reset sense as architecture is optimised for active high resets
rx_fifo_reset <= not rx_fifo_resetn;
rx_mac_reset <= not rx_mac_resetn;
------------------------------------------------------------------------------
-- Read state machines and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are WAIT, QUEUE1, QUEUE2, QUEUE3, QUEUE_SOF, SOF, DATA, EOF.
-- Clock state to next state.
clock_rds_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_state <= WAIT_s;
else
rd_state <= rd_nxt_state;
end if;
end if;
end process clock_rds_p;
rx_axis_fifo_tlast <= rx_axis_fifo_tlast_int;
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rx_axis_fifo_tready,
rx_axis_fifo_tlast_int, rd_valid_pipe)
begin
case rd_state is
when WAIT_s =>
-- Wait until there is a full frame in the FIFO, then
-- start to load the pipeline.
if frame_in_fifo = '1' and rx_axis_fifo_tlast_int = '0' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= WAIT_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_SOF_s;
when QUEUE_SOF_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_s;
when SOF_s =>
-- A new frame begins immediately following end of last frame.
if rx_axis_fifo_tready = '1' then
rd_nxt_state <= DATA_s;
else
rd_nxt_state <= SOF_s;
end if;
when DATA_s =>
-- Read data from the FIFO. When the EOF marker is detected from
-- the BRAM output, move to the EOF state.
if rx_axis_fifo_tready = '1' and rd_eof = '1' then
rd_nxt_state <= EOF_s;
else
rd_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- Hold in this state until tready is asserted and the EOF
-- marker (tlast) is accepted on interface.
-- If there is another frame in the FIFO, then it will already be
-- queued into the pipeline so so move straight to SOF state.
if rx_axis_fifo_tready = '1' then
if rd_valid_pipe(1) = '1' then
rd_nxt_state <= SOF_s;
else
rd_nxt_state <= WAIT_s;
end if;
else
rd_nxt_state <= EOF_s;
end if;
when others =>
rd_nxt_state <= WAIT_s;
end case;
end process next_rds_p;
-- Detect if frame_in_fifo was high 3 reads ago.
-- This is used to ensure we only treat data in the pipeline as valid if
-- frame_in_fifo goes high at or before the EOF marker of the current frame.
-- It may be that there is valid data (i.e a partial frame has been written)
-- but until the end of that frame we do not know if it is a good frame.
rd_valid_pipe_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if (rx_axis_fifo_tready = '1') then
rd_valid_pipe <= rd_valid_pipe(0) & frame_in_fifo;
end if;
end if;
end process rd_valid_pipe_p;
-- Decode tlast signal from EOF marker.
rd_ll_decode_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tlast_int <= '0';
elsif rx_axis_fifo_tready = '1' then
-- Assert tlast signal when the EOF marker has been detected, and
-- continue to drive it until it has been accepted on the interface.
case rd_state is
when EOF_s =>
rx_axis_fifo_tlast_int <= '1';
when others =>
rx_axis_fifo_tlast_int <= '0';
end case;
end if;
end if;
end process rd_ll_decode_p;
-- Decode the tvalid output based on state.
rd_ll_src_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tvalid <= '0';
else
case rd_state is
when QUEUE_SOF_s =>
rx_axis_fifo_tvalid <= '1';
when SOF_s =>
rx_axis_fifo_tvalid <= '1';
when DATA_s =>
rx_axis_fifo_tvalid <= '1';
when EOF_s =>
rx_axis_fifo_tvalid <= '1';
when others =>
if rx_axis_fifo_tready = '1' then
rx_axis_fifo_tvalid <= '0';
end if;
end case;
end if;
end if;
end process rd_ll_src_p;
-- Decode internal control signals.
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en_p : process(rd_state, rx_axis_fifo_tready)
begin
case rd_state is
when WAIT_s =>
rd_en <= '0';
when QUEUE1_s =>
rd_en <= '1';
when QUEUE2_s =>
rd_en <= '1';
when QUEUE3_s =>
rd_en <= '1';
when QUEUE_SOF_s =>
rd_en <= '1';
when others =>
rd_en <= rx_axis_fifo_tready;
end case;
end process rd_en_p;
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
-- When the current frame is done, and if there is no frame in the FIFO, then
-- the FIFO must wait until a new frame is written in. This requires the read
-- address to be moved back to where the new frame will be written. The
-- pipeline is then reloaded using the QUEUE states.
p_rd_addr_reload : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_addr_reload <= '0';
else
if rd_state = EOF_s and rd_nxt_state = WAIT_s then
rd_addr_reload <= '1';
else
rd_addr_reload <= '0';
end if;
end if;
end if;
end process p_rd_addr_reload;
-- Data is available if there is at least one frame stored in the FIFO.
p_rd_avail : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
frame_in_fifo <= '0';
else
if rd_frames /= (rd_frames'range => '0') then
frame_in_fifo <= '1';
else
frame_in_fifo <= '0';
end if;
end if;
end if;
end process p_rd_avail;
-- When a frame has been stored we need to synchronize that event to the
-- read clock domain for frame count store.
resync_wr_store_frame_tog : temac_10_100_1000_sync_block
port map (
clk => rx_fifo_aclk,
data_in => wr_store_frame_tog,
data_out => rd_store_frame_sync
);
p_delay_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
rd_store_frame_delay <= rd_store_frame_sync;
end if;
end process p_delay_rd_store;
-- Edge detect of the resynchronized frame count. This creates a pulse
-- when a new frame has been stored.
p_sync_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_store_frame <= '0';
else
-- Edge detector
if (rd_store_frame_delay xor rd_store_frame_sync) = '1' then
rd_store_frame <= '1';
else
rd_store_frame <= '0';
end if;
end if;
end if;
end process p_sync_rd_store;
-- This creates a pulse when a new frame has begun to be output.
p_rd_pull_frame : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_pull_frame <= '0';
else
if rd_state = SOF_s and rd_nxt_state /= SOF_s then
rd_pull_frame <= '1';
elsif rd_state = QUEUE_SOF_s and rd_nxt_state /= QUEUE_SOF_s then
rd_pull_frame <= '1';
else
rd_pull_frame <= '0';
end if;
end if;
end if;
end process p_rd_pull_frame;
-- Up/down counter to monitor the number of frames stored within the FIFO.
-- Note:
-- * increments at the end of a frame write cycle
-- * decrements at the beginning of a frame read cycle
p_rd_frames : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_frames <= (others => '0');
else
-- A frame is written to the FIFO in this cycle, and no frame is being
-- read out on the same cycle.
if rd_store_frame = '1' and rd_pull_frame = '0' then
rd_frames <= rd_frames + 1;
-- A frame is being read out on this cycle and no frame is being
-- written on the same cycle.
elsif rd_store_frame = '0' and rd_pull_frame = '1' then
rd_frames <= rd_frames - 1;
end if;
end if;
end if;
end process p_rd_frames;
------------------------------------------------------------------------------
-- Write state machines and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are IDLE, FRAME, GF, BF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_state <= IDLE_s;
else
wr_state <= wr_nxt_state;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinatorial.
next_wrs_p : process(wr_state, wr_dv_pipe(1), wr_gf, wr_bf, wr_fifo_full)
begin
case wr_state is
when IDLE_s =>
-- There is data in incoming pipeline when dv_pipe(1) goes high.
if wr_dv_pipe(1) = '1' then
wr_nxt_state <= FRAME_s;
else
wr_nxt_state <= IDLE_s;
end if;
when FRAME_s =>
-- If FIFO is full then go to overflow state.
-- If the good or bad flag is detected, then the end of the frame
-- has been reached and the gf or bf state is visited before idle.
-- Otherwise remain in frame state while data is written to FIFO.
if wr_fifo_full = '1' then
wr_nxt_state <= OVFLOW_s;
elsif wr_gf = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf = '1' then
wr_nxt_state <= BF_s;
else
wr_nxt_state <= FRAME_s;
end if;
when GF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when BF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when OVFLOW_s =>
-- Wait until the good or bad flag received.
if wr_gf = '1' or wr_bf = '1' then
wr_nxt_state <= IDLE_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= IDLE_s;
end case;
end process next_wrs_p;
-- Decode control signals, combinatorial.
-- wr_en is used to enable the BRAM write and loading of the input pipeline.
wr_en <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- The upper and lower signals are used to distinguish between the upper and
-- lower BRAMs.
wr_en_l <= wr_en and not(wr_addr(11));
wr_en_u <= wr_en and wr_addr(11);
wr_en_l_bram(0) <= wr_en_l;
wr_en_u_bram(0) <= wr_en_u;
-- Increment the write address when we are receiving valid frame data.
wr_addr_inc <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- If the FIFO overflows or a frame is to be dropped, we need to move the
-- write address back to the start of the frame. This allows the data to be
-- overwritten.
wr_addr_reload <= '1' when wr_state = BF_s or wr_state = OVFLOW_s else '0';
-- The start address is saved when in the idle state.
wr_start_addr_load <= '1' when wr_state = IDLE_s else '0';
-- We need to know when a frame is stored, in order to increment the count of
-- frames stored in the FIFO.
p_wr_store_tog : process (rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if wr_state = GF_s then
wr_store_frame_tog <= not wr_store_frame_tog;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when data is being written into the FIFO.
wr_addr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_addr <= (others => '0');
else
if wr_addr_reload = '1' then
wr_addr <= wr_start_addr;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process wr_addr_p;
-- Store the start address.
wr_staddr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_start_addr <= (others => '0');
else
if wr_start_addr_load = '1' then
wr_start_addr <= wr_addr;
end if;
end if;
end if;
end process wr_staddr_p;
-- Read address is incremented when data is being read from the FIFO.
rd_addr_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_addr <= (others => '0');
else
if rd_addr_reload = '1' then
rd_addr <= rd_addr - 3;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process rd_addr_p;
-- Which BRAM is read from is dependant on the upper bit of the address
-- space. This needs to be registered to give the correct timing.
rd_bram_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_bram_u <= '0';
rd_bram_u_reg <= '0';
elsif rd_addr_inc = '1' then
rd_bram_u <= rd_addr(11);
rd_bram_u_reg <= rd_bram_u;
end if;
end if;
end process rd_bram_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_data_pipe(0) <= rx_axis_mac_tdata;
wr_data_pipe(1) <= wr_data_pipe(0);
wr_data_bram <= wr_data_pipe(1);
end if;
end process reg_din_p;
-- The valid input enables BRAM write and is a condition for other signals.
reg_dv_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_dv_pipe(0) <= rx_axis_mac_tvalid;
wr_dv_pipe(1) <= wr_dv_pipe(0);
wr_dv_pipe(2) <= wr_dv_pipe(1);
end if;
end process reg_dv_p;
-- End of frame flag set when tlast and tvalid are asserted together.
reg_eof_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_eof_bram_pipe(0) <= rx_axis_mac_tlast;
wr_eof_bram_pipe(1) <= wr_eof_bram_pipe(0);
wr_eof_bram <= wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_eof_p;
-- Upon arrival of EOF flag, the frame is good if tuser signal
-- is low, and bad if tuser signal is high.
reg_gf_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_gfbf_pipe(0) <= rx_axis_mac_tuser;
wr_gfbf_pipe(1) <= wr_gfbf_pipe(0);
wr_gf <= (not wr_gfbf_pipe(1)) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
wr_bf <= wr_gfbf_pipe(1) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_gf_p;
-- The MAC's RX path cannot be helpd off, so the tready signal is always high.
reg_ready_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if (rx_mac_reset = '1') then
rx_axis_mac_tready <= '0';
else
rx_axis_mac_tready <= '1';
end if;
end if;
end process reg_ready_p;
-- Register data outputs from BRAM.
-- No resets to allow for SRL16 target.
reg_dout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_data_pipe_u <= rd_data_bram_u;
rd_data_pipe_l <= rd_data_bram_l;
if rd_bram_u_reg = '1' then
rd_data_pipe <= rd_data_pipe_u;
else
rd_data_pipe <= rd_data_pipe_l;
end if;
rx_axis_fifo_tdata <= rd_data_pipe;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
if rd_bram_u = '1' then
rd_eof <= rd_eof_bram_u(0);
else
rd_eof <= rd_eof_bram_l(0);
end if;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Overflow functionality
------------------------------------------------------------------------------
-- to minimise the number of read address updates the bottom 6 bits of the
-- read address are not passed across and the write domain will only sample
-- them when bits 5 and 4 of the read address transition from 01 to 10.
-- Since this is for full detection this just means that if the read stops
-- the write will hit full up to 64 locations early
-- need to use two bits and look for an increment transition as reload can cause
-- a decrement on this boundary (decrement is only by 3 so above bit 2 should be safe)
p_rd_addr_tog : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
old_rd_addr <= (others => '0');
update_addr_tog <= '0';
else
old_rd_addr <= std_logic_vector(rd_addr(5 downto 4));
if rd_addr(5 downto 4) = "10" and old_rd_addr = "01" then
update_addr_tog <= not update_addr_tog;
end if;
end if;
end if;
end process p_rd_addr_tog;
sync_rd_addr_tog: temac_10_100_1000_sync_block
port map (
clk => rx_mac_aclk,
data_in => update_addr_tog,
data_out => update_addr_tog_sync
);
-- Obtain the difference between write and read pointers.
p_sample_addr : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
update_addr_tog_sync_reg <= '0';
wr_rd_addr <= (others => '0');
else
update_addr_tog_sync_reg <= update_addr_tog_sync;
if update_addr_tog_sync_reg /= update_addr_tog_sync then
wr_rd_addr <= rd_addr(11 downto 6) & "000000";
end if;
end if;
end if;
end process p_sample_addr;
wr_addr_diff_in <= ('0' & wr_rd_addr) - ('0' & wr_addr);
-- Obtain the difference between write and read pointers.
p_addr_diff : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_addr_diff <= (others => '0');
else
wr_addr_diff <= wr_addr_diff_in(11 downto 0);
end if;
end if;
end process p_addr_diff;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_full <= '0';
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1';
else
wr_fifo_full <= '0';
end if;
end if;
end if;
end process p_wr_full;
-- Decode the overflow indicator output.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_wr_fifo_status : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_status <= "0000";
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000";
else
wr_fifo_status(3) <= not wr_addr_diff(11);
wr_fifo_status(2) <= not wr_addr_diff(10);
wr_fifo_status(1) <= not wr_addr_diff(9);
wr_fifo_status(0) <= not wr_addr_diff(8);
end if;
end if;
end if;
end process p_wr_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
wr_addr_slv <= std_logic_vector(wr_addr(10 downto 0));
rd_addr_slv <= std_logic_vector(rd_addr(10 downto 0));
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram;
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
-- Block RAM for lower address space (rx_addr(11) = '0')
rd_eof_bram_l(0) <= rd_eof_data_bram_l(8);
rd_data_bram_l <= rd_eof_data_bram_l(7 downto 0);
ramgen_l : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => doa_l_unused,
DOB => rd_eof_data_bram_l,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => rx_mac_aclk,
CLKB => rx_fifo_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => rx_mac_reset,
RSTB => rx_fifo_reset,
WEA => wr_en_l_bram,
WEB => GND
);
-- Block RAM for lower address space (rx_addr(11) = '0')
rd_eof_bram_u(0) <= rd_eof_data_bram_u(8);
rd_data_bram_u <= rd_eof_data_bram_u(7 downto 0);
ramgen_u : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => doa_u_unused,
DOB => rd_eof_data_bram_u,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => rx_mac_aclk,
CLKB => rx_fifo_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => rx_mac_reset,
RSTB => rx_fifo_reset,
WEA => wr_en_u_bram,
WEB => GND
);
end RTL;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4088/EPROC_IN2_DEC8b10b.vhd
|
2
|
6320
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN2 module
entity EPROC_IN2_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2_DEC8b10b;
architecture Behavioral of EPROC_IN2_DEC8b10b is
signal EDATAbitstreamSREG : std_logic_vector (11 downto 0) := (others=>'0'); -- 12 bit (2 x 5 = 10, plus 2 more)
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal word10b, word10b_s : std_logic_vector (9 downto 0) := (others=>'0');
signal isk : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits_or, word10b_align_rdy_r,
word10b_rdy, word10b_rdy_s, word10b_rdy_s1 : std_logic;
signal align_select : std_logic := '0';
signal comma_valid_bits : std_logic_vector (1 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(11 downto 2);
end if;
end process;
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 1 generate -- 1 10bit-word per alignment, 2 possible alignments
--word10b_align_array(I) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 10 bit word, alligned to bit I
word10b_align_array(I) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 1 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits(I) <= '1' when (word10b_align_array(I) = COMMAp or word10b_align_array(I) = COMMAn) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
--
word10b_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= '0';
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select <= (not comma_valid_bits(0)) and comma_valid_bits(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_rdy <= word10b_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when '0' => -- bit0 word got comma => align to bit0
word10b <= word10b_align_array_r(0);
when '1' => -- bit1 word got comma => align to bit1
word10b <= word10b_align_array_r(1);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_s <= word10b;
word10b_rdy_s <= word10b_rdy;
end if;
end process;
--
word10b_rdy_s1 <= word10b_rdy_s;
----
-------------------------------------------------------------------------------------------
-- 1 8b word get aligned and ready as 10 bit word (data and data code)
-------------------------------------------------------------------------------------------
EPROC_IN2_ALIGN_BLOCK_inst: entity work.EPROC_IN2_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_s,
bytes_rdy => word10b_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4371/EPROC_IN2_DEC8b10b.vhd
|
2
|
6320
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 05/19/2014
--! Module Name: EPROC_IN2_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN2 module
entity EPROC_IN2_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN2_DEC8b10b;
architecture Behavioral of EPROC_IN2_DEC8b10b is
signal EDATAbitstreamSREG : std_logic_vector (11 downto 0) := (others=>'0'); -- 12 bit (2 x 5 = 10, plus 2 more)
signal word10b_align_array, word10b_align_array_r : word10b_2array_type;
signal word10b, word10b_s : std_logic_vector (9 downto 0) := (others=>'0');
signal isk : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits_or, word10b_align_rdy_r,
word10b_rdy, word10b_rdy_s, word10b_rdy_s1 : std_logic;
signal align_select : std_logic := '0';
signal comma_valid_bits : std_logic_vector (1 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(11 downto 2);
end if;
end process;
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 1 generate -- 1 10bit-word per alignment, 2 possible alignments
--word10b_align_array(I) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 10 bit word, alligned to bit I
word10b_align_array(I) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 10 bit word, alligned to bit I
end generate input_map;
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 1 generate -- 1 10bit-word per alignment, comma is valid if two first words have comma...
comma_valid_bits(I) <= '1' when (word10b_align_array(I) = COMMAp or word10b_align_array(I) = COMMAn) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_align_array_r <= word10b_align_array;
end if;
end process;
--
word10b_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= '0';
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select <= (not comma_valid_bits(0)) and comma_valid_bits(1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_rdy <= word10b_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when '0' => -- bit0 word got comma => align to bit0
word10b <= word10b_align_array_r(0);
when '1' => -- bit1 word got comma => align to bit1
word10b <= word10b_align_array_r(1);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_s <= word10b;
word10b_rdy_s <= word10b_rdy;
end if;
end process;
--
word10b_rdy_s1 <= word10b_rdy_s;
----
-------------------------------------------------------------------------------------------
-- 1 8b word get aligned and ready as 10 bit word (data and data code)
-------------------------------------------------------------------------------------------
EPROC_IN2_ALIGN_BLOCK_inst: entity work.EPROC_IN2_ALIGN_BLOCK
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_s,
bytes_rdy => word10b_rdy_s1,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
gpl-3.0
|
rkrajnc/minimig-mist
|
rtl/tg68k/TG68K.vhd
|
1
|
25186
|
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- Copyright (c) 2009-2011 Tobias Gubener --
-- Subdesign fAMpIGA by TobiFlex --
-- --
-- This is the TOP-Level for TG68KdotC_Kernel to generate 68K Bus signals --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68K is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
vpa : in std_logic:='1';
ein : in std_logic:='1';
addr : buffer std_logic_vector(31 downto 0);
data_read : in std_logic_vector(15 downto 0);
data_write : buffer std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
e : out std_logic;
vma : buffer std_logic:='1';
wrd : out std_logic;
ena7RDreg : in std_logic:='1';
ena7WRreg : in std_logic:='1';
enaWRreg : in std_logic:='1';
fromram : in std_logic_vector(15 downto 0);
ramready : in std_logic:='0';
cpu : in std_logic_vector(1 downto 0);
fastramcfg : in std_logic_vector(2 downto 0);
eth_en : in std_logic:='0';
sel_eth : buffer std_logic;
frometh : in std_logic_vector(15 downto 0);
ethready : in std_logic;
turbochipram : in std_logic;
turbokick : in std_logic;
cache_inhibit : out std_logic;
ovr : in std_logic;
ramaddr : out std_logic_vector(31 downto 0);
cpustate : out std_logic_vector(5 downto 0);
nResetOut : buffer std_logic;
skipFetch : buffer std_logic;
cpuDMA : buffer std_logic;
ramlds : out std_logic;
ramuds : out std_logic;
CACR_out : buffer std_logic_vector(3 downto 0);
VBR_out : buffer std_logic_vector(31 downto 0)
);
end TG68K;
ARCHITECTURE logic OF TG68K IS
COMPONENT TG68KdotC_Kernel
generic(
SR_Read : integer := 2; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe : integer := 2; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode : integer := 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
BitField : integer := 2 --0=>no, 1=>yes, 2=>switchable with CPU(1)
);
port(
clk : in std_logic;
nReset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
IPL_autovector : in std_logic:='0';
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only same parts - yet)
addr_out : buffer std_logic_vector(31 downto 0);
data_write : buffer std_logic_vector(15 downto 0);
nWr : out std_logic;
nUDS, nLDS : out std_logic;
nResetOut : out std_logic;
FC : out std_logic_vector(2 downto 0);
busstate : out std_logic_vector(1 downto 0); -- 00-> fetch code 10->read data 11->write data 01->no memaccess
skipFetch : out std_logic;
regin_out : buffer std_logic_vector(31 downto 0);
CACR_out : buffer std_logic_vector(3 downto 0);
VBR_out : buffer std_logic_vector(31 downto 0)
);
END COMPONENT;
SIGNAL cpuaddr : std_logic_vector(31 downto 0);
SIGNAL r_data : std_logic_vector(15 downto 0);
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL vpad : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
SIGNAL vmaena : std_logic;
SIGNAL state_ena : std_logic;
SIGNAL eind : std_logic;
SIGNAL eindd : std_logic;
SIGNAL sel_autoconfig : std_logic;
SIGNAL autoconfig_out : std_logic_vector(1 downto 0); -- We use this as a counter since we have two cards to configure
SIGNAL autoconfig_data : std_logic_vector(3 downto 0); -- Zorro II RAM
SIGNAL autoconfig_data2 : std_logic_vector(3 downto 0); -- Zorro III RAM
SIGNAL autoconfig_data3 : std_logic_vector(3 downto 0); -- Zorro III ethernet
SIGNAL sel_fast : std_logic;
SIGNAL sel_chipram : std_logic;
SIGNAL turbochip_ena : std_logic := '0';
SIGNAL turbochip_d : std_logic := '0';
SIGNAL turbokick_d : std_logic := '0';
SIGNAL slower : std_logic_vector(3 downto 0);
TYPE sync_states IS (sync0, sync1, sync2, sync3, sync4, sync5, sync6, sync7, sync8, sync9);
SIGNAL sync_state : sync_states;
SIGNAL datatg68 : std_logic_vector(15 downto 0);
SIGNAL ramcs : std_logic;
SIGNAL z2ram_ena : std_logic;
SIGNAL z3ram_base : std_logic_vector(7 downto 0);
SIGNAL z3ram_ena : std_logic;
SIGNAL eth_base : std_logic_vector(7 downto 0);
SIGNAL eth_cfgd : std_logic;
SIGNAL sel_z2ram : std_logic;
SIGNAL sel_z3ram : std_logic;
SIGNAL sel_kickram : std_logic;
--SIGNAL sel_eth : std_logic;
SIGNAL NMI_vector : std_logic_vector(15 downto 0);
SIGNAL NMI_addr : std_logic_vector(31 downto 0);
SIGNAL NMI_active : std_logic;
SIGNAL sel_interrupt : std_logic;
SIGNAL cpuaddr_w : std_logic_vector(31 downto 0);
SIGNAL data_write_w : std_logic_vector(15 downto 0);
SIGNAL state_w : std_logic_vector(1 downto 0);
SIGNAL wr_w : std_logic;
SIGNAL uds_in_w : std_logic;
SIGNAL lds_in_w : std_logic;
SIGNAL nResetOut_w : std_logic;
SIGNAL skipFetch_w : std_logic;
SIGNAL CACR_out_w : std_logic_vector(3 downto 0);
SIGNAL VBR_out_w : std_logic_vector(31 downto 0);
BEGIN
-- NMI
PROCESS(clk) BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
NMI_addr <= X"0000007c";
NMI_active <= '0';
ELSE
NMI_addr <= VBR_out + X"0000007c";
IF (IPL="000") THEN
NMI_active <= '1';
ELSIF (cpuaddr(23 downto 1) = "1111111111111111111111") THEN
NMI_active <= '0';
END IF;
END IF;
END IF;
END PROCESS;
NMI_vector <= X"000c" WHEN cpuaddr(1)='1' ELSE X"00a0"; -- 16-bit bus!
wrd <= wr;
addr <= cpuaddr;
datatg68 <= NMI_vector WHEN sel_interrupt='1' ELSE
fromram WHEN sel_fast='1'
--ELSE frometh WHEN sel_eth='1'
ELSE autoconfig_data&r_data(11 downto 0) WHEN sel_autoconfig='1' AND autoconfig_out="01" -- Zorro II RAM autoconfig
ELSE autoconfig_data2&r_data(11 downto 0) WHEN sel_autoconfig='1' AND autoconfig_out="10" -- Zorro III RAM autoconfig
--ELSE autoconfig_data3&r_data(11 downto 0) WHEN sel_autoconfig='1' AND autoconfig_out="11" -- Zorro III ethernet autoconfig
ELSE r_data;
sel_autoconfig <= '1' WHEN fastramcfg(2 downto 0)/="000" AND cpuaddr(23 downto 19)="11101" AND autoconfig_out/="00" ELSE '0'; --$E80000 - $EFFFFF
sel_z3ram <= '1' WHEN (cpuaddr(31 downto 24)=z3ram_base) AND z3ram_ena='1' ELSE '0';
sel_z2ram <= '1' WHEN (cpuaddr(31 downto 24) = "00000000") AND ((cpuaddr(23 downto 21) = "001") OR (cpuaddr(23 downto 21) = "010") OR (cpuaddr(23 downto 21) = "011") OR (cpuaddr(23 downto 21) = "100")) AND z2ram_ena='1' ELSE '0';
--sel_eth <= '1' WHEN (cpuaddr(31 downto 24) = eth_base) AND eth_cfgd='1' ELSE '0';
sel_chipram <= '1' WHEN (cpuaddr(31 downto 24) = "00000000") AND (cpuaddr(23 downto 21)="000") AND turbochip_ena='1' AND turbochip_d='1' ELSE '0'; --$000000 - $1FFFFF
--sel_chipram <= '1' WHEN sel_z3ram/='1' AND turbochip_ena='1' AND turbochip_d='1' AND (cpuaddr(23 downto 21)="000") ELSE '0'; --$000000 - $1FFFFF
sel_kickram <= '1' WHEN (cpuaddr(31 downto 24) = "00000000") AND ((cpuaddr(23 downto 19)="11111") OR (cpuaddr(23 downto 19)="11100")) AND turbochip_ena='1' AND turbokick_d='1' ELSE '0'; -- $f8xxxx, e0xxxx
--sel_kickram <= '1' WHEN sel_z3ram/='1' AND turbochip_ena='1' AND turbokick_d='1' AND (cpuaddr(23 downto 19)="11111") ELSE '0'; -- $f8xxxx
sel_interrupt <= '1' WHEN (cpuaddr(31 downto 2) = NMI_addr(31 downto 2)) AND wr='0' ELSE '0';
sel_fast <= '1' WHEN state/="01" AND (
sel_z2ram='1'
OR sel_z3ram='1'
OR sel_chipram='1'
OR sel_kickram='1'
) ELSE '0';
--sel_fast <= '1' when state/="01" AND (
-- cpuaddr(23 downto 21)="001"
-- OR cpuaddr(23 downto 21)="010"
-- OR cpuaddr(23 downto 21)="011"
-- OR cpuaddr(23 downto 21)="100"
-- OR sel_z3ram='1'
-- OR sel_chipram='1'
-- OR sel_kickram='1'
-- ) ELSE '0'; --$200000 - $9FFFFF
cache_inhibit <= '1' WHEN sel_chipram='1' OR sel_kickram='1' ELSE '0';
--ramcs <= (NOT sel_fast AND NOT sel_eth) or slower(0);-- OR (state(0) AND NOT state(1));
ramcs <= (NOT sel_fast) or slower(0);-- OR (state(0) AND NOT state(1));
cpuDMA <= sel_fast;
cpustate <= clkena&slower(1 downto 0)&ramcs&state;
ramlds <= lds_in;
ramuds <= uds_in;
ramaddr(31 downto 25) <= "0000000";
ramaddr(24) <= sel_z3ram; -- Remap the Zorro III RAM to 0x1000000
ramaddr(23 downto 21)
<= "100" WHEN sel_z2ram&cpuaddr(23 downto 21)="1001" -- 2 -> 8
ELSE "101" WHEN sel_z2ram&cpuaddr(23 downto 21)="1010" -- 4 -> A
ELSE "110" WHEN sel_z2ram&cpuaddr(23 downto 21)="1011" -- 6 -> C
ELSE "111" WHEN sel_z2ram&cpuaddr(23 downto 21)="1100" -- 8 -> E
ELSE "001" WHEN sel_kickram='1'
ELSE cpuaddr(23 downto 21); -- pass through others
ramaddr(20 downto 19)
<= "11" WHEN sel_kickram='1' AND cpuaddr(23 downto 19)="11111"
ELSE "00" WHEN sel_kickram='1' AND cpuaddr(23 downto 19)="11100"
ELSE cpuaddr(20 downto 19);
ramaddr(18 downto 0) <= cpuaddr(18 downto 0);
--ramaddr(23 downto 21) <= "100" when sel_z3ram&cpuaddr(23 downto 21)="0001" -- 2 -> 8
-- else "101" when sel_z3ram&cpuaddr(23 downto 21)="0010" -- 4 -> A
-- else "110" when sel_z3ram&cpuaddr(23 downto 21)="0011" -- 6 -> C
-- else "111" when sel_z3ram&cpuaddr(23 downto 21)="0100" -- 8 -> E
-- else "001" when sel_kickram='1'
-- else cpuaddr(23 downto 21); -- pass through others
--ramaddr(20 downto 19) <= "11" when sel_kickram='1'
-- else cpuaddr(20 downto 19);
--ramaddr(18 downto 0) <= cpuaddr(18 downto 0);
pf68K_Kernel_inst: TG68KdotC_Kernel
generic map (
SR_Read => 2, -- 0=>user, 1=>privileged, 2=>switchable with CPU(0)
VBR_Stackframe => 2, -- 0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
extAddr_Mode => 2, -- 0=>no, 1=>yes, 2=>switchable with CPU(1)
MUL_Mode => 2, -- 0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
DIV_Mode => 2 -- 0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
)
PORT MAP (
clk => clk, -- : in std_logic;
nReset => reset, -- : in std_logic:='1'; --low active
clkena_in => clkena, -- : in std_logic:='1';
data_in => datatg68, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0):="111";
IPL_autovector => '1', -- : in std_logic:='0';
CPU => cpu,
regin_out => open, -- : out std_logic_vector(31 downto 0);
addr_out => cpuaddr, -- : buffer std_logic_vector(31 downto 0);
data_write => data_write, -- : out std_logic_vector(15 downto 0);
busstate => state, -- : buffer std_logic_vector(1 downto 0);
nWr => wr, -- : out std_logic;
nUDS => uds_in,
nLDS => lds_in, -- : out std_logic;
nResetOut => nResetOut,
skipFetch => skipFetch, -- : out std_logic
CACR_out => CACR_out,
VBR_out => VBR_out
--addr_out => cpuaddr_w, -- : buffer std_logic_vector(31 downto 0);
--data_write => data_write_w, -- : out std_logic_vector(15 downto 0);
--busstate => state_w, -- : buffer std_logic_vector(1 downto 0);
--nWr => wr_w, -- : out std_logic;
--nUDS => uds_in_w,
--nLDS => lds_in_w, -- : out std_logic;
--nResetOut => nResetOut_w,
--skipFetch => skipFetch_w, -- : out std_logic
--CACR_out => CACR_out_w,
--VBR_out => VBR_out_w
);
--PROCESS (clk) BEGIN
-- IF rising_edge(clk) THEN
-- IF reset='0' THEN
-- cpuaddr <= X"00000000";
-- data_write <= X"0000";
-- state <= "01";
-- wr <= '1';
-- uds_in <= '1';
-- lds_in <= '1';
-- nResetOut <= '1';
-- skipFetch <= '0';
-- CACR_out <= "0000";
-- VBR_out <= X"00000000";
-- ELSE
-- cpuaddr <= cpuaddr_w;
-- data_write <= data_write_w;
-- state <= state_w;
-- wr <= wr_w;
-- uds_in <= uds_in_w;
-- lds_in <= lds_in_w;
-- nResetOut <= nResetOut_w;
-- skipFetch <= skipFetch_w;
-- CACR_out <= CACR_out_w;
-- VBR_out <= VBR_out_w;
-- END IF;
-- END IF;
--END PROCESS;
PROCESS(clk,turbochipram, turbokick) BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
turbochip_d <= '0';
turbokick_d <= '0';
ELSIF state="01" THEN -- No mem access, so safe to switch chipram access mode
turbochip_d<=turbochipram;
turbokick_d<=turbokick;
END IF;
END IF;
END PROCESS;
PROCESS (clk) BEGIN
-- Zorro II RAM (Up to 8 meg at 0x200000)
autoconfig_data <= "1111";
IF fastramcfg/="000" THEN
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data <= "1110"; -- Zorro-II card, add mem, no ROM
WHEN "000001" => --autoconfig_data <= "0111"; -- 4MB
CASE fastramcfg(1 downto 0) IS
WHEN "01" => autoconfig_data <= "0110"; -- 2MB
WHEN "10" => autoconfig_data <= "0111"; -- 4MB
WHEN OTHERS => autoconfig_data <= "0000"; -- 8MB
END CASE;
WHEN "001000" => autoconfig_data <= "1110"; -- Manufacturer ID: 0x139c
WHEN "001001" => autoconfig_data <= "1100";
WHEN "001010" => autoconfig_data <= "0110";
WHEN "001011" => autoconfig_data <= "0011";
WHEN "010011" => autoconfig_data <= "1110"; --serial=1
WHEN OTHERS => null;
END CASE;
END IF;
-- Zorro III RAM (Up to 16 meg, address assigned by ROM)
autoconfig_data2 <= "1111";
IF fastramcfg(2)='1' THEN -- Zorro III RAM
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data2 <= "1010"; -- Zorro-III card, add mem, no ROM
WHEN "000001" => autoconfig_data2 <= "0000"; -- 8MB (extended to 16 in reg 08)
WHEN "000010" => autoconfig_data2 <= "1110"; -- ProductID=0x10 (only setting upper nibble)
WHEN "000100" => autoconfig_data2 <= "0000"; -- Memory card, not silenceable, Extended size (16 meg), reserved.
WHEN "000101" => autoconfig_data2 <= "1111"; -- 0000 - logical size matches physical size TODO change this to 0001, so it is autosized by the OS, WHEN it will be 24MB.
WHEN "001000" => autoconfig_data2 <= "1110"; -- Manufacturer ID: 0x139c
WHEN "001001" => autoconfig_data2 <= "1100";
WHEN "001010" => autoconfig_data2 <= "0110";
WHEN "001011" => autoconfig_data2 <= "0011";
WHEN "010011" => autoconfig_data2 <= "1101"; -- serial=2
WHEN OTHERS => null;
END CASE;
END IF;
-- Zorro III ethernet
autoconfig_data3 <= "1111";
IF eth_en='1' THEN
CASE cpuaddr(6 downto 1) IS
WHEN "000000" => autoconfig_data3 <= "1000"; -- 00H: Zorro-III card, no link, no ROM
WHEN "000001" => autoconfig_data3 <= "0001"; -- 00L: next board not related, size 64K
WHEN "000010" => autoconfig_data3 <= "1101"; -- 04H: ProductID=0x20 (only setting upper nibble)
WHEN "000100" => autoconfig_data3 <= "1110"; -- 08H: Not memory, silenceable, normal size, Zorro III
WHEN "000101" => autoconfig_data3 <= "1101"; -- 08L: Logical size 64K
WHEN "001000" => autoconfig_data3 <= "1110"; -- Manufacturer ID: 0x139c
WHEN "001001" => autoconfig_data3 <= "1100";
WHEN "001010" => autoconfig_data3 <= "0110";
WHEN "001011" => autoconfig_data3 <= "0011";
WHEN "010011" => autoconfig_data3 <= "1100"; -- serial=2
WHEN OTHERS => null;
END CASE;
END IF;
IF rising_edge(clk) THEN
IF reset='0' THEN
autoconfig_out <= "01"; --autoconfig on
turbochip_ena <= '0'; -- disable turbo_chipram until we know kickstart's running...
z2ram_ena <='0';
z3ram_ena <='0';
z3ram_base<=X"01";
--eth_cfgd <='0';
--eth_base<=X"02";
ELSIF enaWRreg='1' THEN
IF sel_autoconfig='1' AND state="11"AND uds_in='0' AND clkena='1' THEN
CASE cpuaddr(6 downto 1) IS
WHEN "100100" => -- Register 0x48 - config
IF autoconfig_out="01" THEN
z2ram_ena <= '1';
autoconfig_out<=fastramcfg(2)&'0';
END IF;
turbochip_ena <= '1'; -- enable turbo_chipram after autoconfig has been done...
-- FIXME - this is a hack to allow ROM overlay to work.
WHEN "100010" => -- Register 0x44, assign base address to ZIII RAM.
-- We ought to take 16 bits here, but for now we take liberties and use a single byte.
IF autoconfig_out="10" THEN
z3ram_base<=data_write(15 downto 8);
z3ram_ena <='1';
-- autoconfig_out<= eth_en & eth_en;
-- ELSIF autoconfig_out="11" THEN
-- eth_base <= data_write(15 downto 8);
-- eth_cfgd <= '1';
autoconfig_out <= "00";
END IF;
WHEN others =>
null;
END CASE;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk) BEGIN
IF rising_edge(clk) THEN
IF reset='0' THEN
vmaena <= '0';
ELSIF ena7RDreg='1' THEN
vmaena <= '0';
IF sync_state=sync5 THEN
e <= '1';
END IF;
IF sync_state=sync9 THEN
e <= '0';
vmaena <= NOT vma;
END IF;
END IF;
END IF;
IF rising_edge(clk) THEN
IF ena7WRreg='1' THEN
eind <= ein;
eindd <= eind;
CASE sync_state IS
WHEN sync0 => sync_state <= sync1;
WHEN sync1 => sync_state <= sync2;
WHEN sync2 => sync_state <= sync3;
WHEN sync3 => sync_state <= sync4;
vma <= vpa;
WHEN sync4 => sync_state <= sync5;
WHEN sync5 => sync_state <= sync6;
WHEN sync6 => sync_state <= sync7;
WHEN sync7 => sync_state <= sync8;
WHEN sync8 => sync_state <= sync9;
WHEN OTHERS => sync_state <= sync0;
vma <= '1';
END CASE;
IF eind='1' AND eindd='0' THEN
sync_state <= sync7;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk, clkena_in, enaWRreg, state, ena7RDreg, clkena_e, ramready) BEGIN
state_ena <= '0';
-- IF clkena_in='1' AND enaWRreg='1' AND (state="01" OR (ena7RDreg='1' AND clkena_e='1') OR ramready='1' OR ethready='1') THEN
IF clkena_in='1' AND enaWRreg='1' AND (state="01" OR (ena7RDreg='1' AND clkena_e='1') OR ramready='1') THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
IF state="01" THEN
state_ena <= '1';
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
slower <= "0111"; -- rokk
-- slower <= "0111";
ELSE
slower(3 downto 0) <= '0'&slower(3 downto 1); -- enaWRreg&slower(3 downto 1);
-- slower(0) <= NOT slower(3) AND NOT slower(2);
END IF;
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e, sel_fast)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= (as_s AND as_e) OR sel_fast;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "00";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF ena7WRreg='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
CASE S_state IS
WHEN "00" => IF state/="01" AND sel_fast='0' THEN
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "01";
END IF;
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
r_data <= data_read;
IF waitm='0' OR (vma='0' AND sync_state=sync9) THEN
S_state <= "11";
ELSE
as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
ELSIF rising_edge(clk) THEN
IF ena7RDreg='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
CASE S_state IS
WHEN "00" =>
cpuIPL <= IPL;
IF sel_fast='0' THEN
IF state/="01" THEN
as_e <= '0';
END IF;
rw_e <= wr;
IF wr='1' THEN
uds_e <= uds_in;
lds_e <= lds_in;
END IF;
END IF;
WHEN "01" =>
as_e <= '0';
rw_e <= wr;
uds_e <= uds_in;
lds_e <= lds_in;
WHEN "10" => rw_e <= wr;
cpuIPL <= IPL;
waitm <= dtack;
WHEN OTHERS => --null;
clkena_e <= '1';
END CASE;
END IF;
END IF;
END PROCESS;
END;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/readout/FIFO2UDP.vhd
|
1
|
18337
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL - Michigan
-- Engineer: Panagiotis Gkountoumis & Reid Pinkham & Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Panagiotis Gkountoumis & Reid Pinkham & Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Changelog:
-- 23.07.2016 Output signal "sending" to hold packet_formation from issuing new
-- packets (Paris)
-- 26.07.2016 Increased the size of the FIFO to 2048 in order to be able to handle
-- jumbo UDP frames. (Paris)
-- 22.08.2016 Re-wrote the main logic into a single state machine to fix the freezing
-- bug. (Reid Pinkham)
-- 26.02.2016 Moved to a global clock domain @125MHz (Paris)
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity FIFO2UDP is
Port (
clk_125 : in std_logic;
destinationIP : in std_logic_vector(31 downto 0);
daq_data_in : in std_logic_vector(15 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
re_out : out std_logic;
control : out std_logic;
UDPDone : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in std_logic_vector(11 downto 0);
reset_DAQ_FIFO : in std_logic;
confReply_packet : in std_logic;
vmmID : in std_logic_vector(2 downto 0);
trigger_out : out std_logic;
count_o : out std_logic_vector(3 downto 0);
faifouki : out std_logic
);
end FIFO2UDP;
architecture Behavioral of FIFO2UDP is
signal count : unsigned(3 downto 0) := x"0";
signal i : integer := 0;
signal count_length : unsigned(15 downto 0) := x"0000";
signal daq_fifo_re : std_logic := '0';
signal fifo_empty_UDP : std_logic := '0';
signal fifo_full_UDP : std_logic := '0';
signal prog_fifo_empty : std_logic := '0';
signal daq_out : std_logic_vector(255 downto 0);
signal data_out : std_logic_vector(7 downto 0) := x"00";
signal data_out_valid : std_logic := '0';
signal packet_length : unsigned(15 downto 0) := x"0000";
signal data_out_last : std_logic := '0';
signal end_packet_synced : std_logic := '0';
signal udp_tx_start_int : std_logic := '0';
signal wr_en_int : std_logic := '0';
signal fifo_len_wr_en : std_logic := '0';
signal fifo_len_rd_en : std_logic := '0';
signal packet_len_r : std_logic_vector(11 downto 0);
signal fifo_empty_len : std_logic;
signal state : std_logic := '0';
signal is_trailer : integer := 0;
signal temp_buffer : std_logic_vector(63 downto 0) := (others=> '0');
signal daq_data_out : std_logic_vector(7 downto 0) := x"00";
signal vmmID_i : std_logic_vector(2 downto 0);
signal trigger : std_logic;
signal len_cnt : unsigned(7 downto 0) := "00000000";
signal rst_fifo : std_logic := '0';
-- attribute mark_debug : string;
-- attribute mark_debug of prog_fifo_empty : signal is "true";
-- attribute mark_debug of fifo_empty_UDP : signal is "true";
-- attribute mark_debug of daq_fifo_re : signal is "true";
-- attribute mark_debug of data_out_last : signal is "true";
-- attribute mark_debug of data_out : signal is "true";
-- attribute mark_debug of data_out_valid : signal is "true";
-- attribute mark_debug of udp_tx_data_out_ready : signal is "true";
-- attribute mark_debug of daq_data_out : signal is "true";
-- attribute mark_debug of udp_tx_start : signal is "true";
-- attribute mark_debug of end_packet_synced : signal is "true";
-- attribute mark_debug of i : signal is "true";
-- attribute mark_debug of packet_length : signal is "true";
-- attribute mark_debug of count : signal is "true";
-- attribute mark_debug of count_length : signal is "true";
-- attribute mark_debug of wr_en_int : signal is "true";
-- attribute mark_debug of fifo_full_UDP : signal is "true";
-- attribute mark_debug of fifo_empty_len : signal is "true";
-- attribute mark_debug of wr_en : signal is "true";
-- attribute mark_debug of packet_length_in : signal is "true";
-- attribute mark_debug of vmmID_i : signal is "true";
-- attribute mark_debug of trigger : signal is "true";
-- attribute mark_debug of len_cnt : signal is "true";
-- attribute mark_debug of fifo_len_wr_en : signal is "true";
-- attribute mark_debug of fifo_len_rd_en : signal is "true";
-- attribute mark_debug of packet_len_r : signal is "true";
component readout_fifo is
port(
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component packet_len_fifo
port (
clk : in std_logic;
srst : in std_logic;
din : in std_logic_vector(11 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(11 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
component ila_0
PORT (
clk : in std_logic;
probe0 : in std_logic_vector(255 DOWNTO 0);
probe1 : in std_logic);
end component;
begin
-- process ot trigger ILAs
trigger_proc: process (clk_125, vmmID_i, data_out_last)
begin
if rising_edge(clk_125) then
if (vmmID_i = "000" and data_out_last = '1') then
trigger <= '1';
else
trigger <= '0';
end if;
end if;
end process;
daq_FIFO_instance: readout_fifo
port map(
clk => clk_125,
srst => rst_fifo,
din => daq_data_in,
wr_en => wr_en,
rd_en => daq_fifo_re,
dout => daq_data_out,
full => fifo_full_UDP,
empty => fifo_empty_UDP
);
packet_len_fifo_instance: packet_len_fifo
port map (
clk => clk_125,
srst => rst_fifo,
din => packet_length_in,
wr_en => fifo_len_wr_en,
rd_en => fifo_len_rd_en,
dout => packet_len_r,
full => open,
empty => fifo_empty_len
);
fill_packet_len: process (clk_125, state) -- small state machine to write packet_len to fifo
begin
if rising_edge(clk_125) then
case state is
when '0' => -- idle
if (end_packet_synced = '1') then -- latch the packet_len into the fifo
fifo_len_wr_en <= '1';
state <= '1';
else
state <= '0';
end if;
when '1' => -- st1
if (end_packet_synced = '0') then-- prevent a double latch
state <= '0';
else
state <= '1';
end if;
fifo_len_wr_en <= '0';
when others =>
state <= '0';
end case;
end if;
end process;
process (clk_125, fifo_len_rd_en)
begin
if rising_edge(clk_125) then
if fifo_len_rd_en = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end process;
UDPDone_proc: process (clk_125)
begin
if rising_edge(clk_125) then
if fifo_empty_UDP = '1' and fifo_empty_len = '1' then -- IF Statement to inidcate when packets have been sent
UDPDone <= '1';
else
UDPDone <= '0';
end if;
end if;
end process;
process (clk_125, count, udp_tx_data_out_ready, fifo_empty_UDP, prog_fifo_empty, data_out_valid)
begin
if rising_edge(clk_125) then
if global_reset = '1' then -- IF statement to read from length fifo and initiate a packet send
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
fifo_len_rd_en <= '0';
daq_fifo_re <= '0';
count <= x"0";
else
case count is
when x"0" =>
if fifo_empty_len = '0' then -- Send packets until FIFO is empty
fifo_len_rd_en <= '1';
count <= x"1";
end if;
when x"1" => -- state to allow fifo time to respond
count <= x"2";
fifo_len_rd_en <= '0';
when x"2" =>
packet_length <= resize(unsigned("0000" & packet_len_r) * 2 + 4, 16);
count_length <= resize(unsigned("0000" & packet_len_r) * 2, 16);
fifo_len_rd_en <= '0';
count <= x"3";
when x"3" =>
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
if(confReply_packet = '1')then
udp_txi.hdr.dst_port <= x"E887";
else
udp_txi.hdr.dst_port <= x"1778";
end if;
count <= x"4";
when x"4" =>
udp_tx_start_int <= '1';
udp_txi.hdr.dst_ip_addr <= destinationIP; -- set a generic ip adrress (192.168.0.255)
udp_txi.hdr.src_port <= x"19CB"; -- set src and dst ports
udp_txi.hdr.data_length <= std_logic_vector(packet_length); -- defined to be 16 bits in UDP
daq_fifo_re <= '0';
udp_txi.hdr.checksum <= x"0000";
count <= x"5";
when x"5" =>
if udp_tx_data_out_ready = '1' then
udp_tx_start_int <= '0';
daq_fifo_re <= '1';
count <= x"6";
end if;
when x"6" =>
if udp_tx_data_out_ready = '1' then
count_length <= count_length - 1;
udp_tx_start_int <= '0';
data_out <= daq_data_out;
count <= x"7";
end if;
when x"7" =>
if udp_tx_data_out_ready = '1' then
if count_length = 1 then
daq_fifo_re <= '0';
elsif count_length = 0 then
count <= x"8";
daq_fifo_re <= '0';
else
daq_fifo_re <= '1';
end if;
count_length <= count_length - 1;
udp_tx_start_int <= '0';
data_out_valid <= '1';
control <= '0';
data_out_last <= '0';
data_out <= daq_data_out;
else
daq_fifo_re <= '0';
end if;
when x"8" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= x"9";
end if;
when x"9" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= x"a";
end if;
when x"a" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '0';
data_out <= x"ff";
count <= x"b";
end if;
when x"b" =>
if udp_tx_data_out_ready = '1' then
daq_fifo_re <= '0';
udp_tx_start_int <= '0';
data_out_last <= '1';
data_out <= x"ff";
count <= x"c";
end if;
when x"c" =>
data_out_last <= '0';
data_out_valid <= '0';
data_out <= (others => '0');
udp_tx_start_int <= '0';
count <= x"d";
when x"d" =>
count <= x"0";
count_length <= x"0000";
data_out_last <= '0';
data_out_valid <= '0';
udp_tx_start_int <= '0';
when others =>
count <= x"0";
end case;
end if;
end if;
end process;
vmmID_i <= vmmID; -- assign external signal to internal
udp_tx_start <= udp_tx_start_int;
udp_txi.data.data_out_last <= data_out_last;
udp_txi.data.data_out_valid <= data_out_valid ;
udp_txi.data.data_out <= data_out;
wr_en_int <= wr_en;
end_packet_synced <= end_packet;
rst_fifo <= reset_DAQ_FIFO or global_reset;
trigger_out <= trigger;
count_o <= std_logic_vector(count);
faifouki <= fifo_empty_len;
--ila_daq_send : ila_0
-- port map
-- (
-- clk => clk_125,
-- probe0 => daq_out,
-- probe1 => udp_tx_data_out_ready
-- );
daq_out(0) <= end_packet_synced;
daq_out(1) <= fifo_empty_UDP;
daq_out(2) <= daq_fifo_re;
daq_out(3) <= data_out_valid;
daq_out(4) <= data_out_last;
daq_out(12 downto 5) <= data_out;
daq_out(16 downto 13) <= std_logic_vector(count);
daq_out(38 downto 17) <= (others => '0');
daq_out(39) <= udp_tx_start_int;
daq_out(40) <= '0'; --udp_tx_data_out_ready;
daq_out(48 downto 41) <= daq_data_out;
daq_out(112 downto 49) <= (others => '0');
daq_out(113) <= '0';
daq_out(129 downto 114) <= std_logic_vector(packet_length);
daq_out(145 downto 130) <= std_logic_vector(count_length);
daq_out(157 downto 146) <= packet_len_r;
daq_out(221 downto 158) <= (others => '0');
daq_out(222) <= wr_en_int;
daq_out(223) <= wr_en;
daq_out(235 downto 224) <= packet_length_in;
daq_out(236) <= udp_tx_data_out_ready;
daq_out(237) <= fifo_len_wr_en;
daq_out(238) <= fifo_len_rd_en;
daq_out(239) <= fifo_empty_len;
daq_out(240) <= fifo_full_UDP;
daq_out(243 downto 241) <= vmmID_i;
daq_out(244) <= trigger;
daq_out(252 downto 245) <= std_logic_vector(len_cnt);
daq_out(255 downto 253) <= (others => '0');
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/imports/sgmii_10_100_1000/ipcore_dir/temac_10_100_1000/example_design/temac_10_100_1000_block.vhd
|
2
|
16567
|
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_block.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the block level VHDL design for the Tri-Mode
-- Ethernet MAC Example Design.
--
-- This block level:
--
-- * instantiates all clock enable logic required to operate the
-- TEMAC and its example design;
--
-- * instantiates appropriate PHY interface module (GMII/MII/RGMII)
-- as required based on the user configuration;
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- -----------------------------------------|
-- | BLOCK LEVEL WRAPPER |
-- | |
-- | --------------------- |
-- | | ETHERNET MAC | |
-- | | CORE | |
-- | | | |
-- --|--->| Tx Tx |-------------->|
-- | | AXI PHY | |
-- | | I/F I/F | |
-- | | | |
-- | | | |
-- | | | |
-- | | Rx Rx | |
-- | | AXI PHY | |
-- <-|----| I/F I/F |<--------------|
-- | | | |
-- | --------------------- |
-- | |
-- | clock enable logic |
-- | |
-- -----------------------------------------|
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block level example design.
--------------------------------------------------------------------------------
entity temac_10_100_1000_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end temac_10_100_1000_block;
architecture wrapper of temac_10_100_1000_block is
-----------------------------------------------------------------------------
-- Component Declaration for TEMAC (the Tri-Mode EMAC core).
-----------------------------------------------------------------------------
component temac_10_100_1000
port(
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
gtx_clk : in std_logic;
clk_enable : in std_logic;
-- Receiver Interface
----------------------------
-- rx_axi_clk : in std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- rx_enable : in std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Transmitter Interface
-------------------------------
-- tx_axi_clk : in std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
-- tx_enable : in std_logic;
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Current Speed Indication
---------------------------
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Physical Interface of the core
--------------------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Configuration Vector
-----------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this block level wrapper.
------------------------------------------------------------------------------
attribute keep : string;
signal glbl_rst : std_logic;
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal.
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal.
signal gmii_rx_dv_int : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_er_int : std_logic; -- gmii_rx_er registered in IOBs.
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal txspeedis10100 : std_logic; -- MAC speed setting resampled on the transmitter clock
signal rxspeedis10100 : std_logic; -- MAC speed setting resampled on the receiver clock
signal tx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Tx domain
signal rx_reset_int : std_logic; -- Synchronous reset in the MAC and rgmii Rx domain
signal rx_statistics_vector_int : std_logic_vector(27 downto 0);
signal rx_statistics_valid_int : std_logic;
signal tx_statistics_vector_int : std_logic_vector(31 downto 0);
signal tx_statistics_valid_int : std_logic;
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_addr : std_logic_vector(31 downto 0);
signal bus2ip_cs : std_logic;
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal bus2ip_data : std_logic_vector(31 downto 0);
signal ip2bus_data : std_logic_vector(31 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal tx_axis_mac_tuser_int : std_logic_vector(0 downto 0);
begin
-- assign outputs
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
glbl_rst <= not glbl_rstn;
rx_statistics_vector <= rx_statistics_vector_int;
rx_statistics_valid <= rx_statistics_valid_int;
tx_statistics_vector <= tx_statistics_vector_int;
tx_statistics_valid <= tx_statistics_valid_int;
gmii_tx_en <= gmii_tx_en_int;
gmii_tx_er <= gmii_tx_er_int;
gmii_txd <= gmii_txd_int;
gmii_rx_dv_int <= gmii_rx_dv;
gmii_rx_er_int <= gmii_rx_er;
gmii_rxd_int <= gmii_rxd;
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
trimac_core : temac_10_100_1000
port map (
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
gtx_clk => gtx_clk,
clk_enable => clk_enable,
-- Receiver Interface
-- rx_axi_clk => gtx_clk,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Receiver Statistics
rx_statistics_vector => rx_statistics_vector_int,
rx_statistics_valid => rx_statistics_valid_int,
-- Transmitter Interface
-- tx_axi_clk => gtx_clk,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser_int,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_ifg_delay => tx_ifg_delay,
-- tx_enable => clk_enable,
-- Transmitter Statistics
tx_statistics_vector => tx_statistics_vector_int,
tx_statistics_valid => tx_statistics_valid_int,
-- MAC Control Interface
pause_req => pause_req,
pause_val => pause_val,
-- Current Speed Indication
speedis100 => speedis100,
speedis10100 => speedis10100,
-- Physical Interface of the core
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
-- Configuration Vectors
rx_configuration_vector => rx_configuration_vector,
tx_configuration_vector => tx_configuration_vector);
tx_axis_mac_tuser_int(0) <= tx_axis_mac_tuser;
end wrapper;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/imports/ICMP_RX.vhd
|
1
|
13307
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 03.02.2017
-- Design Name: ICMP Receiver
-- Module Name: ICMP_RX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: Handles simple ICMP RX
--
-- Dependencies:
--
-- Changelog:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity ICMP_RX is
port (
-- ICMP Layer signals
icmp_rx_start : out std_logic; -- indicates receipt of icmp header
icmp_rxo : out icmp_rx_type;
-- system signals
clk : in std_logic;
reset : in std_logic;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
end ICMP_RX;
architecture Behavioral of ICMP_RX is
type rx_state_type is (IDLE, ICMP_HDR, ICMP_PAYLOAD, WAIT_END, ERR);
type rx_event_type is (NO_EVENT, DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- state variables
signal rx_state : rx_state_type;
signal rx_count : unsigned (15 downto 0);
signal icmp_type : std_logic_vector (7 downto 0);
signal icmp_code : std_logic_vector (7 downto 0);
signal icmp_chksum : std_logic_vector (15 downto 0);
signal icmp_ident : std_logic_vector (15 downto 0);
signal icmp_seqNum : std_logic_vector (15 downto 0);
signal icmp_rx_start_reg : std_logic; -- indicates start of user data
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
-- rx control signals
signal next_rx_state : rx_state_type;
signal set_rx_state : std_logic;
signal rx_event : rx_event_type;
signal rx_count_mode : settable_count_mode_type;
signal rx_count_val : unsigned (15 downto 0);
signal set_type : std_logic;
signal set_code : std_logic;
signal set_chksum_h : std_logic;
signal set_chksum_l : std_logic;
signal set_ident_h : std_logic;
signal set_ident_l : std_logic;
signal set_seq_h : std_logic;
signal set_seq_l : std_logic;
signal set_icmp_rx_start : set_clr_type;
signal dataval : std_logic_vector (7 downto 0);
signal set_src_ip : std_logic;
signal set_data_last : std_logic;
-- ICMP datagram header format
--
-- 0 8 16 31
-- --------------------------------------------------------------------------------------------
-- | Type | Code | Checksum |
-- | | | |
-- --------------------------------------------------------------------------------------------
-- | Identifier | Sequence Number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | Payload |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
--
-- Type = 8 and Code = 0 (echo request)
-- Type = 0 and Code = 0 (echo reply)
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
rx_combinatorial : process (
-- input signals
ip_rx, ip_rx_start,
-- state variables
rx_state, rx_count, icmp_type, icmp_code, icmp_chksum, icmp_ident, icmp_seqNum, icmp_rx_start_reg, src_ip_addr,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
set_type, set_code, set_chksum_h, set_chksum_l, set_ident_h, set_ident_l, set_seq_h, set_seq_l, set_data_last,
set_icmp_rx_start, dataval, set_src_ip
)
begin
-- set output followers
icmp_rx_start <= icmp_rx_start_reg;
icmp_rxo.hdr.src_ip_addr <= src_ip_addr;
icmp_rxo.hdr.icmp_type <= icmp_type;
icmp_rxo.hdr.icmp_code <= icmp_code;
icmp_rxo.hdr.icmp_chksum <= icmp_chksum;
icmp_rxo.hdr.icmp_ident <= icmp_ident;
icmp_rxo.hdr.icmp_seqNum <= icmp_seqNum;
-- transfer data upstream if in user data phase
if rx_state = ICMP_PAYLOAD then
icmp_rxo.payload.data_in <= ip_rx.data.data_in;
icmp_rxo.payload.data_in_valid <= ip_rx.data.data_in_valid;
icmp_rxo.payload.data_in_last <= set_data_last;
else
icmp_rxo.payload.data_in <= (others => '0');
icmp_rxo.payload.data_in_valid <= '0';
icmp_rxo.payload.data_in_last <= '0';
end if;
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= RST;
set_type <= '0';
set_code <= '0';
set_chksum_h <= '0';
set_chksum_l <= '0';
set_ident_h <= '0';
set_ident_l <= '0';
set_seq_h <= '0';
set_seq_l <= '0';
set_icmp_rx_start <= CLR;
dataval <= (others => '0');
set_src_ip <= '0';
rx_count_val <= (others => '0');
set_data_last <= '0';
-- determine event (if any)
if ip_rx.data.data_in_valid = '1' then
rx_event <= DATA;
dataval <= ip_rx.data.data_in;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.hdr.protocol = x"01" then -- ICMP protocol
rx_count_mode <= INCR;
set_src_ip <= '1';
set_type <= '1';
next_rx_state <= ICMP_HDR;
set_rx_state <= '1';
else -- non-ICMP protocol - ignore this pkt
next_rx_state <= WAIT_END;
set_rx_state <= '1';
end if;
end case;
when ICMP_HDR =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if rx_count = x"0007" then
rx_count_mode <= SET_VAL;
rx_count_val <= x"0001";
next_rx_state <= ICMP_PAYLOAD;
set_rx_state <= '1';
else
rx_count_mode <= INCR;
end if;
-- handle early frame termination
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
else
case rx_count is
when x"0000" => set_type <= '1'; -- set ICMP type
when x"0001" => set_code <= '1'; -- set ICMP code
when x"0002" => set_chksum_h <= '1'; -- set checksum (1st byte)
when x"0003" => set_chksum_l <= '1'; -- set checksum (2nd byte)
when x"0004" => set_ident_h <= '1'; -- set identifier (1st byte)
when x"0005" => set_ident_l <= '1'; -- set identifier (2nd byte)
when x"0006" => set_seq_h <= '1'; -- set sequence number (1st byte)
when x"0007" => set_seq_l <= '1'; -- set sequence number (2nd byte)
set_icmp_rx_start <= SET; -- indicate frame received
when others => -- ignore other bytes in icmp header
end case;
end if;
end case;
when ICMP_PAYLOAD =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
-- note: data/payload gets transfered upstream as part of "output followers" processing
if ip_rx.data.data_in_last = '1' then -- no early frame termination check
next_rx_state <= IDLE;
set_icmp_rx_start <= CLR;
rx_count_mode <= RST;
set_rx_state <= '1';
set_data_last <= '1';
else
rx_count_mode <= INCR;
set_rx_state <= '0';
end if;
end case;
when ERR =>
if ip_rx.data.data_in_last = '0' then
next_rx_state <= WAIT_END;
set_rx_state <= '1';
else
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if ip_rx.data.data_in_last = '1' then
next_rx_state <= IDLE;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
rx_sequential : process (clk, reset)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"0000";
icmp_type <= (others => '0');
icmp_code <= (others => '0');
icmp_chksum <= (others => '0');
icmp_ident <= (others => '0');
icmp_seqNum <= (others => '0');
icmp_rx_start_reg <= '0';
src_ip_addr <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST => rx_count <= x"0000";
when INCR => rx_count <= rx_count + 1;
when SET_VAL => rx_count <= rx_count_val;
when HOLD => rx_count <= rx_count;
end case;
-- ICMP datafields capture
if (set_type = '1') then icmp_type(7 downto 0) <= dataval; end if;
if (set_code = '1') then icmp_code(7 downto 0) <= dataval; end if;
if (set_chksum_h = '1') then icmp_chksum(15 downto 8) <= dataval; end if;
if (set_chksum_l = '1') then icmp_chksum(7 downto 0) <= dataval; end if;
if (set_ident_h = '1') then icmp_ident(15 downto 8) <= dataval; end if;
if (set_ident_l = '1') then icmp_ident(7 downto 0) <= dataval; end if;
if (set_seq_h = '1') then icmp_seqNum(15 downto 8) <= dataval; end if;
if (set_seq_l = '1') then icmp_seqNum(7 downto 0) <= dataval; end if;
case set_icmp_rx_start is
when SET => icmp_rx_start_reg <= '1';
when CLR => icmp_rx_start_reg <= '0';
when HOLD => icmp_rx_start_reg <= icmp_rx_start_reg;
end case;
-- capture src IP address
if set_src_ip = '1' then
src_ip_addr <= ip_rx.hdr.src_ip_addr;
else
src_ip_addr <= src_ip_addr;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
sources/sources_1/readout/packet_formation.vhd
|
1
|
23094
|
----------------------------------------------------------------------------------
-- Company: NTU ATHENS - BNL
-- Engineer: Paris Moschovakos
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 25.06.2016
-- Design Name:
-- Module Name: packet_formation.vhd - Behavioral
-- Project Name: MMFE8
-- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2017.1
--
-- Changelog:
-- 22.08.2016 Changed readout trigger pulse from 125 to 100 ns long (Reid Pinkham)
-- 09.09.2016 Added two signals for ETR interconnection (Christos Bakalis)
-- 26.02.2016 Moved to a global clock domain @125MHz (Paris)
-- 06.04.2017 Hard setting latency to 300ns as configurable latency was moved to trigger module (Paris)
-- 25.04.2017 Added vmm_driver module. (Christos Bakalis)
-- 06.06.2017 Added ART header a handling (Paris)
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity packet_formation is
Generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic;
artEnabled : std_logic);
Port(
clk : in std_logic;
newCycle : in std_logic;
trigVmmRo : out std_logic;
vmmId : out std_logic_vector(2 downto 0);
vmmWord : in std_logic_vector(15 downto 0);
vmmWordReady : in std_logic;
vmmEventDone : in std_logic;
UDPDone : in std_logic;
pfBusy : out std_logic; -- Control signal to ETR
glBCID : in std_logic_vector(11 downto 0); -- glBCID counter from ETR
packLen : out std_logic_vector(11 downto 0);
dataout : out std_logic_vector(15 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
rd_ena_buff : out std_logic;
rst_l0 : out std_logic;
tr_hold : out std_logic;
reset : in std_logic;
rst_vmm : out std_logic;
linkHealth_bmsk : in std_logic_vector(8 downto 1);
rst_FIFO : out std_logic;
latency : in std_logic_vector(15 downto 0);
dbg_st_o : out std_logic_vector(4 downto 0);
trraw_synced125 : in std_logic;
vmmArtData125 : in std_logic_vector(5 downto 0);
vmmArtReady : in std_logic
);
end packet_formation;
architecture Behavioral of packet_formation is
signal artHeader : std_logic_vector(15 downto 0) := ( others => '0' );
signal header : std_logic_vector(63 downto 0) := ( others => '0' );
signal header_l0 : std_logic_vector(47 downto 0) := ( others => '0' );
signal vmmId_i : std_logic_vector(2 downto 0) := b"000";
signal globBcid : std_logic_vector(15 downto 0) := x"FFFF"; --( others => '0' );
signal precCnt : std_logic_vector(7 downto 0) := x"00"; --( others => '0' );
signal globBcid_i : std_logic_vector(15 downto 0);
signal globBCID_etr : std_logic_vector(11 downto 0) := (others => '0'); --globBCID counter as it is coming from ETR
signal eventCounter_i : unsigned(31 downto 0) := to_unsigned(0, 32);
signal wait_Cnt : integer range 0 to 31 := 0;
signal vmmId_cnt : integer range 0 to 7 := 0;
signal trigLatencyCnt : integer := 0;
signal trigLatency : integer := 140; -- 700ns (140x5ns)
signal pfBusy_i : std_logic := '0'; -- control signal to be sent to ETR
signal daqFIFO_wr_en_hdr : std_logic := '0';
signal daqFIFO_wr_en_drv : std_logic := '0';
signal sel_wrenable : std_logic := '0';
signal drv_enable : std_logic := '0';
signal drv_done : std_logic := '0';
signal daqFIFO_din : std_logic_vector(15 downto 0) := ( others => '0' );
signal triggerVmmReadout_i : std_logic := '0';
signal selectDataInput : std_logic_vector(2 downto 0) := (others => '0');
signal sel_cnt : unsigned(2 downto 0) := (others => '0');
signal vmmWord_i : std_logic_vector(15 downto 0) := ( others => '0' );
signal packLen_i : unsigned(11 downto 0) := x"000";
signal packLen_drv2pf_unsg : unsigned(11 downto 0) := x"000";
signal packLen_drv2pf : std_logic_vector(11 downto 0) := x"000";
signal packLen_cnt : unsigned(11 downto 0) := x"000";
signal end_packet_int : std_logic := '0';
signal artValid : std_logic := '0';
signal trraw_synced125_prev : std_logic := '0';
signal clearValid : std_logic := '0';
type stateType is (waitingForNewCycle, increaseCounter, waitForLatency, captureEventID, setEventID, sendHeaderStep1, sendHeaderStep2,
sendHeaderStep3, triggerVmmReadout, waitForData, sendVmmDataStep1, sendVmmDataStep2, formTrailer, sendTrailer, packetDone,
isUDPDone, isTriggerOff, S2, eventDone);
signal state : stateType;
-------------------- Debugging ------------------------------
signal probe0_out : std_logic_vector(132 downto 0);
signal probe1_out : std_logic_vector(200 downto 0);
signal debug_state : std_logic_vector(4 downto 0);
-----------------------------------------------------------------
---------------------- Debugging ------------------------------
-- attribute mark_debug : string;
-- attribute mark_debug of header : signal is "true";
-- attribute mark_debug of globBcid : signal is "true";
-- attribute mark_debug of globBcid_i : signal is "true";
-- attribute mark_debug of precCnt : signal is "true";
-- attribute mark_debug of vmmId_i : signal is "true";
-- attribute mark_debug of daqFIFO_din : signal is "true";
-- attribute mark_debug of vmmWord_i : signal is "true";
-- attribute mark_debug of packLen_i : signal is "true";
-- attribute mark_debug of packLen_cnt : signal is "true";
-- attribute mark_debug of end_packet_int : signal is "true";
-- attribute mark_debug of triggerVmmReadout_i : signal is "true";
-- attribute mark_debug of debug_state : signal is "true";
-- attribute mark_debug of artValid : signal is "true";
-- attribute mark_debug of trraw_synced125 : signal is "true";
-- attribute mark_debug of vmmArtReady : signal is "true";
component ila_pf
port (
clk : in std_logic;
probe0 : in std_logic_vector(132 downto 0);
probe1 : in std_logic_vector(200 downto 0)
);
end component;
component vio_0
port (
clk : in std_logic;
probe_out0 : out std_logic_vector ( 11 downto 0 )
);
end component;
component vmm_driver
port(
------------------------------------
------ General/PF Interface --------
clk : in std_logic;
drv_enable : in std_logic;
drv_done : out std_logic;
pack_len_drv : out std_logic_vector(11 downto 0);
------------------------------------
----- VMM_RO/FIFO2UDP Interface ----
wr_en_fifo2udp : out std_logic;
rd_en_buff : out std_logic;
vmmWordReady : in std_logic
);
end component;
-----------------------------------------------------------------
begin
packetCaptureProc: process(clk, newCycle, vmmEventDone, vmmWordReady, wait_Cnt, UDPDone)
begin
if rising_edge(clk) then
if reset = '1' then
debug_state <= "11111";
eventCounter_i <= to_unsigned(0, 32);
tr_hold <= '0';
pfBusy_i <= '0';
triggerVmmReadout_i <= '0';
rst_l0 <= '1';
sel_wrenable <= '0';
rst_FIFO <= '1';
daqFIFO_wr_en_hdr <= '0';
packLen_cnt <= x"000";
wait_Cnt <= 0;
sel_cnt <= (others => '0');
drv_enable <= '0';
triggerVmmReadout_i <= '0';
end_packet_int <= '0';
state <= waitingForNewCycle;
else
case state is
when waitingForNewCycle =>
debug_state <= "00000";
pfBusy_i <= '0';
triggerVmmReadout_i <= '0';
rst_l0 <= '0';
sel_wrenable <= '0';
drv_enable <= '0';
trigLatencyCnt <= 0;
sel_cnt <= (others => '0');
rst_FIFO <= '0';
if newCycle = '1' then
pfBusy_i <= '1';
state <= increaseCounter;
end if;
when increaseCounter =>
debug_state <= "00001";
eventCounter_i <= eventCounter_i + 1;
state <= waitForLatency;
when waitForLatency =>
debug_state <= "00010";
tr_hold <= '1'; -- Prevent new triggers
if(trigLatencyCnt > trigLatency and is_mmfe8 = '1')then
state <= S2;
elsif(trigLatencyCnt > trigLatency and is_mmfe8 = '0')then
state <= captureEventID;
else
trigLatencyCnt <= trigLatencyCnt + 1;
end if;
when S2 => -- wait for the header elements to be formed
debug_state <= "00010";
-- --tr_hold <= '1'; -- Prevent new triggers
packLen_cnt <= x"000"; -- Reset length count
sel_wrenable <= '0';
vmmId_i <= std_logic_vector(to_unsigned(vmmId_cnt, 3));
state <= captureEventID;
when captureEventID => -- Form Header
debug_state <= "00011";
packLen_cnt <= x"000";
state <= setEventID;
when setEventID =>
debug_state <= "00100";
rst_FIFO <= '0';
daqFIFO_wr_en_hdr <= '0';
if(wait_Cnt < 3)then
wait_Cnt <= wait_Cnt + 1;
state <= setEventID;
else
wait_Cnt <= 0;
state <= sendHeaderStep1;
end if;
when sendHeaderStep1 =>
debug_state <= "00101";
daqFIFO_wr_en_hdr <= '1';
packLen_cnt <= packLen_cnt + 1;
state <= sendHeaderStep2;
when sendHeaderStep2 =>
debug_state <= "00110";
daqFIFO_wr_en_hdr <= '0';
if(wait_Cnt < 3)then
wait_Cnt <= wait_Cnt + 1;
state <= sendHeaderStep2;
else
wait_Cnt <= 0;
state <= sendHeaderStep3;
end if;
when sendHeaderStep3 =>
if(sel_cnt < 5 and vmmReadoutMode = '0')then -- incr the counter to select the other parts of the header
sel_cnt <= sel_cnt + 1;
state <= setEventID;
elsif(sel_cnt < 4 and vmmReadoutMode = '1')then
sel_cnt <= sel_cnt + 1;
state <= setEventID;
else -- the whole header has been sent
state <= triggerVmmReadout;
end if;
when triggerVmmReadout => -- Creates an 136ns pulse to trigger the readout if not at level0 mode
debug_state <= "00111";
sel_cnt <= "110"; -- fix the counter to 4 to select the VMM data for the next steps
sel_wrenable <= '1'; -- grant control to driver
if wait_Cnt < 30 and vmmReadoutMode = '0' then
wait_Cnt <= wait_Cnt + 1;
triggerVmmReadout_i <= '1';
else
triggerVmmReadout_i <= '0';
wait_Cnt <= 0;
state <= waitForData;
end if;
when waitForData =>
debug_state <= "01000";
if (vmmWordReady = '1') then
state <= sendVmmDataStep1;
elsif (vmmEventDone = '1') then
state <= sendTrailer;
end if;
when sendVmmDataStep1 =>
debug_state <= "01001";
drv_enable <= '1';
state <= sendVmmDataStep2;
when sendVmmDataStep2 =>
debug_state <= "01010";
if(drv_done = '1')then
state <= formTrailer;
else
state <= sendVmmDataStep2;
end if;
when formTrailer =>
debug_state <= "01011";
if (vmmEventDone = '1') then
state <= sendTrailer;
elsif (vmmEventDone = '0' and vmmWordReady = '0') then
state <= waitForData;
else -- (vmmWordReady = '1') then
state <= formTrailer;
end if;
when sendTrailer =>
debug_state <= "01100";
packLen_i <= packLen_cnt + packLen_drv2pf_unsg;
state <= packetDone;
when packetDone =>
debug_state <= "01101";
end_packet_int <= '1';
if(is_mmfe8 = '1')then
state <= eventDone;
else
state <= isUDPDone;
end if;
when eventDone =>
debug_state <= "01110";
end_packet_int <= '0';
drv_enable <= '0';
if vmmId_cnt = 7 then
vmmId_cnt <= 0;
state <= isUDPDone;
else
vmmId_cnt <= vmmId_cnt + 1;
sel_cnt <= "000";
sel_wrenable <= '0';
state <= S2;
end if;
-- when resetVMMs =>
-- debug_state <= "01111";
-- rst_vmm <= '1';
-- state <= resetDone;
-- when resetDone =>
-- debug_state <= "10000";
-- if resetting = '0' then
-- rst_vmm <= '0';
-- state <= isUDPDone;
-- rst_vmm <= '0'; -- Prevent from continuously resetting while waiting for UDP Packet
-- end if;
when isUDPDone =>
debug_state <= "01110";
drv_enable <= '0';
end_packet_int <= '0';
rst_l0 <= '1'; -- reset the level0 buffers and the interface with packet_formation
-- pfBusy_i <= '0';
if (UDPDone = '1') then -- Wait for the UDP packet to be sent
state <= isTriggerOff;
end if;
when isTriggerOff => -- Wait for whatever ongoing trigger pulse to go to 0
debug_state <= "01111";
if trraw_synced125 /= '1' then
tr_hold <= '0'; -- Allow new triggers
state <= waitingForNewCycle;
end if;
when others =>
tr_hold <= '0';
state <= waitingForNewCycle;
end case;
end if;
end if;
end process;
muxFIFOData: process( sel_cnt, header, header_l0, vmmWord, vmmArtData125 )
begin
case sel_cnt is
when "000" => daqFIFO_din <= b"1111000" & artValid & "01" &
vmmArtData125(0) & vmmArtData125(1) & vmmArtData125(2) & vmmArtData125(3) & vmmArtData125(4) & vmmArtData125(5);
when "001" => daqFIFO_din <= b"0000000" & artValid & "00" &
vmmArtData125(0) & vmmArtData125(1) & vmmArtData125(2) & vmmArtData125(3) & vmmArtData125(4) & vmmArtData125(5);
when "010" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(63 downto 48); else daqFIFO_din <= header_l0(47 downto 32); end if;
when "011" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(47 downto 32); else daqFIFO_din <= header_l0(31 downto 16); end if;
when "100" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(31 downto 16); else daqFIFO_din <= header_l0(15 downto 0); end if;
when "101" => daqFIFO_din <= header(15 downto 0);
when "110" => daqFIFO_din <= vmmWord;
when others => daqFIFO_din <= (others => '0');
end case;
end process;
muxWrEn: process( sel_wrenable, daqFIFO_wr_en_hdr, daqFIFO_wr_en_drv )
begin
case sel_wrenable is
when '0' => wrenable <= daqFIFO_wr_en_hdr;
when '1' => wrenable <= daqFIFO_wr_en_drv;
when others => wrenable <= '0';
end case;
end process;
vmm_driver_inst: vmm_driver
port map(
------------------------------------
------ General/PF Interface --------
clk => clk,
drv_enable => drv_enable,
drv_done => drv_done,
pack_len_drv => packLen_drv2pf,
------------------------------------
----- VMM_RO/FIFO2UDP Interface ----
wr_en_fifo2udp => daqFIFO_wr_en_drv,
rd_en_buff => rd_ena_buff,
vmmWordReady => vmmWordReady
);
triggerEdgeDetection: process(clk) --125
begin
if rising_edge(clk) then
if trraw_synced125_prev = '0' and trraw_synced125 = '1' then
clearValid <= '1';
trraw_synced125_prev <= trraw_synced125;
else
clearValid <= '0';
trraw_synced125_prev <= trraw_synced125;
end if;
end if;
end process;
LDCE_inst : LDCE
generic map (
INIT => '0')
port map (
Q => artValid,
CLR => clearValid,
D => '1',
G => vmmArtReady,
GE => artEnabled
);
globBcid_i <= globBcid;
vmmWord_i <= vmmWord;
dataout <= daqFIFO_din;
packLen <= std_logic_vector(packLen_i);
end_packet <= end_packet_int;
trigVmmRo <= triggerVmmReadout_i;
vmmId <= vmmId_i;
trigLatency <= 37 + to_integer(unsigned(latency)); --(hard set to 300ns )--to_integer(unsigned(latency));
pfBusy <= pfBusy_i;
globBCID_etr <= glBCID;
artHeader <= b"0000000000" & vmmArtData125;
-- header of level 0 has three 16-bit words from FPGA + one 16-bit word from VMM
header_l0(47 downto 16) <= std_logic_vector(eventCounter_i);
header_l0(15 downto 0) <= b"00000" & vmmId_i & linkHealth_bmsk;
-- 5 & 3 & 8 ;
header(63 downto 32) <= std_logic_vector(eventCounter_i);
header(31 downto 0) <= precCnt & globBcid & b"00000" & vmmId_i;
-- 8 & 16 & 5 & 3
dbg_st_o <= debug_state;
packLen_drv2pf_unsg <= unsigned(packLen_drv2pf);
--ilaPacketFormation: ila_pf
--port map(
-- clk => clk,
-- probe0 => probe0_out,
-- probe1 => probe1_out
--);
probe0_out(9 downto 0) <= std_logic_vector(to_unsigned(trigLatencyCnt, 10));
probe0_out(19 downto 10) <= std_logic_vector(to_unsigned(trigLatency, 10));
probe0_out(20) <= '0';
probe0_out(21) <= artValid;
probe0_out(22) <= trraw_synced125;
probe0_out(23) <= vmmArtReady;
probe0_out(29 downto 24) <= vmmArtData125;
probe0_out(132 downto 30) <= (others => '0');--vmmId_i;
probe1_out(63 downto 0) <= (others => '0');--daqFIFO_din;
probe1_out(64) <= vmmWordReady;
probe1_out(65) <= vmmEventDone;
probe1_out(66) <= '0';
probe1_out(67) <= newCycle;
probe1_out(79 downto 68) <= std_logic_vector(packLen_i);
probe1_out(91 downto 80) <= std_logic_vector(packLen_cnt);
probe1_out(92) <= end_packet_int;
probe1_out(93) <= triggerVmmReadout_i;
probe1_out(109 downto 94) <= latency;
probe1_out(110) <= '0';
probe1_out(142 downto 111) <= std_logic_vector(eventCounter_i);
probe1_out(147 downto 143) <= debug_state;
probe1_out(200 downto 148) <= (others => '0');
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/Elink_4_FELIX/elinkInterface_felix_svn4472/EPROC_OUT2.vhd
|
1
|
5653
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 18/03/2015
--! Module Name: EPROC_OUT2
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee,work;
use ieee.std_logic_1164.all;
use work.all;
--! E-link processor, 2bit output
entity EPROC_OUT2 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
swap_outbits : in std_logic;
getDataTrig : out std_logic; -- @ bitCLKx4
ENCODING : in std_logic_vector (3 downto 0);
EDATA_OUT : out std_logic_vector (1 downto 0);
TTCin : in std_logic_vector (1 downto 0);
DATA_IN : in std_logic_vector (9 downto 0);
DATA_RDY : in std_logic
);
end EPROC_OUT2;
architecture Behavioral of EPROC_OUT2 is
constant zeros2bit : std_logic_vector (1 downto 0) := (others=>'0');
signal EdataOUT_ENC8b10b_case, EdataOUT_direct_case, EdataOUT_HDLC_case, EdataOUT_TTC0_case : std_logic_vector (1 downto 0);
signal rst_s, rst_case000, rst_case001, rst_case010, rst_case011 : std_logic;
signal getDataTrig_ENC8b10b_case, getDataTrig_direct_case, getDataTrig_HDLC_case, getDataTrig_TTC_case : std_logic;
signal edata_out_s : std_logic_vector (1 downto 0);
begin
gen_enabled: if do_generate = true generate
rst_s <= rst or (not ENA);
-------------------------------------------------------------------------------------------
-- case 0: direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case000 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "000")) else '1';
direct_case: entity work.EPROC_OUT2_direct
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case000,
getDataTrig => getDataTrig_direct_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_direct_case
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
EdataOUT_direct_case <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- case 1: DEC8b10b
-------------------------------------------------------------------------------------------
rst_case001 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "001")) else '1';
--
ENC8b10b_case: entity work.EPROC_OUT2_ENC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case001,
getDataTrig => getDataTrig_ENC8b10b_case,
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_ENC8b10b_case
);
--
-------------------------------------------------------------------------------------------
-- case 2: HDLC
-------------------------------------------------------------------------------------------
rst_case010 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "010")) else '1';
--
HDLC_case: entity work.EPROC_OUT2_HDLC
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case010,
getDataTrig => getDataTrig_HDLC_case, -- output, data request
edataIN => DATA_IN,
edataINrdy => DATA_RDY,
EdataOUT => EdataOUT_HDLC_case
);
--
-------------------------------------------------------------------------------------------
-- case 3: TTC-0
-------------------------------------------------------------------------------------------
rst_case011 <= '0' when ((rst_s = '0') and (ENCODING(2 downto 0) = "011")) else '1';
--
getDataTrig_TTC_case <= '0'; --'1' when (ENCODING(2 downto 0) = "011") else '0';
--
ttc_r: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if rst_case011 = '1' then
EdataOUT_TTC0_case <= zeros2bit;
else
EdataOUT_TTC0_case <= TTCin;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- output data and busy according to the encoding settings
-------------------------------------------------------------------------------------------
dataOUTmux: entity work.MUX4_Nbit
generic map (N=>2)
port map(
data0 => EdataOUT_direct_case,
data1 => EdataOUT_ENC8b10b_case,
data2 => EdataOUT_HDLC_case,
data3 => EdataOUT_TTC0_case,
sel => ENCODING(1 downto 0),
data_out => edata_out_s
);
--
getDataTrig <= ENA and (getDataTrig_TTC_case or getDataTrig_HDLC_case or getDataTrig_ENC8b10b_case or getDataTrig_direct_case);
--
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
edata_out_s <= (others=>'0');
getDataTrig <= '0';
end generate gen_disabled;
--
out_sel: process(swap_outbits,edata_out_s)
begin
if swap_outbits = '1' then
EDATA_OUT <= edata_out_s(0) & edata_out_s(1);
else
EDATA_OUT <= edata_out_s;
end if;
end process;
--
end Behavioral;
|
gpl-3.0
|
cbakalis/vmm_boards_firmware
|
miscellaneous/MMFE8_1VMM/sources_1/imports/UDP_TX.vhd
|
2
|
11282
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 5 June 2011
-- Design Name:
-- Module Name: UDP_TX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple UDP TX
-- doesnt generate the checksum(supposedly optional)
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added abort of tx when receive last from upstream
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity UDP_TX is
Port (
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic -- indicates IP TX is ready to take data
);
end UDP_TX;
architecture Behavioral of UDP_TX is
type tx_state_type is (IDLE, PAUSE, SEND_UDP_HDR, SEND_USER_DATA);
type count_mode_type is (RST, INCR, HOLD);
type settable_cnt_type is (RST, SET, INCR, HOLD);
type set_clr_type is (SET, CLR, HOLD);
-- TX state variables
signal udp_tx_state : tx_state_type;
signal tx_count : unsigned (15 downto 0);
signal tx_result_reg : std_logic_vector (1 downto 0);
signal ip_tx_start_reg : std_logic;
signal data_out_ready_reg : std_logic;
-- tx control signals
signal next_tx_state : tx_state_type;
signal set_tx_state : std_logic;
signal next_tx_result : std_logic_vector (1 downto 0);
signal set_tx_result : std_logic;
signal tx_count_val : unsigned (15 downto 0);
signal tx_count_mode : settable_cnt_type;
signal tx_data : std_logic_vector (7 downto 0);
signal set_last : std_logic;
signal set_ip_tx_start : set_clr_type;
signal tx_data_valid : std_logic; -- indicates whether data is valid to tx or not
-- tx temp signals
signal total_length : std_logic_vector (15 downto 0); -- computed combinatorially from header size
-- IP datagram header format
--
-- 0 4 8 16 19 24 31
-- --------------------------------------------------------------------------------------------
-- | source port number | dest port number |
-- | | |
-- --------------------------------------------------------------------------------------------
-- | length (bytes) | checksum |
-- | (header and data combined) | |
-- --------------------------------------------------------------------------------------------
-- | Data |
-- | |
-- --------------------------------------------------------------------------------------------
-- | .... |
-- | |
-- --------------------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------
-- combinatorial process to implement FSM and determine control signals
-----------------------------------------------------------------------
tx_combinatorial : process(
-- input signals
udp_tx_start, udp_txi, clk, ip_tx_result, ip_tx_data_out_ready,
-- state variables
udp_tx_state, tx_count, tx_result_reg, ip_tx_start_reg, data_out_ready_reg,
-- control signals
next_tx_state, set_tx_state, next_tx_result, set_tx_result, tx_count_mode, tx_count_val,
tx_data, set_last, total_length, set_ip_tx_start, tx_data_valid
)
begin
-- set output followers
ip_tx_start <= ip_tx_start_reg;
ip_tx.hdr.protocol <= x"11"; -- UDP protocol
ip_tx.hdr.data_length <= total_length;
ip_tx.hdr.dst_ip_addr <= udp_txi.hdr.dst_ip_addr;
if udp_tx_start = '1' and ip_tx_start_reg = '0' then
udp_tx_result <= UDPTX_RESULT_NONE; -- kill the result until have started the IP layer
else
udp_tx_result <= tx_result_reg;
end if;
case udp_tx_state is
when SEND_USER_DATA =>
ip_tx.data.data_out <= udp_txi.data.data_out;
tx_data_valid <= udp_txi.data.data_out_valid;
ip_tx.data.data_out_last <= udp_txi.data.data_out_last;
when SEND_UDP_HDR =>
ip_tx.data.data_out <= tx_data;
tx_data_valid <= ip_tx_data_out_ready;
ip_tx.data.data_out_last <= set_last;
when others =>
ip_tx.data.data_out <= (others => '0');
tx_data_valid <= '0';
ip_tx.data.data_out_last <= set_last;
end case;
ip_tx.data.data_out_valid <= tx_data_valid and ip_tx_data_out_ready;
-- set signal defaults
next_tx_state <= IDLE;
set_tx_state <= '0';
tx_count_mode <= HOLD;
tx_data <= x"00";
set_last <= '0';
next_tx_result <= UDPTX_RESULT_NONE;
set_tx_result <= '0';
set_ip_tx_start <= HOLD;
tx_count_val <= (others => '0');
udp_tx_data_out_ready <= '0';
-- set temp signals
total_length <= std_logic_vector(unsigned(udp_txi.hdr.data_length) + 8); -- total length = user data length + header length (bytes)
-- TX FSM
case udp_tx_state is
when IDLE =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
tx_count_mode <= RST;
if udp_tx_start = '1' then
-- check header count for error if too high
if unsigned(udp_txi.hdr.data_length) > 8966 then
next_tx_result <= UDPTX_RESULT_ERR; -- 10
set_tx_result <= '1';
else
-- start to send UDP header
tx_count_mode <= RST;
next_tx_result <= UDPTX_RESULT_SENDING; -- 01
set_ip_tx_start <= SET;
set_tx_result <= '1';
next_tx_state <= PAUSE;
set_tx_state <= '1';
end if;
end if;
when PAUSE =>
-- delay one clock for IP layer to respond to ip_tx_start and remove any tx error result
next_tx_state <= SEND_UDP_HDR;
set_tx_state <= '1';
when SEND_UDP_HDR =>
udp_tx_data_out_ready <= '0'; -- in this state, we are unable to accept user data for tx
if ip_tx_result = IPTX_RESULT_ERR then -- 10
set_ip_tx_start <= CLR;
next_tx_result <= UDPTX_RESULT_ERR; -- 10
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif ip_tx_data_out_ready = '1' then
if tx_count = x"0007" then
tx_count_val <= x"0001";
tx_count_mode <= SET;
next_tx_state <= SEND_USER_DATA;
set_tx_state <= '1';
else
tx_count_mode <= INCR;
end if;
case tx_count is
when x"0000" => tx_data <= udp_txi.hdr.src_port (15 downto 8); -- src port
when x"0001" => tx_data <= udp_txi.hdr.src_port (7 downto 0);
when x"0002" => tx_data <= udp_txi.hdr.dst_port (15 downto 8); -- dst port
when x"0003" => tx_data <= udp_txi.hdr.dst_port (7 downto 0);
when x"0004" => tx_data <= total_length (15 downto 8); -- length
when x"0005" => tx_data <= total_length (7 downto 0);
when x"0006" => tx_data <= udp_txi.hdr.checksum (15 downto 8); -- checksum (set by upstream)
when x"0007" => tx_data <= udp_txi.hdr.checksum (7 downto 0);
when others =>
-- shouldnt get here - handle as error
next_tx_result <= UDPTX_RESULT_ERR;
set_tx_result <= '1';
end case;
end if;
when SEND_USER_DATA =>
udp_tx_data_out_ready <= ip_tx_data_out_ready; -- in this state, we can accept user data if IP TX rdy
if ip_tx_data_out_ready = '1' then
if udp_txi.data.data_out_valid = '1' or tx_count = x"000" then
-- only increment if ready and valid has been subsequently established, otherwise data count moves on too fast
if unsigned(tx_count) = unsigned(udp_txi.hdr.data_length) then
-- TX terminated due to count - end normally
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_SENT; --11
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
elsif udp_txi.data.data_out_last = '1' then
-- terminate tx with error as got last from upstream before exhausting count
set_last <= '1';
tx_data <= udp_txi.data.data_out;
next_tx_result <= UDPTX_RESULT_ERR; --10
set_ip_tx_start <= CLR;
set_tx_result <= '1';
next_tx_state <= IDLE;
set_tx_state <= '1';
else
-- TX continues
tx_count_mode <= INCR;
tx_data <= udp_txi.data.data_out;
end if;
end if;
end if;
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process to action control signals and change states and outputs
-----------------------------------------------------------------------------
tx_sequential : process (clk,reset,data_out_ready_reg)
begin
if rising_edge(clk) then
data_out_ready_reg <= ip_tx_data_out_ready;
else
data_out_ready_reg <= data_out_ready_reg;
end if;
if rising_edge(clk) then
if reset = '1' then
-- reset state variables
udp_tx_state <= IDLE;
tx_count <= x"0000";
tx_result_reg <= IPTX_RESULT_NONE;
ip_tx_start_reg <= '0';
else
-- Next udp_tx_state processing
if set_tx_state = '1' then
udp_tx_state <= next_tx_state;
else
udp_tx_state <= udp_tx_state;
end if;
-- ip_tx_start_reg processing
case set_ip_tx_start is
when SET => ip_tx_start_reg <= '1';
when CLR => ip_tx_start_reg <= '0';
when HOLD => ip_tx_start_reg <= ip_tx_start_reg;
end case;
-- tx result processing
if set_tx_result = '1' then
tx_result_reg <= next_tx_result;
else
tx_result_reg <= tx_result_reg;
end if;
-- tx_count processing
case tx_count_mode is
when RST => tx_count <= x"0000";
when SET => tx_count <= tx_count_val;
when INCR => tx_count <= tx_count + 1;
when HOLD => tx_count <= tx_count;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
iti-luebeck/RTeasy2
|
RTeasy/src/vhdltmpl/cu_output_net_comp.vhd
|
3
|
329
|
COMPONENT %%COMPONENT_NAME_cu_output_net
PORT(
I : IN std_logic_vector(0 TO %%I_MAX);
STATE : IN std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0);
C : OUT std_logic_vector(0 TO %%C_MAX)
);
END COMPONENT;
FOR ALL : %%COMPONENT_NAME_cu_output_net USE ENTITY
WORK.%%COMPONENT_NAME_cu_output_net(behavioural);
|
gpl-3.0
|
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