repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
chiggs/nvc
|
test/regress/lfsr.vhd
|
5
|
1468
|
entity lfsr16 is
generic (
WIDTH : positive := 16;
TAP : natural := 3 );
port (
clk : in bit;
reset : in bit; -- Asynchronous
en : in bit;
value : out bit_vector(15 downto 0) );
end entity;
architecture rtl of lfsr16 is
signal state_r : bit_vector(WIDTH - 1 downto 0);
begin
value <= state_r;
process (clk, reset) is
begin
if reset = '1' then
state_r <= (others => '0');
elsif clk'event and clk = '1' then
if en = '1' then
state_r(WIDTH - 1 downto 1) <= state_r(WIDTH - 2 downto 0);
state_r(0) <= state_r(WIDTH - 1) xnor state_r(TAP);
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity lfsr is
end entity;
architecture test of lfsr is
constant PERIOD : delay_length := 10 ns;
signal clk, en : bit := '0';
signal reset : bit := '1';
signal value : bit_vector(15 downto 0);
begin
clk <= not clk after PERIOD / 2;
reset <= '0' after 10 ns;
en <= '1' after 30 ns;
uut: entity work.lfsr16
port map ( clk, reset, en, value );
check: process is
begin
wait for 500 ns;
assert value = ('0','1','1','1','1','1','1','1',
'1','1','1','1','1','0','0','0');
wait;
end process;
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/acia/vhdl_sim/tb_acia6551.vhd
|
1
|
6964
|
--------------------------------------------------------------------------------
-- Entity: acia6551
-- Date:2018-11-24
-- Author: gideon
--
-- Description: This is the testbench for the 6551.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.acia6551_pkg.all;
use work.tl_string_util_pkg.all;
entity tb_acia6551 is
end entity;
architecture testbench of tb_acia6551 is
signal clock : std_logic := '0';
signal reset : std_logic;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_irq : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_acia: entity work.acia6551
port map (
clock => clock,
reset => reset,
slot_req => slot_req,
slot_resp => slot_resp,
io_req => io_req,
io_resp => io_resp,
io_irq => io_irq
);
i_io_master: entity work.io_bus_bfm
generic map (
g_name => "io"
)
port map (
clock => clock,
req => io_req,
resp => io_resp
);
i_slot_master: entity work.slot_bus_master_bfm
generic map (
g_name => "slot"
)
port map (
clock => clock,
req => slot_req,
resp => slot_resp
);
p_test: process
variable io : p_io_bus_bfm_object;
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable status : std_logic_vector(7 downto 0);
procedure check_io_irq(level : std_logic; flags : std_logic_vector(7 downto 0) := X"00") is
variable reg : std_logic_vector(7 downto 0);
begin
wait until clock = '1';
wait until clock = '1';
wait until clock = '1';
assert level = io_irq report "Level of IO_irq is wrong." severity error;
if level = '1' then
io_read(io, c_reg_irq_source, reg);
assert flags = reg report "IRQ flags unexpected. " & hstr(reg) & "/=" & hstr(flags)
severity error;
io_write(io, c_reg_irq_source, flags);
end if;
end procedure;
procedure read_status_and_data(exp: boolean := false; expdata : std_logic_vector(7 downto 0) := X"00") is
begin
slot_io_read(slot, c_addr_status_register, status);
slot_io_read(slot, c_addr_data_register, data);
report hstr(status) & ":" & hstr(data);
if exp and status(3) = '0' then
report "Rx Data expected, but not available."
severity error;
end if;
if not exp and status(3) = '1' then
report "NO data expected, but there is Rx data available."
severity error;
end if;
if exp and status(3) = '1' and data /= expdata then
report "Wrong Rx data read."
severity error;
end if;
end procedure;
procedure read_tx(exp: boolean := false; expdata : std_logic_vector(7 downto 0) := X"00") is
variable head, tail : std_logic_vector(7 downto 0);
begin
io_read(io, c_reg_tx_head, head);
io_read(io, c_reg_tx_tail, tail);
io_read(io, unsigned(tail) + X"800", data);
report hstr(head) & ":" & hstr(tail) & ":" & hstr(data);
if head /= tail then
io_write(io, c_reg_tx_tail, std_logic_vector(unsigned(tail) + 1));
assert exp report "There is data, but you didn't expected any." severity error;
assert data = expdata report "Data is not as expected?" severity error;
else
assert not exp report "There is no data, but you did expect some!" severity error;
end if;
end procedure;
begin
bind_io_bus_bfm("io", io);
bind_slot_bus_master_bfm("slot", slot);
wait until reset = '0';
check_io_irq('0');
-- Enable and pass four bytes to the RX of the Host
io_write(io, c_reg_enable, X"19" ); -- enable IRQ on DTR change and control write
io_write(io, X"900", X"47");
io_write(io, X"901", X"69");
io_write(io, X"902", X"64");
io_write(io, X"903", X"65");
io_write(io, c_reg_rx_head, X"04" );
-- On the host side, read status. It should show no data, since DTR is not set
read_status_and_data;
-- Set DTR
slot_io_write(slot, c_addr_command_register, X"03");
check_io_irq('1', X"12"); -- Checks and clears IRQ
check_io_irq('0');
-- set the virtual baud rate
slot_io_write(slot, c_addr_control_register, X"1A");
check_io_irq('1', X"0A"); -- Checks and clears IRQ
check_io_irq('0');
io_read(io, c_reg_control, status);
assert status = X"1A" report "Control read register is different from what we wrote earlier." severity error;
-- Now that DTR is set, reading the host status should show that there is data available
read_status_and_data(true, X"47");
read_status_and_data(true, X"69");
read_status_and_data(true, X"64");
read_status_and_data(true, X"65");
read_status_and_data;
io_write(io, X"904", X"6f");
io_write(io, X"905", X"6e");
io_write(io, c_reg_rx_head, X"06" );
read_status_and_data(true, X"6F");
read_status_and_data(true, X"6E");
read_status_and_data;
io_write(io, c_reg_enable, X"05"); -- enable Tx Interrupt
assert io_irq = '0' report "IO IRQ should be zero now." severity error;
-- Now the other way around (from Host to Appl)
slot_io_write(slot, c_addr_data_register, X"01");
slot_io_write(slot, c_addr_data_register, X"02");
slot_io_write(slot, c_addr_data_register, X"03");
slot_io_write(slot, c_addr_data_register, X"04");
assert io_irq = '1' report "IO IRQ should be active now." severity error;
read_tx(true, X"01");
read_tx(true, X"02");
read_tx(true, X"03");
read_tx(true, X"04");
read_tx;
for i in 0 to 260 loop
slot_io_write(slot, c_addr_data_register, std_logic_vector(to_unsigned((i + 6) mod 256, 8)));
end loop;
read_tx(true, X"06");
read_tx(true, X"07");
read_tx(true, X"08");
read_tx(true, X"09");
read_tx(true, X"0A");
wait;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/regress/attr8.vhd
|
5
|
648
|
entity attr8 is
end entity;
architecture test of attr8 is
begin
process is
type myint is range 1 to 3;
subtype myint_sub is myint range 1 to 2;
variable x : integer;
begin
assert myint'val(1) = 1;
assert myint'val(2) = 2;
x := 1;
assert myint'val(x) = 1;
x := 2;
assert myint'val(x) = 2;
assert myint_sub'val(2) = 2;
assert myint_sub'val(x) = 2;
assert myint'pos(myint(x)) = x;
assert myint_sub'pos(myint(x)) = x;
assert myint'pos(1) = 1;
assert myint_sub'pos(1) = 1;
wait;
end process;
end architecture;
|
gpl-3.0
|
fpgaddicted/5bit-shift-register-structural-
|
HA.vhd
|
1
|
1112
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco
--
-- Create Date: 11:24:14 04/05/2017
-- Design Name:
-- Module Name: HA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HA is
Port ( AI : in STD_LOGIC;
BI : in STD_LOGIC;
CO : out STD_LOGIC;
SUM : out STD_LOGIC);
end HA;
architecture Behavioral of HA is
begin
sum <= AI xor BI;
co <= AI and BI;
end Behavioral;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/io/mem_ctrl/vhdl_source/simple_sram.vhd
|
5
|
5597
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : simple_sram.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity simple_sram is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 4;
SRAM_Data_Width : integer := 32;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
SRAM_A_Width : integer := 18 );
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(SRAM_A_Width-1 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
--
SRAM_A : out std_logic_vector(SRAM_A_Width-1 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end simple_sram;
architecture Gideon of simple_sram is
type t_state is (idle, setup, pulse, hold);
signal state : t_state;
signal sram_d_o : std_logic_vector(SRAM_D'range);
signal sram_d_t : std_logic;
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
rdata <= SRAM_D; -- clock in
case state is
when idle =>
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
SRAM_A <= address;
sram_d_t <= not readwriten;
sram_d_o <= wdata;
if readwriten='0' then -- write
SRAM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
SRAM_WEn <= '0';
state <= pulse;
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
SRAM_BEn <= (others => '0');
if SRAM_RD_ASU=0 then
SRAM_OEn <= '0';
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
when setup =>
if delay = 1 then
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
SRAM_WEn <= '0';
state <= pulse;
else
delay <= SRAM_RD_Pulse;
SRAM_OEn <= '0';
state <= pulse;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
SRAM_OEn <= '1';
SRAM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if rwn_i='0' and SRAM_WR_Hold > 1 then
delay <= SRAM_WR_Hold - 1;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 1 then
state <= hold;
delay <= SRAM_RD_Hold - 1;
else
sram_d_t <= '0';
state <= idle;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if reset='1' then
SRAM_BEn <= (others => '1');
sram_d_o <= (others => '1');
sram_d_t <= '0';
SRAM_OEn <= '1';
SRAM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
end if;
end if;
end process;
SRAM_CSn <= '0';
SRAM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
end Gideon;
|
gpl-3.0
|
chiggs/nvc
|
test/sem/issue131.vhd
|
5
|
352
|
package A_NG is
type STATE_TYPE is (STATE_IDLE, STATE_0, STATE_1);
end package;
package body A_NG is
procedure PROC is
type STATE_TYPE is (STATE_IDLE, STATE_A, STATE_B);
variable state : STATE_TYPE;
begin
state := STATE_A; -- Referenced wrong STATE_TYPE
end procedure;
end package body;
|
gpl-3.0
|
chiggs/nvc
|
test/bounds/bounds.vhd
|
1
|
4167
|
entity bounds is
end entity;
architecture test of bounds is
type foo is range 1 to 5;
type my_vec1 is array (positive range <>) of integer;
type my_vec2 is array (foo range <>) of integer;
signal s : my_vec1(1 to 10);
signal n : my_vec1(1 downto 10);
subtype bool_true is boolean range true to true;
function fun(x : in bit_vector(7 downto 0)) return bit;
procedure proc(x : in bit_vector(7 downto 0));
function natfunc(x : in natural) return boolean;
function enumfunc(x : in bool_true) return boolean;
function realfunc(x : in real) return boolean;
type matrix is array (integer range <>, integer range <>) of integer;
procedure proc2(x : in matrix(1 to 3, 1 to 3));
begin
process is
variable a : my_vec1(0 to 10); -- Error
variable b : my_vec2(1 to 60); -- Error
begin
end process;
s(-52) <= 5; -- Error
s(1 to 11) <= (others => 0); -- Error
s(0 to 2) <= (others => 0); -- Error
process is
begin
report (0 => 'a'); -- Error
end process;
process is
variable v1 : bit_vector(3 downto 0);
variable v2 : bit_vector(8 downto 1);
variable m1 : matrix(1 to 3, 2 to 4);
variable m2 : matrix(1 to 3, 1 to 4);
begin
assert fun(v1) = '1'; -- Error
proc(v1); -- Error
proc(v2); -- OK
proc2(m1); -- OK
proc2(m2); -- Error
end process;
s <= s(1 to 9); -- Error
n <= s(1 to 2); -- Error
n <= (1, 2, 3); -- Error
process is
variable v : my_vec1(1 to 3);
begin
v := s; -- Error
end process;
process is
variable x : integer;
begin
x := s(11); -- Error!
x := s(-1); -- Error!
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, 2, 3); -- OK
a := (5 => 1, 1 => 2, 0 => 3); -- Error
end process;
process is
subtype alpha is character range 'a' to 'z';
variable a : alpha;
variable p : positive;
begin
a := 'c'; -- OK
a := '1'; -- Error
p := 0; -- Error
end process;
process is
begin
assert s'length(5) = 5; -- Error
end process;
process is
begin
assert natfunc(-1); -- Error
end process;
process is
subtype str is string;
constant c : str := "hello"; -- OK
begin
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, others => 2); -- OK
a := (5 => 1, others => 2); -- Error
end process;
process is
type mat2d is array (integer range <>, integer range <>)
of integer;
procedure p(m : in mat2d);
begin
p(((0, 1, 2, 3), (1 to 2 => 5))); -- Error
end process;
-- Reduced from Billowitch tc1374
process is
type t_rec3 is record
f1 : boolean;
end record;
subtype st_rec3 is t_rec3 ;
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype st_arr3 is t_arr3 (1 to 5, true downto false) ;
variable v_st_arr3 : st_arr3;
begin
v_st_arr3(1, true) := (f1 => false);
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
begin
assert i'a(14) = '0'; -- Error
end process;
process is
constant FPO_LOG_MAX_ITERATIONS : integer := 9;
type T_FPO_LOG_ALPHA is array (0 to FPO_LOG_MAX_ITERATIONS-1) of integer;
variable alpha : T_FPO_LOG_ALPHA;
begin
if alpha(0 to 5) = (5, 4, 6, 6, 6, 6) then -- OK
null;
end if;
end process;
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/parse/comp.vhd
|
4
|
223
|
package p is
component c is
generic ( X : integer );
port ( o : out integer );
end component;
component foo
port ( x : inout integer );
end component foo;
end package;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/6502/vhdl_source/proc_interrupt.vhd
|
3
|
2441
|
library ieee;
use ieee.std_logic_1164.all;
entity proc_interrupt is
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
nmi_n : in std_logic;
i_flag : in std_logic;
clear_b : out std_logic;
vect_bit : in std_logic;
interrupt : out std_logic;
vect_addr : out std_logic_vector(3 downto 0) );
end proc_interrupt;
architecture gideon of proc_interrupt is
signal irq_c : std_logic := '0';
signal nmi_c : std_logic := '0';
signal nmi_d : std_logic := '0';
signal nmi_act : std_logic := '0';
signal vect_h : std_logic_vector(1 downto 0) := "00";
type state_t is (idle, do_irq, do_nmi);
signal state : state_t;
begin
vect_addr <= '1' & vect_h & vect_bit;
interrupt <= irq_c or nmi_act;
process(clock)
begin
if rising_edge(clock) then
irq_c <= not (irq_n or i_flag);
nmi_c <= not nmi_n;
clear_b <= '0';
if clock_en='1' then
nmi_d <= nmi_c;
if nmi_d = '0' and nmi_c = '1' then -- edge
nmi_act <= '1';
end if;
case state is
when idle =>
vect_h <= "11"; -- FE/FF
if nmi_act = '1' then
vect_h <= "01"; -- FA/FB
state <= do_nmi;
elsif irq_c = '1' then
state <= do_irq;
clear_b <= '1';
end if;
when do_irq =>
if vect_bit='0' or irq_c='0' then
state <= idle;
end if;
when do_nmi =>
if vect_bit='0' then
nmi_act <= '0';
state <= idle;
end if;
when others =>
state <= idle;
end case;
end if;
if reset='1' then
vect_h <= "10"; -- FC/FD 1100
state <= do_nmi;
nmi_act <= '0';
end if;
end if;
end process;
end gideon;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/fpga_top/ultimate_fpga/vhdl_source/u2p_nios2_solo.vhd
|
1
|
33598
|
-------------------------------------------------------------------------------
-- Title : u2p_nios
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel based on the "solo" nios; without Altera DDR2 ctrl.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.my_math_pkg.all;
use work.audio_type_pkg.all;
entity u2p_nios_solo is
generic (
g_dual_drive : boolean := true );
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout unsigned(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : in std_logic;
SLOT_ROMLn : in std_logic;
SLOT_IO1n : in std_logic;
SLOT_IO2n : in std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
SLOT_DRV_RST : out std_logic := '0';
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_DM : inout std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Misc
BOARD_REVn : in std_logic_vector(4 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_nios_solo is
component nios_solo is
port (
clk_clk : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_solo;
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
signal por_n : std_logic;
signal ref_reset : std_logic;
signal por_count : unsigned(15 downto 0) := (others => '0');
signal led_n : std_logic_vector(0 to 3);
signal RSTn_out : std_logic;
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal slot_addr_o : unsigned(15 downto 0);
signal slot_addr_tl : std_logic;
signal slot_addr_th : std_logic;
signal slot_data_o : std_logic_vector(7 downto 0);
signal slot_data_t : std_logic;
signal slot_rwn_o : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal eth_reset : std_logic;
signal ulpi_reset_req : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal buffer_en : std_logic;
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal is_idle : std_logic;
signal cpu_mem_req : t_mem_req_32;
signal cpu_mem_resp : t_mem_resp_32;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal uart_txd_from_logic : std_logic;
signal i2c_sda_i : std_logic;
signal i2c_sda_o : std_logic;
signal i2c_scl_i : std_logic;
signal i2c_scl_o : std_logic;
signal mdio_o : std_logic;
signal sw_trigger : std_logic;
signal trigger : std_logic;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
signal sw_iec_o : std_logic_vector(3 downto 0);
signal sw_iec_i : std_logic_vector(3 downto 0);
-- Cassette
signal c2n_read_in : std_logic;
signal c2n_write_in : std_logic;
signal c2n_read_out : std_logic;
signal c2n_write_out : std_logic;
signal c2n_read_en : std_logic;
signal c2n_write_en : std_logic;
signal c2n_sense_in : std_logic;
signal c2n_sense_out : std_logic;
signal c2n_motor_in : std_logic;
signal c2n_motor_out : std_logic;
-- io buses
signal io_irq : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_u2p_req_small : t_io_req;
signal io_u2p_resp_small: t_io_resp;
signal io_u2p_req_big : t_io_req;
signal io_u2p_resp_big : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
signal io_req_mixer : t_io_req;
signal io_resp_mixer : t_io_resp;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp;
-- Parallel cable connection
signal drv_track_is_0 : std_logic;
signal drv_via1_port_a_o : std_logic_vector(7 downto 0);
signal drv_via1_port_a_i : std_logic_vector(7 downto 0);
signal drv_via1_port_a_t : std_logic_vector(7 downto 0);
signal drv_via1_ca2_o : std_logic;
signal drv_via1_ca2_i : std_logic;
signal drv_via1_ca2_t : std_logic;
signal drv_via1_cb1_o : std_logic;
signal drv_via1_cb1_i : std_logic;
signal drv_via1_cb1_t : std_logic;
-- audio
signal audio_speaker : signed(12 downto 0);
signal speaker_vol : std_logic_vector(3 downto 0);
signal ult_drive1 : signed(17 downto 0);
signal ult_drive2 : signed(17 downto 0);
signal ult_tape_r : signed(17 downto 0);
signal ult_tape_w : signed(17 downto 0);
signal ult_samp_l : signed(17 downto 0);
signal ult_samp_r : signed(17 downto 0);
signal ult_sid_1 : signed(17 downto 0);
signal ult_sid_2 : signed(17 downto 0);
signal c64_debug_select : std_logic_vector(2 downto 0);
signal c64_debug_data : std_logic_vector(31 downto 0);
signal c64_debug_valid : std_logic;
signal drv_debug_data : std_logic_vector(31 downto 0);
signal drv_debug_valid : std_logic;
signal eth_tx_data : std_logic_vector(7 downto 0);
signal eth_tx_last : std_logic;
signal eth_tx_valid : std_logic;
signal eth_tx_ready : std_logic := '1';
signal eth_u2p_data : std_logic_vector(7 downto 0);
signal eth_u2p_last : std_logic;
signal eth_u2p_valid : std_logic;
signal eth_u2p_ready : std_logic := '1';
signal eth_rx_data : std_logic_vector(7 downto 0);
signal eth_rx_sof : std_logic;
signal eth_rx_eof : std_logic;
signal eth_rx_valid : std_logic;
begin
process(RMII_REFCLK)
begin
if rising_edge(RMII_REFCLK) then
if por_count = X"FFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => sys_reset,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => ulpi_reset_req,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_nios: nios_solo
port map (
clk_clk => sys_clock,
reset_reset_n => not sys_reset,
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => io_irq,
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
unsigned(mem_mem_req_address) => cpu_mem_req.address,
mem_mem_req_byte_en => cpu_mem_req.byte_en,
mem_mem_req_read_writen => cpu_mem_req.read_writen,
mem_mem_req_request => cpu_mem_req.request,
mem_mem_req_tag => cpu_mem_req.tag,
mem_mem_req_wdata => cpu_mem_req.data,
mem_mem_resp_dack_tag => cpu_mem_resp.dack_tag,
mem_mem_resp_data => cpu_mem_resp.data,
mem_mem_resp_rack_tag => cpu_mem_resp.rack_tag
);
i_split_u2p: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_u2p_req_small,
reqs(1) => io_u2p_req_big,
resps(0) => io_u2p_resp_small,
resps(1) => io_u2p_resp_big
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req_small,
resp => io_u2p_resp_small,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 12,
g_ports => 2
)
port map (
clock => sys_clock,
req => io_u2p_req_big,
resp => io_u2p_resp_big,
reqs(0) => io_req_mixer,
reqs(1) => io_req_debug,
resps(0) => io_resp_mixer,
resps(1) => io_resp_debug
);
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => memctrl_inhibit,
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
slow_clock => audio_clock,
slow_reset => audio_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio_i => MDIO_DATA,
mdio_o => mdio_o,
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
iec_i => sw_iec_i,
iec_o => sw_iec_o,
board_rev => not BOARD_REVn,
eth_irq_i => ETH_IRQn,
speaker_en => SPEAKER_ENABLE,
speaker_vol=> speaker_vol,
hub_reset_n=> HUB_RESETn,
ulpi_reset => ulpi_reset_req,
buffer_en => buffer_en
);
i2c_scl_i <= I2C_SCL and I2C_SCL_18;
i2c_sda_i <= I2C_SDA and I2C_SDA_18;
I2C_SCL <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA <= '0' when i2c_sda_o = '0' else 'Z';
I2C_SCL_18 <= '0' when i2c_scl_o = '0' else 'Z';
I2C_SDA_18 <= '0' when i2c_sda_o = '0' else 'Z';
MDIO_DATA <= '0' when mdio_o = '0' else 'Z';
i_logic: entity work.ultimate_logic_32
generic map (
g_simulation => false,
g_ultimate2plus => true,
g_clock_freq => 62_500_000,
g_numerator => 32,
g_denominator => 125,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_microblaze => false,
g_big_endian => false,
g_icap => false,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => g_dual_drive,
g_mm_drive => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_8voices => true,
g_hardware_iec => true,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_acia => true,
g_rmii => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
ext_io_req => io_req,
ext_io_resp => io_resp,
ext_mem_req => cpu_mem_req,
ext_mem_resp=> cpu_mem_resp,
cpu_irq => io_irq,
-- slot side
BUFFER_ENn => open,
VCC => SLOT_VCC,
phi2_i => SLOT_PHI2,
dotclk_i => SLOT_DOTCLK,
rstn_i => SLOT_RSTn,
rstn_o => RSTn_out,
slot_addr_o => slot_addr_o,
slot_addr_i => SLOT_ADDR,
slot_addr_tl=> slot_addr_tl,
slot_addr_th=> slot_addr_th,
slot_data_o => slot_data_o,
slot_data_i => SLOT_DATA,
slot_data_t => slot_data_t,
rwn_i => SLOT_RWn,
rwn_o => slot_rwn_o,
exromn_i => SLOT_EXROMn,
exromn_o => exrom_oc,
gamen_i => SLOT_GAMEn,
gamen_o => game_oc,
irqn_i => SLOT_IRQn,
irqn_o => irq_oc,
nmin_i => SLOT_NMIn,
nmin_o => nmi_oc,
ba_i => SLOT_BA,
dman_o => dma_oc,
romhn_i => SLOT_ROMHn,
romln_i => SLOT_ROMLn,
io1n_i => SLOT_IO1n,
io2n_i => SLOT_IO2n,
-- local bus side
mem_inhibit => memctrl_inhibit,
mem_req => mem_req,
mem_resp => mem_resp,
-- Audio outputs
audio_speaker => audio_speaker,
speaker_vol => speaker_vol,
aud_drive1 => ult_drive1,
aud_drive2 => ult_drive2,
aud_tape_r => ult_tape_r,
aud_tape_w => ult_tape_w,
aud_samp_l => ult_samp_l,
aud_samp_r => ult_samp_r,
aud_sid_1 => ult_sid_1,
aud_sid_2 => ult_sid_2,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
MOTOR_LEDn => led_n(0),
DISK_ACTn => led_n(1),
CART_LEDn => led_n(2),
SDACT_LEDn => led_n(3),
-- Parallel cable pins
drv_track_is_0 => drv_track_is_0,
drv_via1_port_a_o => drv_via1_port_a_o,
drv_via1_port_a_i => drv_via1_port_a_i,
drv_via1_port_a_t => drv_via1_port_a_t,
drv_via1_ca2_o => drv_via1_ca2_o,
drv_via1_ca2_i => drv_via1_ca2_i,
drv_via1_ca2_t => drv_via1_ca2_t,
drv_via1_cb1_o => drv_via1_cb1_o,
drv_via1_cb1_i => drv_via1_cb1_i,
drv_via1_cb1_t => drv_via1_cb1_t,
-- Debug UART
UART_TXD => uart_txd_from_logic,
UART_RXD => UART_RXD,
-- Debug buses
drv_debug_data => drv_debug_data,
drv_debug_valid => drv_debug_valid,
c64_debug_data => c64_debug_data,
c64_debug_valid => c64_debug_valid,
c64_debug_select => c64_debug_select,
-- SD Card Interface
SD_SSn => open,
SD_CLK => open,
SD_MOSI => open,
SD_MISO => '1',
SD_CARDDETn => '1',
SD_DATA => open,
-- RTC Interface
RTC_CS => open,
RTC_SCK => open,
RTC_MOSI => open,
RTC_MISO => '1',
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
c2n_read_in => c2n_read_in,
c2n_write_in => c2n_write_in,
c2n_read_out => c2n_read_out,
c2n_write_out => c2n_write_out,
c2n_read_en => c2n_read_en,
c2n_write_en => c2n_write_en,
c2n_sense_in => c2n_sense_in,
c2n_sense_out => c2n_sense_out,
c2n_motor_in => c2n_motor_in,
c2n_motor_out => c2n_motor_out,
-- Ethernet Interface (RMII)
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_u2p_data,
eth_tx_eof => eth_u2p_last,
eth_tx_valid => eth_u2p_valid,
eth_tx_ready => eth_u2p_ready,
-- Buttons
sw_trigger => sw_trigger,
trigger => sw_trigger,
BUTTON => button_i );
-- Parallel cable not implemented. This is the way to stub it...
drv_via1_port_a_i(7 downto 1) <= drv_via1_port_a_o(7 downto 1) or not drv_via1_port_a_t(7 downto 1);
drv_via1_port_a_i(0) <= drv_track_is_0; -- for 1541C
drv_via1_ca2_i <= drv_via1_ca2_o or not drv_via1_ca2_t;
drv_via1_cb1_i <= drv_via1_cb1_o or not drv_via1_cb1_t;
process(sys_clock)
variable c, d : std_logic := '0';
begin
if rising_edge(sys_clock) then
trigger <= d;
d := c;
c := button_i(0);
end if;
end process;
SLOT_RSTn <= '0' when RSTn_out = '0' else 'Z';
SLOT_DRV_RST <= not RSTn_out when rising_edge(sys_clock); -- Drive this pin HIGH when we want to reset the C64 (uses NFET on Rev.E boards)
SLOT_ADDR(15 downto 12) <= slot_addr_o(15 downto 12) when slot_addr_th = '1' else (others => 'Z');
SLOT_ADDR(11 downto 00) <= slot_addr_o(11 downto 00) when slot_addr_tl = '1' else (others => 'Z');
SLOT_DATA <= slot_data_o when slot_data_t = '1' else (others => 'Z');
SLOT_RWn <= slot_rwn_o when slot_addr_tl = '1' else 'Z';
irq_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => irq_oc, oc_out => SLOT_IRQn);
nmi_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => nmi_oc, oc_out => SLOT_NMIn);
dma_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => dma_oc, oc_out => SLOT_DMAn);
exr_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => exrom_oc, oc_out => SLOT_EXROMn);
gam_push: entity work.oc_pusher port map(clock => sys_clock, sig_in => game_oc, oc_out => SLOT_GAMEn);
LED_MOTORn <= led_n(0) xor sys_reset;
LED_DISKn <= led_n(1) xor sys_reset;
LED_CARTn <= led_n(2) xor sys_reset;
LED_SDACTn <= led_n(3) xor sys_reset;
IEC_SRQ_IN <= '0' when iec_srq_o = '0' or sw_iec_o(3) = '0' else 'Z';
IEC_ATN <= '0' when iec_atn_o = '0' or sw_iec_o(2) = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' or sw_iec_o(1) = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' or sw_iec_o(0) = '0' else 'Z';
sw_iec_i <= IEC_SRQ_IN & IEC_ATN & IEC_DATA & IEC_CLOCK;
button_i <= not BUTTON;
ULPI_RESET <= por_n;
UART_TXD <= uart_txd_from_logic; -- and uart_txd_from_qsys;
-- Tape
c2n_motor_in <= CAS_MOTOR;
CAS_SENSE <= '0' when c2n_sense_out = '1' else 'Z';
c2n_sense_in <= not CAS_SENSE;
CAS_READ <= c2n_read_out when c2n_read_en = '1' else 'Z';
c2n_read_in <= CAS_READ;
CAS_WRITE <= c2n_write_out when c2n_write_en = '1' else 'Z';
c2n_write_in <= CAS_WRITE;
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_divider => 10,
g_width => audio_speaker'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => audio_speaker,
dac_out => SPEAKER_DATA );
b_audio: block
signal aud_drive1 : signed(17 downto 0);
signal aud_drive2 : signed(17 downto 0);
signal aud_tape_r : signed(17 downto 0);
signal aud_tape_w : signed(17 downto 0);
signal aud_samp_l : signed(17 downto 0);
signal aud_samp_r : signed(17 downto 0);
signal aud_sid_1 : signed(17 downto 0);
signal aud_sid_2 : signed(17 downto 0);
signal audio_sid1 : std_logic_vector(17 downto 0);
signal audio_sid2 : std_logic_vector(17 downto 0);
signal codec_left_in : std_logic_vector(23 downto 0);
signal codec_right_in : std_logic_vector(23 downto 0);
signal codec_left_out : std_logic_vector(23 downto 0);
signal codec_right_out : std_logic_vector(23 downto 0);
signal audio_get_sample : std_logic;
signal sys_get_sample : std_logic;
signal inputs : t_audio_array(0 to 9);
begin
-- the SID sound from the socket comes in from the codec
i2s: entity work.i2s_serializer
port map (
clock => audio_clock,
reset => audio_reset,
i2s_out => AUDIO_SDO,
i2s_in => AUDIO_SDI,
i2s_bclk => AUDIO_BCLK,
i2s_fs => AUDIO_LRCLK,
sample_pulse => audio_get_sample,
left_sample_out => codec_left_in,
right_sample_out => codec_right_in,
left_sample_in => codec_left_out,
right_sample_in => codec_right_out );
AUDIO_MCLK <= audio_clock;
i_sync_get: entity work.pulse_synchronizer
port map (
clock_in => audio_clock,
pulse_in => audio_get_sample,
clock_out => sys_clock,
pulse_out => sys_get_sample
);
i_ultfilt1: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_drive1, audio_clock, aud_drive1 );
i_ultfilt2: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_drive2, audio_clock, aud_drive2 );
i_ultfilt3: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_tape_r, audio_clock, aud_tape_r );
i_ultfilt4: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_tape_w, audio_clock, aud_tape_w );
i_ultfilt5: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_samp_l, audio_clock, aud_samp_l );
i_ultfilt6: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_samp_r, audio_clock, aud_samp_r );
i_ultfilt7: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_sid_1, audio_clock, aud_sid_1 );
i_ultfilt8: entity work.sys_to_aud port map(sys_clock, sys_reset, sys_get_sample, ult_sid_2, audio_clock, aud_sid_2 );
inputs(0) <= aud_sid_1;
inputs(1) <= aud_sid_2;
inputs(2) <= signed(codec_left_in(23 downto 6));
inputs(3) <= signed(codec_right_in(23 downto 6));
inputs(4) <= aud_samp_l;
inputs(5) <= aud_samp_r;
inputs(6) <= aud_drive1;
inputs(7) <= aud_drive2;
inputs(8) <= aud_tape_r;
inputs(9) <= aud_tape_w;
-- Now we have ten sources, all in audio domain, let's do some mixing
i_mixer: entity work.generic_mixer
generic map(
g_num_sources => 10
)
port map(
clock => audio_clock,
reset => audio_reset,
start => audio_get_sample,
sys_clock => sys_clock,
req => io_req_mixer,
resp => io_resp_mixer,
inputs => inputs,
out_L => codec_left_out,
out_R => codec_right_out
);
end block;
SLOT_BUFFER_ENn <= not buffer_en;
i_debug_eth: entity work.eth_debug_stream
port map (
eth_clock => RMII_REFCLK,
eth_reset => eth_reset,
eth_u2p_data => eth_u2p_data,
eth_u2p_last => eth_u2p_last,
eth_u2p_valid => eth_u2p_valid,
eth_u2p_ready => eth_u2p_ready,
eth_tx_data => eth_tx_data,
eth_tx_last => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
sys_clock => sys_clock,
sys_reset => sys_reset,
io_req => io_req_debug,
io_resp => io_resp_debug,
c64_debug_select => c64_debug_select,
c64_debug_data => c64_debug_data,
c64_debug_valid => c64_debug_valid,
drv_debug_data => drv_debug_data,
drv_debug_valid => drv_debug_valid,
IEC_ATN => IEC_ATN,
IEC_CLOCK => IEC_CLOCK,
IEC_DATA => IEC_DATA
);
-- Transceiver
i_rmii: entity work.rmii_transceiver
port map (
clock => RMII_REFCLK,
reset => eth_reset,
rmii_crs_dv => RMII_CRS_DV,
rmii_rxd => RMII_RX_DATA,
rmii_tx_en => RMII_TX_EN,
rmii_txd => RMII_TX_DATA,
eth_rx_data => eth_rx_data,
eth_rx_sof => eth_rx_sof,
eth_rx_eof => eth_rx_eof,
eth_rx_valid => eth_rx_valid,
eth_tx_data => eth_tx_data,
eth_tx_eof => eth_tx_last,
eth_tx_valid => eth_tx_valid,
eth_tx_ready => eth_tx_ready,
ten_meg_mode => '0' );
end architecture;
|
gpl-3.0
|
chiggs/nvc
|
test/parse/attr.vhd
|
4
|
249
|
architecture a of e is
attribute foo : integer;
attribute foo of x : signal is 5;
attribute foo of x : component is 5;
attribute foo of x : label is 6;
attribute foo of x : type is 4;
begin
assert x'foo(5);
end architecture;
|
gpl-3.0
|
markusC64/1541ultimate2
|
fpga/ip/memory/vhdl_source/spram.vhd
|
5
|
1660
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
address : in unsigned(g_depth_bits-1 downto 0);
rdata : out std_logic_vector(g_width_bits-1 downto 0);
wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
en : in std_logic := '1';
we : in std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of spram : entity is "yes";
end entity;
architecture xilinx of spram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_port: process(clock)
begin
if rising_edge(clock) then
if en = '1' then
if g_read_first then
rdata <= ram(to_integer(address));
end if;
if we = '1' then
ram(to_integer(address)) := wdata;
end if;
if not g_read_first then
rdata <= ram(to_integer(address));
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/Core/avr_core.vhd
|
4
|
19193
|
--************************************************************************************************
-- Top entity for AVR core
-- Version 1.82? (Special version for the JTAG OCD)
-- Designed by Ruslan Lepetenok
-- Modified 31.08.2006
-- SLEEP and CLRWDT instructions support was added
-- BREAK instructions support was added
-- PM clock enable was added
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use Work.AVR_Core_CompPack.all;
entity AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector(15 downto 0);
inst : in std_logic_vector(15 downto 0);
-- I/O control
adr : out std_logic_vector(15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector(15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector(7 downto 0);
dbusout : out std_logic_vector(7 downto 0);
-- Interrupt
irqlines : in std_logic_vector(22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic
);
end AVR_Core;
architecture Struct of avr_core is
signal dbusin_int : std_logic_vector(7 downto 0);
signal dbusout_int : std_logic_vector(7 downto 0);
signal adr_int : std_logic_vector(15 downto 0);
signal iowe_int : std_logic;
signal iore_int : std_logic;
-- SIGNALS FOR INSTRUCTION AND STATES
signal idc_add : std_logic;
signal idc_adc : std_logic;
signal idc_adiw : std_logic;
signal idc_sub : std_logic;
signal idc_subi : std_logic;
signal idc_sbc : std_logic;
signal idc_sbci : std_logic;
signal idc_sbiw : std_logic;
signal adiw_st : std_logic;
signal sbiw_st : std_logic;
signal idc_and : std_logic;
signal idc_andi : std_logic;
signal idc_or : std_logic;
signal idc_ori : std_logic;
signal idc_eor : std_logic;
signal idc_com : std_logic;
signal idc_neg : std_logic;
signal idc_inc : std_logic;
signal idc_dec : std_logic;
signal idc_cp : std_logic;
signal idc_cpc : std_logic;
signal idc_cpi : std_logic;
signal idc_cpse : std_logic;
signal idc_lsr : std_logic;
signal idc_ror : std_logic;
signal idc_asr : std_logic;
signal idc_swap : std_logic;
signal sbi_st : std_logic;
signal cbi_st : std_logic;
signal idc_bst : std_logic;
signal idc_bset : std_logic;
signal idc_bclr : std_logic;
signal idc_sbic : std_logic;
signal idc_sbis : std_logic;
signal idc_sbrs : std_logic;
signal idc_sbrc : std_logic;
signal idc_brbs : std_logic;
signal idc_brbc : std_logic;
signal idc_reti : std_logic;
signal alu_data_r_in : std_logic_vector(7 downto 0);
signal alu_data_out : std_logic_vector(7 downto 0);
signal reg_rd_in : std_logic_vector(7 downto 0);
signal reg_rd_out : std_logic_vector(7 downto 0);
signal reg_rr_out : std_logic_vector(7 downto 0);
signal reg_rd_adr : std_logic_vector(4 downto 0);
signal reg_rr_adr : std_logic_vector(4 downto 0);
signal reg_h_out : std_logic_vector(15 downto 0);
signal reg_z_out : std_logic_vector(15 downto 0);
signal reg_h_adr : std_logic_vector(2 downto 0);
signal reg_rd_wr : std_logic;
signal post_inc : std_logic;
signal pre_dec : std_logic;
signal reg_h_wr : std_logic;
signal sreg_fl_in : std_logic_vector(7 downto 0);
signal sreg_out : std_logic_vector(7 downto 0);
signal sreg_fl_wr_en : std_logic_vector(7 downto 0);
signal spl_out : std_logic_vector(7 downto 0);
signal sph_out : std_logic_vector(7 downto 0);
signal rampz_out : std_logic_vector(7 downto 0);
signal sp_ndown_up : std_logic;
signal sp_en : std_logic;
signal bit_num_r_io : std_logic_vector(2 downto 0);
signal branch : std_logic_vector(2 downto 0);
signal bitpr_io_out : std_logic_vector(7 downto 0);
signal bit_pr_sreg_out : std_logic_vector(7 downto 0);
signal sreg_flags : std_logic_vector(7 downto 0);
signal bld_op_out : std_logic_vector(7 downto 0);
signal reg_file_rd_in : std_logic_vector(7 downto 0);
signal bit_test_op_out : std_logic;
signal alu_c_flag_out : std_logic;
signal alu_z_flag_out : std_logic;
signal alu_n_flag_out : std_logic;
signal alu_v_flag_out : std_logic;
signal alu_s_flag_out : std_logic;
signal alu_h_flag_out : std_logic;
begin
pm_fetch_dec_Inst:component pm_fetch_dec port map(
-- Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
-- JTAG OCD support
valid_instr => valid_instr,
insert_nop => insert_nop,
block_irq => block_irq,
change_flow => change_flow,
-- Program memory
pc => pc,
inst => inst,
-- I/O control
adr => adr_int,
iore => iore_int,
iowe => iowe_int,
-- Data memory control
ramadr => ramadr,
ramre => ramre,
ramwe => ramwe,
cpuwait => cpuwait,
-- Data paths
dbusin => dbusin_int,
dbusout => dbusout_int,
-- Interrupt
irqlines => irqlines,
irqack => irqack,
irqackad => irqackad,
--Sleep
sleepi => sleepi,
irqok => irqok,
--Watchdog
wdri => wdri,
-- ALU interface(Data inputs)
alu_data_r_in => alu_data_r_in,
-- ALU interface(Instruction inputs)
idc_add_out => idc_add,
idc_adc_out => idc_adc,
idc_adiw_out => idc_adiw,
idc_sub_out => idc_sub,
idc_subi_out => idc_subi,
idc_sbc_out => idc_sbc,
idc_sbci_out => idc_sbci,
idc_sbiw_out => idc_sbiw,
adiw_st_out => adiw_st,
sbiw_st_out => sbiw_st,
idc_and_out => idc_and,
idc_andi_out => idc_andi,
idc_or_out => idc_or,
idc_ori_out => idc_ori,
idc_eor_out => idc_eor,
idc_com_out => idc_com,
idc_neg_out => idc_neg,
idc_inc_out => idc_inc,
idc_dec_out => idc_dec,
idc_cp_out => idc_cp,
idc_cpc_out => idc_cpc,
idc_cpi_out => idc_cpi,
idc_cpse_out => idc_cpse,
idc_lsr_out => idc_lsr,
idc_ror_out => idc_ror,
idc_asr_out => idc_asr,
idc_swap_out => idc_swap,
-- ALU interface(Data output)
alu_data_out => alu_data_out,
-- ALU interface(Flag outputs)
alu_c_flag_out => alu_c_flag_out,
alu_z_flag_out => alu_z_flag_out,
alu_n_flag_out => alu_n_flag_out,
alu_v_flag_out => alu_v_flag_out,
alu_s_flag_out => alu_s_flag_out,
alu_h_flag_out => alu_h_flag_out,
-- General purpose register file interface
reg_rd_in => reg_rd_in,
reg_rd_out => reg_rd_out,
reg_rd_adr => reg_rd_adr,
reg_rr_out => reg_rr_out,
reg_rr_adr => reg_rr_adr,
reg_rd_wr => reg_rd_wr,
post_inc => post_inc,
pre_dec => pre_dec,
reg_h_wr => reg_h_wr,
reg_h_out => reg_h_out,
reg_h_adr => reg_h_adr,
reg_z_out => reg_z_out,
-- I/O register file interface
sreg_fl_in => sreg_fl_in, --??
globint => sreg_out(7), -- SREG I flag
sreg_fl_wr_en => sreg_fl_wr_en,
spl_out => spl_out,
sph_out => sph_out,
sp_ndown_up => sp_ndown_up,
sp_en => sp_en,
rampz_out => rampz_out,
-- Bit processor interface
bit_num_r_io => bit_num_r_io,
bitpr_io_out => bitpr_io_out,
branch => branch,
bit_pr_sreg_out => bit_pr_sreg_out,
bld_op_out => bld_op_out,
bit_test_op_out => bit_test_op_out,
sbi_st_out => sbi_st,
cbi_st_out => cbi_st,
idc_bst_out => idc_bst,
idc_bset_out => idc_bset,
idc_bclr_out => idc_bclr,
idc_sbic_out => idc_sbic,
idc_sbis_out => idc_sbis,
idc_sbrs_out => idc_sbrs,
idc_sbrc_out => idc_sbrc,
idc_brbs_out => idc_brbs,
idc_brbc_out => idc_brbc,
idc_reti_out => idc_reti);
GPRF_Inst:component reg_file port map (
--Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
reg_rd_in => reg_rd_in,
reg_rd_out => reg_rd_out,
reg_rd_adr => reg_rd_adr,
reg_rr_out => reg_rr_out,
reg_rr_adr => reg_rr_adr,
reg_rd_wr => reg_rd_wr,
post_inc => post_inc,
pre_dec => pre_dec,
reg_h_wr => reg_h_wr,
reg_h_out => reg_h_out,
reg_h_adr => reg_h_adr,
reg_z_out => reg_z_out);
BP_Inst:component bit_processor port map(
--Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
bit_num_r_io => bit_num_r_io,
dbusin => dbusin_int,
bitpr_io_out => bitpr_io_out,
sreg_out => sreg_out,
branch => branch,
bit_pr_sreg_out => bit_pr_sreg_out,
bld_op_out => bld_op_out,
reg_rd_out => reg_rd_out,
bit_test_op_out => bit_test_op_out,
-- Instructions and states
sbi_st => sbi_st,
cbi_st => cbi_st,
idc_bst => idc_bst,
idc_bset => idc_bset,
idc_bclr => idc_bclr,
idc_sbic => idc_sbic,
idc_sbis => idc_sbis,
idc_sbrs => idc_sbrs,
idc_sbrc => idc_sbrc,
idc_brbs => idc_brbs,
idc_brbc => idc_brbc,
idc_reti => idc_reti);
io_dec_Inst:component io_adr_dec port map (
adr => adr_int,
iore => iore_int,
dbusin_int => dbusin_int, -- LOCAL DATA BUS OUTPUT
dbusin_ext => dbusin, -- EXTERNAL DATA BUS INPUT
spl_out => spl_out,
sph_out => sph_out,
sreg_out => sreg_out,
rampz_out => rampz_out
);
IORegs_Inst: component io_reg_file port map(
--Clock and reset
cp2 => cp2,
cp2en => cp2en,
ireset => ireset,
adr => adr_int,
iowe => iowe_int,
dbusout => dbusout_int,
sreg_fl_in => sreg_fl_in,
sreg_out => sreg_out,
sreg_fl_wr_en => sreg_fl_wr_en,
spl_out => spl_out,
sph_out => sph_out,
sp_ndown_up => sp_ndown_up,
sp_en => sp_en,
rampz_out => rampz_out);
ALU_Inst:component alu_avr port map(
-- Data inputs
alu_data_r_in => alu_data_r_in,
alu_data_d_in => reg_rd_out,
alu_c_flag_in => sreg_out(0),
alu_z_flag_in => sreg_out(1),
-- Instructions and states
idc_add => idc_add,
idc_adc => idc_adc,
idc_adiw => idc_adiw,
idc_sub => idc_sub,
idc_subi => idc_subi,
idc_sbc => idc_sbc,
idc_sbci => idc_sbci,
idc_sbiw => idc_sbiw,
adiw_st => adiw_st,
sbiw_st => sbiw_st,
idc_and => idc_and,
idc_andi => idc_andi,
idc_or => idc_or,
idc_ori => idc_ori,
idc_eor => idc_eor,
idc_com => idc_com,
idc_neg => idc_neg,
idc_inc => idc_inc,
idc_dec => idc_dec,
idc_cp => idc_cp,
idc_cpc => idc_cpc,
idc_cpi => idc_cpi,
idc_cpse => idc_cpse,
idc_lsr => idc_lsr,
idc_ror => idc_ror,
idc_asr => idc_asr,
idc_swap => idc_swap,
-- Data outputs
alu_data_out => alu_data_out,
-- Flag outputs
alu_c_flag_out => alu_c_flag_out,
alu_z_flag_out => alu_z_flag_out,
alu_n_flag_out => alu_n_flag_out,
alu_v_flag_out => alu_v_flag_out,
alu_s_flag_out => alu_s_flag_out,
alu_h_flag_out => alu_h_flag_out);
-- Outputs
adr <= adr_int;
iowe <= iowe_int;
iore <= iore_int;
dbusout <= dbusout_int;
-- Sleep support
globint <= sreg_out(7); -- I flag
end Struct;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/eth_marvell_88e1111/hdl/other/tx_arbitrator_over_ip.vhd
|
1
|
2120
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipv4_types.all;
entity tx_arbitrator_over_ip is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in ipv4_tx_type; -- data byte to tx
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in ipv4_tx_type; -- data byte to tx
data : out ipv4_tx_type -- data byte to tx
);
end tx_arbitrator_over_ip;
architecture Behavioral of tx_arbitrator_over_ip is
type grant_type is (M1,M2);
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1,
data_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
else
data <= data_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/sobel/hdl/sobel_process.vhd
|
1
|
5345
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity sobel_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer;
WEIGHT_SIZE : integer := 8
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end sobel_process;
architecture rtl of sobel_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- products calculation
signal prod00, prod01, prod02 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod10, prod11, prod12 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod20, prod21, prod22 : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
signal prod_dv : std_logic;
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_width
);
process (clk_proc, reset_n, matrix_dv)
variable sum : signed((WEIGHT_SIZE + IN_SIZE) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
prod_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
if(in_fv = '0') then
enable_s <= status_reg_enable_bit;
prod_dv <= '0';
value_dv <= '0';
end if;
-- product calculation pipeline stage
prod_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
prod00 <= "11111110" * signed('0' & p00); -- w00 = -2
prod01 <= "11111110" * signed('0' & p01); -- w01 = -2
prod02 <= "00000000" * signed('0' & p02); -- w02 = 0
prod10 <= "11111110" * signed('0' & p10); -- w10 = -2
prod11 <= "00000000" * signed('0' & p11); -- w11 = 0
prod12 <= "00000010" * signed('0' & p12); -- w12 = 2
prod20 <= "00000000" * signed('0' & p20); -- w20 = 0
prod21 <= "00000010" * signed('0' & p21); -- w21 = 2
prod22 <= "00000010" * signed('0' & p22); -- w22 = 2
prod_dv <= '1';
end if;
value_dv <= '0';
if(prod_dv='1' and enable_s = '1') then
sum := prod00 + prod01 + prod02 +
prod10 + prod11 + prod12 +
prod20 + prod21 + prod22;
if (sum(sum'left) = '1') then
sum := (others => '0');
end if;
value_data <= std_logic_vector(sum)(OUT_SIZE -1 downto 0);
value_dv <= '1';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/fastfilter/hdl/components/taps2.vhd
|
1
|
1121
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity taps2 is
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end taps2;
architecture bhv of taps2 is
signal cell : pixel_array (0 to TAPS_WIDTH-1);
begin
process(clk)
variable i : integer := 0;
begin
if ( reset_n = '0' ) then
cell <= (others =>(others => '0'));
out_data <= (others => '0');
taps_data <= (others =>(others => '0'));
elsif (rising_edge(clk)) then
if (enable='1') then
cell(0) <= in_data;
for i in 1 to (TAPS_WIDTH-1) loop
cell(i) <= cell(i-1);
end loop;
taps_data <= cell(0 to KERNEL_SIZE-1);
out_data <= cell(TAPS_WIDTH-1);
end if;
end if;
end process;
end bhv;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
src/altera/pll1.vhd
|
1
|
18368
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll1 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll1;
ARCHITECTURE SYN OF pll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_phase_shift => "0",
clk1_divide_by => 3,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
clk2_divide_by => 3,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 41666,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll32.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/conv/hdl/conv_slave.vhd
|
1
|
9439
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity conv_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
norm_reg_norm : out std_logic_vector(3 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end conv_slave;
architecture rtl of conv_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant W00_REG_REG_ADDR : natural := 2;
constant W01_REG_REG_ADDR : natural := 3;
constant W02_REG_REG_ADDR : natural := 4;
constant W10_REG_REG_ADDR : natural := 5;
constant W11_REG_REG_ADDR : natural := 6;
constant W12_REG_REG_ADDR : natural := 7;
constant W20_REG_REG_ADDR : natural := 8;
constant W21_REG_REG_ADDR : natural := 9;
constant W22_REG_REG_ADDR : natural := 10;
constant NORM_REG_REG_ADDR : natural := 11;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
signal w00_reg_m00_reg : std_logic_vector (7 downto 0);
signal w01_reg_m01_reg : std_logic_vector (7 downto 0);
signal w02_reg_m02_reg : std_logic_vector (7 downto 0);
signal w10_reg_m10_reg : std_logic_vector (7 downto 0);
signal w11_reg_m11_reg : std_logic_vector (7 downto 0);
signal w12_reg_m12_reg : std_logic_vector (7 downto 0);
signal w20_reg_m20_reg : std_logic_vector (7 downto 0);
signal w21_reg_m21_reg : std_logic_vector (7 downto 0);
signal w22_reg_m22_reg : std_logic_vector (7 downto 0);
signal norm_reg_norm_reg : std_logic_vector (3 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
w00_reg_m00_reg <= "00000000";
w01_reg_m01_reg <= "00000000";
w02_reg_m02_reg <= "00000000";
w10_reg_m10_reg <= "00000000";
w11_reg_m11_reg <= "00000000";
w12_reg_m12_reg <= "00000000";
w20_reg_m20_reg <= "00000000";
w21_reg_m21_reg <= "00000000";
w22_reg_m22_reg <= "00000000";
norm_reg_norm_reg <= "0000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
when WIDTHIMG_REG_REG_ADDR =>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W00_REG_REG_ADDR =>
w00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W01_REG_REG_ADDR =>
w01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W02_REG_REG_ADDR =>
w02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W10_REG_REG_ADDR =>
w10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W11_REG_REG_ADDR =>
w11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W12_REG_REG_ADDR =>
w12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W20_REG_REG_ADDR =>
w20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W21_REG_REG_ADDR =>
w21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when W22_REG_REG_ADDR =>
w22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when NORM_REG_REG_ADDR =>
norm_reg_norm_reg <= datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when WIDTHIMG_REG_REG_ADDR =>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when W00_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w00_reg_m00_reg(7) & w00_reg_m00_reg(6) & w00_reg_m00_reg(5) & w00_reg_m00_reg(4) & w00_reg_m00_reg(3) & w00_reg_m00_reg(2) & w00_reg_m00_reg(1) & w00_reg_m00_reg(0);
when W01_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w01_reg_m01_reg(7) & w01_reg_m01_reg(6) & w01_reg_m01_reg(5) & w01_reg_m01_reg(4) & w01_reg_m01_reg(3) & w01_reg_m01_reg(2) & w01_reg_m01_reg(1) & w01_reg_m01_reg(0);
when W02_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w02_reg_m02_reg(7) & w02_reg_m02_reg(6) & w02_reg_m02_reg(5) & w02_reg_m02_reg(4) & w02_reg_m02_reg(3) & w02_reg_m02_reg(2) & w02_reg_m02_reg(1) & w02_reg_m02_reg(0);
when W10_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w10_reg_m10_reg(7) & w10_reg_m10_reg(6) & w10_reg_m10_reg(5) & w10_reg_m10_reg(4) & w10_reg_m10_reg(3) & w10_reg_m10_reg(2) & w10_reg_m10_reg(1) & w10_reg_m10_reg(0);
when W11_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w11_reg_m11_reg(7) & w11_reg_m11_reg(6) & w11_reg_m11_reg(5) & w11_reg_m11_reg(4) & w11_reg_m11_reg(3) & w11_reg_m11_reg(2) & w11_reg_m11_reg(1) & w11_reg_m11_reg(0);
when W12_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w12_reg_m12_reg(7) & w12_reg_m12_reg(6) & w12_reg_m12_reg(5) & w12_reg_m12_reg(4) & w12_reg_m12_reg(3) & w12_reg_m12_reg(2) & w12_reg_m12_reg(1) & w12_reg_m12_reg(0);
when W20_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w20_reg_m20_reg(7) & w20_reg_m20_reg(6) & w20_reg_m20_reg(5) & w20_reg_m20_reg(4) & w20_reg_m20_reg(3) & w20_reg_m20_reg(2) & w20_reg_m20_reg(1) & w20_reg_m20_reg(0);
when W21_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w21_reg_m21_reg(7) & w21_reg_m21_reg(6) & w21_reg_m21_reg(5) & w21_reg_m21_reg(4) & w21_reg_m21_reg(3) & w21_reg_m21_reg(2) & w21_reg_m21_reg(1) & w21_reg_m21_reg(0);
when W22_REG_REG_ADDR =>
datard_o <= "000000000000000000000000" & w22_reg_m22_reg(7) & w22_reg_m22_reg(6) & w22_reg_m22_reg(5) & w22_reg_m22_reg(4) & w22_reg_m22_reg(3) & w22_reg_m22_reg(2) & w22_reg_m22_reg(1) & w22_reg_m22_reg(0);
when NORM_REG_REG_ADDR =>
datard_o <= "0000000000000000000000000000" & norm_reg_norm_reg(3) & norm_reg_norm_reg(2) & norm_reg_norm_reg(1) & norm_reg_norm_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
w00_reg_m00 <= w00_reg_m00_reg;
w01_reg_m01 <= w01_reg_m01_reg;
w02_reg_m02 <= w02_reg_m02_reg;
w10_reg_m10 <= w10_reg_m10_reg;
w11_reg_m11 <= w11_reg_m11_reg;
w12_reg_m12 <= w12_reg_m12_reg;
w20_reg_m20 <= w20_reg_m20_reg;
w21_reg_m21 <= w21_reg_m21_reg;
w22_reg_m22 <= w22_reg_m22_reg;
norm_reg_norm <= norm_reg_norm_reg;
end rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/com/hdl/flow_to_com.vhd
|
1
|
8339
|
-- This block receives a flow from a GPStudio block.
-- Depending on the data valid and flow valid, it add the GPStudio header (Start of Frame and End of Frame flags and the number of the packet)
-- before sending the data to the HAL block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.com_package.all;
entity flow_to_com is
generic (
ID_FIFO : std_logic_vector(5 downto 0) := "000001";
FLOW_IN_SIZE : integer := 8;
DATA_WIDTH : integer := 8;
FIFO_DEPTH : integer := 2048;
ONE_PACKET : integer := 1450
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
flow_in_data : in std_logic_vector(FLOW_IN_SIZE-1 downto 0);
flow_in_fv : in std_logic;
flow_in_dv : in std_logic;
read_data : in std_logic;
ready : out std_logic;
data_size : out std_logic_vector(15 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end flow_to_com;
architecture RTL of flow_to_com is
type flow_to_com_fsm is (idle, gps_header, data_state);
signal state : flow_to_com_fsm; --Flow to hal FSM
signal count_fifo : std_logic_vector(15 downto 0);
signal one_packet_size : std_logic_vector(15 downto 0);
signal num_packet_s : std_logic_vector(7 downto 0);
signal ready_s : std_logic;
signal wrreq,rdreq : std_logic;
signal reset : std_logic;
signal flow_fv_dl : std_logic;
signal empty_fifo : std_logic;
signal rd_flags,wr_flags : std_logic;
signal empty_flags : std_logic;
signal data_flags : std_logic_vector(17 downto 0);
signal count_wr,count_wr_b : std_logic_vector(15 downto 0);
signal count_rd : std_logic_vector(15 downto 0);
signal pkt_size : std_logic_vector(15 downto 0);
signal sof,eof : std_logic;
signal data,data_out_s : std_logic_vector(7 downto 0);
signal flags_out : std_logic_vector(17 downto 0);
signal count_fsm : std_logic_vector(3 downto 0);
signal data_size_s : std_logic_vector(15 downto 0);
signal read_data_dl : std_logic;
signal rdreq_s : std_logic;
begin
reset <= not reset_n;
rd_flags <= '1' when read_data='1' and read_data_dl='0' and state=idle else '0';
ready <= '0' when empty_fifo='1' else ready_s;
one_packet_size <= std_logic_vector(to_unsigned(ONE_PACKET,16));
data_size <= data_size_s+x"2";
--- Write fifo only when enable
wrreq <= flow_in_dv when enable='1' else '0';
--- Fifo that contains data
fifo_data_inst : entity work.gp_dcfifo
generic map (DATA_WIDTH => 8,
FIFO_DEPTH => FIFO_DEPTH)
port map(
aclr => reset,
data => flow_in_data,
rdclk => clk_hal,
rdreq => rdreq,
wrclk => clk_proc,
wrreq => wrreq,
q => data,
rdempty => empty_fifo
);
--- Fifo that contains flags of the packets and their size
fifo_flags_inst : entity work.gp_dcfifo
generic map (DATA_WIDTH => 18,
FIFO_DEPTH => 256)
port map(
aclr => reset,
data => data_flags,
rdclk => clk_hal,
rdreq => rd_flags,
wrclk => clk_proc,
wrreq => wr_flags,
q => flags_out,
rdempty => empty_flags
);
data_flags <= sof & eof & pkt_size;
count_wr_b <= std_logic_vector(to_unsigned(to_integer(unsigned(count_wr)) rem ONE_PACKET,16));
pkt_size <= count_wr when count_wr<one_packet_size else
count_wr_b when eof='1' else
one_packet_size;
----- Set the write signals for fifo flags
process(clk_proc, reset_n)
begin
if reset_n='0' then
count_wr <= x"0000";
wr_flags <= '0';
sof <= '0';
eof <= '0';
elsif clk_proc'event and clk_proc='1' then
flow_fv_dl <= flow_in_fv;
--- Counting data write
if wrreq='1' then
count_wr <= count_wr+1;
elsif eof='1' then
count_wr <= x"0000";
end if;
--- Control fifo flags write
if (flow_in_fv='0' and flow_fv_dl='1') or (to_integer(unsigned(count_wr)) rem ONE_PACKET=0 and count_wr>=one_packet_size) then
wr_flags <= '1';
else
wr_flags <= '0';
end if;
--- Set flags for each packet
--- Set Start of Frame when a flow starts
if flow_in_fv='1' and flow_fv_dl='0' then
sof <= '1';
elsif eof='1' or count_wr>one_packet_size then
sof <= '0';
end if;
--- Set End of Frame when a flow ends
if flow_in_fv='0' and flow_fv_dl='1' then
eof <= '1';
elsif flow_in_fv='1' and flow_fv_dl='0' then
eof <= '0';
end if;
end if;
end process;
----- Set the read signals for fifo flags and place gps header when HAL starts to read
process(clk_hal, reset_n)
begin
if reset_n='0' then
count_rd <= x"0000";
data_size_s <= x"0000";
num_packet_s <= x"00";
elsif clk_hal'event and clk_hal='1' then
read_data_dl <= read_data;
--- Control fifo flags read
if rdreq='1' then
count_rd <= count_rd +1;
elsif state=idle then
count_rd <= x"0000";
end if;
--- Place gps header then read data from fifo
case state is
when idle =>
rdreq_s <= '0';
if rd_flags='1' then
state <= gps_header;
count_fsm <= x"0";
end if;
when gps_header =>
if read_data='1' then
count_fsm <= count_fsm+1;
if count_fsm=x"0" then
data_out_s <= ID_FIFO & flags_out(17 downto 16);
if flags_out(17)='1' then --- Increment numero of the packet only when SoF=0
num_packet_s <= x"00";
else
num_packet_s <= num_packet_s+1;
end if;
elsif count_fsm=x"1" then
data_out_s <= num_packet_s;
rdreq_s <= '1';
data_size_s <= flags_out(15 downto 0);
elsif count_fsm=x"2" then
state <= data_state;
data_out_s <= data;
end if;
end if;
when data_state =>
if read_data='1' then
rdreq_s <= '1';
if count_rd=data_size_s-x"1" or empty_fifo='1' then
state <= idle;
rdreq_s <= '0';
end if;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
data_out <= data_out_s when state=gps_header else data;
rdreq <= '0' when (ready_s='0' or empty_fifo='1') else rdreq_s;
----- Set the ready signal
process(clk_hal, reset_n)
begin
if reset_n='0' then
ready_s <= '0';
elsif clk_hal'event and clk_hal='1' then
if empty_flags='0' and ready_s='0' then
ready_s <= '1';
elsif (state=data_state and count_rd=data_size_s-x"1") or (empty_fifo='1') then --- Not ready when a full packet has been read or when it's the last packet
ready_s <= '0';
end if;
end if;
end process;
end RTL;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/JTAG_OCD_Prg/JTAGDataPack.vhd
|
4
|
1359
|
--**********************************************************************************************
-- Fuses/Lock bits and Calibration bytes for JTAG "Flash" Programmer
-- Version 0.11
-- Modified 19.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGDataPack is
-- Extended Fuse Byte
constant C_ExtFuseByte : std_logic_vector(7 downto 0) := x"FD"; -- x"00"
-- Fuse High Byte
constant C_HighFuseByte : std_logic_vector(7 downto 0) := x"19"; -- x"01"
-- Fuse Low Byte
constant C_LowFuseByte : std_logic_vector(7 downto 0) := x"E3"; -- x"00"
-- Lock bits
constant C_LockBits : std_logic_vector(7 downto 0) := x"FF";
-- Signature Bytes(3 Bytes)
constant C_SignByte1 : std_logic_vector(7 downto 0) := x"1E";
constant C_SignByte2 : std_logic_vector(7 downto 0) := x"97";
constant C_SignByte3 : std_logic_vector(7 downto 0) := x"02";
-- Calibration Bytes(4 Bytes)
constant C_CalibrByte1 : std_logic_vector(7 downto 0) := x"C1";
constant C_CalibrByte2 : std_logic_vector(7 downto 0) := x"C2";
constant C_CalibrByte3 : std_logic_vector(7 downto 0) := x"C3";
constant C_CalibrByte4 : std_logic_vector(7 downto 0) := x"C4";
end JTAGDataPack;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/MC6809CpuMon.vhd
|
1
|
12849
|
-------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MC6808CpuMon.vhd
-- /___/ /\ Timestamp : 24/10/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MC6808CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MC6809CpuMon is
generic (
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
-- Fast clock
clock : in std_logic;
-- Quadrature clocks
E : in std_logic;
Q : in std_logic;
--6809 Signals
DMA_n_BREQ_n : in std_logic;
-- 6809E Sig
TSC : in std_logic;
LIC : out std_logic;
AVMA : out std_logic;
BUSY : out std_logic;
-- Signals common to both 6809 and 6809E
RES_n : in std_logic;
NMI_n : in std_logic;
IRQ_n : in std_logic;
FIRQ_n : in std_logic;
HALT_n : in std_logic;
BS : out std_logic;
BA : out std_logic;
R_W_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic
);
end MC6809CpuMon;
architecture behavioral of MC6809CpuMon is
signal clock_avr : std_logic;
signal cpu_clk : std_logic;
signal cpu_reset_n : std_logic;
signal busmon_clk : std_logic;
signal R_W_n_int : std_logic;
signal NMI_sync : std_logic;
signal IRQ_sync : std_logic;
signal FIRQ_sync : std_logic;
signal HALT_sync : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
signal Dbusmon : std_logic_vector(7 downto 0);
signal Sync_int : std_logic;
signal hold : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal memory_rd1 : std_logic;
signal memory_wr1 : std_logic;
signal memory_addr : std_logic_vector(15 downto 0);
signal memory_addr1 : std_logic_vector(15 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal Regs : std_logic_vector(111 downto 0);
signal Regs1 : std_logic_vector(255 downto 0);
signal last_PC : std_logic_vector(15 downto 0);
signal ifetch : std_logic;
signal ifetch1 : std_logic;
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(2 downto 0);
signal LIC_int : std_logic;
signal E_a : std_logic; -- E delayed by 0..20ns
signal E_b : std_logic; -- E delayed by 20..40ns
signal E_c : std_logic; -- E delayed by 40..60ns
signal E_d : std_logic; -- E delayed by 60..80ns
signal E_e : std_logic; -- E delayed by 80..100ns
signal E_f : std_logic; -- E delayed by 100..120ns
signal E_g : std_logic; -- E delayed by 120..140ns
signal E_h : std_logic; -- E delayed by 120..140ns
signal E_i : std_logic; -- E delayed by 120..140ns
signal data_wr : std_logic;
signal nRSTout : std_logic;
signal NMI_n_masked : std_logic;
signal IRQ_n_masked : std_logic;
signal FIRQ_n_masked : std_logic;
begin
LIC <= LIC_int;
-- The following outputs are not implemented
-- BUSY (6809E mode)
BUSY <= '0';
-- The following inputs are not implemented
-- DMA_n_BREQ_n (6809 mode)
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
mon : entity work.BusMonCore
generic map (
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => '1',
cpu_clk => cpu_clk,
cpu_clken => '1',
Addr => Addr_int,
Data => Dbusmon,
Rd_n => not R_W_n_int,
Wr_n => R_W_n_int,
RdIO_n => '1',
WrIO_n => '1',
Sync => Sync_int,
Rdy => open,
nRSTin => RES_n,
nRSTout => cpu_reset_n,
CountCycle => CountCycle,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
Regs => Regs1,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => open,
WrIOOut => open,
AddrOut => memory_addr,
DataOut => memory_dout,
DataIn => memory_din,
Done => memory_done,
Special => special,
SS_Step => SS_Step,
SS_Single => SS_Single
);
FIRQ_n_masked <= FIRQ_n or special(2);
NMI_n_masked <= NMI_n or special(1);
IRQ_n_masked <= IRQ_n or special(0);
-- The CPU is slightly pipelined and the register update of the last
-- instruction overlaps with the opcode fetch of the next instruction.
--
-- If the single stepping stopped on the opcode fetch cycle, then the registers
-- valued would not accurately reflect the previous instruction.
--
-- To work around this, when single stepping, we stop on the cycle after
-- the opcode fetch, which means the program counter has advanced.
--
-- To hide this from the user single stepping, all we need to do is to
-- also pipeline the value of the program counter by one stage to compensate.
last_pc_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (hold = '0') then
last_PC <= Regs(95 downto 80);
end if;
end if;
end process;
Regs1( 79 downto 0) <= Regs( 79 downto 0);
Regs1( 95 downto 80) <= last_PC;
Regs1(111 downto 96) <= Regs(111 downto 96);
Regs1(255 downto 112) <= (others => '0');
inst_cpu09: entity work.cpu09 port map (
clk => cpu_clk,
rst => not cpu_reset_n,
vma => AVMA,
lic_out => LIC_int,
ifetch => ifetch,
opfetch => open,
ba => BA,
bs => BS,
addr => Addr_int,
rw => R_W_n_int,
data_out => Dout,
data_in => Din,
irq => IRQ_sync,
firq => FIRQ_sync,
nmi => NMI_sync,
halt => HALT_sync,
hold => hold,
Regs => Regs
);
-- Synchronize all external inputs, to avoid subtle bugs like missed interrupts
irq_gen : process(cpu_clk)
begin
if falling_edge(cpu_clk) then
NMI_sync <= not NMI_n_masked;
IRQ_sync <= not IRQ_n_masked;
FIRQ_sync <= not FIRQ_n_masked;
HALT_sync <= not HALT_n;
end if;
end process;
-- This block generates a sync signal that has the same characteristic as
-- a 6502 sync, i.e. asserted during the fetching the first byte of each instruction.
-- The below logic copes ifetch being active for all bytes of the instruction.
sync_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (hold = '0') then
ifetch1 <= ifetch and not LIC_int;
end if;
end if;
end process;
Sync_int <= ifetch and not ifetch1;
-- This block generates a hold signal that acts as the inverse of a clock enable
-- for the 6809. See comments above for why this is a cycle later than the way
-- we would do if for the 6502.
hold_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if (Sync_int = '1') then
-- stop after the opcode has been fetched
hold <= SS_Single;
elsif (SS_Step = '1') then
-- start again when the single step command is issues
hold <= '0';
end if;
end if;
end process;
-- Only count cycles when the 6809 is actually running
CountCycle <= not hold;
-- this block delays memory_rd, memory_wr, memory_addr until the start of the next cpu clk cycle
-- necessary because the cpu mon block is clocked of the opposite edge of the clock
-- this allows a full cpu clk cycle for cpu mon reads and writes
mem_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
memory_rd1 <= memory_rd;
memory_wr1 <= memory_wr;
memory_addr1 <= memory_addr;
end if;
end process;
R_W_n <= 'Z' when TSC = '1' else
'1' when memory_rd1 = '1' else
'0' when memory_wr1 = '1' else
R_W_n_int;
Addr <= (others => 'Z') when TSC = '1' else
memory_addr1 when (memory_rd1 = '1' or memory_wr1 = '1') else
Addr_int;
data_latch : process(E)
begin
if falling_edge(E) then
Din <= Data;
memory_din <= Data;
end if;
end process;
Data <= memory_dout when TSC = '0' and data_wr = '1' and memory_wr1 = '1' else
Dout when TSC = '0' and data_wr = '1' and R_W_n_int = '0' and memory_rd1 = '0' else
(others => 'Z');
-- Version of data seen by the Bus Mon need to use Din rather than the
-- external bus value as by the rising edge of cpu_clk we will have stopped driving
-- the external bus. On the ALS version we get away way this, but on the GODIL
-- version, due to the pullups, we don't. So all write watch breakpoints see
-- the data bus as 0xFF.
Dbusmon <= Din when R_W_n_int = '1' else Dout;
memory_done <= memory_rd1 or memory_wr1;
-- Delayed/Deglitched version of the E clock
e_gen : process(clock)
begin
if rising_edge(clock) then
E_a <= E;
E_b <= E_a;
if E_b /= E_i then
E_c <= E_b;
end if;
E_d <= E_c;
E_e <= E_d;
E_f <= E_e;
E_g <= E_f;
E_h <= E_g;
E_i <= E_h;
end if;
end process;
-- Main clock timing control
-- E_c is delayed by 40-60ns
-- On a real 6809 the output delay (to ADDR, RNW, BA, BS) is 65ns (measured)
cpu_clk <= not E_c;
busmon_clk <= E_c;
-- Data bus write timing control
--
-- When data_wr is 0 the bus is high impedence
--
-- This avoids bus conflicts when the direction of the data bus
-- changes from read to write (or visa versa).
--
-- Note: on the dragon this is not critical; setting to '1' seemed to work
data_wr <= Q or E;
-- Spare pins used for testing
test1 <= E_a;
test2 <= E_c;
end behavioral;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/maxPool/hdl/maxPool_process.vhd
|
1
|
3909
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maxPool_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end entity;
architecture rtl of maxPool_process is
--------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------
signal connect_data : std_logic_vector (PIXEL_SIZE - 1 downto 0);
signal connect_dv : std_logic;
signal connect_fv : std_logic;
--------------------------------------------------------------------------
-- components
--------------------------------------------------------------------------
component poolH
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------
component poolV
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------
begin
poolV_inst : poolV
generic map (
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out_data => connect_data,
out_dv => connect_dv,
out_fv => connect_fv
);
------------------------------------------------------------------------
poolh_inst : poolH
generic map (
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => connect_data,
in_dv => connect_dv,
in_fv => connect_fv,
out_data => out_data,
out_dv => out_dv,
out_fv => out_fv
);
end rtl;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
src/altera/sdram_simple.vhd
|
1
|
15994
|
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Matthew Hagerty
-- Copyright 2019 Google LLC
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
-- Simple SDRAM Controller for Winbond W9812G6JH-75
-- http://codehackcreate.com/archives/444
--
-- Matthew Hagerty, copyright 2014
--
-- Create Date: 18:22:00 March 18, 2014
-- Module Name: sdram_simple - RTL
--
-- Change Log:
--
-- Jul 2019 (Phillip Pearson)
-- Added clk_en to allow running at half rate, for easy timing
--
-- Jan 28, 2016
-- Changed to use positive clock edge.
-- Buffered output (read) data, sampled during RAS2.
-- Removed unused signals for features that were not implemented.
-- Changed tabs to space.
--
-- March 19, 2014
-- Initial implementation.
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity sdram_simple is
port(
-- Host side
clk_100m0_i : in std_logic; -- Master clock
clk_en : in std_logic; -- Master clock enable
reset_i : in std_logic := '0'; -- Reset, active high
refresh_i : in std_logic := '0'; -- Initiate a refresh cycle, active high
rw_i : in std_logic := '0'; -- Initiate a read or write operation, active high
we_i : in std_logic := '0'; -- Write enable, active low
addr_i : in std_logic_vector(23 downto 0) := (others => '0'); -- Address from host to SDRAM
data_i : in std_logic_vector(15 downto 0) := (others => '0'); -- Data from host to SDRAM
ub_i : in std_logic; -- Data upper byte enable, active low
lb_i : in std_logic; -- Data lower byte enable, active low
ready_o : out std_logic := '0'; -- Set to '1' when the memory is ready
done_o : out std_logic := '0'; -- Read, write, or refresh, operation is done
data_o : out std_logic_vector(15 downto 0); -- Data from SDRAM to host
-- SDRAM side
sdCke_o : out std_logic; -- Clock-enable to SDRAM
sdCe_bo : out std_logic; -- Chip-select to SDRAM
sdRas_bo : out std_logic; -- SDRAM row address strobe
sdCas_bo : out std_logic; -- SDRAM column address strobe
sdWe_bo : out std_logic; -- SDRAM write enable
sdBs_o : out std_logic_vector(1 downto 0); -- SDRAM bank address
sdAddr_o : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sdData_io : inout std_logic_vector(15 downto 0); -- Data to/from SDRAM
sdDqmh_o : out std_logic; -- Enable upper-byte of SDRAM databus if true
sdDqml_o : out std_logic -- Enable lower-byte of SDRAM databus if true
);
end entity;
architecture rtl of sdram_simple is
-- SDRAM controller states.
type fsm_state_type is (
ST_INIT_WAIT, ST_INIT_PRECHARGE, ST_INIT_REFRESH1, ST_INIT_MODE, ST_INIT_REFRESH2,
ST_IDLE, ST_REFRESH, ST_ACTIVATE, ST_RCD, ST_RW, ST_RAS1, ST_RAS2, ST_PRECHARGE);
signal state_r, state_x : fsm_state_type := ST_INIT_WAIT;
-- SDRAM mode register data sent on the address bus.
--
-- | A12-A10 | A9 | A8 A7 | A6 A5 A4 | A3 | A2 A1 A0 |
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
-- 0 0 0 0 0 0 0 1 0 0 0 0 0
constant MODE_REG : std_logic_vector(12 downto 0) := "000" & "0" & "00" & "010" & "0" & "000";
-- SDRAM commands combine SDRAM inputs: cs, ras, cas, we.
subtype cmd_type is unsigned(3 downto 0);
constant CMD_ACTIVATE : cmd_type := "0011";
constant CMD_PRECHARGE : cmd_type := "0010";
constant CMD_WRITE : cmd_type := "0100";
constant CMD_READ : cmd_type := "0101";
constant CMD_MODE : cmd_type := "0000";
constant CMD_NOP : cmd_type := "0111";
constant CMD_REFRESH : cmd_type := "0001";
signal cmd_r : cmd_type;
signal cmd_x : cmd_type;
signal bank_s : std_logic_vector(1 downto 0);
signal row_s : std_logic_vector(12 downto 0);
signal col_s : std_logic_vector(8 downto 0);
signal addr_r : std_logic_vector(12 downto 0);
signal addr_x : std_logic_vector(12 downto 0); -- SDRAM row/column address.
signal sd_dout_r : std_logic_vector(15 downto 0);
signal sd_dout_x : std_logic_vector(15 downto 0);
signal sd_busdir_r : std_logic;
signal sd_busdir_x : std_logic;
signal timer_r, timer_x : natural range 0 to 20000 := 0;
signal refcnt_r, refcnt_x : natural range 0 to 8 := 0;
signal bank_r, bank_x : std_logic_vector(1 downto 0);
signal cke_r, cke_x : std_logic;
signal sd_dqmu_r, sd_dqmu_x : std_logic;
signal sd_dqml_r, sd_dqml_x : std_logic;
signal ready_r, ready_x : std_logic;
-- Data buffer for SDRAM to Host.
signal buf_dout_r, buf_dout_x : std_logic_vector(15 downto 0);
begin
-- All signals to SDRAM buffered.
(sdCe_bo, sdRas_bo, sdCas_bo, sdWe_bo) <= cmd_r; -- SDRAM operation control bits
sdCke_o <= cke_r; -- SDRAM clock enable
sdBs_o <= bank_r; -- SDRAM bank address
sdAddr_o <= addr_r; -- SDRAM address
sdData_io <= sd_dout_r when sd_busdir_r = '1' else (others => 'Z'); -- SDRAM data bus.
sdDqmh_o <= sd_dqmu_r; -- SDRAM high data byte enable, active low
sdDqml_o <= sd_dqml_r; -- SDRAM low date byte enable, active low
-- Signals back to host.
ready_o <= ready_r;
data_o <= buf_dout_r;
-- 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 09 | 08 07 06 05 04 03 02 01 00 |
-- BS0 BS1 | ROW (A12-A0) 8192 rows | COL (A8-A0) 512 cols |
bank_s <= addr_i(23 downto 22);
row_s <= addr_i(21 downto 9);
col_s <= addr_i(8 downto 0);
process (
state_r, timer_r, refcnt_r, cke_r, addr_r, sd_dout_r, sd_busdir_r, sd_dqmu_r, sd_dqml_r, ready_r,
bank_s, row_s, col_s,
rw_i, refresh_i, addr_i, data_i, we_i, ub_i, lb_i,
buf_dout_r, sdData_io)
begin
state_x <= state_r; -- Stay in the same state unless changed.
timer_x <= timer_r; -- Hold the cycle timer by default.
refcnt_x <= refcnt_r; -- Hold the refresh timer by default.
cke_x <= cke_r; -- Stay in the same clock mode unless changed.
cmd_x <= CMD_NOP; -- Default to NOP unless changed.
bank_x <= bank_r; -- Register the SDRAM bank.
addr_x <= addr_r; -- Register the SDRAM address.
sd_dout_x <= sd_dout_r; -- Register the SDRAM write data.
sd_busdir_x <= sd_busdir_r; -- Register the SDRAM bus tristate control.
sd_dqmu_x <= sd_dqmu_r;
sd_dqml_x <= sd_dqml_r;
buf_dout_x <= buf_dout_r; -- SDRAM to host data buffer.
ready_x <= ready_r; -- Always ready unless performing initialization.
done_o <= '0'; -- Done tick, single cycle.
if timer_r /= 0 then
timer_x <= timer_r - 1;
else
cke_x <= '1';
bank_x <= bank_s;
addr_x <= "0000" & col_s; -- A10 low for rd/wr commands to suppress auto-precharge.
sd_dqmu_x <= '0';
sd_dqml_x <= '0';
case state_r is
when ST_INIT_WAIT =>
-- 1. Wait 200us with DQM signals high, cmd NOP.
-- 2. Precharge all banks.
-- 3. Eight refresh cycles.
-- 4. Set mode register.
-- 5. Eight refresh cycles.
state_x <= ST_INIT_PRECHARGE;
timer_x <= 20000; -- Wait 200us (20,000 cycles).
-- timer_x <= 2; -- for simulation
sd_dqmu_x <= '1';
sd_dqml_x <= '1';
when ST_INIT_PRECHARGE =>
state_x <= ST_INIT_REFRESH1;
refcnt_x <= 8; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
cmd_x <= CMD_PRECHARGE;
timer_x <= 2; -- Wait 2 cycles plus state overhead for 20ns Trp.
bank_x <= "00";
addr_x(10) <= '1'; -- Precharge all banks.
when ST_INIT_REFRESH1 =>
if refcnt_r = 0 then
state_x <= ST_INIT_MODE;
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 7; -- Wait 7 cycles plus state overhead for 70ns refresh.
end if;
when ST_INIT_MODE =>
state_x <= ST_INIT_REFRESH2;
refcnt_x <= 8; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
bank_x <= "00";
addr_x <= MODE_REG;
cmd_x <= CMD_MODE;
timer_x <= 2; -- Trsc == 2 cycles after issuing MODE command.
when ST_INIT_REFRESH2 =>
if refcnt_r = 0 then
state_x <= ST_IDLE;
ready_x <= '1';
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 7; -- Wait 7 cycles plus state overhead for 70ns refresh.
end if;
--
-- Normal Operation
--
-- Trc - 70ns - Attive to active command.
-- Trcd - 20ns - Active to read/write command.
-- Tras - 50ns - Active to precharge command.
-- Trp - 20ns - Precharge to active command.
-- TCas - 2clk - Read/write to data out.
--
-- |<----------- Trc ------------>|
-- |<----------- Tras ---------->|
-- |<- Trcd ->|<- TCas ->| |<- Trp ->|
-- T0__ T1__ T2__ T3__ T4__ T5__ T6__ T7__ T8__ T9__ T10__
-- __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
-- IDLE ACTVT NOP RD/WR NOP NOP PRECG IDLE ACTVT
-- --<Row>-------<Col>------------<Bank>-------<Row>--
-- ---------------<A10>-------------<A10>-------------------
-- ------------------<Din>------------<Dout>--------
-- ---------------<DQM>---------------
-- --<Refsh>-------------
--
-- A10 during rd/wr : 0 = disable auto-precharge, 1 = enable auto-precharge.
-- A10 during precharge: 0 = single bank, 1 = all banks.
-- T0__ T1__ T2__ T3__ T4__ T5__ T6__ T7__ T8__ T9__ T10__
-- __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
-- IDLE ACTVT NOP RD/WR NOP NOP PRECG IDLE ACTVT
-- T0__ T1__ T2__ T3__ T4__ T5__ T6__ T7__ T8__ T9__ T10__
-- __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
-- IDLE ACTVT NOP RD/WR NOP NOP PRECG IDLE ACTVT
when ST_IDLE =>
-- 60ns since activate when coming from PRECHARGE state.
-- 10ns since PRECHARGE. Trp == 20ns min.
if rw_i = '1' then
state_x <= ST_ACTIVATE;
cmd_x <= CMD_ACTIVATE;
addr_x <= row_s; -- Set bank select and row on activate command.
elsif refresh_i = '1' then
state_x <= ST_REFRESH;
cmd_x <= CMD_REFRESH;
timer_x <= 7; -- Wait 7 cycles plus state overhead for 70ns refresh.
end if;
when ST_REFRESH =>
state_x <= ST_IDLE;
done_o <= '1';
when ST_ACTIVATE =>
-- Trc (Active to Active Command Period) is 65ns min.
-- 70ns since activate when coming from PRECHARGE -> IDLE states.
-- 20ns since PRECHARGE.
-- ACTIVATE command is presented to the SDRAM. The command out of this
-- state will be NOP for one cycle.
state_x <= ST_RCD;
sd_dout_x <= data_i; -- Register any write data, even if not used.
when ST_RCD =>
-- 10ns since activate.
-- Trcd == 20ns min. The clock is 10ns, so the requirement is satisfied by this state.
-- READ or WRITE command will be active in the next cycle.
state_x <= ST_RW;
if we_i = '0' then
cmd_x <= CMD_WRITE;
sd_busdir_x <= '1'; -- The SDRAM latches the input data with the command.
sd_dqmu_x <= ub_i;
sd_dqml_x <= lb_i;
else
cmd_x <= CMD_READ;
end if;
when ST_RW =>
-- 20ns since activate.
-- READ or WRITE command presented to SDRAM.
state_x <= ST_RAS1;
sd_busdir_x <= '0';
when ST_RAS1 =>
-- 30ns since activate.
state_x <= ST_RAS2;
when ST_RAS2 =>
-- 40ns since activate.
-- Tras (Active to precharge Command Period) 45ns min.
-- PRECHARGE command will be active in the next cycle.
state_x <= ST_PRECHARGE;
cmd_x <= CMD_PRECHARGE;
addr_x(10) <= '1'; -- Precharge all banks.
buf_dout_x <= sdData_io;
when ST_PRECHARGE =>
-- 50ns since activate.
-- PRECHARGE presented to SDRAM.
state_x <= ST_IDLE;
done_o <= '1'; -- Read data is ready and should be latched by the host.
timer_x <= 1; -- Buffer to make sure host takes down memory request before going IDLE.
end case;
end if;
end process;
process (clk_100m0_i)
begin
if rising_edge(clk_100m0_i) then
if clk_en = '1' then
if reset_i = '1' then
state_r <= ST_INIT_WAIT;
timer_r <= 0;
cmd_r <= CMD_NOP;
cke_r <= '0';
ready_r <= '0';
else
state_r <= state_x;
timer_r <= timer_x;
refcnt_r <= refcnt_x;
cke_r <= cke_x; -- CKE to SDRAM.
cmd_r <= cmd_x; -- Command to SDRAM.
bank_r <= bank_x; -- Bank to SDRAM.
addr_r <= addr_x; -- Address to SDRAM.
sd_dout_r <= sd_dout_x; -- Data to SDRAM.
sd_busdir_r <= sd_busdir_x; -- SDRAM bus direction.
sd_dqmu_r <= sd_dqmu_x; -- Upper byte enable to SDRAM.
sd_dqml_r <= sd_dqml_x; -- Lower byte enable to SDRAM.
ready_r <= ready_x;
buf_dout_r <= buf_dout_x;
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/usb3_ft600x/hdl/usb3_ft600x.vhd
|
1
|
2942
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity usb3_ft600x is
generic (
CLK_PROC_FREQ : integer;
OUT0_SIZE : integer;
OUT1_SIZE : integer;
IN0_SIZE : integer;
IN1_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
ftreset_n : out std_logic;
ftclk : in std_logic;
be : inout std_logic_vector(1 downto 0);
data : inout std_logic_vector(15 downto 0);
txe_n : in std_logic;
rxf_n : in std_logic;
siwu_n : out std_logic;
wr_n : out std_logic;
rd_n : out std_logic;
oe_n : out std_logic;
------------------------ out0 flow ----------------------
out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0);
out0_fv : out std_logic;
out0_dv : out std_logic;
------------------------ out1 flow ----------------------
out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0);
out1_fv : out std_logic;
out1_dv : out std_logic;
------------------------ in0 flow -----------------------
in0_data : in std_logic_vector(IN0_SIZE-1 downto 0);
in0_fv : in std_logic;
in0_dv : in std_logic;
------------------------ in1 flow -----------------------
in1_data : in std_logic_vector(IN1_SIZE-1 downto 0);
in1_fv : in std_logic;
in1_dv : in std_logic
);
end usb3_ft600x;
architecture rtl of usb3_ft600x is
type read_sm is (w_wait, w_start_read, w_start_read2, w_start_read3, w_read);
signal read_sm_state : read_sm := w_wait;
begin
ftreset_n <= reset_n;
process (ftclk, reset_n)
begin
if(reset_n = '0') then
wr_n <= '1';
rd_n <= '1';
oe_n <= '1';
data <= "ZZZZZZZZZZZZZZZZ";
be <= "ZZ";
read_sm_state <= w_wait;
elsif(rising_edge(ftclk)) then
case read_sm_state is
when w_wait =>
wr_n <= '1';
rd_n <= '1';
oe_n <= '1';
if(rxf_n = '0') then
read_sm_state <= w_start_read;
end if;
when w_start_read =>
read_sm_state <= w_start_read2;
data <= "ZZZZZZZZZZZZZZZZ";
be <= "ZZ";
when w_start_read2 =>
read_sm_state <= w_start_read3;
oe_n <= '0';
when w_start_read3 =>
read_sm_state <= w_read;
rd_n <= '0';
when w_read =>
out0_data <= data(7 downto 0);
if(rxf_n = '1') then
read_sm_state <= w_wait;
end if;
when others =>
end case;
end if;
end process;
end rtl;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/uC/AVR8.vhd
|
2
|
32312
|
--************************************************************************************************
-- Top entity for AVR microcontroller (for synthesis) with JTAG OCD and DMAs
-- Version 0.5 (Version for Xilinx)
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
--************************************************************************************************
-- Adapted for AtomFPGA
-- input clock is now 16MHz
--************************************************************************************************
--************************************************************************************************
--Adapted for the Papilio FPGA development board. To learn more visit http://papilio.cc
--Gadget Factory Note: This project is currently configured for the Papilio One board Version 2.03 or greater. It assumes a 32Mhz oscillator and a ucf with a period of 31.25.
--*************************************************************************************************
--*************************************************************************************************
--This is AVR8-based SoC for processing diode signals
--modifications by Zvonimir Bandic
--modified 01/05/2013
--*************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
use WORK.AVR_uC_CompPack.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
use WORK.spi_mod_comp_pack.all; --SPI
use WORK.spi_slv_sel_comp_pack.all;
use WORK.MemAccessCtrlPack.all;
use WORK.MemAccessCompPack.all;
entity AVR8 is
generic (
CDATAMEMSIZE : integer;
CPROGMEMSIZE : integer
);
port (
nrst : in std_logic; --Uncomment this to connect reset to an external pushbutton. Must be defined in ucf.
clk16M : in std_logic;
portaout : out std_logic_vector(7 downto 0);
portain : in std_logic_vector(7 downto 0);
portbout : out std_logic_vector(7 downto 0);
portbin : in std_logic_vector(7 downto 0);
portc : inout std_logic_vector(7 downto 0);
portdin : in std_logic_vector(7 downto 0);
portdout : out std_logic_vector(7 downto 0);
portein : in std_logic_vector(7 downto 0);
porteout : out std_logic_vector(7 downto 0);
portf : inout std_logic_vector(7 downto 0);
spi_mosio : out std_logic;
spi_scko : out std_logic;
spi_cs_n : out std_logic;
spi_misoi : in std_logic;
-- UART
rxd : in std_logic;
txd : out std_logic
);
end AVR8;
architecture Struct of AVR8 is
-- Use these setting to control which peripherals you want to include with your custom AVR8 implementation.
constant CImplPORTA : boolean := TRUE; -- set to false here for portA and portB, or DDRAreg and DDRBreg
constant CImplPORTB : boolean := TRUE;
constant CImplPORTC : boolean := FALSE;
constant CImplPORTD : boolean := TRUE;
constant CImplPORTE : boolean := TRUE;
constant CImplPORTF : boolean := FALSE;
constant CImplUART : boolean := TRUE; --AVR8 UART peripheral
constant CImplSPI : boolean := FALSE; -- adding SPI master
constant CImplTmrCnt : boolean := FALSE; --AVR8 Timer
constant CImplExtIRQ : boolean := FALSE; --AVR8 Interrupt Unit
-- ############################## Signals connected directly to the core ##########################################
signal core_cpuwait : std_logic;
-- Program memory
signal core_pc : std_logic_vector (15 downto 0); -- PROM address
signal core_inst : std_logic_vector (15 downto 0); -- PROM data
-- I/O registers
signal core_adr : std_logic_vector (15 downto 0);
signal core_iore : std_logic;
signal core_iowe : std_logic;
-- Data memery
signal core_ramadr : std_logic_vector (15 downto 0);
signal core_ramre : std_logic;
signal core_ramwe : std_logic;
signal core_dbusin : std_logic_vector (7 downto 0);
signal core_dbusout : std_logic_vector (7 downto 0);
-- Interrupts
signal core_irqlines : std_logic_vector(22 downto 0);
signal core_irqack : std_logic;
signal core_irqackad : std_logic_vector(4 downto 0);
-- ###############################################################################################################
-- ############################## Signals connected directly to the SRAM controller ###############################
signal ram_din : std_logic_vector(7 downto 0);
-- ###############################################################################################################
-- ####################### Signals connected directly to the external multiplexer ################################
signal io_port_out : ext_mux_din_type;
signal io_port_out_en : ext_mux_en_type;
signal ind_irq_ack : std_logic_vector(core_irqlines'range);
-- ###############################################################################################################
-- ################################## Reset signals #############################################
signal core_ireset : std_logic;
-- ##############################################################################################
-- Port signals
signal PortAReg : std_logic_vector(portain'range);
signal DDRAReg : std_logic_vector(portain'range);
signal PortBReg : std_logic_vector(portbin'range);
signal DDRBReg : std_logic_vector(portbin'range);
signal PortCReg : std_logic_vector(portc'range);
signal DDRCReg : std_logic_vector(portc'range);
signal PortDReg : std_logic_vector(portdin'range);
signal DDRDReg : std_logic_vector(portdin'range);
signal PortEReg : std_logic_vector(portein'range);
signal DDREReg : std_logic_vector(portein'range);
signal PortFReg : std_logic_vector(portf'range);
signal DDRFReg : std_logic_vector(portf'range);
-- Added for Synopsys compatibility
signal gnd : std_logic;
signal vcc : std_logic;
-- Sleep support
signal core_cp2 : std_logic; -- Global clock signal after gating(and global primitive)
signal sleep_en : std_logic;
signal sleepi : std_logic;
signal irqok : std_logic;
signal globint : std_logic;
signal nrst_clksw : std_logic; -- Separate reset for clock gating module
-- Watchdog related signals
signal wdtmout : std_logic; -- Watchdog overflow
signal core_wdri : std_logic; -- Watchdog clear
-- ********************** JTAG and memory **********************************************
-- PM address,data and control
signal pm_adr : std_logic_vector(core_pc'range);
signal pm_h_we : std_logic;
signal pm_l_we : std_logic;
signal pm_din : std_logic_vector(core_inst'range);
signal pm_dout : std_logic_vector(core_inst'range);
signal TDO_Out : std_logic;
signal TDO_OE : std_logic;
signal JTAG_Rst : std_logic;
-- ********************** JTAG and memory **********************************************
signal nrst_cp64m_tmp : std_logic;
signal ram_cp2_n : std_logic;
signal sleep_mode : std_logic;
-- "EEPROM" related signals
signal EEPrgSel : std_logic;
signal EEAdr : std_logic_vector(11 downto 0);
signal EEWrData : std_logic_vector(7 downto 0);
signal EERdData : std_logic_vector(7 downto 0);
signal EEWr : std_logic;
-- New
signal busmin : MastersOutBus_Type;
signal busmwait : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
signal slv_outs : SlavesOutBus_Type;
signal ram_sel : std_logic;
-- UART DMA
signal udma_mack : std_logic;
signal mem_mux_out : std_logic_vector (7 downto 0);
-- Place Holder Signals for JTAG instead of connecting them externally
signal TRSTn : std_logic;
signal TMS : std_logic;
signal TCK : std_logic;
signal TDI : std_logic;
signal TDO : std_logic;
-- AES
signal aes_mack : std_logic;
-- Address decoder
signal stb_IO : std_logic;
signal stb_IOmod : std_logic_vector (CNumOfSlaves-1 downto 0);
signal ram_ce : std_logic;
signal slv_cpuwait : std_logic;
-- Memory i/f
signal mem_ramadr : std_logic_vector (15 downto 0);
signal mem_ram_dbus_in : std_logic_vector (7 downto 0);
signal mem_ram_dbus_out : std_logic_vector (7 downto 0);
signal mem_ramwe : std_logic;
signal mem_ramre : std_logic;
-- RAM
signal ram_ramwe : std_logic;
-- nrst
--signal nrst : std_logic; --Comment this to connect reset to an external pushbutton.
-- ############################## Signals connected directly to the I/O registers ################################
-- PortA
signal porta_dbusout : std_logic_vector (7 downto 0);
signal porta_out_en : std_logic;
-- PortB
signal portb_dbusout : std_logic_vector (7 downto 0);
signal portb_out_en : std_logic;
-- PortC
signal portc_dbusout : std_logic_vector (7 downto 0);
signal portc_out_en : std_logic;
-- PortD
signal portd_dbusout : std_logic_vector (7 downto 0);
signal portd_out_en : std_logic;
-- PortE
signal porte_dbusout : std_logic_vector (7 downto 0);
signal porte_out_en : std_logic;
-- PortF
signal portf_dbusout : std_logic_vector (7 downto 0);
signal portf_out_en : std_logic;
-- Timer/Counter
signal tc_dbusout : std_logic_vector (7 downto 0);
signal tc_out_en : std_logic;
-- Ext IRQ Controller
signal extirq_dbusout : std_logic_vector (7 downto 0);
signal extirq_out_en : std_logic;
signal ext_irqlines : std_logic_vector(7 downto 0);
-- UART
signal uart_dbusout : std_logic_vector (7 downto 0);
signal uart_out_en : std_logic;
-- SPI
constant c_spi_slvs_num : integer := 1;
--signal spi_misoi : std_logic;
signal spi_mosii : std_logic;
signal spi_scki : std_logic;
signal spi_ss_b : std_logic;
signal spi_misoo : std_logic;
--signal spi_mosio : std_logic;
--signal spi_scko : std_logic;
signal spi_spe : std_logic;
signal spi_spimaster : std_logic;
signal spi_dbusout : std_logic_vector (7 downto 0);
signal spi_out_en : std_logic;
-- Slave selects
signal spi_slv_sel_n : std_logic_vector(c_spi_slvs_num-1 downto 0);
-- SPI
-- ###############################################################################################################
-- ############################## Define Signals for User Cores ##################################################
-- Example Core - - core9
--signal core9_input_sig : std_logic_vector(1 downto 0); --Define a signal for the inputs.
-- ###############################################################################################################
begin
-- Added for Synopsys compatibility
gnd <= '0';
vcc <= '1';
-- Added for Synopsys compatibility
--nrst <= '1'; --Comment this to connect reset to an external pushbutton.
core_inst <= pm_dout;
--Signals to connect peripherals controlled from Generics to the physical ports
-- ****************** User Cores - Instantiate User Cores Here **************************
-- ****************** END User Cores - Instantiate User Cores Here **************************
-- Unused IRQ lines
--core_irqlines(7 downto 4) <= ( others => '0');
--core_irqlines(3 downto 0) <= ( others => '0');
core_irqlines(13 downto 10) <= ( others => '0');
--core_irqlines(16) <= '0'; --now used by SPI
core_irqlines(22 downto 20) <= ( others => '0');
-- ************************
-- Unused out_en
io_port_out_en(11 to 15) <= (others => '0');
io_port_out(11 to 15) <= (others => (others => '0'));
AVR_Core_Inst:component AVR_Core port map(
--Clock and reset
cp2 => core_cp2,
cp2en => vcc,
ireset => core_ireset,
-- JTAG OCD support
valid_instr => open,
insert_nop => gnd,
block_irq => gnd,
change_flow => open,
-- Program Memory
pc => core_pc,
inst => core_inst,
-- I/O control
adr => core_adr,
iore => core_iore,
iowe => core_iowe,
-- Data memory control
ramadr => core_ramadr,
ramre => core_ramre,
ramwe => core_ramwe,
cpuwait => core_cpuwait,
-- Data paths
dbusin => core_dbusin,
dbusout => core_dbusout,
-- Interrupts
irqlines => core_irqlines,
irqack => core_irqack,
irqackad => core_irqackad,
--Sleep Control
sleepi => sleepi,
irqok => irqok,
globint => globint,
--Watchdog
wdri => core_wdri);
RAM_Data_Register:component RAMDataReg port map(
ireset => core_ireset,
cp2 => clk16M, -- clk,
cpuwait => core_cpuwait,
RAMDataIn => core_dbusout,
RAMDataOut => ram_din
);
EXT_MUX:component external_mux port map(
ramre => mem_ramre, -- ramre output of the arbiter and multiplexor
dbus_out => core_dbusin, -- Data input of the core
ram_data_out => mem_mux_out, -- Data output of the RAM mux(RAM or memory located I/O)
io_port_bus => io_port_out, -- Data outputs of the I/O
io_port_en_bus => io_port_out_en, -- Out enable outputs of I/O
irqack => core_irqack,
irqackad => core_irqackad,
ind_irq_ack => ind_irq_ack -- Individual interrupt acknolege for the peripheral
);
-- ****************** PORTA **************************
PORTA_Impl:if CImplPORTA generate
PORTA_COMP:component pport
generic map(PPortNum => 0)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porta_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porta_out_en,
-- External connection
portx => PortAReg,
ddrx => DDRAReg,
pinx => portain,
irqlines => open);
-- PORTA connection to the external multiplexer
io_port_out(0) <= porta_dbusout;
io_port_out_en(0) <= porta_out_en;
---- Tri-state control for PORTA
--PortAZCtrl:for i in porta'range generate
--porta(i) <= PortAReg(i) when DDRAReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTA
PortAZCtrl:for i in portaout'range generate
portaout(i) <= PortAReg(i) when DDRAReg(i)='1' else '0';
end generate;
end generate;
PORTA_Not_Impl:if not CImplPORTA generate
portaout <= (others => '0');
end generate;
-- ****************** PORTB **************************
PORTB_Impl:if CImplPORTB generate
PORTB_COMP:component pport
generic map (PPortNum => 1)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portb_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portb_out_en,
-- External connection
portx => PortBReg,
ddrx => DDRBReg,
pinx => portbin,
irqlines => ext_irqlines);
-- PORTB connection to the external multiplexer
io_port_out(1) <= portb_dbusout;
io_port_out_en(1) <= portb_out_en;
---- Tri-state control for PORTB
--PortBZCtrl:for i in portb'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTB
PortBZCtrl:for i in portbout'range generate
--portb(i) <= PortBReg(i) when DDRBReg(i)='1' else 'Z';
portbout(i) <= PortBReg(i) when DDRBReg(i)='1' else '0';
end generate;
end generate;
PORTB_Not_Impl:if not CImplPORTB generate
portbout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTC **************************
PORTC_Impl:if CImplPORTC generate
PORTC_COMP:component pport
generic map(PPortNum => 2)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portc_out_en,
-- External connection
portx => PortCReg,
ddrx => DDRCReg,
pinx => portc,
irqlines => open);
-- PORTC connection to the external multiplexer
io_port_out(5) <= portc_dbusout;
io_port_out_en(5) <= portc_out_en;
---- Tri-state control for PORTC
--PortCZCtrl:for i in portc'range generate
--portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTC
PortCZCtrl:for i in portc'range generate
portc(i) <= PortCReg(i) when DDRCReg(i)='1' else 'Z';
end generate;
end generate;
PORTC_Not_Impl:if not CImplPORTC generate
portc <= (others => 'Z');
end generate;
-- ****************** PORTD **************************
PORTD_Impl:if CImplPORTD generate
PORTD_COMP:component pport
generic map (PPortNum => 3)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portd_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portd_out_en,
-- External connection
portx => PortDReg,
ddrx => DDRDReg,
pinx => portdin,
irqlines => open);
-- PORTD connection to the external multiplexer
io_port_out(6) <= portd_dbusout;
io_port_out_en(6) <= portd_out_en;
---- Tri-state control for PORTD
--PortDZCtrl:for i in portd'range generate
--portd(i) <= PortDReg(i) when DDRDReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTD
PortDZCtrl:for i in portdout'range generate
portdout(i) <= PortDReg(i) when DDRDReg(i)='1' else '0';
end generate;
end generate;
PORTD_Not_Impl:if not CImplPORTD generate
portdout <= (others => '0');
end generate;
-- ************************************************
-- ****************** PORTE **************************
PORTE_Impl:if CImplPORTE generate
PORTE_COMP:component pport
generic map(PPortNum => 4)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => porte_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => porte_out_en,
-- External connection
portx => PortEReg,
ddrx => DDREReg,
pinx => portein,
irqlines => open);
-- PORTE connection to the external multiplexer
io_port_out(7) <= porte_dbusout;
io_port_out_en(7) <= porte_out_en;
---- Tri-state control for PORTE
--PortEZCtrl:for i in porte'range generate
--porte(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
--end generate;
-- Tri-state control for PORTE
PortEZCtrl:for i in porteout'range generate
porteout(i) <= PortEReg(i) when DDREReg(i)='1' else 'Z';
end generate;
end generate;
PORTE_Not_Impl:if not CImplPORTE generate
porteout <= (others => 'Z');
end generate;
-- ****************** PORTF **************************
PORTF_Impl:if CImplPORTF generate
PORTF_COMP:component pport
generic map (PPortNum => 5)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => portf_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => portf_out_en,
-- External connection
portx => PortFReg,
ddrx => DDRFReg,
pinx => portf,
irqlines => open);
-- PORTF connection to the external multiplexer
io_port_out(8) <= portf_dbusout;
io_port_out_en(8) <= portf_out_en;
-- Tri-state control for PORTF
PortFZCtrl:for i in portf'range generate
portf(i) <= PortFReg(i) when DDRFReg(i)='1' else 'Z';
end generate;
end generate;
PORTF_Not_Impl:if not CImplPORTF generate
portf <= (others => 'Z');
end generate;
-- ************************************************
--****************** External IRQ Controller**************************
ExtIRQ_Impl:if CImplExtIRQ generate
ExtIRQ_Inst:component ExtIRQ_Controller port map(
-- AVR Control
nReset => core_ireset,
clk => clk16M, -- clk,
clken => vcc,
irq_clken => vcc,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => extirq_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => extirq_out_en,
------------------------------------------------
extpins => ext_irqlines,
INTx => core_irqlines(7 downto 0));
-- ExtIRQ connection to the external multiplexer
io_port_out(10) <= extirq_dbusout;
io_port_out_en(10) <= extirq_out_en;
end generate;
--****************** Timer/Counter **************************
TmrCnt_Impl:if CImplTmrCnt generate
TmrCnt_Inst:component Timer_Counter port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M, -- clk,
cp2en => vcc,
tmr_cp2en => vcc,
stopped_mode => gnd,
tmr_running => gnd,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => tc_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => tc_out_en,
-- External inputs/outputs
EXT1 => gnd,
EXT2 => gnd,
OC0_PWM0 => open,
OC1A_PWM1A => open,
OC1B_PWM1B => open,
OC2_PWM2 => open,
-- Interrupt related signals
TC0OvfIRQ => core_irqlines(15), -- Timer/Counter0 overflow ($0020)
TC0OvfIRQ_Ack => ind_irq_ack(15),
TC0CmpIRQ => core_irqlines(14), -- Timer/Counter0 Compare Match ($001E)
TC0CmpIRQ_Ack => ind_irq_ack(14),
TC2OvfIRQ => core_irqlines(9), -- Timer/Counter2 overflow ($0014)
TC2OvfIRQ_Ack => ind_irq_ack(9),
TC2CmpIRQ => core_irqlines(8), -- Timer/Counter2 Compare Match ($0012)
TC2CmpIRQ_Ack => ind_irq_ack(8),
TC1OvfIRQ => open,
TC1OvfIRQ_Ack => gnd,
TC1CmpAIRQ => open,
TC1CmpAIRQ_Ack => gnd,
TC1CmpBIRQ => open,
TC1CmpBIRQ_Ack => gnd,
TC1ICIRQ => open,
TC1ICIRQ_Ack => gnd,
PWM0bit => open,
PWM10bit => open,
PWM11bit => open,
PWM2bit => open);
-- Timer/Counter connection to the external multiplexer
io_port_out(4) <= tc_dbusout;
io_port_out_en(4) <= tc_out_en;
end generate;
-- Watchdog is not implemented
wdtmout <= '0';
-- Reset generator
ResetGenerator_Inst:component ResetGenerator port map(
-- Clock inputs
cp2 => clk16M, -- clk,
cp64m => gnd,
-- Reset inputs
nrst => nrst,
npwrrst => vcc,
wdovf => wdtmout,
jtagrst => JTAG_Rst,
-- Reset outputs
nrst_cp2 => core_ireset,
nrst_cp64m => nrst_cp64m_tmp,
nrst_clksw => nrst_clksw
);
ClockGatingDis:if not CImplClockSw generate
core_cp2 <= clk16M;
end generate;
-- ********************** JTAG and memory **********************************************
ram_cp2_n <= not clk16M;
---- Data memory(8-bit)
DM_Inst : entity work.XDM
generic map (
WIDTH => 8,
SIZE => CDATAMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => mem_ramadr(f_log2(CDATAMEMSIZE) - 1 downto 0),
din => mem_ram_dbus_in,
dout => mem_ram_dbus_out,
we => ram_ramwe
);
-- Program memory
PM_Inst : entity work.XPM
generic map (
WIDTH => 16,
SIZE => CPROGMEMSIZE
)
port map(
cp2 => ram_cp2_n,
ce => vcc,
address => pm_adr(f_log2(CPROGMEMSIZE) - 1 downto 0),
din => pm_din,
dout => pm_dout,
we => pm_l_we
);
-- ********************** JTAG and memory **********************************************
-- Sleep mode is not implemented
sleep_mode <= '0';
JTAGOCDPrgTop_Inst:component JTAGOCDPrgTop port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
-- JTAG related inputs/outputs
TRSTn => TRSTn, -- Optional
TMS => TMS,
TCK => TCK,
TDI => TDI,
TDO => TDO_Out,
TDO_OE => TDO_OE,
-- From the core
PC => core_pc,
-- To the PM("Flash")
pm_adr => pm_adr,
pm_h_we => pm_h_we,
pm_l_we => pm_l_we,
pm_dout => pm_dout,
pm_din => pm_din,
-- To the "EEPROM"
EEPrgSel => EEPrgSel,
EEAdr => EEAdr,
EEWrData => EEWrData,
EERdData => EERdData,
EEWr => EEWr,
-- CPU reset
jtag_rst => JTAG_Rst
);
-- JTAG OCD module connection to the external multiplexer
io_port_out(3) <= (others => '0');
io_port_out_en(3) <= gnd;
TDO <= TDO_Out when TDO_OE='1' else 'Z';
-- *******************************************************************************************************
-- DMA, Memory decoder, ...
-- *******************************************************************************************************
-- ****************** SPI **************************
spi_is_used:if CImplSPI generate
spi_mod_inst:component spi_mod port map(
-- AVR Control
ireset => core_ireset,
cp2 => clk16M,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => spi_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => spi_out_en,
-- SPI i/f
misoi => spi_misoi,
mosii => spi_mosii,
scki => spi_scki,
ss_b => spi_ss_b,
misoo => spi_misoo,
mosio => spi_mosio,
scko => spi_scko,
spe => spi_spe,
spimaster => spi_spimaster,
-- IRQ
spiirq => core_irqlines(16),
spiack => ind_irq_ack(16),
-- Slave Programming Mode
por => gnd,
spiextload => gnd,
spidwrite => open,
spiload => open
);
-- SPI connection to the external multiplexer
io_port_out(9) <= spi_dbusout;
io_port_out_en(9) <= spi_out_en;
-- Pads
--mosi_SIG <= spi_mosio when (spi_spimaster='1') else 'Z';
--miso_SIG <= spi_misoo when (spi_spimaster='0') else 'Z';
--sck_SIG <= spi_scko when (spi_spimaster='1') else 'Z';
--
--spi_misoi <= miso_SIG;
--spi_mosii <= mosi_SIG;
--spi_scki <= sck_SIG;
spi_ss_b <= vcc;
-- Pads
spi_slv_sel_inst:component spi_slv_sel generic map(num_of_slvs => c_spi_slvs_num)
port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => open,
iore => core_iore,
iowe => core_iowe,
out_en => open,
-- Output
slv_sel_n => spi_slv_sel_n
);
end generate;
spi_cs_n <= spi_slv_sel_n(0);
no_spi:if not CImplSPI generate
--mosi_SIG <= 'Z';
--miso_SIG <= 'Z';
--sck_SIG <= 'Z';
--io_slv_out(1).dbusout <= (others => '0');
--io_slv_out(1).out_en <= gnd;
spi_slv_sel_n <= (others => '1');
end generate;
uart_Inst:component uart port map(
-- AVR Control
ireset => core_ireset,
cp2 => core_cp2,
adr => core_adr,
dbus_in => core_dbusout,
dbus_out => uart_dbusout,
iore => core_iore,
iowe => core_iowe,
out_en => uart_out_en,
-- UART
rxd => rxd,
rx_en => open,
txd => txd,
tx_en => open,
-- IRQ
txcirq => core_irqlines(19),
txc_irqack => ind_irq_ack(19),
udreirq => core_irqlines(18),
rxcirq => core_irqlines(17)
);
-- UART connection to the external multiplexer
io_port_out(2) <= uart_dbusout;
io_port_out_en(2) <= uart_out_en;
-- Arbiter and mux
ArbiterAndMux_Inst:component ArbiterAndMux port map(
--Clock and reset
ireset => core_ireset,
cp2 => core_cp2,
-- Bus masters
busmin => busmin,
busmwait => busmwait,
-- Memory Address,Data and Control
ramadr => mem_ramadr,
ramdout => mem_ram_dbus_in,
ramre => mem_ramre,
ramwe => mem_ramwe,
cpuwait => slv_cpuwait
);
-- cpuwait
slv_cpuwait <= '0';
-- Core connection
busmin(0).ramadr <= core_ramadr;
busmin(0).dout <= ram_din; -- !!!
busmin(0).ramre <= core_ramre;
busmin(0).ramwe <= core_ramwe;
core_cpuwait <= busmwait(0);
-- UART DMA connection
busmin(1).ramadr <= (others => '0');
busmin(1).dout <= (others => '0'); -- !!!
busmin(1).ramre <= gnd;
busmin(1).ramwe <= gnd;
udma_mack <= not busmwait(1);
-- AES DMA connection
busmin(2).ramadr <= (others => '0');
busmin(2).dout <= (others => '0');
busmin(2).ramre <= gnd;
busmin(2).ramwe <= gnd;
aes_mack <= not busmwait(2);
-- UART DMA slave part
slv_outs(0).dout <= (others => '0');
slv_outs(0).out_en <= gnd;
-- AES DMA slave part
slv_outs(1).dout <= (others => '0');
slv_outs(1).out_en <= gnd;
-- Memory read mux
MemRdMux_inst:component MemRdMux port map(
slv_outs => slv_outs,
ram_sel => ram_sel, -- Data RAM selection(optional input)
ram_dout => mem_ram_dbus_out, -- Data memory output (From RAM)
dout => mem_mux_out -- Data output (To the core and other bus masters)
);
-- Address decoder
RAMAdrDcd_Inst:component RAMAdrDcd port map(
ramadr => mem_ramadr,
ramre => mem_ramre,
ramwe => mem_ramwe,
-- Memory mapped I/O i/f
stb_IO => stb_IO,
stb_IOmod => stb_IOmod,
-- Data memory i/f
ram_we => ram_ramwe,
ram_ce => ram_ce,
ram_sel => ram_sel
);
end Struct;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/fastfilter/hdl/components/neighExtractor2.vhd
|
1
|
6979
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity neighExtractor2 is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector((PIXEL_SIZE-1) downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out pixel_array (0 to (KERNEL_SIZE * KERNEL_SIZE)- 1);
out_dv : out std_logic;
out_fv : out std_logic
);
end neighExtractor2;
architecture rtl of neighExtractor2 is
-- signals
signal pixel_out : pixel_array(0 to KERNEL_SIZE-1);
-- components
component taps
generic (
PIXEL_SIZE : integer;
TAPS_WIDTH : integer;
KERNEL_SIZE : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE-1 downto 0);
taps_data : out pixel_array (0 to KERNEL_SIZE -1 );
out_data : out std_logic_vector (PIXEL_SIZE-1 downto 0)
);
end component;
component bit_taps2
generic (
TAPS_WIDTH : integer
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic;
out_data : out std_logic
);
end component;
signal all_valid : std_logic;
signal s_valid : std_logic;
signal tmp_dv : std_logic;
signal tmp_fv : std_logic;
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv;
s_valid <= all_valid and enable;
----------------------------------------------------
-- SUPER FOR GENERATE : GO
----------------------------------------------------
taps_inst : for i in 0 to KERNEL_SIZE-1 generate
-- First line
gen_1 : if i=0 generate
gen1_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH ,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => in_data,
taps_data => out_data(0 to KERNEL_SIZE-1),
out_data => pixel_out(0)
);
end generate gen_1;
-- line i
gen_i : if i>0 and i<KERNEL_SIZE-1 generate
geni_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => IMAGE_WIDTH,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data(i * KERNEL_SIZE to KERNEL_SIZE*(i+1)-1),
out_data => pixel_out(i)
);
end generate gen_i;
-- Last line
gen_last : if i= (KERNEL_SIZE-1) generate
gen_last_inst : taps
generic map(
PIXEL_SIZE => PIXEL_SIZE,
TAPS_WIDTH => KERNEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE
)
port map(
clk => clk,
reset_n => reset_n,
enable => s_valid,
in_data => pixel_out(i-1),
taps_data => out_data((KERNEL_SIZE-1) * KERNEL_SIZE to KERNEL_SIZE*KERNEL_SIZE - 1),
out_data => OPEN
);
end generate gen_last;
end generate taps_inst;
--------------------------------------------------------------------------
-- Manage out_dv and out_fv
--------------------------------------------------------------------------
dv_proc : process(clk)
-- 12 bits is enought to count until 4096
constant NBITS_DELAY : integer := 20;
variable delay_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
variable edge_cmp : unsigned (NBITS_DELAY-1 downto 0) :=(others => '0');
begin
if (reset_n = '0') then
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <='0';
tmp_fv <='0';
elsif (rising_edge(clk)) then
if(enable = '1') then
if (in_fv = '1') then
if(in_dv = '1') then
-- Initial delay : Wait until there is data in all the taps
if (delay_cmp >= to_unsigned((KERNEL_SIZE-1)*IMAGE_WIDTH + KERNEL_SIZE - 1 , NBITS_DELAY)) then
-- Taps are full : Frame can start
tmp_fv <= '1';
if ( edge_cmp > to_unsigned (IMAGE_WIDTH - KERNEL_SIZE, NBITS_DELAY)) then
-- If at edge : data is NOT valid
if ( edge_cmp = to_unsigned (IMAGE_WIDTH - 1, NBITS_DELAY)) then
edge_cmp := (others => '0');
tmp_dv <= '0';
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
end if;
-- Else : Data is valid
else
edge_cmp := edge_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '1';
end if;
-- When taps are nor full : Frame is not valid , neither is data
else
delay_cmp := delay_cmp + to_unsigned(1,NBITS_DELAY);
tmp_dv <= '0';
tmp_fv <= '0';
end if;
else
tmp_dv <= '0';
end if;
-- When Fv = 0 (New frame comming): reset counters
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
-- When enable = 0
else
delay_cmp := (others => '0');
edge_cmp := (others => '0');
tmp_dv <= '0';
tmp_fv <= '0';
end if;
end if;
end process;
out_dv <= tmp_dv;
out_fv <= tmp_fv;
end architecture;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/JTAG_OCD_Prg/Resync1b_TCK.vhd
|
4
|
1041
|
--**********************************************************************************************
-- Resynchronizer(1 bit,TCK clock) for JTAG OCD and "Flash" controller
-- Version 0.1
-- Modified 27.05.2004
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end Resync1b_TCK;
architecture RTL of Resync1b_TCK is
signal DIn_Tmp : std_logic;
begin
ResynchronizerStageOne:process(TCK)
begin
if(TCK='0' and TCK'event) then -- Clock(Falling edge)
DIn_Tmp <= DIn; -- Stage 1
end if;
end process;
ResynchronizerStageTwo:process(TCK)
begin
if(TCK='1' and TCK'event) then -- Clock(Rising edge)
DOut <= DIn_Tmp; -- Stage 2
end if;
end process;
end RTL;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/uC/BusMastCompPack.vhd
|
4
|
4467
|
--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package BusMastCompPack is
component uart_dma_top is port(
-- Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Data memory i/f (Slave part)
stb_IO : in std_logic; -- SE
stb_module : in std_logic; -- SE
sramadr : in std_logic_vector(3 downto 0); -- ??
sramre : in std_logic;
sramwe : in std_logic;
sram_dbus_out : out std_logic_vector(7 downto 0);
sram_dbus_in : in std_logic_vector(7 downto 0);
sram_dbus_out_en : out std_logic;
-- Data memory i/f (Master part)
mramadr : out std_logic_vector(15 downto 0);
mramre : out std_logic;
mramwe : out std_logic;
mram_dbus_out : in std_logic_vector(7 downto 0);
mram_dbus_in : out std_logic_vector(7 downto 0);
mack : in std_logic;
-- UART related ports
adr : in std_logic_vector(5 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Interrupts
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
udreirq_ack : in std_logic;
rxcirq : out std_logic;
rxcirq_ack : in std_logic;
-- Wake up IRQ
wupirq : out std_logic;
wup_irqack : in std_logic;
-- External connections
rxd : in std_logic;
txd : out std_logic;
rx_en : out std_logic;
tx_en : out std_logic;
-- IE status
ie_stat : out std_logic_vector(4 downto 0)
);
end component;
component aescmdi_top is port(
-- Clock and reset
cp2 : in std_logic;
ireset : in std_logic;
-- RAM interface (Slave part)
--ssel : in std_logic;
stb_IO : in std_logic;
stb_module : in std_logic;
sramadr : in std_logic_vector(3 downto 0); -- ??
sramre : in std_logic;
sramwe : in std_logic;
sram_dbus_out : out std_logic_vector(7 downto 0);
sram_dbus_in : in std_logic_vector(7 downto 0);
sram_dbus_out_en : out std_logic;
-- RAM interface (Master part)
mramadr : out std_logic_vector(15 downto 0);
mramre : out std_logic;
mramwe : out std_logic;
mram_dbus_out : in std_logic_vector(7 downto 0);
mram_dbus_in : out std_logic_vector(7 downto 0);
mack : in std_logic;
-- Interrupt support
aes_irq : out std_logic;
aes_irqack : in std_logic
);
end component;
end BusMastCompPack;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/laplacian/hdl/laplacian_slave.vhd
|
1
|
9606
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity laplacian_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
w00_reg_m00 : out std_logic_vector(7 downto 0);
w01_reg_m01 : out std_logic_vector(7 downto 0);
w02_reg_m02 : out std_logic_vector(7 downto 0);
w10_reg_m10 : out std_logic_vector(7 downto 0);
w11_reg_m11 : out std_logic_vector(7 downto 0);
w12_reg_m12 : out std_logic_vector(7 downto 0);
w20_reg_m20 : out std_logic_vector(7 downto 0);
w21_reg_m21 : out std_logic_vector(7 downto 0);
w22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end laplacian_slave;
architecture rtl of laplacian_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
constant W00_REG_REG_ADDR : natural := 2;
constant W01_REG_REG_ADDR : natural := 3;
constant W02_REG_REG_ADDR : natural := 4;
constant W10_REG_REG_ADDR : natural := 5;
constant W11_REG_REG_ADDR : natural := 6;
constant W12_REG_REG_ADDR : natural := 7;
constant W20_REG_REG_ADDR : natural := 8;
constant W21_REG_REG_ADDR : natural := 9;
constant W22_REG_REG_ADDR : natural := 10;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
signal w00_reg_m00_reg : std_logic_vector (7 downto 0);
signal w01_reg_m01_reg : std_logic_vector (7 downto 0);
signal w02_reg_m02_reg : std_logic_vector (7 downto 0);
signal w10_reg_m10_reg : std_logic_vector (7 downto 0);
signal w11_reg_m11_reg : std_logic_vector (7 downto 0);
signal w12_reg_m12_reg : std_logic_vector (7 downto 0);
signal w20_reg_m20_reg : std_logic_vector (7 downto 0);
signal w21_reg_m21_reg : std_logic_vector (7 downto 0);
signal w22_reg_m22_reg : std_logic_vector (7 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
w00_reg_m00_reg <= "00000000";
w01_reg_m01_reg <= "00000000";
w02_reg_m02_reg <= "00000000";
w10_reg_m10_reg <= "00000000";
w11_reg_m11_reg <= "00000000";
w12_reg_m12_reg <= "00000000";
w20_reg_m20_reg <= "00000000";
w21_reg_m21_reg <= "00000000";
w22_reg_m22_reg <= "00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W00_REG_REG_ADDR, 4))=>
w00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W01_REG_REG_ADDR, 4))=>
w01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W02_REG_REG_ADDR, 4))=>
w02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W10_REG_REG_ADDR, 4))=>
w10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W11_REG_REG_ADDR, 4))=>
w11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W12_REG_REG_ADDR, 4))=>
w12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W20_REG_REG_ADDR, 4))=>
w20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W21_REG_REG_ADDR, 4))=>
w21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when std_logic_vector(to_unsigned(W22_REG_REG_ADDR, 4))=>
w22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when std_logic_vector(to_unsigned(W00_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w00_reg_m00_reg(7) & w00_reg_m00_reg(6) & w00_reg_m00_reg(5) & w00_reg_m00_reg(4) & w00_reg_m00_reg(3) & w00_reg_m00_reg(2) & w00_reg_m00_reg(1) & w00_reg_m00_reg(0);
when std_logic_vector(to_unsigned(W01_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w01_reg_m01_reg(7) & w01_reg_m01_reg(6) & w01_reg_m01_reg(5) & w01_reg_m01_reg(4) & w01_reg_m01_reg(3) & w01_reg_m01_reg(2) & w01_reg_m01_reg(1) & w01_reg_m01_reg(0);
when std_logic_vector(to_unsigned(W02_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w02_reg_m02_reg(7) & w02_reg_m02_reg(6) & w02_reg_m02_reg(5) & w02_reg_m02_reg(4) & w02_reg_m02_reg(3) & w02_reg_m02_reg(2) & w02_reg_m02_reg(1) & w02_reg_m02_reg(0);
when std_logic_vector(to_unsigned(W10_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w10_reg_m10_reg(7) & w10_reg_m10_reg(6) & w10_reg_m10_reg(5) & w10_reg_m10_reg(4) & w10_reg_m10_reg(3) & w10_reg_m10_reg(2) & w10_reg_m10_reg(1) & w10_reg_m10_reg(0);
when std_logic_vector(to_unsigned(W11_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w11_reg_m11_reg(7) & w11_reg_m11_reg(6) & w11_reg_m11_reg(5) & w11_reg_m11_reg(4) & w11_reg_m11_reg(3) & w11_reg_m11_reg(2) & w11_reg_m11_reg(1) & w11_reg_m11_reg(0);
when std_logic_vector(to_unsigned(W12_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w12_reg_m12_reg(7) & w12_reg_m12_reg(6) & w12_reg_m12_reg(5) & w12_reg_m12_reg(4) & w12_reg_m12_reg(3) & w12_reg_m12_reg(2) & w12_reg_m12_reg(1) & w12_reg_m12_reg(0);
when std_logic_vector(to_unsigned(W20_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w20_reg_m20_reg(7) & w20_reg_m20_reg(6) & w20_reg_m20_reg(5) & w20_reg_m20_reg(4) & w20_reg_m20_reg(3) & w20_reg_m20_reg(2) & w20_reg_m20_reg(1) & w20_reg_m20_reg(0);
when std_logic_vector(to_unsigned(W21_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w21_reg_m21_reg(7) & w21_reg_m21_reg(6) & w21_reg_m21_reg(5) & w21_reg_m21_reg(4) & w21_reg_m21_reg(3) & w21_reg_m21_reg(2) & w21_reg_m21_reg(1) & w21_reg_m21_reg(0);
when std_logic_vector(to_unsigned(W22_REG_REG_ADDR, 4))=>
datard_o <= "000000000000000000000000" & w22_reg_m22_reg(7) & w22_reg_m22_reg(6) & w22_reg_m22_reg(5) & w22_reg_m22_reg(4) & w22_reg_m22_reg(3) & w22_reg_m22_reg(2) & w22_reg_m22_reg(1) & w22_reg_m22_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
w00_reg_m00 <= w00_reg_m00_reg;
w01_reg_m01 <= w01_reg_m01_reg;
w02_reg_m02 <= w02_reg_m02_reg;
w10_reg_m10 <= w10_reg_m10_reg;
w11_reg_m11 <= w11_reg_m11_reg;
w12_reg_m12 <= w12_reg_m12_reg;
w20_reg_m20 <= w20_reg_m20_reg;
w21_reg_m21 <= w21_reg_m21_reg;
w22_reg_m22 <= w22_reg_m22_reg;
end rtl;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/spi_mod/spi_mod.vhd
|
4
|
20772
|
--**********************************************************************************************
-- SPI Peripheral for the AVR Core
-- Version 1.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
-- Internal resynchronizers for scki and ss_b inputs were added
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.std_library.all;
use WORK.avr_adr_pack.all;
use WORK.rsnc_comp_pack.all;
entity spi_mod is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- SPI i/f
misoi : in std_logic;
mosii : in std_logic;
scki : in std_logic; -- Resynch
ss_b : in std_logic; -- Resynch
misoo : out std_logic;
mosio : out std_logic;
scko : out std_logic;
spe : out std_logic;
spimaster : out std_logic;
-- IRQ
spiirq : out std_logic;
spiack : in std_logic;
-- Slave Programming Mode
por : in std_logic;
spiextload : in std_logic;
spidwrite : out std_logic;
spiload : out std_logic
);
end spi_mod;
architecture RTL of spi_mod is
-- Resynch
signal scki_resync : std_logic;
signal ss_b_resync : std_logic;
-- Registers
signal SPCR : std_logic_vector(7 downto 0);
alias SPIE : std_logic is SPCR(7);
alias SPEB : std_logic is SPCR(6); -- SPE in Atmel's doc
alias DORD : std_logic is SPCR(5);
alias MSTR : std_logic is SPCR(4);
alias CPOL : std_logic is SPCR(3);
alias CPHA : std_logic is SPCR(2);
alias SPR : std_logic_vector(1 downto 0) is SPCR(1 downto 0);
signal SPSR : std_logic_vector(7 downto 0);
alias SPIF : std_logic is SPSR(7);
alias WCOL : std_logic is SPSR(6);
alias SPI2X : std_logic is SPSR(0);
signal SPIE_Next : std_logic;
signal SPEB_Next : std_logic;
signal DORD_Next : std_logic;
signal CPOL_Next : std_logic;
signal CPHA_Next : std_logic;
signal SPR_Next : std_logic_vector(SPR'range);
signal SPI2X_Next : std_logic;
signal SPDR_Rc : std_logic_vector(7 downto 0);
signal SPDR_Rc_Next : std_logic_vector(7 downto 0);
signal SPDR_Sh_Current : std_logic_vector(7 downto 0);
signal SPDR_Sh_Next : std_logic_vector(7 downto 0);
signal Div_Next : std_logic_vector(5 downto 0);
signal Div_Current : std_logic_vector(5 downto 0);
signal Div_Toggle : std_logic;
signal DivCntMsb_Current : std_logic;
signal DivCntMsb_Next : std_logic;
type MstSMSt_Type is (MstSt_Idle,MstSt_B0,MstSt_B1,MstSt_B2,MstSt_B3,MstSt_B4,MstSt_B5,MstSt_B6,MstSt_B7);
signal MstSMSt_Current : MstSMSt_Type;
signal MstSMSt_Next : MstSMSt_Type;
signal TrStart : std_logic;
signal scko_Next : std_logic;
signal scko_Current : std_logic; --!!!
signal UpdRcDataRg_Current : std_logic;
signal UpdRcDataRg_Next : std_logic;
signal TmpIn_Current : std_logic;
signal TmpIn_Next : std_logic;
-- Slave
signal sck_EdgeDetDFF : std_logic;
signal SlvSampleSt : std_logic;
signal SlvSMChangeSt : std_logic;
type SlvSMSt_Type is (SlvSt_Idle,SlvSt_B0I,SlvSt_B0,SlvSt_B1,SlvSt_B2,SlvSt_B3,SlvSt_B4,SlvSt_B5,SlvSt_B6,SlvSt_B6W);
signal SlvSMSt_Current : SlvSMSt_Type;
signal SlvSMSt_Next : SlvSMSt_Type;
-- SIF clear SM
signal SPIFClrSt_Current : std_logic;
signal SPIFClrSt_Next : std_logic;
-- WCOL clear SM
signal WCOLClrSt_Current : std_logic;
signal WCOLClrSt_Next : std_logic;
signal MSTR_Next : std_logic;
signal SPIF_Next : std_logic;
signal WCOL_Next : std_logic;
signal MstDSamp_Next : std_logic;
signal MstDSamp_Current : std_logic;
function Fn_RevBitVector(InVector : std_logic_vector) return std_logic_vector is
variable TmpVect : std_logic_vector(InVector'range);
begin
for i in TmpVect'range loop
TmpVect(i) := InVector(InVector'high-i);
end loop;
return TmpVect;
end Fn_RevBitVector;
begin
-- ******************** Resynchronizers ************************************
scki_resync_inst:component rsnc_bit generic map(
add_stgs_num => 0,
inv_f_stgs => 0
)
port map(
clk => cp2,
di => scki,
do => scki_resync
);
ss_b_resync_inst:component rsnc_bit generic map(
add_stgs_num => 0,
inv_f_stgs => 0
)
port map(
clk => cp2,
di => ss_b,
do => ss_b_resync
);
-- ******************** Resynchronizers ************************************
SeqPrc:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
SPCR <= (others => '0');
SPIF <= '0';
WCOL <= '0';
SPI2X <= '0';
Div_Current <= (others => '0');
DivCntMsb_Current <= '0';
MstSMSt_Current <= MstSt_Idle;
SlvSMSt_Current <= SlvSt_Idle;
SPDR_Sh_Current <= (others => '1');
SPDR_Rc <= (others => '0');
sck_EdgeDetDFF <= '0';
SPIFClrSt_Current <= '0';
WCOLClrSt_Current <= '0';
scko <= '0';
scko_Current <= '0';
misoo <= '0';
mosio <= '0';
TmpIn_Current <= '0';
UpdRcDataRg_Current <= '0';
MstDSamp_Current <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
SPIE <= SPIE_Next;
SPEB <= SPEB_Next;
DORD <= DORD_Next;
CPOL <= CPOL_Next;
CPHA <= CPHA_Next;
SPR <= SPR_Next;
MSTR <= MSTR_Next;
SPIF <= SPIF_Next;
SPI2X <= SPI2X_Next;
WCOL <= WCOL_Next;
Div_Current <= Div_Next;
DivCntMsb_Current <= DivCntMsb_Next;
MstSMSt_Current <= MstSMSt_Next;
SlvSMSt_Current <= SlvSMSt_Next;
SPDR_Sh_Current <= SPDR_Sh_Next;
SPDR_Rc <= SPDR_Rc_Next;
sck_EdgeDetDFF <= scki_resync;
SPIFClrSt_Current <= SPIFClrSt_Next;
WCOLClrSt_Current <= WCOLClrSt_Next;
scko_Current <= scko_Next;
scko <= scko_Next;
misoo <= SPDR_Sh_Next(SPDR_Sh_Next'high);
mosio <= SPDR_Sh_Next(SPDR_Sh_Next'high);
TmpIn_Current <= TmpIn_Next;
UpdRcDataRg_Current <= UpdRcDataRg_Next;
MstDSamp_Current <= MstDSamp_Next;
end if;
end process;
IORegWriteComb:process(adr,iowe,SPCR,SPSR,dbus_in)
begin
SPIE_Next <= SPIE;
SPEB_Next <= SPEB;
DORD_Next <= DORD;
CPOL_Next <= CPOL;
CPHA_Next <= CPHA;
SPR_Next <= SPR;
SPI2X_Next <= SPI2X;
if(fn_to_integer(adr)=SPCR_Address and iowe='1') then
SPIE_Next <= dbus_in(7);
SPEB_Next <= dbus_in(6);
DORD_Next <= dbus_in(5);
CPOL_Next <= dbus_in(3);
CPHA_Next <= dbus_in(2);
SPR_Next <= dbus_in(1 downto 0);
end if;
if(fn_to_integer(adr)=SPSR_Address and iowe='1') then
SPI2X_Next <= dbus_in(0);
end if;
end process;
SPSR(5 downto 1) <= (others => '0');
-- Divider
-- SPI2X | SPR1 | SPR0 | SCK Frequency
-- 0 | 0 | 0 | fosc /4 (2)
-- 0 | 0 | 1 | fosc /16 (8)
-- 0 | 1 | 0 | fosc /64 (32)
-- 0 | 1 | 1 | fosc /128 (64)
-- ------+------+------+-------------
-- 1 | 0 | 0 | fosc /2 (1)
-- 1 | 0 | 1 | fosc /8 (4)
-- 1 | 1 | 0 | fosc /32 (16)
-- 1 | 1 | 1 | fosc /64 (32)
DividerToggleComb:process(MstSMSt_Current,Div_Current,SPCR,SPSR)
begin
Div_Toggle <= '0';
if(MstSMSt_Current /= MstSt_Idle) then
if(SPI2X='1') then -- Extended mode
case SPR is
when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /2
when "01" => if (Div_Current="000011") then Div_Toggle <= '1'; end if; -- fosc /8
when "10" => if (Div_Current="001111") then Div_Toggle <= '1'; end if; -- fosc /32
when "11" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64
when others => Div_Toggle <= '0';
end case;
else -- Normal mode
case SPR is
when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /4
when "01" => if (Div_Current="000111") then Div_Toggle <= '1'; end if; -- fosc /16
when "10" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64
when "11" => if (Div_Current="111111") then Div_Toggle <= '1'; end if; -- fosc /128
when others => Div_Toggle <= '0';
end case;
end if;
end if;
end process;
DividerNextComb:process(MstSMSt_Current,Div_Current,DivCntMsb_Current,Div_Toggle)
begin
Div_Next <= Div_Current;
DivCntMsb_Next <= DivCntMsb_Current;
if(MstSMSt_Current /= MstSt_Idle) then
if(Div_Toggle='1') then
Div_Next <= (others => '0');
DivCntMsb_Next <= not DivCntMsb_Current;
else
Div_Next <= Div_Current + 1;
end if;
end if;
end process;
TrStart <= '1' when (fn_to_integer(adr)=SPDR_Address and iowe='1' and SPEB='1') else '0';
-- Transmitter Master Mode Shift Control SM
MstSmNextComb:process(MstSMSt_Current,DivCntMsb_Current,Div_Toggle,TrStart,SPCR)
begin
MstSMSt_Next <= MstSMSt_Current;
case MstSMSt_Current is
when MstSt_Idle =>
if(TrStart='1' and MSTR='1') then
MstSMSt_Next <= MstSt_B0;
end if;
when MstSt_B0 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B1;
end if;
when MstSt_B1 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B2;
end if;
when MstSt_B2 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B3;
end if;
when MstSt_B3 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B4;
end if;
when MstSt_B4 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B5;
end if;
when MstSt_B5 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B6;
end if;
when MstSt_B6 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B7;
end if;
when MstSt_B7 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_Idle;
end if;
when others => MstSMSt_Next <= MstSt_Idle;
end case;
end process;
SPIFClrCombProc:process(SPIFClrSt_Current,SPCR,SPSR,adr,iore,iowe)
begin
SPIFClrSt_Next <= SPIFClrSt_Current;
case SPIFClrSt_Current is
when '0' =>
if(fn_to_integer(adr)=SPSR_Address and iore='1' and SPIF='1' and SPEB='1') then
SPIFClrSt_Next <= '1';
end if;
when '1' =>
if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then
SPIFClrSt_Next <= '0';
end if;
when others => SPIFClrSt_Next <= SPIFClrSt_Current;
end case;
end process; --SPIFClrCombProc
WCOLClrCombProc:process(WCOLClrSt_Current,SPSR,adr,iore,iowe)
begin
WCOLClrSt_Next <= WCOLClrSt_Current;
case WCOLClrSt_Current is
when '0' =>
if(fn_to_integer(adr)=SPSR_Address and iore='1' and WCOL='1') then
WCOLClrSt_Next <= '1';
end if;
when '1' =>
if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then
WCOLClrSt_Next <= '0';
end if;
when others => WCOLClrSt_Next <= WCOLClrSt_Current;
end case;
end process; --WCOLClrCombProc
MstDataSamplingComb:process(SPCR,scko_Current,scko_Next,MstDSamp_Current,MstSMSt_Current)
begin
MstDSamp_Next <= '0';
case MstDSamp_Current is
when '0' =>
if(MstSMSt_Current/=MstSt_Idle) then
if(CPHA=CPOL) then
if(scko_Next='1' and scko_Current='0') then -- Rising edge
MstDSamp_Next <= '1';
end if;
else -- CPHA/=CPOL
if(scko_Next='0' and scko_Current='1') then -- Falling edge
MstDSamp_Next <= '1';
end if;
end if;
end if;
when '1' => MstDSamp_Next <= '0';
when others => MstDSamp_Next <= '0';
end case;
end process; -- MstDataSamplingComb
--
DRLatchComb:process(UpdRcDataRg_Current,MstSMSt_Current,MstSMSt_Next,SlvSMSt_Current,SlvSMSt_Next,SPCR)
begin
UpdRcDataRg_Next <= '0';
case UpdRcDataRg_Current is
when '0' =>
if((MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle)or
(MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle)) then
UpdRcDataRg_Next <= '1';
end if;
when '1' => UpdRcDataRg_Next <= '0';
when others => UpdRcDataRg_Next <= '0';
end case;
end process;
TmpInComb:process(TmpIn_Current,mosii,misoi,MstDSamp_Current,SlvSampleSt,SPCR,ss_b_resync)
begin
TmpIn_Next <= TmpIn_Current;
if(MSTR='1' and MstDSamp_Current='1') then -- Master mode
TmpIn_Next <= misoi;
elsif(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') then -- Slave mode ???
TmpIn_Next <= mosii;
end if;
end process;
ShiftRgComb:process(MstSMSt_Current,SlvSMSt_Current,SPDR_Sh_Current,SPCR,DivCntMsb_Current,Div_Toggle,TrStart,dbus_in,ss_b_resync,TmpIn_Current,SlvSMChangeSt,SlvSampleSt,UpdRcDataRg_Current)
begin
SPDR_Sh_Next <= SPDR_Sh_Current;
if(TrStart='1' and (MstSMSt_Current=MstSt_Idle and SlvSMSt_Current = SlvSt_Idle and not(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') )) then -- Load
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Sh_Next <= Fn_RevBitVector(dbus_in);
else -- the MSB of the data word is transmitted first
SPDR_Sh_Next <= dbus_in;
end if;
elsif(MSTR='1' and UpdRcDataRg_Current='1') then -- ???
SPDR_Sh_Next(SPDR_Sh_Next'high) <= '1';
elsif((MSTR='1' and MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current='1' and Div_Toggle='1') or
(MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMChangeSt='1' and ss_b_resync='0')) then
-- Shift
SPDR_Sh_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto SPDR_Sh_Current'low)&TmpIn_Current;
end if;
end process; --ShiftRgComb
sckoGenComb:process(scko_Current,SPCR,adr,iowe,dbus_in,DivCntMsb_Next,DivCntMsb_Current,TrStart,MstSMSt_Current,MstSMSt_Next)
begin
scko_Next <= scko_Current;
if(fn_to_integer(adr)=SPCR_Address and iowe='1') then -- Write to SPCR
scko_Next <= dbus_in(3); -- CPOL
elsif(TrStart='1' and CPHA='1' and MstSMSt_Current=MstSt_Idle) then
scko_Next <= not CPOL;
elsif(MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle) then -- "Parking"
scko_Next <= CPOL;
elsif(MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current/=DivCntMsb_Next) then
scko_Next <= not scko_Current;
end if;
end process;
-- Receiver data register
SPDRRcComb:process(SPDR_Rc,SPCR,SPDR_Sh_Current,UpdRcDataRg_Current,TmpIn_Current)
begin
SPDR_Rc_Next <= SPDR_Rc;
if(UpdRcDataRg_Current='1') then
if(MSTR='0' and CPHA='1') then
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current);
else -- the MSB of the data word is transmitted first
SPDR_Rc_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current;
end if;
else
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current);
else -- the MSB of the data word is transmitted first
SPDR_Rc_Next <= SPDR_Sh_Current;
end if;
end if;
end if;
end process;
--****************************************************************************************
-- Slave
--****************************************************************************************
SlvSampleSt <= '1' when ((sck_EdgeDetDFF='0' and scki_resync='1' and CPOL=CPHA)or -- Rising edge
(sck_EdgeDetDFF='1' and scki_resync='0' and CPOL/=CPHA))else '0'; -- Falling edge
SlvSMChangeSt <= '1' when ((sck_EdgeDetDFF='1' and scki_resync='0' and CPOL=CPHA)or -- Falling edge
(sck_EdgeDetDFF='0' and scki_resync='1' and CPOL/=CPHA))else '0'; -- Rising edge
-- Slave Master Mode Shift Control SM
SlvSMNextComb:process(SlvSMSt_Current,SPCR,SlvSampleSt,SlvSMChangeSt,ss_b_resync)
begin
SlvSMSt_Next <= SlvSMSt_Current;
if(ss_b_resync='0') then
case SlvSMSt_Current is
when SlvSt_Idle =>
if(MSTR='0') then
if(CPHA='1') then
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B0;
end if;
else -- CPHA='0'
if(SlvSampleSt='1') then
SlvSMSt_Next <= SlvSt_B0I;
end if;
end if;
end if;
when SlvSt_B0I =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B0;
end if;
when SlvSt_B0 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B1;
end if;
when SlvSt_B1 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B2;
end if;
when SlvSt_B2 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B3;
end if;
when SlvSt_B3 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B4;
end if;
when SlvSt_B4 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B5;
end if;
when SlvSt_B5 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B6;
end if;
when SlvSt_B6 =>
if(SlvSMChangeSt='1') then
if(CPHA='0') then
SlvSMSt_Next <= SlvSt_Idle;
else -- CPHA='1'
SlvSMSt_Next <= SlvSt_B6W;
end if;
end if;
when SlvSt_B6W =>
if(SlvSampleSt='1')then
SlvSMSt_Next <= SlvSt_Idle;
end if;
when others => SlvSMSt_Next <= SlvSt_Idle;
end case;
end if;
end process;
MSTRGenComb:process(adr,iowe,dbus_in,ss_b_resync,SPCR)
begin
MSTR_Next <= MSTR;
case MSTR is
when '0' =>
if(fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='1') then -- TBD (ss_b_resync='0')
MSTR_Next <= '1';
end if;
when '1' =>
if((fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='0') or
(ss_b_resync='0')) then
MSTR_Next <= '0';
end if;
when others => MSTR_Next <= MSTR;
end case;
end process;
WCOLGenComb:process(WCOLClrSt_Current,SlvSMSt_Current,MstSMSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSampleSt,ss_b_resync)
begin
WCOL_Next <= WCOL;
case WCOL is
when '0' =>
if(fn_to_integer(adr)=SPDR_Address and iowe='1' and
((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle))) then
WCOL_Next <= '1';
end if;
when '1' =>
if(((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1')) and WCOLClrSt_Current='1') and
not (fn_to_integer(adr)=SPDR_Address and iowe='1' and
((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle)))) then
WCOL_Next <= '0';
end if;
when others => WCOL_Next <= WCOL;
end case;
end process;
SPIFGenComb:process(SPIFClrSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSMSt_Current,SlvSMSt_Next,MstSMSt_Current,MstSMSt_Next,spiack)
begin
SPIF_Next <= SPIF;
case SPIF is
when '0' =>
if((MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle))then
SPIF_Next <= '1';
end if;
when '1' =>
if((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1') and SPIFClrSt_Current='1') or spiack='1') then
SPIF_Next <= '0';
end if;
when others => SPIF_Next <= SPIF;
end case;
end process;
--*************************************************************************************
spimaster <= MSTR;
spe <= SPEB;
-- IRQ
spiirq <= SPIE and SPIF;
OutMuxComb:process(adr,iore,SPDR_Rc,SPSR,SPCR)
begin
case(fn_to_integer(adr)) is
when SPDR_Address => dbus_out <= SPDR_Rc; out_en <= iore;
when SPSR_Address => dbus_out <= SPSR; out_en <= iore;
when SPCR_Address => dbus_out <= SPCR; out_en <= iore;
when others => dbus_out <= (others => '0'); out_en <= '0';
end case;
end process; -- OutMuxComb
--
spidwrite <= '0';
spiload <= '0';
end RTL;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/AVR8/CommonPacks/std_library.vhd
|
3
|
10290
|
-- *****************************************************************************************
-- Standard libraries
-- Version 0.2
-- Modified 02.12.2006
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package std_library is
type log2array_type is array(0 to 1024) of integer;
constant fn_log2 : log2array_type := (
0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
constant fn_log2x : log2array_type := (
0,1,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,
others => 10);
-- *********************************************************************************
function fn_det_x(d : std_logic_vector) return boolean;
function fn_det_x(d : std_logic) return boolean;
function fn_xor_vect(vect : std_logic_vector) return std_logic;
function fn_or_vect(vect : std_logic_vector) return std_logic;
function fn_and_vect(vect : std_logic_vector) return std_logic;
function fn_to_integer(vect : std_logic_vector) return integer;
function fn_to_integer(d : std_logic) return integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector;
function fn_to_std_logic(b : boolean) return std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic;
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector;
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector;
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector;
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector;
end std_library;
package body std_library is
function fn_det_x(d : std_logic_vector) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_det_x(d : std_logic) return boolean is
variable result : boolean;
begin
result := FALSE;
-- pragma translate_off
result := is_x(d);
-- pragma translate_on
return (result);
end fn_det_x;
function fn_xor_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp xor vect(i);
end loop;
return(temp);
end fn_xor_vect;
function fn_or_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '0';
for i in vect'range loop
temp := temp or vect(i);
end loop;
return(temp);
end fn_or_vect;
function fn_and_vect(vect : std_logic_vector) return std_logic is
variable temp : std_logic;
begin
temp := '1';
for i in vect'range loop
temp := temp and vect(i);
end loop;
return(temp);
end fn_and_vect;
function fn_to_integer(vect : std_logic_vector) return integer is
begin
if (not fn_det_x(vect)) then
return(to_integer(unsigned(vect)));
else
return(0);
end if;
end fn_to_integer;
function fn_to_integer(d : std_logic) return integer is
begin
if (not fn_det_x(d)) then
if (d = '1') then
return(1);
else
return(0);
end if;
else
return(0);
end if;
end fn_to_integer;
function fn_to_std_logic_vector(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_unsigned(int, width));
return(temp);
end fn_to_std_logic_vector;
function fn_to_std_logic_vector_signed(int : integer; width : integer) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
begin
temp := std_logic_vector(to_signed(int, width));
return(temp);
end fn_to_std_logic_vector_signed;
function fn_to_std_logic(b : boolean) return std_logic is
begin
if (b) then
return('1');
else
return('0');
end if;
end fn_to_std_logic;
function fn_dcd(vect : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector((2**vect'length)-1 downto 0);
variable i : integer range result'range;
begin
result := (others => '0');
i := 0;
if (not fn_det_x(vect)) then
i := to_integer(unsigned(vect));
end if;
result(i) := '1';
return(result);
end fn_dcd;
function fn_mux(sel : std_logic_vector; vect : std_logic_vector) return std_logic is
variable result : std_logic_vector(vect'length-1 downto 0);
variable i : integer range result'range;
begin
result := vect;
i := 0;
if (not fn_det_x(sel)) then
i := to_integer(unsigned(sel));
end if;
return(result(i));
end fn_mux;
-- >>>>
function "+" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X');
tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) + unsigned(vect_b)));
end "+";
function "+" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + int));
end "+";
function "+" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_b := (others =>'X');
return(tmp_b);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) + unsigned(tmp_b)));
end "+";
function "-" (vect_a : std_logic_vector; vect_b : std_logic_vector) return std_logic_vector is
variable tmp_a : std_logic_vector(vect_a'length-1 downto 0);
variable tmp_b : std_logic_vector(vect_b'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect_a) or fn_det_x(vect_b)) then
tmp_a := (others =>'X'); tmp_b := (others =>'X');
if (tmp_a'length > tmp_b'length) then
return(tmp_a);
else
return(tmp_b);
end if;
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect_a) - unsigned(vect_b)));
end "-";
function "-" (vect : std_logic_vector; int : integer) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - int));
end "-";
function "-" (int : integer; vect : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(vect'length-1 downto 0);
begin
-- pragma translate_off
if (fn_det_x(vect)) then
temp := (others =>'X');
return(temp);
end if;
-- pragma translate_on
return(std_logic_vector(int - unsigned(vect)));
end "-";
function "-" (vect : std_logic_vector; d : std_logic) return std_logic_vector is
variable tmp_a : std_logic_vector(vect'length-1 downto 0);
variable tmp_b : std_logic_vector(0 downto 0);
begin
tmp_b(0) := d;
-- pragma translate_off
if (fn_det_x(vect) or fn_det_x(d)) then
tmp_a := (others =>'X');
return(tmp_a);
end if;
-- pragma translate_on
return(std_logic_vector(unsigned(vect) - unsigned(tmp_b)));
end "-";
end std_library;
|
gpl-3.0
|
hoglet67/ElectronFpga
|
AtomBusMon/src/T6502/T65_Pack.vhd
|
3
|
5460
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_Pack.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
subtype T_Lcycle is std_logic_vector(2 downto 0);
constant Cycle_sync :T_Lcycle:="000";
constant Cycle_1 :T_Lcycle:="001";
constant Cycle_2 :T_Lcycle:="010";
constant Cycle_3 :T_Lcycle:="011";
constant Cycle_4 :T_Lcycle:="100";
constant Cycle_5 :T_Lcycle:="101";
constant Cycle_6 :T_Lcycle:="110";
constant Cycle_7 :T_Lcycle:="111";
function CycleNext(c:T_Lcycle) return T_Lcycle;
type T_Set_BusA_To is
(
Set_BusA_To_DI,
Set_BusA_To_ABC,
Set_BusA_To_X,
Set_BusA_To_Y,
Set_BusA_To_S,
Set_BusA_To_P,
Set_BusA_To_DA,
Set_BusA_To_DAO,
Set_BusA_To_DAX,
Set_BusA_To_AAX,
Set_BusA_To_DONTCARE
);
type T_Set_Addr_To is
(
Set_Addr_To_PBR,
Set_Addr_To_SP,
Set_Addr_To_ZPG,
Set_Addr_To_BA
);
type T_Write_Data is
(
Write_Data_DL,
Write_Data_ABC,
Write_Data_X,
Write_Data_Y,
Write_Data_S,
Write_Data_P,
Write_Data_PCL,
Write_Data_PCH,
Write_Data_AX,
Write_Data_AXB,
Write_Data_XB,
Write_Data_YB,
Write_Data_DONTCARE
);
type T_ALU_OP is
(
ALU_OP_OR, --"0000"
ALU_OP_AND, --"0001"
ALU_OP_EOR, --"0010"
ALU_OP_ADC, --"0011"
ALU_OP_EQ1, --"0100" EQ1 does not change N,Z flags, EQ2/3 does.
ALU_OP_EQ2, --"0101" Not sure yet whats the difference between EQ2&3. They seem to do the same ALU op
ALU_OP_CMP, --"0110"
ALU_OP_SBC, --"0111"
ALU_OP_ASL, --"1000"
ALU_OP_ROL, --"1001"
ALU_OP_LSR, --"1010"
ALU_OP_ROR, --"1011"
ALU_OP_BIT, --"1100"
-- ALU_OP_EQ3, --"1101"
ALU_OP_DEC, --"1110"
ALU_OP_INC, --"1111"
ALU_OP_ARR,
ALU_OP_ANC,
ALU_OP_SAX,
ALU_OP_XAA
-- ALU_OP_UNDEF--"----"--may be replaced with any?
);
type T_t65_dbg is record
I : std_logic_vector(7 downto 0); -- instruction
A : std_logic_vector(7 downto 0); -- A reg
X : std_logic_vector(7 downto 0); -- X reg
Y : std_logic_vector(7 downto 0); -- Y reg
S : std_logic_vector(7 downto 0); -- stack pointer
P : std_logic_vector(7 downto 0); -- processor flags
end record;
end;
package body T65_Pack is
function CycleNext(c:T_Lcycle) return T_Lcycle is
begin
case(c) is
when Cycle_sync=>
return Cycle_1;
when Cycle_1=>
return Cycle_2;
when Cycle_2=>
return Cycle_3;
when Cycle_3=>
return Cycle_4;
when Cycle_4=>
return Cycle_5;
when Cycle_5=>
return Cycle_6;
when Cycle_6=>
return Cycle_7;
when Cycle_7=>
return Cycle_sync;
when others=>
return Cycle_sync;
end case;
end CycleNext;
end T65_Pack;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/eth_marvell_88e1111/hdl/RGMII_MAC/fifo_tx_udp.vhd
|
1
|
6850
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: fifo_tx_udp.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo_tx_udp IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END fifo_tx_udp;
ARCHITECTURE SYN OF fifo_tx_udp IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(7 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone III",
lpm_numwords => 2048,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 8,
lpm_widthu => 11,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
aclr => aclr,
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
-- Retrieval info: PRIVATE: Width NUMERIC "8"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "8"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_tx_udp_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/eth_marvell_88e1111/hdl/RGMII_MAC/eth_ddr_out.vhd
|
1
|
4090
|
-- megafunction wizard: %ALTDDIO_OUT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTDDIO_OUT
-- ============================================================
-- File Name: eth_ddr_out.vhd
-- Megafunction Name(s):
-- ALTDDIO_OUT
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.0 Build 178 05/31/2012 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY eth_ddr_out IS
PORT
(
datain_h : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
outclock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END eth_ddr_out;
ARCHITECTURE SYN OF eth_ddr_out IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
BEGIN
dataout <= sub_wire0(4 DOWNTO 0);
ALTDDIO_OUT_component : ALTDDIO_OUT
GENERIC MAP (
extend_oe_disable => "OFF",
intended_device_family => "Cyclone IV E",
invert_output => "OFF",
lpm_hint => "UNUSED",
lpm_type => "altddio_out",
oe_reg => "UNREGISTERED",
power_up_high => "OFF",
width => 5
)
PORT MAP (
datain_h => datain_h,
datain_l => datain_l,
outclock => outclock,
dataout => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
-- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: datain_h 0 0 5 0 INPUT NODEFVAL "datain_h[4..0]"
-- Retrieval info: CONNECT: @datain_h 0 0 5 0 datain_h 0 0 5 0
-- Retrieval info: USED_PORT: datain_l 0 0 5 0 INPUT NODEFVAL "datain_l[4..0]"
-- Retrieval info: CONNECT: @datain_l 0 0 5 0 datain_l 0 0 5 0
-- Retrieval info: USED_PORT: dataout 0 0 5 0 OUTPUT NODEFVAL "dataout[4..0]"
-- Retrieval info: CONNECT: dataout 0 0 5 0 @dataout 0 0 5 0
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.cmp FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL eth_ddr_out.ppf TRUE FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
DreamIP/GPStudio
|
support/process/dynroi/hdl/dynroi_process.vhd
|
1
|
12657
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroi_process is
generic (
CLK_PROC_FREQ : integer;
BINIMG_SIZE : integer;
IMG_SIZE : integer;
ROI_SIZE : integer;
COORD_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
status_reg_bypass_bit : in std_logic;
status_reg_static_res_bit : in std_logic;
inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
BinImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0);
BinImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_w_reg : in std_logic_vector(11 downto 0);
out_size_reg_out_h_reg : in std_logic_vector(11 downto 0);
----------------------- BinImg flow ---------------------
BinImg_data : in std_logic_vector(BINIMG_SIZE-1 downto 0);
BinImg_fv : in std_logic;
BinImg_dv : in std_logic;
------------------------ Img flow -----------------------
Img_data : in std_logic_vector(IMG_SIZE-1 downto 0);
Img_fv : in std_logic;
Img_dv : in std_logic;
------------------------ roi flow -----------------------
roi_data : out std_logic_vector(ROI_SIZE-1 downto 0);
roi_fv : out std_logic;
roi_dv : out std_logic;
----------------------- coord flow ----------------------
coord_data : out std_logic_vector(COORD_SIZE-1 downto 0);
coord_fv : out std_logic;
coord_dv : out std_logic
);
end dynroi_process;
architecture rtl of dynroi_process is
constant X_COUNTER_SIZE : integer := 12;
constant Y_COUNTER_SIZE : integer := 12;
--process data_process vars
--bin image reference coordinates
signal xBin_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
signal yBin_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal x_min : unsigned(X_COUNTER_SIZE-1 downto 0);
signal x_max : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_min : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal y_max : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal enabled : std_logic;
--conversion offset from binImg to img
signal conv_offset_x : unsigned(X_COUNTER_SIZE-1 downto 0);
signal conv_offset_y : unsigned(Y_COUNTER_SIZE-1 downto 0);
--Coord over serial line related vars
signal frame_buffer : std_logic_vector(63 downto 0);
signal frame_buffer_has_been_filled : std_logic;
signal frame_buffer_has_been_sent : std_logic;
signal frame_buffer_position : unsigned(6 downto 0);
--Apply_roi signals
signal x_temp : unsigned(X_COUNTER_SIZE-1 downto 0);
signal y_temp : unsigned(Y_COUNTER_SIZE-1 downto 0);
signal w_temp : unsigned(X_COUNTER_SIZE-1 downto 0);
signal h_temp : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
------------------------------------------------------------------------
apply_roi : process(clk_proc, reset_n)
--img reference coordinates
variable x : unsigned(X_COUNTER_SIZE-1 downto 0);
variable y : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable w : unsigned(X_COUNTER_SIZE-1 downto 0);
variable h : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable xImg_pos : unsigned(X_COUNTER_SIZE-1 downto 0);
variable yImg_pos : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
if(reset_n='0') then
-- reset pixel counters
xImg_pos := to_unsigned(0, X_COUNTER_SIZE);
yImg_pos := to_unsigned(0, Y_COUNTER_SIZE);
-- reset ROI coord : default is central frame with param.w/h values
x := (others => '0');
y := (others => '0');
w := (others => '0');
h := (others => '0');
x_temp <= (others => '0');
y_temp <= (others => '0');
w_temp <= (others => '0');
h_temp <= (others => '0');
roi_data <= (others => '0');
roi_dv <= '0';
roi_fv <= '0';
elsif(rising_edge(clk_proc)) then
if Img_fv = '1' and enabled = '1' then
roi_fv <= '1';
else
roi_fv <= '0';
end if;
roi_dv <= '0';
roi_data <= (others => '1');
--Updating last frame coordinates
if frame_buffer_has_been_filled = '1' and enabled = '1' then
x_temp <= unsigned(frame_buffer(X_COUNTER_SIZE-1 downto 0));
y_temp <= unsigned(frame_buffer(Y_COUNTER_SIZE+15 downto 16));
w_temp <= unsigned(frame_buffer(X_COUNTER_SIZE+31 downto 32));
h_temp <= unsigned(frame_buffer(Y_COUNTER_SIZE+47 downto 48));
end if;
-- ROI action
if Img_fv = '0' then
--Update ROI coords
x := x_temp;
y := y_temp;
w := w_temp;
h := h_temp;
--Reset pixel counters
xImg_pos := to_unsigned(0, X_COUNTER_SIZE);
yImg_pos := to_unsigned(0, Y_COUNTER_SIZE);
else
if Img_dv = '1' and enabled = '1' then
--ROI
if(yBin_pos >= y
and yBin_pos < y + h
and xBin_pos >= x
and xBin_pos < x + w )then
roi_dv <= '1';
roi_data <= Img_data;
end if;
--Pixel counter in img
xImg_pos := xImg_pos + 1;
if(xImg_pos=unsigned(inImg_size_reg_in_w_reg)) then
yImg_pos := yImg_pos + 1;
xImg_pos := to_unsigned(0, X_COUNTER_SIZE);
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------
------------------------------------------------------------------------
data_process : process (clk_proc, reset_n)
-- Vars used to fill frame_buffer
variable x_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable y_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
variable w_to_send : unsigned(X_COUNTER_SIZE-1 downto 0);
variable h_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0);
begin
if(reset_n='0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= (others => '0');
y_min <= (others => '0');
--Cleaning frame buffer
frame_buffer <= (others=>'0');
--Cleaning signals used to fill buffer
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '0';
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
--Cleaning flags
enabled <= '0';
--Cleaning conv offset
conv_offset_x <= (others => '0');
conv_offset_y <= (others => '0');
elsif(rising_edge(clk_proc)) then
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
--offset calculation
conv_offset_x <= (unsigned(inImg_size_reg_in_w_reg)-unsigned(BinImg_size_reg_in_w_reg))/2;
conv_offset_y <= (unsigned(inImg_size_reg_in_h_reg)-unsigned(BinImg_size_reg_in_h_reg))/2;
if(BinImg_fv = '0') then
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE);
--
if frame_buffer_has_been_filled = '0' then
--We send frame coordinates only if there is something to send
if enabled = '1' and frame_buffer_has_been_sent = '0' then
if status_reg_bypass_bit = '1' then
x_to_send := (others=>'0');
y_to_send := (others=>'0');
w_to_send := unsigned(inImg_size_reg_in_w_reg);
h_to_send := unsigned(inImg_size_reg_in_h_reg);
else
----roi resolution fixed by user
if status_reg_static_res_bit = '1' then
--something was detected
if x_max > 0 then
--checking top left corner position to ensure frame width is matching static_res
if x_min + conv_offset_x > (unsigned(inImg_size_reg_in_w_reg)-unsigned(out_size_reg_out_w_reg)) then
x_to_send := unsigned(inImg_size_reg_in_w_reg) - unsigned(out_size_reg_out_w_reg);
else
x_to_send := x_min + conv_offset_x;
end if;
if y_min + conv_offset_y > (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg)) then
y_to_send := (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg));
else
y_to_send := y_min + conv_offset_y;
end if;
w_to_send := unsigned(out_size_reg_out_w_reg) ;
h_to_send := unsigned(out_size_reg_out_h_reg);
else
--nothing found
x_to_send := (unsigned(inImg_size_reg_in_w_reg)-unsigned(out_size_reg_out_w_reg))/2 ;
y_to_send := (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg))/2;
w_to_send := unsigned(out_size_reg_out_w_reg);
h_to_send := unsigned(out_size_reg_out_h_reg);
end if;
----dynamic resolution for roi
else
--something was detected
if x_max > 0 then
x_to_send := x_min + conv_offset_x;
y_to_send := y_min + conv_offset_y;
w_to_send := x_max-x_min;
h_to_send := y_max-y_min;
else
--nothing found -> empty rectangle at image center
x_to_send := unsigned(inImg_size_reg_in_w_reg)/2;
y_to_send := unsigned(inImg_size_reg_in_h_reg)/2;
w_to_send := (others=>'0');
h_to_send := (others=>'0');
end if;
end if;
end if;
--filling buffer with matching coordinates
frame_buffer(X_COUNTER_SIZE-1 downto 0) <= std_logic_vector(x_to_send);
frame_buffer(Y_COUNTER_SIZE+15 downto 16) <= std_logic_vector(y_to_send);
frame_buffer(X_COUNTER_SIZE+31 downto 32) <= std_logic_vector(w_to_send);
frame_buffer(Y_COUNTER_SIZE+47 downto 48) <= std_logic_vector(h_to_send);
--zero padding, each value has 16 bits but only uses XY_COUNTER_SIZE bits
frame_buffer(15 downto X_COUNTER_SIZE) <= (others=>'0');
frame_buffer(31 downto X_COUNTER_SIZE+16) <= (others=>'0');
frame_buffer(47 downto X_COUNTER_SIZE+32) <= (others=>'0');
frame_buffer(63 downto X_COUNTER_SIZE+48) <= (others=>'0');
-- Get buffer ready to send
frame_buffer_has_been_filled <= '1';
frame_buffer_position <= (others=>'0') ;
end if;
--Cleaning frame coordinates
x_max <= (others=>'0');
y_max <= (others=>'0');
x_min <= unsigned(BinImg_size_reg_in_w_reg);
y_min <= unsigned(BinImg_size_reg_in_h_reg);
--To prevent sending coord after reset of x/y_min/max
frame_buffer_has_been_sent <= '1';
else
--send roi coord
coord_fv <= '1';
coord_dv <= '1';
coord_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position));
if frame_buffer_position >= 56 then
frame_buffer_has_been_filled <= '0';
frame_buffer_has_been_sent <= '1';
else
frame_buffer_position <= frame_buffer_position + to_unsigned(8, 7);
end if;
end if;
enabled <= status_reg_enable_bit;
else
coord_fv <= '0';
coord_dv <= '0';
coord_data <= (others=>'0');
frame_buffer_has_been_sent <= '0';
if status_reg_enable_bit = '1' and enabled = '1' then
if(BinImg_dv = '1' ) then
--bin img pixel counter
xBin_pos <= xBin_pos + 1;
if(xBin_pos=unsigned(BinImg_size_reg_in_w_reg)-1) then
yBin_pos <= yBin_pos + 1;
xBin_pos <= to_unsigned(0, X_COUNTER_SIZE);
end if;
-- This will give the smallest area including all non-black points
if BinImg_data /= (BinImg_data'range => '0') then
if xBin_pos < x_min then
x_min <= xBin_pos;
end if;
if xBin_pos > x_max then
x_max <= xBin_pos;
end if;
--
if yBin_pos < y_min then
y_min <= yBin_pos;
end if;
if yBin_pos > y_max then
y_max <= yBin_pos;
end if;
end if;
end if;
else
enabled <= '0';
end if;
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/component/gp_com/flow_to_com/fv_signal_synchroniser.vhd
|
1
|
1771
|
-- **************************************************************************
-- SYNCHRO enable avec fin de ligne
-- **************************************************************************
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
-- TODO: Supprmier machine d'états => possibilité de mettre à jour le reg seulement sur le front descendant de fv
-- : A verifier !
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fv_signal_synchroniser is
port (
clk : in std_logic;
rst_n : in std_logic;
fv_i : in std_logic;
signal_i : in std_logic;
signal_o : out std_logic
);
end fv_signal_synchroniser;
architecture rtl of fv_signal_synchroniser is
type en_state_t is (WaitforSignal, WaitNextFrame, Run, WaitForEndFrame);
signal en_state : en_state_t := WaitforSignal;
signal enable_s : std_logic :='0';
signal fv_r : std_logic := '0';
begin
-- This process synchronize signal with flow valid
ENABLE_inst: process (clk, rst_n)
begin
if (rst_n = '0') then
en_state <= WaitforSignal;
signal_o <='0';
elsif rising_edge(clk) then
fv_r <= fv_i;
case en_state is
when WaitforSignal =>
if (signal_i = '1') then
-- wait for the next frame
en_state <= WaitNextFrame;
end if;
when WaitNextFrame =>
if (fv_i='0') then
signal_o <= '1';
en_state <= Run;
end if;
when Run =>
if (signal_i ='0') then
en_state <= WaitForEndFrame;
end if;
when WaitForEndFrame =>
if (fv_r ='1' and fv_i='0') then
signal_o <= '0';
en_state <= WaitforSignal;
end if;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/eth_marvell_88e1111/hdl/RGMII_MAC/eth_crc32.vhd
|
1
|
5890
|
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : eth_crc32.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-11-04
-- Last update: 2012-11-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-04 1.0 root Created
-- 经过测试没有问题！计算后输出到外面的crc值需要按照以太网的大小端模式发送才是正确的！
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY eth_crc32 IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iInit : IN STD_LOGIC;
iCalcEn : IN STD_LOGIC;
iData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oCRC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
oCRCErr : OUT STD_LOGIC);
END ENTITY eth_crc32;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF eth_crc32 IS
SIGNAL crc, nxtCrc : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
nxtCrc(0) <= crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(1) <= crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(2) <= crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(3) <= crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(4) <= crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(5) <= crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(6) <= crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(7) <= crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(8) <= crc(0) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(9) <= crc(1) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6);
nxtCrc(10) <= crc(2) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(24) XOR iData(7);
nxtCrc(11) <= crc(3) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(25) XOR iData(6) XOR crc(24) XOR iData(7);
nxtCrc(12) <= crc(4) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(26) XOR iData(5) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(13) <= crc(5) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(14) <= crc(6) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(15) <= crc(7) XOR crc(31) XOR iData(0) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4);
nxtCrc(16) <= crc(8) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(24) XOR iData(7);
nxtCrc(17) <= crc(9) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(25) XOR iData(6);
nxtCrc(18) <= crc(10) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(26) XOR iData(5);
nxtCrc(19) <= crc(11) XOR crc(31) XOR iData(0) XOR crc(27) XOR iData(4);
nxtCrc(20) <= crc(12) XOR crc(28) XOR iData(3);
nxtCrc(21) <= crc(13) XOR crc(29) XOR iData(2);
nxtCrc(22) <= crc(14) XOR crc(24) XOR iData(7);
nxtCrc(23) <= crc(15) XOR crc(25) XOR iData(6) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(24) <= crc(16) XOR crc(26) XOR iData(5) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(25) <= crc(17) XOR crc(27) XOR iData(4) XOR crc(26) XOR iData(5);
nxtCrc(26) <= crc(18) XOR crc(28) XOR iData(3) XOR crc(27) XOR iData(4) XOR crc(24) XOR crc(30) XOR iData(1) XOR iData(7);
nxtCrc(27) <= crc(19) XOR crc(29) XOR iData(2) XOR crc(28) XOR iData(3) XOR crc(25) XOR crc(31) XOR iData(0) XOR iData(6);
nxtCrc(28) <= crc(20) XOR crc(30) XOR iData(1) XOR crc(29) XOR iData(2) XOR crc(26) XOR iData(5);
nxtCrc(29) <= crc(21) XOR crc(31) XOR iData(0) XOR crc(30) XOR iData(1) XOR crc(27) XOR iData(4);
nxtCrc(30) <= crc(22) XOR crc(31) XOR iData(0) XOR crc(28) XOR iData(3);
nxtCrc(31) <= crc(23) XOR crc(29) XOR iData(2);
PROCESS (iClk,iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
crc <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
IF iInit = '1' THEN
crc <= (OTHERS => '1');
ELSIF iCalcEn = '1' THEN
crc <= nxtCrc;
END IF;
END IF;
END PROCESS;
oCRC(31 DOWNTO 24) <= NOT (crc(24)&crc(25)&crc(26)&crc(27)&crc(28)&crc(29)&crc(30)&crc(31));
oCRC(23 DOWNTO 16) <= NOT (crc(16)&crc(17)&crc(18)&crc(19)&crc(20)&crc(21)&crc(22)&crc(23));
oCRC(15 DOWNTO 8) <= NOT (crc(8)&crc(9)&crc(10)&crc(11)&crc(12)&crc(13)&crc(14)&crc(15));
oCRC(7 DOWNTO 0) <= NOT (crc(0)&crc(1)&crc(2)&crc(3)&crc(4)&crc(5)&crc(6)&crc(7));
oCRCErr <= '1' WHEN crc /= X"c704dd7b" ELSE '0'; -- CRC not equal to magic number
END ARCHITECTURE rtl;
|
gpl-3.0
|
DreamIP/GPStudio
|
support/io/mpu/hdl/mpu.vhd
|
1
|
5748
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
use work.mpu_pkg.all;
entity mpu is
generic (
CLK_PROC_FREQ : integer;
ACCELERO_SIZE : integer;
GYROSCOPE_SIZE : integer;
COMPASS_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
--------------------- external ports --------------------
ad0 : out std_logic;
sda : inout std_logic;
scl : inout std_logic;
---------------------- accelero flow --------------------
accelero_data : out std_logic_vector(ACCELERO_SIZE-1 downto 0);
accelero_fv : out std_logic;
accelero_dv : out std_logic;
--------------------- gyroscope flow --------------------
gyroscope_data : out std_logic_vector(GYROSCOPE_SIZE-1 downto 0);
gyroscope_fv : out std_logic;
gyroscope_dv : out std_logic;
---------------------- compass flow ---------------------
compass_data : out std_logic_vector(COMPASS_SIZE-1 downto 0);
compass_fv : out std_logic;
compass_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end mpu;
architecture rtl of mpu is
component mpu_acqui
port (
clk_proc : in std_logic;
reset : in std_logic;
sda : inout std_logic;
scl : inout std_logic;
AD0 : out std_logic;
parameters : in param;
accelero : out flow;
gyroscope : out flow;
compass : out flow
);
end component;
component mpu_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector(31 downto 0);
gyro_config_reg : out std_logic_vector(31 downto 0);
accel_config_reg : out std_logic_vector(31 downto 0);
spl_rate_reg : out std_logic_vector(31 downto 0);
gain_compass_reg : out std_logic_vector(31 downto 0);
fz_compass_reg : out std_logic_vector(31 downto 0);
accel_off_x_reg : out std_logic_vector(31 downto 0);
accel_off_y_reg : out std_logic_vector(31 downto 0);
accel_off_z_reg : out std_logic_vector(31 downto 0);
gyro_off_x_reg : out std_logic_vector(31 downto 0);
gyro_off_y_reg : out std_logic_vector(31 downto 0);
gyro_off_z_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal enable_reg : std_logic_vector (31 downto 0);
signal gyro_config_reg : std_logic_vector (31 downto 0);
signal accel_config_reg : std_logic_vector (31 downto 0);
signal spl_rate_reg : std_logic_vector (31 downto 0);
signal gain_compass_reg : std_logic_vector (31 downto 0);
signal fz_compass_reg : std_logic_vector (31 downto 0);
signal accel_off_x_reg : std_logic_vector (31 downto 0);
signal accel_off_y_reg : std_logic_vector (31 downto 0);
signal accel_off_z_reg : std_logic_vector (31 downto 0);
signal gyro_off_x_reg : std_logic_vector (31 downto 0);
signal gyro_off_y_reg : std_logic_vector (31 downto 0);
signal gyro_off_z_reg : std_logic_vector (31 downto 0);
signal parameters : param;
signal accelero, gyroscope, compass : flow;
begin
mpu_acqui_inst : mpu_acqui
port map(
clk_proc => clk_proc,
reset => reset_n,
sda => sda,
scl => scl,
AD0 => AD0,
parameters => parameters,
accelero => accelero,
gyroscope => gyroscope,
compass => compass
);
parameters(0)(31 downto 13) <= enable_reg(0) & spl_rate_reg(7 downto 0) & gyro_config_reg(1 downto 0) & accel_config_reg(1 downto 0)
& gain_compass_reg(2 downto 0) & fz_compass_reg(2 downto 0);
parameters(1) <= gyro_off_x_reg(15 downto 0) & accel_off_x_reg(15 downto 0);
parameters(2) <= gyro_off_y_reg(15 downto 0) & accel_off_y_reg(15 downto 0);
parameters(3) <= gyro_off_z_reg(15 downto 0) & accel_off_z_reg(15 downto 0);
accelero_data <= accelero.data;
accelero_dv <= accelero.dv;
accelero_fv <= accelero.fv;
gyroscope_data <= gyroscope.data;
gyroscope_dv <= gyroscope.dv;
gyroscope_fv <= gyroscope.fv;
compass_data <= compass.data;
compass_dv <= compass.dv;
compass_fv <= compass.fv;
mpu_slave_inst : mpu_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
enable_reg => enable_reg,
gyro_config_reg => gyro_config_reg,
accel_config_reg => accel_config_reg,
spl_rate_reg => spl_rate_reg,
gain_compass_reg => gain_compass_reg,
fz_compass_reg => fz_compass_reg,
accel_off_x_reg => accel_off_x_reg,
accel_off_y_reg => accel_off_y_reg,
accel_off_z_reg => accel_off_z_reg,
gyro_off_x_reg => gyro_off_x_reg,
gyro_off_y_reg => gyro_off_y_reg,
gyro_off_z_reg => gyro_off_z_reg,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
gpl-3.0
|
nickg/nvc
|
test/regress/loop1.vhd
|
5
|
970
|
entity loop1 is
end entity;
architecture test of loop1 is
begin
process is
variable a, b, c : integer;
begin
a := 0;
loop
exit when a = 10;
a := a + 1;
end loop;
assert a = 10;
a := 0;
b := 0;
loop
a := a + 1;
next when (a mod 2) = 0;
b := b + 1;
exit when b = 10;
end loop;
assert b = 10;
assert a = 19;
a := 0;
b := 0;
loop
a := a + 1;
if (a mod 2) = 0 then
next;
end if;
b := b + 1;
exit when b = 10;
end loop;
assert b = 10;
assert a = 19;
a := 0;
outer: loop
for i in 1 to 10 loop
a := a + 1;
exit outer when a = 50;
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/parse/instance.vhd
|
1
|
1245
|
entity instance is end entity;
entity foo is
port ( a, b, c : in integer := 0; x : out integer );
end entity;
architecture goo of foo is
begin
end architecture;
configuration bar of foo is
use work.foo;
for goo
end for;
end configuration;
package p is
component c is
port ( x : bit );
end component;
end package;
entity something is
port ( a : in bit := '0' ) ;
end entity ;
use work.p;
use work.something;
architecture test of instance is
component foo is
end component;
signal x, c : integer;
signal s1, s2, s3 : integer;
signal v : bit_vector(1 to 3);
begin
a: foo;
b: entity work.foo;
b1: entity work.foo(goo);
c1: configuration work.bar;
d: component foo;
e: entity work.foo
port map ( s1, s2, s3 );
f: entity work.foo
port map ( s1, s2, x => s3 );
g: entity work.foo
generic map ( X => 1 )
port map ( s1, s2 );
h: entity work.foo
port map ( a => open );
i: foo port map ( x );
j: work.p.c port map ( '1' );
k: v(1) port map ( x );
l: entity something;
m: component something; -- Error
n: configuration something; -- Error
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/for4.vhd
|
1
|
422
|
entity for4 is
end entity;
architecture test of for4 is
begin
main: process is
variable n, count : natural;
begin
n := 6;
for i in 1 to n loop -- Discrete range evaluated here
n := 3; -- Does not affect loop trip count
count := count + 1;
end loop;
assert count = 6;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/vests33.vhd
|
1
|
1963
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3083.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests33 IS
END vests33;
ARCHITECTURE c12s06b03x00p02n01i03083arch OF vests33 IS
signal S1 : BIT;
signal X1 : BIT;
signal S : integer := 1;
BEGIN
S1 <= transport '1' after 5 ns;
A : block(X1 = '1')
begin
process(GUARD)
begin
if GUARD then
assert false
report "Failure on test. Guard value shouldn't have been changed" ;
S <= 0;
end if;
end process;
end block A;
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT(S = 1)
report "***PASSED TEST: c12s06b03x00p02n01i03083"
severity NOTE;
assert (S = 1)
report "***FAILED TEST: c12s06b03x00p02n01i03083 - GUARD signal is not modified in the test."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b03x00p02n01i03083arch;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd
|
3
|
11867
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/lower/cond1.vhd
|
1
|
397
|
entity cond1 is
end entity;
architecture test of cond1 is
signal x : integer := 5;
begin
p1: process is
variable y : integer;
begin
if x = y then
y := 2;
end if;
if x = y + 1 then
y := 1;
else
y := 3;
null;
end if;
report "doo";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/const4.vhd
|
5
|
529
|
entity const4 is
end entity;
architecture test of const4 is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := (
( 0, 3, 4, 5 ),
( 6, 7, 8, 9 ) );
begin
process is
begin
assert c'length(1) = 2;
assert c'length(2) = 4;
assert c(0, 0) = 0;
assert c(0, 1) = 3;
assert c(0, 3) = 5;
assert c(1, 0) = 6;
assert c(1, 1) = 7;
assert c(1, 2) = 8;
wait;
end process;
end architecture;
|
gpl-3.0
|
mistryalok/FPGA
|
Xilinx/ISE/Basics/muxx/muxx.vhd
|
1
|
1176
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:52:30 04/03/2013
-- Design Name:
-- Module Name: muxx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity muxx is
Port ( S : in bit_VECTOR (1 downto 0);
A : in STD_LOGIC_VECTOR (3 downto 0);
D : out STD_LOGIC);
end muxx;
architecture Behavioral of muxx is
begin
process(s)
--variable d : std_logic;
begin
case s is
when "00" => d <= A(0);
when "01" => d <= A(1);
when "10" => d <= A(2);
when "11" => d <= A(3);
end case;
-- D <= d;
end process;
end Behavioral;
|
gpl-3.0
|
nickg/nvc
|
test/regress/vests11.vhd
|
1
|
5816
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc485.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p19n01i00485ent_a IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END c03s02b01x01p19n01i00485ent_a;
architecture c03s02b01x01p19n01i00485ent_a of c03s02b01x01p19n01i00485ent_a is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY vests11 IS
END vests11;
ARCHITECTURE c03s02b01x01p19n01i00485arch OF vests11 IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
type array_rec_2cons is array (integer range <>) of record_2cons_array;
function resolution12(i:in array_rec_2cons) return record_2cons_array is
variable temp : record_2cons_array := C52;
begin
return temp;
end resolution12;
subtype array_rec_2cons_state is resolution12 record_2cons_array;
constant C66 : array_rec_2cons_state:= C52;
function complex_scalar(s : array_rec_2cons_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons_state is
begin
return C66;
end scalar_complex;
component c03s02b01x01p19n01i00485ent_a1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : c03s02b01x01p19n01i00485ent_a1 use entity work.c03s02b01x01p19n01i00485ent_a(c03s02b01x01p19n01i00485ent_a);
signal S1 : array_rec_2cons_state;
signal S2 : array_rec_2cons_state;
signal S3 : array_rec_2cons_state:= C66;
BEGIN
T1: c03s02b01x01p19n01i00485ent_a1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00485"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00485 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00485arch;
|
gpl-3.0
|
nickg/nvc
|
test/regress/elab25.vhd
|
5
|
595
|
entity sub is
port (
a : in bit_vector(2 downto 0);
b : out bit_vector(2 downto 0) );
end entity;
architecture test of sub is
begin
b <= a after 0 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab25 is
end entity;
architecture test of elab25 is
signal x0, x1 : bit_vector(1 downto 0);
signal y0, y1 : bit;
begin
sub_i: entity work.sub
port map (
a(1 downto 0) => x0,
a(2) => y0,
b(1 downto 0) => x1,
b(2) => y1 );
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/bounds/issue200.vhd
|
5
|
255
|
entity issue200 is
end entity;
architecture a of issue200 is
begin
main : process
-- Static error
variable bv : bit_vector(-1 downto 0) := (others => '0');
begin
report integer'image(bv'length);
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_axi_dma_0_0/synth/design_1_axi_dma_0_0.vhd
|
1
|
26132
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_9;
USE axi_dma_v7_1_9.axi_dma;
ENTITY design_1_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_dma_0_0;
ARCHITECTURE design_1_axi_dma_0_0_arch OF design_1_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_dma_0_0_arch : ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_dma_0_0_arch: ARCHITECTURE IS "design_1_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=23,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_" &
"AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=8,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=8,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 8,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 8,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_1_axi_dma_0_0_arch;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_sm.vhd
|
7
|
41813
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/simp/issue309.vhd
|
2
|
1226
|
-- test_ng.vhd
entity issue309 is
end issue309;
architecture MODEL of issue309 is
function check return boolean is
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(31 downto 4) := val_data(27 downto 0);
val_data( 3 downto 0) := org_data(i*4+3 downto i*4);
end loop;
return (val_data = org_data);
end function;
function check2 return boolean is
constant org_data : bit_vector(0 to 31) := "01110110010101000011001000010000";
variable val_data : bit_vector(0 to 31);
begin
val_data := (others => '0');
for i in 7 downto 0 loop
val_data(4 to 31) := val_data(0 to 27);
val_data(0 to 3) := org_data(i*4 to i*4+3);
end loop;
return (val_data = org_data);
end function;
constant c : boolean := check;
constant d : boolean := check2;
begin
g1: if c generate
assert true report "c";
end generate;
g2: if d generate
assert true report "d";
end generate;
end MODEL;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_doHist_0_1/synth/design_1_doHist_0_1.vhd
|
1
|
12433
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHist:1.0
-- IP Revision: 1606202043
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHist_0_1 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_doHist_0_1;
ARCHITECTURE design_1_doHist_0_1_arch OF design_1_doHist_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHist_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT doHist IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Din_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
histo_Dout_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT doHist;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doHist_0_1_arch: ARCHITECTURE IS "doHist,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doHist_0_1_arch : ARCHITECTURE IS "design_1_doHist_0_1,doHist,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF histo_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF histo_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF histo_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF histo_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF histo_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF histo_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF histo_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 histo_PORTA DOUT";
BEGIN
U0 : doHist
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 4,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
histo_Clk_A => histo_Clk_A,
histo_Rst_A => histo_Rst_A,
histo_EN_A => histo_EN_A,
histo_WEN_A => histo_WEN_A,
histo_Addr_A => histo_Addr_A,
histo_Din_A => histo_Din_A,
histo_Dout_A => histo_Dout_A
);
END design_1_doHist_0_1_arch;
|
gpl-3.0
|
nickg/nvc
|
test/eopt/ram1.vhd
|
1
|
506
|
entity ram1 is
end entity;
architecture test of ram1 is
type byte_array_t is array (natural range <>) of bit_vector(7 downto 0);
signal ram : byte_array_t(15 downto 0);
signal addr : integer;
signal dout : bit_vector(7 downto 0);
signal din : bit_vector(7 downto 0);
signal we : bit;
begin
dout_p: dout <= ram(addr);
wr_p: process (we, din, addr) is
begin
if we = '1' then
ram(addr) <= din;
end if;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_fifo.vhd
|
3
|
25002
|
-------------------------------------------------------------------------------
-- axi_datamover_fifo.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_fifo.vhd
-- Version: initial
-- Description:
-- This file is a wrapper file for the Synchronous FIFO used by the DataMover.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_10.axi_datamover_afifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_fifo is
generic (
C_DWIDTH : integer := 32 ;
-- Bit width of the FIFO
C_DEPTH : integer := 4 ;
-- Depth of the fifo in fifo width words
C_IS_ASYNC : Integer range 0 to 1 := 0 ;
-- 0 = Syncronous FIFO
-- 1 = Asynchronous (2 clock) FIFO
C_PRIM_TYPE : Integer range 0 to 2 := 2 ;
-- 0 = Register
-- 1 = Block Memory
-- 2 = SRL
C_FAMILY : String := "virtex7"
-- Specifies the Target FPGA device family
);
port (
-- Write Clock and reset -----------------
fifo_wr_reset : In std_logic; --
fifo_wr_clk : In std_logic; --
------------------------------------------
-- Write Side ------------------------------------------------------
fifo_wr_tvalid : In std_logic; --
fifo_wr_tready : Out std_logic; --
fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_wr_full : Out std_logic; --
--------------------------------------------------------------------
-- Read Clock and reset -----------------------------------------------
fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 --
fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 --
-----------------------------------------------------------------------
-- Read Side --------------------------------------------------------
fifo_rd_tvalid : Out std_logic; --
fifo_rd_tready : In std_logic; --
fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
fifo_rd_empty : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_fifo;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_datamover_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_prim_type
--
-- Function Description:
-- Sorts out the FIFO Primitive type selection based on fifo
-- depth and original primitive choice.
--
-------------------------------------------------------------------
function funct_get_prim_type (depth : integer;
input_prim_type : integer) return integer is
Variable temp_prim_type : Integer := 0;
begin
If (depth > 64) Then
temp_prim_type := 1; -- use BRAM
Elsif (depth <= 64 and
input_prim_type = 0) Then
temp_prim_type := 0; -- use regiaters
else
temp_prim_type := 1; -- use BRAM
End if;
Return (temp_prim_type);
end function funct_get_prim_type;
-- Signal declarations
Signal sig_init_reg : std_logic := '0';
Signal sig_init_reg2 : std_logic := '0';
Signal sig_init_done : std_logic := '0';
signal sig_inhibit_rdy_n : std_logic := '0';
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_REG
--
-- Process Description:
-- Registers the reset signal input.
--
-------------------------------------------------------------
IMP_INIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_init_reg <= '1';
sig_init_reg2 <= '1';
else
sig_init_reg <= '0';
sig_init_reg2 <= sig_init_reg;
end if;
end if;
end process IMP_INIT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INIT_DONE_REG
--
-- Process Description:
-- Create a 1 clock wide init done pulse.
--
-------------------------------------------------------------
IMP_INIT_DONE_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_init_done = '1') then
sig_init_done <= '0';
Elsif (sig_init_reg = '1' and
sig_init_reg2 = '1') Then
sig_init_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_INIT_DONE_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDY_INHIBIT_REG
--
-- Process Description:
-- Implements a ready inhibit flop.
--
-------------------------------------------------------------
IMP_RDY_INHIBIT_REG : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_inhibit_rdy_n <= '0';
Elsif (sig_init_done = '1') Then
sig_inhibit_rdy_n <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_RDY_INHIBIT_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SINGLE_REG
--
-- If Generate Description:
-- Implements a 1 deep register FIFO (synchronous mode only)
--
--
------------------------------------------------------------
USE_SINGLE_REG : if (C_IS_ASYNC = 0 and
C_DEPTH <= 1) generate
-- Local Constants
-- local signals
signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_regfifo_full_reg : std_logic := '0';
signal sig_regfifo_empty_reg : std_logic := '0';
signal sig_push_regfifo : std_logic := '0';
signal sig_pop_regfifo : std_logic := '0';
begin
-- Internal signals
-- Write signals
fifo_wr_tready <= sig_regfifo_empty_reg;
fifo_wr_full <= sig_regfifo_full_reg ;
sig_push_regfifo <= fifo_wr_tvalid and
sig_regfifo_empty_reg;
sig_data_in <= fifo_wr_tdata ;
-- Read signals
fifo_rd_tdata <= sig_regfifo_dout_reg ;
fifo_rd_tvalid <= sig_regfifo_full_reg ;
fifo_rd_empty <= sig_regfifo_empty_reg;
sig_pop_regfifo <= sig_regfifo_full_reg and
fifo_rd_tready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_FIFO
--
-- Process Description:
-- This process implements the data and full flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_FIFO : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1' or
sig_pop_regfifo = '1') then
sig_regfifo_full_reg <= '0';
elsif (sig_push_regfifo = '1') then
sig_regfifo_full_reg <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO;
IMP_REG_FIFO1 : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_dout_reg <= (others => '0');
elsif (sig_push_regfifo = '1') then
sig_regfifo_dout_reg <= sig_data_in;
else
null; -- don't change state
end if;
end if;
end process IMP_REG_FIFO1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_REG_EMPTY_FLOP
--
-- Process Description:
-- This process implements the empty flag for the
-- register fifo.
--
-------------------------------------------------------------
IMP_REG_EMPTY_FLOP : process (fifo_wr_clk)
begin
if (fifo_wr_clk'event and fifo_wr_clk = '1') then
if (fifo_wr_reset = '1') then
sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd)
-- it can't be asserted during reset
elsif (sig_pop_regfifo = '1' or
sig_init_done = '1') then
sig_regfifo_empty_reg <= '1';
elsif (sig_push_regfifo = '1') then
sig_regfifo_empty_reg <= '0';
else
null; -- don't change state
end if;
end if;
end process IMP_REG_EMPTY_FLOP;
end generate USE_SINGLE_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SRL_FIFO
--
-- If Generate Description:
-- Generates a fifo implementation usinf SRL based FIFOa
--
--
------------------------------------------------------------
USE_SRL_FIFO : if (C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 2 ) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_empty : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
sig_rd_valid <= not(sig_rd_empty);
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_SYNC_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => fifo_wr_clk ,
Reset => fifo_wr_reset ,
FIFO_Write => sig_wr_fifo ,
Data_In => sig_fifo_wr_data ,
FIFO_Read => sig_rd_fifo ,
Data_Out => sig_fifo_rd_data ,
FIFO_Empty => sig_rd_empty ,
FIFO_Full => sig_wr_full ,
Addr => open
);
end generate USE_SRL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_SYNC_FIFO
--
-- If Generate Description:
-- Instantiates a synchronous FIFO design for use in the
-- synchronous operating mode.
--
------------------------------------------------------------
USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and
(C_DEPTH > 64 or
(C_DEPTH > 1 and C_PRIM_TYPE < 2 )))
or
(C_IS_ASYNC = 0 and
C_DEPTH <= 64 and
C_DEPTH > 1 and
C_PRIM_TYPE = 0 )
generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant NEED_ALMOST_EMPTY : Integer := 0;
Constant NEED_ALMOST_FULL : Integer := 0;
Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1;
Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE);
-- local signals
signal sig_wr_full : std_logic := '0';
signal sig_wr_fifo : std_logic := '0';
signal sig_wr_ready : std_logic := '0';
signal sig_rd_fifo : std_logic := '0';
signal sig_rd_valid : std_logic := '0';
signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
begin
-- Write side signals
fifo_wr_tready <= sig_wr_ready;
fifo_wr_full <= sig_wr_full;
sig_wr_ready <= not(sig_wr_full) and
sig_inhibit_rdy_n;
sig_wr_fifo <= fifo_wr_tvalid and
sig_wr_ready;
sig_fifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_rd_valid;
fifo_rd_tdata <= sig_fifo_rd_data ;
fifo_rd_empty <= not(sig_rd_valid);
sig_rd_fifo <= sig_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_SYNC_FIFO
--
-- Description:
-- Implement the synchronous FIFO
--
------------------------------------------------------------
I_SYNC_FIFO : entity axi_datamover_v5_1_10.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_DATA_CNT_WIDTH => DATA_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY ,
C_NEED_ALMOST_FULL => NEED_ALMOST_FULL ,
C_USE_BLKMEM => PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => fifo_wr_reset ,
SFIFO_Clk => fifo_wr_clk ,
SFIFO_Wr_en => sig_wr_fifo ,
SFIFO_Din => fifo_wr_tdata ,
SFIFO_Rd_en => sig_rd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_rd_valid ,
SFIFO_Dout => sig_fifo_rd_data ,
SFIFO_Full => sig_wr_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
end generate USE_SYNC_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_ASYNC_FIFO
--
-- If Generate Description:
-- Instantiates an asynchronous FIFO design for use in the
-- asynchronous operating mode.
--
------------------------------------------------------------
USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate
-- Local Constants
Constant LOGIC_LOW : std_logic := '0';
Constant CNT_WIDTH : Integer := clog2(C_DEPTH);
-- local signals
signal sig_async_wr_full : std_logic := '0';
signal sig_async_wr_fifo : std_logic := '0';
signal sig_async_wr_ready : std_logic := '0';
signal sig_async_rd_fifo : std_logic := '0';
signal sig_async_rd_valid : std_logic := '0';
signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0);
signal sig_fifo_ainit : std_logic := '0';
Signal sig_init_reg : std_logic := '0';
begin
sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset;
-- Write side signals
fifo_wr_tready <= sig_async_wr_ready;
fifo_wr_full <= sig_async_wr_full;
sig_async_wr_ready <= not(sig_async_wr_full) and
sig_inhibit_rdy_n;
sig_async_wr_fifo <= fifo_wr_tvalid and
sig_async_wr_ready;
sig_afifo_wr_data <= fifo_wr_tdata;
-- Read Side Signals
fifo_rd_tvalid <= sig_async_rd_valid;
fifo_rd_tdata <= sig_afifo_rd_data ;
fifo_rd_empty <= not(sig_async_rd_valid);
sig_async_rd_fifo <= sig_async_rd_valid and
fifo_rd_tready;
------------------------------------------------------------
-- Instance: I_ASYNC_FIFO
--
-- Description:
-- Implement the asynchronous FIFO
--
------------------------------------------------------------
I_ASYNC_FIFO : entity axi_datamover_v5_1_10.axi_datamover_afifo_autord
generic map (
C_DWIDTH => C_DWIDTH ,
C_DEPTH => C_DEPTH ,
C_CNT_WIDTH => CNT_WIDTH ,
C_USE_BLKMEM => C_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
AFIFO_Ainit => sig_fifo_ainit ,
AFIFO_Ainit_Rd_clk => fifo_async_rd_reset ,
AFIFO_Wr_clk => fifo_wr_clk ,
AFIFO_Wr_en => sig_async_wr_fifo ,
AFIFO_Din => sig_afifo_wr_data ,
AFIFO_Rd_clk => fifo_async_rd_clk ,
AFIFO_Rd_en => sig_async_rd_fifo ,
AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
AFIFO_DValid => sig_async_rd_valid,
AFIFO_Dout => sig_afifo_rd_data ,
AFIFO_Full => sig_async_wr_full ,
AFIFO_Empty => open ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate USE_ASYNC_FIFO;
end imp;
|
gpl-3.0
|
nickg/nvc
|
test/sem/issue144.vhd
|
5
|
441
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
procedure proc(x : integer) is -- Error
begin
end procedure;
end package body;
|
gpl-3.0
|
nickg/nvc
|
test/regress/conv4.vhd
|
1
|
1831
|
package pack is
type int_vector is array (natural range <>) of natural;
function spread_ints (x : integer) return int_vector;
end package;
package body pack is
function spread_ints (x : integer) return int_vector is
variable r : int_vector(1 to 5);
begin
for i in 1 to 5 loop
r(i) := x;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port ( o1 : out int_vector(1 to 5);
i1 : in integer;
i2 : in int_vector(1 to 5) );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = 0;
assert i2 = (1 to 5 => 0);
o1 <= (1, 2, 3, 4, 5);
wait for 1 ns;
assert i1 = 150;
assert i2 = (1 to 5 => 42);
o1(1) <= 10;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity conv4 is
end entity;
use work.pack.all;
architecture test of conv4 is
signal x : integer;
signal y : int_vector(1 to 5);
signal q : natural;
function sum_ints(v : in int_vector) return integer is
variable result : integer := 0;
begin
for i in v'range loop
result := result + v(i);
end loop;
return result;
end function;
begin
uut: entity work.sub
port map ( sum_ints(o1) => x,
i1 => sum_ints(y),
i2 => spread_ints(q) );
p2: process is
begin
assert x = 0;
y <= (10, 20, 30, 40, 50);
q <= 42;
wait for 1 ns;
assert x = 15;
wait for 1 ns;
assert x = 24;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/ieee2.vhd
|
1
|
1079
|
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port (
clk : out std_logic;
cnt : inout integer := 0);
end entity;
architecture test of sub is
signal clk_i : bit := '0';
signal clk_std : std_logic;
begin
clk_i <= not clk_i after 1 ns;
clk_std <= to_stdulogic(clk_i);
clk <= clk_std;
process (clk_std) is
begin
if rising_edge(clk_std) then
cnt <= cnt + 1;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity ieee2 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of ieee2 is
signal cnt : integer := 0;
signal clk : std_logic;
begin
sub_i: entity work.sub port map ( clk, cnt );
process (clk) is
begin
if rising_edge(clk) then
report "clock!";
end if;
end process;
process is
begin
wait for 10 ns;
report integer'image(cnt);
assert cnt = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/alias13.vhd
|
1
|
521
|
entity alias13 is
end entity;
architecture test of alias13 is
type mat2d is array (natural range <>, natural range <>) of integer;
signal s1 : mat2d(1 to 2, 1 to 2);
alias a : mat2d is s1; -- OK (2008)
begin
main: process is
begin
s1 <= ((1, 2), (3, 4));
wait for 1 ns;
assert a = ((1, 2), (3, 4));
assert a(1, 1) = 1;
a(2, 2) <= 66;
wait for 1 ns;
assert s1 = ((1, 2), (3, 66));
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/func18.vhd
|
1
|
771
|
entity func18 is
end entity;
architecture test of func18 is
function get_array(n : in integer) return bit_vector is
-- The state struct for this function cannot be allocated on the stack
variable result : bit_vector(3 downto 0);
function get_xor return bit_vector is
begin
case n is
when 1 => return X"1";
when 2 => return X"2";
when others => return X"f";
end case;
end function;
begin
result := result xor get_xor;
return result;
end function;
begin
p1: process is
variable n : integer := 1;
begin
wait for 1 ns;
assert get_array(n) = X"1";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/simp/order1.vhd
|
1
|
312
|
package order1 is
type t is (A, B, C);
type t_vec is array (natural range <>) of t;
end package;
package order1 is
type t is (C, B, A); -- Redefine t
type t_vec is array (1 to 2) of t;
constant x : boolean := t_vec'(A, A) < t_vec'(C, C); -- Should not fold!
end package;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reg_module.vhd
|
3
|
87143
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
bd_eq : in std_logic
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + ((NUM_REG_PER_S2MM+1)*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(121*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
signal s2mm_msb_sa : std_logic_vector (31 downto 0);
signal mm2s_msb_sa : std_logic_vector (31 downto 0);
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or (same_tdest_arrived and (not bd_eq));
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1_9.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(121*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1_9.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(121*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
ADDR32_MSB : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_msb_sa <= (others => '0');
s2mm_msb_sa <= (others => '0');
end generate ADDR32_MSB;
ADDR64_MSB : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
mm2s_msb_sa <= mm2s_sa_i (63 downto 32);
s2mm_msb_sa <= s2mm_da_i (63 downto 32);
end generate ADDR64_MSB;
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i (31 downto 0) ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i (31 downto 0) ,
s2mm_length_i ,
mm2s_msb_sa ,
s2mm_msb_sa
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i (31 downto 0);
when MM2S_SA2_OFFSET =>
ip2axi_rddata <= mm2s_msb_sa; --mm2s_sa_i (63 downto 32);
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i (31 downto 0);
when S2MM_DA2_OFFSET =>
ip2axi_rddata <= s2mm_msb_sa; --s2mm_da_i (63 downto 32);
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue430.vhd
|
1
|
14585
|
library ieee;
use ieee.std_logic_1164.all;
package TYPES is
constant ADDR_MAX_WIDTH : integer := 64;
constant DATA_MAX_WIDTH : integer := 1024;
type CHANNEL_TYPE is (
CHANNEL_AR,
CHANNEL_AW,
CHANNEL_DR,
CHANNEL_DW,
CHANNEL_M
);
type ADDR_CHANNEL_SIGNAL_TYPE is record
ADDR : std_logic_vector(ADDR_MAX_WIDTH -1 downto 0);
WRITE : std_logic;
VALID : std_logic;
READY : std_logic;
end record;
type DATA_CHANNEL_SIGNAL_TYPE is record
DATA : std_logic_vector(DATA_MAX_WIDTH-1 downto 0);
LAST : std_logic;
VALID : std_logic;
READY : std_logic;
end record;
type CHANNEL_SIGNAL_TYPE is record
AR : ADDR_CHANNEL_SIGNAL_TYPE;
DR : DATA_CHANNEL_SIGNAL_TYPE;
AW : ADDR_CHANNEL_SIGNAL_TYPE;
DW : DATA_CHANNEL_SIGNAL_TYPE;
end record;
end package;
-----------------------------------------------------------------------------------
--! @brief CHANNEL_PLAYER :
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.TYPES.all;
entity CHANNEL_PLAYER is
generic (
CHANNEL : CHANNEL_TYPE;
MASTER : boolean := FALSE;
SLAVE : boolean := FALSE;
READ_ENABLE : boolean := TRUE;
WRITE_ENABLE : boolean := TRUE;
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32
);
port(
ACLK : in std_logic;
ARESETn : in std_logic;
ARADDR_I : in std_logic_vector(ADDR_WIDTH-1 downto 0);
ARADDR_O : out std_logic_vector(ADDR_WIDTH-1 downto 0);
ARVALID_I : in std_logic;
ARVALID_O : out std_logic;
ARREADY_I : in std_logic;
ARREADY_O : out std_logic;
RVALID_I : in std_logic;
RVALID_O : out std_logic;
RLAST_I : in std_logic;
RLAST_O : out std_logic;
RDATA_I : in std_logic_vector(DATA_WIDTH-1 downto 0);
RDATA_O : out std_logic_vector(DATA_WIDTH-1 downto 0);
RREADY_I : in std_logic;
RREADY_O : out std_logic;
AWADDR_I : in std_logic_vector(ADDR_WIDTH-1 downto 0);
AWADDR_O : out std_logic_vector(ADDR_WIDTH-1 downto 0);
AWVALID_I : in std_logic;
AWVALID_O : out std_logic;
AWREADY_I : in std_logic;
AWREADY_O : out std_logic;
WLAST_I : in std_logic;
WLAST_O : out std_logic;
WDATA_I : in std_logic_vector(DATA_WIDTH-1 downto 0);
WDATA_O : out std_logic_vector(DATA_WIDTH-1 downto 0);
WVALID_I : in std_logic;
WVALID_O : out std_logic;
WREADY_I : in std_logic;
WREADY_O : out std_logic;
FINISH : out std_logic
);
end CHANNEL_PLAYER;
architecture MODEL of CHANNEL_PLAYER is
procedure function_that_dies_with_this(signals : inout CHANNEL_SIGNAL_TYPE) is
procedure read_val(val: out std_logic_vector) is
constant null_val : std_logic_vector(val'length-1 downto 0) := (others => '0');
begin
val := null_val;
end procedure;
begin
read_val(signals.AR.ADDR(ADDR_WIDTH-1 downto 0));
end procedure;
begin
CHANNEL_M: if (CHANNEL = CHANNEL_M) generate
PROCESS_M: process
begin
FINISH <= '1';
wait;
end process;
end generate;
CHANNEL_A:if (CHANNEL = CHANNEL_AW or CHANNEL = CHANNEL_AR) generate
PROCESS_A: process
procedure execute_output is
begin
if (MASTER and WRITE_ENABLE and CHANNEL = CHANNEL_AW) then
AWADDR_O <= (others => '0');
AWVALID_O <= '0';
end if;
if (MASTER and READ_ENABLE and CHANNEL = CHANNEL_AR) then
ARADDR_O <= (others => '0');
ARVALID_O <= '0';
end if;
if (SLAVE and WRITE_ENABLE and CHANNEL = CHANNEL_AW) then
AWREADY_O <= '0';
end if;
if (SLAVE and READ_ENABLE and CHANNEL = CHANNEL_AR) then
ARREADY_O <= '0';
end if;
end procedure;
begin
FINISH <= '1';
wait;
end process;
end generate;
CHANNEL_D:if (CHANNEL = CHANNEL_DW or CHANNEL = CHANNEL_DR) generate
PROCESS_D: process
procedure execute_output is
begin
if (MASTER and WRITE_ENABLE and CHANNEL = CHANNEL_DW) then
WDATA_O <= (others => '0');
WLAST_O <= '0';
WVALID_O <= '0';
end if;
if (MASTER and READ_ENABLE and CHANNEL = CHANNEL_DR) then
RREADY_O <= '0';
end if;
if (SLAVE and WRITE_ENABLE and CHANNEL = CHANNEL_DW) then
WREADY_O <= '0';
end if;
if (SLAVE and READ_ENABLE and CHANNEL = CHANNEL_DR) then
RDATA_O <= (others => '0');
RLAST_O <= '0';
RVALID_O <= '0';
end if;
end procedure;
begin
execute_output; -- ! add this line.
FINISH <= '1';
wait;
end process;
end generate;
end MODEL;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.TYPES.all;
entity ISSUE430 is
end ISSUE430;
architecture MODEL of ISSUE430 is
constant READ_ENABLE : boolean := TRUE;
constant WRITE_ENABLE : boolean := TRUE;
constant ADDR_WIDTH : integer := 32;
constant DATA_WIDTH : integer := 32;
signal ACLK : std_logic;
signal ARESETn : std_logic;
signal ARADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal ARVALID : std_logic;
signal ARREADY : std_logic;
signal RLAST : std_logic;
signal RDATA : std_logic_vector(DATA_WIDTH-1 downto 0);
signal RVALID : std_logic;
signal RREADY : std_logic;
signal AWADDR : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal AWVALID : std_logic;
signal AWREADY : std_logic;
signal WLAST : std_logic;
signal WDATA : std_logic_vector(DATA_WIDTH-1 downto 0);
signal WVALID : std_logic;
signal WREADY : std_logic;
signal FINISH : std_logic;
begin
M: entity WORK.CHANNEL_PLAYER
generic map (
CHANNEL => CHANNEL_M ,
MASTER => FALSE ,
SLAVE => FALSE ,
READ_ENABLE => READ_ENABLE ,
WRITE_ENABLE => WRITE_ENABLE ,
ADDR_WIDTH => ADDR_WIDTH ,
DATA_WIDTH => DATA_WIDTH
)
port map(
ACLK => ACLK ,
ARESETn => ARESETn ,
ARADDR_I => ARADDR ,
ARVALID_I => ARVALID ,
ARREADY_I => ARREADY ,
RVALID_I => RVALID ,
RLAST_I => RLAST ,
RDATA_I => RDATA ,
RREADY_I => RREADY ,
AWADDR_I => AWADDR ,
AWVALID_I => AWVALID ,
AWREADY_I => AWREADY ,
WVALID_I => WVALID ,
WLAST_I => WLAST ,
WDATA_I => WDATA ,
WREADY_I => WREADY ,
FINISH => FINISH
);
AR: entity WORK.CHANNEL_PLAYER
generic map (
CHANNEL => CHANNEL_AR ,
MASTER => TRUE ,
SLAVE => FALSE ,
READ_ENABLE => READ_ENABLE ,
WRITE_ENABLE => WRITE_ENABLE ,
ADDR_WIDTH => ADDR_WIDTH ,
DATA_WIDTH => DATA_WIDTH
)
port map(
ACLK => ACLK ,
ARESETn => ARESETn ,
ARADDR_I => ARADDR ,
ARADDR_O => ARADDR ,
ARVALID_I => ARVALID ,
ARVALID_O => ARVALID ,
ARREADY_I => ARREADY ,
RVALID_I => RVALID ,
RLAST_I => RLAST ,
RDATA_I => RDATA ,
RREADY_I => RREADY ,
AWADDR_I => AWADDR ,
AWVALID_I => AWVALID ,
AWREADY_I => AWREADY ,
WVALID_I => WVALID ,
WLAST_I => WLAST ,
WDATA_I => WDATA ,
WREADY_I => WREADY
);
DR: entity WORK.CHANNEL_PLAYER
generic map (
CHANNEL => CHANNEL_DR ,
MASTER => TRUE ,
SLAVE => FALSE ,
READ_ENABLE => READ_ENABLE ,
WRITE_ENABLE => WRITE_ENABLE ,
ADDR_WIDTH => ADDR_WIDTH ,
DATA_WIDTH => DATA_WIDTH
)
port map(
ACLK => ACLK ,
ARESETn => ARESETn ,
ARADDR_I => ARADDR ,
ARVALID_I => ARVALID ,
ARREADY_I => ARREADY ,
RVALID_I => RVALID ,
RLAST_I => RLAST ,
RDATA_I => RDATA ,
RREADY_I => RREADY ,
RREADY_O => RREADY ,
AWADDR_I => AWADDR ,
AWVALID_I => AWVALID ,
AWREADY_I => AWREADY ,
WVALID_I => WVALID ,
WLAST_I => WLAST ,
WDATA_I => WDATA ,
WREADY_I => WREADY
);
AW: entity WORK.CHANNEL_PLAYER
generic map (
CHANNEL => CHANNEL_AW ,
MASTER => TRUE ,
SLAVE => FALSE ,
READ_ENABLE => READ_ENABLE ,
WRITE_ENABLE => WRITE_ENABLE ,
ADDR_WIDTH => ADDR_WIDTH ,
DATA_WIDTH => DATA_WIDTH
)
port map(
ACLK => ACLK ,
ARESETn => ARESETn ,
ARADDR_I => ARADDR ,
ARVALID_I => ARVALID ,
ARREADY_I => ARREADY ,
RVALID_I => RVALID ,
RLAST_I => RLAST ,
RDATA_I => RDATA ,
RREADY_I => RREADY ,
AWADDR_I => AWADDR ,
AWADDR_O => AWADDR ,
AWVALID_I => AWVALID ,
AWVALID_O => AWVALID ,
AWREADY_I => AWREADY ,
WVALID_I => WVALID ,
WLAST_I => WLAST ,
WDATA_I => WDATA ,
WREADY_I => WREADY
);
DW: entity WORK.CHANNEL_PLAYER
generic map (
CHANNEL => CHANNEL_DW ,
MASTER => TRUE ,
SLAVE => FALSE ,
READ_ENABLE => READ_ENABLE ,
WRITE_ENABLE => WRITE_ENABLE ,
ADDR_WIDTH => ADDR_WIDTH ,
DATA_WIDTH => DATA_WIDTH
)
port map(
ACLK => ACLK ,
ARESETn => ARESETn ,
ARADDR_I => ARADDR ,
ARVALID_I => ARVALID ,
ARREADY_I => ARREADY ,
RVALID_I => RVALID ,
RLAST_I => RLAST ,
RDATA_I => RDATA ,
RREADY_I => RREADY ,
AWADDR_I => AWADDR ,
AWVALID_I => AWVALID ,
AWREADY_I => AWREADY ,
WVALID_I => WVALID ,
WVALID_O => WVALID ,
WLAST_I => WLAST ,
WLAST_O => WLAST ,
WDATA_I => WDATA ,
WDATA_O => WDATA ,
WREADY_I => WREADY
);
process is
begin
wait until finish = '1' for 100 ns;
assert finish = '1';
assert wdata = (wdata'range => '0');
assert rvalid = 'U';
assert wvalid = '0';
wait;
end process;
end MODEL;
|
gpl-3.0
|
nickg/nvc
|
test/regress/driver5.vhd
|
5
|
513
|
entity driver5 is
end entity;
architecture test of driver5 is
type int_vec is array (integer range <>) of integer;
function resolved(x : int_vec) return integer is
begin
return x'length;
end function;
subtype rint is resolved integer;
signal s : rint;
begin
s <= 5;
process is
begin
assert s = 2;
wait for 0 ns;
assert s = 2;
s <= 4;
wait for 1 ns;
assert s = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/elab/issue330.vhd
|
2
|
2531
|
entity DUMMY is
generic(
BITS: integer := 1
);
port(
I: in bit_vector(BITS-1 downto 0);
O: out bit_vector(BITS-1 downto 0)
);
end DUMMY;
architecture MODEL of DUMMY is
begin
O <= I;
end MODEL;
-- test_ng_comp.vhd
entity TEST_NG_COMP is
generic (
INFO_BITS : integer := 1
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
O_INFO_1 : out bit_vector(INFO_BITS-1 downto 0)
);
end TEST_NG_COMP;
architecture MODEL of TEST_NG_COMP is
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
INFO_0 : INFO_RANGE_TYPE;
INFO_1 : INFO_RANGE_TYPE;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
d_pos := d_pos + BITS;
end procedure;
begin
d_pos := 0;
v.DATA_LO := d_pos;
SET_INFO_RANGE(v.INFO_0, INFO_BITS);
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
v.DATA_HI := d_pos - 1;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal i_data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
component DUMMY
generic(
BITS: integer := 1
);
port(
I: in bit_vector(BITS-1 downto 0);
O: out bit_vector(BITS-1 downto 0)
);
end component;
begin
I0: DUMMY generic map(BITS => INFO_BITS) port map(
I => I_INFO_0,
O => i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO)
);
I1: DUMMY generic map(BITS => INFO_BITS) port map(
I => I_INFO_1,
O => i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO)
);
O_INFO_0 <= i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO);
O_INFO_1 <= i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO);
end MODEL;
|
gpl-3.0
|
nickg/nvc
|
test/regress/vests23.vhd
|
1
|
22985
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests23 IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END vests23;
ARCHITECTURE c01s01b01x01p05n02i00749arch OF vests23 IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st := (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a :record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new := (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record := (C85,C86,C88);
signal V1 : boolean_vector(zero to fifteen) ;
signal V2 : severity_level_vector(zero to fifteen);
signal V3 : integer_vector(zero to fifteen) ;
signal V4 : real_vector(zero to fifteen) ;
signal V5 : time_vector (zero to fifteen);
signal V6 : natural_vector(zero to fifteen);
signal V7 : positive_vector(zero to fifteen);
signal V8 : boolean_cons_vector;
signal V9 : severity_level_cons_vector ;
signal V10 : integer_cons_vector;
signal V11 : real_cons_vector;
signal V12 : time_cons_vector ;
signal V13 : natural_cons_vector ;
signal V14 : positive_cons_vector ;
signal V15 : boolean_cons_vectorofvector ;
signal V16 : severity_level_cons_vectorofvector;
signal V17 : integer_cons_vectorofvector;
signal V18 : real_cons_vectorofvector;
signal V19 : time_cons_vectorofvector;
signal V20 : natural_cons_vectorofvector;
signal V21 : positive_cons_vectorofvector;
signal V22 : record_std_package;
signal V23 : record_cons_array ;
signal V24 : record_cons_arrayofarray ;
signal V25 : boolean_vector_st ;
signal V26 : severity_level_vector_st ;
signal V27 : integer_vector_st ;
signal V28 : real_vector_st ;
signal V29 : time_vector_st ;
signal V30 : natural_vector_st ;
signal V31 : positive_vector_st ;
signal V32 : record_array_st ;
signal V33 : record_array_st ;
signal V34 : record_array_new ;
signal V35 : record_of_records ;
signal V36 : byte ;
signal V37 : word ;
signal V41 : boolean_vector_range ;
signal V42 : severity_level_vector_range ;
signal V43 : integer_vector_range ;
signal V44 : real_vector_range ;
signal V45 : time_vector_range ;
signal V46 : natural_vector_range ;
signal V47 : positive_vector_range ;
signal V48 : array_rec_std(zero to seven) ;
signal V49 : array_rec_cons(zero to seven) ;
signal V50 : array_rec_rec(zero to seven) ;
signal V51 : record_of_arr_of_record ;
BEGIN
V1 <= (zero to fifteen => C1);
V2 <= (zero to fifteen => C4);
V3 <= (zero to fifteen => C5);
V4 <= (zero to fifteen => C6);
V5 <= (zero to fifteen => C7);
V6 <= (zero to fifteen => C8);
V7 <= (zero to fifteen => C9);
V8 <= C19;
V9 <= C20;
V10 <= C21;
V11 <= C22;
V12 <= C23;
V13 <= C24;
V14 <= C25;
V15 <= C26;
V16 <= C27;
V17 <= C28;
V18 <= C29;
V19 <= C30;
V20 <= C31;
V21 <= C32;
V22 <= C50;
V23 <= C51;
V24 <= C53;
V25 <= C70;
V26 <= C71;
V27 <= C72;
V28 <= C73;
V29 <= C74;
V30 <= C75;
V31 <= C76;
V32 <= C54a;
V33 <= C54a;
V34 <= C54b;
V35 <= C55;
V36 <= C60;
V37 <= C61;
V41 <= C78;
V42 <= C79;
V43 <= C80;
V44 <= C81;
V45 <= C82;
V46 <= C83;
V47 <= C84;
V48 <= C85;
V49 <= C86;
V50 <= C88;
V51 <= C102;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34= C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00749"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00749arch;
|
gpl-3.0
|
nickg/nvc
|
test/parse/issue205.vhd
|
5
|
145
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
report """""";
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd
|
3
|
17333
|
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1_10.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue549.vhd
|
1
|
820
|
package pack is
constant C : integer;
type rec is record
x : integer;
y : bit_vector(1 to C);
end record;
end package;
package body pack is
constant C : integer := 4;
end package body;
-------------------------------------------------------------------------------
entity issue549 is
end entity;
use work.pack.all;
architecture test of issue549 is
constant def : rec := (x => 0, y => "0000");
procedure modify (variable arg : inout rec) is
begin
arg.y(1) := '1';
end procedure;
procedure test (arg : in rec) is
variable copy : rec := def;
begin
copy.y := arg.y;
modify(copy);
assert def.y = "0000";
assert copy.y = "1110";
end procedure;
begin
p1: test((x => 1, y => "0110"));
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/record36.vhd
|
1
|
602
|
entity record36 is
end entity;
architecture test of record36 is
type rec is record
s : string;
end record;
procedure test (r : inout rec) is
variable rr : r'subtype;
begin
rr := r;
for i in rr.s'range loop
rr.s(i) := 'X';
end loop;
r := rr;
end procedure;
begin
p1: process is
variable r : rec(s(1 to 3));
begin
r := (s => "abc");
test(r);
assert r.s = "XXX";
r.s := "foo";
test(r);
assert r.s = "XXX";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/lower/issue215.vhd
|
1
|
775
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
variable oo : integer;
begin
PROC_A(I,oo);
O <= oo;
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue340.vhd
|
2
|
1113
|
entity submodule is
port (
sig : in bit);
end entity;
architecture a of submodule is
begin
main : process
begin
wait for 1 ns;
assert sig = '1';
report "Success";
wait;
end process;
end;
entity issue340 is
end entity;
architecture a of issue340 is
signal sig_vector : bit_vector(0 to 1) := "00";
alias sig_bit_alias : bit is sig_vector(0);
signal sig : bit := '0';
alias sig_alias : bit is sig;
procedure drive(signal value : out bit) is
begin
value <= '1';
end;
begin
main : process
begin
drive(sig_alias);
drive(sig_bit_alias);
wait for 1 ns;
assert sig_vector(0) = '1';
assert sig = '1';
assert sig_alias = '1';
assert sig_bit_alias = '1';
report "Success";
wait;
end process;
submodule0_inst : entity work.submodule
port map (
sig => sig_alias);
submodule1_inst : entity work.submodule
port map (
sig => sig_bit_alias);
submodule2_inst : entity work.submodule
port map (
sig => sig);
submodule3_inst : entity work.submodule
port map (
sig => sig_vector(0));
end;
|
gpl-3.0
|
nickg/nvc
|
test/sem/signal.vhd
|
1
|
2391
|
entity e is
port (
p : in bit );
end entity;
architecture a of e is
signal v : bit_vector(1 to 3);
signal x, y, z : bit;
begin
process is
begin
(x, y, z) <= v; -- OK
(x, y, z) <= x; -- Error
(x, y, z) <= "101"; -- Error
(bit'('1'), y, z) <= v; -- Error
(others => x) <= v; -- Error
(p, y, z) <= v; -- Error
end process;
(x, y, z) <= v; -- OK
(x, y, z) <= x; -- Error
(bit'('1'), y, z) <= v; -- Error
(others => x) <= v; -- Error
(p, y, z) <= v; -- Error
process is
variable i : integer;
begin
(v(i), v(1), v(2)) <= v; -- Error
end process;
b1: block is
procedure proc1 (signal s : out bit) is
procedure nested is
begin
s <= '0'; -- OK
end procedure;
begin
x <= '1'; -- Error
s <= '1'; -- OK
end procedure;
begin
end block;
b2: block (true) is
begin
guard <= false; -- Error
end block;
b3: block is
signal guard : integer;
begin
x <= guarded not x; -- Error
end block;
b4: block (v) is -- Error
begin
end block;
b5: block is
constant guard : boolean := false;
begin
x <= guarded not x; -- Error
x <= null; -- Error
end block;
b6: block is
signal q : integer bus; -- Error
begin
end block;
b7: block is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
signal s : rbit bus; -- OK
disconnect s : rbit after 1 ns; -- OK
disconnect 'x' : character after 1 ns; -- Error
disconnect v : bit_vector after 1 ns; -- Error
disconnect s : bit_vector after 2 ns; -- Error
disconnect s : rbit after s; -- Error
signal i : integer;
disconnect s : rbit after i * ns; -- Error
begin
end block;
b8: block is
signal bad : bit := e; -- Error
begin
end block;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_sitofp_4_no_dsp_32/sim/doHistStretch_ap_sitofp_4_no_dsp_32.vhd
|
1
|
10511
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_sitofp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_sitofp_4_no_dsp_32;
ARCHITECTURE doHistStretch_ap_sitofp_4_no_dsp_32_arch OF doHistStretch_ap_sitofp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_sitofp_4_no_dsp_32_arch;
|
gpl-3.0
|
nickg/nvc
|
test/jit/relop1.vhd
|
1
|
421
|
package relop1 is
type uint8 is range 0 to 255;
function cmpless (x, y : uint8) return boolean;
function cmpless (x, y : real) return boolean;
end package;
package body relop1 is
function cmpless (x, y : uint8) return boolean is
begin
return x < y;
end function;
function cmpless (x, y : real) return boolean is
begin
return x < y;
end function;
end package body;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/hdl/vhdl/parity.vhd
|
7
|
11625
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
gpl-3.0
|
nickg/nvc
|
test/regress/gensub4.vhd
|
1
|
1540
|
package genfact is
function fact generic (type t;
function "*"(l, r : t) return t is <>;
function "-"(l, r : t) return t is <>;
function "<"(l, r : t) return boolean is <>;
one : t) (n : t) return t;
end package;
package body genfact is
function fact generic (type t;
function "*"(l, r : t) return t is <>;
function "-"(l, r : t) return t is <>;
function "<"(l, r : t) return boolean is <>;
one : t) (n : t) return t is
begin
if n < one then
return one;
else
return n * fact(n - ONE);
end if;
end function;
end package body;
-------------------------------------------------------------------------------
entity gensub4 is
end entity;
architecture test of gensub4 is
function fact_int is new work.genfact.fact
generic map (t => integer, one => 1);
function fact_real is new work.genfact.fact
generic map (t => real, one => 1.0);
signal s : integer;
signal r : real;
begin
p1: process is
begin
assert fact_int(1) = 1;
assert fact_int(5) = 120;
assert fact_real(1.0) = 1.0;
assert fact_real(4.0) = 24.0;
s <= 4;
r <= 2.0;
wait for 1 ns;
assert fact_int(s) = 24;
assert fact_real(r) = 2.0;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/access4.vhd
|
1
|
556
|
entity access4 is
end entity;
architecture test of access4 is
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
begin
process is
variable p : int_vec_ptr;
begin
p := new int_vec(1 to 10);
p(1 to 3) := (1, 2, 3);
assert p(1 to 3) = (1, 2, 3);
assert p(2) = 2;
p.all(4 to 6) := (4, 5, 6);
assert p.all(4) = 4;
assert p'length = 10;
assert p.all'low = 1;
deallocate(p);
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/lower/protupref.vhd
|
1
|
2746
|
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
end protected AlertLogStructPType ;
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
begin
report ALERT_NAME(Level); -- Lower crash here
end procedure alert ;
end protected body AlertLogStructPType ;
end package body AlertLogPkg ;
|
gpl-3.0
|
nickg/nvc
|
test/simp/func9.vhd
|
5
|
494
|
entity func9 is
end entity;
architecture test of func9 is
constant msg0 : string := "zero";
constant msg1 : string := "one";
function get_message(x : in bit) return string is
begin
case x is
when '0' => return msg0;
when '1' => return msg1;
end case;
end function;
begin
process is
begin
assert get_message('1') = "one";
assert get_message('0') = "zero";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/assign1.vhd
|
5
|
585
|
entity assign1 is
end entity;
architecture test of assign1 is
begin
process is
variable x, y : integer;
begin
x := 5;
y := 7;
assert x = 5;
assert y = 7;
wait for 1 ns;
assert x + y = 12;
wait;
end process;
process is
variable x : integer := 64;
variable y : integer := -4;
begin
wait for 4 ns;
assert x = 64 report "x not 64";
assert y = -4 report "y not -4";
x := y * 2;
assert x = -8;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/elab/gbounds.vhd
|
2
|
525
|
entity sub is
generic (
X : integer );
end entity;
architecture test of sub is
signal s : bit_vector(7 downto 0);
begin
gen: if x >= s'low and x <= s'high generate
s(x) <= '1';
end generate;
end architecture;
-------------------------------------------------------------------------------
entity gbounds is
end entity;
architecture test of gbounds is
begin
sub1: entity work.sub generic map ( 2 ); -- OK
sub2: entity work.sub generic map ( 9 ); -- No error
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sg_if.vhd
|
3
|
81371
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue433.vhd
|
1
|
934
|
entity SAMPLE is
generic (NAME: string := ""; delay : delay_length);
end entity;
architecture MODEL of SAMPLE is
begin
process begin
wait for delay;
assert (FALSE) report NAME & ":OK" severity NOTE;
wait;
end process;
end MODEL;
entity SAMPLE_NG is
generic (NAME: string := ""; delay : delay_length);
end entity;
architecture MODEL of SAMPLE_NG is
component SAMPLE generic(NAME: STRING := ""; delay : delay_length); end component;
begin
U: SAMPLE generic map (NAME => NAME & "(" & ")", delay => delay);
end MODEL;
entity issue433 is
generic (NAME: string := "TEST_NG");
end entity;
architecture MODEL of issue433 is
component SAMPLE_NG generic(NAME: STRING := ""; delay : delay_length); end component;
begin
U1: SAMPLE_NG generic map(NAME => NAME & string'(":U1"), delay => 1 ns);
U2: SAMPLE_NG generic map(NAME => NAME & string'(":U2"), delay => 2 ns);
end MODEL;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_timer_v2_0/hdl/src/vhdl/tc_types.vhd
|
10
|
6731
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
gpl-3.0
|
nickg/nvc
|
test/regress/conf1.vhd
|
1
|
2564
|
entity comparison is
port (
a : in integer;
b : in integer;
q : out boolean );
end comparison;
architecture rtl of comparison is
begin
q <= a = b;
end architecture;
-------------------------------------------------------------------------------
entity comparison_tb is
generic ( delay : delay_length );
end entity;
architecture sim of comparison_tb is
signal a : integer;
signal b : integer;
signal q : boolean;
component comparison
port (
a : in integer;
b : in integer;
q : out boolean );
end component;
procedure result(a, b : in integer; q : in boolean) is
begin
report integer'image(a) & " <=> " & integer'image(b)
& " = " & boolean'image(q);
end procedure;
begin
DUT: component comparison
port map (
a => a,
b => b,
q => q );
SEQUENCER_PROC: process
begin
wait for delay;
a <= 4;
b <= 2;
wait for 1 ns;
result(a, b, q);
b <= 7;
wait for 1 ns;
result(a, b, q);
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity greater_than is
port (
a : in integer;
b : in integer;
q : out boolean );
end greater_than;
architecture rtl of greater_than is
begin
q <= a > b;
end architecture;
-------------------------------------------------------------------------------
configuration eq of comparison_tb is
for sim
end for;
end configuration;
-------------------------------------------------------------------------------
configuration gt of comparison_tb is
for sim
for DUT : comparison
use entity work.greater_than(rtl);
end for;
end for;
end configuration;
-------------------------------------------------------------------------------
configuration lt of comparison_tb is
for sim
for DUT : comparison
use entity work.greater_than(rtl)
port map (
a => b,
b => a,
q => q );
end for;
end for;
end configuration;
-------------------------------------------------------------------------------
entity conf1 is
end entity;
architecture test of conf1 is
begin
uut1: configuration work.lt
generic map ( delay => 0 ns );
uut2: configuration work.gt
generic map ( delay => 10 ns );
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/elab/open.vhd
|
5
|
542
|
entity open_bot is
port (
i : in integer;
o : out integer;
v : out bit_vector(3 downto 0) := X"f" );
end entity;
architecture test of open_bot is
begin
v(1) <= '0';
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity open_top is
end entity;
architecture test of open_top is
signal x : integer;
begin
uut: entity work.open_bot
port map ( x, open );
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue323.vhd
|
2
|
1013
|
entity issue323 is
end entity;
architecture test of issue323 is
type intfile is protected
procedure iwrite(x : in integer);
procedure iread(x : out integer);
end protected;
type intfile is protected body
type ft is file of integer;
file f : ft;
constant FNAME : string := "data";
procedure iwrite(x : in integer) is
begin
file_open(f, FNAME, WRITE_MODE);
write(f, x);
file_close(f);
end procedure;
procedure iread(x : out integer) is
begin
file_open(f, FNAME, READ_MODE);
read(f, x);
file_close(f);
end procedure;
end protected body;
shared variable f : intfile;
begin
p0: process is
begin
f.iwrite(42);
wait;
end process;
p1: process is
variable x : integer;
begin
wait for 1 ns;
f.iread(x);
assert x = 42;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/parse/loc.vhd
|
1
|
169
|
entity e is end entity;
architecture a of e is
procedure f(x, y, z : integer);
signal x : bit;
begin
f(1, 2, 3 + 5);
assert x'active;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd
|
18
|
75691
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_demux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_datamover_wr_demux;
architecture implementation of axi_datamover_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/elab4.vhd
|
5
|
740
|
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/simp/issue362.vhd
|
2
|
740
|
entity bug is
end entity;
architecture a of bug is
type enum_t is (enum0, enum1);
subtype enum_subtype_t is enum_t;
type enum_vec_t is array (natural range <>) of enum_t;
function resolve_enum(values : enum_vec_t) return enum_t;
subtype resolved_enum_t is resolve_enum enum_t;
function resolve_enum(values : enum_vec_t) return enum_t is
begin
return values(0);
end;
function func return enum_t is
begin
return enum_subtype_t'low;
end;
function func2 return enum_t is
begin
return resolved_enum_t'high;
end;
begin
main : process is
begin
-- Should both be optimised out during constant folding
assert func = enum_t'low;
assert func2 = enum_t'high;
wait;
end process;
end;
|
gpl-3.0
|
nickg/nvc
|
lib/vital/prmtvs_p.vhdl
|
7
|
68530
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
-- v95.3 | ddl | 09/24/96 | #236 - VitalTruthTable DataIn should be of
-- | | | of class SIGNAL (PROPOSED)
-- ----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
SIGNAL DataIn : IN std_logic_vector -- IR#236
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector); --IR236 4/2/98
END VITAL_Primitives;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd
|
3
|
74551
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_10.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_10.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_10.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_10.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_10.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_10.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_10.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_10.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/sim/vhdl/doHistStretch_fmul_32ns_32ns_32_4_max_dsp.vhd
|
5
|
3113
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity doHistStretch_fmul_32ns_32ns_32_4_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 4;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of doHistStretch_fmul_32ns_32ns_32_4_max_dsp is
--------------------- Component ---------------------
component doHistStretch_ap_fmul_2_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
doHistStretch_ap_fmul_2_max_dsp_32_u : component doHistStretch_ap_fmul_2_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/operator3.vhd
|
5
|
934
|
entity operator3 is
end entity;
architecture test of operator3 is
type int_array is array (integer range <>) of integer;
begin
process is
variable x : int_array(1 to 3);
variable y : bit_vector(1 to 3);
begin
x := (1, 2, 3);
assert x < (2, 2, 3);
assert x > (0, 0, 0);
assert x < (1, 2, 4);
assert x < (1, 2, 3, 4);
assert not (x < (1, 2));
assert x <= (1, 2, 3);
assert x >= (1, 2, 3);
assert x >= (1, 1, 1);
y := "000";
assert not (y < "000");
assert not (y < "00");
assert not ("000" < y);
assert "00" < y;
assert y <= "000";
assert not (y <= "00");
assert "000" <= y;
assert "00" <= y;
assert not (y > "000");
assert not ("000" > y);
assert y > "00";
assert not ("00" > y);
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/concat6.vhd
|
1
|
2913
|
entity concat6 is
end entity;
architecture test of concat6 is
-- Examples from LRM 93 section 7.2.5
type R1 is range 0 to 7;
type R2 is range 7 downto 0;
type T1 is array (R1 range <>) of Bit;
type T2 is array (R2 range <>) of Bit;
subtype S1 is T1(R1);
subtype S2 is T2(R2);
constant K1: S1 := (others => '0');
constant K2: T1 := K1(1 to 3) & K1(3 to 4); -- K2'Left = 0 and K2'Right = 4
constant K3: T1 := K1(5 to 7) & K1(1 to 2); -- K3'Left = 0 and K3'Right = 4
constant K4: T1 := K1(2 to 1) & K1(1 to 2); -- K4'Left = 0 and K4'Right = 1
constant K5: S2 := (others => '0');
constant K6: T2 := K5(3 downto 1) & K5(4 downto 3); -- K6'Left = 7 and K6'Right = 3
constant K7: T2 := K5(7 downto 5) & K5(2 downto 1); -- K7'Left = 7 and K7'Right = 3
constant K8: T2 := K5(1 downto 2) & K5(2 downto 1); -- K8'Left = 7 and K8'Right = 6
function get_left(x : T1) return R1 is
begin
return x'left;
end function;
function get_left(x : T2) return R2 is
begin
return x'left;
end function;
function get_right(x : T1) return R1 is
begin
return x'right;
end function;
function get_right(x : T2) return R2 is
begin
return x'right;
end function;
begin
main: process is
begin
assert K2'left = 0 report R1'image(K2'left);
assert get_left(K2) = 0 report R1'image(K2'left);
assert K2'right = 4 report R1'image(K2'right);
assert get_right(K2) = 4 report R1'image(K2'right);
assert K2'ascending;
assert K3'left = 0 report R1'image(K3'left);
assert get_left(K3) = 0 report R1'image(K3'left);
assert K3'right = 4 report R1'image(K3'right);
assert get_right(K3) = 4 report R1'image(K3'right);
assert K3'ascending;
assert K4'left = 0 report R1'image(K4'left);
assert get_left(K4) = 0 report R1'image(K4'left);
assert K4'right = 1 report R1'image(K4'right);
assert get_right(K4) = 1 report R1'image(K4'right);
assert K4'ascending;
assert K6'left = 7 report R2'image(K6'left);
assert get_left(K6) = 7 report R2'image(K6'left);
assert K6'right = 3 report R2'image(K6'right);
assert get_right(K6) = 3 report R2'image(K6'right);
assert not K6'ascending;
assert K7'left = 7 report R2'image(K7'left);
assert get_left(K7) = 7 report R2'image(K7'left);
assert K7'right = 3 report R2'image(K7'right);
assert get_right(K7) = 3 report R2'image(K7'right);
assert not K6'ascending;
assert K8'left = 7 report R2'image(K8'left);
assert get_left(K8) = 7 report R2'image(K8'left);
assert K8'right = 6 report R2'image(K8'right);
assert get_right(K8) = 6 report R2'image(K8'right);
assert not K6'ascending;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/access9.vhd
|
1
|
749
|
-- Test garbage collection
entity access9 is
end entity;
architecture test of access9 is
type int_vec is array (natural range <>) of integer;
type int_vec_ptr is access int_vec;
type rec is record
s : string(1 to 50);
i : integer;
p : int_vec_ptr;
end record;
type rec_ptr is access rec;
procedure do_test (p : inout rec_ptr) is
begin
p := new rec;
p.p := new int_vec(1 to 1000);
end procedure;
begin
p1: process is
variable p : rec_ptr;
begin
for i in 1 to 1000 loop
for j in 1 to 100 loop
do_test(p);
end loop;
wait for 1 ns;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/real3.vhd
|
4
|
370
|
entity real3 is
end real3;
architecture Behavioral of real3 is
signal value_real : real := -523467.0;
signal value_integer : integer;
begin
process
begin
report "real: " & real'image(value_real);
value_integer <= integer(value_real);
wait for 0 ns;
report "integer: " & integer'image(value_integer);
wait;
end process;
end Behavioral;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/pselect_f.vhd
|
28
|
10116
|
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
|
gpl-3.0
|
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