repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
nickg/nvc
|
test/regress/record2.vhd
|
5
|
468
|
entity record2 is
end entity;
architecture test of record2 is
type rec is record
x, y : integer;
end record;
procedure set_to(variable r : inout rec;
constant n : in integer) is
begin
r.x := n;
r.y := r.x;
end procedure;
begin
process is
variable r : rec;
begin
set_to(r, 5);
assert r.x = 5;
assert r.y = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_rd_status_cntl.vhd
|
13
|
18971
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_rd_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_rd_status_cntl is
generic (
C_STS_WIDTH : Integer := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the Status reply
);
port (
-- Clock and Reset input --------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Calculator Status Interface ---------------------------
--
calc2rsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
-------------------------------------------------------------------
-- Address Controller Status Interface ----------------------------
--
addr2rsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- is empty (no commands pending) --
--
addr2rsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
-------------------------------------------------------------------
-- Data Controller Status Interface ---------------------------------------------
--
data2rsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2rsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- is empty (no commands pending) --
--
data2rsc_okay : In std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : In std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : In std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : In std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : Out std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : in std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
----------------------------------------------------------------------------------
-- Command/Status Module Interface ----------------------------------------------
--
rsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2rsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is ready to accept a transfer --
--
rsc2stat_status_valid : Out std_logic ; --
-- Control Signal to the Status Reg/FIFO indicating a new status --
-- output value is valid and ready for transfer --
---------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt ----------------------------------
--
rsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
---------------------------------------------------------------------------
);
end entity axi_sg_rd_status_cntl;
architecture implementation of axi_sg_rd_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
-- Signal Declarations --------------------------------------------
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_rsc2status_valid : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_rd_sts_okay_reg : std_logic := '0';
signal sig_rd_sts_interr_reg : std_logic := '0';
signal sig_rd_sts_decerr_reg : std_logic := '0';
signal sig_rd_sts_slverr_reg : std_logic := '0';
signal sig_rd_sts_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_rd_sts_reg : std_logic := '0';
signal sig_push_rd_sts_reg : std_logic := '0';
Signal sig_rd_sts_push_ok : std_logic := '0';
signal sig_rd_sts_reg_empty : std_logic := '0';
signal sig_rd_sts_reg_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the status write output control
rsc2stat_status_valid <= sig_rsc2status_valid ;
sig_rsc2status_valid <= sig_rd_sts_reg_full;
-- Formulate the status outout value (assumes an 8-bit status width)
rsc2stat_status <= sig_rd_sts_okay_reg &
sig_rd_sts_slverr_reg &
sig_rd_sts_decerr_reg &
sig_rd_sts_interr_reg &
sig_tag2status;
-- Detect that a push of a new status word is completing
sig_rd_sts_push_ok <= sig_rsc2status_valid and
stat2rsc_status_ready;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it
rsc2mstr_halt_pipe <= sig_rsc2status_valid and
(not(stat2rsc_status_ready) );
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_rd_sts_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0);
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_rd_sts_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_rd_sts_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
------- Read Status Collection Logic --------------------------------
rsc2data_ready <= sig_rsc2data_ready ;
sig_rsc2data_ready <= sig_rd_sts_reg_empty;
sig_push_rd_sts_reg <= data2rsc_valid and
sig_rsc2data_ready;
sig_pop_rd_sts_reg <= sig_rd_sts_push_ok;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_STATUS_FIFO_REG
--
-- Process Description:
-- Implement Read status FIFO register.
-- This register holds the Read status from the Data Controller
-- until it is transfered to the Status FIFO.
--
-------------------------------------------------------------
RD_STATUS_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_rd_sts_reg = '1') then
sig_rd_sts_tag_reg <= (others => '0');
sig_rd_sts_interr_reg <= '0';
sig_rd_sts_decerr_reg <= '0';
sig_rd_sts_slverr_reg <= '0';
sig_rd_sts_okay_reg <= '1'; -- set back to default of "OKAY"
sig_rd_sts_reg_full <= '0';
sig_rd_sts_reg_empty <= '1';
Elsif (sig_push_rd_sts_reg = '1') Then
sig_rd_sts_tag_reg <= data2rsc_tag;
sig_rd_sts_interr_reg <= data2rsc_calc_error or
sig_rd_sts_interr_reg;
sig_rd_sts_decerr_reg <= data2rsc_decerr or sig_rd_sts_decerr_reg;
sig_rd_sts_slverr_reg <= data2rsc_slverr or sig_rd_sts_slverr_reg;
sig_rd_sts_okay_reg <= data2rsc_okay and
not(data2rsc_decerr or
sig_rd_sts_decerr_reg or
data2rsc_slverr or
sig_rd_sts_slverr_reg or
data2rsc_calc_error or
sig_rd_sts_interr_reg
);
sig_rd_sts_reg_full <= data2rsc_cmd_cmplt or
data2rsc_calc_error;
sig_rd_sts_reg_empty <= not(data2rsc_cmd_cmplt or
data2rsc_calc_error);
else
null; -- hold current state
end if;
end if;
end process RD_STATUS_FIFO_REG;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue90.vhd
|
5
|
510
|
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/elab/bounds10.vhd
|
5
|
642
|
entity UC is
port(
an_input: in bit_vector;
an_output: out bit_vector
);
end entity;
architecture test of UC is
begin
an_output <= an_input;
end architecture;
-------------------------------------------------------------------------------
entity bounds10 is
end entity;
architecture test of bounds10 is
signal an_input: bit_vector( 0 downto 0);
signal an_output: bit_vector(100 downto 0);
begin
UC:
entity work.UC
port map
(
an_input => an_input,
an_output => an_output
);
TEST:
an_input <= "0", "1" after 1 ns;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue521.vhd
|
1
|
295
|
entity issue521 is
end entity;
architecture test of issue521 is
signal i : natural;
signal j : natural;
begin
p1: process is
begin
i <= i + 1;
wait for 0 ns;
end process;
p2: process (i) is
begin
j <= i;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue8.vhd
|
5
|
435
|
package pack is
constant results : bit_vector(1 downto 0):="11";
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity issue8 is
end entity;
architecture test of issue8 is
signal bv : bit_vector(1 downto 0);
begin
bv <= results;
process is
begin
wait for 1 ns;
assert bv = "11";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/simp/issue194.vhd
|
5
|
547
|
package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_timer_v2_0/hdl/src/vhdl/mux_onehot_f.vhd
|
3
|
12555
|
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0_2;
--use proc_common_v4_0_2.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
|
gpl-3.0
|
pleonex/Efponga
|
Pong/escenario.vhd
|
1
|
6726
|
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.NUMERIC_STD.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY escenario IS
PORT (
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Controles del juego
btn_up1 : IN STD_LOGIC;
btn_down1 : IN STD_LOGIC;
btn_up2 : IN STD_LOGIC;
btn_down2 : IN STD_LOGIC;
-- Marcados de 7 segmentos
hex00 : OUT STD_LOGIC;
hex01 : OUT STD_LOGIC;
hex02 : OUT STD_LOGIC;
hex03 : OUT STD_LOGIC;
hex04 : OUT STD_LOGIC;
hex05 : OUT STD_LOGIC;
hex06 : OUT STD_LOGIC;
hex20 : OUT STD_LOGIC;
hex21 : OUT STD_LOGIC;
hex22 : OUT STD_LOGIC;
hex23 : OUT STD_LOGIC;
hex24 : OUT STD_LOGIC;
hex25 : OUT STD_LOGIC;
hex26 : OUT STD_LOGIC
);
END escenario;
ARCHITECTURE funcional OF escenario IS
-- Pelota de juego
COMPONENT bola
PORT(
-- Variables de dibujado
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Control de bola
bola_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rebote_xIzq : IN STD_LOGIC;
rebote_xDer : IN STD_LOGIC;
rebote_y : IN STD_LOGIC;
gol1 : OUT STD_LOGIC;
gol2 : OUT STD_LOGIC
);
END COMPONENT;
-- Pala de juego
COMPONENT pala
GENERIC (
DEFAULT_POS_X : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(0, 10)
);
PORT (
-- Puertos para dibujado
vert_sync : IN STD_LOGIC;
pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
pixel_column : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
Red : OUT STD_LOGIC;
Green : OUT STD_LOGIC;
Blue : OUT STD_LOGIC;
-- Botones de control
btn_up : IN STD_LOGIC;
btn_down : IN STD_LOGIC;
-- Control de rebotes de bola
bola_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
bola_size_y : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rebote : OUT STD_LOGIC
);
END COMPONENT;
-- Marcador
COMPONENT marcador
PORT (
numero : IN UNSIGNED(3 DOWNTO 0);
hex0 : OUT STD_LOGIC;
hex1 : OUT STD_LOGIC;
hex2 : OUT STD_LOGIC;
hex3 : OUT STD_LOGIC;
hex4 : OUT STD_LOGIC;
hex5 : OUT STD_LOGIC;
hex6 : OUT STD_LOGIC
);
END COMPONENT;
-- Constantes de la pantalla
CONSTANT PANTALLA_ANCHO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(640, 10);
CONSTANT PANTALLA_ALTO : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(480, 10);
-- Variables
SIGNAL red_bola, red_palaIzq, red_palaDer : STD_LOGIC;
SIGNAL green_bola, green_palaIzq, green_palaDer : STD_LOGIC;
SIGNAL blue_bola, blue_palaIzq, blue_palaDer : STD_LOGIC;
SIGNAL bola_x, bola_y, bola_size_x, bola_size_y : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rebote_palaIzq, rebote_palaDer : STD_LOGIC;
SIGNAL contador1 : UNSIGNED(3 DOWNTO 0);
SIGNAL contador2 : UNSIGNED(3 DOWNTO 0);
SIGNAL gol1 : STD_LOGIC;
SIGNAL gol2 : STD_LOGIC;
BEGIN
Red <= red_bola or red_palaIzq or red_palaDer;
Green <= green_bola or green_palaIzq or green_palaDer;
Blue <= blue_bola or blue_palaIzq or blue_palaDer;
PROCESS (vert_sync)
BEGIN
IF (vert_sync'event AND vert_sync = '1') THEN
-- FIX: Arreglar fallo de doble detección de borde
contador1 <= contador1 + gol1;
contador2 <= contador2 + gol2;
END IF;
END PROCESS;
PELOTA: bola
PORT MAP (
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_column,
Red => red_bola,
Green => green_bola,
Blue => blue_bola,
bola_x => bola_x,
bola_y => bola_y,
bola_size_x => bola_size_x,
bola_size_y => bola_size_y,
rebote_xIzq => rebote_palaDer,
rebote_xDer => rebote_palaIzq,
rebote_y => '0',
gol1 => gol1,
gol2 => gol2
);
PALA_IZQ: pala
GENERIC MAP (
DEFAULT_POS_X => CONV_STD_LOGIC_VECTOR(10, 10)
)
PORT MAP (
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_column,
Red => red_palaIzq,
Green => green_palaIzq,
Blue => blue_palaIzq,
btn_up => btn_up1,
btn_down => btn_down1,
bola_x => bola_x,
bola_y => bola_y,
bola_size_x => bola_size_x,
bola_size_y => bola_size_y,
rebote => rebote_palaIzq
);
PALA_DER: pala
GENERIC MAP (
DEFAULT_POS_X => PANTALLA_ANCHO - CONV_STD_LOGIC_VECTOR(10, 10)
)
PORT MAP (
vert_sync => vert_sync,
pixel_row => pixel_row,
pixel_column => pixel_column,
Red => red_palaDer,
Green => green_palaDer,
Blue => blue_palaDer,
btn_up => btn_up2,
btn_down => btn_down2,
bola_x => bola_x,
bola_y => bola_y,
bola_size_x => bola_size_x,
bola_size_y => bola_size_y,
rebote => rebote_palaDer
);
MARCADOR1: marcador
PORT MAP (
numero => contador1,
hex0 => hex00,
hex1 => hex01,
hex2 => hex02,
hex3 => hex03,
hex4 => hex04,
hex5 => hex05,
hex6 => hex06
);
MARCADOR2: marcador
PORT MAP (
numero => contador2,
hex0 => hex20,
hex1 => hex21,
hex2 => hex22,
hex3 => hex23,
hex4 => hex24,
hex5 => hex25,
hex6 => hex26
);
END funcional;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_ms_strb_set.vhd
|
18
|
62690
|
-------------------------------------------------------------------------------
-- axi_datamover_ms_strb_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ms_strb_set.vhd
--
-- Description:
-- This module implements a function to detect the most significant strobe
-- bit asserted and outputs the index value of that strobe bit. It can only
-- be used in applications where the asserted strobe bits are contiguous and
-- always asserted from LS to MS bit positions,
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ms_strb_set is
generic (
C_STRB_WIDTH : Integer := 8;
-- Sets the width of the input strobe port
C_INDEX_WIDTH : Integer := 3
-- Sets the width of the ms_strb_index output port
-- Should be log2(C_STRB_WIDTH)
);
port (
-- Input strobe value ------------------------------------------------
strbs_in : in std_logic_vector(C_STRB_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Specifies the index of the most significant strobe set ------------
ms_strb_index : out std_logic_vector(C_INDEX_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Invalid strobe input Indcation ------------------------------------
strb_error : Out std_logic --
-- Indicates an error with the strobe input, either a hole in the --
-- asserted strobes or not asserted from LS bits upwards. --
----------------------------------------------------------------------
);
end entity axi_datamover_ms_strb_set;
architecture implementation of axi_datamover_ms_strb_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_2
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 2-bit wide strobe value.
--
-------------------------------------------------------------------
function get_ms_index_2 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(1 downto 0);
begin
var_strb_value := input_strobe(1 downto 0);
case var_strb_value is
when "01" =>
var_ms_strb_index := 0;
when "11" | "10" =>
var_ms_strb_index := 1;
when others =>
var_ms_strb_index := 2;
end case;
Return (var_ms_strb_index);
end function get_ms_index_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_4
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 4-bit wide strobe value.
--
-------------------------------------------------------------------
function get_ms_index_4 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(3 downto 0);
begin
var_strb_value := input_strobe(3 downto 0);
case var_strb_value is
when "0001" =>
var_ms_strb_index := 0;
when "0011" | "0010" =>
var_ms_strb_index := 1;
when "0111" | "0110" | "0100" =>
var_ms_strb_index := 2;
when "1111" | "1110" | "1100" | "1000"=>
var_ms_strb_index := 3;
when others =>
var_ms_strb_index := 4;
end case;
Return (var_ms_strb_index);
end function get_ms_index_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_8
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 8-bit wide strobe value.
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_8 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(7 downto 0);
begin
var_strb_value := input_strobe(7 downto 0);
case var_strb_value is
when "00000001" =>
var_ms_strb_index := 0;
when "00000010" =>
var_ms_strb_index := 1;
when "00000100" =>
var_ms_strb_index := 2;
when "00001000" =>
var_ms_strb_index := 3;
when "00010000" =>
var_ms_strb_index := 4;
when "00100000" =>
var_ms_strb_index := 5;
when "01000000" =>
var_ms_strb_index := 6;
when "10000000" =>
var_ms_strb_index := 7;
when others =>
var_ms_strb_index := 8;
end case;
Return (var_ms_strb_index);
end function get_ms_index_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_16
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 16-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_16 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(15 downto 0);
begin
var_strb_value := input_strobe(15 downto 0);
case var_strb_value is
when "0000000000000001" =>
var_ms_strb_index := 0;
when "0000000000000010" =>
var_ms_strb_index := 1;
when "0000000000000100" =>
var_ms_strb_index := 2;
when "0000000000001000" =>
var_ms_strb_index := 3;
when "0000000000010000" =>
var_ms_strb_index := 4;
when "0000000000100000" =>
var_ms_strb_index := 5;
when "0000000001000000" =>
var_ms_strb_index := 6;
when "0000000010000000" =>
var_ms_strb_index := 7;
when "0000000100000000" =>
var_ms_strb_index := 8;
when "0000001000000000" =>
var_ms_strb_index := 9;
when "0000010000000000" =>
var_ms_strb_index := 10;
when "0000100000000000" =>
var_ms_strb_index := 11;
when "0001000000000000" =>
var_ms_strb_index := 12;
when "0010000000000000" =>
var_ms_strb_index := 13;
when "0100000000000000" =>
var_ms_strb_index := 14;
when "1000000000000000" =>
var_ms_strb_index := 15;
when others =>
var_ms_strb_index := 16;
end case;
Return (var_ms_strb_index);
end function get_ms_index_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_32
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 32-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_32 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(31 downto 0);
begin
var_strb_value := input_strobe(31 downto 0);
case var_strb_value is
when "00000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "00000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "00000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "00000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "00000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "00000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "00000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "00000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "00000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "00000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "00000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "00000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "00000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "00000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "00000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "00000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "00000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "00000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "00000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "00000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "00000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "00000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "00000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "00000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "00000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "00000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "00000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "00001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "00010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "00100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "01000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "10000000000000000000000000000000" =>
var_ms_strb_index := 31;
when others =>
var_ms_strb_index := 32;
end case;
Return (var_ms_strb_index);
end function get_ms_index_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_64
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 64-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_64 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(63 downto 0);
begin
var_strb_value := input_strobe(63 downto 0);
case var_strb_value is
when "0000000000000000000000000000000000000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "0000000000000000000000000000000000000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "0000000000000000000000000000000000000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "0000000000000000000000000000000000000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "0000000000000000000000000000000000000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "0000000000000000000000000000000000000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "0000000000000000000000000000000000000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "0000000000000000000000000000000000000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "0000000000000000000000000000000000000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "0000000000000000000000000000000000000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "0000000000000000000000000000000000000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "0000000000000000000000000000000000000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "0000000000000000000000000000000000000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "0000000000000000000000000000000000000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "0000000000000000000000000000000000000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "0000000000000000000000000000000000000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "0000000000000000000000000000000000000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "0000000000000000000000000000000000000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "0000000000000000000000000000000000000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "0000000000000000000000000000000000000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "0000000000000000000000000000000000000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "0000000000000000000000000000000000000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "0000000000000000000000000000000000000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "0000000000000000000000000000000000000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "0000000000000000000000000000000000000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "0000000000000000000000000000000000000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "0000000000000000000000000000000000000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "0000000000000000000000000000000000001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "0000000000000000000000000000000000010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "0000000000000000000000000000000000100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "0000000000000000000000000000000001000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "0000000000000000000000000000000010000000000000000000000000000000" =>
var_ms_strb_index := 31;
when "0000000000000000000000000000000100000000000000000000000000000000" =>
var_ms_strb_index := 32;
when "0000000000000000000000000000001000000000000000000000000000000000" =>
var_ms_strb_index := 33;
when "0000000000000000000000000000010000000000000000000000000000000000" =>
var_ms_strb_index := 34;
when "0000000000000000000000000000100000000000000000000000000000000000" =>
var_ms_strb_index := 35;
when "0000000000000000000000000001000000000000000000000000000000000000" =>
var_ms_strb_index := 36;
when "0000000000000000000000000010000000000000000000000000000000000000" =>
var_ms_strb_index := 37;
when "0000000000000000000000000100000000000000000000000000000000000000" =>
var_ms_strb_index := 38;
when "0000000000000000000000001000000000000000000000000000000000000000" =>
var_ms_strb_index := 39;
when "0000000000000000000000010000000000000000000000000000000000000000" =>
var_ms_strb_index := 40;
when "0000000000000000000000100000000000000000000000000000000000000000" =>
var_ms_strb_index := 41;
when "0000000000000000000001000000000000000000000000000000000000000000" =>
var_ms_strb_index := 42;
when "0000000000000000000010000000000000000000000000000000000000000000" =>
var_ms_strb_index := 43;
when "0000000000000000000100000000000000000000000000000000000000000000" =>
var_ms_strb_index := 44;
when "0000000000000000001000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 45;
when "0000000000000000010000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 46;
when "0000000000000000100000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 47;
when "0000000000000001000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 48;
when "0000000000000010000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 49;
when "0000000000000100000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 50;
when "0000000000001000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 51;
when "0000000000010000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 52;
when "0000000000100000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 53;
when "0000000001000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 54;
when "0000000010000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 55;
when "0000000100000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 56;
when "0000001000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 57;
when "0000010000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 58;
when "0000100000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 59;
when "0001000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 60;
when "0010000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 61;
when "0100000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 62;
when "1000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 63;
when others =>
var_ms_strb_index := 64;
end case;
Return (var_ms_strb_index);
end function get_ms_index_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_128
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 64-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_128 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(127 downto 0);
begin
var_strb_value := input_strobe(127 downto 0);
case var_strb_value is
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000" =>
var_ms_strb_index := 31;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000" =>
var_ms_strb_index := 32;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000" =>
var_ms_strb_index := 33;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000" =>
var_ms_strb_index := 34;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000" =>
var_ms_strb_index := 35;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000" =>
var_ms_strb_index := 36;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000" =>
var_ms_strb_index := 37;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000" =>
var_ms_strb_index := 38;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000" =>
var_ms_strb_index := 39;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000" =>
var_ms_strb_index := 40;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000" =>
var_ms_strb_index := 41;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000" =>
var_ms_strb_index := 42;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000" =>
var_ms_strb_index := 43;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000" =>
var_ms_strb_index := 44;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 45;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 46;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 47;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 48;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 49;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 50;
when "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 51;
when "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 52;
when "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 53;
when "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 54;
when "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 55;
when "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 56;
when "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 57;
when "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 58;
when "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 59;
when "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 60;
when "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 61;
when "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 62;
when "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 63;
when "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 64;
when "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 65;
when "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 66;
when "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 67;
when "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 68;
when "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 69;
when "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 70;
when "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 71;
when "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 72;
when "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 73;
when "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 74;
when "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 75;
when "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 76;
when "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 77;
when "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 78;
when "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 79;
when "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 80;
when "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 81;
when "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 82;
when "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 83;
when "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 84;
when "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 85;
when "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 86;
when "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 87;
when "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 88;
when "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 89;
when "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 90;
when "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 91;
when "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 92;
when "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 93;
when "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 94;
when "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 95;
when "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 96;
when "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 97;
when "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 98;
when "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 99;
when "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 100;
when "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 101;
when "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 102;
when "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 103;
when "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 104;
when "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 105;
when "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 106;
when "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 107;
when "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 108;
when "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 109;
when "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 110;
when "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 111;
when "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 112;
when "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 113;
when "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 114;
when "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 115;
when "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 116;
when "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 117;
when "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 118;
when "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 119;
when "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 120;
when "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 121;
when "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 122;
when "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 123;
when "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 124;
when "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 125;
when "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 126;
when "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 127;
when others =>
var_ms_strb_index := 128;
end case;
Return (var_ms_strb_index);
end function get_ms_index_128;
-- Constants
Constant ERROR_INDEX : natural := C_STRB_WIDTH;
Constant TEMP_NAT_MAX : natural := 255; -- allows for a 0 to 255 strobe index value
Constant TEMP_UN_WIDTH : natural := 8; -- 8 bits allows for a 0 to 255 index value
-- Signals
signal sig_input_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_ms_asserted_index_un : unsigned(C_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_error : std_logic := '0';
signal sig_temp_ms_index_un : unsigned(TEMP_UN_WIDTH-1 downto 0) := (others => '0');
signal sig_temp_ms_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin --(architecture implementation)
-- Assign the ms asserted strobe value
ms_strb_index <= STD_LOGIC_VECTOR(sig_ms_asserted_index_un);
-- Assign the input strobe
sig_input_stbs <= strbs_in ; -- assign input strobes
-- Assign the strobe eror output
strb_error <= sig_strb_error ; -- assign the strobe error output
-- Rip the valid index bits
sig_ms_asserted_index_un <= sig_temp_ms_index_un(C_INDEX_WIDTH-1 downto 0);
-- Assert the Strobe Error output if an out of range index is returned
sig_temp_ms_index_nat <= TO_INTEGER(sig_ms_asserted_index_un) ;
sig_strb_error <= '1'
When (sig_temp_ms_index_nat >= ERROR_INDEX)
else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_temp_ms_index_un <= TO_UNSIGNED( 0, TEMP_UN_WIDTH);
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin
lsig_ms_asserted_index_nat <= get_ms_index_2(sig_input_stbs);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 4-bit strobe width case.
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin
lsig_ms_asserted_index_nat <= get_ms_index_4(sig_input_stbs);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 8-bit strobe width case.
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_8(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_16(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 32-bit strobe width case.
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_32(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 64-bit strobe width case.
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_64(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 128-bit strobe width case.
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_128(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_128BIT_CASE;
end implementation;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_ms_strb_set.vhd
|
18
|
62690
|
-------------------------------------------------------------------------------
-- axi_datamover_ms_strb_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_ms_strb_set.vhd
--
-- Description:
-- This module implements a function to detect the most significant strobe
-- bit asserted and outputs the index value of that strobe bit. It can only
-- be used in applications where the asserted strobe bits are contiguous and
-- always asserted from LS to MS bit positions,
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_ms_strb_set is
generic (
C_STRB_WIDTH : Integer := 8;
-- Sets the width of the input strobe port
C_INDEX_WIDTH : Integer := 3
-- Sets the width of the ms_strb_index output port
-- Should be log2(C_STRB_WIDTH)
);
port (
-- Input strobe value ------------------------------------------------
strbs_in : in std_logic_vector(C_STRB_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Specifies the index of the most significant strobe set ------------
ms_strb_index : out std_logic_vector(C_INDEX_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Invalid strobe input Indcation ------------------------------------
strb_error : Out std_logic --
-- Indicates an error with the strobe input, either a hole in the --
-- asserted strobes or not asserted from LS bits upwards. --
----------------------------------------------------------------------
);
end entity axi_datamover_ms_strb_set;
architecture implementation of axi_datamover_ms_strb_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_2
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 2-bit wide strobe value.
--
-------------------------------------------------------------------
function get_ms_index_2 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(1 downto 0);
begin
var_strb_value := input_strobe(1 downto 0);
case var_strb_value is
when "01" =>
var_ms_strb_index := 0;
when "11" | "10" =>
var_ms_strb_index := 1;
when others =>
var_ms_strb_index := 2;
end case;
Return (var_ms_strb_index);
end function get_ms_index_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_4
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 4-bit wide strobe value.
--
-------------------------------------------------------------------
function get_ms_index_4 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(3 downto 0);
begin
var_strb_value := input_strobe(3 downto 0);
case var_strb_value is
when "0001" =>
var_ms_strb_index := 0;
when "0011" | "0010" =>
var_ms_strb_index := 1;
when "0111" | "0110" | "0100" =>
var_ms_strb_index := 2;
when "1111" | "1110" | "1100" | "1000"=>
var_ms_strb_index := 3;
when others =>
var_ms_strb_index := 4;
end case;
Return (var_ms_strb_index);
end function get_ms_index_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_8
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 8-bit wide strobe value.
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_8 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(7 downto 0);
begin
var_strb_value := input_strobe(7 downto 0);
case var_strb_value is
when "00000001" =>
var_ms_strb_index := 0;
when "00000010" =>
var_ms_strb_index := 1;
when "00000100" =>
var_ms_strb_index := 2;
when "00001000" =>
var_ms_strb_index := 3;
when "00010000" =>
var_ms_strb_index := 4;
when "00100000" =>
var_ms_strb_index := 5;
when "01000000" =>
var_ms_strb_index := 6;
when "10000000" =>
var_ms_strb_index := 7;
when others =>
var_ms_strb_index := 8;
end case;
Return (var_ms_strb_index);
end function get_ms_index_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_16
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 16-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_16 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(15 downto 0);
begin
var_strb_value := input_strobe(15 downto 0);
case var_strb_value is
when "0000000000000001" =>
var_ms_strb_index := 0;
when "0000000000000010" =>
var_ms_strb_index := 1;
when "0000000000000100" =>
var_ms_strb_index := 2;
when "0000000000001000" =>
var_ms_strb_index := 3;
when "0000000000010000" =>
var_ms_strb_index := 4;
when "0000000000100000" =>
var_ms_strb_index := 5;
when "0000000001000000" =>
var_ms_strb_index := 6;
when "0000000010000000" =>
var_ms_strb_index := 7;
when "0000000100000000" =>
var_ms_strb_index := 8;
when "0000001000000000" =>
var_ms_strb_index := 9;
when "0000010000000000" =>
var_ms_strb_index := 10;
when "0000100000000000" =>
var_ms_strb_index := 11;
when "0001000000000000" =>
var_ms_strb_index := 12;
when "0010000000000000" =>
var_ms_strb_index := 13;
when "0100000000000000" =>
var_ms_strb_index := 14;
when "1000000000000000" =>
var_ms_strb_index := 15;
when others =>
var_ms_strb_index := 16;
end case;
Return (var_ms_strb_index);
end function get_ms_index_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_32
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 32-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_32 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(31 downto 0);
begin
var_strb_value := input_strobe(31 downto 0);
case var_strb_value is
when "00000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "00000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "00000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "00000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "00000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "00000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "00000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "00000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "00000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "00000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "00000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "00000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "00000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "00000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "00000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "00000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "00000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "00000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "00000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "00000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "00000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "00000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "00000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "00000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "00000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "00000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "00000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "00001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "00010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "00100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "01000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "10000000000000000000000000000000" =>
var_ms_strb_index := 31;
when others =>
var_ms_strb_index := 32;
end case;
Return (var_ms_strb_index);
end function get_ms_index_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_64
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 64-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_64 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(63 downto 0);
begin
var_strb_value := input_strobe(63 downto 0);
case var_strb_value is
when "0000000000000000000000000000000000000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "0000000000000000000000000000000000000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "0000000000000000000000000000000000000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "0000000000000000000000000000000000000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "0000000000000000000000000000000000000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "0000000000000000000000000000000000000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "0000000000000000000000000000000000000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "0000000000000000000000000000000000000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "0000000000000000000000000000000000000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "0000000000000000000000000000000000000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "0000000000000000000000000000000000000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "0000000000000000000000000000000000000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "0000000000000000000000000000000000000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "0000000000000000000000000000000000000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "0000000000000000000000000000000000000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "0000000000000000000000000000000000000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "0000000000000000000000000000000000000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "0000000000000000000000000000000000000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "0000000000000000000000000000000000000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "0000000000000000000000000000000000000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "0000000000000000000000000000000000000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "0000000000000000000000000000000000000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "0000000000000000000000000000000000000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "0000000000000000000000000000000000000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "0000000000000000000000000000000000000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "0000000000000000000000000000000000000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "0000000000000000000000000000000000000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "0000000000000000000000000000000000001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "0000000000000000000000000000000000010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "0000000000000000000000000000000000100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "0000000000000000000000000000000001000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "0000000000000000000000000000000010000000000000000000000000000000" =>
var_ms_strb_index := 31;
when "0000000000000000000000000000000100000000000000000000000000000000" =>
var_ms_strb_index := 32;
when "0000000000000000000000000000001000000000000000000000000000000000" =>
var_ms_strb_index := 33;
when "0000000000000000000000000000010000000000000000000000000000000000" =>
var_ms_strb_index := 34;
when "0000000000000000000000000000100000000000000000000000000000000000" =>
var_ms_strb_index := 35;
when "0000000000000000000000000001000000000000000000000000000000000000" =>
var_ms_strb_index := 36;
when "0000000000000000000000000010000000000000000000000000000000000000" =>
var_ms_strb_index := 37;
when "0000000000000000000000000100000000000000000000000000000000000000" =>
var_ms_strb_index := 38;
when "0000000000000000000000001000000000000000000000000000000000000000" =>
var_ms_strb_index := 39;
when "0000000000000000000000010000000000000000000000000000000000000000" =>
var_ms_strb_index := 40;
when "0000000000000000000000100000000000000000000000000000000000000000" =>
var_ms_strb_index := 41;
when "0000000000000000000001000000000000000000000000000000000000000000" =>
var_ms_strb_index := 42;
when "0000000000000000000010000000000000000000000000000000000000000000" =>
var_ms_strb_index := 43;
when "0000000000000000000100000000000000000000000000000000000000000000" =>
var_ms_strb_index := 44;
when "0000000000000000001000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 45;
when "0000000000000000010000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 46;
when "0000000000000000100000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 47;
when "0000000000000001000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 48;
when "0000000000000010000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 49;
when "0000000000000100000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 50;
when "0000000000001000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 51;
when "0000000000010000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 52;
when "0000000000100000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 53;
when "0000000001000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 54;
when "0000000010000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 55;
when "0000000100000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 56;
when "0000001000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 57;
when "0000010000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 58;
when "0000100000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 59;
when "0001000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 60;
when "0010000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 61;
when "0100000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 62;
when "1000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 63;
when others =>
var_ms_strb_index := 64;
end case;
Return (var_ms_strb_index);
end function get_ms_index_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_ms_index_128
--
-- Function Description:
-- Returns the index of the most significant strobe set in a
-- 64-bit wide strobe value.
--
--
-- Note that this function expects an input vector marking the
-- assertion/deassertion boundaries, not the actual strobe vector.
--
-------------------------------------------------------------------
function get_ms_index_128 (input_strobe : std_logic_vector) return natural is
Variable var_ms_strb_index : natural := 0;
Variable var_strb_value : std_logic_vector(127 downto 0);
begin
var_strb_value := input_strobe(127 downto 0);
case var_strb_value is
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001" =>
var_ms_strb_index := 0;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010" =>
var_ms_strb_index := 1;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100" =>
var_ms_strb_index := 2;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000" =>
var_ms_strb_index := 3;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000" =>
var_ms_strb_index := 4;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000" =>
var_ms_strb_index := 5;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000" =>
var_ms_strb_index := 6;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000" =>
var_ms_strb_index := 7;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" =>
var_ms_strb_index := 8;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000" =>
var_ms_strb_index := 9;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000" =>
var_ms_strb_index := 10;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000" =>
var_ms_strb_index := 11;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000" =>
var_ms_strb_index := 12;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000" =>
var_ms_strb_index := 13;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000" =>
var_ms_strb_index := 14;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000" =>
var_ms_strb_index := 15;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000" =>
var_ms_strb_index := 16;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000" =>
var_ms_strb_index := 17;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000" =>
var_ms_strb_index := 18;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000" =>
var_ms_strb_index := 19;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000" =>
var_ms_strb_index := 20;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000" =>
var_ms_strb_index := 21;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000" =>
var_ms_strb_index := 22;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000" =>
var_ms_strb_index := 23;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000" =>
var_ms_strb_index := 24;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000" =>
var_ms_strb_index := 25;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000" =>
var_ms_strb_index := 26;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000" =>
var_ms_strb_index := 27;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000" =>
var_ms_strb_index := 28;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000" =>
var_ms_strb_index := 29;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000" =>
var_ms_strb_index := 30;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000" =>
var_ms_strb_index := 31;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000" =>
var_ms_strb_index := 32;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000" =>
var_ms_strb_index := 33;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000" =>
var_ms_strb_index := 34;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000" =>
var_ms_strb_index := 35;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000" =>
var_ms_strb_index := 36;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000" =>
var_ms_strb_index := 37;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000" =>
var_ms_strb_index := 38;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000" =>
var_ms_strb_index := 39;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000" =>
var_ms_strb_index := 40;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000" =>
var_ms_strb_index := 41;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000" =>
var_ms_strb_index := 42;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000" =>
var_ms_strb_index := 43;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000" =>
var_ms_strb_index := 44;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 45;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 46;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 47;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 48;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 49;
when "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 50;
when "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 51;
when "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 52;
when "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 53;
when "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 54;
when "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 55;
when "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 56;
when "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 57;
when "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 58;
when "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 59;
when "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 60;
when "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 61;
when "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 62;
when "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 63;
when "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 64;
when "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 65;
when "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 66;
when "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 67;
when "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 68;
when "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 69;
when "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 70;
when "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 71;
when "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 72;
when "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 73;
when "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 74;
when "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 75;
when "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 76;
when "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 77;
when "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 78;
when "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 79;
when "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 80;
when "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 81;
when "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 82;
when "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 83;
when "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 84;
when "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 85;
when "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 86;
when "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 87;
when "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 88;
when "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 89;
when "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 90;
when "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 91;
when "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 92;
when "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 93;
when "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 94;
when "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 95;
when "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 96;
when "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 97;
when "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 98;
when "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 99;
when "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 100;
when "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 101;
when "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 102;
when "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 103;
when "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 104;
when "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 105;
when "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 106;
when "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 107;
when "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 108;
when "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 109;
when "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 110;
when "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 111;
when "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 112;
when "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 113;
when "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 114;
when "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 115;
when "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 116;
when "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 117;
when "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 118;
when "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 119;
when "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 120;
when "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 121;
when "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 122;
when "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 123;
when "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 124;
when "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 125;
when "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 126;
when "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" =>
var_ms_strb_index := 127;
when others =>
var_ms_strb_index := 128;
end case;
Return (var_ms_strb_index);
end function get_ms_index_128;
-- Constants
Constant ERROR_INDEX : natural := C_STRB_WIDTH;
Constant TEMP_NAT_MAX : natural := 255; -- allows for a 0 to 255 strobe index value
Constant TEMP_UN_WIDTH : natural := 8; -- 8 bits allows for a 0 to 255 index value
-- Signals
signal sig_input_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_ms_asserted_index_un : unsigned(C_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_error : std_logic := '0';
signal sig_temp_ms_index_un : unsigned(TEMP_UN_WIDTH-1 downto 0) := (others => '0');
signal sig_temp_ms_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin --(architecture implementation)
-- Assign the ms asserted strobe value
ms_strb_index <= STD_LOGIC_VECTOR(sig_ms_asserted_index_un);
-- Assign the input strobe
sig_input_stbs <= strbs_in ; -- assign input strobes
-- Assign the strobe eror output
strb_error <= sig_strb_error ; -- assign the strobe error output
-- Rip the valid index bits
sig_ms_asserted_index_un <= sig_temp_ms_index_un(C_INDEX_WIDTH-1 downto 0);
-- Assert the Strobe Error output if an out of range index is returned
sig_temp_ms_index_nat <= TO_INTEGER(sig_ms_asserted_index_un) ;
sig_strb_error <= '1'
When (sig_temp_ms_index_nat >= ERROR_INDEX)
else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_temp_ms_index_un <= TO_UNSIGNED( 0, TEMP_UN_WIDTH);
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin
lsig_ms_asserted_index_nat <= get_ms_index_2(sig_input_stbs);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 4-bit strobe width case.
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
begin
lsig_ms_asserted_index_nat <= get_ms_index_4(sig_input_stbs);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 8-bit strobe width case.
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_8(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_16(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 32-bit strobe width case.
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_32(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 64-bit strobe width case.
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_64(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the MS asserted strobe index for the
-- 128-bit strobe width case.
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_ms_asserted_index_nat : natural range 0 to TEMP_NAT_MAX := 0;
Signal lsig_strb_last_assert_vect : std_logic_vector(C_STRB_WIDTH downto 0);
Signal lsig_strb_test_vect : std_logic_vector(C_STRB_WIDTH downto 0);
begin
-- Create a strobe vector with the most significant bit zeroed.
lsig_strb_test_vect <= '0' & sig_input_stbs;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_ASSERT_BNDRY_CHK
--
-- For Generate Description:
-- Find the assertion/deassertion boundaries in the input
-- Strobe vector in the least to most significant index
-- direction.
--
--
------------------------------------------------------------
GEN_ASSERT_BNDRY_CHK : for strb_index in 1 to C_STRB_WIDTH generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FIND_DEASSERTION
--
-- Process Description:
-- Detects the case when two adjoining strobe bits have an
-- assertion transition from asserted to deasserted moving
-- from lower to higher bit ordering.
--
-------------------------------------------------------------
IMP_FIND_DEASSERTION : process (lsig_strb_test_vect)
begin
if ((lsig_strb_test_vect(strb_index-1) = '1') and
(lsig_strb_test_vect(strb_index) = '0')) then
lsig_strb_last_assert_vect(strb_index-1) <= '1';
else
lsig_strb_last_assert_vect(strb_index-1) <= '0';
end if;
end process IMP_FIND_DEASSERTION;
end generate GEN_ASSERT_BNDRY_CHK;
lsig_ms_asserted_index_nat <= get_ms_index_128(lsig_strb_last_assert_vect);
sig_temp_ms_index_un <= TO_UNSIGNED(lsig_ms_asserted_index_nat, TEMP_UN_WIDTH);
end generate GEN_128BIT_CASE;
end implementation;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_0/sim/design_1_axi_bram_ctrl_0_0.vhd
|
2
|
15632
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_7;
USE axi_bram_ctrl_v4_0_7.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
|
gpl-3.0
|
nickg/nvc
|
test/regress/elab3.vhd
|
5
|
824
|
entity sub is
end entity;
architecture test of sub is
signal p : integer;
begin
process is
begin
wait for 2 ns;
report p'instance_name;
report p'path_name;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab3 is
end entity;
architecture test of elab3 is
signal x : integer;
begin
s: entity work.sub;
b: block is
signal y : integer;
begin
process is
begin
wait for 1 ns;
report y'instance_name;
report y'path_name;
wait;
end process;
end block;
process is
begin
report x'instance_name;
report x'path_name;
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd
|
44
|
7144
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
gpl-3.0
|
nickg/nvc
|
lib/std.19/textio.vhdl
|
1
|
8222
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Library : This package shall be compiled into a library
-- : symbolically named std.
-- :
-- Developers: IEEE P1076 Working Group
-- :
-- Purpose : This packages defines subprograms for file I/O
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
package TEXTIO is
-- Type definitions for text I/O:
type LINE is access STRING; -- A LINE is a pointer to a STRING value.
-- The predefined operations for this type are as follows:
-- function"=" (anonymous, anonymous: LINE) return BOOLEAN;
-- function"/=" (anonymous, anonymous: LINE) return BOOLEAN;
-- procedure DEALLOCATE (P: inout LINE);
type LINE_VECTOR is array(NATURAL range <>) of LINE;
-- The predefined operations for this type are as follows:
-- function "="(anonymous, anonymous: LINE_VECTOR) return BOOLEAN;
-- function "/="(anonymous, anonymous: LINE_VECTOR) return BOOLEAN;
-- function "&"(anonymous: LINE_VECTOR; anonymous: LINE_VECTOR) return LINE_VECTOR;
-- function "&"(anonymous: LINE_VECTOR; anonymous: LINE) return LINE_VECTOR;
-- function "&"(anonymous: LINE; anonymous: LINE_VECTOR) return LINE_VECTOR;
-- function "&"(anonymous: LINE; anonymous: LINE) return LINE_VECTOR;
type TEXT is file of STRING; -- A file of variable-length ASCII records.
-- The predefined operations for this type are as follows:
-- procedure FILE_OPEN (file F: TEXT; External_Name; in STRING; Open_Kind: in FILE_OPEN_KIND := READ_MODE);
-- procedure FILE_OPEN (Status: out FILE_OPEN_STATUS; file F: TEXT; External_Name: in STRING; Open_Kind: in FILE_OPEN_KIND := READ_MODE);
-- procedure FILE_REWIND (file F: FT);
-- procedure FILE_SEEK (file F: FT; Offset : INTEGER; Origin : FILE_ORIGIN_KIND := FILE_ORIGIN_BEGIN);
-- procedure FILE_TRUNCATE (file F: FT; Size : INTEGER; Origin : FILE_ORIGIN_KIND := FILE_ORIGIN_BEGIN);
-- function FILE_MODE (file F: FT) return FILE_OPEN_KIND;
-- function FILE_TELL (file F: FT; Origin : FILE_ORIGIN_KIND := FILE_ORIGIN_BEGIN) return INTEGER;
-- function FILE_SIZE (file F: FT) return INTEGER;
-- procedure FILE_CLOSE (file F: TEXT);
-- procedure READ (file F: TEXT; VALUE: out STRING);
-- procedure WRITE (file F: TEXT; VALUE: in STRING);
-- procedure FLUSH (file F: TEXT);
-- function ENDFILE (file F: TEXT) return BOOLEAN;
type SIDE is (RIGHT, LEFT); -- For justifying output data within fields.
-- The predefined operations for this type are as follows:
-- function "=" (anonymous, anonymous: SIDE) return BOOLEAN;
-- function "/=" (anonymous, anonymous: SIDE) return BOOLEAN;
-- function "<" (anonymous, anonymous: SIDE) return BOOLEAN;
-- function "<=" (anonymous, anonymous: SIDE) return BOOLEAN;
-- function ">" (anonymous, anonymous: SIDE) return BOOLEAN;
-- function ">=" (anonymous, anonymous: SIDE) return BOOLEAN;
-- function MINIMUM (L, R: SIDE) return SIDE;
-- function MAXIMUM (L, R: SIDE) return SIDE;
-- function TO_STRING (VALUE: SIDE) return STRING;
subtype WIDTH is NATURAL; -- For specifying widths of output fields.
function JUSTIFY (VALUE: STRING; JUSTIFIED: SIDE := RIGHT; FIELD: WIDTH := 0 ) return STRING;
-- Standard text files:
file INPUT: TEXT open READ_MODE is "STD_INPUT";
file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT";
-- Input routines for standard types:
procedure READLINE (file F: TEXT; L: inout LINE);
procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out BIT);
procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out BIT_VECTOR);
procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out CHARACTER);
procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out INTEGER);
procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out REAL);
procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STRING);
procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out TIME);
procedure SREAD (L: inout LINE; VALUE: out STRING; STRLEN: out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- Output routines for standard types:
procedure WRITELINE (file F: TEXT; L: inout LINE);
procedure TEE (file F: TEXT; L: inout LINE);
procedure WRITE (L: inout LINE; VALUE: in BIT; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in BOOLEAN; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in CHARACTER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in INTEGER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in REAL; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; DIGITS: in NATURAL:= 0);
procedure WRITE (L: inout LINE; VALUE: in REAL; FORMAT: in STRING);
procedure WRITE (L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in TIME; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; UNIT: in TIME:= ns);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package TEXTIO;
|
gpl-3.0
|
nickg/nvc
|
test/parse/range1.vhd
|
1
|
710
|
entity range1 is
end entity;
architecture test of range1 is
begin
p1: process is
variable x : character;
begin
for i in 1 to 3 loop -- OK
end loop;
for i in character'range loop -- OK
end loop;
for i in character loop -- OK
end loop;
for i in x'range loop -- Error
end loop;
for i in x loop -- Error
end loop;
for i in 4 loop -- Error
end loop;
for i in integer range 1 to 3 loop -- OK
end loop;
for i in x range 'a' to 'b' loop -- Error
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/real2.vhd
|
5
|
488
|
entity real2 is
end entity;
architecture test of real2 is
type real_vec is array (integer range <>) of real;
type real_rec is record
x, y : real;
end record;
begin
process is
variable a, b : real_vec(1 to 3);
variable r : real_rec;
begin
a := (1.0, 1.2, 3.4);
b := (0.9, 0.2, 4.1);
assert b < a;
r.x := 2.0;
r.y := 3.0;
assert r = (2.0, 3.0);
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/bounds/issue36.vhd
|
5
|
441
|
entity bounds18 is
generic (
W : integer range 1 to integer'high := 8
);
function func2(x : integer; w : natural) return integer is
begin
return x + w;
end func2;
pure function fA (
iA : integer range 0 to 2**W-1
) return integer is
begin
return func2(iA, W);
end function fA;
begin
assert (fA(0) = 0) report "should not assert" severity failure;
end entity bounds18;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue146.vhd
|
5
|
986
|
package A_NG is
type A_NG_TYPE is record
debug : integer;
end record;
procedure PROC_B(B_ARG:inout A_NG_TYPE; B_VAL:out integer);
end A_NG;
package body A_NG is
procedure PROC_A(A_ARG:inout A_NG_TYPE) is
begin
A_ARG.debug := A_ARG.debug + 1;
end procedure;
procedure PROC_B(B_ARG:inout A_NG_TYPE; B_VAL:out integer) is
procedure PROC_C(C_VAL:out integer) is
begin
PROC_A(B_ARG);
C_VAL := B_ARG.debug;
end procedure;
begin
PROC_C(B_VAL);
end procedure;
end A_NG;
-------------------------------------------------------------------------------
entity issue146 is
end entity;
use work.a_ng.all;
architecture test of issue146 is
begin
process is
variable a_arg : a_ng_type := ( debug => 4 );
variable c_val : integer;
begin
proc_b(a_arg, c_val);
assert c_val = 5;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/const1.vhd
|
5
|
474
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
lib/vital/timing_p.vhdl
|
7
|
65467
|
-------------------------------------------------------------------------------
-- Title : Standard VITAL TIMING Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, attributes, constants,
-- : functions and procedures for use in developing ASIC models.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- v95.1 | | 08/31/95 | #203 - Timing violations at time 0
-- #204 - Output mapping prior to glitch detection
-- v98.0 |TAG | 03/27/98 | Initial ballot draft 1998
-- | #IR225 - Negative Premptive Glitch
-- **Pkg_effected=VitalPathDelay,
-- VitalPathDelay01,VitalPathDelay01z.
-- #IR105 - Skew timing check needed
-- **Pkg_effected=NONE, New code added!!
-- #IR248 - Allows VPD to use a default timing
-- delay
-- **Pkg_effected=VitalPathDelay,
-- VitalPathDelay01,VitalPathDelay01z,
-- #IR250 - Corrects fastpath condition in VPD
-- **Pkg_effected=VitalPathDelay01,
-- VitalPathDelay01z,
-- #IR252 - Corrects cancelled timing check call if
-- condition expires.
-- **Pkg_effected=VitalSetupHoldCheck,
-- VitalRecoveryRemovalCheck.
-- #IR105 - Skew timing check
-- **Pkg_effected=NONE, New code added
-- v98.1 | jdc | 03/25/99 | Changed UseDefaultDelay to IgnoreDefaultDelay
-- and set default to FALSE in VitalPathDelay()
-- v00.7 | dbb | 07/18/00 | Removed "maximum" from VitalPeriodPulse()
-- comments
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
PACKAGE VITAL_Timing IS
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME;
TYPE VitalDelayType01Z IS ARRAY (VitalTransitionType RANGE tr01 to trz0)
OF TIME;
TYPE VitalDelayType01ZX IS ARRAY (VitalTransitionType RANGE tr01 to trzx)
OF TIME;
TYPE VitalDelayArrayType IS ARRAY (NATURAL RANGE <>) OF VitalDelayType;
TYPE VitalDelayArrayType01 IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01;
TYPE VitalDelayArrayType01Z IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01Z;
TYPE VitalDelayArrayType01ZX IS ARRAY (NATURAL RANGE <>) OF VitalDelayType01ZX;
-- ----------------------------------------------------------------------
-- **********************************************************************
-- ----------------------------------------------------------------------
CONSTANT VitalZeroDelay : VitalDelayType := 0 ns;
CONSTANT VitalZeroDelay01 : VitalDelayType01 := ( 0 ns, 0 ns );
CONSTANT VitalZeroDelay01Z : VitalDelayType01Z := ( OTHERS => 0 ns );
CONSTANT VitalZeroDelay01ZX : VitalDelayType01ZX := ( OTHERS => 0 ns );
---------------------------------------------------------------------------
-- examples of usage:
---------------------------------------------------------------------------
-- tpd_CLK_Q : VitalDelayType := 5 ns;
-- tpd_CLK_Q : VitalDelayType01 := (tr01 => 2 ns, tr10 => 3 ns);
-- tpd_CLK_Q : VitalDelayType01Z := ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns );
-- tpd_CLK_Q : VitalDelayArrayType(0 to 1)
-- := (0 => 5 ns, 1 => 6 ns);
-- tpd_CLK_Q : VitalDelayArrayType01(0 to 1)
-- := (0 => (tr01 => 2 ns, tr10 => 3 ns),
-- 1 => (tr01 => 2 ns, tr10 => 3 ns));
-- tpd_CLK_Q : VitalDelayArrayType01Z(0 to 1)
-- := (0 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ),
-- 1 => ( 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns ));
---------------------------------------------------------------------------
-- TRUE if the model is LEVEL0 | LEVEL1 compliant
ATTRIBUTE VITAL_Level0 : BOOLEAN;
ATTRIBUTE VITAL_Level1 : BOOLEAN;
SUBTYPE std_logic_vector2 IS std_logic_vector(1 DOWNTO 0);
SUBTYPE std_logic_vector3 IS std_logic_vector(2 DOWNTO 0);
SUBTYPE std_logic_vector4 IS std_logic_vector(3 DOWNTO 0);
SUBTYPE std_logic_vector8 IS std_logic_vector(7 DOWNTO 0);
-- Types for strength mapping of outputs
TYPE VitalOutputMapType IS ARRAY ( std_ulogic ) OF std_ulogic;
TYPE VitalResultMapType IS ARRAY ( UX01 ) OF std_ulogic;
TYPE VitalResultZMapType IS ARRAY ( UX01Z ) OF std_ulogic;
CONSTANT VitalDefaultOutputMap : VitalOutputMapType
:= "UX01ZWLH-";
CONSTANT VitalDefaultResultMap : VitalResultMapType
:= ( 'U', 'X', '0', '1' );
CONSTANT VitalDefaultResultZMap : VitalResultZMapType
:= ( 'U', 'X', '0', '1', 'Z' );
-- Types for fields of VitalTimingDataType
TYPE VitalTimeArrayT IS ARRAY (INTEGER RANGE <>) OF TIME;
TYPE VitalTimeArrayPT IS ACCESS VitalTimeArrayT;
TYPE VitalBoolArrayT IS ARRAY (INTEGER RANGE <>) OF BOOLEAN;
TYPE VitalBoolArrayPT IS ACCESS VitalBoolArrayT;
TYPE VitalLogicArrayPT IS ACCESS std_logic_vector;
TYPE VitalTimingDataType IS RECORD
NotFirstFlag : BOOLEAN;
RefLast : X01;
RefTime : TIME;
HoldEn : BOOLEAN;
TestLast : std_ulogic;
TestTime : TIME;
SetupEn : BOOLEAN;
TestLastA : VitalLogicArrayPT;
TestTimeA : VitalTimeArrayPT;
HoldEnA : VitalBoolArrayPT;
SetupEnA : VitalBoolArrayPT;
END RECORD;
FUNCTION VitalTimingDataInit RETURN VitalTimingDataType;
-- type for internal data of VitalPeriodPulseCheck
TYPE VitalPeriodDataType IS RECORD
Last : X01;
Rise : TIME;
Fall : TIME;
NotFirstFlag : BOOLEAN;
END RECORD;
CONSTANT VitalPeriodDataInit : VitalPeriodDataType
:= ('X', 0 ns, 0 ns, FALSE );
-- Type for specifying the kind of Glitch handling to use
TYPE VitalGlitchKindType IS (OnEvent,
OnDetect,
VitalInertial,
VitalTransport);
TYPE VitalGlitchDataType IS
RECORD
SchedTime : TIME;
GlitchTime : TIME;
SchedValue : std_ulogic;
LastValue : std_ulogic;
END RECORD;
TYPE VitalGlitchDataArrayType IS ARRAY (NATURAL RANGE <>)
OF VitalGlitchDataType;
-- PathTypes: for handling simple PathDelay info
TYPE VitalPathType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01Type IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01; -- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
TYPE VitalPath01ZType IS RECORD
InputChangeTime : TIME; -- timestamp for path input signal
PathDelay : VitalDelayType01Z;-- delay for this path
PathCondition : BOOLEAN; -- path sensitize condition
END RECORD;
-- For representing multiple paths to an output
TYPE VitalPathArrayType IS ARRAY (NATURAL RANGE <> ) OF VitalPathType;
TYPE VitalPathArray01Type IS ARRAY (NATURAL RANGE <> ) OF VitalPath01Type;
TYPE VitalPathArray01ZType IS ARRAY (NATURAL RANGE <> ) OF VitalPath01ZType;
TYPE VitalTableSymbolType IS (
'/', -- 0 -> 1
'\', -- 1 -> 0
'P', -- Union of '/' and '^' (any edge to 1)
'N', -- Union of '\' and 'v' (any edge to 0)
'r', -- 0 -> X
'f', -- 1 -> X
'p', -- Union of '/' and 'r' (any edge from 0)
'n', -- Union of '\' and 'f' (any edge from 1)
'R', -- Union of '^' and 'p' (any possible rising edge)
'F', -- Union of 'v' and 'n' (any possible falling edge)
'^', -- X -> 1
'v', -- X -> 0
'E', -- Union of 'v' and '^' (any edge from X)
'A', -- Union of 'r' and '^' (rising edge to or from 'X')
'D', -- Union of 'f' and 'v' (falling edge to or from 'X')
'*', -- Union of 'R' and 'F' (any edge)
'X', -- Unknown level
'0', -- low level
'1', -- high level
'-', -- don't care
'B', -- 0 or 1
'Z', -- High Impedance
'S' -- steady value
);
SUBTYPE VitalEdgeSymbolType IS VitalTableSymbolType RANGE '/' TO '*';
-- Addition of Vital Skew Type Information
-- March 14, 1998
---------------------------------------------------------------------------
-- Procedures and Type Definitions for Defining Skews
---------------------------------------------------------------------------
TYPE VitalSkewExpectedType IS (none, s1r, s1f, s2r, s2f);
TYPE VitalSkewDataType IS RECORD
ExpectedType : VitalSkewExpectedType;
Signal1Old1 : TIME;
Signal2Old1 : TIME;
Signal1Old2 : TIME;
Signal2Old2 : TIME;
END RECORD;
CONSTANT VitalSkewDataInit : VitalSkewDataType := ( none, 0 ns, 0 ns, 0 ns, 0 ns );
-- ------------------------------------------------------------------------
--
-- Function Name: VitalExtendToFillDelay
--
-- Description: A six element array of delay values of type
-- VitalDelayType01Z is returned when a 1, 2 or 6
-- element array is given. This function will convert
-- VitalDelayType and VitalDelayType01 delay values into
-- a VitalDelayType01Z type following these rules:
--
-- When a VitalDelayType is passed, all six transition
-- values are assigned the input value. When a
-- VitalDelayType01 is passed, the 01 transitions are
-- assigned to the 01, 0Z and Z1 transitions and the 10
-- transitions are assigned to 10, 1Z and Z0 transition
-- values. When a VitalDelayType01Z is passed, the values
-- are kept as is.
--
-- The function is overloaded based on input type.
--
-- There is no function to fill a 12 value delay
-- type.
--
-- Arguments:
--
-- IN Type Description
-- Delay A one, two or six delay value Vital-
-- DelayType is passed and a six delay,
-- VitalDelayType01Z, item is returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- VitalDelayType01Z
--
-- -------------------------------------------------------------------------
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01
) RETURN VitalDelayType01Z;
FUNCTION VitalExtendToFillDelay (
CONSTANT Delay : IN VitalDelayType01Z
) RETURN VitalDelayType01Z;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalCalcDelay
--
-- Description: This function accepts a 1, 2 or 6 value delay and
-- chooses the correct delay time to delay the NewVal
-- signal. This function is overloaded based on the
-- delay type passed. The function returns a single value
-- of time.
--
-- This function is provided for Level 0 models in order
-- to calculate the delay which should be applied
-- for the passed signal. The delay selection is performed
-- using the OldVal and the NewVal to determine the
-- transition to select. The default value of OldVal is X.
--
-- This function cannot be used in a Level 1 model since
-- the VitalPathDelay routines perform the delay path
-- selection and output driving function.
--
-- Arguments:
--
-- IN Type Description
-- NewVal New value of the signal to be
-- assigned
-- OldVal Previous value of the signal.
-- Default value is 'X'
-- Delay The delay structure from which to
-- select the appropriate delay. The
-- function overload is based on the
-- type of delay passed. In the case of
-- the single delay, VitalDelayType, no
-- selection is performed, since there
-- is only one value to choose from.
-- For the other cases, the transition
-- from the old value to the new value
-- decide the value returned.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- Time The time value selected from the
-- Delay INPUT is returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01
) RETURN TIME;
FUNCTION VitalCalcDelay (
CONSTANT NewVal : IN std_ulogic := 'X';
CONSTANT OldVal : IN std_ulogic := 'X';
CONSTANT Delay : IN VitalDelayType01Z
) RETURN TIME;
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPathDelay
--
-- Description: VitalPathDelay is the Level 1 routine used to select
-- the propagation delay path and schedule a new output
-- value.
--
-- For single and dual delay values, VitalDelayType and
-- VitalDelayType01 are used. The output value is
-- scheduled with a calculated delay without strength
-- modification.
--
-- For the six delay value, VitalDelayType01Z, the output
-- value is scheduled with a calculated delay. The drive
-- strength can be modified to handle weak signal strengths
-- to model tri-state devices, pull-ups and pull-downs as
-- an example.
--
-- The correspondence between the delay type and the
-- path delay function is as follows:
--
-- Delay Type Path Type
--
-- VitalDelayType VitalPathDelay
-- VitalDelayType01 VitalPathDelay01
-- VitalDelayType01Z VitalPathDelay01Z
--
-- For each of these routines, the following capabilities
-- is provided:
--
-- o Transition dependent path delay selection
-- o User controlled glitch detection with the ability
-- to generate "X" on output and report the violation
-- o Control of the severity level for message generation
-- o Scheduling of the computed values on the specified
-- signal.
--
-- Selection of the appropriate path delay begins with the
-- candidate paths. The candidate paths are selected by
-- identifying the paths for which the PathCondition is
-- true. If there is a single candidate path, then that
-- delay is selected. If there is more than one candidate
-- path, then the shortest delay is selected using
-- transition dependent delay selection. If there is no
-- candidate paths, then the delay specified by the
-- DefaultDelay parameter to the path delay is used.
--
-- Once the delay is known, the output signal is then
-- scheduled with that delay. In the case of
-- VitalPathDelay01Z, an additional result mapping of
-- the output value is performed before scheduling. The
-- result mapping is performed after transition dependent
-- delay selection but before scheduling the final output.
--
-- In order to perform glitch detection, the user is
-- obligated to provide a variable of VitalGlitchDataType
-- for the propagation delay functions to use. The user
-- cannot modify or use this information.
--
-- Arguments:
--
-- IN Type Description
-- OutSignalName string The name of the output signal
-- OutTemp std_logic The new output value to be driven
-- Paths VitalPathArrayType A list of paths of VitalPathArray
-- VitalPathArrayType01 type. The VitalPathDelay routine
-- VitalPathArrayType01Z is overloaded based on the type
-- of constant passed in. With
-- VitalPathArrayType01Z, the
-- resulting output strengths can be
-- mapped.
-- DefaultDelay VitalDelayType The default delay can be changed
-- VitalDelayType01 from zero-delay to another set
-- VitalDelayType01Z of values.
--
-- IgnoreDefaultDelay BOOLEAN If TRUE, the default delay will
-- be used when no paths are
-- selected. If false, no event
-- will be scheduled if no paths are
-- selected.
--
-- Mode VitalGlitchKindType The value of this constant
-- selects the type of glitch
-- detection.
-- OnEvent Glitch on transition event
-- | OnDetect Glitch immediate on detection
-- | VitalInertial No glitch, use INERTIAL
-- assignment
-- | VitalTransport No glitch, use TRANSPORT
-- assignment
-- XOn BOOLEAN Control for generation of 'X' on
-- glitch. When TRUE, 'X's are
-- scheduled for glitches, otherwise
-- no are generated.
-- MsgOn BOOLEAN Control for message generation on
-- glitch detect. When TRUE,
-- glitches are reported, otherwise
-- they are not reported.
-- MsgSeverity SEVERITY_LEVEL The level at which the message,
-- or assertion, will be reported.
-- IgnoreDefaultDelay BOOLEAN Tells the VPD whether to use the
-- default delay value in the absense
-- of a valid delay for input conditions 3/14/98 MG
--
-- OutputMap VitalOutputMapType For VitalPathDelay01Z, the output
-- can be mapped to alternate
-- strengths to model tri-state
-- devices, pull-ups and pull-downs.
--
-- INOUT
-- GlitchData VitalGlitchDataType The internal data storage
-- variable required to detect
-- glitches.
--
-- OUT
-- OutSignal std_logic The output signal to be driven
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalPathDelay (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArrayType;
CONSTANT DefaultDelay : IN VitalDelayType := VitalZeroDelay;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE --IR248 3/14/98
);
PROCEDURE VitalPathDelay01 (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01Type;
CONSTANT DefaultDelay : IN VitalDelayType01 := VitalZeroDelay01;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98
CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250
);
PROCEDURE VitalPathDelay01Z (
SIGNAL OutSignal : OUT std_logic;
VARIABLE GlitchData : INOUT VitalGlitchDataType;
CONSTANT OutSignalName : IN string;
CONSTANT OutTemp : IN std_logic;
CONSTANT Paths : IN VitalPathArray01ZType;
CONSTANT DefaultDelay : IN VitalDelayType01Z := VitalZeroDelay01Z;
CONSTANT Mode : IN VitalGlitchKindType := OnEvent;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT OutputMap : IN VitalOutputMapType := VitalDefaultOutputMap;
CONSTANT NegPreemptOn : IN BOOLEAN := FALSE; --IR225 3/14/98
CONSTANT IgnoreDefaultDelay : IN BOOLEAN := FALSE; --IR248 3/14/98
CONSTANT RejectFastPath : IN BOOLEAN := FALSE --IR250
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalWireDelay
--
-- Description: VitalWireDelay is used to delay an input signal.
-- The delay is selected from the input parameter passed.
-- The function is useful for back annotation of actual
-- net delays.
--
-- The function is overloaded to permit passing a delay
-- value for twire for VitalDelayType, VitalDelayType01
-- and VitalDelayType01Z. twire is a generic which can
-- be back annotated and must be constructed to follow
-- the SDF to generic mapping rules.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The input signal (port) to be
-- delayed.
-- twire VitalDelayType The delay value for which the input
-- VitalDelayType01 signal should be delayed. For Vital-
-- VitalDelayType01Z DelayType, the value is single value
-- passed. For VitalDelayType01 and
-- VitalDelayType01Z, the appropriate
-- delay value is selected by VitalCalc-
-- Delay.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The internal delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01
);
PROCEDURE VitalWireDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT twire : IN VitalDelayType01Z
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSignalDelay
--
-- Description: The VitalSignalDelay procedure is called in a signal
-- delay block in the architecture to delay the
-- appropriate test or reference signal in order to
-- accommodate negative constraint checks.
--
-- The amount of delay is of type TIME and is a constant.
--
-- Arguments:
--
-- IN Type Description
-- InSig std_ulogic The signal to be delayed.
-- dly TIME The amount of time the signal is
-- delayed.
--
-- INOUT
-- none
--
-- OUT
-- OutSig std_ulogic The delayed signal
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSignalDelay (
SIGNAL OutSig : OUT std_ulogic;
SIGNAL InSig : IN std_ulogic;
CONSTANT dly : IN TIME
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalSetupHoldCheck
--
-- Description: The VitalSetupHoldCheck procedure detects a setup or a
-- hold violation on the input test signal with respect
-- to the corresponding input reference signal. The timing
-- constraints are specified through parameters
-- representing the high and low values for the setup and
-- hold values for the setup and hold times. This
-- procedure assumes non-negative values for setup and hold
-- timing constraints.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative setup times result in
-- a delayed reference signal. Negative hold times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- This function is overloaded based on the input
-- TestSignal. A vector and scalar form are provided.
--
-- TestSignal XXXXXXXXXXXX____________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| error region |<--
-- :
-- _______________________________
-- RefSignal \______________________________
-- : | | |
-- : | -->| |<-- thold
-- : -->| tsetup |<--
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- std_logic_vector
-- TestSignalName STRING Name of test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- RefSignal std_ulogic Value of reference signal
-- RefSignalName STRING Name of reference signal
-- RefDelay TIME Model's internal delay associated
-- with RefSignal
-- SetupHigh TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a setup violation.
-- SetupLow TIME Absolute minimum time duration before
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a setup violation.
-- HoldHigh TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "1" state without
-- causing a hold violation.
-- HoldLow TIME Absolute minimum time duration after
-- the transition of RefSignal for which
-- transitions of TestSignal are allowed
-- to proceed to the "0" state without
-- causing a hold violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specified. Events on
-- the RefSignal which match the edge
-- spec. are used as reference edges.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0".
-- MsgOn BOOLEAN If TRUE, set and hold violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
-- EnableSetupOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no setup check will be performed.
-- EnableSetupOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no setup check will be performed.
-- EnableHoldOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no hold check will be performed.
-- EnableHoldOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no hold check will be performed.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalSetupHoldCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
PROCEDURE VitalSetupHoldCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_logic_vector;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT SetupHigh : IN TIME := 0 ns;
CONSTANT SetupLow : IN TIME := 0 ns;
CONSTANT HoldHigh : IN TIME := 0 ns;
CONSTANT HoldLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableSetupOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableSetupOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableHoldOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalRecoveryRemovalCheck
--
-- Description: The VitalRecoveryRemovalCheck detects the presence of
-- a recovery or removal violation on the input test
-- signal with respect to the corresponding input reference
-- signal. It assumes non-negative values of setup and
-- hold timing constraints. The timing constraint is
-- specified through parameters representing the recovery
-- and removal times associated with a reference edge of
-- the reference signal. A flag indicates whether a test
-- signal is asserted when it is high or when it is low.
--
-- It is assumed that negative timing constraints
-- are handled by internally delaying the test or
-- reference signals. Negative recovery times result in
-- a delayed reference signal. Negative removal times
-- result in a delayed test signal. Furthermore, the
-- delays and constraints associated with these and
-- other signals may need to be appropriately
-- adjusted so that all constraint intervals overlap
-- the delayed reference signals and all constraint
-- values (with respect to the delayed signals) are
-- non-negative.
--
-- Arguments:
--
-- IN Type Description
-- TestSignal std_ulogic Value of TestSignal. The routine is
-- TestSignalName STRING Name of TestSignal
-- TestDelay TIME Model internal delay associated with
-- the TestSignal
-- RefSignal std_ulogic Value of RefSignal
-- RefSignalName STRING Name of RefSignal
-- RefDelay TIME Model internal delay associated with
-- the RefSignal
-- Recovery TIME A change to an unasserted value on
-- the asynchronous TestSignal must
-- precede reference edge (on RefSignal)
-- by at least this time.
-- Removal TIME An asserted condition must be present
-- on the asynchronous TestSignal for at
-- least the removal time following a
-- reference edge on RefSignal.
-- ActiveLow BOOLEAN A flag which indicates if TestSignal
-- is asserted when it is low - "0."
-- FALSE indicate that TestSignal is
-- asserted when it has a value "1."
-- CheckEnabled BOOLEAN The check in enabled when the value
-- is TRUE, otherwise the constraints
-- are not checked.
-- RefTransition VitalEdgeSymbolType
-- Reference edge specifier. Events on
-- RefSignal will match the edge
-- specified.
-- HeaderMsg STRING A header message that will accompany
-- any assertion message.
-- XOn BOOLEAN When TRUE, the output Violation is
-- set to "X." When FALSE, it is always
-- "0."
-- MsgOn BOOLEAN When TRUE, violation messages are
-- output. When FALSE, no messages are
-- generated.
-- MsgSeverity SEVERITY_LEVEL Severity level of the asserted
-- message.
-- EnableRecOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no recovery check will be performed.
-- EnableRecOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no recovery check will be performed.
-- EnableRemOnRef BOOLEAN If FALSE at the time that the
-- RefSignal signal changes,
-- no removal check will be performed.
-- EnableRemOnTest BOOLEAN If FALSE at the time that the
-- TestSignal signal changes,
-- no removal check will be performed.
--
-- INOUT
-- TimingData VitalTimingDataType
-- VitalRecoveryRemovalCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the time of the last edge.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalRecoveryRemovalCheck (
VARIABLE Violation : OUT X01;
VARIABLE TimingData : INOUT VitalTimingDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName: IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
SIGNAL RefSignal : IN std_ulogic;
CONSTANT RefSignalName : IN STRING := "";
CONSTANT RefDelay : IN TIME := 0 ns;
CONSTANT Recovery : IN TIME := 0 ns;
CONSTANT Removal : IN TIME := 0 ns;
CONSTANT ActiveLow : IN BOOLEAN := TRUE;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT RefTransition : IN VitalEdgeSymbolType;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT EnableRecOnTest : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRecOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRemOnRef : IN BOOLEAN := TRUE; --IR252 3/23/98
CONSTANT EnableRemOnTest : IN BOOLEAN := TRUE --IR252 3/23/98
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalPeriodPulseCheck
--
-- Description: VitalPeriodPulseCheck checks for minimum
-- periodicity and pulse width for "1" and "0" values of
-- the input test signal. The timing constraint is
-- specified through parameters representing the minimal
-- period between successive rising and falling edges of
-- the input test signal and the minimum pulse widths
-- associated with high and low values.
--
-- VitalPeriodCheck's accepts rising and falling edges
-- from 1 and 0 as well as transitions to and from 'X.'
--
-- _______________ __________
-- ____________| |_______|
--
-- |<--- pw_hi --->|
-- |<-------- period ----->|
-- -->| pw_lo |<--
--
-- Arguments:
-- IN Type Description
-- TestSignal std_ulogic Value of test signal
-- TestSignalName STRING Name of the test signal
-- TestDelay TIME Model's internal delay associated
-- with TestSignal
-- Period TIME Minimum period allowed between
-- consecutive rising ('P') or
-- falling ('F') transitions.
-- PulseWidthHigh TIME Minimum time allowed for a high
-- pulse ('1' or 'H')
-- PulseWidthLow TIME Minimum time allowed for a low
-- pulse ('0' or 'L')
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0".
-- XOnChecks is a global that allows for
-- only timing checks to be turned on.
-- MsgOn BOOLEAN If TRUE, period/pulse violation
-- message will be generated.
-- Otherwise, no messages are generated,
-- even though a violation is detected.
-- MsgOnChecks allows for only timing
-- check messages to be turned on.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- PeriodData VitalPeriodDataType
-- VitalPeriodPulseCheck information
-- storage area. This is used
-- internally to detect reference edges
-- and record the pulse and period
-- times.
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- ------------------------------------------------------------------------
PROCEDURE VitalPeriodPulseCheck (
VARIABLE Violation : OUT X01;
VARIABLE PeriodData : INOUT VitalPeriodDataType;
SIGNAL TestSignal : IN std_ulogic;
CONSTANT TestSignalName : IN STRING := "";
CONSTANT TestDelay : IN TIME := 0 ns;
CONSTANT Period : IN TIME := 0 ns;
CONSTANT PulseWidthHigh : IN TIME := 0 ns;
CONSTANT PulseWidthLow : IN TIME := 0 ns;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT HeaderMsg : IN STRING := " ";
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalInPhaseSkewCheck
--
-- Description: The VitalInPhaseSkewCheck procedure detects an in-phase
-- skew violation between input signals Signal1 and Signal2.
-- This is a timer based skew check in which a
-- violation is detected if Signal1 and Signal2 are in
-- different logic states longer than the specified skew
-- interval.
--
-- The timing constraints are specified through parameters
-- representing the skew values for the different states
-- of Signal1 and Signal2.
--
--
-- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| |<--
-- : Signal2 should go low in this region
-- :
--
-- ____________
-- Signal1 \_________________________________________________
-- : | |
-- : |<-------- tskew -------->|
--
-- Arguments:
--
-- IN Type Description
-- Signal1 std_ulogic Value of first signal
-- Signal1Name STRING Name of first signal
-- Signal1Delay TIME Model's internal delay associated
-- with Signal1
-- Signal2 std_ulogic Value of second signal
-- Signal2Name STRING Name of second signal
-- Signal2Delay TIME Model's internal delay associated
-- with Signal2
-- SkewS1S2RiseRise TIME Absolute maximum time duration for
-- which Signal2 can remain at "0"
-- after Signal1 goes to the "1" state,
-- without causing a skew violation.
-- SkewS2S1RiseRise TIME Absolute maximum time duration for
-- which Signal1 can remain at "0"
-- after Signal2 goes to the "1" state,
-- without causing a skew violation.
-- SkewS1S2FallFall TIME Absolute maximum time duration for
-- which Signal2 can remain at "1"
-- after Signal1 goes to the "0" state,
-- without causing a skew violation.
-- SkewS2S1FallFall TIME Absolute maximum time duration for
-- which Signal1 can remain at "1"
-- after Signal2 goes to the "0" state,
-- without causing a skew violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, skew timing violation
-- messages will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- SkewData VitalSkewDataType
-- VitalInPhaseSkewCheck information
-- storage area. This is used
-- internally to detect signal edges
-- and record the time of the last edge.
--
--
-- Trigger std_ulogic This signal is used to trigger the
-- process in which the timing check
-- occurs upon expiry of the skew
-- interval.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalInPhaseSkewCheck (
VARIABLE Violation : OUT X01;
VARIABLE SkewData : INOUT VitalSkewDataType;
SIGNAL Signal1 : IN std_ulogic;
CONSTANT Signal1Name : IN STRING := "";
CONSTANT Signal1Delay : IN TIME := 0 ns;
SIGNAL Signal2 : IN std_ulogic;
CONSTANT Signal2Name : IN STRING := "";
CONSTANT Signal2Delay : IN TIME := 0 ns;
CONSTANT SkewS1S2RiseRise : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1RiseRise : IN TIME := TIME'HIGH;
CONSTANT SkewS1S2FallFall : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1FallFall : IN TIME := TIME'HIGH;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT HeaderMsg : IN STRING := "";
SIGNAL Trigger : INOUT std_ulogic
);
-- ------------------------------------------------------------------------
--
-- Function Name: VitalOutPhaseSkewCheck
--
-- Description: The VitalOutPhaseSkewCheck procedure detects an
-- out-of-phase skew violation between input signals Signal1
-- and Signal2. This is a timer based skew check in
-- which a violation is detected if Signal1 and Signal2 are
-- in the same logic state longer than the specified skew
-- interval.
--
-- The timing constraints are specified through parameters
-- representing the skew values for the different states
-- of Signal1 and Signal2.
--
--
-- Signal2 XXXXXXXXXXXX___________________________XXXXXXXXXXXXXXXXXXXXXX
-- :
-- : -->| |<--
-- : Signal2 should go high in this region
-- :
--
-- ____________
-- Signal1 \_________________________________________________
-- : | |
-- : |<-------- tskew -------->|
--
-- Arguments:
--
-- IN Type Description
-- Signal1 std_ulogic Value of first signal
-- Signal1Name STRING Name of first signal
-- Signal1Delay TIME Model's internal delay associated
-- with Signal1
-- Signal2 std_ulogic Value of second signal
-- Signal2Name STRING Name of second signal
-- Signal2Delay TIME Model's internal delay associated
-- with Signal2
-- SkewS1S2RiseFall TIME Absolute maximum time duration for
-- which Signal2 can remain at "1"
-- after Signal1 goes to the "1" state,
-- without causing a skew violation.
-- SkewS2S1RiseFall TIME Absolute maximum time duration for
-- which Signal1 can remain at "1"
-- after Signal2 goes to the "1" state,
-- without causing a skew violation.
-- SkewS1S2FallRise TIME Absolute maximum time duration for
-- which Signal2 can remain at "0"
-- after Signal1 goes to the "0" state,
-- without causing a skew violation.
-- SkewS2S1FallRise TIME Absolute maximum time duration for
-- which Signal1 can remain at "0"
-- after Signal2 goes to the "0" state,
-- without causing a skew violation.
-- CheckEnabled BOOLEAN Check performed if TRUE.
-- HeaderMsg STRING String that will accompany any
-- assertion messages produced.
-- XOn BOOLEAN If TRUE, Violation output parameter
-- is set to "X". Otherwise, Violation
-- is always set to "0."
-- MsgOn BOOLEAN If TRUE, skew timing violation
-- messages will be generated.
-- Otherwise, no messages are generated,
-- even upon violations.
-- MsgSeverity SEVERITY_LEVEL Severity level for the assertion.
--
-- INOUT
-- SkewData VitalSkewDataType
-- VitalInPhaseSkewCheck information
-- storage area. This is used
-- internally to detect signal edges
-- and record the time of the last edge.
--
-- Trigger std_ulogic This signal is used to trigger the
-- process in which the timing check
-- occurs upon expiry of the skew
-- interval.
--
-- OUT
-- Violation X01 This is the violation flag returned.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalOutPhaseSkewCheck (
VARIABLE Violation : OUT X01;
VARIABLE SkewData : INOUT VitalSkewDataType;
SIGNAL Signal1 : IN std_ulogic;
CONSTANT Signal1Name : IN STRING := "";
CONSTANT Signal1Delay : IN TIME := 0 ns;
SIGNAL Signal2 : IN std_ulogic;
CONSTANT Signal2Name : IN STRING := "";
CONSTANT Signal2Delay : IN TIME := 0 ns;
CONSTANT SkewS1S2RiseFall : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1RiseFall : IN TIME := TIME'HIGH;
CONSTANT SkewS1S2FallRise : IN TIME := TIME'HIGH;
CONSTANT SkewS2S1FallRise : IN TIME := TIME'HIGH;
CONSTANT CheckEnabled : IN BOOLEAN := TRUE;
CONSTANT XOn : IN BOOLEAN := TRUE;
CONSTANT MsgOn : IN BOOLEAN := TRUE;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING;
CONSTANT HeaderMsg : IN STRING := "";
SIGNAL Trigger : INOUT std_ulogic
);
END VITAL_Timing;
|
gpl-3.0
|
nickg/nvc
|
test/regress/signal5.vhd
|
5
|
325
|
entity signal5 is
end entity;
architecture test of signal5 is
signal x, y : integer;
begin
update_y: y <= x + 4;
stim: process is
begin
x <= 1;
wait for 1 ns;
assert y = 5;
x <= 10;
wait on y;
assert y = 14;
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/project.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/xbip_bram18k_v3_0_2/hdl/xbip_bram18k_v3_0.vhd
|
9
|
9340
|
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`protect end_protected
|
gpl-3.0
|
nickg/nvc
|
test/regress/operator5.vhd
|
5
|
819
|
package pack is
type int_vec2 is array (integer range <>) of integer;
type int_vec is array (integer range <>) of integer;
function "<"(a, b : int_vec) return boolean;
end package;
package body pack is
function "<"(a, b : int_vec) return boolean is
begin
return false;
end function;
end package body;
entity operator5 is
end entity;
use work.pack.all;
architecture test of operator5 is
function ">="(a, b : int_vec) return boolean is
begin
return false;
end function;
begin
process is
variable x, y : int_vec(1 to 3);
begin
x := (1, 2, 3);
y := (4, 5, 6);
assert not (y >= x);
assert (int_vec2(y) >= int_vec2(x));
assert not (y < x) and not (x < y);
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reset.vhd
|
3
|
39337
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_bram_ctrl_v4_0/hdl/vhdl/correct_one_bit_64.vhd
|
7
|
8400
|
-------------------------------------------------------------------------------
-- correct_one_bit_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit_64.vhd
--
-- Description: Identifies single bit to correct in 64-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit_64 is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 7));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 7);
DCorr : out std_logic);
end entity Correct_One_Bit_64;
architecture IMP of Correct_One_Bit_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 7)) return natural is
begin -- function find_one
for I in 0 to 7 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 6);
signal lut_corr_val : std_logic_vector(0 to 6);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 7);
lut_corr_val <= Correct_Value(1 to 7);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 6);
lut_corr_val <= Correct_Value(0 to 6);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 7);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 7);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
|
gpl-3.0
|
nickg/nvc
|
test/sem/issue102.vhd
|
5
|
328
|
package COMPONENTS is
component DUMMY_MODULE
port (I : in bit; O : out bit);
end component;
end package;
use WORK.COMPONENTS.DUMMY_MODULE;
entity DUMMY_TOP is
port (I : in bit; O : out bit);
end entity;
architecture RTL of DUMMY_TOP is
begin
U: DUMMY_MODULE port map(I=>I, O=>O);
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/lib_srl_fifo_v1_0/hdl/src/vhdl/dynshreg_f.vhd
|
15
|
11276
|
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
-- constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
-- constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
-- (C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
-- constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
constant W32 : boolean := (C_DEPTH > 16);
constant W16 : boolean := (not W32);
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
-- constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
-- and ( (W16 and C_DEPTH >= 16)
-- or (W32 and C_DEPTH >= 32)
-- )
-- )
-- or (not W32 and not W16);
constant USE_INFERRED : boolean := true;
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/lib_srl_fifo_v1_0/hdl/src/vhdl/dynshreg_f.vhd
|
15
|
11276
|
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
-- constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
-- constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
-- (C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
-- constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
constant W32 : boolean := (C_DEPTH > 16);
constant W16 : boolean := (not W32);
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
-- constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
-- and ( (W16 and C_DEPTH >= 16)
-- or (W32 and C_DEPTH >= 32)
-- )
-- )
-- or (not W32 and not W16);
constant USE_INFERRED : boolean := true;
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/hdl/vhdl/ua_narrow.vhd
|
6
|
18144
|
-------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: ua_narrow.vhd
--
-- Description: Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/8/2011 v1.03a
-- ~~~~~~
-- Update bit vector usage of address LSB for calculating ua_narrow_load.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Update range of integer signals.
-- ^^^^^^
-- JLJ 3/4/2011 v1.03a
-- ~~~~~~
-- Remove use of local function, Create_Size_Max.
-- ^^^^^^
-- JLJ 3/11/2011 v1.03a
-- ~~~~~~
-- Remove C_AXI_DATA_WIDTH generate statments.
-- ^^^^^^
-- JLJ 3/14/2011 v1.03a
-- ~~~~~~
-- Update ua_narrow_load signal assignment to pass simulations & XST.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, ua_narrow_wrap_gt_width,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity ua_narrow is
generic (
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_NARROW_BURST_CNT_LEN : integer := 4
-- Size of narrow burst counter
);
port (
curr_wrap_burst : in std_logic;
curr_incr_burst : in std_logic;
bram_addr_ld_en : in std_logic;
curr_axlen : in std_logic_vector (7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector (2 downto 0) := (others => '0');
curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
curr_ua_narrow_wrap : out std_logic;
curr_ua_narrow_incr : out std_logic;
ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0)
:= (others => '0')
);
end entity ua_narrow;
-------------------------------------------------------------------------------
architecture implementation of ua_narrow is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- Use constant to compare when LSB of ADDR is equal to zero.
constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0).
constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) :=
to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal ua_narrow_wrap_gt_width : std_logic := '0';
signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal curr_axsize_int : integer := 0;
signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1;
signal size_plus_lsb : integer range 1 to 256 := 1;
signal narrow_addr_offset : integer := 1;
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- v1.03a
-- Added for narrow INCR bursts with UA addresses
-- Check if burst is a) INCR type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1')
else '0';
-- v1.03a
-- Detect narrow WRAP bursts
-- Detect if the operation is a) WRAP type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
-- d) complete size of WRAP is larger than width of BRAM
curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1') and
(ua_narrow_wrap_gt_width = '1')
else '0';
---------------------------------------------------------------------------
-- v1.03a
-- Check condition if narrow burst wraps within the size of the BRAM width.
-- Check if size * length > BRAM width in bytes.
--
-- When asserted = '1', means that narrow burst counter is not preloaded early,
-- the BRAM burst will be contained within the BRAM data width.
curr_axsize_unsigned <= unsigned (curr_axsize);
curr_axsize_int <= to_integer (curr_axsize_unsigned);
curr_axlen_unsigned <= unsigned (curr_axlen);
-- Original logic with multiply function.
--
-- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) *
-- unsigned (curr_axlen (7 downto 0)))
-- < C_AXI_DATA_WIDTH_BYTES)
-- else '1';
-- Replace with left shift operation of AxLEN.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int)
begin
for i in C_MAX_LSHIFT_SIZE downto 0 loop
if (i >= curr_axsize_int + 8) then
curr_axlen_unsigned_lshift (i) <= '0';
elsif (i >= curr_axsize_int) then
curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int);
else
curr_axlen_unsigned_lshift (i) <= '0';
end if;
end loop;
end process LEN_LSHIFT;
-- Final result.
ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED)
else '1';
---------------------------------------------------------------------------
-- v1.03a
-- For narrow burst transfer, provides the number of bytes per address
-- XST does not support divisors that are not constants AND powers of two.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned)));
-- With this new process:
-- Replace case statement with unsigned signal comparator.
DIV_AXSIZE: process (curr_axsize)
begin
case (curr_axsize) is
when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus
when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES;
end case;
end process DIV_AXSIZE;
-- Original statement.
-- XST does not support divisors that are not constants AND powers of two.
-- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load.
--
-- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned)));
--
-- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
-- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN));
-- AxSIZE + LSB of address
-- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH
size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) +
to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0)));
-- Process to keep synthesis with divide by constants that are a power of 2.
DIV_SIZE_BYTES: process (size_plus_lsb,
curr_axsize)
begin
-- Use unsigned w/ curr_axsize signal
case (curr_axsize) is
when "000" => narrow_addr_offset <= size_plus_lsb / 1;
when "001" => narrow_addr_offset <= size_plus_lsb / 2;
when "010" => narrow_addr_offset <= size_plus_lsb / 4;
when "011" => narrow_addr_offset <= size_plus_lsb / 8;
when "100" => narrow_addr_offset <= size_plus_lsb / 16;
when "101" => narrow_addr_offset <= size_plus_lsb / 32;
when "110" => narrow_addr_offset <= size_plus_lsb / 64;
when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus
when others => narrow_addr_offset <= size_plus_lsb;
end case;
end process DIV_SIZE_BYTES;
-- Final new statement.
-- Passing in simulation and XST.
ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
narrow_addr_offset, C_NARROW_BURST_CNT_LEN))
when (bytes_per_addr >= narrow_addr_offset)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
end architecture implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue481.vhd
|
1
|
314
|
entity issue481 is
end entity;
architecture beh of issue481 is
signal sig_1 : bit;
begin
process
begin
assert sig_1 = '0';
sig_1 <= force '1';
wait for 1 ps;
assert sig_1 = '1' report "signal val is not 1 " & to_string(sig_1) severity failure;
wait;
end process;
end architecture beh;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd
|
3
|
75297
|
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1_10.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When (mm2s_rresp = DECERR and mm2s_rvalid = '1')
Else '0';
sig_slverr <= '1'
When (mm2s_rresp = SLVERR and mm2s_rvalid = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/vests15.vhd
|
1
|
4784
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2959.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02959pkg is
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit_vector;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN boolean;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN character;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN real;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN string;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN time;
end c02s03b00x00p02n01i02959pkg;
package body c02s03b00x00p02n01i02959pkg is
FUNCTION boo ( PARM_VAL : bit_vector) RETURN time IS
BEGIN
assert false report "boo with TIME returned" severity note;
RETURN 10 ns;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN string IS
BEGIN
assert false report "boo with STRING returned" severity note;
RETURN "STRING";
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN real IS
BEGIN
assert false report "boo with REAL returned" severity note;
RETURN 10.01;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with INTEGER returned" severity note;
RETURN 55;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN character IS
BEGIN
assert false report "boo with CHARACTER returned" severity note;
RETURN 'Z';
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN boolean IS
BEGIN
assert false report "boo with BOOLEAN returned" severity note;
RETURN TRUE;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit_vector IS
BEGIN
assert false report "boo with BIT_VECTOR returned" severity
note;
RETURN "1010";
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit IS
BEGIN
assert false report "boo with BIT returned" severity note;
RETURN '1';
END;
end c02s03b00x00p02n01i02959pkg;
ENTITY vests15 IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END vests15;
use work.c02s03b00x00p02n01i02959pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02959arch OF vests15 IS
SIGNAL c1 : bv_4;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo ( bv_6'(OTHERS => '1'));
bb <= boo (c1);
bv <= boo (c1);
bo <= boo (c1);
cc <= boo (c1);
ii <= boo (c1);
rr <= boo (c1);
ss <= boo (c1);
tt <= boo (c1);
WAIT FOR 1 ns;
assert NOT( (c1 = "1010") AND
(bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***PASSED TEST: c02s03b00x00p02n01i02959"
severity NOTE;
assert ( (c1 = "1010") AND
(bb = '1') AND
(bv = "1010") AND
(bo = TRUE) AND
(cc = 'Z') AND
(ii = 55) AND
(rr = 10.01) AND
(ss = "STRING") AND
(tt = 10 ns))
report "***FAILED TEST: c02s03b00x00p02n01i02959 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02959arch;
|
gpl-3.0
|
nickg/nvc
|
test/regress/wait11.vhd
|
5
|
370
|
entity wait11 is
end entity;
architecture test of wait11 is
begin
process is
begin
wait for 0.1 ns;
assert now = 100 ps;
wait for 0.5 ns;
assert now = 600 ps;
wait for 1 ns / 10.0;
assert now = 700 ps;
wait for 10 ps * 10.0;
assert now = 800 ps;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/bitvec.vhd
|
2
|
748
|
entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
variable n : integer;
begin
b := "1101";
n := 2;
wait for 1 ns;
assert not b = "0010";
assert (b and "1010") = "1000";
assert (b or "0110") = "1111";
assert (b xor "0111") = "1010";
assert (b xnor "0111") = "0101";
assert (b nand "1010") = "0111";
assert (b nor "0110") = "0000";
assert get_bitvec(1, n) = "00";
wait;
end process;
end architecture;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/hdl/vhdl/lite_ecc_reg.vhd
|
7
|
68156
|
-------------------------------------------------------------------------------
-- lite_ecc_reg.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: lite_ecc_reg.vhd
--
-- Description: This module contains the register components for the
-- ECC status & control data when enabled.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/17/2011 v1.03a
-- ~~~~~~
-- Add ECC support for 128-bit BRAM data width.
-- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and
-- modify BRAM address registers.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_lite_if;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity lite_ecc_reg is
generic (
C_S_AXI_PROTOCOL : string := "AXI4";
-- Used in this module to differentiate timing for error capture
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_SINGLE_PORT_BRAM : INTEGER := 1;
-- Enable single port usage of BRAM
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Clock and Reset
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI-Lite Clock and Reset
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
-- S_AXI_CTRL_AClk : in std_logic;
-- S_AXI_CTRL_AResetn : in std_logic;
Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- *** AXI-Lite ECC Register Interface Signals ***
-- All synchronized to S_AXI_CTRL_AClk
-- AXI-Lite Write Address Channel Signals (AW)
AXI_CTRL_AWVALID : in std_logic;
AXI_CTRL_AWREADY : out std_logic;
AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_WVALID : in std_logic;
AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_BVALID : out std_logic;
AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
AXI_CTRL_ARVALID : in std_logic;
AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
AXI_CTRL_RVALID : out std_logic;
AXI_CTRL_RREADY : in std_logic;
-- *** Memory Controller Interface Signals ***
-- All synchronized to S_AXI_AClk
Enable_ECC : out std_logic;
-- Indicates if and when ECC is enabled
FaultInjectClr : in std_logic;
-- Clear for Fault Inject Registers
CE_Failing_We : in std_logic;
-- WE for CE Failing Registers
-- UE_Failing_We : in std_logic;
-- WE for CE Failing Registers
CE_CounterReg_Inc : in std_logic;
-- Increment CE Counter Register
Sl_CE : in std_logic;
-- Correctable Error Flag
Sl_UE : in std_logic;
-- Uncorrectable Error Flag
BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a
BRAM_Addr_En : in std_logic;
Active_Wr : in std_logic;
-- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
-- Outputs
FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1);
FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1)
);
end entity lite_ecc_reg;
-------------------------------------------------------------------------------
architecture implementation of lite_ecc_reg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4"));
constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE"));
-- Start LMB BRAM v3.00a HDL
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirrorring of registers in address space of module
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11
constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00
constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01
constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10
constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00
constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00
constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01
constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00
constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01
constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10
constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00
constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00
constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00
constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00
constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01
constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10
constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
constant C_ECC_ON_OFF_WIDTH : natural := 1;
-- End LMB BRAM v3.00a HDL
constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0');
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal S_AXI_AReset : std_logic;
-- Start LMB BRAM v3.00a HDL
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
--signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
--signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0');
signal RegWr : std_logic;
signal RegWr_i : std_logic;
--signal RegWr_d1 : std_logic;
--signal RegWr_d2 : std_logic;
-- Fault Inject Register
signal FaultInjectData_WE_0 : std_logic := '0';
signal FaultInjectData_WE_1 : std_logic := '0';
signal FaultInjectData_WE_2 : std_logic := '0';
signal FaultInjectData_WE_3 : std_logic := '0';
signal FaultInjectECC_WE : std_logic := '0';
--signal FaultInjectClr : std_logic := '0';
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0');
signal CE_Failing_We_i : std_logic := '0';
-- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
-- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0');
-- signal UE_Failing_We_i : std_logic := '0';
-- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
-- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0');
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0');
signal ECC_EnableIRQReg_WE : std_logic := '0';
-- ECC On/Off Control register
signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0');
signal ECC_OnOffReg_WE : std_logic := '0';
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0');
signal CE_CounterReg_WE : std_logic := '0';
signal CE_CounterReg_Inc_i : std_logic := '0';
-- End LMB BRAM v3.00a HDL
signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0');
signal Enable_ECC_i : std_logic := '0';
signal ECC_UE_i : std_logic := '0';
signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0');
signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
FaultInjectData <= FaultInjectData_i;
FaultInjectECC <= FaultInjectECC_i;
-- Reserve for future support.
-- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn);
S_AXI_AReset <= not (S_AXI_AResetn);
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
--
-- Description:
-- This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
--
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
--
-- Synchronized to AXI-Lite clock and reset.
-- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to
-- the AXI clock.
--
---------------------------------------------------------------------------
I_AXI_LITE_IF : entity work.axi_lite_if
generic map(
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH
)
port map (
-- Reserve for future support.
-- LMB_Clk => S_AXI_CTRL_AClk,
-- LMB_Rst => S_AXI_CTRL_AReset,
LMB_Clk => S_AXI_AClk,
LMB_Rst => S_AXI_AReset,
S_AXI_AWADDR => AXI_CTRL_AWADDR,
S_AXI_AWVALID => AXI_CTRL_AWVALID,
S_AXI_AWREADY => AXI_CTRL_AWREADY,
S_AXI_WDATA => AXI_CTRL_WDATA,
S_AXI_WSTRB => axi_lite_wstrb_int,
S_AXI_WVALID => AXI_CTRL_WVALID,
S_AXI_WREADY => AXI_CTRL_WREADY,
S_AXI_BRESP => AXI_CTRL_BRESP,
S_AXI_BVALID => AXI_CTRL_BVALID,
S_AXI_BREADY => AXI_CTRL_BREADY,
S_AXI_ARADDR => AXI_CTRL_ARADDR,
S_AXI_ARVALID => AXI_CTRL_ARVALID,
S_AXI_ARREADY => AXI_CTRL_ARREADY,
S_AXI_RDATA => AXI_CTRL_RDATA,
S_AXI_RRESP => AXI_CTRL_RRESP,
S_AXI_RVALID => AXI_CTRL_RVALID,
S_AXI_RREADY => AXI_CTRL_RREADY,
RegWr => RegWr_i,
RegWrData => RegWrData_i,
RegAddr => RegAddr_i,
RegRdData => RegRdData_i
);
-- Note: AXI-Lite Control IF and AXI IF share the same clock.
--
-- Save HDL
-- If it is decided to go back and use seperate clock inputs
-- One for AXI4 and one for AXI4-Lite on this core.
-- For now, temporarily comment out and replace the *_i signal
-- assignments.
RegWr <= RegWr_i;
RegWrData <= RegWrData_i;
RegAddr <= RegAddr_i;
RegRdData_i <= RegRdData;
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- --
-- -- All registers must be synchronized to the correct clock.
-- -- RegWr must be synchronized to the S_AXI_Clk
-- -- RegWrData must be synchronized to the S_AXI_Clk
-- -- RegAddr must be synchronized to the S_AXI_Clk
-- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk
-- --
-- ---------------------------------------------------------------------------
--
-- SYNC_AXI_CLK: process (S_AXI_AClk)
-- begin
-- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- RegWr_d1 <= RegWr_i;
-- RegWr_d2 <= RegWr_d1;
-- RegWrData_d1 <= RegWrData_i;
-- RegWrData_d2 <= RegWrData_d1;
-- RegAddr_d1 <= RegAddr_i;
-- RegAddr_d2 <= RegAddr_d1;
-- end if;
-- end process SYNC_AXI_CLK;
--
-- RegWr <= RegWr_d2;
-- RegWrData <= RegWrData_d2;
-- RegAddr <= RegAddr_d2;
--
--
-- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk)
-- begin
-- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then
-- RegRdData_d1 <= RegRdData;
-- RegRdData_d2 <= RegRdData_d1;
-- end if;
-- end process SYNC_AXI_LITE_CLK;
--
-- RegRdData_i <= RegRdData_d2;
--
---------------------------------------------------------------------------
axi_lite_wstrb_int <= (others => '1');
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_SNG
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If single port, only register Port A address.
--
-- With CE flag being registered, must account for one more
-- pipeline stage in stored BRAM addresss that correlates to
-- failing ECC.
---------------------------------------------------------------------------
GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
-- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY
signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_A_d2 <= BRAM_Addr_A_d2;
BRAM_Addr_A_d3 <= BRAM_Addr_A_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time.
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline).
-- During read operaitons, use 3-deep address pipeline to store address values.
FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR_REG_DUAL
-- Purpose: Generate two deep wrap-around address pipeline to store
-- read address presented to BRAM. Used to update ECC
-- register value when ECC correctable or uncorrectable error
-- is detected.
--
-- If dual port BRAM, register Port A & Port B address.
--
-- Account for CE flag register delay, add 3rd BRAM address
-- pipeline stage.
--
---------------------------------------------------------------------------
GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
-- Port B pipeline stages only used in a dual port mode configuration.
signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a
begin
BRAM_ADDR_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (BRAM_Addr_En = '1') then
BRAM_Addr_A_d1 <= BRAM_Addr_A;
BRAM_Addr_B_d1 <= BRAM_Addr_B;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d2;
else
BRAM_Addr_A_d1 <= BRAM_Addr_A_d1;
BRAM_Addr_B_d1 <= BRAM_Addr_B_d1;
BRAM_Addr_B_d2 <= BRAM_Addr_B_d2;
BRAM_Addr_B_d3 <= BRAM_Addr_B_d3;
end if;
end if;
end process BRAM_ADDR_REG;
---------------------------------------------------------------------------
-- Generate: GEN_L_ADDR
-- Purpose: Lower order BRAM address bits fixed @ zero depending
-- on BRAM data width size.
---------------------------------------------------------------------------
GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
FailingAddr_Ld (i) <= '0';
end generate GEN_L_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_ADDR
-- Purpose: Assign valid BRAM address bits based on BRAM data width size.
---------------------------------------------------------------------------
GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
GEN_FA_LITE: if IF_IS_AXI4LITE generate
begin
-- Only one active operation at a time.
-- Use one deep address pipeline. Determine if Port A or B based on active read or write.
FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_LITE;
GEN_FA_AXI: if IF_IS_AXI4 generate
begin
-- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A).
-- During read operations, use 3-deep address pipeline to store address values (and from Port B).
FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i);
end generate GEN_FA_AXI;
end generate GEN_ADDR;
end generate GEN_ADDR_REG_DUAL;
---------------------------------------------------------------------------
-- Generate: FAULT_INJECT
-- Purpose: Implement fault injection registers
-- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB)
---------------------------------------------------------------------------
FAULT_INJECT : if C_HAS_FAULT_INJECT generate
begin
-- FaultInjectClr added to top level port list.
-- Original LMB BRAM HDL
-- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0';
---------------------------------------------------------------------------
-- Generate: GEN_32_FAULT
-- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 32-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (25:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_32_FAULT;
---------------------------------------------------------------------------
-- Generate: GEN_64_FAULT
-- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 64-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
-- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1);
-- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1);
-- (24:31)
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_64_FAULT;
-- v1.03a
---------------------------------------------------------------------------
-- Generate: GEN_128_FAULT
-- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH
---------------------------------------------------------------------------
GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate
begin
FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0';
FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0';
FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0';
FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0';
FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0';
-- Create fault vector for 128-bit data widths
FaultInjectDataReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
elsif FaultInjectData_WE_0 = '1' then
FaultInjectData_i (96 to 127) <= RegWrData;
elsif FaultInjectData_WE_1 = '1' then
FaultInjectData_i (64 to 95) <= RegWrData;
elsif FaultInjectData_WE_2 = '1' then
FaultInjectData_i (32 to 63) <= RegWrData;
elsif FaultInjectData_WE_3 = '1' then
FaultInjectData_i (0 to 31) <= RegWrData;
elsif FaultInjectECC_WE = '1' then
FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1);
elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate GEN_128_FAULT;
end generate FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: NO_FAULT_INJECT
-- Purpose: Set default outputs when no fault inject capabilities.
-- Remove check from C_WRITE_ACCESS (from LMB)
---------------------------------------------------------------------------
NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate
begin
FaultInjectData_i <= (others => '0');
FaultInjectECC_i <= (others => '0');
end generate NO_FAULT_INJECT;
---------------------------------------------------------------------------
-- Generate: CE_FAILING_REGISTERS
-- Purpose: Implement Correctable Error First Failing Register
---------------------------------------------------------------------------
CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate
begin
-- TBD (could come from axi_lite)
-- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
-- else '0';
CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0')
else '0';
CE_FailingReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
CE_FailingAddress <= (others => '0');
-- Reserve for future support.
-- CE_FailingData <= (others => '0');
elsif CE_Failing_We_i = '1' then
--As the AXI Addr Width can now be lesser than 32, the address is getting shifted
--Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000
CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0);
--CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ;
-- Reserve for future support.
-- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1);
end if;
end if;
end process CE_FailingReg;
-- Note: Remove storage of CE_FFE & CE_FFD registers.
-- Here for future support.
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_CE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- CE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- CE_FailingECC <= (others => '0');
-- elsif CE_Failing_We_i = '1' then
-- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process CE_FailingECCReg;
--
-- end generate GEN_CE_ECC_64;
end generate CE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_CE_FAILING_REGISTERS
-- Purpose: No Correctable Error Failing registers.
---------------------------------------------------------------------------
NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
-- CE_FailingData <= (others => '0');
-- CE_FailingECC <= (others => '0');
end generate NO_CE_FAILING_REGISTERS;
-- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0
-- This generate clause will never be evaluated.
-- Here for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: UE_FAILING_REGISTERS
-- -- Purpose: Implement Unorrectable Error First Failing Register
-- ---------------------------------------------------------------------------
--
-- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate
-- begin
--
-- -- TBD (could come from axi_lite)
-- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- -- else '0';
--
-- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0')
-- else '0';
--
--
-- UE_FailingReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingAddress <= FailingAddr_Ld;
-- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingReg;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_32
-- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39)
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_32;
--
-- -----------------------------------------------------------------
-- -- Generate: GEN_UE_ECC_64
-- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width.
-- -----------------------------------------------------------------
-- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate
-- begin
--
-- UE_FailingECCReg : process(S_AXI_AClk) is
-- begin
-- if S_AXI_AClk'event and S_AXI_AClk = '1' then
-- if S_AXI_AResetn = C_RESET_ACTIVE then
-- UE_FailingECC <= (others => '0');
-- elsif UE_Failing_We = '1' then
-- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1);
-- end if;
-- end if;
-- end process UE_FailingECCReg;
--
-- end generate GEN_UE_ECC_64;
--
-- end generate UE_FAILING_REGISTERS;
--
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_UE_FAILING_REGISTERS
-- -- Purpose: No Uncorrectable Error Failing registers.
-- ---------------------------------------------------------------------------
--
-- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate
-- begin
-- UE_FailingAddress <= (others => '0');
-- UE_FailingData <= (others => '0');
-- UE_FailingECC <= (others => '0');
-- end generate NO_UE_FAILING_REGISTERS;
---------------------------------------------------------------------------
-- Generate: ECC_STATUS_REGISTERS
-- Purpose: Enable ECC status and interrupt enable registers.
---------------------------------------------------------------------------
ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE;
ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE;
StatusReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
ECC_EnableIRQReg <= (others => '0');
elsif ECC_EnableIRQReg_WE = '1' then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
---------------------------------------------------------------------------
-- Generate output flag for UE sticky bit
-- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted.
REG_UE : process (S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE or
(Enable_ECC_i = '0') then
ECC_UE_i <= '0';
elsif Sl_UE = '1' then
ECC_UE_i <= '1';
elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then
ECC_UE_i <= '0';
else
ECC_UE_i <= ECC_UE_i;
end if;
end if;
end process REG_UE;
ECC_UE <= ECC_UE_i;
---------------------------------------------------------------------------
end generate ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: NO_ECC_STATUS_REGISTERS
-- Purpose: No ECC status or interrupt registers enabled.
---------------------------------------------------------------------------
NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
ECC_UE <= '0';
end generate NO_ECC_STATUS_REGISTERS;
---------------------------------------------------------------------------
-- Generate: GEN_ECC_ONOFF
-- Purpose: Implement ECC on/off control register.
---------------------------------------------------------------------------
GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate
begin
ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0';
EnableIRQReg : process(S_AXI_AClk) is
begin
if S_AXI_AClk'event and S_AXI_AClk = '1' then
if S_AXI_AResetn = C_RESET_ACTIVE then
if (C_ECC_ONOFF_RESET_VALUE = 0) then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
else
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1';
end if;
-- ECC on by default at reset (but can be disabled)
elsif ECC_OnOffReg_WE = '1' then
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH);
end if;
end if;
end process EnableIRQReg;
Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH);
Enable_ECC <= Enable_ECC_i;
end generate GEN_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC_ONOFF
-- Purpose: No ECC on/off control register.
---------------------------------------------------------------------------
GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate
begin
Enable_ECC <= '0';
-- ECC ON/OFF register is only enabled when C_ECC = 1.
-- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then
-- ECC should be disabled.
ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0';
end generate GEN_NO_ECC_ONOFF;
---------------------------------------------------------------------------
-- Generate: CE_COUNTER
-- Purpose: Enable Correctable Error Counter
-- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits.
-- Parameterized here for future enhancements.
---------------------------------------------------------------------------
CE_COUNTER : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0';
-- TBD (could come from axi_lite)
-- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and
-- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
-- else '0';
CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0')
else '0';
CountReg : process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
CE_CounterReg <= (others => '0');
elsif CE_CounterReg_WE = '1' then
-- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1);
CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31);
elsif CE_CounterReg_Inc_i = '1' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_COUNTER;
-- Note: Hit this generate when C_ECC = 0.
-- Reserve for future support.
--
-- ---------------------------------------------------------------------------
-- -- Generate: NO_CE_COUNTER
-- -- Purpose: Default for no CE counter register.
-- ---------------------------------------------------------------------------
--
-- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate
-- begin
-- CE_CounterReg <= (others => '0');
-- end generate NO_CE_COUNTER;
---------------------------------------------------------------------------
-- Generate: GEN_REG_32_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 32-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_32_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_64_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 64-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_64_DATA;
---------------------------------------------------------------------------
-- Generate: GEN_REG_128_DATA
-- Purpose: Generate read register values & signal assignments based on
-- 128-bit BRAM data width.
---------------------------------------------------------------------------
GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate
begin
SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg,
CE_CounterReg, CE_FailingAddress,
FaultInjectData_i,
FaultInjectECC_i
-- CE_FailingData, CE_FailingECC,
-- UE_FailingAddress, UE_FailingData, UE_FailingECC
)
begin
RegRdData <= (others => '0');
case RegAddr is
-- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31);
when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- Temporary addition to readback fault inject register values
when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31);
when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63);
when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95);
when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127);
when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1);
-- Note: For future enhancement.
-- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127);
-- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95);
-- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63);
-- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31);
-- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
-- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31);
-- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0');
-- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127);
-- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95);
-- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63);
-- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31);
-- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
end generate GEN_REG_128_DATA;
---------------------------------------------------------------------------
end architecture implementation;
|
gpl-3.0
|
nickg/nvc
|
test/lower/vunit1.vhd
|
1
|
2534
|
package string_ptr_pkg is
subtype index_t is integer range -1 to integer'high;
subtype byte_t is integer range 0 to 255;
type storage_mode_t is (internal, extfnc, extacc);
type string_access_t is access string;
type string_access_vector_t is array (natural range <>) of string_access_t;
type string_access_vector_access_t is access string_access_vector_t;
type extstring_access_t is access string(1 to integer'high);
type extstring_access_vector_t is array (natural range <>) of extstring_access_t;
type extstring_access_vector_access_t is access extstring_access_vector_t;
type string_ptr_t is record
ref : index_t;
end record;
constant null_string_ptr : string_ptr_t := (ref => -1);
alias ptr_t is string_ptr_t;
alias val_t is character;
alias vec_t is string;
alias vav_t is string_access_vector_t;
alias evav_t is extstring_access_vector_t;
alias vava_t is string_access_vector_access_t;
alias evava_t is extstring_access_vector_access_t;
procedure set (
ptr : ptr_t;
index : positive;
value : val_t
);
end package;
package body string_ptr_pkg is
type prot_storage_t is protected
procedure set (
ref : natural;
index : positive;
value : val_t
);
end protected;
type prot_storage_t is protected body
type storage_t is record
id : integer;
mode : storage_mode_t;
length : integer;
end record;
constant null_storage : storage_t := (integer'low, internal, integer'low);
type storage_vector_t is array (natural range <>) of storage_t;
type storage_vector_access_t is access storage_vector_t;
type ptr_storage is record
idx : natural;
ptr : natural;
eptr : natural;
idxs : storage_vector_access_t;
ptrs : vava_t;
eptrs : evava_t;
end record;
variable st : ptr_storage := (0, 0, 0, null, null, null);
procedure set (
ref : natural;
index : positive;
value : val_t
) is
variable s : storage_t := st.idxs(ref);
begin
case s.mode is
when extfnc => null;--write_char(s.id, index-1, value);
when extacc => st.eptrs(s.id)(index) := value;
when internal => st.ptrs(s.id)(index) := value;
end case;
end;
end protected body;
shared variable vec_ptr_storage : prot_storage_t;
procedure set (
ptr : ptr_t;
index : positive;
value : val_t
) is begin
vec_ptr_storage.set(ptr.ref, index, value);
end;
end package body;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd
|
32
|
49938
|
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/regress/func20.vhd
|
1
|
439
|
entity func20 is
end entity;
architecture test of func20 is
impure function outer return string is
variable s : string(1 to 5);
impure function inner return string is
begin
return s;
end function;
begin
s := "hello";
return inner;
end function;
begin
p1: process is
begin
assert outer = "hello";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/lower/issue94.vhd
|
5
|
487
|
entity issue94 is
end entity;
architecture test of issue94 is
function func (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1'); -- Error with LLVM asserts build
return y_temp(0);
end func;
begin
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/sem/issue246.vhd
|
2
|
134
|
package pkg is
subtype s is integer (0 to 10); -- error
subtype ss is string range 2 to 5; -- error
end package pkg;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/utt.fr/doimgproc_v1_0/hdl/vhdl/doImgProc_KERNEL_BUS_s_axi.vhd
|
4
|
14313
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity doImgProc_KERNEL_BUS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
kernel_address0 :in STD_LOGIC_VECTOR(3 downto 0);
kernel_ce0 :in STD_LOGIC;
kernel_q0 :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity doImgProc_KERNEL_BUS_s_axi;
-- ------------------------Address Info-------------------
-- 0x10 ~
-- 0x1f : Memory 'kernel' (3 * 8b)
-- Word n : bit [ 7: 0] - kernel[4n]
-- bit [15: 8] - kernel[4n+1]
-- bit [23:16] - kernel[4n+2]
-- bit [31:24] - kernel[4n+3]
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of doImgProc_KERNEL_BUS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_KERNEL_BASE : INTEGER := 16#10#;
constant ADDR_KERNEL_HIGH : INTEGER := 16#1f#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- memory signals
signal int_kernel_address0 : UNSIGNED(1 downto 0);
signal int_kernel_ce0 : STD_LOGIC;
signal int_kernel_we0 : STD_LOGIC;
signal int_kernel_be0 : UNSIGNED(3 downto 0);
signal int_kernel_d0 : UNSIGNED(31 downto 0);
signal int_kernel_q0 : UNSIGNED(31 downto 0);
signal int_kernel_address1 : UNSIGNED(1 downto 0);
signal int_kernel_ce1 : STD_LOGIC;
signal int_kernel_we1 : STD_LOGIC;
signal int_kernel_be1 : UNSIGNED(3 downto 0);
signal int_kernel_d1 : UNSIGNED(31 downto 0);
signal int_kernel_q1 : UNSIGNED(31 downto 0);
signal int_kernel_read : STD_LOGIC;
signal int_kernel_write : STD_LOGIC;
signal int_kernel_shift : UNSIGNED(1 downto 0);
component doImgProc_KERNEL_BUS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end component doImgProc_KERNEL_BUS_s_axi_ram;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 1;
m := 2;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
begin
-- ----------------------- Instantiation------------------
-- int_kernel
int_kernel : doImgProc_KERNEL_BUS_s_axi_ram
generic map (
BYTES => 4,
DEPTH => 3,
AWIDTH => log2(3))
port map (
clk0 => ACLK,
address0 => int_kernel_address0,
ce0 => int_kernel_ce0,
we0 => int_kernel_we0,
be0 => int_kernel_be0,
d0 => int_kernel_d0,
q0 => int_kernel_q0,
clk1 => ACLK,
address1 => int_kernel_address1,
ce1 => int_kernel_ce1,
we1 => int_kernel_we1,
be1 => int_kernel_be1,
d1 => int_kernel_d1,
q1 => int_kernel_q1);
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) and (int_kernel_read = '0') else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
elsif (int_kernel_read = '1') then
rdata_data <= int_kernel_q1;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
-- ----------------------- Memory logic ------------------
-- kernel
int_kernel_address0 <= SHIFT_RIGHT(UNSIGNED(kernel_address0), 2)(1 downto 0);
int_kernel_ce0 <= kernel_ce0;
int_kernel_we0 <= '0';
int_kernel_be0 <= (others => '0');
int_kernel_d0 <= (others => '0');
kernel_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_kernel_q0, TO_INTEGER(int_kernel_shift) * 8)(7 downto 0));
int_kernel_address1 <= raddr(3 downto 2) when ar_hs = '1' else waddr(3 downto 2);
int_kernel_ce1 <= '1' when ar_hs = '1' or (int_kernel_write = '1' and WVALID = '1') else '0';
int_kernel_we1 <= '1' when int_kernel_write = '1' and WVALID = '1' else '0';
int_kernel_be1 <= UNSIGNED(WSTRB);
int_kernel_d1 <= UNSIGNED(WDATA);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_kernel_read <= '0';
elsif (ACLK_EN = '1') then
if (ar_hs = '1' and raddr >= ADDR_KERNEL_BASE and raddr <= ADDR_KERNEL_HIGH) then
int_kernel_read <= '1';
else
int_kernel_read <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_kernel_write <= '0';
elsif (ACLK_EN = '1') then
if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_KERNEL_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_KERNEL_HIGH) then
int_kernel_write <= '1';
elsif (WVALID = '1') then
int_kernel_write <= '0';
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (kernel_ce0 = '1') then
int_kernel_shift <= UNSIGNED(kernel_address0(1 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity doImgProc_KERNEL_BUS_s_axi_ram is
generic (
BYTES : INTEGER :=4;
DEPTH : INTEGER :=256;
AWIDTH : INTEGER :=8);
port (
clk0 : in STD_LOGIC;
address0: in UNSIGNED(AWIDTH-1 downto 0);
ce0 : in STD_LOGIC;
we0 : in STD_LOGIC;
be0 : in UNSIGNED(BYTES-1 downto 0);
d0 : in UNSIGNED(BYTES*8-1 downto 0);
q0 : out UNSIGNED(BYTES*8-1 downto 0);
clk1 : in STD_LOGIC;
address1: in UNSIGNED(AWIDTH-1 downto 0);
ce1 : in STD_LOGIC;
we1 : in STD_LOGIC;
be1 : in UNSIGNED(BYTES-1 downto 0);
d1 : in UNSIGNED(BYTES*8-1 downto 0);
q1 : out UNSIGNED(BYTES*8-1 downto 0));
end entity doImgProc_KERNEL_BUS_s_axi_ram;
architecture behave of doImgProc_KERNEL_BUS_s_axi_ram is
signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0);
signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0);
type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0);
shared variable mem : RAM_T := (others => (others => '0'));
begin
process (address0)
begin
address0_tmp <= address0;
--synthesis translate_off
if (address0 > DEPTH-1) then
address0_tmp <= (others => '0');
else
address0_tmp <= address0;
end if;
--synthesis translate_on
end process;
process (address1)
begin
address1_tmp <= address1;
--synthesis translate_off
if (address1 > DEPTH-1) then
address1_tmp <= (others => '0');
else
address1_tmp <= address1;
end if;
--synthesis translate_on
end process;
--read port 0
process (clk0) begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1') then
q0 <= mem(to_integer(address0_tmp));
end if;
end if;
end process;
--read port 1
process (clk1) begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1') then
q1 <= mem(to_integer(address1_tmp));
end if;
end if;
end process;
gen_write : for i in 0 to BYTES - 1 generate
begin
--write port 0
process (clk0)
begin
if (clk0'event and clk0 = '1') then
if (ce0 = '1' and we0 = '1' and be0(i) = '1') then
mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i);
end if;
end if;
end process;
--write port 1
process (clk1)
begin
if (clk1'event and clk1 = '1') then
if (ce1 = '1' and we1 = '1' and be1(i) = '1') then
mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i);
end if;
end if;
end process;
end generate;
end architecture behave;
|
gpl-3.0
|
nickg/nvc
|
test/sem/issue128.vhd
|
5
|
400
|
package A_NG is
procedure PROC(SEL: in integer);
end package;
package body A_NG is
procedure PROC(SEL: in integer) is
begin
case SEL is
when 0 | 1 => -- Used to crash in sem_hoist_for_loop_var
for i in 0 to 3 loop
end loop;
when others =>
null;
end case;
end procedure;
end package body;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fdiv_14_no_dsp_32/xbip_dsp48_multadd_v3_0_2/hdl/xbip_dsp48_multadd_v3_0.vhd
|
9
|
10163
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
RRooMx8aKXOKuw0jba9AAvNqcv1aOAWx0dmOeAMZtfEA8NEQBycfD1he5bNQ520rjDcafpEIYoFH
8wShwJiQKg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
RgXfz+8mp1qbBTyetHH5ngynBLMwZxu0rxkXLh6QHG9XAy4+BbRKOjz1+c6cH6NYhRRfM4vT5Wl9
ixg8Rc8Yc/S242b09BUNorP5ATo1wne5IxcZ3jC1T4BUzl0tgUScvpD0uFueK3/IMnEjC4aKr60w
VKR6qyW4sq2X954pF24=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oSpqzFUI/f1Ucw6UHNSsuY41hVH/I8MTwUZaCMUrE6zrelZVctDl9yufZENXxn0WT1Yem6/W+w1g
j5QeVJm+5hjC0WIxLupVJMkqfzQw8dGHJPDGoEaTB2RcDqLTnI9CrpQ+iJb7hrQn6dDmxZImAuMq
3pJVs+aaFHAeNuzZZhE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
X4Fi+a1OzUk68cyxZUSzfNpLCwkSC0wmt8tY0kB574VuReti34LgiOkcPXhGDj4gSUKkUF4A/Yda
WDzaAnabrJ3zv3CWcxwC2pPrD1rNotHPICUvwJpTTNzK8oCLdrgMtygrsL5CwXaOVNz1a++BWa6C
QlArFRdlccowSRhXDf5tSyKNSLiV9tJxHNvWPzIowxyUtoVMdFV+wv3UhZXGP74OmYsEJ9ESIEXz
q0P+Tc5gairxuvjskvUVpqbsNEBOq90+NKAEaLtPOQ6vY8kzp+eWm8uf5f3kgAZZsAiQGswk7vU2
f5LaUSeubviPjfs+8uQjBW2DPBwJbScjsXNcQA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Ro6yqNSieyMPHHxOuV5fgYIFX1ue1fCOQaUrsWRJcJVYR01otjGNBK1LpULF9osLOrFWk4AtTJqV
rWcIGuQTGE8iRA3XlZBfUPo5Auyp6hG2JT2LLT/s9g6oUGrueNakH+McXpdG6aUJkgH9/eoBjrLX
DrPrHqq40IlnSppHpDAOq11fRkZk9TkYdWeakR7Tqj5fMix/Hves5J2MNw7M+0/bs9k7crMC3AB4
hiMav0upztwGMWPFQOTJLcPJQ9Jmlip35nCdHQRH+L1Pz5yPl599XvkZh7InTkLreIaRmIpZaIPJ
dSX841g9ZA3G2q8OiDyHBCZOsKYNN4/R2I8Cjw==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
K8DR1xFh8LdLJFzLYbjbQJHVBapMV/A5ef8aS1igRTqWTzaxTp8rcNFvJmLeb2FVSABbW9ENq0z2
4PAQuZAFntoQZCy0B96/GhJqiwWNdo9SkQAXHie4qn1yl5LCT837iglxkr5T9u9hdW/y32580N70
9mwvaao2qtKVUj2WO7a8JbZTzIZj2kxqfrfxG+wf2zMcUTQ1XZCsGULlRMnDM7exK4fGQxqbrLsN
3z3GB/1h4CYvFQCvVlD3CURFCtPUP/5toS0Ja6ccVb6/3q73spZWxAHrzIuZDq1YEczGdzSMR+k6
s98cQiYspIArx3y1cvwLR27cpPujPAWuCP8Wyw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5392)
`protect data_block
qSsiLyvJuChi2E0XpHgqvrKS1epB0U4feczmHFW/2YJen2AC64LL92z2ukfDjg3+ewU/xhyTUUya
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HTFvV+R2C9y94QNdnXt3ULowPaCPP+UFGS+pmbwSndIZZVvY1YtXj5Jjmy2mk3gUvM8n9yi1qGBr
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BrHclMY3jxuLtQQXGPI+JmM06pBOpuwUDSk9q7YIXG3PiCYT62yhy5a2UhMooDOhmUKCz0ZfOjPr
O1GxGPzufCnOLGn4nSrWIpyzpf34hSjpZQ2Icbds85xRaDryyubxrtiGnDdbqZHt5XijCOTQAefw
YYCgq3QY/rsFV9rf0eWFKCC2bdh9lmbBCmctAwtdPzPWI+N0w81Z9KT9rIXdATwRlTDamU3oqIWX
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CX17uXVuDrJFN/sBwKh8Bb3vsVQgr+NrPRTSxXbAPCROkv6Vzd3wwS0XnLmb/fm4+vMTBCzf2b0J
ddMzpezmquaHLmDpABxff5buJ3AiWv605St1jkqB6kV5ExtY34Yph27LbiLy9ba7yvSEUNy2+VTG
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QkU0zdVOPyK4WYLR/CcdCjO7A8gpTvlC+9+7S5zLJXrKCumhur5hX1BDwX8AsjkTTIKKEtR1KP1m
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2/RKBOvRpBwI6dAeuGVaUF0C+Mw4R7tihE+seFhdmQccQNMcTpHDwISSBbYl/+OIky3FPJF6Ub8W
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vpR8p/YJn+LSOKay5eBqO8UFp3RCioCmYSJ8cJfrweN3DQsyvbrFczBIa+6lbzHUBdBbwO6wsDMb
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C633DjUAmiZv8IliA9bZo8Kjr1J/IjBxODREFUctkztPUqpGOKwHOfbWLiNwPWmkud/SHwHZchy1
LxSzI6Ue7QZkMTlt/73tZ7AV+U/oq7n8vh6Q2nY83bgDWY/WumtsLOWAvTEiNQYxdnYEt3xh26Vj
2sFk+l0pDX8NXTkxZD3S6QtRHARAJyi2jb6QwXOOIvCvLIerZ8Y4PbN4LSiPxXzJyIs2fhdruswn
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0humU+qYNKGislj3803oXBRhWn5iBr6Q7/yZCsqGFLVcZABG900Lj8omc91BSAdRGfnT1onQ7JdE
5fafOSNvqyJha18FDq+KpA5dyOs/nvX3IbwSe0k2wAEtX541MYcD5jEbQnH0fgKedfDBzwb6yqFL
jh7bYtThZWi5/sukIp83mr5VxY0aa2w2wCjvnf4exUmbjUFXZmEoLi27EWCFgOH6jjTnjNr+rBIm
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b3gwVi5ir5x62CYoVwgZkqK67fbiWW9zvTQiE7mn7t3P+G/mcjFKkxsKAJ2zhW4xAz06TJC+S3Ce
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ff+hhRYhJPbXAkqj+Y75aVtOdPk2ZfElDIYGPSJj2nGh3ohs1R8IhRd5N+A+cQ4QmxEIdCCBPowR
BF7zxaTsul42PrfEpIgEwK5fk1W+ubyI/S7y3SCRWgeO7UBucI+QD00S29+pXDuyt3+1goYU53lH
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jbmMBdkuqSwNvw+c0RX7x8jJZY6KTGyyQyICEAK/h7k6e5g7umAk3APVKHnMKIz7DOLojgSpvbDO
ALjGDA3vfztum1DJvVwhf5sirhya54VqWBoKjeWArZXzztB2wau3jWB7Zz3tf6ZfO71Ev9IL5N/6
NvRxx6xZKP06vXdHrWbwV7/kOY1jCVnG0yCpLdwv4nsBUyFCSl0n0pRXJvex+1EZDX1lRgWcYaMa
jzEc4aNoP9V2jhmvfbHdCXReRfily3bGWBuhh0JMaW5woAAbH0C3qBKGi6hYA43vCYXvTBezb1Hv
zJitLFLjND6nJx5RuXgY0M7wYI/d8SNDuq9/01sTgPY5rTwotDE9rTx8VtPk7BKBl/1Ctow1WfQv
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a5CSaqQhyVYD6AdBYmgSc1MsFb7U3xVCb36+8yFhSgkdYg==
`protect end_protected
|
gpl-3.0
|
nickg/nvc
|
test/lower/directmap.vhd
|
1
|
642
|
entity bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity directmap is
end entity;
architecture test of directmap is
signal x, y : integer;
begin
uut: entity work.bot
port map ( x, y );
process is
begin
x <= 0;
wait for 1 ns;
assert y = 1;
x <= 2;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/record16.vhd
|
1
|
678
|
entity record16 is
end entity;
architecture test of record16 is
type rec is record
x : bit;
y : integer;
end record;
signal r : rec := ('1', 0);
procedure drive(signal s : out integer; value : in integer) is
begin
s <= value;
end procedure;
procedure read(signal s : in integer; value : out integer) is
begin
value := s;
end procedure;
begin
process is
variable x : integer;
begin
drive(r.y, 123);
wait for 1 ns;
assert r.y = 123;
read(r.y, x);
--report integer'image(x);
--assert x = 123;
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/bounds/issue99.vhd
|
5
|
321
|
entity Top_PhysicalTest_Simple is
end entity;
architecture top of Top_PhysicalTest_Simple is
type my_int is range 1 to 5;
constant int_1 : INTEGER := natural(0.5); -- OK
constant int_2 : INTEGER := natural(-1.5); -- Error
constant int_3 : my_int := my_int(integer'(-1)); -- Error
begin
end;
|
gpl-3.0
|
nickg/nvc
|
test/regress/signal26.vhd
|
1
|
583
|
entity signal26 is
end entity;
architecture test of signal26 is
function func (x : integer) return integer is
begin
return x / 2;
end function;
constant w : integer := 4;
type rec is record
f : bit_vector(func(w) - 1 downto 0);
end record;
signal v : bit_vector(w - 1 downto 0);
signal r : rec;
begin
v(w-1 downto r.f'left + 1) <= (others => '1');
v(r.f'left downto 0) <= (others => '0');
check: process is
begin
wait for 1 ns;
assert v = "1100";
wait;
end process;
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/parse/visibility2.vhd
|
1
|
371
|
package pack1 is
procedure p (x : integer);
end package;
-------------------------------------------------------------------------------
use work.pack1.all;
package pack2 is
procedure p (y : integer); -- OK, hides pack1.p
end package;
package body pack2 is
procedure p (y : integer) is -- OK
begin
end procedure;
end package body;
|
gpl-3.0
|
nickg/nvc
|
test/elab/ifgen.vhd
|
5
|
472
|
entity sub is
generic (
foo : boolean := true );
port (
x : out integer );
end entity;
architecture test of sub is
begin
g: if foo = true generate
x <= 5;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity ifgen is
end entity;
architecture test of ifgen is
signal x : integer;
begin
sub_i: entity work.sub
port map ( x );
end architecture;
|
gpl-3.0
|
nickg/nvc
|
test/regress/case7.vhd
|
2
|
867
|
entity case7 is
end entity;
architecture test of case7 is
constant C1 : bit_vector(3 downto 0) := X"1";
constant C2 : bit_vector(3 downto 0) := X"2";
signal x : bit_vector(7 downto 0);
signal y : integer;
begin
process (x) is
begin
case x is
when C1 & X"0" =>
y <= 5;
when C1 & X"8" =>
y <= 6;
when C2 & X"0" =>
y <= 10;
when others =>
y <= 0;
end case;
end process;
process is
begin
x <= X"10";
wait for 1 ns;
assert y = 5;
x <= X"18";
wait for 1 ns;
assert y = 6;
x <= X"20";
wait for 1 ns;
assert y = 10;
x <= X"21";
wait for 1 ns;
assert y = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
pleonex/Efponga
|
Pong/marcador.vhd
|
1
|
2993
|
LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY marcador IS
PORT (
numero : IN UNSIGNED(3 DOWNTO 0);
hex0 : OUT STD_LOGIC;
hex1 : OUT STD_LOGIC;
hex2 : OUT STD_LOGIC;
hex3 : OUT STD_LOGIC;
hex4 : OUT STD_LOGIC;
hex5 : OUT STD_LOGIC;
hex6 : OUT STD_LOGIC
);
END marcador;
ARCHITECTURE funcional OF marcador IS
BEGIN
PROCESS (numero)
BEGIN
CASE numero IS
WHEN x"0" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '1';
WHEN x"1" =>
hex0 <= '1';
hex1 <= '0';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '1';
hex6 <= '1';
WHEN x"2" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '1';
hex3 <= '0';
hex4 <= '0';
hex5 <= '1';
hex6 <= '0';
WHEN x"3" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '1';
hex5 <= '1';
hex6 <= '0';
WHEN x"4" =>
hex0 <= '0';
hex1 <= '1';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '0';
hex6 <= '0';
WHEN x"5" =>
hex0 <= '0';
hex1 <= '1';
hex2 <= '0';
hex3 <= '0';
hex4 <= '1';
hex5 <= '0';
hex6 <= '0';
WHEN x"6" =>
hex0 <= '0';
hex1 <= '1';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '0';
WHEN x"7" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '0';
hex6 <= '1';
WHEN x"8" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '0';
WHEN x"9" =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '1';
hex4 <= '1';
hex5 <= '0';
hex6 <= '0';
WHEN OTHERS =>
hex0 <= '0';
hex1 <= '0';
hex2 <= '0';
hex3 <= '0';
hex4 <= '0';
hex5 <= '0';
hex6 <= '0';
END CASE;
END process;
END funcional;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue45.vhd
|
5
|
291
|
entity issue45 is
begin
end entity issue45;
architecture a of issue45 is
begin
b: block is
begin
p : process
begin
report p'instance_name;
report b'instance_name;
wait;
end process p;
end block;
end architecture a;
|
gpl-3.0
|
nickg/nvc
|
test/parse/literal.vhd
|
1
|
1277
|
-- -*- coding: latin-1 -*-
entity ee is
end entity;
ARCHITECTURE aa OF ee IS
SIGNAL pos : INTEGER := 64;
SIGNAL neg : INTEGER := -265;
CONSTANT c : INTEGER := 523;
CONSTANT a : STRING := "hel""lo";
CONSTANT b : STRING := """quote""";
CONSTANT d : INTEGER := 1E3; -- Integer not real
CONSTANT e : REAL := 1.234;
CONSTANT f : REAL := 0.21712;
CONSTANT g : REAL := 1.4e6;
CONSTANT h : REAL := 235.1e-2;
CONSTANT i : INTEGER := 1_2_3_4;
CONSTANT j : REAL := 5_6_7.12_3;
type ptr is access integer;
shared variable k : ptr := NULL;
CONSTANT l : STRING := "Setup time is too short";
CONSTANT m : STRING := "";
CONSTANT n : STRING := " ";
CONSTANT o : STRING := "A";
CONSTANT p : STRING := """";
CONSTANT q : STRING := %Setup time is too short%;
CONSTANT r : STRING := %%;
CONSTANT s : STRING := % %;
CONSTANT t : STRING := %A%;
CONSTANT u : STRING := %%%%;
constant v : string := "©";
subtype lowercase is character range 'a' to 'z';
type my_string is array (lowercase range <>) of character;
constant w : my_string := "hello";
constant too_big : integer := 9223372036854775808; -- Error
constant way_too_big : integer := 235423414124e124124; -- Error
BEGIN
END ARCHITECTURE;
|
gpl-3.0
|
nickg/nvc
|
test/regress/issue293.vhd
|
2
|
348
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.math_real.all;
entity issue293 is
end issue293;
architecture behv of issue293 is
constant AWIDTH : natural := integer(ceil(log2(real(4))));
signal a : std_logic_vector (AWIDTH downto 0);
begin
process is
begin
assert a'left = 2;
wait;
end process;
end behv;
|
gpl-3.0
|
nickg/nvc
|
test/parse/func.vhd
|
1
|
335
|
package func is
function add(x, y : integer; z : in integer) return integer;
impure function naughty return integer;
function "+"(x, y : integer) return integer;
end package;
package body func is
function "+"(x, y : integer) return integer is
begin
return 42;
end function "+";
end package body;
|
gpl-3.0
|
Darkin47/Zynq-TX-UTT
|
Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_mngr.vhd
|
3
|
51651
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1_9.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1_9.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1_9.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1_9.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1_9.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1_9.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1_9.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
gpl-3.0
|
nickg/nvc
|
test/bounds/issue208.vhd
|
5
|
711
|
entity test is
end test;
architecture fum of test is
signal foo : bit_vector(1 downto 0);
alias foo1 is foo(1);
alias foo0 is foo(0);
begin
dummy:
process is
begin
for i in foo'range loop -- range is 1 downto 0
case i is -- OK
when 0 =>
report "foo(0) = " & bit'image(foo0);
when 1 =>
report "foo(1) = " & bit'image(foo1);
end case;
case i is -- Error
when 0 =>
report "foo(0) = " & bit'image(foo0);
end case;
end loop;
wait;
end process dummy;
end architecture fum;
|
gpl-3.0
|
nickg/nvc
|
lib/ieee/math_complex-body.vhdl
|
3
|
52648
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_COMPLEX package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common COMPLEX
-- : constants and common COMPLEX mathematical functions and
-- : operators.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
use WORK.MATH_REAL.all;
package body MATH_COMPLEX is
--
-- Equality and Inequality Operators for COMPLEX_POLAR
--
function "=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in =(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return TRUE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return TRUE;
end if;
return FALSE;
end function "=";
function "/=" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR ) return BOOLEAN
is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns FALSE on error
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /=(L,R)"
severity ERROR;
return FALSE;
end if;
-- Get special values
if ( L.MAG = 0.0 and R.MAG = 0.0 ) then
return FALSE;
end if;
-- Get value for general case
if ( L.MAG = R.MAG and L.ARG = R.ARG ) then
return FALSE;
end if;
return TRUE;
end function "/=";
--
-- Other Functions Start Here
--
function CMPLX(X: in REAL; Y: in REAL := 0.0 ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(X, Y);
end function CMPLX;
function GET_PRINCIPAL_VALUE(X: in REAL ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Check if already a principal value
if ( X > -MATH_PI and X <= MATH_PI ) then
return PRINCIPAL_VALUE'(X);
end if;
-- Get principal value
TEMP := X;
while ( TEMP <= -MATH_PI ) loop
TEMP := TEMP + MATH_2_PI;
end loop;
while (TEMP > MATH_PI ) loop
TEMP := TEMP - MATH_2_PI;
end loop;
return PRINCIPAL_VALUE'(TEMP);
end function GET_PRINCIPAL_VALUE;
function COMPLEX_TO_POLAR(Z: in COMPLEX ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.IM > 0.0 ) then
return COMPLEX_POLAR'(Z.IM, MATH_PI_OVER_2);
else
return COMPLEX_POLAR'(-Z.IM, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
elsif ( Z.RE > 0.0 ) then
return COMPLEX_POLAR'(Z.RE, 0.0);
else
return COMPLEX_POLAR'(-Z.RE, MATH_PI);
end if;
end if;
-- Get principal value for general case
TEMP := ARCTAN(Z.IM, Z.RE);
return COMPLEX_POLAR'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM),
GET_PRINCIPAL_VALUE(TEMP));
end function COMPLEX_TO_POLAR;
function POLAR_TO_COMPLEX(Z: in COMPLEX_POLAR ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns MATH_CZERO on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in POLAR_TO_COMPLEX(Z)"
severity ERROR;
return MATH_CZERO;
end if;
-- Get value for general case
return COMPLEX'( Z.MAG*COS(Z.ARG), Z.MAG*SIN(Z.ARG) );
end function POLAR_TO_COMPLEX;
function "ABS"(Z: in COMPLEX ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = SQRT(Z.RE*Z.RE + Z.IM*Z.IM)
begin
-- Get value for general case
return POSITIVE_REAL'(SQRT(Z.RE*Z.RE + Z.IM*Z.IM));
end function "ABS";
function "ABS"(Z: in COMPLEX_POLAR ) return POSITIVE_REAL is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ABS(Z) = Z.MAG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ABS(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.MAG;
end function "ABS";
function ARG(Z: in COMPLEX ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = ARCTAN(Z.IM, Z.RE)
variable ZTEMP : COMPLEX_POLAR;
begin
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
return ZTEMP.ARG;
end function ARG;
function ARG(Z: in COMPLEX_POLAR ) return PRINCIPAL_VALUE is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) ARG(Z) = Z.ARG
-- b) Returns 0.0 on error
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in ARG(Z)"
severity ERROR;
return 0.0;
end if;
-- Get value for general case
return Z.ARG;
end function ARG;
function "-" (Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns -x -jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(-Z.RE, -Z.IM);
end function "-";
function "-" (Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns (Z.MAG, Z.ARG + MATH_PI)
-- b) Returns Z on error
variable TEMP: REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in -(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
TEMP := REAL'(Z.ARG) + MATH_PI;
return COMPLEX_POLAR'(Z.MAG, GET_PRINCIPAL_VALUE(TEMP));
end function "-";
function CONJ (Z: in COMPLEX) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns x - jy for Z = x + jy
begin
-- Get value for general case
return COMPLEX'(Z.RE, -Z.IM);
end function CONJ;
function CONJ (Z: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX conjugate (Z.MAG, -Z.ARG)
-- b) Returns Z on error
--
variable TEMP: PRINCIPAL_VALUE;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in CONJ(Z)"
severity ERROR;
return Z;
end if;
-- Get principal value for general case
if ( Z.ARG = MATH_PI or Z.ARG = 0.0 ) then
TEMP := Z.ARG;
else
TEMP := -Z.ARG;
end if;
return COMPLEX_POLAR'(Z.MAG, TEMP);
end function CONJ;
function SQRT(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable ZTEMP : COMPLEX_POLAR;
variable ZOUT : COMPLEX;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CZERO;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TMAG := SQRT(ZTEMP.MAG);
TARG := 0.5*ZTEMP.ARG;
if ( COS(TARG) > 0.0 ) then
ZOUT.RE := TMAG*COS(TARG);
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
if ( COS(TARG) < 0.0 ) then
ZOUT.RE := TMAG*COS(TARG + MATH_PI);
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end if;
if ( SIN(TARG) > 0.0 ) then
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG);
return ZOUT;
end if;
ZOUT.RE := 0.0;
ZOUT.IM := TMAG*SIN(TARG + MATH_PI);
return ZOUT;
end function SQRT;
function SQRT(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZOUT : COMPLEX_POLAR;
variable TMAG : REAL;
variable TARG : REAL;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SQRT(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return Z;
end if;
-- Get principal value for general case
TMAG := SQRT(Z.MAG);
TARG := 0.5*Z.ARG;
ZOUT.MAG := POSITIVE_REAL'(TMAG);
if ( COS(TARG) < 0.0 ) then
TARG := TARG + MATH_PI;
end if;
if ( (COS(TARG) = 0.0) and (SIN(TARG) < 0.0) ) then
TARG := TARG + MATH_PI;
end if;
ZOUT.ARG := GET_PRINCIPAL_VALUE(TARG);
return ZOUT;
end function SQRT;
function EXP(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
variable TEMP: REAL;
begin
-- Get value for special cases
if ( Z = MATH_CZERO ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 0.0 ) then
if ( Z.IM = MATH_PI or Z.IM = -MATH_PI ) then
return COMPLEX'(-1.0, 0.0);
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return COMPLEX'(0.0, -1.0);
end if;
end if;
-- Get value for general case
TEMP := EXP(Z.RE);
return COMPLEX'(TEMP*COS(Z.IM), TEMP*SIN(Z.IM));
end function EXP;
function EXP(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns Z on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in EXP(Z)"
severity ERROR;
return Z;
end if;
-- Get value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and (Z.ARG = MATH_PI_OVER_2 or
Z.ARG = -MATH_PI_OVER_2 )) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 ) then
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get principal value for general case
ZTEMP := POLAR_TO_COMPLEX(Z);
ZOUT.MAG := POSITIVE_REAL'(EXP(ZTEMP.RE));
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZTEMP.IM);
return ZOUT;
end function EXP;
function LOG(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = -1.0 ) then
return COMPLEX'(0.0, MATH_PI);
end if;
if ( Z.RE = MATH_E ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
if ( Z.RE = 0.0 ) then
if (Z.IM = 1.0) then
return COMPLEX'(0.0, MATH_PI_OVER_2);
end if;
if (Z.IM = -1.0) then
return COMPLEX'(0.0, -MATH_PI_OVER_2);
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, ZTEMP.ARG);
end function LOG;
function LOG2(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 2.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG2_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG2_OF_E*ZTEMP.ARG);
end function LOG2;
function LOG10(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMP : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 10.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMP := MATH_LOG10_OF_E*LOG(ZTEMP.MAG);
return COMPLEX'(TEMP, MATH_LOG10_OF_E*ZTEMP.ARG);
end function LOG10;
function LOG(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 ) then
if ( Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(MATH_PI, MATH_PI_OVER_2);
end if;
if ( Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, MATH_PI_OVER_2);
end if;
if ( Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(MATH_PI_OVER_2, -MATH_PI_OVER_2);
end if;
end if;
if ( Z.MAG = MATH_E and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG);
ZTEMP.IM := Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function LOG2(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG2(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 2.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG2_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG2_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG2;
function LOG10(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG10(Z)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = 10.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := MATH_LOG10_OF_E*LOG(Z.MAG);
ZTEMP.IM := MATH_LOG10_OF_E*Z.ARG;
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG10;
function LOG(Z: in COMPLEX; BASE: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'LOW, 0.0) on error
variable ZTEMP : COMPLEX_POLAR;
variable TEMPRE : REAL;
variable TEMPIM : REAL;
begin
-- Check validity of input arguments
if ( Z.RE = 0.0 and Z.IM = 0.0 ) then
assert FALSE
report "Z.RE = 0.0 and Z.IM = 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX'(REAL'LOW, 0.0);
end if;
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = BASE ) then
return MATH_CBASE_1;
end if;
if ( Z.RE = 1.0 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
ZTEMP := COMPLEX_TO_POLAR(Z);
TEMPRE := LOG(ZTEMP.MAG, BASE);
TEMPIM := ZTEMP.ARG/LOG(BASE);
return COMPLEX'(TEMPRE, TEMPIM);
end function LOG;
function LOG(Z: in COMPLEX_POLAR; BASE: in REAL ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(REAL'HIGH, MATH_PI) on error
variable ZTEMP : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.MAG <= 0.0 ) then
assert FALSE
report "Z.MAG <= 0.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( BASE <= 0.0 or BASE = 1.0 ) then
assert FALSE
report "BASE <= 0.0 or BASE = 1.0 in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in LOG(Z,BASE)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, MATH_PI);
end if;
-- Compute value for special cases
if (Z.MAG = 1.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = BASE and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
-- Compute value for general case
ZTEMP.RE := LOG(Z.MAG, BASE);
ZTEMP.IM := Z.ARG/LOG(BASE);
ZOUT := COMPLEX_TO_POLAR(ZTEMP);
return ZOUT;
end function LOG;
function SIN(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = 0.0 or Z.RE = MATH_PI) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(SIN(Z.RE)*COSH(Z.IM), COS(Z.RE)*SINH(Z.IM));
end function SIN;
function SIN(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SIN(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SIN(Z1.RE)*COSH(Z1.IM), COS(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SIN;
function COS(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.IM = 0.0 ) then
if ( Z.RE = MATH_PI_OVER_2 or Z.RE = -MATH_PI_OVER_2) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COS(Z.RE)*COSH(Z.IM), -SIN(Z.RE)*SINH(Z.IM));
end function COS;
function COS(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COS(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COS(Z1.RE)*COSH(Z1.IM), -SIN(Z1.RE)*SINH(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COS;
function SINH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 or Z.IM = MATH_PI ) then
return MATH_CZERO;
end if;
if ( Z.IM = MATH_PI_OVER_2 ) then
return MATH_CBASE_J;
end if;
if ( Z.IM = -MATH_PI_OVER_2 ) then
return -MATH_CBASE_J;
end if;
end if;
-- Get value for general case
return COMPLEX'(SINH(Z.RE)*COS(Z.IM), COSH(Z.RE)*SIN(Z.IM));
end function SINH;
function SINH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in SINH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI_OVER_2);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, -MATH_PI_OVER_2);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(SINH(Z1.RE)*COS(Z1.IM), COSH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function SINH;
function COSH(Z: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
-- Get value for special cases
if ( Z.RE = 0.0 ) then
if ( Z.IM = 0.0 ) then
return MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI ) then
return -MATH_CBASE_1;
end if;
if ( Z.IM = MATH_PI_OVER_2 or Z.IM = -MATH_PI_OVER_2 ) then
return MATH_CZERO;
end if;
end if;
-- Get value for general case
return COMPLEX'(COSH(Z.RE)*COS(Z.IM), SINH(Z.RE)*SIN(Z.IM));
end function COSH;
function COSH(Z: in COMPLEX_POLAR ) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR(0.0, 0.0) on error
variable Z1, Z2 : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( Z.ARG = -MATH_PI ) then
assert FALSE
report "Z.ARG = -MATH_PI in COSH(Z)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for special cases
if ( Z.MAG = 0.0 and Z.ARG = 0.0 ) then
return COMPLEX_POLAR'(1.0, 0.0);
end if;
if ( Z.MAG = MATH_PI and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(1.0, MATH_PI);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( Z.MAG = MATH_PI_OVER_2 and Z.ARG = -MATH_PI_OVER_2 ) then
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Compute value for general case
Z1 := POLAR_TO_COMPLEX(Z);
Z2 := COMPLEX'(COSH(Z1.RE)*COS(Z1.IM), SINH(Z1.RE)*SIN(Z1.IM));
ZOUT := COMPLEX_TO_POLAR(Z2);
return ZOUT;
end function COSH;
--
-- Arithmetic Operators
--
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R.RE, L.IM + R.IM);
end function "+";
function "+" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L + R.RE, R.IM);
end function "+";
function "+" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE + R, L.IM);
end function "+";
function "+" (L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + ZR.RE, ZL.IM +ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L + ZR.RE, ZR.IM));
return ZOUT;
end function "+";
function "+" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in +(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE + R, ZL.IM));
return ZOUT;
end function "+";
function "-" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R.RE, L.IM - R.IM);
end function "-";
function "-" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L - R.RE, -1.0 * R.IM);
end function "-";
function "-" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE - R, L.IM);
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL, ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - ZR.RE, ZL.IM -ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR := POLAR_TO_COMPLEX( R );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(L - ZR.RE, -1.0*ZR.IM));
return ZOUT;
end function "-";
function "-" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in -(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL := POLAR_TO_COMPLEX( L );
ZOUT := COMPLEX_TO_POLAR(COMPLEX'(ZL.RE - R, ZL.IM));
return ZOUT;
end function "-";
function "*" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R.RE - L.IM * R.IM, L.RE * R.IM + L.IM * R.RE);
end function "*";
function "*" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L * R.RE, L * R.IM);
end function "*";
function "*" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- None
begin
return COMPLEX'(L.RE * R, L.IM * R);
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if ( L < 0.0 ) then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG * R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG + R.ARG);
return ZOUT;
end function "*";
function "*" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(0.0, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in *(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if ( R < 0.0 ) then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG * ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG + ZR.ARG);
return ZOUT;
end function "*";
function "/" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
constant TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'( (L.RE * R.RE + L.IM * R.IM) / TEMP,
(L.IM * R.RE - L.RE * R.IM) / TEMP);
end function "/";
function "/" ( L: in REAL; R: in COMPLEX ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
--
variable TEMP : REAL := R.RE*R.RE + R.IM*R.IM;
begin
-- Check validity of input arguments
if (TEMP = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by (0.0, 0.0)"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
TEMP := L / TEMP;
return COMPLEX'( TEMP * R.RE, -TEMP * R.IM );
end function "/";
function "/" ( L: in COMPLEX; R: in REAL ) return COMPLEX is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX'(REAL'HIGH, 0.0) on error
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX by 0.0"
severity ERROR;
return COMPLEX'(REAL'HIGH, 0.0);
end if;
-- Get value
return COMPLEX'(L.RE / R, L.IM / R);
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in COMPLEX_POLAR)
return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZOUT.MAG := L.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - R.ARG);
return ZOUT;
end function "/";
function "/" ( L: in COMPLEX_POLAR; R: in REAL) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZR : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by 0.0"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( L.ARG = -MATH_PI ) then
assert FALSE
report "L.ARG = -MATH_PI in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
-- Get principal value
ZR.MAG := POSITIVE_REAL'(ABS(R));
if R < 0.0 then
ZR.ARG := MATH_PI;
else
ZR.ARG := 0.0;
end if;
ZOUT.MAG := L.MAG/ZR.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(L.ARG - ZR.ARG);
return ZOUT;
end function "/";
function "/" ( L: in REAL; R: in COMPLEX_POLAR) return COMPLEX_POLAR is
-- Description:
-- See function declaration in IEEE Std 1076.2-1996
-- Notes:
-- a) Returns COMPLEX_POLAR'(REAL'HIGH, 0.0) on error
--
variable ZL : COMPLEX_POLAR;
variable ZOUT : COMPLEX_POLAR;
begin
-- Check validity of input arguments
if (R.MAG = 0.0) then
assert FALSE
report "Attempt to divide COMPLEX_POLAR by (0.0, 0.0)"
severity ERROR;
return COMPLEX_POLAR'(REAL'HIGH, 0.0);
end if;
if ( R.ARG = -MATH_PI ) then
assert FALSE
report "R.ARG = -MATH_P in /(L,R)"
severity ERROR;
return COMPLEX_POLAR'(0.0, 0.0);
end if;
-- Get principal value
ZL.MAG := POSITIVE_REAL'(ABS(L));
if L < 0.0 then
ZL.ARG := MATH_PI;
else
ZL.ARG := 0.0;
end if;
ZOUT.MAG := ZL.MAG/R.MAG;
ZOUT.ARG := GET_PRINCIPAL_VALUE(ZL.ARG - R.ARG);
return ZOUT;
end function "/";
end package body MATH_COMPLEX;
|
gpl-3.0
|
nickg/nvc
|
test/parse/issue367.vhd
|
2
|
382
|
package r is
function r1(a:bit_vector) return bit_vector;
end package;
package body r is
function r1(a:bit_vector) return bit_vector is
variable ret : bit_vector(a'range);
variable i : integer range a'range; -- Error here
begin
for i in a'range loop
ret(i) := not a(i);
end loop;
return ret;
end r1;
end r;
|
gpl-3.0
|
nickg/nvc
|
test/sem/const2.vhd
|
4
|
229
|
package deferred is
type t_int_array is array (natural range <>) of integer;
constant def_arr : t_int_array;
end package;
package body deferred is
constant def_arr : t_int_array := (0 to 2 => 10);
end package body;
|
gpl-3.0
|
nickg/nvc
|
test/jit/prot1.vhd
|
1
|
764
|
package prot1 is
impure function fetch_and_add (n : integer) return integer;
end package;
package body prot1 is
type pt is protected
procedure increment (n : integer);
impure function get return integer;
end protected;
type pt is protected body
variable counter : integer := 0;
procedure increment (n : integer) is
begin
counter := counter + n;
end procedure;
impure function get return integer is
begin
return counter;
end function;
end protected body;
shared variable p : pt;
impure function fetch_and_add (n : integer) return integer is
begin
p.increment(n);
return p.get;
end function;
end package body;
|
gpl-3.0
|
nickg/nvc
|
test/jit/sum.vhd
|
1
|
907
|
package sumpkg is
type int_vector is array (natural range <>) of integer;
function get_left(a : int_vector) return integer;
function get_right(a : int_vector) return integer;
function get_length(a : int_vector) return integer;
function sum(a : int_vector) return integer;
end package;
package body sumpkg is
function sum(a : int_vector) return integer is
variable result : integer := 0;
begin
for i in a'range loop
result := result + a(i);
end loop;
return result;
end function;
function get_left(a : int_vector) return integer is
begin
return a'left;
end function;
function get_right(a : int_vector) return integer is
begin
return a'right;
end function;
function get_length(a : int_vector) return integer is
begin
return a'length;
end function;
end package body;
|
gpl-3.0
|
Separius/CordicWrapper
|
CordicWrapperTB1.vhd
|
1
|
2631
|
-- Vhdl test bench created from schematic G:\University\5th semester\CAD\CAD-CA5-wrapper\wrapper\FinalDP.sch - Sat Jan 16 17:16:35 2016
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY FinalDP_FinalDP_sch_tb IS
END FinalDP_FinalDP_sch_tb;
ARCHITECTURE behavioral OF FinalDP_FinalDP_sch_tb IS
COMPONENT FinalDP
PORT( clk : IN STD_LOGIC;
bus_reset : IN STD_LOGIC;
start0 : IN STD_LOGIC;
rst0 : IN STD_LOGIC;
start1 : IN STD_LOGIC;
rst1 : IN STD_LOGIC;
start2 : IN STD_LOGIC;
rst2 : IN STD_LOGIC;
rst3 : IN STD_LOGIC;
start3 : IN STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL bus_reset : STD_LOGIC;
SIGNAL start0 : STD_LOGIC;
SIGNAL rst0 : STD_LOGIC;
SIGNAL start1 : STD_LOGIC;
SIGNAL rst1 : STD_LOGIC;
SIGNAL start2 : STD_LOGIC;
SIGNAL rst2 : STD_LOGIC;
SIGNAL rst3 : STD_LOGIC;
SIGNAL start3 : STD_LOGIC;
constant in_clk_period : time := 10 ns;
BEGIN
in_clk_process :process
begin
clk <= '0';
wait for in_clk_period/2;
clk <= '1';
wait for in_clk_period/2;
end process;
UUT: FinalDP PORT MAP(
clk => clk,
bus_reset => bus_reset,
start0 => start0,
rst0 => rst0,
start1 => start1,
rst1 => rst1,
start2 => start2,
rst2 => rst2,
rst3 => rst3,
start3 => start3
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
bus_reset <= '1';
start0 <= '0';
rst0 <= '1';
start1 <= '0';
rst1 <= '1';
start2 <= '0';
rst2 <= '1';
start3 <= '0';
rst3 <= '1';
wait for in_clk_period*5;
bus_reset <= '0';
start0 <= '1';
rst0 <= '0';
start1 <= '1';
rst1 <= '0';
start2 <= '1';
rst2 <= '0';
start3 <= '1';
rst3 <= '0';
wait for in_clk_period*60;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_prim_width.vhd
|
9
|
70108
|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/common/wr_pf_as.vhd
|
9
|
27228
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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5/Y8ky3xhQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18416)
`protect data_block
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H+UhB0Q=
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00058.vhd
|
1
|
11405
|
-- NEED RESULT: ARCH00058.P1: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P2: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P3: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P4: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P5: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P6: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P7: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P8: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P9: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P10: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P11: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P12: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P13: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P14: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P15: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P16: While condition in loop is evaluated prior to execution of loop body passed
-- NEED RESULT: ARCH00058.P17: While condition in loop is evaluated prior to execution of loop body passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00058
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.8 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00058)
-- ENT00058_Test_Bench(ARCH00058_Test_Bench)
--
-- REVISION HISTORY:
--
-- 02-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00058 of E00000 is
signal Dummy : Boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean := true ;
variable v_boolean : boolean :=
c_boolean_1 ;
--
begin
L1 :
while v_boolean /= c_boolean_1 loop
correct := false ;
v_boolean := c_boolean_2 ;
end loop L1 ;
test_report ( "ARCH00058.P1" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
variable v_bit : bit :=
c_bit_1 ;
--
begin
L1 :
while v_bit /= c_bit_1 loop
correct := false ;
v_bit := c_bit_2 ;
end loop L1 ;
test_report ( "ARCH00058.P2" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P2 ;
--
P3 :
process ( Dummy )
variable correct : boolean := true ;
variable v_severity_level : severity_level :=
c_severity_level_1 ;
--
begin
L1 :
while v_severity_level /= c_severity_level_1 loop
correct := false ;
v_severity_level := c_severity_level_2 ;
end loop L1 ;
test_report ( "ARCH00058.P3" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P3 ;
--
P4 :
process ( Dummy )
variable correct : boolean := true ;
variable v_character : character :=
c_character_1 ;
--
begin
L1 :
while v_character /= c_character_1 loop
correct := false ;
v_character := c_character_2 ;
end loop L1 ;
test_report ( "ARCH00058.P4" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P4 ;
--
P5 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_enum1 : st_enum1 :=
c_st_enum1_1 ;
--
begin
L1 :
while v_st_enum1 /= c_st_enum1_1 loop
correct := false ;
v_st_enum1 := c_st_enum1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P5" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P5 ;
--
P6 :
process ( Dummy )
variable correct : boolean := true ;
variable v_integer : integer :=
c_integer_1 ;
--
begin
L1 :
while v_integer /= c_integer_1 loop
correct := false ;
v_integer := c_integer_2 ;
end loop L1 ;
test_report ( "ARCH00058.P6" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P6 ;
--
P7 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_int1 : st_int1 :=
c_st_int1_1 ;
--
begin
L1 :
while v_st_int1 /= c_st_int1_1 loop
correct := false ;
v_st_int1 := c_st_int1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P7" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P7 ;
--
P8 :
process ( Dummy )
variable correct : boolean := true ;
variable v_time : time :=
c_time_1 ;
--
begin
L1 :
while v_time /= c_time_1 loop
correct := false ;
v_time := c_time_2 ;
end loop L1 ;
test_report ( "ARCH00058.P8" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P8 ;
--
P9 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_phys1 : st_phys1 :=
c_st_phys1_1 ;
--
begin
L1 :
while v_st_phys1 /= c_st_phys1_1 loop
correct := false ;
v_st_phys1 := c_st_phys1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P9" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P9 ;
--
P10 :
process ( Dummy )
variable correct : boolean := true ;
variable v_real : real :=
c_real_1 ;
--
begin
L1 :
while v_real /= c_real_1 loop
correct := false ;
v_real := c_real_2 ;
end loop L1 ;
test_report ( "ARCH00058.P10" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P10 ;
--
P11 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_real1 : st_real1 :=
c_st_real1_1 ;
--
begin
L1 :
while v_st_real1 /= c_st_real1_1 loop
correct := false ;
v_st_real1 := c_st_real1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P11" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P11 ;
--
P12 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_rec1 : st_rec1 :=
c_st_rec1_1 ;
--
begin
L1 :
while v_st_rec1 /= c_st_rec1_1 loop
correct := false ;
v_st_rec1 := c_st_rec1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P12" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P12 ;
--
P13 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_rec2 : st_rec2 :=
c_st_rec2_1 ;
--
begin
L1 :
while v_st_rec2 /= c_st_rec2_1 loop
correct := false ;
v_st_rec2 := c_st_rec2_2 ;
end loop L1 ;
test_report ( "ARCH00058.P13" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P13 ;
--
P14 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
--
begin
L1 :
while v_st_rec3 /= c_st_rec3_1 loop
correct := false ;
v_st_rec3 := c_st_rec3_2 ;
end loop L1 ;
test_report ( "ARCH00058.P14" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P14 ;
--
P15 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
--
begin
L1 :
while v_st_arr1 /= c_st_arr1_1 loop
correct := false ;
v_st_arr1 := c_st_arr1_2 ;
end loop L1 ;
test_report ( "ARCH00058.P15" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P15 ;
--
P16 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
--
begin
L1 :
while v_st_arr2 /= c_st_arr2_1 loop
correct := false ;
v_st_arr2 := c_st_arr2_2 ;
end loop L1 ;
test_report ( "ARCH00058.P16" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P16 ;
--
P17 :
process ( Dummy )
variable correct : boolean := true ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
L1 :
while v_st_arr3 /= c_st_arr3_1 loop
correct := false ;
v_st_arr3 := c_st_arr3_2 ;
end loop L1 ;
test_report ( "ARCH00058.P17" ,
"While condition in loop is evaluated prior to " &
"execution of loop body",
correct ) ;
--
end process P17 ;
--
--
end ARCH00058 ;
--
entity ENT00058_Test_Bench is
end ENT00058_Test_Bench ;
--
architecture ARCH00058_Test_Bench of ENT00058_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00058 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00058_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00698.vhd
|
1
|
2968
|
-- NEED RESULT: ARCH00698: Formal parameters of mode in may be left unspecified in association list if they have default expressions passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00698
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00698(ARCH00698)
-- ENT00698_Test_Bench(ARCH00698_Test_Bench)
--
-- REVISION HISTORY:
--
-- 09-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00698 is
port (
p_integer : integer := 5 ;
p_boolean : boolean := true ;
p_st_arr3 : st_arr3 := c_st_arr3_1
) ;
end ENT00698 ;
--
architecture ARCH00698 of ENT00698 is
procedure p1 (
pc_integer : integer := -4 ;
pc_boolean : boolean := false ;
pc_st_arr3 : st_arr3 := c_st_arr3_2 ;
pv_integer : integer := 3 ;
pv_boolean : boolean := true ;
pv_st_arr3 : st_arr3 := c_st_arr3_1 ;
signal ps_integer : integer ;
signal ps_boolean : boolean ;
signal ps_st_arr3 : st_arr3
) is
variable correct : boolean := true ;
begin
correct := correct and pc_integer = -4 ;
correct := correct and not pc_boolean ;
correct := correct and pc_st_arr3 = c_st_arr3_2 ;
correct := correct and pv_integer = 0 ;
correct := correct and pv_boolean ;
correct := correct and pv_st_arr3 = c_st_arr3_1 ;
correct := correct and ps_integer = 5 ;
correct := correct and ps_boolean ;
correct := correct and ps_st_arr3 = c_st_arr3_1 ;
test_report ( "ARCH00698" ,
"Formal parameters of mode in may be left unspecified"
& " in association list if they have default expressions" ,
correct ) ;
end p1 ;
begin
process
variable v_integer : integer := 0 ;
variable v_boolean : boolean := true ;
variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
begin
p1 (
ps_integer => p_integer ,
ps_boolean => p_boolean ,
ps_st_arr3 => p_st_arr3 ,
pv_integer => 0
) ;
wait ;
end process ;
end ARCH00698 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00698_Test_Bench is
end ENT00698_Test_Bench ;
--
architecture ARCH00698_Test_Bench of ENT00698_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00698 ( ARCH00698 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00698_Test_Bench ;
--
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00390.vhd
|
1
|
69202
|
-- NEED RESULT: ARCH00390.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P4: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P5: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P6: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P7: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P8: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390.P9: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00390: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P9: Inertial transactions completed entirely passed
-- NEED RESULT: P8: Inertial transactions completed entirely passed
-- NEED RESULT: P7: Inertial transactions completed entirely passed
-- NEED RESULT: P6: Inertial transactions completed entirely passed
-- NEED RESULT: P5: Inertial transactions completed entirely passed
-- NEED RESULT: P4: Inertial transactions completed entirely passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00390
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00390(ARCH00390)
-- ENT00390_Test_Bench(ARCH00390_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00390 is
end ENT00390 ;
--
--
architecture ARCH00390 of ENT00390 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 4 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 5 ;
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_boolean_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_boolean_vector(lowb to highb-1) <=
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
wait until (not s_st_boolean_vector(lowb to highb-1)'Quiet) and
(s_st_boolean_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb to highb-1) <=
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns
when st_boolean_vector_select = 3 else
--
c_st_boolean_vector_1(lowb to highb-1) after 100 ns
when st_boolean_vector_select = 4 else
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when st_boolean_vector_select = 5 else
--
-- Last transaction above is marked
c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 4 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 5 ;
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_severity_level_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_severity_level_vector(lowb to highb-1) <=
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
wait until (not s_st_severity_level_vector(lowb to highb-1)'Quiet) and
(s_st_severity_level_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb to highb-1) <=
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns
when st_severity_level_vector_select = 3 else
--
c_st_severity_level_vector_1(lowb to highb-1) after 100 ns
when st_severity_level_vector_select = 4 else
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when st_severity_level_vector_select = 5 else
--
-- Last transaction above is marked
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 4 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 5 ;
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_string_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_string(highb-1 to highb-1) <=
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
wait until (not s_st_string(highb-1 to highb-1)'Quiet) and
(s_st_string_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb-1 to highb-1) <=
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb-1 to highb-1) after 5 ns
when st_string_select = 3 else
--
c_st_string_1(highb-1 to highb-1) after 100 ns
when st_string_select = 4 else
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when st_string_select = 5 else
--
-- Last transaction above is marked
c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
CHG4 :
process
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P4" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 4 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 5 ;
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_enum1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_enum1_vector(highb-1 to highb-1) <=
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
wait until (not s_st_enum1_vector(highb-1 to highb-1)'Quiet) and
(s_st_enum1_vector_savt /= Std.Standard.Now) ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions completed entirely",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb-1 to highb-1) <=
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns
when st_enum1_vector_select = 3 else
--
c_st_enum1_vector_1(highb-1 to highb-1) after 100 ns
when st_enum1_vector_select = 4 else
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when st_enum1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
CHG5 :
process
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P5" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 4 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 5 ;
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_integer_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_integer_vector(lowb to highb-1) <=
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
wait until (not s_st_integer_vector(lowb to highb-1)'Quiet) and
(s_st_integer_vector_savt /= Std.Standard.Now) ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions completed entirely",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb to highb-1) <=
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns
when st_integer_vector_select = 3 else
--
c_st_integer_vector_1(lowb to highb-1) after 100 ns
when st_integer_vector_select = 4 else
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when st_integer_vector_select = 5 else
--
-- Last transaction above is marked
c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
CHG6 :
process
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P6" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 4 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 5 ;
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_time_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_time_vector(lowb to highb-1) <=
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
wait until (not s_st_time_vector(lowb to highb-1)'Quiet) and
(s_st_time_vector_savt /= Std.Standard.Now) ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions completed entirely",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb to highb-1) <=
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb to highb-1) after 5 ns
when st_time_vector_select = 3 else
--
c_st_time_vector_1(lowb to highb-1) after 100 ns
when st_time_vector_select = 4 else
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when st_time_vector_select = 5 else
--
-- Last transaction above is marked
c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
CHG7 :
process
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P7" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 4 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 5 ;
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_real_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_real_vector(highb-1 to highb-1) <=
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
wait until (not s_st_real_vector(highb-1 to highb-1)'Quiet) and
(s_st_real_vector_savt /= Std.Standard.Now) ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions completed entirely",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb-1 to highb-1) <=
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns
when st_real_vector_select = 3 else
--
c_st_real_vector_1(highb-1 to highb-1) after 100 ns
when st_real_vector_select = 4 else
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when st_real_vector_select = 5 else
--
-- Last transaction above is marked
c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
CHG8 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P8" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(highb-1 to highb-1) <=
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(highb-1 to highb-1)'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb-1 to highb-1) <=
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(highb-1 to highb-1) after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
CHG9 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390.P9" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb to highb-1) <=
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00390" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb to highb-1)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb to highb-1) <=
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns
when st_arr2_vector_select = 3 else
--
c_st_arr2_vector_1(lowb to highb-1) after 100 ns
when st_arr2_vector_select = 4 else
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when st_arr2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
end ARCH00390 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00390_Test_Bench is
end ENT00390_Test_Bench ;
--
--
architecture ARCH00390_Test_Bench of ENT00390_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00390 ( ARCH00390 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00390_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00207.vhd
|
1
|
5163
|
-- NEED RESULT: ENT00207: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00207: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00207: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00207: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00207
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00207(ARCH00207)
-- ENT00207_Test_Bench(ARCH00207_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00207 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00207 ;
--
--
architecture ARCH00207 of ENT00207 is
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(1 to 2) <= transport
c_st_int1_vector_2(1 to 2) after 10 ns ;
wait until s_st_int1_vector(1 to 2) =
c_st_int1_vector_2(1 to 2) ;
Test_Report (
"ENT00207",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(1 to 2) =
c_st_int1_vector_2(1 to 2) )) ;
--
when 1
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(G-1 to G) <= transport
c_st_int1_vector_2(G-1 to G) after 10 ns ;
wait until s_st_int1_vector(G-1 to G) =
c_st_int1_vector_2(G-1 to G) ;
Test_Report (
"ENT00207",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(G-1 to G) =
c_st_int1_vector_2(G-1 to G) )) ;
--
when 2
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_2(1) ;
s_st_int1_vector(CG-1 to CG) <= transport
c_st_int1_vector_2(CG-1 to CG) after 10 ns ;
wait until s_st_int1_vector(CG-1 to CG) =
c_st_int1_vector_2(CG-1 to CG) ;
Test_Report (
"ENT00207",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG-1 to CG) =
c_st_int1_vector_2(CG-1 to CG) )) ;
--
when 3
=>
s_st_int1_vector(1) <= transport
c_st_int1_vector_1(1) ;
s_st_int1_vector(CG'Attr-1 to CG'Attr) <= transport
c_st_int1_vector_2(CG'Attr-1 to CG'Attr) after 10 ns ;
wait until s_st_int1_vector(CG'Attr-1 to CG'Attr) =
c_st_int1_vector_2(CG'Attr-1 to CG'Attr) ;
Test_Report (
"ENT00207",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1_vector(CG'Attr-1 to CG'Attr) =
c_st_int1_vector_2(CG'Attr-1 to CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00207 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00207_Test_Bench is
end ENT00207_Test_Bench ;
--
--
architecture ARCH00207_Test_Bench of ENT00207_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00207 ( ARCH00207 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00207_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00596.vhd
|
1
|
2059
|
-- NEED RESULT: ARCH00596: Direction of subtype with range is that of range passed
-- NEED RESULT: ARCH00596: Direction of subtype without range is that of underlying type passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00596
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.2 (7)
-- 4.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00596)
-- ENT00596_Test_Bench(ARCH00596_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00596 of E00000 is
begin
process
subtype s0 is integer ;
subtype s1 is integer range -10 downto -20 ;
subtype s2 is integer range 10 to 20 ;
subtype s3 is t_enum1 ;
subtype s4 is t_enum1 range en2 downto en1 ;
subtype s5 is t_enum1 range en1 to en2 ;
type t6 is range 5 downto 1 ;
subtype s6 is t6 ;
begin
test_report ( "ARCH00596" ,
"Direction of subtype with range is that of range" ,
s1'left > s1'right and
s2'left < s2'right and
s4'left > s4'right and
s5'left < s5'right ) ;
test_report ( "ARCH00596" ,
"Direction of subtype without range is that of"
& " underlying type" ,
s0'left < s0'right and
s3'left < s3'right and
s6'left > s6'right ) ;
wait ;
end process ;
end ARCH00596 ;
--
entity ENT00596_Test_Bench is
end ENT00596_Test_Bench ;
architecture ARCH00596_Test_Bench of ENT00596_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00596 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00596_Test_Bench ;
--
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00264.vhd
|
1
|
2237
|
-- NEED RESULT: ARCH00264: Scalar types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00264
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.1 (1)
-- 3.1 (2)
-- 3.1 (3)
-- 3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00264)
-- ENT00264_Test_Bench(ARCH00264_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
-- 14-JUN-1988 - EL - arrays must be initialized to values within the
-- element subtype
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00264 of E00000 is
-- these test 3.1 (1)
function f ( ary : t_arr1 ) return integer is
begin
return ary'right ;
end f ;
-- these test 3.1 (2) and 3.1 (3)
type ascending_range is range 0 to 10 ;
type descending_range is range 10 downto 0 ;
-- these test 3.1 (4)
subtype ascending_subrange is descending_range range 2 to 5 ;
subtype descending_subrange is ascending_range range 5 downto 2 ;
begin
P :
process
variable ascending_array : t_arr1 (5 to 7) := (10,10,10);
variable descending_array : t_arr1 (20 downto 17) := (10,10,10,10);
begin
test_report ( "ARCH00264" ,
"Scalar types" ,
(ascending_range'left = 0) and
(descending_range'left = 10) and
(ascending_subrange'right = 5) and
(descending_subrange'right = 2) and
(f(ascending_array) = 7) and
(f(descending_array) = 17)
) ;
wait ;
end process P ;
end ARCH00264 ;
entity ENT00264_Test_Bench is
end ENT00264_Test_Bench ;
architecture ARCH00264_Test_Bench of ENT00264_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00264 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00264_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00664.vhd
|
1
|
2377
|
-- NEED RESULT: ARCH00664: Ports on blocks and entities of mode 'linkage' may appear as an actual corresponding to an interface object of mode linkage passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00664
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (20)
-- 4.3.3.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00664(ARCH00664)
-- ENT00664_Test_Bench(ARCH00664_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00664 is
port ( Pt1 : linkage Integer ) ;
end ENT00664 ;
--
architecture ARCH00664 of ENT00664 is
function To_Integer ( P : Real ) return Integer is
begin
if P = -1.0 then
return -1 ;
else
return -2 ;
end if ;
end To_Integer ;
function To_Real ( P : Integer ) return Real is
begin
if P = -1 then
return -1.0 ;
else
return -2.0 ;
end if ;
end To_Real ;
begin
L1 :
block
port ( Pt1 : linkage Real ) ;
port map ( To_Integer(Pt1) => To_Real(Pt1) ) ; -- Check block 'linkage' p
begin
BP1 :
process
begin
wait ;
end process BP1 ;
end block L1 ;
end ARCH00664 ;
--
use WORK.STANDARD_TYPES.all;
entity ENT00664_Test_Bench is
end ENT00664_Test_Bench ;
architecture ARCH00664_Test_Bench of ENT00664_Test_Bench is
begin
L1:
block
component UUT
end component ;
signal S1 : Integer := -2 ;
for CIS1 : UUT use entity WORK.ENT00664 ( ARCH00664 )
port map ( S1 ) ; -- Check entity 'linkage' port
begin
CIS1 : UUT ;
process
begin
test_report ( "ARCH00664" ,
"Ports on blocks and entities "&
"of mode 'linkage' may appear as an actual "&
"corresponding to an interface object of "&
"mode linkage" ,
S1 = -2 ) ;
wait ;
end process ;
end block L1 ;
end ARCH00664_Test_Bench ;
--
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_v8_0_pkg.vhd
|
9
|
123409
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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nRx2DEslmg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/service/src/boot_backup.vhd
|
1
|
8924
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity boot is
port (
CLK50 : in std_logic;
BUTTON1 : in std_logic;
BUTTON2 : in std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
SRAM_A : out std_logic_vector(18 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_UB : out std_logic;
SRAM_LB : out std_logic;
SRAM_CE0 : out std_logic;
SRAM_CE1 : out std_logic;
COMM_CSA : in std_logic;
COMM_CSD : in std_logic;
COMM_SCK : in std_logic;
COMM_SDI : in std_logic;
COMM_SDO : out std_logic;
COMM_READY : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_VSYNC : out std_logic;
VGA_HSYNC : out std_logic
);
end boot;
architecture rtl of boot is
-- SPI COMMANDS
constant CMD_SET_ATTR : std_logic_vector(6 downto 0) := "0000000";
constant CMD_SET_X : std_logic_vector(6 downto 0) := "0000001";
constant CMD_SET_Y : std_logic_vector(6 downto 0) := "0000010";
constant CMD_WRITE_CHAR : std_logic_vector(6 downto 0) := "0000011";
constant CMD_H_ADDR : std_logic_vector(6 downto 0) := "0000100";
constant CMD_M_ADDR : std_logic_vector(6 downto 0) := "0000101";
constant CMD_L_ADDR : std_logic_vector(6 downto 0) := "0000110";
constant CMD_DATA_WR : std_logic_vector(6 downto 0) := "0000111";
constant CMD_DATA_RD : std_logic_vector(6 downto 0) := "0001000";
signal CLK : std_logic;
signal VGA_CLK : std_logic;
signal RESET : std_logic;
signal LOCKED : std_logic;
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal VA : std_logic_vector(11 downto 0);
signal VDI : std_logic_vector(7 downto 0);
signal VWR : std_logic;
signal VATTR : std_logic_vector(7 downto 0);
signal COMM_AO : std_logic_vector(7 downto 0);
signal COMM_AI : std_logic_vector(7 downto 0);
signal COMM_A_REQ : std_logic;
signal COMM_A_ACK : std_logic;
signal COMM_DO : std_logic_vector(7 downto 0);
signal COMM_DI : std_logic_vector(7 downto 0);
signal COMM_D_REQ : std_logic;
signal COMM_D_ACK : std_logic;
signal COMM_RG : std_logic_vector(7 downto 0);
signal COMM_MA : std_logic_vector(19 downto 0);
type STATES is (ST_IDLE, ST_READ1, ST_READ2, ST_WRITE1);
signal STATE : STATES;
begin
LED1 <= BUTTON1;
LED2 <= not BUTTON1 and not BUTTON2;
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK,
VGA_CLK => VGA_CLK,
LOCKED => LOCKED );
-- ###########################
RESET <= not LOCKED;
u_VIDEO : entity work.video
port map(
CLK => CLK,
VGA_CLK => VGA_CLK,
RESET => RESET,
VA => VA,
VDI => VDI,
VWR => VWR,
VATTR => VATTR,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
u_COMM_SPI : entity work.spi_comm
port map(
CLK => CLK,
RESET => RESET,
SPI_CS_A => COMM_CSA,
SPI_CS_D => COMM_CSD,
SPI_SCK => COMM_SCK,
SPI_DI => COMM_SDI,
SPI_DO => COMM_SDO,
ADDR_O => COMM_AO,
ADDR_I => COMM_AI,
ADDR_REQ => COMM_A_REQ,
ADDR_ACK => COMM_A_ACK,
DATA_O => COMM_DO,
DATA_I => COMM_DI,
DATA_REQ => COMM_D_REQ,
DATA_ACK => COMM_D_ACK );
p_state_machine : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
STATE <= ST_IDLE;
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
COMM_A_ACK <= '0';
COMM_D_ACK <= '0';
COMM_READY <= '0';
VWR <= '0';
else
COMM_A_ACK <= '0';
COMM_D_ACK <= '0';
VWR <= '0';
case STATE is
when ST_IDLE =>
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE <= '1';
SRAM_OE <= '1';
SRAM_CE0 <= '1';
SRAM_CE1 <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
if COMM_A_REQ = '1' then
COMM_A_ACK <= '1';
COMM_RG <= COMM_AO;
if COMM_AO(7) = '0' then -- ### READ ###
case (COMM_AO(6 downto 0)) is
when CMD_DATA_RD =>
SRAM_A <= '0' & COMM_MA(17 downto 0);
SRAM_OE <= '0';
if COMM_MA(18) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if COMM_MA(19) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 1);
STATE <= ST_READ1;
when OTHERS =>
NULL;
end case;
end if;
elsif COMM_D_REQ = '1' then
COMM_D_ACK <= '1';
if COMM_RG(7) = '1' then -- ### WRITE ###
case (COMM_RG(6 downto 0)) is
when CMD_SET_ATTR =>
VATTR <= COMM_DO;
when CMD_SET_X =>
VA <= VA(11 downto 7) & COMM_DO(6 downto 0);
when CMD_SET_Y =>
VA <= COMM_DO(4 downto 0) & VA(6 downto 0);
when CMD_WRITE_CHAR =>
VDI <= COMM_DO;
VWR <= '1';
when CMD_H_ADDR =>
COMM_MA(19 downto 16) <= COMM_DO(3 downto 0);
when CMD_M_ADDR =>
COMM_MA(15 downto 8) <= COMM_DO;
when CMD_L_ADDR =>
COMM_MA(7 downto 0 ) <= COMM_DO;
when CMD_DATA_WR =>
SRAM_A <= '0' & COMM_MA(17 downto 0);
SRAM_DI <= COMM_DO & COMM_DO;
SRAM_WE <= '0';
if COMM_MA(18) = '0' then
SRAM_CE0 <= '0';
else
SRAM_CE1 <= '0';
end if;
if COMM_MA(19) = '0' then
SRAM_LB <= '0';
else
SRAM_UB <= '0';
end if;
COMM_MA <= std_logic_vector(unsigned(COMM_MA) + 1);
STATE <= ST_WRITE1;
when OTHERS =>
NULL;
end case;
end if;
end if;
when ST_READ1 =>
if COMM_MA(19) = '0' then
COMM_DI <= SRAM_DO(7 downto 0);
else
COMM_DI <= SRAM_DO(15 downto 8);
end if;
STATE <= ST_READ2;
when ST_READ2 =>
if COMM_D_REQ = '1' then
COMM_D_ACK <= '1';
STATE <= ST_IDLE;
end if;
when ST_WRITE1 =>
SRAM_WE <= '1';
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
SRAM_D <= SRAM_DI;
SRAM_DO <= SRAM_D;
end rtl;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_STD
|
Extras/VHDL/STD_03100_good.vhd
|
1
|
2776
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03100_good.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Dead VHDL code: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03100_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03100_good;
--CODE
architecture Behavioral of STD_03100_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/atari800core_simple_sdram.vhd
|
1
|
11083
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use ieee.numeric_std.all;
LIBRARY work;
-- Simple version that:
-- i) needs: CLK(58 or 28MHZ) SDRAM,joystick,keyboard
-- ii) provides: VIDEO,AUDIO
-- iii) passes upstream: DMA port, for attaching ZPU for SDCARD/drive emulation
-- THIS SHOULD DO FOR ALL PLATFORMS EXCEPT THOSE USING GPIO FOR PBI etc
ENTITY atari800core_simple_sdram is
GENERIC
(
-- use CLK of 1.79*cycle_length
-- I've tested 16 and 32 only, but 4 and 8 might work...
cycle_length : integer := 16; -- or 32...
-- how many bits for video
video_bits : integer := 8;
palette : integer :=1; -- 0:gtia colour on VIDEO_B, 1:altirra, 2:laoo
-- For initial port may help to have no
internal_rom : integer := 1; -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
internal_ram : integer := 16384 -- at start of memory map
);
PORT
(
CLK : IN STD_LOGIC; -- cycle_length*1.79MHz
RESET_N : IN STD_LOGIC;
-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
VIDEO_VS : OUT STD_LOGIC;
VIDEO_HS : OUT STD_LOGIC;
VIDEO_B : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_G : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
VIDEO_R : OUT STD_LOGIC_VECTOR(video_bits-1 DOWNTO 0);
-- These ones are probably only needed for e.g. svideo
VIDEO_BLANK : out std_logic;
VIDEO_BURST : out std_logic;
VIDEO_START_OF_FIELD : out std_logic;
VIDEO_ODD_LINE : out std_logic;
-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
-- TODO - choose stereo/mono pokey
AUDIO_L : OUT std_logic_vector(15 downto 0);
AUDIO_R : OUT std_logic_vector(15 downto 0);
-- JOYSTICK
JOY1_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
JOY2_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
-- Pokey keyboard matrix
-- Standard component available to connect this to PS2
KEYBOARD_RESPONSE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
KEYBOARD_SCAN : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- SIO
SIO_COMMAND : out std_logic;
SIO_RXD : in std_logic;
SIO_TXD : out std_logic;
-- GTIA consol
CONSOL_OPTION : IN STD_LOGIC;
CONSOL_SELECT : IN STD_LOGIC;
CONSOL_START : IN STD_LOGIC;
-----------------------
-- After here all FPGA implementation specific
-- e.g. need to write up RAM/ROM
-- we can dma from memory space
-- etc.
-- External RAM/ROM - adhere to standard memory map
-- TODO - lower/upper memory split defined by generic
-- (TODO SRAM lower ram, SDRAM upper ram - no overlap?)
---- SDRAM memory map (8MB) (lower 512k if USE_SDRAM=1)
---- base 64k RAM - banks 0-3 "000 0000 1111 1111 1111 1111" (TOP)
---- to 512k RAM - banks 4-31 "000 0111 1111 1111 1111 1111" (TOP)
---- to 4MB RAM - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
---- +64k - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
---- SCRATCH - 4MB+64k-5MB
---- CARTS - "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
--SDRAM_CART_ADDR <= "101"&cart_select& "0000000000000";
---- BASIC/OS ROM - "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K
--SDRAM_BASIC_ROM_ADDR <= "111"&"000000" &"00000000000000";
--SDRAM_OS_ROM_ADDR <= "111"&rom_select &"00000000000000";
---- SYSTEM - "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
-- TODO - review if we need to pass out so many of these
-- Perhaps we can simplify address decoder and have an external layer?
SDRAM_REQUEST : OUT std_logic;
SDRAM_REQUEST_COMPLETE : IN std_logic;
SDRAM_READ_ENABLE : out STD_LOGIC;
SDRAM_WRITE_ENABLE : out std_logic;
SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
SDRAM_DI : out STD_LOGIC_VECTOR(31 DOWNTO 0);
SDRAM_32BIT_WRITE_ENABLE : out std_logic;
SDRAM_16BIT_WRITE_ENABLE : out std_logic;
SDRAM_8BIT_WRITE_ENABLE : out std_logic;
SDRAM_REFRESH : out std_logic;
-- DMA memory map differs
-- e.g. some special addresses to read behind hardware registers
-- 0x0000-0xffff: Atari registers + 3 mirrors (bit 16/17)
-- 23 downto 21:
-- 001 : SRAM,512k
-- 010|011 : ROM, 4MB
-- 10xx : SDRAM, 8MB (If you have more, its unmapped for now... Can bank switch! Atari can't access this much anyway...)
DMA_FETCH : in STD_LOGIC; -- we want to read/write
DMA_READ_ENABLE : in std_logic;
DMA_32BIT_WRITE_ENABLE : in std_logic;
DMA_16BIT_WRITE_ENABLE : in std_logic;
DMA_8BIT_WRITE_ENABLE : in std_logic;
DMA_ADDR : in std_logic_vector(23 downto 0);
DMA_WRITE_DATA : in std_logic_vector(31 downto 0);
MEMORY_READY_DMA : out std_logic; -- op complete
DMA_MEMORY_DATA : out std_logic_vector(31 downto 0);
-- Special config params
RAM_SELECT : in std_logic_vector(2 downto 0); -- 64K,128K,320KB Compy, 320KB Rambo, 576K Compy, 576K Rambo, 1088K, 4MB
ROM_SELECT : in std_logic_vector(5 downto 0); -- 16KB ROM Bank - 0 is illegal (slot used for BASIC!)
PAL : in STD_LOGIC;
HALT : in std_logic;
THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0) -- standard speed is cycle_length-1
);
end atari800core_simple_sdram;
ARCHITECTURE vhdl OF atari800core_simple_sdram IS
-- PIA
SIGNAL CA1_IN : STD_LOGIC;
SIGNAL CB1_IN: STD_LOGIC;
SIGNAL CA2_OUT : STD_LOGIC;
SIGNAL CA2_DIR_OUT: STD_LOGIC;
SIGNAL CB2_OUT : STD_LOGIC;
SIGNAL CB2_DIR_OUT: STD_LOGIC;
SIGNAL CA2_IN: STD_LOGIC;
SIGNAL CB2_IN: STD_LOGIC;
SIGNAL PORTA_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTA_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL PORTB_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL PORTB_DIR_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- GTIA
signal GTIA_TRIG : std_logic_vector(3 downto 0);
-- ANTIC
signal ANTIC_LIGHTPEN : std_logic;
-- CARTRIDGE ACCESS
SIGNAL CART_RD4 : STD_LOGIC;
SIGNAL CART_RD5 : STD_LOGIC;
-- PBI
SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
-- INTERNAL ROM/RAM
SIGNAL RAM_ADDR : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL RAM_DO : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RAM_REQUEST : STD_LOGIC;
SIGNAL RAM_REQUEST_COMPLETE : STD_LOGIC;
SIGNAL RAM_WRITE_ENABLE : STD_LOGIC;
SIGNAL ROM_ADDR : STD_LOGIC_VECTOR(21 DOWNTO 0);
SIGNAL ROM_DO : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ROM_REQUEST : STD_LOGIC;
SIGNAL ROM_REQUEST_COMPLETE : STD_LOGIC;
-- CONFIG
SIGNAL USE_SDRAM : STD_LOGIC;
SIGNAL ROM_IN_RAM : STD_LOGIC;
BEGIN
-- PIA mapping
CA1_IN <= '1';
CB1_IN <= '1';
CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
SIO_COMMAND <= CB2_OUT;
PORTA_IN <= ((JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)&JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
PORTB_IN <= PORTB_OUT;
-- ANTIC lightpen
ANTIC_LIGHTPEN <= JOY2_n(4) and JOY1_n(4);
-- GTIA triggers
GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
-- Cartridge not inserted
CART_RD4 <= '0';
CART_RD5 <= '0';
-- Since we're not exposing PBI, expose a few key parts needed for SDRAM
SDRAM_DI <= PBI_WRITE_DATA;
-- Internal rom/ram
internalromram1 : entity work.internalromram
GENERIC MAP
(
internal_rom => internal_rom,
internal_ram => internal_ram
)
PORT MAP (
clock => CLK,
reset_n => RESET_N,
ROM_ADDR => ROM_ADDR,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
ROM_REQUEST => ROM_REQUEST,
ROM_DATA => ROM_DO,
RAM_ADDR => RAM_ADDR,
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_REQUEST => RAM_REQUEST,
RAM_DATA => RAM_DO(7 downto 0)
);
USE_SDRAM <= '1' when internal_ram=0 else '0';
ROM_IN_RAM <= '1' when internal_rom=0 else '0';
atari800xl : entity work.atari800core
GENERIC MAP
(
cycle_length => cycle_length,
video_bits => video_bits,
palette => palette
)
PORT MAP
(
CLK => CLK,
RESET_N => RESET_N,
VIDEO_VS => VIDEO_VS,
VIDEO_HS => VIDEO_HS,
VIDEO_B => VIDEO_B,
VIDEO_G => VIDEO_G,
VIDEO_R => VIDEO_R,
VIDEO_BLANK => VIDEO_BLANK,
VIDEO_BURST => VIDEO_BURST,
VIDEO_START_OF_FIELD => VIDEO_START_OF_FIELD,
VIDEO_ODD_LINE => VIDEO_ODD_LINE,
AUDIO_L => AUDIO_L,
AUDIO_R => AUDIO_R,
CA1_IN => CA1_IN,
CB1_IN => CB1_IN,
CA2_IN => CA2_IN,
CA2_OUT => CA2_OUT,
CA2_DIR_OUT => CA2_DIR_OUT,
CB2_IN => CB2_IN,
CB2_OUT => CB2_OUT,
CB2_DIR_OUT => CB2_DIR_OUT,
PORTA_IN => PORTA_IN,
PORTA_DIR_OUT => PORTA_DIR_OUT,
PORTA_OUT => PORTA_OUT,
PORTB_IN => PORTB_IN,
PORTB_DIR_OUT => open,--PORTB_DIR_OUT,
PORTB_OUT => PORTB_OUT,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
POT_IN => "00000000",
POT_RESET => open,
-- PBI
PBI_ADDR => open,
PBI_WRITE_ENABLE => open,
PBI_SNOOP_DATA => DMA_MEMORY_DATA,
PBI_WRITE_DATA => PBI_WRITE_DATA,
PBI_WIDTH_8bit_ACCESS => SDRAM_8BIT_WRITE_ENABLE,
PBI_WIDTH_16bit_ACCESS => SDRAM_16BIT_WRITE_ENABLE,
PBI_WIDTH_32bit_ACCESS => SDRAM_32BIT_WRITE_ENABLE,
PBI_ROM_DO => "11111111",
PBI_REQUEST => open,
PBI_REQUEST_COMPLETE => '1',
CART_RD4 => CART_RD4,
CART_RD5 => CART_RD5,
CART_S4_n => open,
CART_S5_N => open,
CART_CCTL_N => open,
SIO_RXD => SIO_RXD,
SIO_TXD => SIO_TXD,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START=> CONSOL_START,
GTIA_TRIG => GTIA_TRIG,
ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
ANTIC_REFRESH => SDRAM_REFRESH,
SDRAM_REQUEST => SDRAM_REQUEST,
SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_DO => SDRAM_DO,
RAM_ADDR => RAM_ADDR,
RAM_DO => RAM_DO,
RAM_REQUEST => RAM_REQUEST,
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
ROM_ADDR => ROM_ADDR,
ROM_DO => ROM_DO,
ROM_REQUEST => ROM_REQUEST,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
DMA_FETCH => DMA_FETCH,
DMA_READ_ENABLE => DMA_READ_ENABLE,
DMA_32BIT_WRITE_ENABLE => DMA_32BIT_WRITE_ENABLE,
DMA_16BIT_WRITE_ENABLE => DMA_16BIT_WRITE_ENABLE,
DMA_8BIT_WRITE_ENABLE => DMA_8BIT_WRITE_ENABLE,
DMA_ADDR => DMA_ADDR,
DMA_WRITE_DATA => DMA_WRITE_DATA,
MEMORY_READY_DMA => MEMORY_READY_DMA,
RAM_SELECT => RAM_SELECT,
ROM_SELECT => ROM_SELECT,
CART_EMULATION_SELECT => "0000000",
CART_EMULATION_ACTIVATE => '0',
PAL => PAL,
USE_SDRAM => USE_SDRAM,
ROM_IN_RAM => ROM_IN_RAM,
THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
HALT => HALT
);
end vhdl;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/korvet/src/keyboard/keyboard.vhd
|
1
|
12133
|
-- ###################################################################################
--
-- #### #### #####
-- ## ## ##### ## ## ##### ## ###### ##### ##### ##### ## ##
-- ## ## ## ## ## ## ## ## ##### ## ## ## ## ## ## ## ##
-- ## ## ## ## ## ## ###### ## ###### ###### ## ## ######
-- ## ## ## ## ### ## ## ## ## ## ## ##
-- #### ######## ##### # ##### ##### ## ##### ##### ##### #####
--
-- ###################################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
generic (FilterSize : positive := 10);
port(
clk : in std_logic;
reset : in std_logic;
o_reset : out std_logic;
PS2_Clk : in std_logic;
PS2_Data : in std_logic;
Key_Addr : in std_logic_vector(8 downto 0);
Key_Data : out std_logic_vector(7 downto 0) );
end keyboard;
architecture Behavioral of keyboard is
signal PS2_Datr : std_logic;
signal DoRead : std_logic; -- From outside when reading the scan code
signal Scan_Err : std_logic; -- To outside : Parity or Overflow error
signal Scan_Code : std_logic_vector(7 downto 0); -- Eight bits Data Out
signal Filter : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t0 : std_logic_vector(FilterSize-1 downto 0);
signal Filter_t1 : std_logic_vector(FilterSize-1 downto 0);
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned (3 downto 0);
signal Parity : std_logic;
signal S_Reg : std_logic_vector(8 downto 0);
signal PS2_Clk_f : std_logic; signal Code_Readed : std_logic;
signal Key_Released : std_logic;
signal Extend_Key : std_logic;
signal Key_Data_0 : std_logic_vector(7 downto 0);
signal Key_Data_1 : std_logic_vector(7 downto 0);
type Matrix_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Matrix_0 : Matrix_Image(0 to 7);
signal Matrix_1 : Matrix_Image(0 to 7);
Type State_t is (Idle, Shifting);
signal State : State_t;
begin
Filter_t0 <= (others=>'0');
Filter_t1 <= (others=>'1');
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t1 then
PS2_Clk_f <= '1';
elsif Filter = Filter_t0 then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Parity <= '0';
Scan_Err <= '0';
Code_Readed <= '0';
elsif rising_edge (Clk) then
Code_Readed <= '0';
case State is
when Idle =>
Parity <= '0';
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
Scan_Err <= '0';
State <= Shifting;
end if;
when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
-- Error is (wrong Parity) or (Stop='0') or Overflow
Scan_Err <= (not Parity) or (not PS2_Datr);
Scan_Code <= S_Reg(7 downto 0);
Code_Readed <= '1';
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
Parity <= Parity xor PS2_Datr;
end if;
when others => -- never reached
State <= Idle;
end case;
--Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !
end if;
end process;
process(Clk,Reset)
variable aaa : std_logic_vector(10 downto 0);
variable bbb : std_logic_vector(10 downto 0);
begin
if Reset='1' then
Matrix_0 <= (others => (others => '0'));
Matrix_1 <= (others => (others => '0'));
Key_Released <= '0';
Extend_Key <= '0';
elsif rising_edge (Clk) then
o_reset <= '0';
if Code_Readed = '1' then -- ScanCode is Readed
if Scan_Code = x"F0" then -- Key is Released
Key_Released <= '1';
elsif Scan_Code = x"E0" then -- Extended Key Pressed
Extend_Key <= '1';
else -- Analyse
aaa := (others=>'0');
bbb := (others=>'0');
case Scan_Code is
------------------------------------
when x"52" => aaa := "00000000001"; -- @
when x"1C" => aaa := "00000000010"; -- A
when x"32" => aaa := "00000000100"; -- B
when x"21" => aaa := "00000001000"; -- C
when x"23" => aaa := "00000010000"; -- D
when x"24" => aaa := "00000100000"; -- E
when x"2B" => aaa := "00001000000"; -- F
when x"34" => aaa := "00010000000"; -- G
------------------------------------
when x"33" => aaa := "00100000001"; -- H
when x"43" => aaa := "00100000010"; -- I
when x"3B" => aaa := "00100000100"; -- J
when x"42" => aaa := "00100001000"; -- K
when x"4B" => aaa := "00100010000"; -- L
when x"3A" => aaa := "00100100000"; -- M
when x"31" => aaa := "00101000000"; -- N
when x"44" => aaa := "00110000000"; -- O
------------------------------------
when x"4D" => aaa := "01000000001"; -- P
when x"15" => aaa := "01000000010"; -- Q
when x"2D" => aaa := "01000000100"; -- R
when x"1B" => aaa := "01000001000"; -- S
when x"2C" => aaa := "01000010000"; -- T
when x"3C" => aaa := "01000100000"; -- U
when x"2A" => aaa := "01001000000"; -- V
when x"1D" => aaa := "01010000000"; -- W
------------------------------------
when x"22" => aaa := "01100000001"; -- X
when x"1A" => aaa := "01100000010"; -- Y
when x"35" => aaa := "01100000100"; -- Z
when x"54" => aaa := "01100001000"; -- [
when x"0E" => aaa := "01100010000"; -- ?
when x"5B" => aaa := "01100100000"; -- ]
when x"61" => aaa := "01101000000"; -- ?
when x"4C" => aaa := "01110000000"; -- ?
------------------------------------
when x"45" => aaa := "10000000001"; -- 0
when x"16" => aaa := "10000000010"; -- 1
when x"1E" => aaa := "10000000100"; -- 2
when x"26" => aaa := "10000001000"; -- 3
when x"25" => aaa := "10000010000"; -- 4
when x"2E" => aaa := "10000100000"; -- 5
when x"36" => aaa := "10001000000"; -- 6
when x"3D" => aaa := "10010000000"; -- 7
------------------------------------
when x"3E" => aaa := "10100000001"; -- 8
when x"46" => aaa := "10100000010"; -- 9
when x"5D" => aaa := "10100000100"; -- *
when x"55" => aaa := "10100001000"; -- +
when x"41" => aaa := "10100010000"; -- <
when x"4A" => aaa := "10100100000"; -- =
when x"49" => aaa := "10101000000"; -- >
when x"4E" => aaa := "10110000000"; -- ?
------------------------------------
when x"5A" => aaa := "11000000001"; -- ENTER
when x"7B" => aaa := "11000000010"; -- ????
when x"07" => aaa := "11000000100"; -- ????
when x"77" => aaa := "11000001000"; -- ??
when x"7C" => aaa := "11000010000"; -- ??
when x"66" => aaa := "11000100000"; -- BACKSPACE
when x"0D" => aaa := "11001000000"; -- TAB
when x"29" => aaa := "11010000000"; -- SPACE
------------------------------------
when x"12" => aaa := "11100000001"; -- ?? ???.
when x"11" =>
case Extend_Key is
when '0' => aaa := "11100000010"; -- ???
when others => aaa := "11100000100"; -- ????
end case;
when x"76" => aaa := "11100001000"; -- ???
when x"14" =>
case Extend_Key is
when '0' => aaa := "11101000000"; -- o
when others => aaa := "11100010000"; -- ???
end case;
when x"58" => aaa := "11100100000"; -- ???
when x"59" => aaa := "11110000000"; -- ?? ????.
------------------------------------
when x"70" => bbb := "00000000001"; -- 0
when x"69" => bbb := "00000000010"; -- 1
when x"72" => bbb := "00000000100"; -- 2
when x"7A" => bbb := "00000001000"; -- 3
when x"6B" => bbb := "00000010000"; -- 4
when x"73" => bbb := "00000100000"; -- 5
when x"74" => bbb := "00001000000"; -- 6
when x"6C" => bbb := "00010000000"; -- 7
------------------------------------
when x"75" => bbb := "00100000001"; -- 8
when x"7D" => bbb := "00100000010"; -- 9
when x"71" => bbb := "00101000000"; -- .
------------------------------------
when x"05" => bbb := "01000000001"; -- P
when x"06" => bbb := "01000000010"; -- Q
when x"04" => bbb := "01000000100"; -- R
when x"0C" => bbb := "01000001000"; -- S
when x"03" => bbb := "01000010000"; -- T
------------------------------------
when x"7E" => o_reset <= '1';
when others => null;
end case;
if Key_Released = '0' then
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) <=
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) or
std_logic_vector(unsigned(aaa(7 downto 0)));
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) <=
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) or
std_logic_vector(unsigned(bbb(7 downto 0)));
else
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) <=
Matrix_0(to_integer(unsigned(aaa(10 downto 8)))) and
std_logic_vector(not unsigned(aaa(7 downto 0)));
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) <=
Matrix_1(to_integer(unsigned(bbb(10 downto 8)))) and
std_logic_vector(not unsigned(bbb(7 downto 0)));
end if;
Key_Released <= '0';
Extend_Key <= '0';
end if;
end if;
end if;
end process;
-- if RX_ShiftReg = x"aa" and RX_Received = '1' then
-- Matrix <= (others => (others => '0'));
-- end if;
g_out1 : for i in 0 to 7 generate
Key_Data_0(i) <= (Matrix_0(0)(i) and Key_Addr(0)) or
(Matrix_0(1)(i) and Key_Addr(1)) or
(Matrix_0(2)(i) and Key_Addr(2)) or
(Matrix_0(3)(i) and Key_Addr(3)) or
(Matrix_0(4)(i) and Key_Addr(4)) or
(Matrix_0(5)(i) and Key_Addr(5)) or
(Matrix_0(6)(i) and Key_Addr(6)) or
(Matrix_0(7)(i) and Key_Addr(7));
end generate;
g_out2 : for i in 0 to 7 generate
Key_Data_1(i) <= (Matrix_1(0)(i) and Key_Addr(0)) or
(Matrix_1(1)(i) and Key_Addr(1)) or
(Matrix_1(2)(i) and Key_Addr(2)) or
(Matrix_1(3)(i) and Key_Addr(3)) or
(Matrix_1(4)(i) and Key_Addr(4)) or
(Matrix_1(5)(i) and Key_Addr(5)) or
(Matrix_1(6)(i) and Key_Addr(6)) or
(Matrix_1(7)(i) and Key_Addr(7));
end generate;
Key_Data <= Key_Data_0 when Key_Addr(8) = '0' else Key_Data_1;
end Behavioral;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/pokey.vhdl
|
1
|
37114
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Problem - UART on the DE1 does not have all pins connected. Need to use...
ENTITY pokey IS
PORT
(
CLK : IN STD_LOGIC;
ENABLE_179 :in std_logic;
ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
-- keyboard interface
-- KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
-- KEY_HELD : IN STD_LOGIC;
-- SHIFT_PRESSED : IN STD_LOGIC;
-- BREAK_PRESSED : IN STD_LOGIC;
-- KEY_INTERRUPT : IN STD_LOGIC;
keyboard_scan : out std_logic_vector(5 downto 0);
keyboard_response : in std_logic_vector(1 downto 0);
-- pots - go high as capacitor charges
POT_IN : in std_logic_vector(7 downto 0);
-- sio interface
SIO_IN1 : IN std_logic;
SIO_IN2 : IN std_logic;
SIO_IN3 : IN std_logic;
DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
IRQ_N_OUT : OUT std_logic;
SIO_OUT1 : OUT std_logic;
SIO_OUT2 : OUT std_logic;
SIO_OUT3 : OUT std_logic;
SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
POT_RESET : out std_logic
);
END pokey;
ARCHITECTURE vhdl OF pokey IS
component synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END component;
component syncreset_enable_divider IS
generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
PORT
(
CLK : IN STD_LOGIC;
syncreset : in std_logic;
reset_n : in std_logic;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
component pokey_poly_17_9 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC;
RAND_OUT : OUT std_logic_vector(7 downto 0)
);
END component;
component pokey_poly_5 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END component;
component pokey_poly_4 IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INIT : IN STD_LOGIC;
BIT_OUT : OUT STD_LOGIC
);
END component;
component pokey_countdown_timer IS
generic(UNDERFLOW_DELAY : natural := 3);
PORT
(
CLK : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
ENABLE_UNDERFLOW : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
DATA_OUT : OUT STD_LOGIC
);
END component;
component pokey_noise_filter IS
PORT
(
NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
PULSE_IN : IN STD_LOGIC;
NOISE_4 : IN STD_LOGIC;
NOISE_5 : IN STD_LOGIC;
NOISE_LARGE : IN STD_LOGIC;
PULSE_OUT : OUT STD_LOGIC
);
END component;
COMPONENT complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
component pokey_keyboard_scanner is
port
(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic; -- typically hsync or equiv timing
keyboard_response : in std_logic_vector(1 downto 0);
debounce_disable : in std_logic;
scan_enable : in std_logic;
keyboard_scan : out std_logic_vector(5 downto 0);
shift_pressed : out std_logic;
control_pressed : out std_logic;
break_pressed : out std_logic;
key_held : out std_logic;
keycode : out std_logic_vector(5 downto 0);
other_key_irq : out std_logic
);
end component;
--signal enable_179 : std_logic;
signal enable_64 : std_logic;
signal enable_15 : std_logic;
signal audf0_reg : std_logic_vector(7 downto 0);
signal audc0_reg : std_logic_vector(7 downto 0);
signal audf1_reg : std_logic_vector(7 downto 0);
signal audc1_reg : std_logic_vector(7 downto 0);
signal audf2_reg : std_logic_vector(7 downto 0);
signal audc2_reg : std_logic_vector(7 downto 0);
signal audf3_reg : std_logic_vector(7 downto 0);
signal audc3_reg : std_logic_vector(7 downto 0);
signal audctl_reg : std_logic_vector(7 downto 0);
signal audf0_next : std_logic_vector(7 downto 0);
signal audc0_next : std_logic_vector(7 downto 0);
signal audf1_next : std_logic_vector(7 downto 0);
signal audc1_next : std_logic_vector(7 downto 0);
signal audf2_next : std_logic_vector(7 downto 0);
signal audc2_next : std_logic_vector(7 downto 0);
signal audf3_next : std_logic_vector(7 downto 0);
signal audc3_next : std_logic_vector(7 downto 0);
signal audctl_next : std_logic_vector(7 downto 0);
signal audf0_pulse : std_logic;
signal audf1_pulse : std_logic;
signal audf2_pulse : std_logic;
signal audf3_pulse : std_logic;
signal audf0_reload : std_logic;
signal audf1_reload : std_logic;
signal audf2_reload : std_logic;
signal audf3_reload : std_logic;
signal stimer_write : std_logic;
signal stimer_write_delayed : std_logic;
signal audf0_pulse_noise : std_logic;
signal audf1_pulse_noise : std_logic;
signal audf2_pulse_noise : std_logic;
signal audf3_pulse_noise : std_logic;
signal audf0_enable : std_logic;
signal audf1_enable : std_logic;
signal audf2_enable : std_logic;
signal audf3_enable : std_logic;
signal chan0_output_next : std_logic;
signal chan1_output_next : std_logic;
signal chan2_output_next : std_logic;
signal chan3_output_next : std_logic;
signal chan0_output_reg : std_logic;
signal chan1_output_reg : std_logic;
signal chan2_output_reg : std_logic;
signal chan3_output_reg : std_logic;
signal highpass0_next : std_logic;
signal highpass1_next : std_logic;
signal highpass0_reg : std_logic;
signal highpass1_reg : std_logic;
signal volume_channel_0_next : std_logic_vector(3 downto 0);
signal volume_channel_1_next : std_logic_vector(3 downto 0);
signal volume_channel_2_next : std_logic_vector(3 downto 0);
signal volume_channel_3_next : std_logic_vector(3 downto 0);
signal volume_channel_0_reg : std_logic_vector(3 downto 0);
signal volume_channel_1_reg : std_logic_vector(3 downto 0);
signal volume_channel_2_reg : std_logic_vector(3 downto 0);
signal volume_channel_3_reg : std_logic_vector(3 downto 0);
signal addr_decoded : std_logic_vector(15 downto 0);
signal noise_4 : std_logic;
signal noise_5 : std_logic;
signal noise_large : std_logic;
signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
signal initmode : std_logic;
signal irqen_next : std_logic_vector(7 downto 0);
signal irqen_reg : std_logic_vector(7 downto 0);
signal irqst_next : std_logic_vector(7 downto 0);
signal irqst_reg : std_logic_vector(7 downto 0);
signal irq_n_next : std_logic;
signal irq_n_reg : std_logic; -- for output
-- serial ports!
signal serial_ip_ready_interrupt : std_logic;
signal serial_ip_framing_next : std_logic;
signal serial_ip_framing_reg : std_logic;
signal serial_ip_overrun_next : std_logic;
signal serial_ip_overrun_reg : std_logic;
signal serial_op_needed_interrupt : std_logic;
signal skctl_next : std_logic_vector(7 downto 0);
signal skctl_reg : std_logic_vector(7 downto 0);
signal serin_shift_next : std_logic_vector(9 downto 0);
signal serin_shift_reg : std_logic_vector(9 downto 0);
signal serin_next : std_logic_vector(7 downto 0);
signal serin_reg : std_logic_vector(7 downto 0);
signal serin_bitcount_next : std_logic_vector(3 downto 0);
signal serin_bitcount_reg : std_logic_vector(3 downto 0);
signal sio_in1_reg : std_logic;
signal sio_in2_reg : std_logic;
signal sio_in3_reg : std_logic;
signal sio_in_next : std_logic;
signal sio_in_reg : std_logic;
signal sio_out_next : std_logic;
signal sio_out_reg : std_logic;
signal serial_out_next : std_logic;
signal serial_out_reg : std_logic;
signal serout_shift_next : std_logic_vector(9 downto 0);
signal serout_shift_reg : std_logic_vector(9 downto 0);
signal serout_holding_full_next : std_logic;
signal serout_holding_full_reg : std_logic;
signal serout_holding_next : std_logic_vector(7 downto 0);
signal serout_holding_reg : std_logic_vector(7 downto 0);
signal serout_holding_load : std_logic;
signal serout_bitcount_next : std_logic_vector(3 downto 0);
signal serout_bitcount_reg : std_logic_vector(3 downto 0);
signal serout_active_next : std_logic;
signal serout_active_reg : std_logic;
signal serial_reset : std_logic;
signal serout_sync_reset : std_logic;
signal skrest_write : std_logic;
signal serout_enable : std_logic;
signal serout_enable_delayed : std_logic;
signal serin_enable : std_logic;
signal async_serial_reset : std_logic;
signal waiting_for_start_bit : std_logic;
signal serin_clock_next : std_logic;
signal serin_clock_reg : std_logic;
signal serin_clock_last_next : std_logic;
signal serin_clock_last_reg : std_logic;
signal serout_clock_next : std_logic;
signal serout_clock_reg : std_logic;
signal serout_clock_last_next : std_logic;
signal serout_clock_last_reg : std_logic;
signal twotone_reset : std_logic;
signal twotone_next : std_logic;
signal twotone_reg : std_logic;
signal clock_next : std_logic;
signal clock_reg : std_logic;
signal clock_sync_next : std_logic;
signal clock_sync_reg : std_logic;
signal clock_input : std_logic;
-- keyboard
signal keyboard_overrun_next : std_logic;
signal keyboard_overrun_reg : std_logic;
signal shift_pressed : std_logic;
signal control_pressed : std_logic;
signal break_pressed : std_logic;
signal key_held : std_logic;
signal other_key_irq : std_logic;
signal kbcode : std_logic_vector(5 downto 0);
-- pots
signal pot0_next : std_logic_vector(7 downto 0);
signal pot0_reg : std_logic_vector(7 downto 0);
signal pot1_next : std_logic_vector(7 downto 0);
signal pot1_reg : std_logic_vector(7 downto 0);
signal pot2_next : std_logic_vector(7 downto 0);
signal pot2_reg : std_logic_vector(7 downto 0);
signal pot3_next : std_logic_vector(7 downto 0);
signal pot3_reg : std_logic_vector(7 downto 0);
signal pot4_next : std_logic_vector(7 downto 0);
signal pot4_reg : std_logic_vector(7 downto 0);
signal pot5_next : std_logic_vector(7 downto 0);
signal pot5_reg : std_logic_vector(7 downto 0);
signal pot6_next : std_logic_vector(7 downto 0);
signal pot6_reg : std_logic_vector(7 downto 0);
signal pot7_next : std_logic_vector(7 downto 0);
signal pot7_reg : std_logic_vector(7 downto 0);
signal pot_counter_next : std_logic_vector(7 downto 0);
signal pot_counter_reg : std_logic_vector(7 downto 0);
signal potgo_write : std_logic;
signal pot_reset_next : std_logic;
signal pot_reset_reg : std_logic;
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
audf0_reg <= X"00";
audc0_reg <= X"00";
audf1_reg <= X"00";
audc1_reg <= X"00";
audf2_reg <= X"00";
audc2_reg <= X"00";
audf3_reg <= X"00";
audc3_reg <= X"00";
audctl_reg <= X"00";
irqen_reg <= X"00";
irqst_reg <= X"FF";
irq_n_reg <= '1';
skctl_reg <= X"00";
highpass0_reg <= '0';
highpass1_reg <= '0';
chan0_output_reg <= '0';
chan1_output_reg <= '0';
chan2_output_reg <= '0';
chan3_output_reg <= '0';
volume_channel_0_reg <= (others=>'0');
volume_channel_1_reg <= (others=>'0');
volume_channel_2_reg <= (others=>'0');
volume_channel_3_reg <= (others=>'0');
serin_reg <= (others=>'0');
serin_shift_reg <= (others=>'0');
serin_bitcount_reg <= (others=>'0');
serout_shift_reg <= (others=>'0');
serout_holding_reg <= (others=>'0');
serout_holding_full_reg <= '0';
serout_active_reg <= '0';
sio_out_reg <= '1';
serial_out_reg <= '1';
serial_ip_framing_reg <= '0';
serial_ip_overrun_reg <= '0';
clock_reg <= '0';
clock_sync_reg <= '0';
keyboard_overrun_reg <= '0';
serin_clock_reg <= '0';
serin_clock_last_reg <= '0';
serout_clock_reg <= '0';
serout_clock_last_reg <= '0';
twotone_reg <= '0';
sio_in_reg <= '0';
pot0_reg <= (others=>'0');
pot1_reg <= (others=>'0');
pot2_reg <= (others=>'0');
pot3_reg <= (others=>'0');
pot4_reg <= (others=>'0');
pot5_reg <= (others=>'0');
pot6_reg <= (others=>'0');
pot7_reg <= (others=>'0');
pot_counter_reg <= (others=>'0');
pot_reset_reg <= '1';
elsif (clk'event and clk='1') then
audf0_reg <= audf0_next;
audc0_reg <= audc0_next;
audf1_reg <= audf1_next;
audc1_reg <= audc1_next;
audf2_reg <= audf2_next;
audc2_reg <= audc2_next;
audf3_reg <= audf3_next;
audc3_reg <= audc3_next;
audctl_reg <= audctl_next;
irqen_reg <= irqen_next;
irqst_reg <= irqst_next;
irq_n_reg <= irq_n_next;
skctl_reg <= skctl_next;
highpass0_reg <= highpass0_next;
highpass1_reg <= highpass1_next;
chan0_output_reg <= chan0_output_next;
chan1_output_reg <= chan1_output_next;
chan2_output_reg <= chan2_output_next;
chan3_output_reg <= chan3_output_next;
volume_channel_0_reg<= volume_channel_0_next;
volume_channel_1_reg<= volume_channel_1_next;
volume_channel_2_reg<= volume_channel_2_next;
volume_channel_3_reg<= volume_channel_3_next;
serin_reg <= serin_next;
serin_shift_reg <= serin_shift_next;
serin_bitcount_reg <= serin_bitcount_next;
serout_shift_reg <= serout_shift_next;
serout_bitcount_reg <= serout_bitcount_next;
serout_holding_reg<=serout_holding_next;
serout_holding_full_reg<=serout_holding_full_next;
serout_active_reg <= serout_active_next;
sio_out_reg <= sio_out_next;
serial_out_reg <= serial_out_next;
serial_ip_framing_reg <= serial_ip_framing_next;
serial_ip_overrun_reg <= serial_ip_overrun_next;
clock_reg <= clock_next;
clock_sync_reg <= clock_sync_next;
keyboard_overrun_reg <= keyboard_overrun_next;
serin_clock_reg <= serin_clock_next;
serin_clock_last_reg <= serin_clock_last_next;
serout_clock_reg <= serout_clock_next;
serout_clock_last_reg <= serout_clock_last_next;
twotone_reg <= twotone_next;
sio_in_reg <= sio_in_next;
pot0_reg <= pot0_next;
pot1_reg <= pot1_next;
pot2_reg <= pot2_next;
pot3_reg <= pot3_next;
pot4_reg <= pot4_next;
pot5_reg <= pot5_next;
pot6_reg <= pot6_next;
pot7_reg <= pot7_next;
pot_counter_reg <= pot_counter_next;
pot_reset_reg <= pot_reset_next;
end if;
end process;
-- decode address
decode_addr1 : complete_address_decoder
generic map(width=>4)
port map (addr_in=>addr, addr_decoded=>addr_decoded);
-- clock selection
process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
begin
audf0_enable <= enable_64;
audf1_enable <= enable_64;
audf2_enable <= enable_64;
audf3_enable <= enable_64;
if (audctl_reg(0) = '1') then
audf0_enable <= enable_15;
audf1_enable <= enable_15;
audf2_enable <= enable_15;
audf3_enable <= enable_15;
end if;
if (audctl_reg(6) = '1') then
audf0_enable <= enable_179;
end if;
if (audctl_reg(5) = '1') then
audf2_enable <= enable_179;
end if;
if(audctl_reg(4) = '1') then
audf1_enable <= audf0_pulse;
end if;
if(audctl_reg(3) = '1') then
audf3_enable <= audf2_pulse;
end if;
end process;
-- Instantiate timers
timer0 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
timer1 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
timer2 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
timer3 : pokey_countdown_timer
generic map (UNDERFLOW_DELAY=>3)
port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);
-- Timer reloading
process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
begin
audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
end process;
-- Writes to registers
process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
begin
audf0_next <= audf0_reg;
audc0_next <= audc0_reg;
audf1_next <= audf1_reg;
audc1_next <= audc1_reg;
audf2_next <= audf2_reg;
audc2_next <= audc2_reg;
audf3_next <= audf3_reg;
audc3_next <= audc3_reg;
audctl_next <= audctl_reg;
irqen_next <= irqen_reg;
skctl_next <= skctl_reg;
stimer_write <= '0';
serout_holding_load <= '0';
serout_holding_next <= serout_holding_reg;
serial_reset <= '0';
skrest_write <= '0';
potgo_write <= '0';
if (wr_en = '1') then
if(addr_decoded(0) = '1') then
audf0_next <= data_in;
end if;
if(addr_decoded(1) = '1') then
audc0_next <= data_in;
end if;
if(addr_decoded(2) = '1') then
audf1_next <= data_in;
end if;
if(addr_decoded(3) = '1') then
audc1_next <= data_in;
end if;
if(addr_decoded(4) = '1') then
audf2_next <= data_in;
end if;
if(addr_decoded(5) = '1') then
audc2_next <= data_in;
end if;
if(addr_decoded(6) = '1') then
audf3_next <= data_in;
end if;
if(addr_decoded(7) = '1') then
audc3_next <= data_in;
end if;
if(addr_decoded(8) = '1') then
audctl_next <= data_in;
end if;
if (addr_decoded(9) = '1') then --STIMER
stimer_write <= '1';
end if;
if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
skrest_write <= '1';
end if;
if (addr_decoded(11) = '1') then -- POTGO - start POT scan
potgo_write <= '1';
end if;
if (addr_decoded(13) = '1') then --SEROUT
serout_holding_next <= data_in;
serout_holding_load <= '1';
end if;
if (addr_decoded(14) = '1') then --IRQEN
irqen_next <= data_in;
end if;
if (addr_decoded(15) = '1') then --SKCTL
skctl_next <= data_in;
if (data_in(6 downto 4)="000") then
serial_reset <= '1';
end if;
end if;
end if;
end process;
-- Read from registers
process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
begin
data_out <= X"FF";
if(addr_decoded(0) = '1') then --POT0
data_out <= pot0_reg;
end if;
if(addr_decoded(1) = '1') then --POT1
data_out <= pot1_reg;
end if;
if(addr_decoded(2) = '1') then --POT2
data_out <= pot2_reg;
end if;
if(addr_decoded(3) = '1') then --POT3
data_out <= pot3_reg;
end if;
if(addr_decoded(4) = '1') then --POT4
data_out <= pot4_reg;
end if;
if(addr_decoded(5) = '1') then --POT5
data_out <= pot5_reg;
end if;
if(addr_decoded(6) = '1') then --POT6
data_out <= pot6_reg;
end if;
if(addr_decoded(7) = '1') then --POT7
data_out <= pot7_reg;
end if;
if(addr_decoded(8) = '1') then --ALLPOT
data_out <= not(pot_in);
end if;
if(addr_decoded(9) = '1') then --KBCODE
data_out <= control_pressed&shift_pressed&kbcode;
end if;
if(addr_decoded(10) = '1') then -- RANDOM
data_out <= RAND_OUT;
end if;
if (addr_decoded(13) = '1') then --SERIN
data_out <= serin_reg;
end if;
if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
data_out <= IRQST_REG;
--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
end if;
if (addr_decoded(15) = '1') then --SKSTAT
data_out <= not(serial_ip_framing_reg)¬(keyboard_overrun_reg)¬(serial_ip_overrun_reg)&sio_in_reg¬(SHIFT_PRESSED)¬(KEY_HELD)&waiting_for_start_bit&"1";
end if;
end process;
-- Fire interrupts
process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
begin
-- clear interrupts
irqst_next <= irqst_reg or not(irqen_reg);
irq_n_next <= '0';
if ((irqst_reg or "0000"¬(irqen_reg(3))&"000") = X"FF") then
irq_n_next <= '1';
end if;
-- set interrupts
if (audf0_pulse = '1') then
irqst_next(0) <= not(irqen_reg(0));
end if;
if (audf1_pulse = '1') then
irqst_next(1) <= not(irqen_reg(1));
end if;
if (audf3_pulse = '1') then
irqst_next(2) <= not(irqen_reg(2));
end if;
if (other_key_irq = '1') then
irqst_next(6) <= not(irqen_reg(6));
end if;
if (break_pressed = '1') then
irqst_next(7) <= not(irqen_reg(7));
end if;
if (serial_ip_ready_interrupt = '1') then
irqst_next(5) <= not(irqen_reg(5));
end if;
irqst_next(3) <= serout_active_reg;
if (serial_op_needed_interrupt = '1') then
irqst_next(4) <= not(irqen_reg(4));
end if;
end process;
-- Instantiate delay for stimer reload_request
stimer_delay : delay_line
generic map (count=>3)
port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
--stimer_write_delayed <= stimer_write;
-- Instantiate audio noise filters
pokey_noise_filter0 : pokey_noise_filter
port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter1 : pokey_noise_filter
port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter2 : pokey_noise_filter
port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
pokey_noise_filter3 : pokey_noise_filter
port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
-- Audio output stage
process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
begin
chan0_output_next <= chan0_output_reg;
chan1_output_next <= chan1_output_reg;
chan2_output_next <= chan2_output_reg;
chan3_output_next <= chan3_output_reg;
if (audf0_pulse_noise = '1') then
chan0_output_next <= not(chan0_output_reg);
end if;
if (audf1_pulse_noise = '1') then
chan1_output_next <= not(chan1_output_reg);
end if;
if (audf2_pulse_noise = '1') then
chan2_output_next <= not(chan2_output_reg);
end if;
if (audf3_pulse_noise = '1') then
chan3_output_next <= not(chan3_output_reg);
end if;
end process;
-- High pass filters
process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
begin
highpass0_next <= highpass0_reg;
highpass1_next <= highpass1_reg;
if (audctl_reg(2) = '1') then
if (audf2_pulse = '1') then
highpass0_next <= chan0_output_reg;
end if;
else
highpass0_next <= '1';
end if;
if (audctl_reg(1) = '1') then
if (audf3_pulse = '1') then
highpass1_next <= chan1_output_reg;
end if;
else
highpass1_next <= '1';
end if;
end process;
-- Instantiate key pokey clocks
-- ~1.79MHz - from 25MHz/14
-- ~64KHz - from 1.79MHz/28
-- ~15KHz - from 1.79MHz/114
--enable_179_div : enable_divider
-- generic map (COUNT=>14)
-- port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
-- resetcount 6/33
enable_64_div : syncreset_enable_divider
generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
enable_15_div : syncreset_enable_divider
generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
-- Instantiate pokey noise circuits (lfsr)
initmode <= skctl_next(1) nor skctl_next(0);
poly_17_19_lfsr : pokey_poly_17_9
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
poly_5_lfsr : pokey_poly_5
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
poly_4_lfsr : pokey_poly_4
port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
begin
volume_channel_0_next <= "0000";
volume_channel_1_next <= "0000";
volume_channel_2_next <= "0000";
volume_channel_3_next <= "0000";
if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
volume_channel_0_next <= audc0_reg(3 downto 0);
end if;
if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
volume_channel_1_next <= audc1_reg(3 downto 0);
end if;
if ((chan2_output_reg or audc2_reg(4)) = '1') then
volume_channel_2_next <= audc2_reg(3 downto 0);
end if;
if ((chan3_output_reg or audc3_reg(4)) = '1') then
volume_channel_3_next <= audc3_reg(3 downto 0);
end if;
end process;
-- serial port output
-- urghhh
serout_sync_reset <= serial_reset or stimer_write_delayed;
serout_clock_delay : delay_line
generic map (count=>2)
port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
begin
serout_clock_next <= serout_clock_reg;
serout_clock_last_next <= serout_clock_reg;
serout_shift_next <= serout_shift_reg;
serout_bitcount_next <= serout_bitcount_reg;
serout_holding_full_next <= serout_holding_full_reg;
serout_active_next <= serout_active_reg;
serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
sio_out_next <= serial_out_reg;
-- two tone output
twotone_next <= twotone_reg;
twotone_reset <= '0';
if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
twotone_next <= not(twotone_reg);
twotone_reset <= skctl_reg(3);
end if;
if (skctl_reg(3) = '1') then
sio_out_next <= twotone_reg;
end if;
-- force break
if (skctl_reg(7) = '1') then
sio_out_next <= '0';
end if;
serial_op_needed_interrupt <= '0';
-- generate clock from enable signals
if (serout_enable_delayed = '1') then
serout_clock_next <= not(serout_clock_reg);
end if;
-- output bits over sio
if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then
serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
-- reload
if (serout_bitcount_reg = X"0") then
if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
serout_shift_next <= '1'&serout_holding_reg&'0';
serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
serout_holding_full_next <= '0';
serial_op_needed_interrupt <= '1'; -- more data please!
serout_active_next <= '1';
else
serout_active_next <= '0';
serial_out_next <= '1'; -- remove blip!
end if;
else
serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
end if;
end if;
-- register to load has been written too, update our state to reflect that it is full
if (serout_holding_load = '1') then
serout_holding_full_next <= '1';
end if;
if (serial_reset = '1') then
twotone_next <= '0';
serout_bitcount_next <= (others=>'0');
serout_shift_next <= (others=>'0');
serout_holding_full_next <= '0';
serout_clock_next <= '0';
serout_clock_last_next <= '0';
serout_active_next <= '0';
end if;
end process;
-- serial port input
sio_in1_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);
sio_in2_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);
sio_in3_synchronizer : synchronizer
port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);
sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
begin
serin_clock_next <= serin_clock_reg;
serin_clock_last_next <= serin_clock_reg;
serin_shift_next <= serin_shift_reg;
serin_bitcount_next <= serin_bitcount_reg;
serin_next <= serin_reg;
serial_ip_overrun_next <= serial_ip_overrun_reg;
serial_ip_framing_next <= serial_ip_framing_reg;
serial_ip_ready_interrupt <= '0';
async_serial_reset <= '0';
-- generate clock from enable signals
if (serin_enable = '1') then
serin_clock_next <= not(serin_clock_reg);
end if;
-- resync clock on receipt of start bit
if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
async_serial_reset <= '1';
serin_clock_next <= '1';
end if;
-- receive bits into shift reg
if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge
if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then
serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
if (serin_bitcount_reg = X"0") then -- full byte
serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
-- irq to alert new data avilable
serial_ip_ready_interrupt <= '1';
-- flag up overrun
if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
serial_ip_overrun_next <= '1';
end if;
-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
if (sio_in_reg='0') then
serial_ip_framing_next <= '1';
end if;
else
serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
end if;
end if;
end if;
if (skrest_write = '1') then
serial_ip_overrun_next <= '0';
serial_ip_framing_next <= '0';
end if;
if (serial_reset = '1') then
serin_clock_next <= '0';
serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
serin_shift_next <= (others=>'0');
end if;
end process;
-- serial clocks
process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
begin
clock_next <= sio_clock;
clock_sync_next <= clock_reg;
serout_enable <= '0';
serin_enable <= '0';
clock_input <= '1'; -- when output, outputs channel 4
case skctl_reg(6 downto 4) is
when "000" =>
serin_enable <= not(clock_sync_reg) and clock_reg;
serout_enable <= not(clock_sync_reg) and clock_reg;
when "001" =>
serin_enable <= audf3_pulse;
serout_enable <= not(clock_sync_reg) and clock_reg;
when "010" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
clock_input <= '0';
when "011" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
when "100" =>
serin_enable <= not(clock_sync_reg) and clock_reg;
serout_enable <= audf3_pulse;
when "101" =>
serin_enable <= audf3_pulse;
serout_enable <= audf3_pulse;
when "110" =>
serin_enable <= audf3_pulse;
serout_enable <= audf1_pulse;
clock_input <= '0';
when "111" =>
serin_enable <= audf3_pulse;
serout_enable <= audf1_pulse;
when others =>
-- nop
end case;
end process;
-- keyboard overrun (i.e. second key pressed before interrupt cleared)
process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
begin
keyboard_overrun_next <= keyboard_overrun_reg;
if (other_key_irq='1' and irqst_reg(6)='0') then
keyboard_overrun_next <= '1';
end if;
if (skrest_write = '1') then
keyboard_overrun_next <= '0';
end if;
end process;
-- keyboard scan
pokey_keyboard_scanner1 : pokey_keyboard_scanner
port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);
-- POT scan
process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
begin
pot0_next <= pot0_reg;
pot1_next <= pot1_reg;
pot2_next <= pot2_reg;
pot3_next <= pot3_reg;
pot4_next <= pot4_reg;
pot5_next <= pot5_reg;
pot6_next <= pot6_reg;
pot7_next <= pot7_reg;
pot_reset_next <= pot_reset_reg;
pot_counter_next <= pot_counter_reg;
if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
if (pot_counter_reg = X"E4") then
pot_reset_next <= '1'; -- turn on pot dump transistors
end if;
if (pot_reset_reg = '0') then
if (pot_in(0) = '0') then -- pot now high, latch
pot0_next <= pot_counter_reg;
end if;
if (pot_in(1) = '0') then -- pot now high, latch
pot1_next <= pot_counter_reg;
end if;
if (pot_in(2) = '0') then -- pot now high, latch
pot2_next <= pot_counter_reg;
end if;
if (pot_in(3) = '0') then -- pot now high, latch
pot3_next <= pot_counter_reg;
end if;
if (pot_in(4) = '0') then -- pot now high, latch
pot4_next <= pot_counter_reg;
end if;
if (pot_in(5) = '0') then -- pot now high, latch
pot5_next <= pot_counter_reg;
end if;
if (pot_in(6) = '0') then -- pot now high, latch
pot6_next <= pot_counter_reg;
end if;
if (pot_in(7) = '0') then -- pot now high, latch
pot7_next <= pot_counter_reg;
end if;
end if;
end if;
if (potgo_write = '1') then
pot_counter_next <= (others=>'0');
pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
end if;
end process;
-- Outputs
irq_n_out <= irq_n_reg;
CHANNEL_0_OUT <= volume_channel_0_reg;
CHANNEL_1_OUT <= volume_channel_1_reg;
CHANNEL_2_OUT <= volume_channel_2_reg;
CHANNEL_3_OUT <= volume_channel_3_reg;
sio_out1 <= sio_out_reg;
sio_out2 <= sio_out_reg;
sio_out3 <= sio_out_reg;
sio_clock <= audf3_pulse when clock_input='0' else 'Z';
pot_reset <= pot_reset_reg;
END vhdl;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/antic_counter.vhdl
|
1
|
1698
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
ENTITY antic_counter IS
generic
(
STORE_WIDTH : natural := 1;
COUNT_WIDTH : natural := 1
);
PORT
(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
increment : in std_logic;
load : IN STD_LOGIC;
load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
);
END antic_counter;
ARCHITECTURE vhdl OF antic_counter IS
signal value_next : std_logic_vector(STORE_WIDTH-1 downto 0);
signal value_reg : std_logic_vector(STORE_WIDTH-1 downto 0);
BEGIN
-- register
process(clk,reset_n)
begin
if (reset_n = '0') then
value_reg <= (others=>'0');
elsif (clk'event and clk='1') then
value_reg <= value_next;
end if;
end process;
-- next state
process(increment, value_reg, load, load_value)
begin
value_next <= value_reg;
if (increment = '1') then
value_next <= value_reg(STORE_WIDTH-1 downto COUNT_WIDTH)&std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
end if;
if (load = '1') then
value_next <= load_value;
end if;
end process;
-- output
current_value <= value_reg;
END vhdl;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/components/synchronizer.vhdl
|
1
|
946
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY synchronizer IS
PORT
(
CLK : IN STD_LOGIC;
RAW : IN STD_LOGIC;
SYNC : OUT STD_LOGIC
);
END synchronizer;
ARCHITECTURE vhdl OF synchronizer IS
signal ff_next : std_logic_vector(2 downto 0);
signal ff_reg : std_logic_vector(2 downto 0);
begin
-- register
process(clk)
begin
if (clk'event and clk='1') then
ff_reg <= ff_next;
end if;
end process;
ff_next <= RAW&ff_reg(2 downto 1);
SYNC <= ff_reg(0);
end vhdl;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/cham_rom/cham_rom/simulation/random.vhd
|
101
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/zpu/zpu_glue.vhdl
|
1
|
14150
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_MISC.all;
library work;
use work.zpupkg.all;
ENTITY zpu_glue IS
PORT
(
CLK : in std_logic;
RESET : in std_logic;
PAUSE : in std_logic;
ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack
ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
ZPU_DO : out std_logic_vector(31 downto 0);
ZPU_ADDR_ROM_RAM : out std_logic_vector(15 downto 0); -- direct from zpu, for short paths
ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
-- request
MEMORY_FETCH : out std_logic;
ZPU_READ_ENABLE : out std_logic;
ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
-- config
ZPU_CONFIG_WRITE : out std_logic;
-- stack request
ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
-- write to ROM!!
ZPU_ROM_WREN : out std_logic;
-- response
MEMORY_READY : in std_logic
);
END zpu_glue;
architecture sticky of zpu_glue is
component ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=24; -- Total address space width (incl. I/O)
MEM_W : integer:=16; -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable (32-bit)
read_en_o : out std_logic; -- Memory read enable (32-bit)
byte_read_o : out std_logic;
byte_write_o : out std_logic;
short_write_o: out std_logic); -- never happens
end component;
signal zpu_addr_unsigned : unsigned(23 downto 0);
signal zpu_do_unsigned : unsigned(31 downto 0);
signal ZPU_DI_unsigned : unsigned(31 downto 0);
signal zpu_break : std_logic;
signal zpu_debug : zpu_dbgo_t;
signal zpu_mem_busy : std_logic;
signal zpu_memory_fetch_pending_next : std_logic;
signal zpu_memory_fetch_pending_reg : std_logic;
signal ZPU_32bit_READ_ENABLE_temp : std_logic;
signal ZPU_8bit_READ_ENABLE_temp : std_logic;
signal ZPU_READ_temp : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_WRITE_temp : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_READ_next : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_READ_reg : std_logic;
signal block_mem : std_logic;
signal config_mem : std_logic;
signal special_mem : std_logic;
signal result_next : std_logic_vector(4 downto 0);
signal result_reg : std_logic_vector(4 downto 0);
constant result_external : std_logic_vector(4 downto 0) := "00000";
constant result_ram : std_logic_vector(4 downto 0) := "00001";
constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
constant result_rom : std_logic_vector(4 downto 0) := "00110";
constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";
constant result_config : std_logic_vector(4 downto 0) := "01011";
constant result_external_special : std_logic_vector(4 downto 0) := "01100";
signal request_type : std_logic_vector(4 downto 0);
signal zpu_di_use : std_logic_vector(31 downto 0);
signal memORY_ACCESS : std_logic;
-- 1 cycle delay on memory read - needed to allow running at higher clock
signal zpu_di_next : std_logic_vector(31 downto 0);
signal zpu_di_reg : std_logic_vector(31 downto 0);
signal memory_ready_next : std_logic;
signal memory_ready_reg : std_logic;
signal zpu_enable : std_logic;
signal zpu_addr_next : std_logic_vector(23 downto 0);
signal zpu_addr_reg : std_logic_vector(23 downto 0);
signal ZPU_DO_next : std_logic_vector(31 downto 0);
signal ZPU_DO_reg : std_logic_vector(31 downto 0);
begin
-- register
process(clk,reset)
begin
if (reset='1') then
zpu_memory_fetch_pending_reg <= '0';
result_reg <= result_rom;
zpu_di_reg <= (others=>'0');
zpu_do_reg <= (others=>'0');
memory_ready_reg <= '0';
zpu_addr_reg <= (others=>'0');
ZPU_32BIT_WRITE_ENABLE_reg <= '0';
ZPU_16BIT_WRITE_ENABLE_reg <= '0';
ZPU_8BIT_WRITE_ENABLE_reg <= '0';
ZPU_READ_reg <= '0';
elsif (clk'event and clk='1') then
zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
result_reg <= result_next;
zpu_di_reg <= zpu_di_next;
zpu_do_reg <= zpu_do_next;
memory_ready_reg <= memORY_READY_next;
zpu_addr_reg <=zpu_addr_next;
ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
ZPU_READ_reg <= ZPU_READ_next;
end if;
end process;
-- a little glue
process(zpu_ADDR_unsigned)
begin
block_mem <= '0';
config_mem <= '0';
special_mem <= '0';
-- $00000-$0FFFF = Own ROM/RAM
-- $10000-$1FFFF = Atari
-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
-- $40000-$4FFFF = Config area
if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
config_mem <= zpu_addr_unsigned(18);
special_mem <= zpu_addr_unsigned(17);
end if;
end process;
ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, special_mem, memORY_ACCESS,
zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
zpu_do_unsigned, zpu_do_reg
)
begin
zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
result_next <= result_reg;
memory_ready_next <= memory_ready;
zpu_stACK_WRITE <= (others=>'0');
ZPU_ROM_WREN <= '0';
ZPU_config_write <= '0';
zpu_addr_next <= zpu_addr_reg;
zpu_do_next <= zpu_do_reg;
ZPU_MEM_BUSY <= pause;
MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
if (memory_access = '1') then
zpu_do_next <= std_logic_vector(zpu_do_unsigned);
end if;
memory_fetch <= zpu_memory_fetch_pending_reg;
zpu_read_next <= zpu_read_reg;
zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;
request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
case request_type is
when "00010"|"00110" =>
zpu_memory_fetch_pending_next <= '1';
if (special_mem='0') then
result_next <= result_external;
else
result_next <= result_external_special;
end if;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
zpu_read_next <= zpu_read_temp;
zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;
when "01010" =>
if (zpu_8bit_read_enable_temp='1') then
case (zpu_addr_unsigned(1 downto 0)) is
when "00" =>
result_next <= result_rom_8bit_3;
when "01" =>
result_next <= result_rom_8bit_2;
when "10" =>
result_next <= result_rom_8bit_1;
when "11" =>
result_next <= result_rom_8bit_0;
when others =>
--nop
end case;
else
result_next <= result_rom;
end if;
ZPU_ROM_WREN <= ZPU_WRITE_TEMP;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "01110" =>
if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
case (zpu_addr_unsigned(1 downto 0)) is
when "00" =>
result_next <= result_ram_8bit_3;
ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
when "01" =>
result_next <= result_ram_8bit_2;
ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
when "10" =>
result_next <= result_ram_8bit_1;
ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;
when "11" =>
result_next <= result_ram_8bit_0;
ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
when others =>
--nop
end case;
else
result_next <= result_ram;
ZPU_STACK_WRITE <= (others=>zpu_write_temp);
end if;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "10110"|"10010" =>
result_next <= result_config;
ZPU_MEM_BUSY <= '1';
ZPU_config_write <= ZPU_WRITE_temp;
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
"10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111"|"00X01" =>
ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
zpu_memory_fetch_pending_next <= not(memORY_READY);
when others =>
-- nop
end case;
end process;
zpu_di_next <= zpu_di;
process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
begin
zpu_di_use <= (others=>'0');
case result_reg is
when result_external =>
zpu_di_use <= zpu_di_reg;
when result_external_special =>
zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);
when result_rom =>
zpu_di_use <= zpu_rom_DI;
when result_rom_8bit_0 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
when result_rom_8bit_1 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
when result_rom_8bit_2 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
when result_rom_8bit_3 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);
when result_ram =>
zpu_di_use <= zpu_ram_DI;
when result_ram_8bit_0 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
when result_ram_8bit_1 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
when result_ram_8bit_2 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
when result_ram_8bit_3 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);
when result_config =>
zpu_di_use <= zpu_config_di;
when others =>
-- nothing
end case;
end process;
-- zpu itself
--zpu_enable <= enable and not(pause);
zpu_enable <= '1'; -- does nothing useful...
myzpu: ZPUMediumCore
port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
zpu_di_unsigned <= unsigned(zpu_di_use);
zpu_do <= zpu_do_next;
ZPU_ADDR_ROM_RAM <= zpu_addr_next(15 downto 0);
ZPU_ADDR_FETCH <= zpu_addr_reg;
zpu_read_enable <= zpu_read_reg;
zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
end sticky;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/components/generic_ram_infer.vhdl
|
1
|
1827
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
ENTITY generic_ram_infer IS
generic
(
ADDRESS_WIDTH : natural := 9;
SPACE : natural := 512;
DATA_WIDTH : natural := 8
);
PORT
(
clock: IN std_logic;
data: IN std_logic_vector (data_width-1 DOWNTO 0);
address: IN std_logic_vector(address_width-1 downto 0);
we: IN std_logic;
q: OUT std_logic_vector (data_width-1 DOWNTO 0)
);
END generic_ram_infer;
ARCHITECTURE rtl OF generic_ram_infer IS
TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0);
SIGNAL ram_block : mem;
SIGNAL q_ram : std_logic_vector(data_width-1 downto 0);
SIGNAL we_ram : std_logic;
signal address2 : std_logic_vector(address_width-1 downto 0);
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we_ram = '1') THEN
ram_block(to_integer(to_01(unsigned(address2), '0'))) <= data;
q_ram <= data;
ELSE
q_ram <= ram_block(to_integer(to_01(unsigned(address2), '0')));
END IF;
END IF;
END PROCESS;
PROCESS(address, we, q_ram)
begin
q <= (others=>'1');
we_ram <= '0';
address2 <= (others=>'0');
IF (to_integer(to_01(unsigned(address))) < space) THEN
q <= q_ram;
we_ram <= we;
address2 <= address;
end if;
end process;
END rtl;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_STD
|
Extras/VHDL/STD_05700_good.vhd
|
1
|
3495
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_05700_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of gated clocks: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_05700_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_Data : in std_logic; -- Input data
o_Data : out std_logic; -- Output data
o_Gated_Clock : out std_logic -- Gated clock
);
end STD_05700_good;
architecture Behavioral of STD_05700_good is
signal Enable_r : std_logic;
signal Data_r : std_logic; -- Data signal registered
signal Data_r2 : std_logic; -- Data signal registered twice
begin
DFF_En : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_Enable,
o_Q => Enable_r,
o_Q_n => open
);
-- Make the Flip-Flop work when Enable signal is at 1
-- Enable signal on D Flip-flop
P_Sync_Data : process(i_Reset_n, i_Clock)
begin
if (i_Reset_n = '0') then
Data_r <= '0';
Data_r2 <= '0';
elsif (rising_edge(i_Clock)) then
if (Enable_r = '1') then
Data_r <= i_Data;
Data_r2 <= Data_r;
end if;
end if;
end process;
o_Data <= Data_r2;
end Behavioral;
--CODE
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/t80-latest/T80_Reg.vhd
|
1
|
3906
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/speccy/src/cpu/T80_RegX.vhd
|
8
|
5101
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/covox.vhd
|
1
|
2829
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY covox IS
PORT
(
CLK : IN STD_LOGIC;
ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR_EN : IN STD_LOGIC;
covox_channel0 : out std_logic_vector(7 downto 0);
covox_channel1 : out std_logic_vector(7 downto 0);
covox_channel2 : out std_logic_vector(7 downto 0);
covox_channel3 : out std_logic_vector(7 downto 0)
);
END covox;
ARCHITECTURE vhdl OF covox IS
component complete_address_decoder IS
generic (width : natural := 1);
PORT
(
addr_in : in std_logic_vector(width-1 downto 0);
addr_decoded : out std_logic_vector((2**width)-1 downto 0)
);
END component;
signal channel0_next : std_logic_vector(7 downto 0);
signal channel1_next : std_logic_vector(7 downto 0);
signal channel2_next : std_logic_vector(7 downto 0);
signal channel3_next : std_logic_vector(7 downto 0);
signal channel0_reg : std_logic_vector(7 downto 0);
signal channel1_reg : std_logic_vector(7 downto 0);
signal channel2_reg : std_logic_vector(7 downto 0);
signal channel3_reg : std_logic_vector(7 downto 0);
signal addr_decoded : std_logic_vector(3 downto 0);
BEGIN
complete_address_decoder1 : complete_address_decoder
generic map (width => 2)
port map (addr_in => addr, addr_decoded => addr_decoded);
-- next state logic
process(channel0_reg,channel1_reg,channel2_reg,channel3_reg,addr_decoded,data_in,WR_EN)
begin
channel0_next <= channel0_reg;
channel1_next <= channel1_reg;
channel2_next <= channel2_reg;
channel3_next <= channel3_reg;
if (WR_EN = '1') then
if (addr_decoded(0) = '1') then
channel0_next <= data_in;
end if;
if (addr_decoded(1) = '1') then
channel1_next <= data_in;
end if;
if (addr_decoded(2) = '1') then
channel2_next <= data_in;
end if;
if (addr_decoded(3) = '1') then
channel3_next <= data_in;
end if;
end if;
end process;
-- register
process(clk)
begin
if (clk'event and clk='1') then
channel0_reg <= channel0_next;
channel1_reg <= channel1_next;
channel2_reg <= channel2_next;
channel3_reg <= channel3_next;
end if;
end process;
-- output
covox_channel0 <= channel0_reg;
covox_channel1 <= channel1_reg;
covox_channel2 <= channel2_reg;
covox_channel3 <= channel3_reg;
END vhdl;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_STD
|
Extras/VHDL/STD_03200_good.vhd
|
1
|
2741
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-03 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03200_good.vhd
-- File Creation date : 2015-04-03
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unused output ports components management: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.pkg_HBK.all;
entity STD_03200_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03200_good;
--CODE
architecture Behavioral of STD_03200_good is
begin
FlipFlop : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_D,
o_Q => o_Q,
o_Q_n => open
);
end Behavioral;
--CODE
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/shared_enable.vhdl
|
1
|
4664
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.math_real.ceil;
USE ieee.math_real.log2;
-- TODO - review this whole scheme
-- Massively overcomplex and turbo doesn't even work with it right now!
ENTITY shared_enable IS
GENERIC
(
cycle_length : integer := 16 -- or 32...
);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ANTIC_REFRESH : IN STD_LOGIC;
MEMORY_READY_CPU : IN STD_LOGIC; -- during memory wait states keep CPU awake
MEMORY_READY_ANTIC : IN STD_LOGIC; -- during memory wait states keep CPU awake
PAUSE_6502 : in std_logic;
THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
ANTIC_ENABLE_179 : OUT STD_LOGIC; -- always about 1.79MHz to keep sound the same - 1 cycle early
oldcpu_enable : OUT STD_LOGIC; -- always about 1.79MHz to keep sound the same - 1 cycle only, when memory is ready...
CPU_ENABLE_OUT : OUT STD_LOGIC -- for compatibility run at 1.79MHz, for speed run as fast as we can
-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by cycle_length-1 cycles vs CPU_ENABLE (when in 1.79MHz mode)
);
END shared_enable;
ARCHITECTURE vhdl OF shared_enable IS
component enable_divider IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
ENABLE_IN : IN STD_LOGIC;
ENABLE_OUT : OUT STD_LOGIC
);
END component;
component delay_line IS
generic(COUNT : natural := 1);
PORT
(
CLK : IN STD_LOGIC;
SYNC_RESET : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC
);
END component;
signal enable_179 : std_logic;
signal enable_179_early : std_logic;
signal cpu_enable : std_logic;
signal cpu_extra_enable_next : std_logic;
signal cpu_extra_enable_reg : std_logic;
signal speed_shift_next : std_logic_vector(cycle_length-1 downto 0);
signal speed_shift_reg : std_logic_vector(cycle_length-1 downto 0);
-- TODO - clean up
signal oldcpu_pending_next : std_logic;
signal oldcpu_pending_reg : std_logic;
signal oldcpu_go : std_logic;
signal memory_ready : std_logic;
constant cycle_length_bits: integer := integer(ceil(log2(real(cycle_length))));
begin
-- instantiate some clock calcs
enable_179_clock_div : enable_divider
generic map (COUNT=>cycle_length)
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
process(THROTTLE_COUNT_6502, speed_shift_reg, enable_179)
variable speed_shift : std_logic;
variable speed_shift_temp : std_logic_vector(cycle_length-1 downto 0);
begin
if (enable_179 = '1') then -- synchronize
speed_shift_temp(cycle_length-1 downto 1) := (others=>'0');
speed_shift_temp(0) := '1';
else
speed_shift_temp := speed_shift_reg;
end if;
speed_shift_next(cycle_length-1 downto 1) <= speed_shift_temp(cycle_length-2 downto 0);
speed_shift := '0';
for i in 0 to cycle_length_bits loop
speed_shift := speed_shift or (speed_shift_temp(cycle_length/(2**i)-1) and throttle_count_6502(i));
end loop;
speed_shift_next(0) <= speed_shift;
end process;
delay_line_phase : delay_line
generic map (COUNT=>cycle_length-1)
port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);
-- registers
process(clk,reset_n)
begin
if (reset_n = '0') then
cpu_extra_enable_reg <= '0';
oldcpu_pending_reg <= '0';
speed_shift_reg <= (others=>'0');
elsif (clk'event and clk='1') then
cpu_extra_enable_reg <= cpu_extra_enable_next;
oldcpu_pending_reg <= oldcpu_pending_next;
speed_shift_reg <= speed_shift_next;
end if;
end process;
-- next state
memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
cpu_enable <= (speed_shift_reg(0) or cpu_extra_enable_reg or enable_179) and not(pause_6502 or antic_refresh);
cpu_extra_enable_next <= cpu_enable and not(memory_ready);
oldcpu_pending_next <= (oldcpu_pending_reg or enable_179) and not(memory_ready or antic_refresh);
oldcpu_go <= (oldcpu_pending_reg or enable_179) and (memory_ready or antic_refresh);
-- output
oldcpu_enable <= oldcpu_go;
ANTIC_ENABLE_179 <= enable_179_early;
CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
end vhdl;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/atari_bak.vhd
|
1
|
11292
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ATARI is
port(
CLK_50 : in std_logic;
KB_CLK : in std_logic;
KB_DAT : in std_logic;
JOY_CLK : out std_logic;
JOY_LOAD : out std_logic;
JOY_DATA0 : in std_logic;
JOY_DATA1 : in std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end ATARI;
architecture RTL of ATARI is
-- System
signal CLK : std_logic;
signal PLL_LOCKED : std_logic;
signal RESET_N : std_logic;
-- Video
signal HSYNC : std_logic;
signal VSYNC : std_logic;
-- Audio
signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
-- Gamepads
signal GAMEPAD0 : std_logic_vector(7 downto 0);
signal GAMEPAD1 : std_logic_vector(7 downto 0);
signal JOY1_n : std_logic_vector(7 downto 0);
signal JOY2_n : std_logic_vector(7 downto 0);
-- Keyboard
signal KEYBOARD_SCAN : std_logic_vector(5 downto 0);
signal KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
signal CONSOL_START : std_logic;
signal CONSOL_SELECT : std_logic;
signal CONSOL_OPTION : std_logic;
signal FKEYS : std_logic_vector(11 downto 0);
-- PIA
signal CA2_OUT : std_logic;
signal CA2_DIR_OUT : std_logic;
signal CB2_OUT : std_logic;
signal CB2_DIR_OUT : std_logic;
signal CA2_IN : std_logic;
signal CB2_IN : std_logic;
signal PORTA_IN : std_logic_vector(7 downto 0);
signal PORTA_OUT : std_logic_vector(7 downto 0);
signal PORTA_DIR_OUT : std_logic_vector(7 downto 0);
signal PORTB_IN : std_logic_vector(7 downto 0);
signal PORTB_OUT : std_logic_vector(7 downto 0);
-- PBI
signal PBI_WRITE_DATA : std_logic_vector(31 downto 0);
signal PBI_WIDTH_32BIT_ACCESS : std_logic;
signal PBI_WIDTH_16BIT_ACCESS : std_logic;
signal PBI_WIDTH_8BIT_ACCESS : std_logic;
signal GTIA_TRIG : std_logic_vector(3 downto 0);
signal ANTIC_LIGHTPEN : std_logic;
-- INTERNAL ROM/RAM
signal RAM_ADDR : std_logic_vector(18 downto 0);
signal RAM_DO : std_logic_vector(15 downto 0);
signal RAM_REQUEST : std_logic;
signal RAM_REQUEST_COMPLETE : std_logic;
signal RAM_WRITE_ENABLE : std_logic;
signal ROM_ADDR : std_logic_vector(21 downto 0);
signal ROM_DO : std_logic_vector(7 downto 0);
signal ROM_REQUEST : std_logic;
signal ROM_REQUEST_COMPLETE : std_logic;
-- DMA/Virtual drive
signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
signal DMA_FETCH : std_logic;
signal DMA_32BIT_WRITE_ENABLE : std_logic;
signal DMA_16BIT_WRITE_ENABLE : std_logic;
signal DMA_8BIT_WRITE_ENABLE : std_logic;
signal DMA_READ_ENABLE : std_logic;
signal DMA_MEMORY_READY : std_logic;
signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
signal ZPU_ROM_DATA : std_logic_vector(31 downto 0);
signal ZPU_OUT1 : std_logic_vector(31 downto 0);
signal ZPU_OUT2 : std_logic_vector(31 downto 0);
signal ZPU_OUT3 : std_logic_vector(31 downto 0);
signal ZPU_OUT4 : std_logic_vector(31 downto 0);
signal ZPU_POKEY_ENABLE : std_logic;
signal ZPU_SIO_TXD : std_logic;
signal ZPU_SIO_RXD : std_logic;
signal ZPU_SIO_COMMAND : std_logic;
-- System control from ZPU
signal RAM_SELECT : std_logic_vector(2 downto 0);
signal ROM_SELECT : std_logic_vector(5 downto 0);
signal RESET_ATARI : std_logic;
signal PAUSE_ATARI : std_logic;
signal SPEED_6502 : std_logic_vector(5 downto 0);
begin
u_PLL : entity work.PLL
port map (
CLKIN => CLK_50,
CLKOUT => CLK,
LOCKED => PLL_LOCKED );
u_DAC_L : entity work.dac
port map (
clk_i => CLK,
res_n_i => RESET_N,
dac_i => AUDIO_L_PCM,
dac_o => SOUND_L );
u_DAC_R : entity work.dac
port map (
clk_i => CLK,
res_n_i => RESET_N,
dac_i => AUDIO_R_PCM,
dac_o => SOUND_R );
u_KEYBOARD : entity work.ps2_to_atari800
port map (
CLK => CLK,
RESET_N => RESET_N,
PS2_CLK => KB_CLK,
PS2_DAT => KB_DAT,
KEYBOARD_SCAN => KEYBOARD_SCAN,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
CONSOL_START => CONSOL_START,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_OPTION => CONSOL_OPTION,
FKEYS => FKEYS );
u_JOYSTICKS : entity work.nes_gamepad
port map(
CLK => CLK,
RESET => not RESET_N,
JOY_CLK => JOY_CLK,
JOY_LOAD => JOY_LOAD,
JOY_DATA0 => JOY_DATA0,
JOY_DATA1 => JOY_DATA1,
JOY0_BUTTONS => GAMEPAD0,
JOY1_BUTTONS => GAMEPAD1,
JOY0_CONNECTED => OPEN,
JOY1_CONNECTED => OPEN );
u_INTROMRAM : entity work.internalromram
generic map (
internal_rom => 1,
internal_ram => 16384 )
port map (
clock => CLK,
reset_n => RESET_N,
ROM_ADDR => ROM_ADDR,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
ROM_REQUEST => ROM_REQUEST,
ROM_DATA => ROM_DO,
RAM_ADDR => RAM_ADDR,
RAM_WR_ENABLE => RAM_WRITE_ENABLE,
RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_REQUEST => RAM_REQUEST,
RAM_DATA => RAM_DO(7 downto 0) );
u_ATARI800 : entity work.atari800core
generic map (
cycle_length => 16,
video_bits => 4 )
port map (
CLK => CLK,
RESET_N => RESET_N,
VIDEO_VS => VSYNC,
VIDEO_HS => HSYNC,
VIDEO_B => VGA_B,
VIDEO_G => VGA_G,
VIDEO_R => VGA_R,
AUDIO_L => AUDIO_L_PCM,
AUDIO_R => AUDIO_R_PCM,
CA1_IN => '1',
CB1_IN => '1',
CA2_IN => CA2_IN,
CA2_OUT => CA2_OUT,
CA2_DIR_OUT => CA2_DIR_OUT,
CB2_IN => CB2_IN,
CB2_OUT => CB2_OUT,
CB2_DIR_OUT => CB2_DIR_OUT,
PORTA_IN => PORTA_IN,
PORTA_DIR_OUT => PORTA_DIR_OUT,
PORTA_OUT => PORTA_OUT,
PORTB_IN => PORTB_IN,
PORTB_DIR_OUT => OPEN,
PORTB_OUT => PORTB_OUT,
KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
KEYBOARD_SCAN => KEYBOARD_SCAN,
POT_IN => "00000000",
POT_RESET => OPEN,
PBI_ADDR => OPEN,
PBI_WRITE_ENABLE => OPEN,
PBI_SNOOP_DATA => OPEN,
PBI_WRITE_DATA => PBI_WRITE_DATA,
PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
PBI_ROM_DO => "11111111",
PBI_REQUEST => OPEN,
PBI_REQUEST_COMPLETE => '1',
CART_RD4 => '0',
CART_RD5 => '0',
CART_S4_n => OPEN,
CART_S5_N => OPEN,
CART_CCTL_N => OPEN,
SIO_RXD => '0',
SIO_TXD => OPEN,
CONSOL_OPTION => CONSOL_OPTION,
CONSOL_SELECT => CONSOL_SELECT,
CONSOL_START => CONSOL_START,
GTIA_TRIG => GTIA_TRIG,
ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
SDRAM_REQUEST => OPEN,
SDRAM_REQUEST_COMPLETE => '1',
SDRAM_READ_ENABLE => OPEN,
SDRAM_WRITE_ENABLE => OPEN,
SDRAM_ADDR => OPEN,
SDRAM_DO => (others=>'1'),
ANTIC_REFRESH => OPEN,
RAM_ADDR => RAM_ADDR,
RAM_DO => RAM_DO,
RAM_REQUEST => RAM_REQUEST,
RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
ROM_ADDR => ROM_ADDR,
ROM_DO => ROM_DO,
ROM_REQUEST => ROM_REQUEST,
ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
DMA_FETCH => '0',
DMA_READ_ENABLE => '0',
DMA_32BIT_WRITE_ENABLE => '0',
DMA_16BIT_WRITE_ENABLE => '0',
DMA_8BIT_WRITE_ENABLE => '0',
DMA_ADDR => (others=>'1'),
DMA_WRITE_DATA => (others=>'1'),
MEMORY_READY_DMA => OPEN,
PBI_SNOOP_DATA => OPEN,
RAM_SELECT => "000",
ROM_SELECT => "000001",
CART_EMULATION_SELECT => "0000000",
CART_EMULATION_ACTIVATE => '0',
PAL => '1',
USE_SDRAM => '0',
ROM_IN_RAM => '0',
THROTTLE_COUNT_6502 => "000001",
HALT => '0' );
u_ZPU : entity work.zpucore
generic map (
platform => 1,
spi_clock_div => 1 ) -- 28MHz/2. Max for SD cards is 25MHz...
port map (
CLK => CLK,
RESET_N => RESET_N,
ZPU_ADDR_FETCH => dma_addr_fetch,
ZPU_DATA_OUT => dma_write_data,
ZPU_FETCH => dma_fetch,
ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
ZPU_READ_ENABLE => dma_read_enable,
ZPU_MEMORY_READY => dma_memory_ready,
ZPU_MEMORY_DATA => dma_memory_data,
ZPU_ADDR_ROM => zpu_addr_rom,
ZPU_ROM_DATA => zpu_rom_data,
ZPU_SD_DAT0 => SD_MISO,
ZPU_SD_CLK => SD_SCK,
ZPU_SD_CMD => SD_MOSI,
ZPU_SD_DAT3 => SD_CS,
ZPU_POKEY_ENABLE => zpu_pokey_enable,
ZPU_SIO_TXD => zpu_sio_txd,
ZPU_SIO_RXD => zpu_sio_rxd,
ZPU_SIO_COMMAND => zpu_sio_command,
ZPU_IN1 => X"00000"& FKEYS,
ZPU_IN2 => X"00000000",
ZPU_IN3 => X"00000000",
ZPU_IN4 => X"00000000",
ZPU_OUT1 => ZPU_OUT1,
ZPU_OUT2 => ZPU_OUT2,
ZPU_OUT3 => ZPU_OUT3,
ZPU_OUT4 => ZPU_OUT4 );
u_ZPUROM : entity work.zpu_rom
port map (
clock => clk,
address => zpu_addr_rom(13 downto 2),
q => zpu_rom_data );
u_ZPU_POKEY : entity work.enable_divider
generic map (
COUNT => 16)
port map(
clk => clk,
reset_n => reset_n,
enable_in => '1',
enable_out => zpu_pokey_enable );
RESET_N <= PLL_LOCKED;
VGA_HSYNC <= not(HSYNC or VSYNC);
VGA_VSYNC <= not(HSYNC or VSYNC);
CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
PORTB_IN <= PORTB_OUT;
PORTA_IN <= ((JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3)&JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
ANTIC_LIGHTPEN <= JOY2_n(7) and JOY1_n(7);
GTIA_TRIG <= "01"&JOY2_n(7)&JOY1_n(7);
JOY1_n <= not GAMEPAD0; -- FRLDU
JOY2_n <= not GAMEPAD1; -- FRLDU
PAUSE_ATARI <= ZPU_OUT1(0);
RESET_ATARI <= ZPU_OUT1(1);
SPEED_6502 <= ZPU_OUT1(7 downto 2);
RAM_SELECT <= ZPU_OUT1(10 downto 8);
ROM_SELECT <= ZPU_OUT1(16 downto 11);
end RTL;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/host/VGA Console/fontrom/fontrom/example_design/bmg_wrapper.vhd
|
1
|
9881
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : fontrom.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT fontrom_top IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : fontrom_top
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/alf/src/clock/clock.vhd
|
1
|
6674
|
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____56.000______0.000______50.0______557.143____150.000
-- CLK_OUT2____25.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic;
VGA_CLK : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 28,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK,
I => clkfx);
clkout2_buf : BUFG
port map
(O => VGA_CLK,
I => clkdv);
end xilinx;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_STD
|
Extras/VHDL/STD_03000_good.vhd
|
1
|
2944
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03000_good.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description: Handbook example: Comments for objects declaration statements: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03000_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Enable : in std_logic; -- Enable signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03000_good;
--CODE
architecture Behavioral of STD_03000_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
if (i_Enable = '1') then -- D Flip-Flop enabled
Q <= i_D;
end if;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/atari800xl/src/a8core/basic.vhdl
|
1
|
58074
|
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredoutput(template2)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity basic is
port(
clock:in std_logic;
address:in std_logic_vector(12 downto 0);
q:out std_logic_vector(7 downto 0)
);
end basic;
architecture syn of basic is
type rom_type is array(0 to 8191) of std_logic_vector(7 downto 0);
signal ROM:rom_type:=
(
X"a5",
X"ca",
X"d0",
X"04",
X"a5",
X"08",
X"d0",
X"45",
X"a2",
X"ff",
X"9a",
X"d8",
X"ae",
X"e7",
X"02",
X"ac",
X"e8",
X"02",
X"86",
X"80",
X"84",
X"81",
X"a9",
X"00",
X"85",
X"92",
X"85",
X"ca",
X"c8",
X"8a",
X"a2",
X"82",
X"95",
X"00",
X"e8",
X"94",
X"00",
X"e8",
X"e0",
X"92",
X"90",
X"f6",
X"a2",
X"86",
X"a0",
X"01",
X"20",
X"7a",
X"a8",
X"a2",
X"8c",
X"a0",
X"03",
X"20",
X"7a",
X"a8",
X"a9",
X"00",
X"a8",
X"91",
X"84",
X"91",
X"8a",
X"c8",
X"a9",
X"80",
X"91",
X"8a",
X"c8",
X"a9",
X"03",
X"91",
X"8a",
X"a9",
X"0a",
X"85",
X"c9",
X"20",
X"f1",
X"b8",
X"20",
X"45",
X"bd",
X"20",
X"5b",
X"bd",
X"a5",
X"92",
X"f0",
X"03",
X"20",
X"9d",
X"bd",
X"20",
X"62",
X"bd",
X"a5",
X"ca",
X"d0",
X"9c",
X"a2",
X"ff",
X"9a",
X"20",
X"51",
X"da",
X"a9",
X"5d",
X"85",
X"c2",
X"20",
X"ed",
X"bd",
X"20",
X"f2",
X"a9",
X"f0",
X"ea",
X"a9",
X"00",
X"85",
X"f2",
X"85",
X"9f",
X"85",
X"94",
X"85",
X"a6",
X"85",
X"b3",
X"85",
X"b0",
X"85",
X"b1",
X"a5",
X"84",
X"85",
X"ad",
X"a5",
X"85",
X"85",
X"ae",
X"20",
X"a1",
X"db",
X"20",
X"9a",
X"a1",
X"20",
X"c4",
X"a2",
X"a5",
X"d5",
X"10",
X"02",
X"85",
X"a6",
X"20",
X"a1",
X"db",
X"a4",
X"f2",
X"84",
X"a8",
X"b1",
X"f3",
X"c9",
X"9b",
X"d0",
X"07",
X"24",
X"a6",
X"30",
X"b2",
X"4c",
X"86",
X"a1",
X"a5",
X"94",
X"85",
X"a7",
X"20",
X"c4",
X"a2",
X"20",
X"a1",
X"db",
X"a9",
X"a4",
X"a0",
X"9f",
X"a2",
X"02",
X"20",
X"54",
X"a4",
X"86",
X"f2",
X"a5",
X"af",
X"20",
X"c4",
X"a2",
X"20",
X"a1",
X"db",
X"20",
X"be",
X"a1",
X"90",
X"35",
X"a4",
X"9f",
X"b1",
X"f3",
X"c9",
X"9b",
X"d0",
X"06",
X"c8",
X"91",
X"f3",
X"88",
X"a9",
X"20",
X"09",
X"80",
X"91",
X"f3",
X"a9",
X"40",
X"05",
X"a6",
X"85",
X"a6",
X"a4",
X"a8",
X"84",
X"f2",
X"a2",
X"03",
X"86",
X"a7",
X"e8",
X"86",
X"94",
X"a9",
X"37",
X"20",
X"c4",
X"a2",
X"a4",
X"f2",
X"b1",
X"f3",
X"e6",
X"f2",
X"c9",
X"9b",
X"d0",
X"f3",
X"20",
X"c4",
X"a2",
X"a5",
X"94",
X"a4",
X"a7",
X"91",
X"80",
X"a4",
X"f2",
X"88",
X"b1",
X"f3",
X"c9",
X"9b",
X"d0",
X"9a",
X"a0",
X"02",
X"a5",
X"94",
X"91",
X"80",
X"20",
X"a2",
X"a9",
X"a9",
X"00",
X"b0",
X"03",
X"20",
X"dc",
X"a9",
X"38",
X"e5",
X"94",
X"f0",
X"1e",
X"b0",
X"13",
X"49",
X"ff",
X"a8",
X"c8",
X"a2",
X"8a",
X"20",
X"7a",
X"a8",
X"a5",
X"97",
X"85",
X"8a",
X"a5",
X"98",
X"85",
X"8b",
X"d0",
X"09",
X"a8",
X"20",
X"d0",
X"a9",
X"a2",
X"8a",
X"20",
X"f8",
X"a8",
X"a4",
X"94",
X"88",
X"b1",
X"80",
X"91",
X"8a",
X"98",
X"d0",
X"f8",
X"24",
X"a6",
X"50",
X"29",
X"a5",
X"b1",
X"0a",
X"0a",
X"0a",
X"a2",
X"88",
X"20",
X"f7",
X"a8",
X"38",
X"a5",
X"84",
X"e5",
X"ad",
X"a8",
X"a5",
X"85",
X"e5",
X"ae",
X"a2",
X"84",
X"20",
X"fa",
X"a8",
X"24",
X"a6",
X"10",
X"06",
X"20",
X"aa",
X"b5",
X"4c",
X"60",
X"a0",
X"20",
X"8e",
X"b5",
X"4c",
X"60",
X"a0",
X"10",
X"fb",
X"4c",
X"5e",
X"a9",
X"20",
X"a2",
X"a9",
X"b0",
X"f3",
X"20",
X"dc",
X"a9",
X"a8",
X"20",
X"d0",
X"a9",
X"a2",
X"8a",
X"20",
X"f8",
X"a8",
X"4c",
X"60",
X"a0",
X"20",
X"00",
X"d8",
X"90",
X"08",
X"a9",
X"00",
X"85",
X"f2",
X"a0",
X"80",
X"30",
X"09",
X"20",
X"41",
X"ad",
X"a4",
X"d5",
X"30",
X"f1",
X"a5",
X"d4",
X"84",
X"a1",
X"85",
X"a0",
X"20",
X"c4",
X"a2",
X"a5",
X"a1",
X"85",
X"d5",
X"4c",
X"c4",
X"a2",
X"a0",
X"01",
X"b1",
X"95",
X"85",
X"9e",
X"8d",
X"83",
X"04",
X"88",
X"b1",
X"95",
X"85",
X"9d",
X"8d",
X"82",
X"04",
X"84",
X"a9",
X"a5",
X"94",
X"8d",
X"81",
X"04",
X"a5",
X"f2",
X"8d",
X"80",
X"04",
X"20",
X"93",
X"a2",
X"30",
X"16",
X"c9",
X"01",
X"90",
X"24",
X"d0",
X"06",
X"20",
X"08",
X"a2",
X"4c",
X"59",
X"a2",
X"c9",
X"05",
X"90",
X"55",
X"20",
X"9b",
X"a2",
X"4c",
X"59",
X"a2",
X"38",
X"e9",
X"c1",
X"b0",
X"02",
X"a2",
X"ff",
X"18",
X"65",
X"9d",
X"48",
X"8a",
X"65",
X"9e",
X"48",
X"4c",
X"1b",
X"a2",
X"20",
X"93",
X"a2",
X"48",
X"20",
X"93",
X"a2",
X"48",
X"90",
X"09",
X"68",
X"a8",
X"68",
X"aa",
X"98",
X"48",
X"8a",
X"48",
X"60",
X"a6",
X"a9",
X"e8",
X"e8",
X"e8",
X"e8",
X"f0",
X"1f",
X"86",
X"a9",
X"a5",
X"f2",
X"9d",
X"80",
X"04",
X"a5",
X"94",
X"9d",
X"81",
X"04",
X"a5",
X"9d",
X"9d",
X"82",
X"04",
X"a5",
X"9e",
X"9d",
X"83",
X"04",
X"68",
X"85",
X"9e",
X"68",
X"85",
X"9d",
X"4c",
X"db",
X"a1",
X"4c",
X"18",
X"b9",
X"a6",
X"a9",
X"f0",
X"d1",
X"bd",
X"82",
X"04",
X"85",
X"9d",
X"bd",
X"83",
X"04",
X"85",
X"9e",
X"ca",
X"ca",
X"ca",
X"ca",
X"86",
X"a9",
X"b0",
X"03",
X"4c",
X"db",
X"a1",
X"20",
X"93",
X"a2",
X"30",
X"fb",
X"c9",
X"02",
X"b0",
X"08",
X"20",
X"8c",
X"a2",
X"20",
X"8c",
X"a2",
X"d0",
X"ef",
X"c9",
X"03",
X"f0",
X"d2",
X"b0",
X"e9",
X"a5",
X"f2",
X"c5",
X"9f",
X"90",
X"02",
X"85",
X"9f",
X"a6",
X"a9",
X"bd",
X"80",
X"04",
X"85",
X"f2",
X"bd",
X"81",
X"04",
X"85",
X"94",
X"4c",
X"db",
X"a1",
X"e6",
X"9d",
X"d0",
X"02",
X"e6",
X"9e",
X"60",
X"20",
X"8c",
X"a2",
X"a2",
X"00",
X"a1",
X"9d",
X"60",
X"c9",
X"0f",
X"f0",
X"17",
X"b0",
X"40",
X"c9",
X"0d",
X"d0",
X"06",
X"20",
X"8c",
X"a2",
X"4c",
X"e4",
X"a2",
X"68",
X"68",
X"a9",
X"04",
X"48",
X"a9",
X"a6",
X"48",
X"4c",
X"1b",
X"a2",
X"20",
X"8c",
X"a2",
X"a0",
X"00",
X"b1",
X"9d",
X"a4",
X"94",
X"88",
X"91",
X"80",
X"18",
X"60",
X"a4",
X"94",
X"91",
X"80",
X"e6",
X"94",
X"d0",
X"f7",
X"4c",
X"18",
X"b9",
X"a2",
X"ff",
X"9a",
X"a5",
X"94",
X"a4",
X"a7",
X"91",
X"80",
X"4c",
X"b1",
X"a0",
X"a2",
X"ff",
X"9a",
X"4c",
X"fb",
X"a0",
X"20",
X"a1",
X"db",
X"a5",
X"f2",
X"c5",
X"b3",
X"f0",
X"15",
X"85",
X"b3",
X"a9",
X"a7",
X"a0",
X"de",
X"a2",
X"00",
X"20",
X"54",
X"a4",
X"b0",
X"23",
X"86",
X"b2",
X"a5",
X"af",
X"69",
X"10",
X"85",
X"b0",
X"a0",
X"00",
X"b1",
X"9d",
X"c5",
X"b0",
X"f0",
X"0a",
X"c9",
X"44",
X"d0",
X"13",
X"a5",
X"b0",
X"c9",
X"44",
X"90",
X"0d",
X"20",
X"c4",
X"a2",
X"a6",
X"b2",
X"86",
X"f2",
X"18",
X"60",
X"a9",
X"00",
X"85",
X"b0",
X"38",
X"60",
X"a9",
X"00",
X"f0",
X"02",
X"a9",
X"80",
X"85",
X"d2",
X"20",
X"a1",
X"db",
X"a5",
X"f2",
X"85",
X"ac",
X"20",
X"e8",
X"a3",
X"b0",
X"25",
X"20",
X"e1",
X"a2",
X"a5",
X"b0",
X"f0",
X"08",
X"a4",
X"b2",
X"b1",
X"f3",
X"c9",
X"30",
X"90",
X"16",
X"e6",
X"f2",
X"20",
X"e8",
X"a3",
X"90",
X"f9",
X"20",
X"af",
X"db",
X"90",
X"f4",
X"b1",
X"f3",
X"c9",
X"24",
X"f0",
X"06",
X"24",
X"d2",
X"10",
X"09",
X"38",
X"60",
X"24",
X"d2",
X"10",
X"fa",
X"c8",
X"d0",
X"0d",
X"b1",
X"f3",
X"c9",
X"28",
X"d0",
X"07",
X"c8",
X"a9",
X"40",
X"05",
X"d2",
X"85",
X"d2",
X"a5",
X"ac",
X"85",
X"f2",
X"84",
X"ac",
X"a5",
X"83",
X"a4",
X"82",
X"a2",
X"00",
X"20",
X"54",
X"a4",
X"b0",
X"0a",
X"e4",
X"ac",
X"f0",
X"4d",
X"20",
X"82",
X"a4",
X"4c",
X"7e",
X"a3",
X"38",
X"a5",
X"ac",
X"e5",
X"f2",
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X"ba",
X"20",
X"89",
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X"66",
X"da",
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X"10",
X"c6",
X"a2",
X"ec",
X"a0",
X"05",
X"20",
X"89",
X"dd",
X"a5",
X"f1",
X"f0",
X"23",
X"38",
X"e9",
X"40",
X"18",
X"6a",
X"18",
X"69",
X"40",
X"29",
X"7f",
X"85",
X"e0",
X"a5",
X"f1",
X"6a",
X"a9",
X"01",
X"90",
X"02",
X"a9",
X"10",
X"85",
X"e1",
X"a2",
X"04",
X"a9",
X"00",
X"95",
X"e2",
X"ca",
X"10",
X"fb",
X"20",
X"db",
X"da",
X"60",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"a0",
X"00",
X"05",
X"f0",
X"bf"
);
signal rdata:std_logic_vector(7 downto 0);
begin
rdata<=ROM(conv_integer(address));
process(clock)
begin
if(clock'event and clock='1')then
q<=rdata;
end if;
end process;
end syn;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/host/VGA Console/mips_vram/mips_vram/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
ILoveSpeccy/Aeon-Lite
|
cores/lvov-pk02-mips/src/cham_rom/cham_rom/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-3.0
|
peteut/nvc
|
test/lower/bounds1.vhd
|
4
|
413
|
entity bounds1 is
end entity;
architecture test of bounds1 is
type int_vec is array (natural range <>) of integer;
begin
process is
variable v : int_vec(0 to 9) := (others => 0);
variable k : integer range 0 to 9;
begin
assert v(k) = 1; -- Should elide
assert v(k + 1) = 1; -- Cannot elide
wait;
end process;
end architecture;
|
gpl-3.0
|
peteut/nvc
|
test/regress/textio2008.vhd
|
1
|
632
|
entity textio2008 is
end entity;
use std.textio.all;
architecture test of textio2008 is
begin
process is
file fptr : text;
variable l : line;
begin
file_open(fptr, "tmp.txt", WRITE_MODE);
write(l, string'("0123"));
tee(fptr, l);
write(l, string'("4567"));
tee(fptr, l);
assert l'length = 0;
file_close(fptr);
file_open(fptr, "tmp.txt", READ_MODE);
readline(fptr, l);
assert l.all = "0123";
readline(fptr, l);
assert l.all = "4567";
file_close(fptr);
wait;
end process;
end architecture;
|
gpl-3.0
|
peteut/nvc
|
test/elab/issue93.vhd
|
5
|
676
|
entity t is
generic(
ORDER : integer := 8
);
port(
clk : in bit;
reset : in bit
);
end entity t;
architecture RTL of t is
function calc_order(i:integer) return integer is
begin
if i mod 2 = 1 then
return i/2+1;
else
return i/2;
end if;
end function;
constant C_ORDER :integer:=calc_order(ORDER);
type t_48 is array (C_ORDER-1 downto 0) of bit_vector(47 downto 0);
signal a:t_48;
constant zero48 : bit_vector(47 downto 0):=(others=>'0');
begin
loop_gen: for i in 0 to C_ORDER-1 generate
a(i)<=zero48;
end generate;
end architecture RTL;
|
gpl-3.0
|
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